ATTINY15L-1SC [ATMEL]
8-bit AVR Microcontroller with 1K Byte Flash; 8位AVR微控制器1K字节的FLASH型号: | ATTINY15L-1SC |
厂家: | ATMEL |
描述: | 8-bit AVR Microcontroller with 1K Byte Flash |
文件: | 总11页 (文件大小:199K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• High-performance, Low-power AVR® 8-bit Microcontroller
• Advanced RISC Architecture
– 90 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• Nonvolatile Program and Data Memories
– 1K Byte In-System Programmable Flash Program Memory
Endurance: 1,000 Write/Erase Cycles
– 64 Bytes EEPROM
Endurance: 100,000 Write/Erase Cycles
– Programming Lock for Flash Program Data Security
• Peripheral Features
8-bit
Microcontroller
with 1K Byte
Flash
– Interrupt and Wake-up on Pin Change
– Two 8-bit Timer/Counters with Separate Prescalers
– One 150 kHz, 8-bit High-speed PWM Output
– 4-channel 10-bit ADC
One Differential Voltage Input with Optional Gain of 20x
– On-chip Analog Comparator
– Programmable Watchdog Timer with On-chip Oscillator
• Special Microcontroller Features
ATtiny15L
– In-System Programmable via SPI Port
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal, Calibrated 1.6 MHz Tunable Oscillator
– Internal 25.6 MHz Clock Generator for Timer/Counter
– External and Internal Interrupt Sources
– Low-power Idle and Power-down Modes
• Power Consumption at 1.6 MHz, 3V, 25°C
– Active: 3.0 mA
– Idle Mode: 1.0 mA
– Power-down: < 1 µA
• I/O and Packages
– 8-lead PDIP and 8-lead SOIC: 6 Programmable I/O Lines
• Operating Voltages
– 2.7V - 5.5V
• Internal 1.6 MHz System Clock
Pin Configuration
PDIP/SOIC
(RESET/ADC0) PB5
(ADC3) PB4
(ADC2) PB3
GND
1
2
3
4
8
7
6
5
VCC
PB2 (ADC1/SCK/T0/INT0)
PB1 (AIN1/MISO/OC1A)
PB0 (AIN0/AREF/MOSI)
Rev. 1187DS–12/01
Note: This is a summary document. A complete document is
available on our web site at www.atmel.com.
Description
The ATtiny15L is a low-power CMOS 8-bit microcontroller based on the AVR RISC
architecture. By executing powerful instructions in a single clock cycle, the ATtiny15L
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to
optimize power consumption versus processing speed.
The AVR core combines a rich instruction set with 32 general purpose working registers.
All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing
two independent registers to be accessed in one single instruction executed in one clock
cycle. The resulting architecture is more code efficient while achieving throughputs up to
ten times faster than conventional CISC microcontrollers.
The ATtiny15L provides 1K byte of Flash, 64 bytes EEPROM, six general purpose I/O
lines, 32 general purpose working registers, two 8-bit Timer/Counters, one with high-
speed PWM output, internal oscillators, internal and external interrupts, programmable
Watchdog Timer, 4-channel 10-bit Analog-to-Digital Converter with one differential volt-
age input with optional 20x gain, and three software-selectable Power-saving modes.
The Idle mode stops the CPU while allowing the ADC, analog comparator,
Timer/Counters and interrupt system to continue functioning. The ADC Noise Reduction
mode facilitates high-accuracy ADC measurements by stopping the CPU while allowing
the ADC to continue functioning. The Power-down mode saves the register contents but
freezes the oscillators, disabling all other chip functions until the next interrupt or hard-
ware reset. The wake-up or interrupt on pin change features enable the ATtiny15L to be
highly responsive to external events, still featuring the lowest power consumption while
in the Power-saving modes.
The device is manufactured using Atmel’s high-density, nonvolatile memory technology.
By combining a RISC 8-bit CPU with Flash on a monolithic chip, the ATtiny15L is a pow-
erful microcontroller that provides a highly flexible and cost-efficient solution to many
embedded control applications. The peripheral features make the ATtiny15L particularly
suited for battery chargers, lighting ballasts and all kinds of intelligent sensor
applications.
The ATtiny15L AVR is supported with a full suite of program and system development
tools including macro assemblers, program debugger/simulators, In-circuit emulators
and evaluation kits.
2
ATtiny15L
1187DS–12/01
ATtiny15L
Block Diagram
Figure 1. The ATtiny15L Block Diagram
VCC
8-BIT DATA BUS
TUNABLE
INTERNAL
INTERNAL
OSCILLATOR
OSCILLATOR
GND
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
MCU CONTROL
REGISTER
PROGRAM
FLASH
HARDWARE
STACK
INSTRUCTION
REGISTER
MCU STATUS
REGISTER
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
DECODER
TIMER/
COUNTER0
Z
CONTROL
LINES
TIMER/
COUNTER1
ALU
INTERRUPT
UNIT
STATUS
REGISTER
PROGRAMMING
LOGIC
DATA
EEPROM
ISP MODULE
ANALOG MUX
ADC
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
PORT B DRIVERS
PB0-PB5
3
1187DS–12/01
Pin Descriptions
VCC
Supply voltage pin.
Ground pin.
GND
Port B (PB5..PB0)
Port B is a 6-bit I/O port. PB4..0 are I/O pins that can provide internal pull-ups (selected
for each bit). PB5 is input or open-drain output. The use of pin PB5 is defined by a fuse
and the special function associated with this pin is external Reset. The port pins are tri-
stated when a reset condition becomes active, even if the clock is not running.
Port B also accommodates analog I/O pins. The Port B pins with alternate functions are
shown in Table 1.
Table 1. Port B Alternate Functions
Port Pin
Alternate Function
PB0
MOSI (Data Input Line for Memory Downloading)
AREF (ADC Voltage Reference)
AIN0 (Analog Comparator Positive Input)
PB1
PB2
MISO (Data Output Line for Memory Downloading)
OC1A (Timer/Counter PWM Output)
AIN1 (Analog Comparator Negative Input)
SCK (Serial Clock Input for Serial Programming)
INT0 (External Interrupt0 Input)
ADC1 (ADC Input Channel 1)
T0 (Timer/Counter0 External Counter Input)
PB3
PB4
PB5
ADC2 (ADC Input Channel 2)
ADC3 (ADC Input Channel 3)
RESET (External Reset Pin)
ADC0 (ADC Input Channel 0)
Analog Pins
Up to four analog inputs can be selected as inputs to Analog-to-Digital Converter (ADC).
Internal Oscillators
The internal oscillator provides a clock rate of nominally 1.6 MHz for the system clock
(CK). Due to large initial variation (0.8 -1.6 MHz) of the internal oscillator, a tuning capa-
bility is built in. Through an 8-bit control register – OSCCAL – the system clock rate can
be tuned with less than 1% steps of the nominal clock.
There is an internal PLL that provides a 16x clock rate locked to the system clock (CK)
for the use of the Peripheral Timer/Counter1. The nominal frequency of this peripheral
clock, PCK, is 25.6 MHz.
4
ATtiny15L
1187DS–12/01
ATtiny15L
ATtiny15L Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
$3F
$3E
$3C
$3B
$3A
$39
$38
$37
$36
$35
$34
$33
$32
$31
$30
$2F
$2E
$2D
$2C
$2B
$2A
$29
$28
$27
$26
$25
$24
$23
$22
$21
$20
$1F
$1E
$1D
$1C
$1B
$1A
$19
$18
$17
$16
$15
$14
$13
$12
$11
$10
$0F
$0E
$0D
$0C
$0B
$0A
$09
$08
$07
$06
$05
$04
…
SREG
Reserved
Reserved
GIMSK
I
T
H
S
V
N
Z
C
page 11
-
-
-
-
INT0
INTF0
PCIE
-
-
-
-
-
-
-
-
-
-
-
-
-
-
page 19
page 19
page 20
page 21
GIFR
PCIF
-
-
TIMSK
OCIE1A
OCF1A
-
-
TOIE1
TOV1
TOIE0
TOV0
TIFR
Reserved
Reserved
MCUCR
MCUSR
TCCR0
-
-
-
PUD
SE
SM1
SM0
WDRF
-
-
ISC01
EXTRF
CS01
ISC00
PORF
CS00
page 22
page 17
page 27
page 28
page 24
page 30
page 31
page 31
page 33
page 26
-
-
-
-
-
-
BORF
CS02
TCNT0
Timer/Counter0 (8-Bit)
OSCCAL
TCCR1
Oscillator Calibration Register
CTC1
PWM1
COM1A1
COM1A0
CS13
CS12
CS11
PSR1
CS10
PSR0
TCNT1
Timer/Counter1 (8-Bit)
OCR1A
OCR1B
SFIOR
Timer/Counter1 Output Compare Register A (8-Bit)
Timer/Counter1 Output Compare Register B (8-Bit)
-
-
-
-
-
FOC1A
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
WDTCR
Reserved
Reserved
EEAR
-
-
-
WDTOE
EEAR4
WDE
WDP2
WDP1
WDP0
page 34
-
-
-
-
EEAR5
-
EEAR3
EEAR2
EEAR1
EEWE
EEAR0
EERE
page 36
page 36
page 36
EEDR
EEPROM Data Register (8-Bit)
EECR
-
EERIE
EEMWE
Reserved
Reserved
Reserved
PORTB
DDRB
-
-
-
-
-
-
-
PORTB4
DDB4
PORTB3
DDB3
PORTB2
DDB2
PORTB1
DDB1
PORTB0
DDB0
page 51
page 51
page 51
DDB5
PINB5
PINB
PINB4
PINB3
PINB2
PINB1
PINB0
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
ACSR
ACD
REFS1
ADEN
ACBG
REFS0
ADSC
ACO
ADLAR
ADFR
ACI
-
ACIE
-
-
ACIS1
MUX1
ADPS1
ACIS0
MUX0
ADPS0
page 39
page 46
page 47
page 48
page 48
ADMUX
ADCSR
ADCH
MUX2
ADPS2
ADIF
ADIE
ADC Data Register High Byte
ADC Data Register Low Byte
ADCL
Reserved
Reserved
$00
5
1187DS–12/01
ATtiny15L Instruction Set Summary
Mnemonic
Operands
Description
Operation
Flags
# Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
SUB
SUBI
SBC
SBCI
AND
ANDI
OR
Rd, Rr
Rd, Rr
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add Two Registers
Rd ← Rd + Rr
Rd ← Rd + Rr + C
Rd ← Rd - Rr
Rd ← Rd - K
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Add with Carry Two Registers
Subtract Two Registers
Subtract Constant from Register
Subtract with Carry Two Registers
Subtract with Carry Constant from Reg.
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rd ← Rd • Rr
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Rd ← Rd v K
Rd ← Rd⊕Rr
Rd ← $FF - Rd
Rd ← $00 - Rd
Rd ← Rd v K
Rd ← Rd • (FFh - K)
Rd ← Rd + 1
Z,N,V
ORI
Z,N,V
EOR
COM
NEG
SBR
CBR
INC
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd, K
Rd, K
Rd
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Z,N,V
Z,N,V
DEC
TST
CLR
SER
Rd
Decrement
Rd ← Rd - 1
Z,N,V
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Rd ← Rd⊕Rd
Rd ← $FF
Z,N,V
Rd
Z,N,V
Rd
Set Register
None
BRANCH INSTRUCTIONS
RJMP
RCALL
RET
k
k
Relative Jump
PC ← PC + k + 1
None
None
None
I
2
Relative Subroutine Call
Subroutine Return
PC ← PC + k + 1
3
PC ← STACK
4
RETI
Interrupt Return
PC ← STACK
4
CPSE
CP
Rd, Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd - Rr
None
Z,N,V,C,H
Z,N,V,C,H
Z,N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2
1
Rd, Rr
CPC
Rd, Rr
Compare with Carry
Rd - Rr - C
1
CPI
Rd, K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd - K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b) = 0) PC ← PC + 2 or 3
if (Rr(b) = 1) PC ← PC + 2 or 3
if (P(b) = 0) PC ← PC + 2 or 3
if (P(b) = 1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC ← PC + k + 1
if (SREG(s) = 0) then PC ← PC + k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if (I = 1) then PC ← PC + k + 1
if (I = 0) then PC ← PC + k + 1
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half-carry Flag Set
Branch if Half-carry Flag Cleared
Branch if T-flag Set
k
k
k
k
k
Branch if T-flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
k
k
k
BRID
k
DATA TRANSFER INSTRUCTIONS
LD
Rd, Z
Z, Rr
Load Register Indirect
Store Register Indirect
Move between Registers
Load Immediate
In Port
Rd ← (Z)
(Z) ← Rr
Rd ← Rr
Rd ← K
Rd ← P
P ← Rr
None
None
None
None
None
None
None
2
2
1
1
1
1
3
ST
MOV
LDI
IN
Rd, Rr
Rd, K
Rd, P
P, Rr
OUT
LPM
Out Port
Load Program Memory
R0 ← (Z)
BIT AND BIT-TEST INSTRUCTIONS
SBI P, b
Set Bit in I/O Register
I/O(P,b) ← 1
None
2
6
ATtiny15L
1187DS–12/01
ATtiny15L
ATtiny15L Instruction Set Summary (Continued)
Mnemonic
Operands
Description
Operation
Flags
# Clocks
CBI
P, b
Rd
Rd
Rd
Rd
Rd
Rd
s
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 0
None
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
LSL
Rd(n+1) ← Rd(n), Rd(0) ← 0
Z,C,N,V
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Logical Shift Right
Rotate Left through Carry
Rotate Right through Carry
Arithmetic Shift Right
Swap Nibbles
Rd(n) ← Rd(n+1), Rd(7) ← 0
Z,C,N,V
Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7)
Z,C,N,V
Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0)
Z,C,N,V
Rd(n) ← Rd(n+1), n = 0..6
Z,C,N,V
Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0)
None
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit Load from T to Register
Set Carry
T
None
C
Clear Carry
C ← 0
C
Set Negative Flag
N ← 1
N
Clear Negative Flag
Set Zero Flag
N ← 0
N
Z ← 1
Z
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
S ← 1
S
S ← 0
S
V ← 1
V
V ← 0
V
T ← 1
T
Clear T in SREG
T ← 0
T
SEH
CLH
NOP
SLEEP
WDR
Set Half-carry Flag in SREG
Clear Half-carry Flag in SREG
No Operation
H ← 1
H
H ← 0
H
None
None
None
Sleep
(see specific descr. for Sleep function)
(see specific descr. for WDR/timer)
Watchdog Reset
7
1187DS–12/01
Ordering Information
Power Supply
Speed (MHz)
Ordering Code
Package
Operation Range
2.7 - 5.5V
1.6
ATtiny15L-1PC
ATtiny15L-1SC
8P3
8S2
Commercial
(0°C to 70°C)
ATtiny15L-1PI
ATtiny15L-1SI
8P3
8S2
Industrial
(-40°C to 85°C)
Package Type
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC)
8P3
8S2
8
ATtiny15L
1187DS–12/01
ATtiny15L
Packaging Information
8P3
8P3, 8-lead, Plastic Dual Inline
Package (PDIP), 0.300" Wide.
Dimensions in Millimeters and (Inches)*
JEDEC STANDARD MS-001 BA
10.16(0.400)
9.017(0.355)
PIN
1
7.11(0.280)
6.10(0.240)
.300 (7.62) REF
254(0.100) BSC
5.33(0.210) MAX
Seating Plane
4.95(0.195)
2.92(0.115)
3.81(0.150)
2.92(0.115)
0.381(0.015)MIN
0.559(0.022)
0.356(0.014)
1.78(0.070)
1.14(0.045)
8.26(0.325)
7.62(0.300)
0.356(0.014)
0.203(0.008)
1.524(0.060)
0.000(0.000)
10.90(0.430) MAX
*Controlling dimension: Inches
REV. A 04/11/2001
9
1187DS–12/01
8S2
.020 (.508)
.012 (.305)
.213 (5.41) .330 (8.38)
.205 (5.21) .300 (7.62)
PIN 1
.050 (1.27) BSC
.212 (5.38)
.203 (5.16)
.080 (2.03)
.070 (1.78)
.013 (.330)
.004 (.102)
0
8
REF
.010 (.254)
.007 (.178)
.035 (.889)
.020 (.508)
10
ATtiny15L
1187DS–12/01
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