ATTINY261 [ATMEL]
8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash; 8位微控制器与2/4 / 8K字节的系统内可编程闪存
| 型号： | ATTINY261 |
| 厂家： | 
ATMEL |
| 描述： | 8-bit Microcontroller with 2/4/8K Bytes In-System Programmable Flash |
| 文件： | 总19页 (文件大小：297K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 123 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• Non-volatile Program and Data Memories
– 2/4/8K Byte of In-System Programmable Program Memory Flash
(ATtiny261/461/861)
8-bit
Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM (ATtiny261/461/861)
Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM (ATtiny261/461/861)
– Programming Lock for Self-Programming Flash Program and EEPROM Data
Security
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
• Peripheral Features
– 8/16-bit Timer/Counter with Prescaler and Two PWM Channels
– 8/10-bit High Speed Timer/Counter with Separate Prescaler
3 High Frequency PWM Outputs with Separate Output Compare Registers
Programmable Dead Time Generator
– Universal Serial Interface with Start Condition Detector
– 10-bit ADC
ATtiny261/V
ATtiny461/V
ATtiny861/V
11 Single Ended Channels
16 Differential ADC Channel Pairs
15 Differential ADC Channel Pairs with Programmable Gain (1x, 8x, 20x, 32x)
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– debugWIRE On-chip Debug System
Preliminary
Summary
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
• I/O and Packages
– 16 Programmable I/O Lines
– 20-pin PDIP, 20-pin SOIC and 32-pad MLF
• Operating Voltage:
– 1.8 - 5.5V for ATtiny261V/461V/861V
– 2.7 - 5.5V for ATtiny261/461/861
• Speed Grade:
– ATtiny261V/461V/861V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny261/461/861: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
• Industrial Temperature Range
• Low Power Consumption
– Active Mode: 1 MHz, 1.8V: 380μA
– Power-down Mode: 0.1μA at 1.8V
2588BS–AVR–11/06
1. Pin Configurations
Figure 1-1. Pinout ATtiny261/461/861
PDIP/SOIC
(MOSI/DI/SDA/OC1A/PCINT8) PB0
1
20
19
18
17
16
15
14
13
12
11
PA0 (ADC0/DI/SDA/PCINT0)
PA1 (ADC1/DO/PCINT1)
PA2 (ADC2/INT1/USCK/SCL/PCINT2)
PA3 (AREF/PCINT3)
(MISO/DO/OC1A/PCINT9) PB1
(SCK/USCK/SCL/OC1B/PCINT10) PB2
(OC1B/PCINT11) PB3
2
3
4
VCC
5
AGND
GND
6
AVCC
(ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4
(ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5
(ADC9/INT0/T0/PCINT14) PB6
(ADC10/RESET/PCINT15) PB7
7
PA4 (ADC3/ICP0/PCINT4)
PA5 (ADC4/AIN2/PCINT5)
PA6 (ADC5/AIN0/PCINT6)
PA7 (ADC6/AIN1/PCINT7)
8
9
10
NC
NC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
(OC1B/PCINT11) PB3
PA2 (ADC2/INT1/USCK/SCL/PCINT2)
NC
PA3 (AREF/PCINT3)
VCC
AGND
QFN/MLF
GND
NC
NC
NC
(ADC7/OC1D/CLKI/XTAL1/PCINT12) PB4
(ADC8/OC1D/CLKO/XTAL2/PCINT13) PB5
AVCC
PA4 (ADC3/ICP0/PCINT4)
Note:
The large center pad underneath the QFN/MLF package should be soldered to ground on the board to ensure good mechanical
stability.
1.1
Disclaimer
Typical values contained in this data sheet are based on simulations and characterization of other AVR microcontrollers
manufactured on the same process technology. Min and Max values will be available after the device is characterized.
2
ATtiny261/461/861
2588BS–AVR–11/06
ATtiny261/461/861
2. Overview
The ATtiny261/461/861 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the
ATtiny261/461/861 achieves throughputs approaching 1 MIPS per MHz allowing the system
designer to optimize power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1. Block Diagram
Watchdog
Timer
Power
Supervision
POR / BOD &
RESET
debugWIRE
Watchdog
Oscillator
PROGRAM
LOGIC
Oscillator
Circuits /
Clock
Flash
SRAM
Generation
CPU
EEPROM
AVCC
AGND
AREF
Timer/Counter0
USI
Timer/Counter1
Analog Comp.
A/D Conv.
Internal
Bandgap
3
11
PORT B (8)
PORT A (8)
RESET
XTAL[1..2]
PB[0..7]
PA[0..7]
3
2588BS–AVR–11/06
The AVR core combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATtiny261/461/861 provides the following features: 2/4/8K byte of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/512 bytes SRAM, 6 general purpose I/O lines, 32
general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high
speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel,
10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software select-
able power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The
Power-down mode saves the register contents, disabling all chip functions until the next Inter-
rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules
except ADC, to minimize switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny261/461/861 AVR is supported with a full suite of program and system development
tools including: C Compilers, Macro Assemblers, Program Debugger/Simulators, In-Circuit Emu-
lators, and Evaluation kits.
2.2
Pin Descriptions
2.2.1
VCC
Supply voltage.
Ground.
2.2.2
2.2.3
2.2.4
2.2.5
GND
AVCC
AGND
Analog supply voltage.
Analog ground.
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port A output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port A pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port A pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port A also serves the functions of various special features of the ATtiny261/461/861 as listed
on page 65.
4
ATtiny261/461/861
2588BS–AVR–11/06
ATtiny261/461/861
2.2.6
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny261/461/861 as listed
on page 61.
2.2.7
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running. The minimum pulse length is given in Table 23-3 on page
189. Shorter pulses are not guaranteed to generate a reset.
5
2588BS–AVR–11/06
3. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
6
ATtiny261/461/861
2588BS–AVR–11/06
ATtiny261/461/861
4. Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
0x3C (0x5C)
0x3B (0x5B)
0x3A (0x5A)
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
0x33 (0x53)
0x32 (0x52)
0x31 (0x51)
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
0x22 (0x42)
0x21 (0x41)
0x20 (0x40)
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
0x1B (0x3B)
0x1A (0x3A)
0x19 (0x39)
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
SREG
SPH
I
–
T
–
H
–
S
–
V
–
N
Z
C
page 9
page 12
page 12
SP10
SP2
SP9
SP1
SP8
SP0
SPL
SP7
SP6
SP5
SP4
SP3
Reserved
GIMSK
GIFR
–
INT1
INTF1
OCIE1D
OCF1D
–
INT0
INTF0
OCIE1A
OCF1A
–
PCIE1
PCIF
PCIE0
–
–
–
–
–
page 51
page 51
–
–
–
–
TIMSK
TIFR
OCIE1B
OCF1B
–
OCIE0A
OCF0A
CTPB
OCIE0B
OCF0B
RFLB
PRTIM1
SM0
TOIE1
TOV1
PGWRT
PRTIM0
–
TOIE0
TOV0
PGERS
PRUSI
ISC01
EXTRF
CS01
TICIE0
ICF0
page 86, page 123
page 87, page 124
page 166
page 35
SPMCSR
PRR
SPMEN
PRADC
ISC00
PORF
CS00
MCUCR
MCUSR
TCCR0B
TCNT0L
OSCCAL
TCCR1A
TCCR1B
TCNT1
OCR1A
OCR1B
OCR1C
OCR1D
PLLCSR
CLKPR
TCCR1C
TCCR1D
TC1H
–
–
–
PUD
SE
–
SM1
–
page 37, page 68, page 50
page 44,
page 70
–
–
WDRF
PSR0
BORF
CS02
–
TSM
Timer/Counter0 Counter Register Low Byte
Oscillator Calibration Register
page 85
page 32
COM1A1
PWM1X
COM1A0
PSR1
COM1B1
DTPS11
COM1B0
DTPS10
FOC1A
CS13
FOC1B
CS12
PWM1A
CS11
PWM1B
CS10
page 113
page 166
page 121
page 121
page 122
page 122
page 123
page 89
Timer/Counter1 Counter Register
Timer/Counter1 Output Compare Register A
Timer/Counter1 Output Compare Register B
Timer/Counter1 Output Compare Register C
Timer/Counter1 Output Compare Register D
LSM
CLKPCE
COM1A1S
FPIE1
PCKE
PLLE
CLKPS1
FOC1D
WGM11
TC19
PLOCK
CLKPS0
PWM1D
WGM10
TC18
CLKPS3
COM1D1
FPAC1
CLKPS2
COM1D0
FPF1
page 32
COM1A0S
FPEN1
COM1B1S
FPNC1
COM1B0S
FPES1
page 117
page 119
page 121
page 124
page 52
DT1
DT1H3
PCINT7
PCINT15
WDIF
DT1H2
PCINT6
PCINT14
WDIE
DT1H1
PCINT5
PCINT13
WDP3
DT1H0
PCINT4
PCINT12
WDCE
DT1L3
PCINT3
PCINT11
WDE
DT1L2
PCINT2
PCINT10
WDP2
DT1L1
PCINT1
PCINT9
WDP1
DT1L0
PCMSK0
PCMSK1
WDTCR
DWDR
EEARH
EEARL
EEDR
PCINT0
PCINT8
WDP0
page 52
page 44
DWDR[7:0]
page 35
EEAR8
EEAR0
page 21
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
page 21
EEPROM Data Register
page 22
EECR
–
–
EEPM1
PORTA5
DDA5
EEPM0
PORTA4
DDA4
EERIE
PORTA3
DDA3
EEMPE
PORTA2
DDA2
EEPE
PORTA1
DDA1
EERE
PORTA0
DDA0
page 22
PORTA
DDRA
PORTA7
DDA7
PORTA6
DDA6
page 68
page 68
PINA
PINA7
PORTB7
DDB7
PINA6
PORTB6
DDB6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
page 68
PORTB
DDRB
PORTB5
DDB5
PORTB4
DDB4
PORTB3
DDB3
PORTB2
DDB2
PORTB1
DDB1
PORTB0
DDB0
page 68
page 68
PINB
PINB7
TCW0
PINB6
ICEN0
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
page 68
TCCR0A
TCNT0H
OCR0A
OCR0B
USIPP
ICNC0
ICES0
ACIC0
WGM00
page 84
Timer/Counter0 Counter Register High Byte
Timer/Counter0 Output Compare Register A
Timer/Counter0 Output Compare Register B
page 85
page 85
page 85
USIPOS
page 137
page 134
page 133
page 134
page 135
page 23
USIBR
USIDR
USISR
USICR
GPIOR2
GPIOR1
GPIOR0
ACSRB
ACSRA
ADMUX
ADCSRA
ADCH
USI Buffer Register
USI Data Register
USISIF
USISIE
USIOIF
USIOIE
USIPF
USIDC
USICNT3
USICS1
USICNT2
USICS0
USICNT1
USICLK
USICNT0
USITC
USIWM1
USIWM0
General Purpose I/O Register 2
General Purpose I/O Register 1
General Purpose I/O Register 0
page 23
page 23
HSEL
ACD
HLEV
ACBG
REFS0
ADSC
ACM2
ACME
MUX2
ADPS2
ACM1
ACIS1
MUX1
ADPS1
ACM0
ACIS0
MUX0
ADPS0
page 141
page 138
page 154
page 157
page 158
page 158
page 158
page 160
page 160
page 120
ACO
ACI
MUX4
ADIF
ACIE
MUX3
ADIE
REFS1
ADEN
ADLAR
ADATE
ADC Data Register High Byte
ADC Data Register Low Byte
ADCL
ADCSRB
DIDR1
BIN
ADC10D
ADC6D
–
GSEL
ADC9D
ADC5D
-
REFS2
ADC7D
ADC3D
OC1OE4
MUX5
ADTS2
ADTS1
ADTS0
ADC8D
ADC4D
OC1OE5
DIDR0
AREFD
ADC2D
ADC1D
ADC0D
TCCR1E
OC1OE3
OC1OE2
OC1OE1
OC1OE0
7
2588BS–AVR–11/06
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
8
ATtiny261/461/861
2588BS–AVR–11/06
ATtiny261/461/861
5. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
CBR
INC
Rd ← Rd ⊕ Rr
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Z,N,V
Z,N,V
DEC
TST
Rd
Decrement
Rd ← Rd − 1
Z,N,V
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← 0xFF
Z,N,V
CLR
SER
Rd
Z,N,V
Rd
Set Register
None
BRANCH INSTRUCTIONS
RJMP
IJMP
k
k
Relative Jump
PC ← PC + k + 1
None
None
None
None
None
I
2
2
Indirect Jump to (Z)
PC ← Z
RCALL
ICALL
RET
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
3
PC ← Z
3
Subroutine Return
PC ← STACK
4
RETI
Interrupt Return
PC ← STACK
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
k
k
k
k
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
P,b
Rd
Rd
Rd
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
None
2
2
1
1
1
CBI
LSL
LSR
ROL
I/O(P,b) ← 0
None
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Logical Shift Right
Rotate Left Through Carry
9
2588BS–AVR–11/06
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Rd
Rd
s
Arithmetic Shift Right
Swap Nibbles
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
S ← 1
S
S
V
V
T
S ← 0
V ← 1
V ← 0
T ← 1
Clear T in SREG
T ← 0
T
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H ← 1
H
H
H ← 0
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd, X
Load Indirect
Rd ← (X)
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LD
LDD
LDS
ST
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ← Rr
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
(z) ← R1:R0
Rd, P
P, Rr
Rr
Rd ← P
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
MCU CONTROL INSTRUCTIONS
NOP
No Operation
Sleep
None
None
None
None
1
1
SLEEP
WDR
(see specific descr. for Sleep function)
(see specific descr. for WDR/Timer)
For On-chip Debug Only
Watchdog Reset
Break
1
BREAK
N/A
10
ATtiny261/461/861
2588BS–AVR–11/06
ATtiny261/461/861
6. Ordering Information
6.1
ATtiny261
Speed (MHz)(3)
Power Supply
Ordering Code(2)
Package(1)
Operational Range
ATtiny261V-10MU
ATtiny261V-10PU
ATtiny261V-10SU
32M1-A
20P3
Industrial
(-40°C to 85°C)
10
20
1.8 - 5.5V
20S2
ATtiny261-20MU
ATtiny261-20PU
ATtiny261-20SU
32M1-A
20P3
Industrial
(-40°C to 85°C)
2.7 - 5.5V
20S2
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC,see Figure 23.3 on page 187
Package Type
32M1-A
20P3
32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)
20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20S2
20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)
11
2588BS–AVR–11/06
6.2
ATtiny461
Speed (MHz)(3)
Power Supply
Ordering Code(2)
Package(1)
Operational Range
ATtiny461V-10MU
ATtiny461V-10PU
ATtiny461V-10SU
32M1-A
20P3
Industrial
(-40°C to 85°C)
10
20
1.8 - 5.5V
20S2
ATtiny461-20MU
ATtiny461-20PU
ATtiny461-20SU
32M1-A
20P3
Industrial
(-40°C to 85°C)
2.7 - 5.5V
20S2
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC,see Figure 23.3 on page 187
Package Type
32M1-A
20P3
32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)
20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20S2
20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)
12
ATtiny261/461/861
2588BS–AVR–11/06
ATtiny261/461/861
6.3
ATtiny861
Speed (MHz)(3)
Power Supply
Ordering Code(2)
Package(1)
Operational Range
ATtiny861V-10MU
ATtiny861V-10PU
ATtiny861V-10SU
32M1-A
20P3
Industrial
(-40°C to 85°C)
10
20
1.8 - 5.5V
20S2
ATtiny861-20MU
ATtiny861-20PU
ATtiny861-20SU
32M1-A
20P3
Industrial
(-40°C to 85°C)
2.7 - 5.5V
20S2
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information
and minimum quantities.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For Speed vs. VCC,see Figure 23.3 on page 187
Package Type
32M1-A
20P3
32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm, Micro Lead Frame Package (MLF)
20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
20S2
20-lead, 0.300" Wide, Plastic Gull Wing Small Outline Package (SOIC)
13
2588BS–AVR–11/06
7. Packaging Information
7.1
32M1-A
D
D1
1
2
3
0
Pin 1 ID
SIDE VIEW
E1
E
TOP VIEW
A3
A1
A2
A
K
COMMON DIMENSIONS
0.08
C
(Unit of Measure = mm)
P
D2
MIN
0.80
–
MAX
1.00
0.05
1.00
NOM
0.90
NOTE
SYMBOL
A
A1
A2
A3
b
0.02
1
2
3
P
–
0.65
Pin #1 Notch
(0.20 R)
0.20 REF
0.23
E2
0.18
2.95
2.95
0.30
3.25
3.25
D
5.00 BSC
4.75 BSC
3.10
K
D1
D2
E
5.00 BSC
4.75BSC
3.10
e
b
L
E1
E2
e
BOTTOM VIEW
0.50 BSC
0.40
L
0.30
–
0.50
0.60
P
–
o
–
–
12
0
Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.
K
0.20
–
–
8/19/04
DRAWING NO. REV.
32M1-A
TITLE
2325 Orchard Parkway
San Jose, CA 95131
32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm,
3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)
D
R
14
ATtiny261/461/861
2588BS–AVR–11/06
ATtiny261/461/861
7.2
20P3
D
PIN
1
E1
A
SEATING PLANE
A1
L
B
B1
e
E
COMMON DIMENSIONS
(Unit of Measure = mm)
C
MIN
–
MAX
5.334
–
NOM
NOTE
SYMBOL
eC
A
–
–
–
–
–
–
–
–
–
–
–
eB
A1
D
0.381
25.493
7.620
6.096
0.356
1.270
2.921
0.203
–
25.984 Note 2
8.255
E
E1
B
7.112 Note 2
0.559
B1
L
1.551
Notes:
1. This package conforms to JEDEC reference MS-001, Variation AD.
2. Dimensions D and E1 do not include mold Flash or Protrusion.
Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").
3.810
C
0.356
eB
eC
e
10.922
0.000
1.524
2.540 TYP
1/12/04
DRAWING NO. REV.
20P3
TITLE
2325 Orchard Parkway
San Jose, CA 95131
20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual
Inline Package (PDIP)
C
R
15
2588BS–AVR–11/06
7.3
20S2
16
ATtiny261/461/861
2588BS–AVR–11/06
ATtiny261/461/861
8. Errata
8.1
Errata ATtiny261
The revision letter in this section refers to the revision of the ATtiny261 device.
8.1.1
Rev A
No known errata.
8.2
Errata ATtiny461
The revision letter in this section refers to the revision of the ATtiny461 device.
8.2.1
8.2.2
Rev B
Rev A
Yield improvement. No known errata.
No known errata.
8.3
Errata ATtiny861
The revision letter in this section refers to the revision of the ATtiny861 device.
8.3.1
8.3.2
Rev B
Rev A
No known errata.
Not sampled.
17
2588BS–AVR–11/06
9. Datasheet Revision History
9.1
Rev. 2588A – 11/06
1.
2.
Updated ”Ordering Information” on page 222.
Updated ”Packaging Information” on page 225.
9.2
Rev. 2588A – 10/06
1.
Initial Revision.
18
ATtiny261/461/861
2588BS–AVR–11/06
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131, USA
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
Theresienstrasse 2
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Tel: (49) 71-31-67-0
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