ATTINY26L-8PI_技术文档

Features

• High-performance, Low-power AVR ^®8-bit Microcontroller

• RISC Architecture

– 118 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

– Up to 16 MIPS Throughput at 16 MHz

• Data and Non-volatile Program Memory

– 2K Bytes of In-System Programmable Program Memory Flash

Endurance: 10,000 Write/Erase Cycles

– 128 Bytes of In-System Programmable EEPROM

Endurance: 100,000 Write/Erase Cycles

– 128 Bytes Internal SRAM

8-bit

Microcontroller

with 2K Bytes

Flash

– Programming Lock for Flash Program and EEPROM Data Security

• Peripheral Features

– 8-bit Timer/Counter with Separate Prescaler

– 8-bit High-speed Timer with Separate Prescaler

2 High Frequency PWM Outputs with Separate Output Compare Registers

Non-overlapping Inverted PWM Output Pins

– Universal Serial Interface with Start Condition Detector

– 10-bit ADC

ATtiny26

11 Single Ended Channels

8 Differential ADC Channels

7 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)

– On-chip Analog Comparator

ATtiny26L

– External Interrupt

– Pin Change Interrupt on 11 Pins

– Programmable Watchdog Timer with Separate On-chip Oscillator

• Special Microcontroller Features

Summary

– Low Power Idle, Noise Reduction, and Power-down Modes

– Power-on Reset and Programmable Brown-out Detection

– External and Internal Interrupt Sources

– In-System Programmable via SPI Port

– Internal Calibrated RC Oscillator

• I/O and Packages

– 20-lead PDIP/SOIC: 16 Programmable I/O Lines

– 32-lead MLF: 16 programmable I/O Lines

• Operating Voltages

– 2.7V - 5.5V for ATtiny26L

– 4.5V - 5.5V for ATtiny26

• Speed Grades

– 0 - 8 MHz for ATtiny26L

– 0 - 16 MHz for ATtiny26

• Power Consumption at 1 MHz, 3V and 25°C for ATtiny26L

– Active 16 MHz, 5V and 25°C: Typ 15 mA

– Active 1 MHz, 3V and 25°C: 0.70 mA

– Idle Mode 1 MHz, 3V and 25°C: 0.18 mA

– Power-down Mode: < 1 µA

Rev. 1477ES–AVR–12/03

Note: This is a summary document. A complete document

is available on our Web site at www.atmel.com.

Pin Configuration

PDIP/SOIC

(MOSI/DI/SDA/OC1A) PB0

(MISO/DO/OC1A) PB1

(SCK/SCL/OC1B) PB2

(OC1B) PB3

1

20

19

18

17

16

15

14

13

12

11

PA0 (ADC0)

PA1 (ADC1)

PA2 (ADC2)

PA3 (AREF)

GND

2

3

4

VCC

5

GND

6

AVCC

(ADC7/XTAL1) PB4

(ADC8/XTAL2) PB5

(ADC9/INT0/T0) PB6

(ADC10/RESET) PB7

7

PA4 (ADC3)

PA5 (ADC4)

PA6 (ADC5/AIN0)

PA7 (ADC6/AIN1)

8

9

10

MLF Top View

NC

24

NC

1

PA2 (ADC2)

(OC1B) PB3

2

23

22

21

20

19

18

17

PA3 (AREF)

GND

NC

3

VCC

4

NC

GND

5

NC

6

AVCC

(ADC7/XTAL1) PB4

7

PA4 (ADC3)

(ADC8/XTAL2) PB5

8

2

ATtiny26(L)

1477ES–AVR–12/03

ATtiny26(L)

Description

The ATtiny26(L) is a low-power CMOS 8-bit microcontroller based on the AVR

enhanced RISC architecture. By executing powerful instructions in a single clock cycle,

the ATtiny26(L) achieves throughputs approaching 1 MIPS per MHz allowing the system

designer to optimize power consumption versus processing speed.

The AVR core combines a rich instruction set with 32 general purpose working registers.

All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing

two independent registers to be accessed in one single instruction executed in one clock

cycle. The resulting architecture is more code efficient while achieving throughputs up to

ten times faster than conventional CISC microcontrollers. The ATtiny26(L) has a high

precision ADC with up to 11 single ended channels and 8 differential channels. Seven

differential channels have an optional gain of 20x. Four out of the seven differential

channels, which have the optional gain, can be used at the same time. The ATtiny26(L)

also has a high frequency 8-bit PWM module with two independent outputs. Two of the

PWM outputs have inverted non-overlapping output pins ideal for synchronous rectifica-

tion. The Universal Serial Interface of the ATtiny26(L) allows efficient software

implementation of TWI (Two-wire Serial Interface) or SM-bus interface. These features

allow for highly integrated battery charger and lighting ballast applications, low-end ther-

mostats, and firedetectors, among other applications.

The ATtiny26(L) provides 2K bytes of Flash, 128 bytes EEPROM, 128 bytes SRAM, up

to 16 general purpose I/O lines, 32 general purpose working registers, two 8-bit

Timer/Counters, one with PWM outputs, internal and external Oscillators, internal and

external interrupts, programmable Watchdog Timer, 11-channel, 10-bit Analog to Digital

Converter with two differential voltage input gain stages, and four software selectable

power saving modes. The Idle mode stops the CPU while allowing the Timer/Counters

and interrupt system to continue functioning. The ATtiny26(L) also has a dedicated ADC

Noise Reduction mode for reducing the noise in ADC conversion. In this sleep mode,

only the ADC is functioning. The Power-down mode saves the register contents but

freezes the oscillators, disabling all other chip functions until the next interrupt or hard-

ware reset. The Standby mode is the same as the Power-down mode, but external

oscillators are enabled. The wakeup or interrupt on pin change features enable the

ATtiny26(L) to be highly responsive to external events, still featuring the lowest power

consumption while in the Power-down mode.

The device is manufactured using Atmel’s high density non-volatile memory technology.

By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the

ATtiny26(L) is a powerful microcontroller that provides a highly flexible and cost effec-

tive solution to many embedded control applications.

The ATtiny26(L) AVR is supported with a full suite of program and system development

tools including: Macro assemblers, program debugger/simulators, In-circuit emulators,

and evaluation kits.

3

1477ES–AVR–12/03

Block Diagram

Figure 1. The ATtiny26(L) Block Diagram

VCC

8-BIT DATA BUS

INTERNAL

CALIBRATED

OSCILLATOR

INTERNAL

OSCILLATOR

GND

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

TIMING AND

CONTROL

MCU CONTROL

REGISTER

PROGRAM

FLASH

SRAM

AVCC

MCU STATUS

REGISTER

INSTRUCTION

REGISTER

GENERAL

PURPOSE

REGISTERS

TIMER/

COUNTER0

X

Y

Z

INSTRUCTION

DECODER

TIMER/

COUNTER1

CONTROL

LINES

ALU

UNIVERSAL

SERIAL

INTERFACE

STATUS

REGISTER

INTERRUPT

UNIT

PROGRAMMING

LOGIC

EEPROM

OSCILLATORS

ISP INTERFACE

DATA REGISTER

PORT A

DATA DIR.

REG.PORT A

ADC

DATA REGISTER

PORT B

DATA DIR.

REG.PORT B

PORT A DRIVERS

PORT B DRIVERS

PA0-PA7

PB0-PB7

4

ATtiny26(L)

1477ES–AVR–12/03

ATtiny26(L)

Pin Descriptions

VCC

Digital supply voltage pin.

Digital ground pin.

GND

AVCC

AVCC is the supply voltage pin for Port A and the A/D Converter (ADC). It should be

externally connected to V_CC, even if the ADC is not used. If the ADC is used, it should be

connected to V_CCthrough a low-pass filter. See page 77 for details on operating of the

ADC.

Port A (PA7..PA0)

Port B (PB7..PB0)

Port A is an 8-bit general purpose I/O port. PA7..PA0 are all I/O pins that can provide

internal pull-ups (selected for each bit). Port A has alternate functions as analog inputs

for the ADC and analog comparator and pin change interrupt as described in “Alternate

Port Functions” on page 95.

Port B is an 8-bit general purpose I/O port. PB6..0 are all I/O pins that can provide inter-

nal pull-ups (selected for each bit). PB7 is an I/O pin if not used as the reset. To use pin

PB7 as an I/O pin, instead of RESET pin, program (“0”) RSTDISBL Fuse. Port B has

alternate functions for the ADC, clocking, timer counters, USI, SPI programming, and

pin change interrupt as described in “Alternate Port Functions” on page 95.

An External Reset is generated by a low level on the PB7/RESET pin. Reset pulses

longer than 50 ns will generate a reset, even if the clock is not running. Shorter pulses

are not guaranteed to generate a reset.

XTAL1

XTAL2

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting oscillator amplifier.

5

1477ES–AVR–12/03

Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$3F ($5F)

$3E ($5E)

$3D ($5D)

$3C ($5C)

$3B ($5B)

$3A ($5A)

$39 ($59)

$38 ($58)

$37 ($57)

$36 ($56)

$35 ($55)

$34 ($54)

$33 ($53)

$32 ($52)

$31 ($51)

$30 ($50)

$2F ($4F)

$2E ($4E)

$2D ($4D)

$2C ($4C)

$2B ($4B)

$2A ($4A)

$29 ($49)

$28 ($48)

$27 ($47)

$26 ($46)

$25 ($45)

$24 ($44)

$23 ($43)

$22 ($42)

$21 ($41)

$20 ($40)

$1F ($3F)

$1E ($3E)

$1D ($3D)

$1C ($3C)

$1B ($3B)

$1A ($3A)

$19 ($39)

$18 ($38)

$17 ($37)

$16 ($36)

$15 ($35)

$14 ($34)

$13 ($33)

$12 ($32)

$11 ($31)

$10 ($30)

$0F ($2F)

$0E ($2E)

$0D ($2D)

$0C ($2C)

$0B ($2)B

$0A ($2A)

$09 ($29)

$08 ($28)

$07 ($27)

$06 ($26)

$05 ($25)

$04 ($24)

…

SREG

Reserved

SP

I

T

H

S

V

N

Z

C

18

SP7

SP6

SP5

SP4

SP3

SP2

SP1

SP0

19

Reserved

GIMSK

-

INT0

INTF0

PCIE1

PCIF

PCIE0

-

34

35

36

37

GIFR

-

TIMSK

OCIE1A

OCF1A

OCIE1B

OCF1B

TOIE1

TOV1

TOIE0

TOV0

TIFR

Reserved

MCUCR

MCUSR

TCCR0

TCNT0

-

PUD

SE

SM1

SM0

WDRF

PSR0

-

ISC01

EXTRF

CS01

ISC00

PORF

CS00

39

33

46

47

31

50

51

52

53

-

BORF

CS02

Timer/Counter0 (8-Bit)

OSCCAL

TCCR1A

TCCR1B

TCNT1

Oscillator Calibration Register

COM1A1

CTC1

COM1A0

PSR1

COM1B1

-

COM1B0

-

FOC1A

CS13

FOC1B

CS12

PWM1A

CS11

PWM1B

CS10

Timer/Counter1 (8-Bit)

OCR1A

OCR1B

OCR1C

Reserved

PLLCSR

Reserved

WDTCR

Reserved

EEAR

Timer/Counter1 Output Compare Register A (8-Bit)

Timer/Counter1 Output Compare Register B (8-Bit)

Timer/Counter1 Output Compare Register C (8-Bit)

-

PCKE

PLLE

PLOCK

-

WDCE

EEAR4

WDE

WDP2

WDP1

WDP0

58

EEAR6

EEAR5

EEAR3

EEAR2

EEAR1

EEAR0

60

EEDR

EEPROM Data Register (8-Bit)

EECR

-

EERIE

PORTA3

DDA3

EEMWE

PORTA2

DDA2

EEWE

PORTA1

DDA1

EERE

PORTA0

DDA0

PORTA

DDRA

PORTA7

DDA7

PORTA6

DDA6

PORTA5

DDA5

PORTA4

DDA4

PINA

PINA7

PORTB7

DDB7

PINA6

PORTB6

DDB6

PINA5

PORTB5

DDB5

PINA4

PORTB4

DDB4

PINA3

PINA2

PINA1

PINA0

PORTB

DDRB

PORTB3

DDB3

PORTB2

DDB2

PORTB1

DDB1

PORTB0

DDB0

PINB

PINB7

PINB6

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

Reserved

USIDR

Universal Serial Interface Data Register (8-Bit)

64

65

USISR

USISIF

USISIE

USIOIF

USIOIE

USIPF

USIDC

USICNT3

USICS1

USICNT2

USICS0

USICNT1

USICLK

USICNT0

USITC

USICR

USIWM1

USIWM0

Reserved

ACSR

ACD

REFS1

ADEN

ACBG

REFS0

ADSC

ACO

ADLAR

ADFR

ACI

ACIE

MUX3

ADIE

ACME

MUX2

ACIS1

MUX1

ADPS1

ACIS0

MUX0

ADPS0

74

84

86

87

ADMUX

ADCSR

ADCH

MUX4

ADIF

ADPS2

ADC Data Register High Byte

ADC Data Register Low Byte

ADCL

Reserved

$00 ($20)

6

ATtiny26(L)

1477ES–AVR–12/03

ATtiny26(L)

Instruction Set Summary

Mnemonic

Operands

Description

Operation

Flags

# Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

OR

Rd, Rr

Rdl, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add Two Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

Add with Carry Two Registers

Add Immediate to Word

Subtract Two Registers

Subtract Constant from Register

Subtract with Carry Two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Rd ← Rd v K

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Z,N,V

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd Rr

Rd ← $FF - Rd

Rd ← $00 - Rd

Rd ← Rd v K

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd, K

Rd

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd ← Rd • ($FF - K)

Rd ← Rd + 1

Z,N,V

DEC

TST

Rd

Decrement

Rd ← Rd - 1

Z,N,V

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Rd ← Rd Rd

Rd ← $FF

Z,N,V

CLR

SER

Rd

Z,N,V

Rd

Set Register

None

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

RCALL

ICALL

RET

k

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

Subroutine Return

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd, Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd - Rr

None

Z,N,V,C,H

None

1/2/3

1

Rd, Rr

CPC

Rd, Rr

Compare with Carry

Rd - Rr - C

1

CPI

Rd, K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd - K

1

SBRC

SBRS

SBIC

SBIS

Rr, b

if (Rr(b) = 0) PC ← PC + 2 or 3

if (Rr(b) = 1) PC ← PC + 2 or 3

if (P(b) = 0) PC ← PC + 2 or 3

if (P(b) = 1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC ← PC + k + 1

if (SREG(s) = 0) then PC ← PC + k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N V = 0) then PC ← PC + k + 1

if (N V = 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if (I = 1) then PC ← PC + k + 1

if (I = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less than Zero, Signed

Branch if Half-carry Flag Set

Branch if Half-carry Flag Cleared

Branch if T-flag Set

k

Branch if T-flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

DATA TRANSFER INSTRUCTIONS

MOV

LDI

LD

Rd, Rr

Rd, K

Move between Registers

Load Immediate

Rd ← Rr

None

1

2

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, -X

Load Indirect and Post-inc.

Load Indirect and Pre-dec.

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

LD

7

1477ES–AVR–12/03

Instruction Set Summary (Continued)

Mnemonic

Operands

Description

Operation

Flags

# Clocks

LD

Rd, Y

Load Indirect

Rd ← (Y)

None

2

3

1

2

LD

Rd, Y+

Rd, -Y

Rd,Y+q

Rd, Z

Load Indirect and Post-inc.

Load Indirect and Pre-dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-inc.

Load Indirect and Pre-dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z + 1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

-X, Rr

Y, Rr

Store Indirect and Post-inc.

Store Indirect and Pre-dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

-Y, Rr

Y+q, Rr

Z, Rr

Store Indirect and Post-inc.

Store Indirect and Pre-dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

(Z) ← Rr

ST

STD

ST

Z+, Rr

-Z, Rr

Z+q, Rr

k, Rr

Store Indirect and Post-inc.

Store Indirect and Pre-dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

IN

(k) ← Rr

R0 ← (Z)

Rd, Z

Rd, P

P, Rr

Rr

Rd ← (Z)

Rd ← P

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

BIT AND BIT-TEST INSTRUCTIONS

SBI

P, b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rotate Left through Carry

Rotate Right through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7)

Z,C,N,V

Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n = 0..6

Z,C,N,V

Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit Load from T to Register

Set Carry

T

None

C

Clear Carry

C ← 0

C

Set Negative Flag

N ← 1

N

Clear Negative Flag

Set Zero Flag

N ← 0

N

Z ← 1

Z

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Two’s Complement Overflow

Clear Two’s Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

NOP

SLEEP

WDR

S ← 1

S

S ← 0

S

V ← 1

V

V ← 0

V

T ← 1

T

Clear T in SREG

T ← 0

T

Set Half-carry Flag in SREG

Clear Half-carry Flag in SREG

No Operation

H ← 1

H

H ← 0

H

None

Sleep

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

Watchdog Reset

8

ATtiny26(L)

1477ES–AVR–12/03

ATtiny26(L)

Ordering Information⁽¹⁾

Speed (MHz)

Power Supply

Ordering Code

Package

Operation Range

8

2.7 - 5.5V

ATtiny26L-8PC

ATtiny26L-8SC

ATtiny26L-8MC

20P3

20S

32M1-A

Commercial

(0°C to 70°C)

ATtiny26L-8PI

ATtiny26L-8SI

ATtiny26L-8MI

20P3

20S

32M1-A

Industrial

(-40°C to 85°C)

16

4.5 - 5.5V

ATtiny26-16PC

ATtiny26-16SC

ATtiny26-16MC

20P3

20S

32M1-A

Commercial

(0°C to 70°C)

ATtiny26-16PI

ATtiny26-16SI

ATtiny26-16MI

20P3

20S

32M1-A

Industrial

(-40°C to 85°C)

Note:

1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

9

1477ES–AVR–12/03

Package Type

20P3

20S

20-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

20-lead, 0.300" Wide, Plastic Gull Wing Small Outline (SOIC)

32-pad, 5 x 5 x 1.0 body, Lead Pitch 0.50 mm Micro Lead Frame Package (MLF)

32M1-A

10

ATtiny26(L)

1477ES–AVR–12/03

ATtiny26(L)

Packaging Information

20P3

D

1

E1

A

SEATING PLANE

A1

L

B

B1

e

E

COMMON DIMENSIONS

(Unit of Measure = mm)

C

MIN

–

MAX

5.334

–

NOM

NOTE

SYMBOL

eC

A

–

eB

A1

D

0.381

25.984

7.620

6.096

0.356

1.270

2.921

0.203

–

25.493 Note 2

8.255

E

E1

B

7.112 Note 2

0.559

B1

L

1.551

Notes:

1. This package conforms to JEDEC reference MS-001, Variation AD.

2. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

3.810

C

0.356

eB

eC

e

10.922

0.000

1.524

2.540 TYP

09/28/01

DRAWING NO. REV.

20P3

TITLE

2325 Orchard Parkway

San Jose, CA 95131

20P3, 20-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP)

B

R

11

1477ES–AVR–12/03

20S

C

1

H

E

N

A1

Top View

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

MIN

MAX

NOM

NOTE

SYMBOL

e

b

A

A1

b

0.0926

0.0040

0.0130

0.0091

0.4961

0.2914

0.3940

0.0160

0.1043

0.0118

0.0200

0.0125

0.5118

0.2992

0.4190

0.050

A

4

C

D

E

H

L

D

1

2

Side View

3

e

0.050 BSC

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-013, Variation AC for additional information.

2. Dimension "D" does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed

0.15 mm (0.006") per side.

3. Dimension "E" does not include inter-lead Flash or protrusion. Inter-lead Flash and protrusions shall not exceed 0.25 mm

(0.010") per side.

4. "L" is the length of the terminal for soldering to a substrate.

5. The lead width "b", as measured 0.36 mm (0.014") or greater above the seating plane, shall not exceed a maximum value of 0.61 mm

1/9/02

(0.024") per side.

TITLE

DRAWING NO.

REV.

20S2, 20-lead, 0.300" Wide Body, Plastic Gull

Wing Small Outline Package (SOIC)

2325 Orchard Parkway

San Jose, CA 95131

A

20S2

R

12

ATtiny26(L)

1477ES–AVR–12/03

ATtiny26(L)

32M1-A

D

D1

1

2

3

0

Pin 1 ID

SIDE VIEW

E1

E

TOP VIEW

A3

A1

A2

A

0.08

C

P

COMMON DIMENSIONS

(Unit of Measure = mm)

D2

Pin 1 ID

MIN

0.80

–

MAX

1.00

0.05

1.00

NOM

0.90

NOTE

SYMBOL

1

2

3

A

P

A1

A2

A3

b

0.02

–

0.65

E2

0.20 REF

0.23

0.18

2.95

0.30

3.25

D

5.00 BSC

4.75 BSC

3.10

D1

D2

E

e

b

L

5.00 BSC

4.75BSC

3.10

BOTTOM VIEW

E1

E2

e

0.50 BSC

0.40

L

0.30

–

0.50

0.60

P

–

Notes: 1. JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.

o

–

12

0

01/15/03

DRAWING NO. REV.

32M1-A

TITLE

2325 Orchard Parkway

San Jose, CA 95131

32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm

Micro Lead Frame Package (MLF)

C

R

13

1477ES–AVR–12/03

Datasheet Change

Log for ATtiny26

Please note that the referring page numbers in this section are referred to this docu-

ment. The referring revision in this section are referring to the document revision.

Changes from Rev.

1477D-05/03 to Rev.

1477E-10/03

1. Removed Preliminary references.

2. Updated “Features” on page 1.

3. Removed SSOP package reference from “Pin Configuration” on page 2.

4. Updated V_RSTand t_RSTin Table 3 on page 22.

5. Updated “Calibrated Internal RC Oscillator” on page 31.

6. Updated DC Charcteristics for V_OL, I_IL, I_IH, I_CCPower Down and V_ACIOin “Electri-

cal Characteristics” on page 125.

7. Updated V_INT, INL and Gain Error in “ADC Characteristics” on page 128 and

page 129. Fixed typo in “Absolute Accuracy” on page 129.

8. Added Figure 106 in “Pin Driver Strength” on page 145, Figure 120, Figure 121

and Figure 122 in “BOD Thresholds and Analog Comparator Offset” on page

154. Updated Figure 117 and Figure 118.

9. Removed LPM Rd, Z+ from “Instruction Set Summary” on page 7. This

instruction is not supported in ATtiny26.

Changes from Rev.

1477C-09/02 to Rev.

1477D-05/03

1. Updated “Packaging Information” on page 11.

2. Removed ADHSM from “ADC Characteristics” on page 128.

3. Added section “EEPROM Write During Power-down Sleep Mode” on page 62.

4. Added section “Default Clock Source” on page 28.

5. Corrected PLL Lock value in the “Bit 0 – PLOCK: PLL Lock Detector” on page

54.

6. Added information about conversion time when selecting differential chan-

nels on page 80.

7. Corrected {DDxn, PORTxn} value on page 92.

8. Added section “Unconnected Pins” on page 95.

9. Added note for RSTDISBL Fuse in Table 49 on page 107.

10. Corrected DATA value in Figure 61 on page 115.

11. Added WD_FUSE period in Table 59 on page 122.

12. Updated “ADC Characteristics” on page 128 and added Table 64, “ADC Char-

acteristics, Differential Channels, TA = -40×C to 85×C,” on page 129.

14

ATtiny26(L)

1477ES–AVR–12/03

ATtiny26(L)

13. Updated “ATtiny26 Typical Characteristics” on page 130.

14. Added LPM Rd, Z and LPM Rd, Z+ in “Instruction Set Summary” on page 7.

1. Changed the Endurance on the Flash to 10,000 Write/Erase Cycles.

Changes from Rev.

1477B-04/02 to Rev.

1477C-09/02

Changes from Rev.

1477A-03/02 to Rev.

1477B-04/02

1. Removed all references to Power Save sleep mode in the section “System

Clock and Clock Options” on page 25.

2. Updated the section “Analog to Digital Converter” on page 77 with more

details on how to read the conversion result for both differential and single-

ended conversion.

3. Updated “Ordering Information⁽¹⁾” on page 9 and added MLF package

information.

15

1477ES–AVR–12/03

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Tel: (41) 26-426-5555

Fax: (41) 26-426-5500

Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Avenue de Rochepleine

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

Tel: (33) 2-40-18-18-18

Fax: (33) 2-40-18-19-60

BP 123

38521 Saint-Egreve Cedex, France

Tel: (33) 4-76-58-30-00

Fax: (33) 4-76-58-34-80

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

Tel: (33) 4-42-53-60-00

Fax: (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

Literature Requests

www.atmel.com/literature

Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard

warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any

errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and

does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are

granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use

as critical components in life support devices or systems.

Atmel Corporation or its subsidiaries. Microsoft^®, Windows^®, Windows NT^®, and Windows XP^®are the registered trademarks of Microsoft Corpo-

ration. Other terms and product names may be the trademarks of others

Printed on recycled paper.

1477ES–AVR–12/03


型号：	ATTINY26L-8PI
厂家：	ATMEL
描述：	8-bit Microcontroller with 2K Bytes Flash 8位微控制器与2K字节的闪存闪存微控制器
文件：	总16页 (文件大小：134K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATTINY26L-8PI [ATMEL]

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ATTINY26_06