ATTINY28V-1PJ_技术文档

Features

• Utilizes the AVR^®RISC Architecture

• AVR – High-performance and Low-power RISC Architecture

– 90 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General-purpose Working Registers

– Up to 4 MIPS Throughput at 4 MHz

• Nonvolatile Program Memory

– 2K Bytes of Flash Program Memory

– Endurance: 1,000 Write/Erase Cycles

– Programming Lock for Flash Program Data Security

• Peripheral Features

8-bit

– Interrupt and Wake-up on Low-level Input

– One 8-bit Timer/Counter with Separate Prescaler

– On-chip Analog Comparator

Microcontroller

with 2K Bytes of

Flash

– Programmable Watchdog Timer with On-chip Oscillator

– Built-in High-current LED Driver with Programmable Modulation

• Special Microcontroller Features

– Low-power Idle and Power-down Modes

– External and Internal Interrupt Sources

– Power-on Reset Circuit with Programmable Start-up Time

– Internal Calibrated RC Oscillator

ATtiny28L

ATtiny28V

• Power Consumption at 1 MHz, 2V, 25°C

– Active: 3.0 mA

– Idle Mode: 1.2 mA

– Power-down Mode: <1 µA

• I/O and Packages

– 11 Programmable I/O Lines, 8 Input Lines and a High-current LED Driver

– 28-lead PDIP, 32-lead TQFP, and 32-pad MLF

• Operating Voltages

– V_CC: 1.8V - 5.5V for the ATtiny28V

– V_CC: 2.7V - 5.5V for the ATtiny28L

• Speed Grades

– 0 - 1.2 MHz for the ATtiny28V

– 0 - 4 MHz For the ATtiny28L

Pin Configurations

PDIP

TQFP/QFN/MLF

RESET

PD0

1

2

3

4

5

6

7

8

9

28 PA0

27 PA1

PD1

26 PA3

PD2

25 PA2 (IR)

24 PB7

PD3

PD4

1

2

3

4

5

6

7

8

24 PB7

23 PB6

22 NC

21 GND

20 NC

19 NC

18 VCC

17 PB5

PD3

PD4

23 PB6

NC

VCC

GND

NC

VCC

GND

XTAL1

22 GND

21 NC

20 VCC

XTAL1

XTAL2

XTAL2 10

PD5 11

19 PB5

18 PB4 (INT1)

17 PB3 (INT0)

16 PB2 (T0)

15 PB1 (AIN1)

PD6 12

PD7 13

(AIN0) PB0 14

Rev. 1062F–AVR–07/06

1

Description

The ATtiny28 is a low-power CMOS 8-bit microcontroller based on the AVR RISC archi-

tecture. By executing powerful instructions in a single clock cycle, the ATtiny28 achieves

throughputs approaching 1 MIPS per MHz, allowing the system designer to optimize

power consumption versus processing speed. The AVR core combines a rich instruction

set with 32 general-purpose working registers. All the 32 registers are directly con-

nected to the Arithmetic Logic Unit (ALU), allowing two independent registers to be

accessed in one single instruction executed in one clock cycle. The resulting architec-

ture is more code efficient while achieving throughputs up to ten times faster than

conventional CISC microcontrollers.

Block Diagram

Figure 1. The ATtiny28 Block Diagram

VCC

XTAL1

XTAL2

INTERNAL

8-BIT DATA BUS

CALIBRATED

OSCILLATOR

INTERNAL

OSCILLATOR

GND

RESET

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

TIMING AND

CONTROL

MCU CONTROL

REGISTER

PROGRAM

FLASH

HARDWARE

STACK

TIMER/

COUNTER

INSTRUCTION

REGISTER

GENERAL

PURPOSE

REGISTERS

INTERRUPT

UNIT

INSTRUCTION

DECODER

Z

CONTROL

LINES

ALU

STATUS

REGISTER

HARDWARE

MODULATOR

PROGRAMMING

LOGIC

DATA REGISTER

PORTB

DATA REGISTER

PORTD

DATA DIR

REG. PORTD

DATA REGISTER

PORTA

PORTA CONTROL

REGISTER

PORTB

PORTA

PORTD

The ATtiny28 provides the following features: 2K bytes of Flash, 11 general-purpose I/O

lines, 8 input lines, a high-current LED driver, 32 general-purpose working registers, an

8-bit timer/counter, internal and external interrupts, programmable Watchdog Timer with

internal oscillator and 2 software-selectable power-saving modes. The Idle Mode stops

the CPU while allowing the timer/counter and interrupt system to continue functioning.

The Power-down mode saves the register contents but freezes the oscillator, disabling

all other chip functions until the next interrupt or hardware reset. The wake-up or inter-

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ATtiny28L/V

rupt on low-level input feature enables the ATtiny28 to be highly responsive to external

events, still featuring the lowest power consumption while in the power-down modes.

The device is manufactured using Atmel’s high-density, nonvolatile memory technology.

By combining an enhanced RISC 8-bit CPU with Flash on a monolithic chip, the Atmel

ATtiny28 is a powerful microcontroller that provides a highly flexible and cost-effective

solution to many embedded control applications. The ATtiny28 AVR is supported with a

full suite of program and system development tools including: macro assemblers, pro-

gram debugger/simulators, in-circuit emulators and evaluation kits.

Pin Descriptions

VCC

Supply voltage pin.

Ground pin.

GND

Port A (PA3..PA0)

Port A is a 4-bit I/O port. PA2 is output-only and can be used as a high-current LED

driver. At V_CC= 2.0V, the PA2 output buffer can sink 25 mA. PA3, PA1 and PA0 are

bi-directional I/O pins with internal pull-ups (selected for each bit). The port pins are tri-

stated when a reset condition becomes active, even if the clock is not running.

Port B (PB7..PB0)

Port B is an 8-bit input port with internal pull-ups (selected for all Port B pins). Port B

pins that are externally pulled low will source current if the pull-ups are activated.

Port B also serves the functions of various special features of the ATtiny28 as listed on

page 27. If any of the special features are enabled, the pull-up(s) on the corresponding

pin(s) is automatically disabled. The port pins are tri-stated when a reset condition

becomes active, even if the clock is not running.

Port D (PD7..PD0)

Port D is an 8-bit I/O port. Port pins can provide internal pull-up resistors (selected for

each bit). The port pins are tri-stated when a reset condition becomes active, even if the

clock is not running.

XTAL1

XTAL2

RESET

Input to the inverting oscillator amplifier and input to the internal clock operating circuit.

Output from the inverting oscillator amplifier.

Reset input. An external reset is generated by a low level on the RESET pin. Reset

pulses longer than 50 ns will generate a reset, even if the clock is not running. Shorter

pulses are not guaranteed to generate a reset.

Figure 2.

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Architectural

Overview

The fast-access register file concept contains 32 x 8-bit general-purpose working regis-

ters with a single clock cycle access time. This means that during one single clock cycle,

one ALU (Arithmetic Logic Unit) operation is executed. Two operands are output from

the register file, the operation is executed, and the result is stored back in the register

file – in one clock cycle.

Two of the 32 registers can be used as a 16-bit pointer for indirect memory access. This

pointer is called the Z-pointer and can address the register file and the Flash program

memory.

Figure 3. The ATtiny28 AVR RISC Architecture

Data Bus 8-bit

Status

and Test

Control

Registrers

1K x 16

Program

Flash

Program

Counter

Interrupts

Unit

32 x 8

General

Purpose

Registrers

Instruction

Register

8-bit

Timer/Counter

Z

Watchdog

Timer

Instruction

Decoder

Analog

Comparator

ALU

20

Control Lines

I/O Lines

The ALU supports arithmetic and logic functions between registers or between a con-

stant and a register. Single register operations are also executed in the ALU. Figure 3

shows the ATtiny28 AVR RISC microcontroller architecture. The AVR uses a Harvard

architecture concept – with separate memories and buses for program and data memo-

ries. The program memory is accessed with a two-stage pipeline. While one instruction

is being executed, the next instruction is pre-fetched from the program memory. This

concept enables instructions to be executed every clock cycle. The program memory is

reprogrammable Flash memory.

With the relative jump and relative call instructions, the whole 1K address space is

directly accessed. All AVR instructions have a single 16-bit word format, meaning that

every program memory address contains a single 16-bit instruction.

During interrupts and subroutine calls, the return address program counter (PC) is

stored on the stack. The stack is a 3-level-deep hardware stack dedicated for subrou-

tines and interrupts.

The I/O memory space contains 64 addresses for CPU peripheral functions such as

Control Registers, Timer/Counters and other I/O functions. The memory spaces in the

AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional

global interrupt enable bit in the status register. All the different interrupts have a sepa-

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ATtiny28L/V

rate interrupt vector in the interrupt vector table at the beginning of the

program memory. The different interrupts have priority in accordance with their interrupt

vector position. The lower the interrupt vector address, the higher the priority.

ALU – Arithmetic Logic

Unit

The high-performance AVR ALU operates in direct connection with all the 32 general-

purpose working registers. Within a single clock cycle, ALU operations between regis-

ters in the register file are executed. The ALU operations are divided into three main

categories – arithmetic, logic and bit functions. Some microcontrollers in the AVR prod-

uct family feature a hardware multiplier in the arithmetic part of the ALU.

Subroutine and Interrupt The ATtiny28 uses a 3-level-deep hardware stack for subroutines and interrupts. The

hardware stack is 10 bits wide and stores the program counter (PC) return address

while subroutines and interrupts are executed.

Hardware Stack

RCALL instructions and interrupts push the PC return address onto stack level 0, and

the data in the other stack levels 1 - 2 are pushed one level deeper in the stack. When a

RET or RETI instruction is executed the returning PC is fetched from stack level 0, and

the data in the other stack levels 1 - 2 are popped one level in the stack.

If more than three subsequent subroutine calls or interrupts are executed, the first val-

ues written to the stack are overwritten.

General-purpose

Register File

Figure 4 shows the structure of the 32 general-purpose registers in the CPU.

Figure 4. AVR CPU General-purpose Working Registers

7

0

R0

R1

R2

General

Purpose

Working

Registers

…

R28

R29

R30 (Z-Register low byte)

R31(Z-Register high byte)

All the register operating instructions in the instruction set have direct and single cycle

access to all registers. The only exception are the five constant arithmetic and logic

instructions SBCI, SUBI, CPI, ANDI and ORI between a constant and a register and the

LDI instruction for load immediate constant data. These instructions apply to the second

half of the registers in the register file – R16..R31. The general SBC, SUB, CP, AND,

OR and all other operations between two registers or on a single register apply to the

entire register file.

Registers 30 and 31 form a 16-bit pointer (the Z-pointer), which is used for indirect Flash

memory and register file access. When the register file is accessed, the contents of R31

are discarded by the CPU.

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Status Register

Status Register – SREG

The AVR status register (SREG) at I/O space location $3F is defined as:

Bit

7

I

6

T

5

H

4

S

3

V

2

N

1

Z

0

C

$3F

SREG

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – I: Global Interrupt Enable

The global interrupt enable bit must be set (one) for the interrupts to be enabled. The

individual interrupt enable control is then performed in separate control registers. If the

global interrupt enable register is cleared (zero), none of the interrupts are enabled inde-

pendent of the individual interrupt enable settings. The I-bit is cleared by hardware after

an interrupt has occurred, and is set by the RETI instruction to enable subsequent

interrupts.

• Bit 6 – T: Bit Copy Storage

The bit copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source

and destination for the operated bit. A bit from a register in the register file can be copied

into T by the BST instruction, and a bit in T can be copied into a bit in a register in the

register file by the BLD instruction.

• Bit 5 – H: Half-carry Flag

The half-carry flag H indicates a half-carry in some arithmetic operations. See the

Instruction Set description for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the negative flag N and the two’s comple-

ment overflow flag V. See the Instruction Set description for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The two’s complement overflow flag V supports two’s complement arithmetic. See the

Instruction Set description for detailed information.

• Bit 2 – N: Negative Flag

The negative flag N indicates a negative result from an arithmetical or logical operation.

See the Instruction Set description for detailed information.

• Bit 1 – Z: Zero Flag

The zero flag Z indicates a zero result from an arithmetical or logical operation. See the

Instruction Set description for detailed information.

• Bit 0 – C: Carry Flag

The carry flag C indicates a carry in an arithmetical or logical operation. See the Instruc-

tion Set description for detailed information.

Note that the status register is not automatically stored when entering an interrupt rou-

tine and restored when returning from an interrupt routine. This must be handled by

software.

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ATtiny28L/V

System Clock and

Clock Options

The device has the following clock source options, selectable by Flash Fuse bits as

shown in Table 1.

Table 1. Device Clocking Option Select

Clock Option

CKSEL3..0

1111 - 1010

1001 - 1000

0111 - 0101

0100 - 0010

0001 - 0000

External Crystal/Ceramic Resonator

External Low-frequency Crystal

External RC Oscillator

Internal RC Oscillator

External Clock

Note:

“1” means unprogrammed, “0” means programmed.

The various choices for each clocking option give different start-up times as shown in

Table 5 on page 16.

Internal RC Oscillator

The internal RC oscillator option is an on-chip calibrated oscillator running at a nominal

frequency of 1.2 MHz. If selected, the device can operate with no external components.

The device is shipped with this option selected.

Calibrated Internal RC

Oscillator

The calibrated internal oscillator provides a fixed 1.2 MHz (nominal) clock at 3V and

25°C. This clock may be used as the system clock. This oscillator can be calibrated by

writing the calibration byte to the OSCCAL register. When this oscillator is used as the

chip clock, the Watchdog oscillator will still be used for the Watchdog Timer and for the

reset time-out. For details on how to use the pre-programmed calibration value, see the

section “Calibration Byte” on page 46.

Crystal Oscillator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier, which

can be configured for use as an on-chip oscillator, as shown in Figure 5. Either a quartz

crystal or a ceramic resonator may be used. When the INTCAP fuse is programmed,

internal load capacitors with typical values 50 pF are connected between XTAL1/XTAL2

and ground.

Figure 5. Oscillator Connections

MAX 1 HC BUFFER

HC

C2

XTAL2

C1

XTAL1

GND

Note:

1. When using the MCU oscillator as a clock for an external device, an HC buffer should

be connected as indicated in the figure.

External Clock

To drive the device from an external clock source, XTAL2 should be left unconnected

while XTAL1 is driven as shown in Figure 6.

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Figure 6. External Clock Drive Configuration

XTAL2

XTAL1

GND

NC

EXTERNAL

OSCILLATOR

SIGNAL

External RC Oscillator

For timing insensitive applications, the external RC configuration shown in Figure 7 can

be used. For details on how to choose R and C, see Table 25 on page 56.

Figure 7. External RC Configuration

V

CC

XTAL2

XTAL1

GND

NC

R

C

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ATtiny28L/V

Register Description

Oscillator Calibration Register

– OSCCAL

Bit

7

CAL7

R/W

0

6

CAL6

R/W

0

5

CAL5

R/W

0

4

CAL4

R/W

0

3

CAL3

R/W

0

2

CAL2

R/W

0

1

CAL1

R/W

0

CAL0

R/W

0

$00

OSCCAL

Read/Write

Initial Value

• Bits 7..0 – CAL7..CAL0: Oscillator Calibration Value

Writing the calibration byte to this address will trim the internal oscillator to remove pro-

cess variation from the oscillator frequency. When OSCCAL is zero, the lowest available

frequency is chosen. Writing non-zero values to the register will increase the frequency

to the internal oscillator. Writing $FF to the register gives the highest available fre-

quency. Table 2 shows the range for OSCCAL. Note that the oscillator is intended for

calibration to 1.2 MHz, thus tuning to other values is not guaranteed. At 3V and 25^oC,

the pre-programmed calibration byte gives a frequency within 1% of the nominal

frequency.

Table 2. Internal RC Oscillator Range

OSCCAL Value

0x00

Min Frequency

0.6 MHz

Max Frequency

1.2 MHz

0x7F

0.8 MHz

1.7 MHz

0xFF

1.2 MHz

2.5 MHz

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Memories

I/O Memory

The I/O space definition of the ATtiny28 is shown in Table 3.

Table 3. ATtiny28 I/O Space

Address Hex

$3F

Name

SREG

PORTA

PACR

Function

Status Register

$1B

$1A

$19

Data Register, Port A

Port A Control Register

Input Pins, Port A

PINA

$16

PINB

Input Pins, Port B

$12

PORTD

DDRD

PIND

Data Register, Port D

$11

Data Direction Register, Port D

Input Pins, Port D

$10

$08

ACSR

MCUCS

ICR

Analog Comparator Control and Status Register

MCU Control and Status Register

Interrupt Control Register

Interrupt Flag Register

$07

$06

$05

IFR

$04

TCCR0

TCNT0

MODCR

WDTCR

OSCCAL

Timer/Counter0 Control Register

Timer/Counter0 (8-bit)

$03

$02

Modulation Control Register

Watchdog Timer Control Register

Oscillator Calibration Register

$01

$00

Note:

Reserved and unused locations are not shown in the table.

All ATtiny28 I/O and peripherals are placed in the I/O space. The I/O locations are

accessed by the IN and OUT instructions transferring data between the 32 general-pur-

pose working registers and the I/O space. I/O registers within the address range $00 -

$1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the

value of single bits can be checked by using the SBIS and SBIC instructions. Refer to

the Instruction Set section for more details.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

The I/O and peripherals control registers are explained in the following sections.

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ATtiny28L/V

Program and Data

Addressing Modes

The ATtiny28 AVR RISC microcontroller supports powerful and efficient addressing

modes. This section describes the different addressing modes supported in the

ATtiny28. In the figures, OP means the operation code part of the instruction word. To

simplify, not all figures show the exact location of the addressing bits.

Register Direct, Single

Register Rd

Figure 8. Direct Single Register Addressing

The operand is contained in register d (Rd).

Register Indirect

Figure 9. Indirect Register Addressing

REGISTERFILE

0

Z-Register

30

31

The register accessed is the one pointed to by the Z-register (R31, R30).

Register Direct, Two Registers Figure 10. Direct Register Addressing, Two Registers

Rd and Rr

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Operands are contained in register r (Rr) and d (Rd). The result is stored in register d

(Rd).

I/O Direct

Figure 11. I/O Direct Addressing

Operand address is contained in six bits of the instruction word. n is the destination or

source register address.

Relative Program Addressing, Figure 12. Relative Program Memory Addressing

RJMP and RCALL

PROGRAM MEMORY

$000

15

0

PC

+1

15

12 11

0

k

OP

$3FF

Program execution continues at address PC + k + 1. The relative address k is -2048 to

2047.

Constant Addressing Using

the LPM Instruction

Figure 13. Code Memory Constant Addressing

PROGRAM MEMORY

$000

15

1 0

Z-REGISTER

$3FF

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ATtiny28L/V

Constant byte address is specified by the Z-register contents. The 15 MSBs select word

address (0 - 1K), and LSB selects low byte if cleared (LSB = 0) or high byte if set (LSB =

1).

Memory Access and

Instruction Execution

Timing

This section describes the general access timing concepts for instruction execution and

internal memory access.

The AVR CPU is driven by the System Clock, directly generated from the external clock

crystal for the chip. No internal clock division is used.

Figure 14 shows the parallel instruction fetches and instruction executions enabled by

the Harvard architecture and the fast-access register file concept. This is the basic pipe-

lining concept to obtain up to 1 MIPS per MHz with the corresponding unique results for

functions per cost, functions per clocks and functions per power unit.

Figure 14. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

System Clock Ø

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 15 shows the internal timing concept for the register file. In a single clock cycle

an ALU operation using two register operands is executed, and the result is stored back

to the destination register.

Figure 15. Single Cycle ALU Operation

T1

T2

T3

T4

System Clock Ø

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

Flash Program Memory

The ATtiny28 contains 2K bytes of on-chip Flash memory for program storage. Since all

instructions are single 16-bit words, the Flash is organized as 1K x 16 words. The Flash

memory has an endurance of at least 1,000 write/erase cycles.

The ATtiny28 program counter is 10 bits wide, thus addressing the 1K word Flash pro-

gram memory. See “Programming the Flash” on page 47 for a detailed description of

Flash data downloading.

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Sleep Modes

To enter the sleep modes, the SE bit in MCUCS must be set (one) and a SLEEP instruc-

tion must be executed. The SM bit in the MCUCS register selects which sleep mode

(Idle or Power-down) will be activated by the SLEEP instruction. If an enabled interrupt

occurs while the MCU is in a sleep mode, the MCU awakes. The CPU is then halted for

four cycles. It executes the interrupt routine and resumes execution from the instruction

following SLEEP. The contents of the register file and I/O memory are unaltered. If a

reset occurs during sleep mode, the MCU wakes up and executes from the Reset

vector.

Idle Mode

When the SM bit is cleared (zero), the SLEEP instruction forces the MCU into the Idle

Mode, stopping the CPU but allowing Timer/Counters, Watchdog and the interrupt sys-

tem to continue operating. This enables the MCU to wake up from external triggered

interrupts as well as internal ones like Timer Overflow interrupt and Watchdog reset. If

wake-up from the Analog Comparator Interrupt is not required, the analog comparator

can be powered down by setting the ACD bit in the Analog Comparator Control and Sta-

tus register (ACSR). This will reduce power consumption in Idle Mode. Note that the

ACD bit is set by default.

Power-down Mode

When the SM bit is set (one), the SLEEP instruction forces the MCU into the Power-

down mode. In this mode, the external oscillator is stopped, while the external interrupts

and the Watchdog (if enabled) continue operating. Only an external reset, a Watchdog

reset (if enabled), or an external level interrupt can wake up the MCU.

Note that if a level-triggered interrupt is used for wake-up from Power-down mode, the

changed level must be held for some time to wake up the MCU. This makes the MCU

less sensitive to noise. The wake-up period is equal to the clock-counting part of the

reset period (see Table 5). The MCU will wake up from power-down if the input has the

required level for two Watchdog oscillator cycles. If the wake-up period is shorter than

two Watchdog oscillator cycles, the MCU will wake up if the input has the required level

for the duration of the wake-up period. If the wake-up condition disappears before the

wake-up period has expired, the MCU will wake up from power-down without executing

the corresponding interrupt. The period of the Watchdog oscillator is 2.7 µs (nominal) at

3.0V and 25°C. The frequency of the watchdog oscillator is voltage-dependent as

shown in the section “Typical Characteristics” on page 57.

When waking up from the Power-down mode, there is a delay from the wake-up condi-

tion until the wake-up becomes effective. This allows the clock to restart and become

stable after having been stopped.

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ATtiny28L/V

System Control and

Reset

Reset Sources

The ATtiny28 provides three sources of reset:

•

Power-on Reset. The MCU is reset when the supply voltage is below the Power-on

Reset threshold (V_POT).

External Reset. The MCU is reset when a low level is present on the RESET pin for

more than 50 ns.

Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and

the Watchdog is enabled.

During reset, all I/O registers are then set to their initial values and the program starts

execution from address $000. The instruction placed in address $000 must be an RJMP

(relative jump) instruction to the reset handling routine. If the program never enables an

interrupt source, the interrupt vectors are not used, and regular program code can be

placed at these locations. The circuit diagram in Figure 16 shows the reset logic. Table 4

defines the timing and electrical parameters of the reset circuitry.

Figure 16. Reset Logic

DATA BUS

MCU Control and Status

Register (MCUCS)

Power-on

VCC

Reset Circuit

S

R

Q

100 - 500K

RESET

Reset Circuit

Watchdog

Timer

CKSEL[3..0]

Delay Counters

On-chip

RC Oscillator

Full

CK

Table 4. Reset Characteristics

Symbol

Parameter

Min

1.0

0.4

Typ

Max

Unit

V

Power-on Reset Threshold Voltage (rising)

Power-on Reset Threshold Voltage (falling)

RESET Pin Threshold Voltage

1.4

0.6

1.8

0.8

(1)

V_POT

V

V_RST

0.6 V_CC

V

Note:

1. The Power-on Reset will not work unless the supply voltage has been below V_POT

(falling).

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Table 5. ATtiny28 Clock Options and Start-up Time

CKSEL3..0

1111

1110

1101

1100

1011

1010

1001

1000

0111

0110

0101

0100

0011

0010

0001

0000

Clock Source

Start-up Time at 2.7V

1K CK

External Crystal/Ceramic Resonator⁽¹⁾

External Crystal/Ceramic Resonator

External Low-frequency Crystal

External RC Oscillator

4.2 ms + 1K CK

67 ms + 1K CK

16K CK

4.2 ms + 16K CK

67 ms + 16K CK

67 ms + 1K CK

67 ms + 32K CK

6 CK

External RC Oscillator

4.2 ms + 6 CK

67 ms + 6 CK

6 CK

External RC Oscillator

Internal RC Oscillator

4.2 ms + 6 CK

67 ms + 6 CK

6 CK

Internal RC Oscillator

External Clock

4.2 ms + 6 CK

Note:

1. Due to limited number of clock cycles in the start-up period, it is recommended that

ceramic resonator be used.

This table shows the start-up times from reset. From Power-down mode, only the clock

counting part of the start-up time is used. The Watchdog oscillator is used for timing the

real-time part of the start-up time. The number WDT oscillator cycles used for each

time-out is shown in Table 6.

Table 6. Number of Watchdog Oscillator Cycles

Time-out

4.2 ms

Number of Cycles

1K

67 ms

16K

The frequency of the Watchdog oscillator is voltage-dependent, as shown in the section

“Typical Characteristics” on page 57.

The device is shipped with CKSEL = 0010.

Power-on Reset

A Power-on Reset (POR) pulse is generated by an on-chip detection circuit. The detec-

tion level is nominally 1.4V. The POR is activated whenever V_CCis below the detection

level. The POR circuit can be used to trigger the start-up reset, as well as detect a fail-

ure in supply voltage.

The Power-on Reset (POR) circuit ensures that the device is reset from power-on.

Reaching the Power-on Reset threshold voltage invokes a delay counter, which deter-

mines the delay for which the device is kept in RESET after V_CCrise. The time-out

period of the delay counter can be defined by the user through the CKSEL fuses. The

different selections for the delay period are presented in Table 5. The RESET signal is

16

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

activated again, without any delay, when the V_CCdecreases below detection level. See

Figure 17.

If the built-in start-up delay is sufficient, RESET can be connected to VCC directly or via

an external pull-up resistor. By holding the RESET pin low for a period after V_CChas

been applied, the Power-on Reset period can be extended. Refer to Figure 18 for a tim-

ing example of this.

Figure 17. MCU Start-up, RESET Tied to VCC.

V_POT

VCC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

Figure 18. MCU Start-up, RESET Controlled Externally

V_POT

VCC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

External Reset

An external reset is generated by a low level on the RESET pin. Reset pulses longer

than 50 ns will generate a reset, even if the clock is not running. Shorter pulses are not

guaranteed to generate a reset. When the applied voltage reaches the Reset Threshold

Voltage (V_RST) on its positive edge, the delay timer starts the MCU after the Time-out

period (t_TOUT) has expired.

17

1062F–AVR–07/06

Figure 19. External Reset during Operation

VCC

RESET

V_RST

t_TOUT

TIME-OUT

INTERNAL

RESET

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of 1 XTAL cycle dura-

tion. On the falling edge of this pulse, the delay timer starts counting the Time-out period

(t_TOUT). Refer to page 37 for details on operation of the Watchdog.

Figure 20. Watchdog Reset during Operation

18

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Register Description

MCU Control and Status

Register – MCUCS

The MCU Control and Status Register contains control and status bits for general MCU

functions.

Bit

7

PLUPB

R/W

0

6

–

5

SE

R/W

0

4

SM

R/W

0

3

2

–

1

0

$07

WDRF

R/W

EXTRF

R/W

PORF

R/W

MCUCS

Read/Write

Initial Value

R

0

R

0

See Bit

Desc.

See Bit Description

• Bit 7 – PLUPB: Pull-up Enable Port B

When the PLUPB bit is set (one), pull-up resistors are enabled on all Port B input pins.

When PLUPB is cleared, the pull-ups are disabled. If any of the special functions of Port

B is enabled, the corresponding pull-up(s) is disabled, independent of the value of

PLUPB.

• Bit 6 – Res: Reserved Bit

This bit is a reserved bit in the ATtiny28 and always reads as zero.

• Bit 5 – SE: Sleep Enable

The SE bit must be set (one) to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the pro-

grammer’s purpose, it is recommended to set the Sleep Enable SE bit just before the

execution of the SLEEP instruction.

• Bit 4 – SM: Sleep Mode

This bit selects between the two available sleep modes. When SM is cleared (zero), Idle

Mode is selected as sleep mode. When SM is set (one), Power-down mode is selected

as sleep mode. For details, refer to “Sleep Modes” below.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog reset occurs. The bit is cleared by a Power-on Reset, or by

writing a logical “0” to the flag.

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the ATtiny28 and always reads as zero.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an external reset occurs. The bit is cleared by a Power-on Reset, or by

writing a logical “0” to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is cleared by writing a logical “0” to the

flag.

To make use of the reset flags to identify a reset condition, the user should read and

then clear the flag bits in MCUCS as early as possible in the program. If the register is

cleared before another reset occurs, the source of the reset can be found by examining

the reset flags.

19

1062F–AVR–07/06

Interrupts

Reset and Interrupt

The ATtiny28 provides five different interrupt sources. These interrupts and the reset

vector each have a separate program vector in the program memory space. All the inter-

rupts are assigned to individual enable bits. In order to enable the interrupt, both the

individual enable bit and the I-bit in the status register (SREG) must be set to one.

The lowest addresses in the program memory space are automatically defined as the

Reset and Interrupt vectors. The complete list of vectors is shown in Table 7. The list

also determines the priority levels of the different interrupts. The lower the address, the

higher the priority level. RESET has the highest priority, and next is INT0 – the External

Interrupt Request 0.

Table 7. Reset and Interrupt Vectors

Vector

No.

Program

Address

Source

Interrupt Definition

Hardware Pin, Power-on Reset and

Watchdog Reset

1

$000

RESET

2

3

4

$001

$002

$003

INT0

External Interrupt Request 0

External Interrupt Request 1

Low-level Input on Port B

INT1

Input Pins

TIMER0,

OVF0

5

6

$004

$005

Timer/Counter0 Overflow

Analog Comparator

ANA_COMP

The most typical and general program setup for the Reset and Interrupt vector

addresses are:

Address Labels

Code

rjmp

Comments

$000

$001

$002

$003

$004

$005

;

RESET

; Reset handler

EXT_INT0

EXT_INT1

LOW_LEVEL

TIM0_OVF

ANA_COMP

; IRQ0 handler

; IRQ1 handler

; Low level input handler

; Timer0 overflow handle

; Analog Comparator handle

$006

…

MAIN:

…

<instr> xxx

; Main program start

…

Interrupt Handling

The ATtiny28 has one 8-bit Interrupt Control Register (ICR).

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared (zero) and all inter-

rupts are disabled. The user software can set (one) the I-bit to enable nested interrupts.

The I-bit is set (one) when a Return from Interrupt instruction (RETI) is executed.

When the program counter is vectored to the actual interrupt vector in order to execute

the interrupt handling routine, hardware clears the corresponding flag that generated the

interrupt. Some of the interrupt flags can also be cleared by writing a logical “1” to the

flag bit position(s) to be cleared.

20

ATtiny28L/V

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ATtiny28L/V

If an interrupt condition occurs when the corresponding interrupt enable bit is cleared

(zero), the interrupt flag will be set and remembered until the interrupt is enabled or the

flag is cleared by software.

If one or more interrupt conditions occur when the global interrupt enable bit is cleared

(zero), the corresponding interrupt flag(s) will be set and remembered until the global

interrupt enable bit is set (one), and will be executed by order of priority.

Note that external level interrupt does not have a flag and will only be remembered for

as long as the interrupt condition is active.

Note that the status register is not automatically stored when entering an interrupt rou-

tine and restored when returning from an interrupt routine. This must be handled by

software.

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles

minimum. After four clock cycles the program vector address for the actual interrupt

handling routine is executed. During this 4-clock-cycle period, the program counter (10

bits) is pushed onto the stack. The vector is normally a relative jump to the interrupt rou-

tine, and this jump takes two clock cycles. If an interrupt occurs during execution of a

multi-cycle instruction, this instruction is completed before the interrupt is served. If an

interrupt occurs when the MCU is in sleep mode, the interrupt execution response time

is increased by four clock cycles.

A return from an interrupt handling routine takes four clock cycles. During these four

clock cycles, the program counter (10 bits) is popped back from the stack, and the I-flag

in SREG is set. When AVR exits from an interrupt, it will always return to the main pro-

gram and execute one more instruction before any pending interrupt is served.

External Interrupt

The external interrupt is triggered by the INT pins. Observe that, if enabled, the interrupt

will trigger even if the INT pin is configured as an output. This feature provides a way of

generating a software interrupt. The external interrupt can be triggered by a falling or ris-

ing edge, a pin change or a low level. This is set up as indicated in the specification for

the Interrupt Control Register (ICR). When the external interrupt is enabled and is con-

figured as level-triggered, the interrupt will trigger as long as the pin is held low.

The external interrupt is set up as described in the specification for the Interrupt Control

Register (ICR).

Low-level Input Interrupt

The low-level interrupt is triggered by setting any of the Port B pins low. However, if any

Port B pins are used for other special features, these pins will not trigger the interrupt.

For example, if the analog comparator is enabled, a low level on PB0 or PB1 will not

cause an interrupt. This is also the case for the special functions T0, INT0 and INT1. If

low-level interrupt is selected, the low level must be held until the completion of the cur-

rently executing instruction to generate an interrupt. When this interrupt is enabled, the

interrupt will trigger as long as any of the Port B pins are held low.

21

1062F–AVR–07/06

Register Description

Interrupt Control Register –

ICR

Bit

7

6

5

4

TOIE0

R/W

0

3

ISC11

R/W

0

2

ISC10

R/W

0

1

ISC01

R/W

0

ISC00

R/W

0

$06

INT1

R/W

0

INT0

R/W

0

LLIE

R/W

0

ICR

Read/Write

Initial Value

• Bit 7 – INT1: External Interrupt Request 1 Enable

When the INT1 bit is set (one) and I-bit in the Status Register (SREG) is set (one), the

external pin interrupt 1 is enabled. The interrupt Sense Control1 bits 1/0 (ISC11 and

ISC10) define whether the external interrupt is activated on rising or falling edge, on pin

change or low level of the INT1 pin. The corresponding interrupt of External Interrupt

Request 1 is executed from program memory address $002. See also “External

Interrupt”.

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one),

the external pin interrupt 0 is enabled. The interrupt Sense Control0 bits 1/0 (ISC01 and

ISC00) define whether the external interrupt is activated on rising or falling edge, on pin

change or low level of the INT0 pin. The corresponding interrupt of External Interrupt

Request 0 is executed from program memory address $001. See also “External

Interrupt”.

• Bit 5 – LLIE: Low-level Input Interrupt Enable

When the LLIE is set (one) and the I-bit in the status register (SREG) is set (one), the

interrupt on low-level input is activated. Any of the Port B pins pulled low will then cause

an interrupt. However, if any Port B pins are used for other special features, these pins

will not trigger the interrupt. The corresponding interrupt of Low-level Input Interrupt

Request is executed from program memory address $003. See also “Low-level Input

Interrupt”.

• Bit 4 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter0 Overflow Interrupt is enabled. The corresponding interrupt (at vector

$004) is executed if an overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set

in the Interrupt Flag Register (IFR).

• Bits 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0

The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the

corresponding interrupt enable are set. The level and edges on the external INT1 pin

that activate the interrupt are defined in Table 8.

22

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Table 8. Interrupt 1 Sense Control

ISC11

ISC10

Description

0

1

0

1

0

1

The low level of INT1 generates an interrupt request.

Any change on INT1 generates an interrupt request.

The falling edge of INT1 generates an interrupt request.

The rising edge of INT1 generates an interrupt request.

Note:

When changing the ISC11/ISC10 bits, INT1 must be disabled by clearing its Interrupt

Enable bit. Otherwise, an interrupt can occur when the bits are changed.

• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the

corresponding interrupt enable are set. The level and edges on the external INT0 pin

that activate the interrupt are defined in Table 9.

Table 9. Interrupt 0 Sense Control

ISC01

ISC00

Description

0

1

0

1

0

1

The low level of INT0 generates an interrupt request.

Any change on INT0 generates an interrupt request.

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

Note:

When changing the ISC01/ISC00 bits, INT0 must be disabled by clearing its Interrupt

Enable bit. Otherwise, an interrupt can occur when the bits are changed.

The value on the INT pins are sampled before detecting edges. If edge interrupt is

selected, pulses that last longer than one CPU clock period will generate an interrupt.

Shorter pulses are not guaranteed to generate an interrupt. If low-level interrupt is

selected, the low level must be held until the completion of the currently executing

instruction to generate an interrupt. If enabled, a level-triggered interrupt will generate

an interrupt request as long as the pin is held low.

Interrupt Flag Register – IFR

Bit

7

INTF1

R/W

0

6

INTF0

R/W

0

5

–

4

TOV0

R/W

0

3

–

2

–

1

–

0

–

$05

IFR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

• Bit 7 – INTF1: External Interrupt Flag1

When an edge on the INT1 pin triggers an interrupt request, the corresponding interrupt

flag, INTF1 becomes set (one). If the I-bit in SREG and the corresponding interrupt

enable bit, INT1 in GIMSK is set (one), the MCU will jump to the interrupt vector. The

flag is cleared when the interrupt routine is executed. Alternatively, the flag can be

cleared by writing a logical “1” to it. This flag is always cleared when INT1 is configured

as level interrupt.

• Bit 6 – INTF0: External Interrupt Flag0

When an edge on the INT0 pin triggers an interrupt request, the corresponding interrupt

flag, INTF0 becomes set (one). If the I-bit in SREG and the corresponding interrupt

23

1062F–AVR–07/06

enable bit, INT0 in GIMSK is set (one), the MCU will jump to the interrupt vector. The

flag is cleared when the interrupt routine is executed. Alternatively, the flag can be

cleared by writing a logical “1” to it. This flag is always cleared when INT0 is configured

as level interrupt.

• Bit 5 – Res: Reserved Bit

This bit is a reserved bit in the ATtiny28 and always reads as zero.

• Bit 4 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared

by hardware when executing the corresponding interrupt handling vector. TOV0 is

cleared by writing a logical “1” to the flag. When the SREG I-bit, TOIE0 in ICR and TOV0

are set (one), the Timer/Counter0 Overflow interrupt is executed.

• Bit 3..0 - Res: Reserved Bits

These bits are reserved bits in the ATtiny28 and always read as zero.

Note:

1. One should not try to use the SBI (Set Bit in I/O Register) instruction to clear individ-

ual flags in the Register. This will result in clearing all the flags in the register,

because the register is first read, then modified and finally written, thus writing ones

to all set flags. Using the CBI (Clear Bit in I/O Register) instruction on IFR will result in

clearing all bits apart from the specified bit.

24

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

I/O Ports

All AVR ports have true read-modify-write functionality when used as general digital I/O

ports. This means that the direction of one port pin can be changed without unintention-

ally changing the direction of any other pin with the SBI and CBI instructions. The same

applies for changing drive value (if configured as output) or enabling/disabling of pull-up

resistors (if configured as input).

Port A

Port A is a 4-bit I/O port. PA3, PA1, and PA0 are bi-directional, while PA2 is output-only.

Before entering Power-down, see “Sleep Modes” on page 14, PORTA2 bit in PORTA

register should be set.

Three I/O memory address locations are allocated for Port A, one each for the Data

Register – PORTA, $1B, Port A Control Register – PACR, $1A and the Port A Input Pins

– PINA, $19. The Port A Input Pins address is read-only, while the Data Register and

the Control Register are read/write. Compared to other output ports, the Port A output is

delayed one extra clock cycle.

Port pins PA0, PA1 and PA3 have individually selectable pull-up resistors. When pins

PA0, PA1 or PA3 are used as inputs and are externally pulled low, they will source cur-

rent if the internal pull-up resistors are activated. PA2 is output-only. The PA2 output

buffer can sink 25 mA and thus drive a high-current LED directly. This output can also

be modulated (see “Hardware Modulator” on page 39 for details).

Port A as General Digital I/O

PA3, PA1 and PA0 are general I/O pins. The DDAn (n: 3,1,0) bits in PACR select the

direction of these pins. If DDAn is set (one), PAn is configured as an output pin. If DDAn

is cleared (zero), PAn is configured as an input pin. If PORTAn is set (one) when the pin

is configured as an input pin, the MOS pull-up resistor is activated. To switch the pull-up

resistor off, the PORTAn bit has to be cleared (zero) or the pin has to be configured as

an output pin. The effects of the DDAn and PORTAn bits on PA3, PA1 and PA0 are

shown in Table 10. The port pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Table 10. DDAn Effects on Port A Pins

DDAn

PORTAn

I/O

Pull-up

No

Comment

0

1

0

1

0

1

Input

Tri-state (high-Z)

Input

Yes

PAn will source current if ext. pulled low.

Push-pull Zero Output

Push-pull One Output

Output

No

Note:

n: 3,1,0, pin number

Alternate Function of PA2

PA2 is the built-in, high-current LED driver and it is always an output pin. The output sig-

nal can be modulated with a software programmable frequency. See “Hardware

Modulator” on page 39 for further details.

25

1062F–AVR–07/06

Port A Schematics

Note that all port pins are synchronized. The synchronization latches are, however, not

shown in the figures.

Figure 21. Port A Schematic Diagram (Pins PA0, PA1 and PA3)

RD

MOS

PULL-

UP

RESET

R

Q

D

DDAn

C

WD

RESET

R

Q

D

Q

D

PAn

PORTAn

C

RL

WP

RP

WP: WRITE PORTA

WD: WRITE DDRA

RL: READ PORTA LATCH

RP: READ PORTA PIN

RD: READ DDRA

n: 0,1,3

Figure 22. Port A Schematic Diagram (Pin PA2)

RESET

R

Q

D

1

HARDWARE

MODULATOR

PORTA2

PA2

C

0

WP

RL

OOM01 OOM00

DISABLE

TOGGLE

0

1

0

1

0

1

CLEAR

SET

RESET

WP: WRITE PORTA

R

RL: READ PORTA LATCH

Q

D

Note: Both the flip-flops shown

have reset value one (set).

C

TOV0

FOV0

26

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Port B

Port B is an 8-bit input port.

One I/O address location is allocated for the Port B Input Pins – PINB, $16. The Port B

Input Pins address is read-only.

All port pins have pull-ups that can be switched on for all Port B pins simultaneously. If

any of the Port B special functions is enabled, the corresponding pull-up(s) is disabled.

When pins PB0 to PB7 are externally pulled low, they will source current (I_IL) if the inter-

nal pull-up resistors are activated.

The Port B pins with alternate functions are shown in Table 11.

Table 11. Port B Pin Alternate Functions

Port Pin

PB0

Alternate Functions

AIN0 (Analog Comparator Positive Input)

AIN1 (Analog Comparator Negative Input)

T0 (Timer/Counter 0 External Counter Input)

INT0 (External Interrupt 0 Input)

PB1

PB2

PB3

PB4

INT1 (External Interrupt 1 Input)

Port B as General Digital Input All eight pins in Port B have equal functionality when used as digital input pins.

PBn, general input pin: To switch the pull-up resistors on, the PLUPB bit in the MCUCS

register must be set (one). This bit controls the pull-up on all Port B pins. To turn the

pull-ups off, this bit has to be cleared (zero). Note that if any Port B pins are used for

alternate functions, the pull-up on the corresponding pins are disabled. The port pins are

tri-stated when a reset condition becomes active, even if the clock is not running.

Alternate Functions of Port B All Port B pins are connected to a low-level detector that can trigger the low-level input

interrupt. See “Low-level Input Interrupt” on page 21 for details. In addition, Port B has

the following alternate functions:

• INT1 – Port B, Bit 4

INT1, External Interrupt source 1. The PB4 pin can serve as an external interrupt source

to the MCU. See the interrupt description for details on how to enable and configure this

interrupt. If the interrupt is enabled, the pull-up resistor on PB4 is disabled and PB4 will

not give low-level interrupts.

• INT0 – Port B, Bit 3

INT0, External Interrupt source 0. The PB3 pin can serve as an external interrupt source

to the MCU. See the interrupt description for details on how to enable and configure this

interrupt. If the interrupt is enabled, the pull-up resistor on PB3 is disabled and PB3 will

not give low-level interrupts.

• T0 – Port B, Bit 2

T0, Timer/Counter0 Counter source. See the timer description for further details. If T0 is

used as the counter source, the pull-up resistor on PB2 is disabled and PB2 will not give

low-level interrupts.

27

1062F–AVR–07/06

• AIN1 – Port B, Bit 1

AIN1, Analog Comparator Negative input. When the on-chip analog comparator is

enabled, this pin also serves as the negative input of the comparator. If the analog com-

parator is enabled, the pull-up resistors on PB1 and PB0 are disabled and these pins will

not give low-level interrupts.

• AIN0 – Port B, Bit 0

AIN0, Analog Comparator Positive input. When the on-chip analog comparator is

enabled, this pin also serves as the positive input of the comparator. If the analog com-

parator is enabled, the pull-up resistors on PB1 and PB0 are disabled and these pins will

not give low-level interrupts.

Port B Schematics

Note that all port pins are synchronized. The synchronization latches are, however, not

shown in the figures.

Figure 23. Port B Schematic Diagram (Pins PB0 and PB1)

PULL-UP PORT B

MOS

PULL-

COMPARATOR DISABLE

UP

PWRDN

RP

PBn

TO LOW-LEVEL DETECTOR

TO COMPARATOR

AINn

RP: READ PORTB PIN

n

: 0, 1

28

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Figure 24. Port B Schematic Diagram (Pin PB2)

PULL-UP PORT B

MOS

PULL-

UP

RP

PB2

TO LOW-LEVEL DETECTOR

TIMER0 CLOCK

SOURCE MUX

SENSE CONTROL

CS02 CS01 CS00

RP: READ PORTB PIN

Figure 25. PORT B Schematic Diagram (Pins PB3 and PB4)

PULL-UP PORT B

INTm ENABLE

MOS

PULL-

UP

RP

PBn

TO LOW-LEVEL DETECTOR

INTm

SENSE CONTROL

ISCm1

ISCm0

RP: READ PORTB PIN

n

: 3, 4

m : 0, 1

29

1062F–AVR–07/06

Figure 26. PORT B Schematic Diagram (Pins PB7 - PB5)

MOS

PULL-

UP

PULL-UP PORT B

RP

PBn

TO LOW-LEVEL DETECTOR

RP: READ PORT B PIN

n: 5 - 7

Port D

Port D is an 8-bit bi-directional I/O port with internal pull-up resistors.

Three I/O memory address locations are allocated for Port D, one each for the Data

Register – PORTD, $12, Data Direction Register – DDRD, $11 and the Port D Input Pins

– PIND, $10. The Port D Input Pins address is read-only, while the Data Register and

the Data Direction Register are read/write.

The Port D output buffers can sink 10 mA. As inputs, Port D pins that are externally

pulled low will source current if the pull-up resistors are activated.

Port D as General Digital I/O

All eight pins in Port D have equal functionality when used as digital I/O pins.

PDn, general I/O pin: The DDDn bit in the DDRD register selects the direction of this pin.

If DDDn is set (one), PDn is configured as an output pin. If DDDn is cleared (zero), PDn

is configured as an input pin. If PDn is set (one) when configured as an input pin, the

MOS pull-up resistor is activated. To switch the pull-up resistor off, the PDn has to be

cleared (zero), or the pin has to be configured as an output pin. The port pins are tri-

stated when a reset condition becomes active, even if the clock is not running.

Table 12. DDDn Bits on Port D Pins

DDDn

PORTDn

I/O

Pull-up

No

Comment

0

1

0

1

0

1

Input

Tri-state (high-Z)

Input

Yes

PDn will source current if ext. pulled low

Push-pull Zero Output

Push-pull One Output

Output

No

NO

Note:

n: 7,6,...,0, pin number

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ATtiny28L/V

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ATtiny28L/V

Figure 27. Port D Schematic Diagram (Pins PD7 - PD0)

RD

MOS

PULL-

UP

RESET

R

DDDn

C

Q

D

WD

RESET

R

Q

D

PDn

PORTDn

C

RL

WP

RP

WP: WRITE PORTD

WD: WRITE DDRD

RL: READ PORTD LATCH

RP: READ PORTD PIN

RD: READ DDRD

n

:

0 - 7

31

1062F–AVR–07/06

Register Description

Port A Data Register – PORTA

Bit

7

–

6

–

5

–

4

–

3

PORTA3

R/W

0

2

PORTA2

R/W

1

PORTA1

R/W

0

PORTA0

R/W

0

PORTA

$1B

Read/Write

Initial Value

R

0

R

0

R

0

R

0

Port A Control Register –

PACR

Bit

7

–

6

–

5

–

4

–

3

DDA3

R/W

0

2

PA2HC

R/W

0

1

DDA1

R/W

0

DDA0

R/W

0

$1A

PACR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny28 and always read as zero.

• Bit 3 – DDA3: Data Direction PA3

When DDA3 is set (one), the corresponding pin is an output pin. Otherwise, it is an input

pin.

• Bit 2 – PA2HC: PORTA2 High Current Enable

When the PA2HC bit is set (one), an additional driver at the output pin PA2 is enabled.

This makes it possible to sink 25 mA at V_CC= 1.8V (V_OL= 0.8V). When the PA2HC bit is

cleared (zero), PA2 can sink 15 mA at V_CC= 1.8V (V_OL= 0.8V).

• Bits 1, 0 – DDA1, DDA0: Data Direction PA1 and PA0

When DDAn is set (one), the corresponding pin is an output pin. Otherwise, it is an input

pin.

Port A Input Pins Address –

PINA

Bit

7

–

6

–

5

–

4

–

3

PINA3

R

2

–

1

PINA1

R

0

PINA0

R

$19

PINA

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

N/A

The Port A Input Pins address (PINA) is not a register; this address enables access to

the physical value on each Port A pin. When reading PORTA, the Port A Data Latch is

read and when reading PINA, the logical values present on the pins are read.

Port B Input Pins Address –

PINB

Bit

7

PINB7

R

6

PINB6

R

5

PINB5

R

4

PINB4

R

3

PINB3

R

2

PINB2

R

1

PINB1

R

0

PINB0

R

$16

PINB

Read/Write

Initial Value

N/A

The Port B Input Pins address (PINB) is not a register; this address enables access to

the physical value on each Port B pin. When reading PINB, the logical values present on

the pins are read.

32

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Port D Data Register – PORTD

Bit

7

PORTD7

R/W

0

6

PORTD6

R/W

0

5

PORTD5

R/W

0

4

PORTD4

R/W

0

3

PORTD3

R/W

0

2

PORTD2

R/W

0

1

PORTD1

R/W

0

PORTD0

R/W

0

PORTD

DDRD

PIND

$12

Read/Write

Initial Value

Port D Data Direction Register

– DDRD

Bit

7

DDD7

R/W

0

6

DDD6

R/W

0

5

DDD5

R/W

0

4

DDD4

R/W

0

3

DDD3

R/W

0

2

DDD2

R/W

0

1

DDD1

R/W

0

DDD0

R/W

0

$11

Read/Write

Initial Value

Port D Input Pins Address –

PIND

Bit

7

PIND7

R

6

PIND6

R

5

PIND5

R

4

PIND4

R

3

PIND3

R

2

PIND2

R

1

PIND1

R

0

PIND0

R

$10

Read/Write

Initial Value

N/A

The Port D Input Pins Address (PIND) is not a register; this address enables access to

the physical value on each Port D pin. When reading PORTD, the Port D Data Latch is

read and when reading PIND, the logical values present on the pins are read.

33

1062F–AVR–07/06

Timer/Counter0

The ATtiny28 provides one general-purpose 8-bit Timer/Counter – Timer/Counter0.

Timer/Counter0 has prescaling selection from the 10-bit prescaling timer. The

Timer/Counter0 can either be used as a timer with an internal clock time base or as a

counter with an external pin connection that triggers the counting.

Timer/Counter Prescaler Figure 28 shows the Timer/Counter prescaler.

Figure 28. Timer/Counter0 Prescaler

CK

10-BIT T/C PRESCALER

COUNT ENABLE

FROM MODULATOR

T0

0

CS00

CS01

CS02

TIMER/COUNTER0 CLOCK SOURCE

TCK0

The four different prescaled selections are: the hardware modulator period, CK/64,

CK/256 and CK/1028, where CK is the oscillator clock. CK, external source and stop

can also be selected as clock sources.

Figure 29 shows the block diagram for Timer/Counter0.

Figure 29. Timer/Counter0 Block Diagram

T/C0 OVER-

FLOW IRQ

INTERRUPT FLAG

REGISTER (IFR)

T/C0 CONTROL

REGISTER (TCCR0)

INTERRUPT CONTROL

REGISTER (ICR)

CONTROL

LOGIC

TIMER/COUNTER0

(TCNT0)

T0

34

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

The 8-bit Timer/Counter0 can select clock source from CK, prescaled CK or an external

pin. In addition, it can be stopped as described in the specification for the

Timer/Counter0 Control Register (TCCR0). The overflow status flag is found in the Inter-

rupt Flag Register (IFR). Control signals are found in the Timer/Counter0 Control

Register (TCCR0). The interrupt enable/disable setting for Timer/Counter0 is found in

the Interrupt Control Register (ICR).

When Timer/Counter0 is externally clocked, the external signal is synchronized with the

oscillator frequency of the CPU. To ensure proper sampling of the external clock, the

minimum time between two external clock transitions must be at least one internal CPU

clock period. The external clock signal is sampled on the rising edge of the internal CPU

clock.

The 8-bit Timer/Counter0 features both a high-resolution and a high-accuracy usage

with the lower prescaling opportunities. Similarly, the high prescaling opportunities make

the Timer/Counter0 useful for lower speed functions or exact timing functions with infre-

quent actions.

Register Description

Timer/Counter0 Control

Register – TCCR0

Bit

7

FOV0

R/W

0

6

–

5

–

4

OOM01

R/W

0

3

OOM00

R/W

0

2

CS02

R/W

0

1

CS01

R/W

0

CS00

R/W

0

$04

TCCR0

Read/Write

Initial Value

R

0

R

0

• Bit 7 – FOV0: Force Overflow

Writing a logical “1” to this bit forces a change on the overflow output pin PA2 according

to the values already set in OOM01 and OOM00. If the OOM01 and OOM00 bits are

written in the same cycle as FOV0, the new settings will not take effect until the next

overflow or forced overflow occurs. The Force Overflow bit can be used to change the

output pin without waiting for an overflow in the timer. The automatic action programmed

in OOM01 and OOM00 happens as if an overflow had occurred, but no interrupt is gen-

erated. The FOV0 bit will always read as zero, and writing a zero to this bit has no effect.

• Bits 6, 5 – Res: Reserved Bits

These bits are reserved bits in the ATtiny28 and always read as zero.

• Bits 4, 3 – OOM01, OOM00: Overflow Output Mode, Bits 1 and 0

The OOM01 and OOM00 control bits determine any output pin action following an over-

flow or a forced overflow in Timer/Counter0. Any output pin actions affect pin PA2. The

control configuration is shown in Table 13.

Table 13. Overflow Output Mode Select

OOM01

OOM00

Description

0

1

0

1

0

1

Timer/Counter0 disconnected from output pin PA2

Toggle the PA2 output line.

Clear the PA2 output line to zero.

Set the PA2 output line to one.

35

1062F–AVR–07/06

• Bits 2, 1, 0 – CS02, CS01, CS00: Clock Select0, Bits 2, 1 and 0

The Clock Select0 bits 2, 1 and 0 define the prescaling source of Timer/Counter0.

Table 14. Clock 0 Prescale Select

CS02

CS01

CS00

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

Stop, the Timer/Counter0 is stopped.

CK

Modulator Period

CK/64

CK/256

CK/1024

External Pin T0, falling edge

External Pin T0, rising edge

The Stop condition provides a Timer Enable/Disable function. The CK down divided

modes are scaled directly from the CK oscillator clock. If the external pin modes are

used for Timer/Counter0, transitions on PB2/(T0) will clock the counter even if the pin is

configured as an output. This feature can give the user software control of the counting.

Timer Counter 0 – TCNT0

Bit

7

6

5

4

3

2

1

0

$03

MSB

R/W

0

LSB

R/W

0

TCNT0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter0 is realized as an up-counter with read and write access. If the

Timer/Counter0 is written and a clock source is present, the Timer/Counter0 continues

counting in the timer clock cycle following the write operation.

36

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Watchdog Timer

The Watchdog Timer is clocked from a separate on-chip oscillator. By controlling the

Watchdog Timer prescaler, the Watchdog reset interval can be adjusted as shown in

Table 15. See characterization data for typical values at other V_CClevels. The WDR

(Watchdog Reset) instruction resets the Watchdog Timer. Eight different clock cycle

periods can be selected to determine the reset period. If the reset period expires without

another Watchdog reset, the ATtiny28 resets and executes from the reset vector. For

timing details on the Watchdog reset, refer to page 18.

To prevent unintentional disabling of the Watchdog, a special turn-off sequence must be

followed when the Watchdog is disabled. Refer to the description of the Watchdog Timer

Control Register for details.

Figure 30. Watchdog Timer

Oscillator

1 MHz at V_CC= 5V

350 kHz at V_CC= 3V

110 kHz at V_CC= 2V

Register Description

Watchdog Timer Control

Register – WDTCR

Bit

7

–

6

–

5

–

4

WDTOE

R/W

0

3

WDE

R/W

0

2

WDP2

R/W

0

1

WDP1

R/W

0

WDP0

R/W

0

$01

WDTCR

Read/Write

Initial Value

R

0

R

0

R

0

• Bits 7..5 - Res: Reserved Bits

These bits are reserved bits in the ATtiny28 and will always read as zero.

• Bit 4 – WDTOE: Watchdog Turn-off Enable

This bit must be set (one) when the WDE bit is cleared. Otherwise, the Watchdog will

not be disabled. Once set, hardware will clear this bit to zero after four clock cycles.

Refer to the description of the WDE bit for a Watchdog disable procedure.

• Bit 3 – WDE: Watchdog Enable

When the WDE is set (one), the Watchdog Timer is enabled and if the WDE is cleared

(zero), the Watchdog Timer function is disabled. WDE can only be cleared if the

WDTOE bit is set (one). To disable an enabled Watchdog Timer, the following proce-

dure must be followed:

37

1062F–AVR–07/06

1. In the same operation, write a logical “1” to WDTOE and WDE. A logical “1” must

be written to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logical “0” to WDE. This disables the

Watchdog.

• Bits 2..0 – WDP2, WDP1, WDP0: Watchdog Timer Prescaler 2, 1 and 0

The WDP2, WDP1 and WDP0 bits determine the Watchdog Timer prescaling when the

Watchdog Timer is enabled. The different prescaling values and their corresponding

time-out periods are shown in Table 15.

Table 15. Watchdog Timer Prescale Select

Number of WDT

Oscillator

Typical

Time-out at

Typical

Time-out at

Typical

Time-out at

WDP2 WDP1 WDP0 Cycles

V

_CC= 2.0V

V

_CC= 3.0V

V_CC= 5.0V

0

1

0

1

0

1

0

1

0

1

0

1

0

1

16K cycles

0.15 s

0.30 s

0.60 s

1.2 s

2.4 s

4.8 s

9.6 s

19 s

47 ms

94 ms

0.19 s

0.38 s

0.75 s

1.5 s

15 ms

30 ms

60 ms

0.12 s

0.24 s

0.49 s

0.97 s

1.9 s

32K cycles

64K cycles

128K cycles

256K cycles

512K cycles

1,024K cycles

2,048K cycles

3.0 s

1

6.0 s

Note:

The frequency of the Watchdog oscillator is voltage-dependent, as shown in the section

“Typical Characteristics” on page 57.

The WDR (Watchdog Reset) instruction should always be executed before the Watchdog

Timer is enabled. This ensures that the reset period will be in accordance with the

Watchdog Timer prescale settings. If the Watchdog Timer is enabled without reset, the

Watchdog Timer may not start counting from zero.

38

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Hardware Modulator

ATtiny28 features a built-in hardware modulator connected to a high-current output pad,

PA2. The hardware modulator generates a configurable pulse train. The on-time of a

pulse can be set to a number of chip clock cycles. This is done by configuring the Modu-

lation Control Register (MODCR).

PA2 is the built-in, high-current LED driver and it is always an output pin. The output

buffer can sink 25 mA at V_CC= 2.0V. When MCONF is zero, modulation is switched off

and the pin acts as a normal high-current output pin. The following truth table shows the

effect of various PORTA2 and MCONF settings.

Table 16. PA2 Output

PORTA2

MCONF

PA2 Output

0

1

0

1 - 7

X

Modulated

1

The modulation period is available as a prescale to Timer/Counter0 and thus, this timer

should be used to time the length of each burst. If the number of pulses to be sent is N,

the number 255 - N should be loaded to the timer. When an overflow occurs, the trans-

mission is complete.The OOM01 and OOM00 bits in TCCR0 can be configured to

automatically change the value on PA2 when a Timer/Counter0 overflow occurs. See

“Timer/Counter0” on page 34 for details on how to configure the OOM01 and OOM00

bits.

The modulation period is available as a prescale even when PORTA2 is high and mod-

ulation is stopped. Thus, this prescale can also be used to time the intervals between

bursts.

To get a glitch-free output, the user should first configure the MODCR register to enable

modulation. There are two ways to start the modulation:

1. Clear the PORTA2 bit in Port A Data Register (PORTA).

2. Configure OOM00 and OOM01 bits in the Timer/Counter0 Control Register

(TCCR0) to clear PA2 on the next overflow. Either an overflow or a forced over-

flow can then be used to start modulation.

The PA2 output will then be set low at the start of the next cycle. To stop the modulated

output, the user should set the PORTA2 bit or configure OOM00 and OOM01 to set PA2

on the next overflow. If the MODCR register is changed during modulation, the changed

value will take effect at the start of the next cycle, producing a glitch-free output. See

Figure 31 below and Figure 22 on page 26.

39

1062F–AVR–07/06

Figure 31. The Hardware Modulator

RM

8

/

5

3

/

COUNT ENABLE

3

TO TIMER/COUNTER0

MODULATOR

STATE

MACHINE

3

/

WM

FROM

DISABLE

MODUALTOR

PORTA2

ENABLE SETTING

WM: WRITE MODCR

RM: READ MODCR

PA2

0

1

D

Q

Figure 32 to Figure 35 show examples on output from the Modulator. Figure 32 also

shows the timing for the enable setting signal and for the count enable signal to

Timer/Counter0.

Figure 32. Modulation with ONTIM = 3, MCONF = 010.

CLK

PA2

ENABLE

SETTING

COUNT

ENABLE

Note:

1. Clock frequency: 455 kHz; modulation frequency: 38 kHz; duty-cycle: 33%

Figure 33. Modulation with ONTIM = 5, MCONF = 001

CLK

PA2

Note:

Clock frequency: 455 kHz; modulation frequency: 38 kHz; duty-cycle: 50%

40

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Figure 34. Modulation with ONTIM = 1, MCONF = 011

CLK

PA2

Note:

Clock frequency: 3.64 MHz; modulation frequency: 455 kHz; duty-cycle: 25%

Figure 35. Modulation with ONTIM = 3, MCONF = 001

CLK

PA2

Note:

Clock frequency: 3.64 MHz; modulation frequency: 455 kHz; duty-cycle: 50%

Table 17. Some Common Modulator Configurations

Crystal/Resonator Carrier

% Error in

Frequency

ONTIM

Value

MCONF

Value

Frequency

Duty-cycle

25%

455 kHz

38 kHz

455 kHz

0.2

1.2

1.1

1.2

1.1

2.0

1.2

0.0

9.9

0.0

1.3

9.9

2

3

011

010

001

100

101

001

011

010

001

011

001

011

111

001

011

001

011

001

011

455 kHz

33%

455 kHz

50%

5

455 kHz

67%

3

455 kHz

75%

2

1 MHz

50%

12

11

15

23

12

25

31

21

25

X

1.8432 MHz

2 MHz

25%

33%

50%

25%

2 MHz

50%

2.4576 MHz

3.2768 MHz

4 MHz

50%

25%

455 kHz

approx. 50%

50%

1 MHz

0

1.82 MHz

1.8432 MHz

2 MHz

25%

0

50%

1

25%

0

50%

1

25%

0

41

1062F–AVR–07/06

Table 17. Some Common Modulator Configurations (Continued)

Crystal/Resonator Carrier

% Error in

Frequency

ONTIM

Value

MCONF

Value

Frequency

Duty-cycle

50%

2 MHz

455 kHz

9.9

10.0

0.0

1

2

1

3

1

3

1

3

001

010

001

011

001

011

001

011

001

2.4576 MHz

3.2768 MHz

3.64 MHz

4 MHz

33%

50%

25%

50%

25%

0.0

50%

9.9

25%

4 MHz

9.9

50%

42

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Register Description

Modulation Control Register –

MODCR

Bit

7

ONTIM4

R/W

0

6

ONTIM3

R/W

0

5

ONTIM2

R/W

0

4

ONTIM1

R/W

0

3

ONTIM0

R/W

0

2

MCONF2

R/W

1

MCONF1

R/W

0

MCONF0

R/W

MODCR

$02

Read/Write

Initial Value

0

• Bits 7..3 – ONTIM4..0: Modulation On-time

This 5-bit value +1 determines the number of clock cycles the output pin PA2 is active

(low).

• Bits 2..0 – MCONF2..0: Modulation Configuration Bits 2, 1 and 0

These three bits determine the relationship between the on- and off-times of the modu-

lator, and thereby the duty-cycle. The various settings are shown in Table 18. The

minimum and maximum modulation period is also shown in the table. The minimum

modulation period is obtained by setting ONTIM to zero, while the maximum period is

obtained by setting ONTIM to 31. The configuration values for some common oscillator

and carrier frequencies are listed in Table 17. The relationship between oscillator fre-

quency and carrier frequency is:

fosc

fcarrier = -----------------------------------------------------

(On-time + Off-time)

If the MCONF register is set to 111, the carrier frequency will be equal to the oscillator

frequency.

Table 18. MCONF2..0 Effect on Duty-cycle and Modulation Period

MCONF2..0

000

On-time

X

Off-time

X

Duty-cycle

100%

Min Period

X

Max Period

X

Comment

Unmodulated output

001

ONTIM+1

50%

2 CK

64 CK

96 CK

128 CK

96 CK

128 CK

010

2 x (ONTIM+1) 33%

3 x (ONTIM+1) 25%

3 CK

011

4 CK

100

2 x (ONTIM+1) ONTIM+1

3 x (ONTIM+1) ONTIM+1

67%

75%

3 CK

101

4 CK

110

Reserved

1 CK

111

X

Note 1

1 CK

High-frequency output

Note:

In the high-frequency mode, the output is gated with the clock signal. Thus, the on- and off-times will be dependent on the clock

input to the MCU. Also note that when changing from this mode directly to another modulation mode, the output will have a

small glitch. Thus, PA2 should be set to stop the modulated output before changing from this mode.

43

1062F–AVR–07/06

Analog Comparator

The analog comparator compares the input values on the positive input PB0 (AIN0) and

negative input PB1 (AIN1). When the voltage on the positive input PB0 (AIN0) is higher

than the voltage on the negative input PB1 (AIN1), the Analog Comparator Output

(ACO) is set (one). The comparator can trigger a separate interrupt exclusive to the ana-

log comparator. The user can select interrupt triggering on comparator output rise, fall or

toggle. A block diagram of the comparator and its surrounding logic is shown in Figure

36.

Figure 36. Analog Comparator Block Diagram

PB0

PB1

Register Description

Analog Comparator Control

and Status Register – ACSR

Bit

7

6

–

5

ACO

R

4

ACI

R/W

0

3

ACIE

R/W

0

2

–

1

ACIS1

R/W

0

ACIS0

R/W

0

$08

ACD

R/W

1

ACSR

Read/Write

Initial Value

R

0

R

0

X

• Bit 7 – ACD: Analog Comparator Disable

When this bit is set (one), the power to the analog comparator is switched off. This bit

can be set at any time to turn off the analog comparator. When changing the ACD bit,

the Analog Comparator Interrupt must be disabled by clearing the ACIE bit in ACSR.

Otherwise, an interrupt can occur when the bit is changed. To use the analog compara-

tor, the user must clear this bit.

• Bit 6 – Res: Reserved Bit

This bit is a reserved bit in the ATtiny28 and will always read as zero.

• Bit 5 – ACO: Analog Comparator Output

ACO is directly connected to the comparator output.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set (one) when a comparator output event triggers the interrupt mode defined

by ACI1 and ACI0. The Analog Comparator Interrupt routine is executed if the ACIE bit

is set (one) and the I-bit in SREG is set (one). ACI is cleared by hardware when execut-

44

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

ing the corresponding interrupt handling vector. Alternatively, ACI is cleared by writing a

logical “1” to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is set (one) and the I-bit in the Status Register is set (one), the ana-

log comparator interrupt is activated. When cleared (zero), the interrupt is disabled.

• Bit 2 – RES: Reserved Bit

This bit is a reserved bit in the ATtiny28 and will always read as zero.

• Bits 1, 0 - ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events trigger the Analog Comparator Interrupt.

The different settings are shown in Table 19.

Table 19. ACIS1/ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

0

1

0

1

0

1

Comparator Interrupt on Output Toggle

Reserved

Comparator Interrupt on Falling Output Edge

Comparator Interrupt on Rising Output Edge

Note:

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be dis-

abled by clearing its Interrupt Enable bit in the ACSR register. Otherwise, an interrupt can

occur when the bits are changed.

Caution: Using the SBI or CBI instruction on bits other than ACI in this register will write

a one back into ACI if it is read as set, thus clearing the flag.

45

1062F–AVR–07/06

Memory

Programming

Program Memory Lock

Bits

The ATtiny28 MCU provides two Lock bits that can be left unprogrammed (“1”) or can be

programmed (“0”) to obtain the additional features listed in Table 20. The Lock bits can

only be erased with the Chip Erase command.

Table 20. Lock Bit Protection Modes

Memory Lock Bits

Mode

LB1

LB2

1

Protection Type

1

2

3

1

0

No memory lock features enabled.

Further programming of the Flash is disabled.⁽¹⁾

Same as mode 2, and verify is also disabled.

1

0

Note:

1. Further programming of the Fuse bits is also disabled. Program the Fuse bits before

programming the Lock bits.

Fuse Bits

The ATtiny28 has five Fuse bits, INTCAP and CKSEL3..0.

•

When the INTCAP Fuse is programmed (“0”), internal load capacitors are

connected between XTAL1/XTAL2 and GND, similar to C1 and C2 in Figure 5. See

“Crystal Oscillator” on page 7. Default value is unprogrammed (“1”).

•

CKSEL3..0 Fuses: See Table 1, “Device Clocking Option Select,” on page 7 and

Table 5, “ATtiny28 Clock Options and Start-up Time,” on page 16, for which

combination of CKSEL3..0 to use. Default value is “0010”, internal RC oscillator with

long start-up time.

The status of the Fuse bits is not affected by Chip Erase.

Signature Bytes

Calibration Byte

All Atmel microcontrollers have a 3-byte signature code that identifies the device. The

three bytes reside in a separate address space.

For the ATtiny28, they are:

1. $000: $1E (indicates manufactured by Atmel)

2. $001: $91 (indicates 2 KB Flash memory)

3. $002: $07 (indicates ATtiny28 device when signature byte $001 is $91)

The ATtiny28 has one byte calibration value for the internal RC oscillator. This byte

resides in the high byte of address $000 in the signature address space. During memory

programming, the external programmer must read this location, and program it into a

selected location in the the normal Flash program memory. At start-up, the user soft-

ware must read this Flash location and write the value to the OSCCAL register.

46

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Programming the Flash

Atmel’s ATtiny28 offers 2K bytes of Flash program memory.

The ATtiny28 is shipped with the on-chip Flash program memory array in the erased

state (i.e., contents = $FF) and ready to be programmed. This device supports a high-

voltage (12V) parallel programming mode. Only minor currents (<1mA) are drawn from

the +12V pin during programming.

The program memory array in the ATtiny28 is programmed byte-by-byte. During pro-

gramming, the supply voltage must be in accordance with Table 21.

Table 21. Supply Voltage during Programming

Part

Serial Programming

Parallel Programming

ATtiny28

Not applicable

4.5 - 5.5V

Parallel Programming

This section describes how to parallel program and verify Flash program memory, Lock

bits and Fuse bits in the ATtiny28.

Signal Names

In this section, some pins of the ATtiny28 are referenced by signal names describing

their function during parallel programming. See Figure 37 and Table 22. Pins not

described in Table 22 are referenced by pin name.

The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a posi-

tive pulse. The coding is shown in Table 23.

When pulsing WR or OE, the command loaded determines the action executed. The

command is a byte where the different bits are assigned functions, as shown in Table

24.

Figure 37. Parallel Programming

ATtiny28

+5V

VCC

PB7 - PB0

PD1

RDY/BSY

OE

PD2

DATA

WR

BS

PD3

PD4

XA0

XA1

+12V

PD5

PD6

RESET

XTAL1

GND

47

1062F–AVR–07/06

Table 22. Pin Name Mapping

Signal Name in

Programming Mode

Pin Name I/O Function

“0”: Device is busy programming, “1”: Device is

ready for new command

RDY/BSY

PD1

O

OE

PD2

PD3

I

Output Enable (active low)

Write Pulse (active low)

WR

Byte Select (“0” selects low byte, “1” selects

high byte)

BS

PD4

I

XA0

XA1

PD5

PD6

I

XTAL1 Action Bit 0

XTAL1 Action Bit 1

DATA

PB7 - PB0 I/O Bi-directional Data Bus (output when OE is low)

.

Table 23. XA1 and XA0 Coding

XA1 XA0 Action when XTAL1 is Pulsed

Load Flash/Signature byte Address (High or low address byte for Flash

determined by BS)

0

1

0

1

Load Data (High or low data byte for Flash determined by BS)

Load Command

No Action, Idle

Table 24. Command Byte Coding

Command Byte

1000 0000

0100 0000

0010 0000

0001 0000

0000 1000

0000 0100

0000 0010

Command Executed

Chip Erase

Write Fuse Bits

Write Lock Bits

Write Flash

Read Signature Bytes and Calibration Byte

Read Fuse and Lock Bits

Read Flash

Enter Programming Mode

The following algorithm puts the device in parallel programming mode:

1. Apply 4.5 - 5.5V between VCC and GND.

2. Set RESET and BS pins to “0” and wait at least 100 ns.

3. Apply 11.5 - 12.5V to RESET. Any activity on BS within 100 ns after +12V has

been applied to RESET will cause the device to fail entering programming mode.

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ATtiny28L/V

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ATtiny28L/V

Chip Erase

The Chip Erase command will erase the Flash memory and the Lock bits. The Lock bits

are not reset until the Flash has been completely erased. The Fuse bits are not

changed. Chip Erase must be performed before the Flash is reprogrammed.

Load Command “Chip Erase”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS to “0”.

3. Set DATA to “1000 0000”. This is the command for Chip Erase.

4. Give XTAL1 a positive pulse. This loads the command.

5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.

6. Wait until RDY/BSY goes high before loading a new command.

Programming the Flash

A: Load Command “Write Flash”

1. Set XA1, XA0 to “10”. This enables command loading.

2. Set BS to “0”.

3. Set DATA to “0001 0000”. This is the command for Write Flash.

4. Give XTAL1 a positive pulse. This loads the command.

B: Load Address High Byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS to “1”. This selects high byte.

3. Set DATA = Address high byte ($00 - $03).

4. Give XTAL1 a positive pulse. This loads the address high byte.

C: Load Address Low Byte

1. Set XA1, XA0 to “00”. This enables address loading.

2. Set BS to “0”. This selects low byte.

3. Set DATA = Address low byte ($00 - $FF).

4. Give XTAL1 a positive pulse. This loads the address low byte.

D: Load Data Low Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data low byte ($00 - $FF).

3. Give XTAL1 a positive pulse. This loads the data low byte.

E: Write Data Low Byte

1. Set BS to “0”. This selects low data.

2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY

goes low.

3. Wait until RDY/BSY goes high to program the next byte.

(See Figure 38 for signal waveforms.)

F: Load Data High Byte

1. Set XA1, XA0 to “01”. This enables data loading.

2. Set DATA = Data high byte ($00 - $FF).

3. Give XTAL1 a positive pulse. This loads the data high byte.

G: Write Data High Byte

49

1062F–AVR–07/06

1. Set BS to “1”. This selects high data.

2. Give WR a negative pulse. This starts programming of the data byte. RDY/BSY

goes low.

3. Wait until RDY/BSY goes high to program the next byte.

(See Figure 39 for signal waveforms.)

The loaded command and address are retained in the device during programming. For

efficient programming, the following should be considered:

•

The command needs to be loaded only once when writing or reading multiple

memory locations.

Address high byte only needs to be loaded before programming a new 256-word

page in the Flash.

Skip writing the data value $FF, that is, the contents of the entire Flash after a Chip

Erase.

These considerations also apply to Flash and signature bytes reading.

Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to “Programming the

Flash” for details on command and address loading):

A: Load Command “0000 0010”.

B: Load Address High Byte ($00 - $03).

C: Load Address Low Byte ($00 - $FF).

1. Set OE to “0”, and BS to “0”. The Flash word low byte can now be read at DATA.

2. Set BS to “1”. The Flash word high byte can now be read from DATA.

3. Set OE to “1”.

Programming the Fuse Bits

The algorithm for programming the Fuse bits is as follows (refer to “Programming the

Flash” for details on command and data loading):

A: Load Command “0100 0000”.

D: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.

Bit 4 = INTCAP Fuse

Bit 3 = CKSEL3 Fuse

Bit 2 = CKSEL2 Fuse

Bit 1 = CKSEL1 Fuse

Bit 0 = CKSEL0 Fuse

Bits 7 - 5 = “1”. These bits are reserved and should be left unprogrammed (“1”).

E: Write Data Low Byte.

Programming the Lock Bits

The algorithm for programming the Lock bits is as follows (refer to “Programming the

Flash” for details on command and data loading):

A: Load Command “0010 0000”.

D: Load Data Low Byte. Bit n = “0” programs the Lock bit.

Bit 2 = Lock Bit2

Bit 1 = Lock Bit1

Bits 7 - 3,0 = “1”. These bits are reserved and should be left unprogrammed (“1”).

E: Write Data Low Byte.

The Lock bits can only be cleared by executing Chip Erase.

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ATtiny28L/V

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ATtiny28L/V

Reading the Fuse and Lock

Bits

The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming

the Flash” for details on command loading):

A: Load Command “0000 0100”.

1. Set OE to “0”, and BS to “0”. The status of the Fuse bits can now be read at

DATA (“0” means programmed).

Bit 4 = INTCAP Fuse

Bit 3 = CKSEL3 Fuse

Bit 2 = CKSEL2 Fuse

Bit 1 = CKSEL1 Fuse

Bit 0 = CKSEL0 Fuse

2. Set BS to “1”. The status of the Lock bits can now be read at DATA (“0” means

programmed).

Bit 2: Lock Bit2

Bit 1: Lock Bit1

3. Set OE to “1”.

Reading the Signature Bytes

and Calibration Byte

The algorithm for reading the signature bytes and the calibration byte is as follows (refer

to “Programming the Flash” for details on command and address loading):

A: Load Command “0000 1000”.

C: Load Address Low Byte ($00 - $02).

1. Set OE to “0”, and BS to “0”. The selected signature byte can now be read at

DATA.

C: Load Address Low Byte ($00).

1. Set OE to “0”, and BS to “1”. The calibration byte can now be read at DATA.

2. Set OE to “1”.

Figure 38. Programming the Flash Waveforms

$10

ADDR. HIGH

ADDR. LOW

DATA LOW

DATA

XA1

XA0

BS

XTAL1

WR

RDY/BSY

RESET

OE

12V

51

1062F–AVR–07/06

Figure 39. Programming the Flash Waveforms (Continued)

DATA

DATA HIGH

XA1

XA0

BS

XTAL1

WR

RDY/BSY

RESET

OE

+12V

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ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Parallel Programming

Characteristics

Figure 40. Parallel Programming Timing

t_XLWL

t_XHXL

XTAL1

t_DVXH

t_XLDXt_BVWL

Data & Contol

(DATA, XA0/1, BS)

t_WLWH

WR

t_RHBX

RDY/BSY

t_WLRL

t_WLRH

t_OHDZ

OE

t_XLOL

t_OLDV

DATA

T_A= 25°C 10%, V_CC= 5V 10%

Symbol

V_PP

Parameter

Min

Typ

Max

12.5

Unit

V

Programming Enable Voltage

Programming Enable Current

11.5

I_PP

250.0

µA

ns

µs

ms

ns

t_DVXH

t_XHXL

t_XLDX

t_XLWL

t_BVWL

t_RHBX

t_WLWH

t_WLRL

t_WLRH

t_XLOL

t_OLDV

t_OHDZ

Data & Control Valid before XTAL1 High

XTAL1 Pulse Width High

Data & Control Hold after XTAL1 Low

XTAL1 Low to WR Low

67.0

0.0

BS Valid to WR Low

BS Hold after RDY/BSY High

WR Pulse Width Low

WR Low to RDY/BSY Low

WR Low to RDY/BSY High

XTAL1 Low to OE Low

2.5

0.9

0.5

0.7

67.0

OE Low to DATA Valid

20.0

OE High to DATA Tri-stated

20.0

53

1062F–AVR–07/06

Electrical Characteristics

Absolute Maximum Ratings

*NOTICE:

Stresses beyond those ratings listed under

“Absolute Maximum Ratings” may cause perma-

nent damage to the device. This is a stress rating

only and functional operation of the device at

these or other conditions beyond those indicated

in the operational sections of this specification is

not implied. Exposure to absolute maximum rat-

ing conditions for extended periods may affect

device reliability.

Operating Temperature............................. -40°C to +85/105°C

Storage Temperature..................................... -65°C to +150°C

Voltage on Any Pin except RESET

with Respect to Ground.............................-1.0V to V_CC+ 0.5V

Maximum Operating Voltage ............................................ 6.0V

Voltage on RESET with Respect to Ground ....-1.0V to +13.0V

DC Current per I/O Pin, except PA2 ........................... 40.0 mA

DC Current PA2 .......................................................... 60.0 mA

DC Current VCC and GND Pin................................. 300.0 mA

DC Characteristics

T_A= -40°C to 85°C, V_CC= 1.8V to 5.5V (unless otherwise noted)

Symbol

V_IL

Parameter

Condition

(Except XTAL)

XTAL

Min

Typ

Max

Units

Input Low Voltage

Input High Voltage

-0.5

0.3 Vcc⁽¹⁾

0.1 Vcc⁽¹⁾

V_CC+ 0.5

V

V_IL1

(2)

V_IH

(Except XTAL, RESET)

XTAL

0.6 V_CC

0.7 V_CC

V_IH1

V_IH2

V_OL

(2)

RESET

0.85 V_CC

Output Low Voltage⁽³⁾

Ports A, D

I_OL= 20 mA, V_CC= 5V

I_OL= 10 mA, V_CC= 3V

0.6

0.5

V

V_OL

V_OH

I_IL

Output Low Voltage⁽³⁾

Port A2

I_OL= 25 mA, V_CC= 2.0V

V

1.0

Output High Voltage⁽⁴⁾

Ports A, D

I

_OH= -3 mA, V_CC= 5V

4.3

2.3

V

I_OH= -1.5 mA, V_CC= 3V

Input Leakage Current I/O Pin V_CC= 5.5V, pin low

(absolute value)

8.0

µA

I_IL

Input Leakage Current I/O Pin V_CC= 5.5V, pin high

(absolute value)

µA

R_I/O

I/O Pin Pull-up

35.0

122.0

3.0

kΩ

Active Mode, V_CC= 3V,

4 MHz

mA

Idle Mode V_CC= 3V,

4 MHz

1.0

9.0

1.2

15.0

2.0

mA

µA

I_CC

Power Supply Current

Power-down⁽⁵⁾⁽⁶⁾, V_CC= 3V

WDT enabled

Power-down⁽⁵⁾⁽⁶⁾, V_CC= 3V

WDT disabled

<1.0

54

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

DC Characteristics (Continued)

T_A= -40°C to 85°C, V_CC= 1.8V to 5.5V (unless otherwise noted)

Symbol

Parameter

Condition

Min

Typ

Max

Units

V_ACIO

Analog Comparator Input

Offset Voltage

V_CC= 5V

V_IN= V_CC/2

40.0

mV

I_ACLK

Analog Comparator Input

Leakage Current

V_CC= 5V

V_IN= V_CC/2

-50.0

50.0

nA

ns

T_ACPD

Analog Comparator

Propagation Delay

V_CC= 2.7V

V_CC= 4.0V

750.0

500.0

Notes: 1. “Max” means the highest value where the pin is guaranteed to be read as low.

2. “Min” means the lowest value where the pin is guaranteed to be read as high.

3. Although each I/O port can sink more than the test conditions (20 mA at V_CC= 5V, 10 mA at V_CC= 3V) under steady-state

conditions (non-transient), the following must be observed:

1] The sum of all I_OL, for all ports, should not exceed 300 mA.

2] The sum of all I_OL, for port D0 - D7 and XTAL2 should not exceed 100 mA.

If I_OLexceeds the test condition, V_OLmay exceed the related specification.

Pins are not guaranteed to sink current greater than the listed test conditions.

4. Although each I/O port can source more than the test conditions (3 mA at V_CC= 5V, 1.5 mA at V_CC= 3V) under steady-state

conditions (non-transient), the following must be observed:

1] The sum of all I_OH, for all ports, should not exceed 300 mA.

2] The sum of all I_OH, for port D0 - D7 and XTAL2 should not exceed 100 mA.

If I_OHexceeds the test condition, V_OHmay exceed the related specification.

Pins are not guaranteed to source current greater than the listed test conditions.

5. Minimum V_CCfor power-down is 1.5V.

6. When entering Power-down, PORTA2 bit in PORTA register should be set.

55

1062F–AVR–07/06

External Clock Drive Waveforms

Figure 41. External Clock

VIH1

VIL1

External Clock Drive

V_CC= 1.8V to 2.7V

V_CC= 2.7V to 4.0V

V_CC= 4.0V to 5.5V

Symbol

1/t_CLCL

t_CLCL

Parameter

Oscillator Frequency

Clock Period

High Time

Min

Max

Min

0.0

Max

Min

0.0

Max

Units

MHz

ns

0.0

1.2

4.0

833.0

333.0

250.0

100.0

250.0

100.0

t_CHCX

t_CLCX

ns

Low Time

ns

t_CLCH

Rise Time

1.6

0.5

µs

t_CHCL

Fall Time

µs

:

Table 25. External RC Oscillator, Typical Frequencies

R [kΩ]

100.0

31.5

C [pF]

70.0

f

100.0 kHz

1.0 MHz

4.0 MHz

20.0

6.5

Note:

R should be in the range 3 - 100 kΩ, and C should be at least 20 pF.

56

ATtiny28L/V

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ATtiny28L/V

Typical

Characteristics

The following charts show typical behavior. These figures are not tested during manu-

facturing. All current consumption measurements are performed with all I/O pins

configured as inputs and with internal pull-ups enabled. A sine wave generator with rail-

to-rail output is used as clock source.

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a function of several factors, such as: operating voltage,

operating frequency, loading of I/O pins, switching rate of I/O pins, code executed and

ambient temperature. The dominating factors are operating voltage and frequency. The

current drawn from capacitive loaded pins may be estimated (for one pin) as C_L• V_CC• f,

where C_L= Load Capacitance, V_CC= Operating Voltage and f = Average Switching Fre-

quency of I/O pin.

The parts are characterized at frequencies and voltages higher than test limits. Parts are

not guaranteed to function properly at frequencies and voltages higher than the ordering

code indicates.

The difference between current consumption in Power-down mode with Watchdog

Timer enabled and Power-down mode with Watchdog Timer disabled represents the dif-

ferential current drawn by the Watchdog Timer.

Figure 42. Active Supply Current vs. Frequency

ACTIVE SUPPLY CURRENT vs. FREQUENCY

T_A= 25˚C

18

V_CC= 6.0V

16

V_CC= 5.5V

V_CC= 5.0V

14

12

10

8

V_CC= 4.5V

V_CC= 4.0V

V_CC= 3.6V

6

V_CC= 3.3V

V_CC= 3.0V

4

V_CC= 2.7V

V_CC= 2.4V

2

V_CC= 2.1V

0

V_CC= 1.8V

1

0

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Frequency (MHz)

57

1062F–AVR–07/06

Figure 43. Active Supply Current vs. V_CC

ACTIVE SUPPLY CURRENT vs. V_CC

FREQUENCY = 4 MHz

8

7

6

5

4

3

2

1

0

T_A= 25˚C

T_A= 85˚C

1.5

2

2.5

3

3.5

V_CC(V)

4

4.5

5

5.5

6

Figure 44. Active Supply Current vs. V_CC, Device Clocked by Internal Oscillator

ACTIVE SUPPLY CURRENT vs. V_cc

DEVICE CLOCKED BY 1.2MHz INTERNAL RC OSCILLATOR

6

5

T_A= 25

˚C

4

3

2

1

0

T_A= 85˚C

1.5

2

2.5

3

3.5

V_cc(V)

4

4.5

5

5.5

6

58

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Figure 45. Active Supply Current vs. V_CC, Device Clocked by External 32 kHz Crystal

ACTIVE SUPPLY CURRENT vs. V_CC

DEVICE CLOCKED BY 32 kHz CRYSTAL

4

3.5

T_A= 25˚C

3

2.5

T_A= 85˚C

2

1.5

1

0.5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

V_CC(V)

Figure 46. Idle Supply Current vs. Frequency

IDLE SUPPLY CURRENT vs. FREQUENCY

T_A= 25˚C

4.5

4

V_CC= 6.0V

V_CC= 5.5V

V_CC= 5.0V

3.5

3

2.5

2

V_CC= 4.5V

V_CC= 4.0V

V_CC= 3.6V

V_CC= 3.3V

V_CC= 3.0V

V_CC= 2.7V

1.5

1

V_CC= 2.4V

0.5

0

V_CC= 2.1V

V_CC= 1.8V

0

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

Frequency (MHz)

59

1062F–AVR–07/06

Figure 47. Idle Supply Current vs. V_CC

IDLE SUPPLY CURRENT vs. V_CC

FREQUENCY = 4 MHz

1.4

1.2

1

T_A= 85˚C

T_A= 25˚C

0.8

0.6

0.4

0.2

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

V_CC(V)

Figure 48. Idle Supply Current vs. V_CC, Device Clocked by Internal Oscillator

IDLE SUPPLY CURRENT vs. V_cc

DEVICE CLOCKED BY 1.2MHz INTERNAL RC OSCILLATOR

0.7

0.6

T_A= 25˚C

0.5

0.4

0.3

0.2

0.1

0

T_A= 85˚C

1.5

2

2.5

3

3.5

V_cc(V)

4

4.5

5

5.5

6

60

ATtiny28L/V

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ATtiny28L/V

Figure 49. Idle Supply Current vs. V_CC, Device Clocked by External 32 kHz Crystal

IDLE SUPPLY CURRENT vs. V_CC

DEVICE CLOCKED BY 32 kHz CRYSTAL

30

25

T_A= 85˚C

T_A= 25˚C

20

15

10

5

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

V_CC(V)

Figure 50. Power-down Supply Current vs. V_CC

POWER-DOWN SUPPLY CURRENT vs. V_CC

WATCHDOG TIMER DISABLED

3

2.5

2

T_A= 85˚C

T_A= 70˚C

1.5

1

0.5

0

T_A= 45˚C

T_A= 25˚C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

V_CC(V)

61

1062F–AVR–07/06

Figure 51. Power-down Supply Current vs. V_CC

POWER-DOWN SUPPLY CURRENT vs. V_CC

WATCHDOG TIMER ENABLED

70

60

50

40

30

20

10

0

T_A= 25˚C

T_A= 85˚C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

V_CC(V)

Analog comparator offset voltage is measured as absolute offset.

Figure 52. Analog Comparator Offset Voltage vs. Common Mode Voltage (V_CC= 5V)

18

16

T_A= 25˚C

14

12

T_A= 85˚C

10

8

6

4

2

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

Common Mode Voltage (V)

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ATtiny28L/V

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ATtiny28L/V

Figure 53. Analog Comparator Offset Voltage vs. Common Mode Voltage (V_CC= 2.7V)

10

T_A= 25˚C

8

6

T_A= 85˚C

4

2

0

0.5

1

1.5

2

2.5

3

Common Mode Voltage (V)

Figure 54. Analog Comparator Input Leakage Current (V_CC= 6V; T_A= 25°C)

60

50

40

30

20

10

0

-10

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

6.5

7

V_IN(V)

63

1062F–AVR–07/06

Figure 55. Calibrated Internal RC Oscillator Frequency vs. V_CC

CALIBRATED RC OSCILLATOR FREQUENCY vs.

OPERATING VOLTAGE

1.28

1.26

1.24

1.22

1.2

T_A= 25˚C

T_A= 45

T_A= 70

˚

C

T_A= 85˚C

1.18

1.16

1.14

1.12

1.1

2

2.5

3

3.5

4

4.5

5

5.5

6

V_cc(V)

Figure 56. Watchdog Oscillator Frequency vs. V_CC

1600

1400

1200

1000

800

600

400

200

0

T_A= 25˚C

T_A= 85˚C

1.5

2

2.5

3

3.5

4

4.5

5

5.5

6

V_CC(V)

64

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Sink and source capabilities of I/O ports are measured on one pin at a time.

Figure 57. Pull-up Resistor Current vs. Input Voltage (V_CC= 5V)

120

T_A= 25˚C

100

T_A= 85˚C

80

60

40

20

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

V_OP(V)

Figure 58. Pull-up Resistor Current vs. Input Voltage (V_CC= 2.7V)

30

T_A= 25˚C

25

T_A= 85˚C

20

15

10

5

0

0.5

1

1.5

2

2.5

3

V_OP(V)

65

1062F–AVR–07/06

Figure 59. I/O Pin Sink Current vs. Output Voltage. All pins except PA2 (V_CC= 5V)

70

T_A= 25˚C

60

T_A= 85˚C

50

40

30

20

10

0

0.5

1

1.5

2

2.5

3

V_OL(V)

Figure 60. I/O Pin Source Current vs. Output voltage (V_CC= 5V)

20

T_A= 25˚C

18

16

T_A= 85˚C

14

12

10

8

6

4

2

0

0.5

1

1.5

2

2.5

3

3.5

4

4.5

5

V_OH(V)

66

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Figure 61. I/O Pin Sink Current vs. Output Voltage, All Pins Except PA2 (V_CC= 2.7V)

25

T_A= 25˚C

20

T_A= 85˚C

15

10

5

0

0.5

1

1.5

2

V_OL(V)

Figure 62. I/O Pin Source Current vs. Output Voltage (V_CC= 2.7V)

6

T_A= 25˚C

5

T_A= 85˚C

4

3

2

1

0

0.5

1

1.5

2

2.5

3

V_OH(V)

67

1062F–AVR–07/06

Figure 63. PA2 I/O Pin Sink Current vs. Output Voltage (High Current Pin PA2; T_A=

25°C)

90

V_CC= 3.6V

80

70

V_CC= 2.4V

60

50

40

V_CC= 1.8V

30

20

10

0

0.5

1

1.5

2

2.5

3

3.5

4

V_OL(V)

Figure 64. I/O Pin Input Threshold Voltage vs. V_CC(T_A= 25°C)

2.5

2

1.5

1

0.5

0

2.7

4.0

V_CC

5.0

68

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Figure 65. I/O Pin Input Hysteresis vs. V_CC(T_A= 25°C)

0.18

0.16

0.14

0.12

0.1

0.08

0.06

0.04

0.02

0

2.7

4.0

V_CC

5.0

69

1062F–AVR–07/06

Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

$3F

$3E

...

SREG

Reserved

PORTA

PACR

I

T

H

S

V

N

Z

C

page 6

$20

$1F

$1E

$1D

$1C

$1B

$1A

$19

$18

$17

$16

$15

$14

$13

$12

$11

$10

$0F

$0E

$0D

$0C

$0B

$0A

$09

$08

$07

$06

$05

$04

$03

$02

$01

$00

-

PORTA3

DDA3

PORTA2

PA2HC

-

PORTA1

DDA1

PORTA0

DDA0

page 32

PINA

PINA3

PINA1

PINA0

Reserved

PINB

PINB7

PINB6

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

page 32

Reserved

PORTD

DDRD

PORTD7

DDD7

PORTD6

DDD6

PORTD5

DDD5

PORTD4

DDD4

PORTD3

DDD3

PORTD2

DDD2

PORTD1

DDD1

PORTD0

DDD0

page 33

PIND

PIND7

PIND6

PIND5

PIND4

PIND3

PIND2

PIND1

PIND0

Reserved

ACSR

ACD

PLUPB

INT1

-

ACO

SE

LLIE

-

ACI

SM

ACIE

WDRF

ISC11

-

ACIS1

EXTRF

ISC01

-

ACIS0

PORF

ISC00

-

page 44

page 19

page 22

page 23

page 35

page 36

page 43

page 37

page 9

MCUCS

ICR

-

INT0

INTF0

-

TOIE0

TOV0

OOM01

ISC10

-

IFR

INTF1

FOV0

TCCR0

-

OOM00

CS02

CS01

CS00

TCNT0

Timer/Counter0 (8-bit)

ONTIM1

WDTOE

MODCR

WDTCR

OSCCAL

ONTIM4

-

ONTIM3

ONTIM2

-

ONTIM0

WDE

MCONF2

WDP2

MCONF1

WDP1

MCONF0

WDP0

-

Oscillator Calibration Register

Notes: 1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. Some of the status flags are cleared by writing a logical “1” to them. Note that the CBI and SBI instructions will operate on all

bits in the I/O register, writing a one back into any flag read as set, thus clearing the flag. The CBI and SBI instructions work

with registers $00 to $1F only.

70

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Instruction Set Summary

Mnemonic

Operands

Description

Operation

Flags

# Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

SUB

SUBI

SBC

SBCI

AND

ANDI

OR

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add Two Registers

Rd ← Rd + Rr

Rd ← Rd + Rr + C

Rd ← Rd - Rr

Rd ← Rd - K

Z,C,N,V,H

Z,N,V

1

Add with Carry Two Registers

Subtract Two Registers

Subtract Constant from Register

Subtract with Carry Two Registers

Subtract with Carry Constant from Reg.

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rd ← Rd • Rr

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Rd ← Rd v K

Z,N,V

ORI

Z,N,V

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd ⊕ Rr

Rd ← $FF - Rd

Rd ← $00 - Rd

Rd ← Rd v K

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd, K

Rd

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd ← Rd • (FFh - K)

Rd ← Rd + 1

Z,N,V

DEC

TST

CLR

SER

Rd

Decrement

Rd ← Rd - 1

Z,N,V

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← $FF

Z,N,V

Rd

Z,N,V

Rd

Set Register

None

BRANCH INSTRUCTIONS

RJMP

RCALL

RET

k

Relative Jump

PC ← PC + k + 1

None

I

2

Relative Subroutine Call

Subroutine Return

PC ← PC + k + 1

3

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd, Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd - Rr

None

Z,N,V,C,H

Z N,V,C,H

None

1/2

1

Rd, Rr

CPC

Rd, Rr

Compare with Carry

Rd - Rr - C

1

CPI

Rd, K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd - K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b) = 0) PC ← PC + 2 or 3

if (Rr(b) = 1) PC ← PC + 2 or 3

if (P(b) = 0) PC ← PC + 2 or 3

if (P(b) = 1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC ← PC + k + 1

if (SREG(s) = 0) then PC ← PC + k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V = 0) then PC ← PC + k + 1

if (N ⊕ V = 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if (I = 1) then PC ← PC + k + 1

if (I = 0) then PC ← PC + k + 1

1/2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less than Zero, Signed

Branch if Half-carry Flag Set

Branch if Half-carry Flag Cleared

Branch if T-flag Set

k

Branch if T-flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

71

1062F–AVR–07/06

Instruction Set Summary (Continued)

Mnemonic

Operands

Description

Operation

Flags

# Clocks

DATA TRANSFER INSTRUCTIONS

LD

Rd, Z

Z, Rr

Load Register Indirect

Store Register Indirect

Move between Registers

Load Immediate

In Port

Rd ← (Z)

(Z) ← Rr

Rd ← Rr

Rd ← K

Rd ← P

P ← Rr

None

2

1

3

ST

MOV

LDI

IN

Rd, Rr

Rd, K

Rd, P

P, Rr

OUT

LPM

Out Port

Load Program Memory

R0 ← (Z)

BIT AND BIT-TEST INSTRUCTIONS

SBI

P, b

Rd

s

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

I/O(P,b) ← 0

None

LSL

Rd(n+1) ← Rd(n), Rd(0) ← 0

Z,C,N,V

LSR

ROL

ROR

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Logical Shift Right

Rotate Left through Carry

Rotate Right through Carry

Arithmetic Shift Right

Swap Nibbles

Rd(n) ← Rd(n+1), Rd(7) ← 0

Z,C,N,V

Rd(0) ← C, Rd(n+1) ← Rd(n), C ← Rd(7)

Z,C,N,V

Rd(7) ← C, Rd(n) ← Rd(n+1), C ← Rd(0)

Z,C,N,V

Rd(n) ← Rd(n+1), n = 0..6

Z,C,N,V

Rd(3..0) ← Rd(7..4), Rd(7..4) ← Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit Load from T to Register

Set Carry

T

None

C

Clear Carry

C ← 0

C

Set Negative Flag

N ← 1

N

Clear Negative Flag

Set Zero Flag

N ← 0

N

Z ← 1

Z

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Two’s Complement Overflow

Clear Two’s Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

NOP

SLEEP

WDR

S ← 1

S

S ← 0

S

V ← 1

V

V ← 0

V

T ← 1

T

Clear T in SREG

T ← 0

T

Set Half-carry Flag in SREG

Clear Half-carry Flag in SREG

No Operation

H ← 1

H

H ← 0

H

None

Sleep

(see specific descr. for Sleep function)

(see specific descr. for WDR/timer)

Watchdog Reset

72

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Ordering Information

Speed (MHz)

Power Supply (Volts)

Ordering Code

Package⁽¹⁾

Operation Range

ATtiny28L-4AC

ATtiny28L-4PC

ATtiny28L-4MC

32A

28P3

32M1-A

Commercial

(0°C to 70°C)

ATtiny28L-4AI

ATtiny28L-4AU⁽²⁾

32A

4

2.7 - 5.5

ATtiny28L-4PI

28P3

32M1-A

Industrial

ATtiny28L-4PU⁽²⁾

ATtiny28L-4MI

ATtiny28L-4MU⁽²⁾

(-40°C to 85°C)

ATtiny28V-1AC

ATtiny28V-1PC

ATtiny28V-1MC

32A

28P3

32M1-A

Commercial

(0°C to 70°C)

ATtiny28V-1AI

ATtiny28V-1AU⁽²⁾

32A

1.2

1.8 - 5.5

28P3

ATtiny28V-1PI

Industrial

ATtiny28V-1PU⁽²⁾

ATtiny28V-1MI

ATtiny28V-1MU⁽²⁾

(-40°C to 85°C)

28P3

32M1-A

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging alternative, complies to the European Directive for Restriction of Hazardous Substances (RoHS direc-

tive).Also Halide free and fully Green.

Package Type

32A

32-lead, Thin (1.0 mm) Plastic Quad Flat Package (TQFP)

28P3

28-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

32M1-A

32-pad, 5x5x1.0 body, Lead Pitch 0.50mm, Quad Flat No-lead/Micro Lead Frame Package (QFN/MLF)

73

1062F–AVR–07/06

Packaging Information

32A

PIN 1

B

PIN 1 IDENTIFIER

E1

E

e

D1

D

C

0˚~7˚

A2

A

A1

L

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

–

MAX

1.20

0.15

1.05

9.25

7.10

9.25

7.10

0.45

0.20

0.75

NOM

NOTE

SYMBOL

A

–

A1

A2

D

0.05

0.95

8.75

6.90

8.75

6.90

0.30

0.09

0.45

1.00

9.00

7.00

9.00

7.00

–

D1

E

Note 2

Notes:

1. This package conforms to JEDEC reference MS-026, Variation ABA.

2. Dimensions D1 and E1 do not include mold protrusion. Allowable

protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum

plastic body size dimensions including mold mismatch.

E1

B

C

–

3. Lead coplanarity is 0.10 mm maximum.

L

–

e

0.80 TYP

10/5/2001

TITLE

DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131

32A, 32-lead, 7 x 7 mm Body Size, 1.0 mm Body Thickness,

0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)

32A

B

R

74

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

28P3

D

1

E1

A

SEATING PLANE

A1

L

B2

(4 PLACES)

B

B1

e

E

COMMON DIMENSIONS

(Unit of Measure = mm)

0º ~ 15º REF

C

MIN

–

MAX

4.5724

–

NOM

NOTE

SYMBOL

A

–

eB

A1

D

0.508

34.544

7.620

7.112

0.381

1.143

0.762

3.175

0.203

–

34.798 Note 1

8.255

E

E1

B

7.493 Note 1

0.533

B1

B2

L

1.397

Note:

1. Dimensions D and E1 do not include mold Flash or Protrusion.

Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

1.143

3.429

C

0.356

eB

e

10.160

2.540 TYP

09/28/01

DRAWING NO. REV.

28P3

TITLE

2325 Orchard Parkway

San Jose, CA 95131

28P3, 28-lead (0.300"/7.62 mm Wide) Plastic Dual

Inline Package (PDIP)

B

R

75

1062F–AVR–07/06

32M1-A

D

D1

1

2

3

0

Pin 1 ID

SIDE VIEW

E1

E

TOP VIEW

A3

A1

A2

A

K

COMMON DIMENSIONS

(Unit of Measure = mm)

0.08

C

P

D2

MIN

0.80

–

MAX

1.00

0.05

1.00

NOM

0.90

0.02

0.65

0.20 REF

0.23

5.00

4.75

3.10

5.00

4.75

3.10

0.50 BSC

0.40

–

NOTE

SYMBOL

A

A1

A2

A3

b

1

2

3

P

–

Pin #1 Notch

(0.20 R)

E2

0.18

4.90

4.70

2.95

4.90

4.70

2.95

0.30

5.10

4.80

3.25

5.10

4.80

3.25

D

K

D1

D2

E

e

b

L

E1

E2

e

BOTTOM VIEW

L

0.30

–

0.50

0.60

P

o

–

12

0

Note: JEDEC Standard MO-220, Fig. 2 (Anvil Singulation), VHHD-2.

K

0.20

–

5/25/06

DRAWING NO. REV.

32M1-A

TITLE

2325 Orchard Parkway

San Jose, CA 95131

32M1-A, 32-pad, 5 x 5 x 1.0 mm Body, Lead Pitch 0.50 mm,

3.10 mm Exposed Pad, Micro Lead Frame Package (MLF)

E

R

76

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Errata

All revisions

No known errata.

77

1062F–AVR–07/06

Datasheet Revision

History

Please note that the referring page numbers in this section are referred to this docu-

ment. The referring revision in this section are referring to the document revision.

Rev – 01/06G

1. Updated chapter layout.

2. Updated “Ordering Information” on page 73.

Rev – 01/06G

1. Updated description for “Port A” on page 25.

2. Added note 6 in “DC Characteristics” on page 54.

3. Updated “Ordering Information” on page 73.

4. Added “Errata” on page 77.

Rev – 03/05F

1. Updated “Electrical Characteristics” on page 54.

2. MLF-package alternative changed to “Quad Flat No-Lead/Micro Lead Frame Package

QFN/MLF”.

3. Updated “Ordering Information” on page 73.

78

ATtiny28L/V

1062F–AVR–07/06

ATtiny28L/V

Table of Contents

Features................................................................................................. 1

Pin Configurations................................................................................ 1

Description............................................................................................ 2

Block Diagram ...................................................................................................... 2

Pin Descriptions.................................................................................................... 3

Clock Options ....................................................................................................... 4

Architectural Overview......................................................................... 6

General-purpose Register File.............................................................................. 7

ALU – Arithmetic Logic Unit.................................................................................. 7

Downloadable Flash Program Memory ................................................................ 7

Program and Data Addressing Modes.................................................................. 7

Subroutine and Interrupt Hardware Stack .......................................................... 10

Memory Access and Instruction Execution Timing............................................. 10

I/O Memory......................................................................................................... 11

Reset and Interrupt Handling.............................................................................. 12

Sleep Modes....................................................................................................... 21

Timer/Counter0 ................................................................................... 24

Timer/Counter Prescaler..................................................................................... 24

Watchdog Timer.................................................................................. 27

Calibrated Internal RC Oscillator ...................................................... 29

Hardware Modulator........................................................................... 30

Analog Comparator ............................................................................ 35

I/O Ports............................................................................................... 37

Port A.................................................................................................................. 37

Port B.................................................................................................................. 40

Port D.................................................................................................................. 43

Memory Programming........................................................................ 45

Program Memory Lock Bits ................................................................................ 45

Fuse Bits............................................................................................................. 45

Signature Bytes .................................................................................................. 45

Calibration Byte .................................................................................................. 45

Programming the Flash ...................................................................................... 45

Parallel Programming ......................................................................................... 46

Parallel Programming Characteristics.............................................. 52

i

1062F–AVR–07/06

Electrical Characteristics................................................................... 53

Absolute Maximum Ratings................................................................................ 53

DC Characteristics.............................................................................................. 53

External Clock Drive Waveforms........................................................................ 55

External Clock Drive ........................................................................................... 55

Typical Characteristics ...................................................................... 56

Register Summary.............................................................................. 69

Instruction Set Summary ................................................................... 70

Ordering Information.......................................................................... 72

Packaging Information....................................................................... 74

32A ..................................................................................................................... 74

28P3 ................................................................................................................... 75

32M1-A ............................................................................................................... 76

Errata ................................................................................................... 77

All revisions......................................................................................................... 77

Datasheet Revision History ............................................................... 78

Rev – 01/06G...................................................................................................... 78

Rev – 03/05F ...................................................................................................... 78

Table of Contents .................................................................................. i

ii

ATtiny28L/V

1062F–AVR–07/06

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Europe

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Printed on recycled paper.

1062F–AVR–07/06


型号：	ATTINY28V-1PJ
厂家：	ATMEL
描述：	RISC Microcontroller, 8-Bit, FLASH, 1.2MHz, CMOS, PDIP28, 0.300 INCH, PLASTIC, DIP-28 微控制器光电二极管
文件：	总81页 (文件大小：663K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ATTINY28V-1PJ [ATMEL]

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