ATTINY45V-10SU-SL383

Features

• High Performance, Low Power AVR^®8-Bit Microcontroller

• Advanced RISC Architecture

– 120 Powerful Instructions – Most Single Clock Cycle Execution

– 32 x 8 General Purpose Working Registers

– Fully Static Operation

• Non-volatile Program and Data Memories

– 2/4/8K Byte of In-System Programmable Program Memory Flash (ATtiny25/45/85)

• Endurance: 10,000 Write/Erase Cycles

– 128/256/512 Bytes In-System Programmable EEPROM (ATtiny25/45/85)

• Endurance: 100,000 Write/Erase Cycles

– 128/256/512 Bytes Internal SRAM (ATtiny25/45/85)

– Programming Lock for Self-Programming Flash Program and EEPROM Data

Security

8-bit

Microcontroller

with 2/4/8K

Bytes In-System

Programmable

Flash

• Peripheral Features

– 8-bit Timer/Counter with Prescaler and Two PWM Channels

– 8-bit High Speed Timer/Counter with Separate Prescaler

• 2 High Frequency PWM Outputs with Separate Output Compare Registers

• Programmable Dead Time Generator

– USI – Universal Serial Interface with Start Condition Detector

– 10-bit ADC

• 4 Single Ended Channels

ATtiny25/V *

ATtiny45/V

ATtiny85/V *

• 2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)

• Temperature Measurement

– Programmable Watchdog Timer with Separate On-chip Oscillator

– On-chip Analog Comparator

• Special Microcontroller Features

– debugWIRE On-chip Debug System

– In-System Programmable via SPI Port

– External and Internal Interrupt Sources

– Low Power Idle, ADC Noise Reduction, and Power-down Modes

– Enhanced Power-on Reset Circuit

* Preliminary

– Programmable Brown-out Detection Circuit

– Internal Calibrated Oscillator

• I/O and Packages

– Six Programmable I/O Lines

– 8-pin PDIP, 8-pin SOIC and 20-pad QFN/MLF

• Operating Voltage

– 1.8 - 5.5V for ATtiny25/45/85V

– 2.7 - 5.5V for ATtiny25/45/85

• Speed Grade

– ATtiny25/45/85V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V

– ATtiny25/45/85: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V

• Industrial Temperature Range

• Low Power Consumption

– Active Mode:

• 1 MHz, 1.8V: 300 μA

– Power-down Mode:

• 0.1μA at 1.8V

2586K–AVR–01/08

1. Pin Configurations

Figure 1-1. Pinout ATtiny25/45/85

PDIP/SOIC

(PCINT5/RESET/ADC0/dW) PB5

1

2

3

4

8

7

6

5

VCC

(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3

(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4

GND

PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)

PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)

PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)

QFN/MLF

1

15

(PCINT5/RESET/ADC0/dW) PB5

VCC

2

3

4

5

14

13

12

11

(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3

PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)

DNC

PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)

PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)

(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4

NOTE: Bottom pad should be soldered to ground.

DNC: Do Not Connect

1.1

Pin Descriptions

1.1.1

VCC

Supply voltage.

1.1.2

1.1.3

GND

Ground.

Port B (PB5..PB0)

Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The

Port B output buffers have symmetrical drive characteristics with both high sink and source

capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up

resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,

even if the clock is not running.

Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in

“Alternate Functions of Port B” on page 61.

On ATtiny25, the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged in

ATtiny15 Compatibility Mode for supporting the backward compatibility with ATtiny15.

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ATtiny25/45/85

1.1.4

RESET

Reset input. A low level on this pin for longer than the minimum pulse length will generate a

reset, even if the clock is not running and provided the reset pin has not been disabled. The min-

imum pulse length is given in Table 21-4 on page 170. Shorter pulses are not guaranteed to

generate a reset.

The reset pin can also be used as a (weak) I/O pin.

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2586K–AVR–01/08

2. Overview

The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced

RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85

achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize

power consumption versus processing speed.

2.1

Block Diagram

Figure 2-1. Block Diagram

8-BIT DATABUS

CALIBRATED

INTERNAL

OSCILLATOR

PROGRAM

COUNTER

STACK

POINTER

WATCHDOG

TIMER

TIMING AND

CONTROL

VCC

GND

MCU CONTROL

REGISTER

PROGRAM

FLASH

SRAM

MCU STATUS

REGISTER

GENERAL

PURPOSE

REGISTERS

INSTRUCTION

REGISTER

TIMER/

COUNTER0

X

Y

Z

INSTRUCTION

DECODER

TIMER/

COUNTER1

UNIVERSAL

SERIAL

INTERFACE

CONTROL

LINES

ALU

INTERRUPT

UNIT

STATUS

REGISTER

PROGRAMMING

LOGIC

DATA

EEPROM

OSCILLATORS

DATA REGISTER

PORT B

DATA DIR.

REG.PORT B

ADC /

ANALOG COMPARATOR

PORT B DRIVERS

RESET

PB0-PB5

The AVR core combines a rich instruction set with 32 general purpose working registers. All 32

registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent

4

ATtiny25/45/85

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ATtiny25/45/85

registers to be accessed in one single instruction executed in one clock cycle. The resulting

architecture is more code efficient while achieving throughputs up to ten times faster than con-

ventional CISC microcontrollers.

The ATtiny25/45/85 provides the following features: 2/4/8K byte of In-System Programmable

Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32

general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high

speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel,

10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software select-

able power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter,

ADC, Analog Comparator, and Interrupt system to continue functioning. Power-down mode

saves the register contents, disabling all chip functions until the next Interrupt or Hardware

Reset. ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize

switching noise during ADC conversions.

The device is manufactured using Atmel’s high density non-volatile memory technology. The

On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI

serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code

running on the AVR core.

The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools

including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.

5

2586K–AVR–01/08

3. About

3.1

3.2

Resources

A comprehensive set of development tools, application notes and datasheets are available for

download on http://www.atmel.com/avr.

Code Examples

This documentation contains simple code examples that briefly show how to use various parts of

the device. These code examples assume that the part specific header file is included before

compilation. Be aware that not all C compiler vendors include bit definitions in the header files

and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-

tation for more details.

For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”

instructions must be replaced with instructions that allow access to extended I/O. Typically, this

means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all

AVR devices include an extended I/O map.

3.3

Data Retention

Reliability Qualification results show that the projected data retention failure rate is much less

than 1 PPM over 20 years at 85°C or 100 years at 25°C.

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ATtiny25/45/85

4. AVR CPU Core

4.1

Introduction

This section discusses the AVR core architecture in general. The main function of the CPU core

is to ensure correct program execution. The CPU must therefore be able to access memories,

perform calculations, control peripherals, and handle interrupts.

4.2

Architectural Overview

Figure 4-1. Block Diagram of the AVR Architecture

Data Bus 8-bit

Program

Counter

Status

and Control

Flash

Program

Memory

32 x 8

General

Purpose

Registrers

Instruction

Register

Interrupt

Unit

Instruction

Decoder

Watchdog

Timer

ALU

Analog

Comparator

Control Lines

I/O Module1

I/O Module 2

I/O Module n

Data

SRAM

EEPROM

I/O Lines

In order to maximize performance and parallelism, the AVR uses a Harvard architecture – with

separate memories and buses for program and data. Instructions in the Program memory are

executed with a single level pipelining. While one instruction is being executed, the next instruc-

tion is pre-fetched from the Program memory. This concept enables instructions to be executed

in every clock cycle. The Program memory is In-System Reprogrammable Flash memory.

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2586K–AVR–01/08

The fast-access Register File contains 32 x 8-bit general purpose working registers with a single

clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-

ical ALU operation, two operands are output from the Register File, the operation is executed,

and the result is stored back in the Register File – in one clock cycle.

Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data

Space addressing – enabling efficient address calculations. One of the these address pointers

can also be used as an address pointer for look up tables in Flash Program memory. These

added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.

The ALU supports arithmetic and logic operations between registers or between a constant and

a register. Single register operations can also be executed in the ALU. After an arithmetic opera-

tion, the Status Register is updated to reflect information about the result of the operation.

Program flow is provided by conditional and unconditional jump and call instructions, able to

directly address the whole address space. Most AVR instructions have a single 16-bit word for-

mat, but there are also 32-bit instructions.

During interrupts and subroutine calls, the return address Program Counter (PC) is stored on the

Stack. The Stack is effectively allocated in the general data SRAM, and consequently the Stack

size is only limited by the total SRAM size and the usage of the SRAM. All user programs must

initialize the SP in the Reset routine (before subroutines or interrupts are executed). The Stack

Pointer (SP) is read/write accessible in the I/O space. The data SRAM can easily be accessed

through the five different addressing modes supported in the AVR architecture.

The memory spaces in the AVR architecture are all linear and regular memory maps.

A flexible interrupt module has its control registers in the I/O space with an additional Global

Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the

Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector posi-

tion. The lower the Interrupt Vector address, the higher the priority.

The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-

ters, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data

Space locations following those of the Register File, 0x20 - 0x5F.

4.3

4.4

ALU – Arithmetic Logic Unit

The high-performance AVR ALU operates in direct connection with all the 32 general purpose

working registers. Within a single clock cycle, arithmetic operations between general purpose

registers or between a register and an immediate are executed. The ALU operations are divided

into three main categories – arithmetic, logical, and bit-functions. Some implementations of the

architecture also provide a powerful multiplier supporting both signed/unsigned multiplication

and fractional format. See the “Instruction Set” section for a detailed description.

Status Register

The Status Register contains information about the result of the most recently executed arith-

metic instruction. This information can be used for altering program flow in order to perform

conditional operations. Note that the Status Register is updated after all ALU operations, as

specified in the Instruction Set Reference. This will in many cases remove the need for using the

dedicated compare instructions, resulting in faster and more compact code.

The Status Register is not automatically stored when entering an interrupt routine and restored

when returning from an interrupt. This must be handled by software.

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ATtiny25/45/85

4.4.1

SREG – AVR Status Register

The AVR Status Register – SREG – is defined as:

Bit

7

I

6

T

5

H

4

S

3

V

2

N

1

Z

0

C

0x3F

SREG

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – I: Global Interrupt Enable

The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual inter-

rupt enable control is then performed in separate control registers. If the Global Interrupt Enable

Register is cleared, none of the interrupts are enabled independent of the individual interrupt

enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and is set by

the RETI instruction to enable subsequent interrupts. The I-bit can also be set and cleared by

the application with the SEI and CLI instructions, as described in the instruction set reference.

• Bit 6 – T: Bit Copy Storage

The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or desti-

nation for the operated bit. A bit from a register in the Register File can be copied into T by the

BST instruction, and a bit in T can be copied into a bit in a register in the Register File by the

BLD instruction.

• Bit 5 – H: Half Carry Flag

The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is useful

in BCD arithmetic. See the “Instruction Set Description” for detailed information.

• Bit 4 – S: Sign Bit, S = N ⊕ V

The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement

Overflow Flag V. See the “Instruction Set Description” for detailed information.

• Bit 3 – V: Two’s Complement Overflow Flag

The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the

“Instruction Set Description” for detailed information.

• Bit 2 – N: Negative Flag

The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the

“Instruction Set Description” for detailed information.

• Bit 1 – Z: Zero Flag

The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction

Set Description” for detailed information.

• Bit 0 – C: Carry Flag

The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set

Description” for detailed information.

9

2586K–AVR–01/08

4.5

General Purpose Register File

The Register File is optimized for the AVR Enhanced RISC instruction set. In order to achieve

the required performance and flexibility, the following input/output schemes are supported by the

Register File:

• One 8-bit output operand and one 8-bit result input

• Two 8-bit output operands and one 8-bit result input

• Two 8-bit output operands and one 16-bit result input

• One 16-bit output operand and one 16-bit result input

Figure 4-2 shows the structure of the 32 general purpose working registers in the CPU.

Figure 4-2. AVR CPU General Purpose Working Registers

7

0

Addr.

R0

R1

0x00

0x01

0x02

R2

…

R13

R14

R15

R16

R17

…

0x0D

0x0E

0x0F

0x10

0x11

General

Purpose

Working

Registers

R26

R27

R28

R29

R30

R31

0x1A

0x1B

0x1C

0x1D

0x1E

0x1F

X-register Low Byte

X-register High Byte

Y-register Low Byte

Y-register High Byte

Z-register Low Byte

Z-register High Byte

Most of the instructions operating on the Register File have direct access to all registers, and

most of them are single cycle instructions.

As shown in Figure 4-2, each register is also assigned a Data memory address, mapping them

directly into the first 32 locations of the user Data Space. Although not being physically imple-

mented as SRAM locations, this memory organization provides great flexibility in access of the

registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.

4.5.1

The X-register, Y-register, and Z-register

The registers R26..R31 have some added functions to their general purpose usage. These reg-

isters are 16-bit address pointers for indirect addressing of the data space. The three indirect

address registers X, Y, and Z are defined as described in Figure 4-3.

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ATtiny25/45/85

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ATtiny25/45/85

Figure 4-3. The X-, Y-, and Z-registers

15

XH

XL

0

X-register

7

0

7

R27 (0x1B)

R26 (0x1A)

15

YH

YL

ZL

0

Y-register

Z-register

7

R29 (0x1D)

R28 (0x1C)

15

ZH

0

7

0

R31 (0x1F)

R30 (0x1E)

In the different addressing modes these address registers have functions as fixed displacement,

automatic increment, and automatic decrement (see the instruction set reference for details).

4.6

Stack Pointer

The Stack is mainly used for storing temporary data, for storing local variables and for storing

return addresses after interrupts and subroutine calls. The Stack Pointer Register always points

to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-

tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack

Pointer.

The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt

Stacks are located. This Stack space in the data SRAM must be defined by the program before

any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be set to

point above 0x60. The Stack Pointer is decremented by one when data is pushed onto the Stack

with the PUSH instruction, and it is decremented by two when the return address is pushed onto

the Stack with subroutine call or interrupt. The Stack Pointer is incremented by one when data is

popped from the Stack with the POP instruction, and it is incremented by two when data is

popped from the Stack with return from subroutine RET or return from interrupt RETI.

The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of

bits actually used is implementation dependent. Note that the data space in some implementa-

tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register

will not be present.

4.6.1

SPH and SPL — Stack Pointer Register

Bit

15

SP15

SP7

14

SP14

SP6

13

SP13

SP5

12

SP12

SP4

11

SP11

SP3

10

SP10

SP2

9

SP9

8

SP8

0x3E

0x3D

SPH

SPL

SP1

SP0

7

6

5

4

3

2

1

0

Read/Write

Initial Value

R/W

RAMEND

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2586K–AVR–01/08

4.7

Instruction Execution Timing

This section describes the general access timing concepts for instruction execution. The AVR

CPU is driven by the CPU clock clk_CPU, directly generated from the selected clock source for the

chip. No internal clock division is used.

Figure 4-4 shows the parallel instruction fetches and instruction executions enabled by the Har-

vard architecture and the fast access Register File concept. This is the basic pipelining concept

to obtain up to 1 MIPS per MHz with the corresponding unique results for functions per cost,

functions per clocks, and functions per power-unit.

Figure 4-4. The Parallel Instruction Fetches and Instruction Executions

T1

T2

T3

T4

clk_CPU

1st Instruction Fetch

1st Instruction Execute

2nd Instruction Fetch

2nd Instruction Execute

3rd Instruction Fetch

3rd Instruction Execute

4th Instruction Fetch

Figure 4-5 shows the internal timing concept for the Register File. In a single clock cycle an ALU

operation using two register operands is executed, and the result is stored back to the destina-

tion register.

Figure 4-5. Single Cycle ALU Operation

T1

T2

T3

T4

clk_CPU

Total Execution Time

Register Operands Fetch

ALU Operation Execute

Result Write Back

4.8

Reset and Interrupt Handling

The AVR provides several different interrupt sources. These interrupts and the separate Reset

Vector each have a separate Program Vector in the Program memory space. All interrupts are

assigned individual enable bits which must be written logic one together with the Global Interrupt

Enable bit in the Status Register in order to enable the interrupt.

The lowest addresses in the Program memory space are by default defined as the Reset and

Interrupt Vectors. The complete list of vectors is shown in “Interrupts” on page 50. The list also

determines the priority levels of the different interrupts. The lower the address the higher is the

priority level. RESET has the highest priority, and next is INT0 – the External Interrupt Request

0.

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ATtiny25/45/85

When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-

abled. The user software can write logic one to the I-bit to enable nested interrupts. All enabled

interrupts can then interrupt the current interrupt routine. The I-bit is automatically set when a

Return from Interrupt instruction – RETI – is executed.

There are basically two types of interrupts. The first type is triggered by an event that sets the

Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt Vec-

tor in order to execute the interrupt handling routine, and hardware clears the corresponding

Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit position(s)

to be cleared. If an interrupt condition occurs while the corresponding interrupt enable bit is

cleared, the Interrupt Flag will be set and remembered until the interrupt is enabled, or the flag is

cleared by software. Similarly, if one or more interrupt conditions occur while the Global Interrupt

Enable bit is cleared, the corresponding Interrupt Flag(s) will be set and remembered until the

Global Interrupt Enable bit is set, and will then be executed by order of priority.

The second type of interrupts will trigger as long as the interrupt condition is present. These

interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before the

interrupt is enabled, the interrupt will not be triggered.

When the AVR exits from an interrupt, it will always return to the main program and execute one

more instruction before any pending interrupt is served.

Note that the Status Register is not automatically stored when entering an interrupt routine, nor

restored when returning from an interrupt routine. This must be handled by software.

When using the CLI instruction to disable interrupts, the interrupts will be immediately disabled.

No interrupt will be executed after the CLI instruction, even if it occurs simultaneously with the

CLI instruction. The following example shows how this can be used to avoid interrupts during the

timed EEPROM write sequence..

Assembly Code Example

in r16, SREG

; store SREG value

cli ; disable interrupts during timed sequence

sbiEECR, EEMPE ; start EEPROM write

sbiEECR, EEPE

outSREG, r16

; restore SREG value (I-bit)

C Code Example

char cSREG;

cSREG = SREG;/* store SREG value */

/* disable interrupts during timed sequence */

_CLI();

EECR |= (1<<EEMPE); /* start EEPROM write */

EECR |= (1<<EEPE);

SREG = cSREG; /* restore SREG value (I-bit) */

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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-

cuted before any pending interrupts, as shown in this example.

Assembly Code Example

sei ; set Global Interrupt Enable

sleep; enter sleep, waiting for interrupt

; note: will enter sleep before any pending

; interrupt(s)

C Code Example

_SEI(); /* set Global Interrupt Enable */

_SLEEP(); /* enter sleep, waiting for interrupt */

/* note: will enter sleep before any pending interrupt(s) */

4.8.1

Interrupt Response Time

The interrupt execution response for all the enabled AVR interrupts is four clock cycles mini-

mum. After four clock cycles the Program Vector address for the actual interrupt handling routine

is executed. During this four clock cycle period, the Program Counter is pushed onto the Stack.

The vector is normally a jump to the interrupt routine, and this jump takes three clock cycles. If

an interrupt occurs during execution of a multi-cycle instruction, this instruction is completed

before the interrupt is served. If an interrupt occurs when the MCU is in sleep mode, the interrupt

execution response time is increased by four clock cycles. This increase comes in addition to the

start-up time from the selected sleep mode.

A return from an interrupt handling routine takes four clock cycles. During these four clock

cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is

incremented by two, and the I-bit in SREG is set.

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ATtiny25/45/85

5. AVR Memories

This section describes the different memories in the ATtiny25/45/85. The AVR architecture has

two main memory spaces, the Data memory and the Program memory space. In addition, the

ATtiny25/45/85 features an EEPROM Memory for data storage. All three memory spaces are lin-

ear and regular.

5.1

In-System Re-programmable Flash Program Memory

The ATtiny25/45/85 contains 2/4/8K byte On-chip In-System Reprogrammable Flash memory

for program storage. Since all AVR instructions are 16 or 32 bits wide, the Flash is organized as

1024/2048/4096 x 16.

The Flash memory has an endurance of at least 10,000 write/erase cycles. The ATtiny25/45/85

Program Counter (PC) is 10/11/12 bits wide, thus addressing the 1024/2048/4096 Program

memory locations. “Memory Programming” on page 151 contains a detailed description on Flash

data serial downloading using the SPI pins.

Constant tables can be allocated within the entire Program memory address space (see the

LPM – Load Program memory instruction description).

Timing diagrams for instruction fetch and execution are presented in “Instruction Execution Tim-

ing” on page 12.

Figure 5-1. Program Memory Map

Program Memory

0x0000

0x03FF/0x07FF/0x0FFF

5.2

SRAM Data Memory

Figure 5-2 shows how the ATtiny25/45/85 SRAM Memory is organized.

The lower 224/352/607 Data memory locations address both the Register File, the I/O memory

and the internal data SRAM. The first 32 locations address the Register File, the next 64 loca-

tions the standard I/O memory, and the last 128/256/512 locations address the internal data

SRAM.

The five different addressing modes for the Data memory cover: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register

File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given

by the Y- or Z-register.

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2586K–AVR–01/08

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, and the 128/256/512 bytes of inter-

nal data SRAM in the ATtiny25/45/85 are all accessible through all these addressing modes.

The Register File is described in “General Purpose Register File” on page 10.

Figure 5-2. Data Memory Map

Data Memory

0x0000 - 0x001F

0x0020 - 0x005F

0x0060

32 Registers

64 I/O Registers

Internal SRAM

(128/256/512 x 8)

0x0DF/0x015F/0x025F

5.2.1

Data Memory Access Times

This section describes the general access timing concepts for internal memory access. The

internal data SRAM access is performed in two clk_CPUcycles as described in Figure 5-3.

Figure 5-3. On-chip Data SRAM Access Cycles

T1

T2

T3

clk_CPU

Address valid

Compute Address

Address

Data

WR

Data

RD

Memory Access Instruction

Next Instruction

5.3

EEPROM Data Memory

The ATtiny25/45/85 contains 128/256/512 bytes of data EEPROM memory. It is organized as a

separate data space, in which single bytes can be read and written. The EEPROM has an

endurance of at least 100,000 write/erase cycles. The access between the EEPROM and the

CPU is described in the following, specifying the EEPROM Address Registers, the EEPROM

Data Register, and the EEPROM Control Register. For details see “Serial Downloading” on page

155.

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ATtiny25/45/85

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ATtiny25/45/85

5.3.1

EEPROM Read/Write Access

The EEPROM Access Registers are accessible in the I/O space.

The write access times for the EEPROM are given in Table 5-1 on page 21. A self-timing func-

tion, however, lets the user software detect when the next byte can be written. If the user code

contains instructions that write the EEPROM, some precautions must be taken. In heavily fil-

tered power supplies, V_CCis likely to rise or fall slowly on Power-up/down. This causes the

device for some period of time to run at a voltage lower than specified as minimum for the clock

frequency used. See “Preventing EEPROM Corruption” on page 19 for details on how to avoid

problems in these situations.

In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.

Refer to “Atomic Byte Programming” on page 17 and “Split Byte Programming” on page 17 for

details on this.

When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction is

executed. When the EEPROM is written, the CPU is halted for two clock cycles before the next

instruction is executed.

5.3.2

Atomic Byte Programming

Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM, the

user must write the address into the EEAR Register and data into EEDR Register. If the EEPMn

bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the erase/write

operation. Both the erase and write cycle are done in one operation and the total programming

time is given in Table 5-1 on page 21. The EEPE bit remains set until the erase and write opera-

tions are completed. While the device is busy with programming, it is not possible to do any

other EEPROM operations.

5.3.3

Split Byte Programming

It is possible to split the erase and write cycle in two different operations. This may be useful if

the system requires short access time for some limited period of time (typically if the power sup-

ply voltage falls). In order to take advantage of this method, it is required that the locations to be

written have been erased before the write operation. But since the erase and write operations

are split, it is possible to do the erase operations when the system allows doing time-critical

operations (typically after Power-up).

5.3.4

5.3.5

Erase

Write

To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the

EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (program-

ming time is given in Table 5-1 on page 21). The EEPE bit remains set until the erase operation

completes. While the device is busy programming, it is not possible to do any other EEPROM

operations.

To write a location, the user must write the address into EEAR and the data into EEDR. If the

EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger

the write operation only (programming time is given in Table 5-1 on page 21). The EEPE bit

remains set until the write operation completes. If the location to be written has not been erased

before write, the data that is stored must be considered as lost. While the device is busy with

programming, it is not possible to do any other EEPROM operations.

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2586K–AVR–01/08

The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator fre-

quency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on

page 32.

The following code examples show one assembly and one C function for erase, write, or atomic

write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling

interrupts globally) so that no interrupts will occur during execution of these functions.

Assembly Code Example

EEPROM_write:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_write

; Set Programming mode

ldi r16, (0<<EEPM1)|(0<<EEPM0)

out EECR, r16

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Write data (r19) to data register

out EEDR, r19

; Write logical one to EEMPE

sbi EECR,EEMPE

; Start eeprom write by setting EEPE

sbi EECR,EEPE

ret

C Code Example

void EEPROM_write(unsigned char ucAddress, unsigned char ucData)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set Programming mode */

EECR = (0<<EEPM1)|(0<<EEPM0);

/* Set up address and data registers */

EEAR = ucAddress;

EEDR = ucData;

/* Write logical one to EEMPE */

EECR |= (1<<EEMPE);

/* Start eeprom write by setting EEPE */

EECR |= (1<<EEPE);

}

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ATtiny25/45/85

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ATtiny25/45/85

The next code examples show assembly and C functions for reading the EEPROM. The exam-

ples assume that interrupts are controlled so that no interrupts will occur during execution of

these functions.

Assembly Code Example

EEPROM_read:

; Wait for completion of previous write

sbic EECR,EEPE

rjmp EEPROM_read

; Set up address (r18:r17) in address register

out EEARH, r18

out EEARL, r17

; Start eeprom read by writing EERE

sbi EECR,EERE

; Read data from data register

in r16,EEDR

ret

C Code Example

unsigned char EEPROM_read(unsigned char ucAddress)

{

/* Wait for completion of previous write */

while(EECR & (1<<EEPE))

;

/* Set up address register */

EEAR = ucAddress;

/* Start eeprom read by writing EERE */

EECR |= (1<<EERE);

/* Return data from data register */

return EEDR;

}

5.3.6

Preventing EEPROM Corruption

During periods of low V_CC, the EEPROM data can be corrupted because the supply voltage is

too low for the CPU and the EEPROM to operate properly. These issues are the same as for

board level systems using EEPROM, and the same design solutions should be applied.

An EEPROM data corruption can be caused by two situations when the voltage is too low. First,

a regular write sequence to the EEPROM requires a minimum voltage to operate correctly. Sec-

ondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too low.

EEPROM data corruption can easily be avoided by following this design recommendation:

Keep the AVR RESET active (low) during periods of insufficient power supply voltage. This can

be done by enabling the internal Brown-out Detector (BOD). If the detection level of the internal

BOD does not match the needed detection level, an external low V_CCreset protection circuit can

be used. If a reset occurs while a write operation is in progress, the write operation will be com-

pleted provided that the power supply voltage is sufficient.

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2586K–AVR–01/08

5.4

I/O Memory

The I/O space definition of the ATtiny25/45/85 is shown in “Register Summary” on page 203.

All ATtiny25/45/85 I/Os and peripherals are placed in the I/O space. All I/O locations may be

accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32

general purpose working registers and the I/O space. I/O Registers within the address range

0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers, the

value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the

instruction set section for more details. When using the I/O specific commands IN and OUT, the

I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space using

LD and ST instructions, 0x20 must be added to these addresses.

For compatibility with future devices, reserved bits should be written to zero if accessed.

Reserved I/O memory addresses should never be written.

Some of the Status Flags are cleared by writing a logical one to them. Note that the CBI and SBI

instructions will only operate on the specified bit, and can therefore be used on registers contain-

ing such Status Flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.

The I/O and Peripherals Control Registers are explained in later sections.

5.5

Register Description

5.5.1

EEARH and EEARL – EEPROM Address Register

Bit

7

6

5

4

3

2

1

0

EEAR8

EEAR0

0

0x1F

-

EEARH

EEARL

0x1E

EEAR7

EEAR6

EEAR5

EEAR4

EEAR3

EEAR2

EEAR1

Bit

7

R

6

R

5

R

4

R

3

R

2

R

1

R

Read/Write

Initial Value

R/W

X

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

X

• Bit 7:1 – Res6:0: Reserved Bits

These bits are reserved for future use and will always read as 0 in ATtiny25/45/85.

• Bits 8:0 – EEAR8:0: EEPROM Address

The EEPROM Address Registers – EEARH and EEARL – specifies the high EEPROM address

in the 128/256/512 bytes EEPROM space. The EEPROM data bytes are addressed linearly

between 0 and 127/255/511. The initial value of EEAR is undefined. A proper value must be writ-

ten before the EEPROM may be accessed.

5.5.2

EEDR – EEPROM Data Register

Bit

7

6

EEDR6

R/W

0

5

EEDR5

R/W

0

4

EEDR4

R/W

0

3

EEDR3

R/W

0

2

EEDR2

R/W

0

1

EEDR1

R/W

0

EEDR0

R/W

0

0x1D

EEDR7

R/W

0

EEDR

Read/Write

Initial Value

• Bits 7:0 – EEDR7:0: EEPROM Data

For the EEPROM write operation the EEDR Register contains the data to be written to the

EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the

EEDR contains the data read out from the EEPROM at the address given by EEAR.

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ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

5.5.3

EECR – EEPROM Control Register

Bit

7

–

6

–

5

EEPM1

R/W

X

4

EEPM0

R/W

X

3

EERIE

R/W

0

2

EEMPE

R/W

0

1

EEPE

R/W

X

0

EERE

R/W

0

0x1C

EECR

Read/Write

Initial Value

R

0

R

0

• Bit 7 – Res: Reserved Bit

This bit is reserved for future use and will always read as 0 in ATtiny25/45/85. For compatibility

with future AVR devices, always write this bit to zero. After reading, mask out this bit.

• Bit 6 – Res: Reserved Bit

This bit is reserved in the ATtiny25/45/85 and will always read as zero.

• Bits 5:4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits

The EEPROM Programming mode bits setting defines which programming action that will be

triggered when writing EEPE. It is possible to program data in one atomic operation (erase the

old value and program the new value) or to split the Erase and Write operations in two different

operations. The Programming times for the different modes are shown in Table 5-1. While EEPE

is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to 0b00

unless the EEPROM is busy programming.

Table 5-1.

EEPROM Mode Bits

Programming

EEPM1

EEPM0

Time

3.4 ms

1.8 ms

–

Operation

0

1

0

1

0

1

Erase and Write in one operation (Atomic Operation)

Erase Only

Write Only

Reserved for future use

• Bit 3 – EERIE: EEPROM Ready Interrupt Enable

Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing

EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant inter-

rupt when Non-volatile memory is ready for programming.

• Bit 2 – EEMPE: EEPROM Master Program Enable

The EEMPE bit determines whether writing EEPE to one will have effect or not.

When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the

selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been

written to one by software, hardware clears the bit to zero after four clock cycles.

• Bit 1 – EEPE: EEPROM Program Enable

The EEPROM Program Enable Signal EEPE is the programming enable signal to the EEPROM.

When EEPE is written, the EEPROM will be programmed according to the EEPMn bits setting.

The EEMPE bit must be written to one before a logical one is written to EEPE, otherwise no

EEPROM write takes place. When the write access time has elapsed, the EEPE bit is cleared

by hardware. When EEPE has been set, the CPU is halted for two cycles before the next

instruction is executed.

21

2586K–AVR–01/08

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the cor-

rect address is set up in the EEAR Register, the EERE bit must be written to one to trigger the

EEPROM read. The EEPROM read access takes one instruction, and the requested data is

available immediately. When the EEPROM is read, the CPU is halted for four cycles before the

next instruction is executed. The user should poll the EEPE bit before starting the read opera-

tion. If a write operation is in progress, it is neither possible to read the EEPROM, nor to change

the EEAR Register.

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ATtiny25/45/85

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ATtiny25/45/85

6. System Clock and Clock Options

6.1

Clock Systems and their Distribution

Figure 6-1 presents the principal clock systems in the AVR and their distribution. All of the clocks

need not be active at a given time. In order to reduce power consumption, the clocks to modules

not being used can be halted by using different sleep modes, as described in “Power Manage-

ment and Sleep Modes” on page 35. The clock systems are detailed below.

Figure 6-1. Clock Distribution

General I/O

Modules

Flash and

EEPROM

ADC

CPU Core

RAM

clk_PCK

clk_I/O

clk_CPU

AVR Clock

Control Unit

clk_FLASH

clk_ADC

Reset Logic

Watchdog Timer

Source clock

Watchdog clock

System Clock

Prescaler

Clock

Multiplexer

Watchdog

Oscillator

PLL

Oscillator

CalCibrryastetadl RC

Oscillator

Low-Frequency

Crystal Oscillator

Calibrated RC

Oscillator

External Clock

6.1.1

CPU Clock – clk_CPU

The CPU clock is routed to parts of the system concerned with operation of the AVR core.

Examples of such modules are the General Purpose Register File, the Status Register and the

Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing

general operations and calculations.

6.1.2

6.1.3

I/O Clock – clk_I/O

The I/O clock is used by the majority of the I/O modules, like Timer/Counter. The I/O clock is

also used by the External Interrupt module, but note that some external interrupts are detected

by asynchronous logic, allowing such interrupts to be detected even if the I/O clock is halted.

Flash Clock – clk_FLASH

The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-

taneously with the CPU clock.

23

2586K–AVR–01/08

6.1.4

6.1.5

ADC Clock – clk_ADC

The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks

in order to reduce noise generated by digital circuitry. This gives more accurate ADC conversion

results.

Internal PLL for Fast Peripheral Clock Generation - clk_PCK

The internal PLL in ATtiny25/45/85 generates a clock frequency that is 8x multiplied from a

source input. By default, the PLL uses the output of the internal, 8.0 MHz RC oscillator as

source. Alternatively, if bit LSM of PLLCSR is set the PLL will use the output of the RC oscillator

divided by two. Thus the output of the PLL, the fast peripheral clock is 64 MHz. The fast periph-

eral clock, or a clock prescaled from that, can be selected as the clock source for

Timer/Counter1 or as a system clock. See Figure 6-2. The frequency of the fast peripheral clock

is divided by two when LSM of PLLCSR is set, resulting in a clock frequency of 32 MHz. Note,

that LSM can not be set if PLL_CLKis used as system clock.

Figure 6-2. PCK Clocking System.

OSCCAL

LSM

PLLE

CKSEL3:0

CLKPS3:0

LOCK

DETECTOR

PLOCK

PCK

1/2

4 MHz

8 MHz

8.0 MHz

OSCILLATOR

PLL

8x

1/4

64 / 32 MHz

16 MHz

8 MHz

PRESCALER

XTAL1

XTAL2

SYSTEM

CLOCK

OSCILLATORS

The PLL is locked on the RC oscillator and adjusting the RC oscillator via OSCCAL register will

adjust the fast peripheral clock at the same time. However, even if the RC oscillator is taken to a

higher frequency than 8 MHz, the fast peripheral clock frequency saturates at 85 MHz (worst

case) and remains oscillating at the maximum frequency. It should be noted that the PLL in this

case is not locked any longer with the RC oscillator clock. Therefore, it is recommended not to

take the OSCCAL adjustments to a higher frequency than 8 MHz in order to keep the PLL in the

correct operating range.

The internal PLL is enabled when:

• The PLLE bit in the register PLLCSR is set.

• The CKSEL fuse is programmed to ‘0001’.

• The CKSEL fuse is programmed to ‘0011’.

The PLLCSR bit PLOCK is set when PLL is locked.

Both internal RC oscillator and PLL are switched off in power down and stand-by sleep modes.

6.1.6

Internal PLL in ATtiny15 Compatibility Mode

Since ATtiny25/45/85 is a migration device for ATtiny15 users there is an ATtiny15 compatibility

mode for backward compatibility. The ATtiny15 compatibility mode is selected by programming

the CKSEL fuses to ‘0011’.

24

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

In the ATtiny15 compatibility mode the frequency of the internal RC oscillator is calibrated down

to 6.4 MHz and the multiplication factor of the PLL is set to 4x. See Figure 6-3. With these

adjustments the clocking system is ATtiny15-compatible and the resulting fast peripheral clock

has a frequency of 25.6 MHz (same as in ATtiny15).

Figure 6-3. PCK Clocking System in ATtiny15 Compatibility Mode.

OSCCAL

PLLE

PLL

8x

25.6 MHz

PCK

1/2

3.2 MHz

LOCK

DETECTOR

6.4 MHz

OSCILLATOR

PLOCK

1/4

1.6 MHz

SYSTEM

CLOCK

Note that low speed mode is not implemented in ATtiny15 compatibility mode.

6.2

Clock Sources

The device has the following clock source options, selectable by Flash Fuse bits as shown

below. The clock from the selected source is input to the AVR clock generator, and routed to the

appropriate modules.

Table 6-1.

Device Clocking Options Select

Device Clocking Option

CKSEL3:0⁽¹⁾

0000

External Clock (see page 26)

High Frequency PLL Clock (see page 26)

Calibrated Internal Oscillator (see page 27)

Internal 128 kHz Oscillator (see page 29)

Low-Frequency Crystal Oscillator (see page 29)

Crystal Oscillator / Ceramic Resonator (see page 29)

Reserved

0001

0010⁽²⁾

0011⁽³⁾

0100

0110

1000 – 1111

0101, 0111

Note:

1. For all fuses “1” means unprogrammed while “0” means programmed.

2. The device is shipped with this option selected.

3. This will select ATtiny15 Compatibility Mode, where system clock is divided by four, resulting in

a 1.6 MHz clock frequency. For more inormation, see “Calibrated Internal Oscillator” on page

27.

The various choices for each clocking option is given in the following sections. When the CPU

wakes up from Power-down, the selected clock source is used to time the start-up, ensuring sta-

ble Oscillator operation before instruction execution starts. When the CPU starts from reset,

there is an additional delay allowing the power to reach a stable level before commencing nor-

25

2586K–AVR–01/08

mal operation. The Watchdog Oscillator is used for timing this real-time part of the start-up time.

The number of WDT Oscillator cycles used for each time-out is shown in Table 6-2.

Table 6-2.

Number of Watchdog Oscillator Cycles

Typ Time-out

4 ms

Number of Cycles

512

64 ms

8K (8,192)

6.2.1

External Clock

To drive the device from an external clock source, CLKI should be driven as shown in Figure 6-

4. To run the device on an external clock, the CKSEL Fuses must be programmed to “00”.

Figure 6-4. External Clock Drive Configuration

EXTERNAL

CLKI

GND

CLOCK

SIGNAL

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 6-3.

Start-up Times for the External Clock Selection

Start-up Time from

Power-down

Additional Delay from

Reset

SUT1:0

00

Recommended Usage

BOD enabled

6 CK

14CK

14CK + 4 ms

14CK + 64 ms

Reserved

01

Fast rising power

Slowly rising power

10

11

When applying an external clock, it is required to avoid sudden changes in the applied clock fre-

quency to ensure stable operation of the MCU. A variation in frequency of more than 2% from

one clock cycle to the next can lead to unpredictable behavior. It is required to ensure that the

MCU is kept in Reset during such changes in the clock frequency.

Note that the System Clock Prescaler can be used to implement run-time changes of the internal

clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on page

31 for details.

6.2.2

High Frequency PLL Clock

There is an internal PLL that provides nominally 64 MHz clock rate locked to the RC Oscillator

for the use of the Peripheral Timer/Counter1 and for the system clock source. When selected as

26

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

a system clock source, by programming the CKSEL fuses to ‘0001’, it is divided by four like

shown in Table 6-4.

Table 6-4.

High Frequency PLL Clock Operating Modes

CKSEL3:0

Nominal Frequency

16 MHz

0001

When this clock source is selected, start-up times are determined by the SUT fuses as shown in

Table 6-5.

Start-up Times for the High Frequency PLL Clock

Start-up Time from

Power Down

Additional Delay from

Recommended

usage

SUT1:0

00

Power-On Reset (V_CC= 5.0V)

14CK + 1K (1024) CK + 4 ms

14CK + 16K (16384) CK + 4 ms

14CK + 1K (1024) CK + 64 ms

14CK + 16K (16384) CK + 64 ms

4 ms

BOD enabled

01

Fast rising power

Slowly rising power

10

11

6.2.3

Calibrated Internal Oscillator

By default, the Internal RC Oscillator provides an approximate 8.0 MHz clock. Though voltage

and temperature dependent, this clock can be very accurately calibrated by the user. See “Cali-

brated Internal RC Oscillator Accuracy” on page 169 and “Internal Oscillator Speed” on page

195 for more details. The device is shipped with the CKDIV8 Fuse programmed. See “System

Clock Prescaler” on page 31 for more details.

This clock may be selected as the system clock by programming the CKSEL Fuses as shown in

Table 6-6 on page 28. If selected, it will operate with no external components. During reset,

hardware loads the pre-programmed calibration value into the OSCCAL Register and thereby

automatically calibrates the RC Oscillator. The accuracy of this calibration is shown as Factory

calibration in Table 21-2 on page 169.

By changing the OSCCAL register from SW, see “OSCCAL – Oscillator Calibration Register” on

page 32, it is possible to get a higher calibration accuracy than by using the factory calibration.

The accuracy of this calibration is shown as User calibration in Table 21-2 on page 169.

When this Oscillator is used as the chip clock, the Watchdog Oscillator will still be used for the

Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed cali-

bration value, see the section “Calibration Bytes” on page 154.

The internal oscillator can also be set to provide a 6.4 MHz clock by writing CKSEL fuses to

“0011”, as shown in Table 6-6 below. This setting is reffered to as ATtiny15 Compatibility Mode

and is intended to provide a calibrated clock source at 6.4 MHz, as in ATtiny15. In ATtiny15

Compatibility Mode the PLL uses the internal oscillator running at 6.4 MHz to generate a 25.6

MHz peripheral clock signal for Timer/Counter1 (see “8-bit Timer/Counter1 in ATtiny15 Mode”

27

2586K–AVR–01/08

on page 98). Note that in this mode of operation the 6.4 MHz clock signal is always divided by

four, providing a 1.6 MHz system clock.

Table 6-6.

Internal Calibrated RC Oscillator Operating Modes

CKSEL3:0

0010⁽¹⁾

Nominal Frequency

8.0 MHz

6.4 MHz

0011⁽²⁾

Note:

1. The device is shipped with this option selected.

2. This setting will select ATtiny15 Compatibility Mode, where system clock is divided by four,

resulting in a 1.6 MHz clock frequency.

When the calibrated 8 MHz internal oscillator is selected as clock source the start-up times are

determined by the SUT Fuses as shown in Table 6-7 below.

Table 6-7.

Start-up Times for Internal Calibrated RC Oscillator Clock

Start-up Time

from Power-down

Additional Delay from

Reset (V_CC= 5.0V)

SUT1:0

00

Recommended Usage

BOD enabled

6 CK

14CK⁽¹⁾

14CK + 4 ms

14CK + 64 ms

Reserved

01

Fast rising power

Slowly rising power

10⁽²⁾

11

Note:

1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to

ensure programming mode can be entered.

2. The device is shipped with this option selected.

In ATtiny15 Compatibility Mode start-up times are determined by SUT fuses as shown in Table

6-8 below..

Table 6-8.

Start-up Times for Internal Calibrated RC Oscillator Clock (in ATtiny15 Mode)

Start-up Time

from Power-down

Additional Delay from

Reset (V_CC= 5.0V)

SUT1:0

00

Recommended Usage

6 CK

1 CK

14CK + 64 ms

14CK + 4 ms

14CK⁽¹⁾

01

10

11

Note:

1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to

ensure programming mode can be entered.

In summary, more information on ATtiny15 Compatibility Mode can be found in sections “Port B

(PB5..PB0)” on page 2, “Internal PLL in ATtiny15 Compatibility Mode” on page 24, “8-bit

Timer/Counter1 in ATtiny15 Mode” on page 98, “Limitations of debugWIRE” on page 144, “Cali-

bration Bytes” on page 154 and in table “Clock Prescaler Select” on page 34.

28

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

6.2.4

Internal 128 kHz Oscillator

The 128 kHz internal Oscillator is a low power Oscillator providing a clock of 128 kHz. The fre-

quency is nominal at 3V and 25°C. This clock may be select as the system clock by

programming the CKSEL Fuses to “0100”.

When this clock source is selected, start-up times are determined by the SUT Fuses as shown in

Table 6-9.

Start-up Times for the 128 kHz Internal Oscillator

Start-up Time from

Power-down

Additional Delay from

Reset

SUT1:0

00

Recommended Usage

BOD enabled

6 CK

14CK⁽¹⁾

14CK + 4 ms

14CK + 64 ms

Reserved

01

Fast rising power

Slowly rising power

10

11

Note:

1. If the RSTDISBL fuse is programmed, this start-up time will be increased to 14CK + 4 ms to

ensure programming mode can be entered.

6.2.5

Low-Frequency Crystal Oscillator

To use a 32.768 kHz watch crystal as the clock source for the device, the low-frequency crystal

oscillator must be selected by setting CKSEL fuses to ‘0110’. The crystal should be connected

as shown in Figure 6-5. To find suitable load capacitance for a 32.768 kHz crysal, please consult

the manufacturer’s datasheet.

When this oscillator is selected, start-up times are determined by the SUT fuses as shown in

Table 6-10.

Table 6-10. Start-up Times for the Low Frequency Crystal Oscillator Clock Selection

Start-up Time from

Power Down

Additional Delay from

Reset (V_CC= 5.0V)

SUT1:0

Recommended usage

Fast rising power or BOD

enabled

00

1K (1024) CK⁽¹⁾

4 ms

01

10

11

1K (1024) CK⁽¹⁾

32K (32768) CK

64 ms

Slowly rising power

64 ms

Stable frequency at start-up

Reserved

Notes: 1. These options should only be used if frequency stability at start-up is not important for the

application.

6.2.6

Crystal Oscillator / Ceramic Resonator

XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be con-

figured for use as an On-chip Oscillator, as shown in Figure 6-5. Either a quartz crystal or a

ceramic resonator may be used.

29

2586K–AVR–01/08

Figure 6-5. Crystal Oscillator Connections

C2

XTAL2

XTAL1

GND

C1

C1 and C2 should always be equal for both crystals and resonators. The optimal value of the

capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the

electromagnetic noise of the environment. Some initial guidelines for choosing capacitors for

use with crystals are given in Table 6-11 below. For ceramic resonators, the capacitor values

given by the manufacturer should be used.

Table 6-11. Crystal Oscillator Operating Modes

Recommended Range for Capacitors C1 and

CKSEL3:1

100⁽¹⁾

101

Frequency Range (MHz)

C2 for Use with Crystals (pF)

0.4 - 0.9

0.9 - 3.0

3.0 - 8.0

8.0 -

–

12 - 22

110

111

Notes: 1. This option should not be used with crystals, only with ceramic resonators.

The Oscillator can operate in three different modes, each optimized for a specific frequency

range. The operating mode is selected by the fuses CKSEL3..1 as shown in Table 6-11.

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in Table

6-12.

Table 6-12. Start-up Times for the Crystal Oscillator Clock Selection

Start-up Time from

Power-down

Additional Delay

from Reset

CKSEL0

SUT1:0

Recommended Usage

Ceramic resonator,

fast rising power

0

00

258 CK⁽¹⁾

14CK + 4 ms

14CK + 64 ms

14CK

Ceramic resonator,

slowly rising power

0

1

01

10

11

00

Ceramic resonator,

BOD enabled

1K (1024) CK⁽²⁾

1K (1024)CK⁽²⁾

Ceramic resonator,

fast rising power

14CK + 4 ms

14CK + 64 ms

Ceramic resonator,

slowly rising power

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ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

Table 6-12. Start-up Times for the Crystal Oscillator Clock Selection (Continued)

Start-up Time from

Power-down

Additional Delay

from Reset

CKSEL0

SUT1:0

Recommended Usage

Crystal Oscillator,

BOD enabled

1

01

16K (16384) CK

14CK

Crystal Oscillator,

fast rising power

1

10

11

14CK + 4 ms

14CK + 64 ms

Crystal Oscillator,

slowly rising power

Notes: 1. These options should only be used when not operating close to the maximum frequency of the

device, and only if frequency stability at start-up is not important for the application. These

options are not suitable for crystals.

2. These options are intended for use with ceramic resonators and will ensure frequency stability

at start-up. They can also be used with crystals when not operating close to the maximum fre-

quency of the device, and if frequency stability at start-up is not important for the application.

6.2.7

Default Clock Source

The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default

clock source setting is therefore the Internal RC Oscillator running at 8 MHz with longest start-up

time and an initial system clock prescaling of 8, resulting in 1.0 MHz system clock. This default

setting ensures that all users can make their desired clock source setting using an In-System or

High-voltage Programmer.

6.3

System Clock Prescaler

The ATtiny25/45/85 system clock can be divided by setting the “CLKPR – Clock Prescale Regis-

ter” on page 33. This feature can be used to decrease power consumption when the

requirement for processing power is low. This can be used with all clock source options, and it

will affect the clock frequency of the CPU and all synchronous peripherals. clk_I/O, clk_ADC, clk_CPU

and clk_FLASHare divided by a factor as shown in Table 6-14 on page 34.

,

6.3.1

Switching Time

When switching between prescaler settings, the System Clock Prescaler ensures that no

glitches occur in the clock system and that no intermediate frequency is higher than neither the

clock frequency corresponding to the previous setting, nor the clock frequency corresponding to

the new setting.

The ripple counter that implements the prescaler runs at the frequency of the undivided clock,

which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the

state of the prescaler – even if it were readable, and the exact time it takes to switch from one

clock division to another cannot be exactly predicted.

From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before the

new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1 is the

previous clock period, and T2 is the period corresponding to the new prescaler setting.

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2586K–AVR–01/08

6.4

Clock Output Buffer

The device can output the system clock on the CLKO pin (when not used as XTAL2 pin). To

enable the output, the CKOUT Fuse has to be programmed. This mode is suitable when the chip

clock is used to drive other circuits on the system. Note that the clock will not be output during

reset and that the normal operation of the I/O pin will be overridden when the fuse is pro-

grammed. Any clock source, including the internal RC Oscillator, can be selected when the clock

is output on CLKO. If the System Clock Prescaler is used, it is the divided system clock that is

output.

6.5

Register Description

6.5.1

OSCCAL – Oscillator Calibration Register

Bit

7

6

5

4

3

2

1

0

0x31

CAL7

R/W

CAL6

R/W

CAL5

R/W

CAL4

R/W

CAL3

R/W

CAL2

R/W

CAL1

R/W

CAL0

R/W

OSCCAL

Read/Write

Initial Value

Device Specific Calibration Value

• Bits 7:0 – CAL7:0: Oscillator Calibration Value

The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to

remove process variations from the oscillator frequency. A pre-programmed calibration value is

automatically written to this register during chip reset, giving the Factory calibrated frequency as

specified in Table 21-2 on page 169. The application software can write this register to change

the oscillator frequency. The oscillator can be calibrated to frequencies as specified in Table 21-

2 on page 169. Calibration outside that range is not guaranteed.

Note that this oscillator is used to time EEPROM and Flash write accesses, and these write

times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to more

than 8.8 MHz. Otherwise, the EEPROM or Flash write may fail.

The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the

lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-

quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher

frequency than OSCCAL = 0x80.

The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00

gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in the

range.

To ensure stable operation of the MCU the calibration value should be changed in small. A vari-

ation in frequency of more than 2% from one cycle to the next can lead to unpredicatble

behavior. Changes in OSCCAL should not exceed 0x20 for each calibration. It is required to

ensure that the MCU is kept in Reset during such changes in the clock frequency

Table 6-13. Internal RC Oscillator Frequency Range

Typical Lowest Frequency

Typical Highest Frequency

OSCCAL Value

0x00

with Respect to Nominal Frequency

50%

75%

100%

150%

200%

0x3F

0x7F

100%

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ATtiny25/45/85

6.5.2

CLKPR – Clock Prescale Register

Bit

7

6

–

R

0

5

–

R

0

4

–

R

0

3

2

1

0

0x26

CLKPCE

CLKPS3

R/W

CLKPS2

R/W

CLKPS1

R/W

CLKPS0

R/W

CLKPR

Read/Write

Initial Value

R/W

0

See Bit Description

• Bit 7 – CLKPCE: Clock Prescaler Change Enable

The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLKPCE

bit is only updated when the other bits in CLKPR are simultaniosly written to zero. CLKPCE is

cleared by hardware four cycles after it is written or when the CLKPS bits are written. Rewriting

the CLKPCE bit within this time-out period does neither extend the time-out period, nor clear the

CLKPCE bit.

• Bits 6:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3 - 0

These bits define the division factor between the selected clock source and the internal system

clock. These bits can be written run-time to vary the clock frequency to suit the application

requirements. As the divider divides the master clock input to the MCU, the speed of all synchro-

nous peripherals is reduced when a division factor is used. The division factors are given in

Table 6-14.

To avoid unintentional changes of clock frequency, a special write procedure must be followed

to change the CLKPS bits:

1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in

CLKPR to zero.

2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.

Interrupts must be disabled when changing prescaler setting to make sure the write procedure is

not interrupted.

The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,

the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to

“0011”, giving a division factor of eight at start up. This feature should be used if the selected

clock source has a higher frequency than the maximum frequency of the device at the present

operating conditions. Note that any value can be written to the CLKPS bits regardless of the

CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is

chosen if the selcted clock source has a higher frequency than the maximum frequency of the

33

2586K–AVR–01/08

device at the present operating conditions. The device is shipped with the CKDIV8 Fuse

programmed.

Table 6-14. Clock Prescaler Select

CLKPS3

CLKPS2

CLKPS1

CLKPS0

Clock Division Factor

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2

4

8

16

32

64

128

256

Reserved

Note:

The prescaler is disabled in ATtiny15 compatibility mode and neither writing to CLKPR, nor pro-

gramming the CKDIV8 fuse has any effect on the system clock (which will always be 1.6 MHz).

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ATtiny25/45/85

7. Power Management and Sleep Modes

The high performance and industry leading code efficiency makes the AVR microcontrollers an

ideal choise for low power applications. In addition, sleep modes enable the application to shut

down unused modules in the MCU, thereby saving power. The AVR provides various sleep

modes allowing the user to tailor the power consumption to the application’s requirements.

7.1

Sleep Modes

Figure 6-1 on page 23 presents the different clock systems and their distribution in

ATtiny25/45/85. The figure is helpful in selecting an appropriate sleep mode. Table 7-1 shows

the different sleep modes and their wake up sources.

Table 7-1.

Active Clock Domains and Wake-up Sources in the Different Sleep Modes

Active Clock Domains

Oscillators

Wake-up Sources

Sleep Mode

Idle

X

ADC Noise

Reduction

X⁽¹⁾

Power-down

Note:

1. For INT0, only level interrupt.

To enter any of the three sleep modes, the SE bit in MCUCR must be written to logic one and a

SLEEP instruction must be executed. The SM1:0 bits in the MCUCR Register select which sleep

mode (Idle, ADC Noise Reduction or Power-down) will be activated by the SLEEP instruction.

See Table 7-2 for a summary.

If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU

is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and

resumes execution from the instruction following SLEEP. The contents of the Register File and

SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,

the MCU wakes up and executes from the Reset Vector.

Note that if a level triggered interrupt is used for wake-up the changed level must be held for

some time to wake up the MCU (and for the MCU to enter the interrupt service routine). See

“External Interrupts” on page 51 for details.

7.1.1

Idle Mode

When the SM1:0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle mode,

stopping the CPU but allowing Analog Comparator, ADC, USI, Timer/Counter, Watchdog, and

the interrupt system to continue operating. This sleep mode basically halts clk_CPUand clk_FLASH

while allowing the other clocks to run.

,

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow. If wake-up from the Analog Comparator interrupt is not required,

35

2586K–AVR–01/08

the Analog Comparator can be powered down by setting the ACD bit in “ACSR – Analog Com-

parator Control and Status Register” on page 124. This will reduce power consumption in Idle

mode. If the ADC is enabled, a conversion starts automatically when this mode is entered.

7.1.2

ADC Noise Reduction Mode

When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC Noise

Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, and the

Watchdog to continue operating (if enabled). This sleep mode halts clk_I/O, clk_CPU, and clk_FLASH

while allowing the other clocks to run.

,

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out

Reset, an SPM/EEPROM ready interrupt, an external level interrupt on INT0 or a pin change

interrupt can wake up the MCU from ADC Noise Reduction mode.

7.1.3

Power-down Mode

When the SM1:0 bits are written to 10, the SLEEP instruction makes the MCU enter Power-

down mode. In this mode, the Oscillator is stopped, while the external interrupts, the USI start

condition detection and the Watchdog continue operating (if enabled). Only an External Reset, a

Watchdog Reset, a Brown-out Reset, USI start condition interupt, an external level interrupt on

INT0 or a pin change interrupt can wake up the MCU. This sleep mode halts all generated

clocks, allowing operation of asynchronous modules only.

7.2

Software BOD Disable

When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses (see Table 20-4 on page

152), the BOD is actively monitoring the supply voltage during a sleep period. In some devices it

is possible to save power by disabling the BOD by software in Power-Down sleep mode. The

sleep mode power consumption will then be at the same level as when BOD is globally disabled

by fuses.

If BOD is disabled by software, the BOD function is turned off immediately after entering the

sleep mode. Upon wake-up from sleep, BOD is automatically enabled again. This ensures safe

operation in case the V_CClevel has dropped during the sleep period.

When the BOD has been disabled, the wake-up time from sleep mode will be the same as that

for wakeing up from RESET. The user must manually configure the wake up times such that the

bandgap reference has time to start and the BOD is working correctly before the MCU continues

executing code. See SUT1:0 and CKSEL3:0 fuse bits in table “Fuse Low Byte” on page 153

BOD disable is controlled by the BODS (BOD Sleep) bit of MCU Control Register, see “MCUCR

– MCU Control Register” on page 38. Writing this bit to one turns off BOD in Power-Down, while

writing a zero keeps the BOD active. The default setting is zero, i.e. BOD active.

Writing to the BODS bit is controlled by a timed sequence and an enable bit, see “MCUCR –

MCU Control Register” on page 38.

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ATtiny25/45/85

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ATtiny25/45/85

7.2.1

Limitations

BOD disable functionality has been implemented in the following devices, only:

• ATtiny25, revision E, and newer

• ATtiny45, all revisions

• ATtiny85, revision C, and newer

Revisions are marked on the device package and can be located as follows:

• Bottom side of packages 8P3 and 8S2

• Top side of package 20M1

7.3

Power Reduction Register

The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 39, pro-

vides a method to reduce power consumption by stopping the clock to individual peripherals.

The current state of the peripheral is frozen and the I/O registers can not be read or written.

Resources used by the peripheral when stopping the clock will remain occupied, hence the

peripheral should in most cases be disabled before stopping the clock. Waking up a module,

which is done by clearing the bit in PRR, puts the module in the same state as before shutdown.

Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall

power consumption. In all other sleep modes, the clock is already stopped. See “Supply Current

of I/O modules” on page 181 for examples.

7.4

Minimizing Power Consumption

There are several issues to consider when trying to minimize the power consumption in an AVR

controlled system. In general, sleep modes should be used as much as possible, and the sleep

mode should be selected so that as few as possible of the device’s functions are operating. All

functions not needed should be disabled. In particular, the following modules may need special

consideration when trying to achieve the lowest possible power consumption.

7.4.1

7.4.2

Analog to Digital Converter

If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-

abled before entering any sleep mode. When the ADC is turned off and on again, the next

conversion will be an extended conversion. Refer to “Analog to Digital Converter” on page 126

for details on ADC operation.

Analog Comparator

When entering Idle mode, the Analog Comparator should be disabled if not used. When entering

ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep

modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is

set up to use the Internal Voltage Reference as input, the Analog Comparator should be dis-

abled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled,

independent of sleep mode. Refer to “Analog Comparator” on page 123 for details on how to

configure the Analog Comparator.

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2586K–AVR–01/08

7.4.3

7.4.4

Brown-out Detector

If the Brown-out Detector is not needed in the application, this module should be turned off. If the

Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep modes,

and hence, always consume power. In the deeper sleep modes, this will contribute significantly

to the total current consumption. See “Brown-out Detection” on page 43 and “Software BOD Dis-

able” on page 36 for details on how to configure the Brown-out Detector.

Internal Voltage Reference

The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the

Analog Comparator or the ADC. If these modules are disabled as described in the sections

above, the internal voltage reference will be disabled and it will not be consuming power. When

turned on again, the user must allow the reference to start up before the output is used. If the

reference is kept on in sleep mode, the output can be used immediately. Refer to “Internal Volt-

age Reference” on page 44 for details on the start-up time.

7.4.5

7.4.6

Watchdog Timer

If the Watchdog Timer is not needed in the application, this module should be turned off. If the

Watchdog Timer is enabled, it will be enabled in all sleep modes, and hence, always consume

power. In the deeper sleep modes, this will contribute significantly to the total current consump-

tion. Refer to “Watchdog Timer” on page 44 for details on how to configure the Watchdog Timer.

Port Pins

When entering a sleep mode, all port pins should be configured to use minimum power. The

most important thing is then to ensure that no pins drive resistive loads. In sleep modes where

both the I/O clock (clk_I/O) and the ADC clock (clk_ADC) are stopped, the input buffers of the device

will be disabled. This ensures that no power is consumed by the input logic when not needed. In

some cases, the input logic is needed for detecting wake-up conditions, and it will then be

enabled. Refer to the section “Digital Input Enable and Sleep Modes” on page 59 for details on

which pins are enabled. If the input buffer is enabled and the input signal is left floating or has an

analog signal level close to V_CC/2, the input buffer will use excessive power.

For analog input pins, the digital input buffer should be disabled at all times. An analog signal

level close to V_CC/2 on an input pin can cause significant current even in active mode. Digital

input buffers can be disabled by writing to the Digital Input Disable Register (DIDR0). Refer to

“DIDR0 – Digital Input Disable Register 0” on page 125 for details.

7.5

Register Description

7.5.1

MCUCR – MCU Control Register

The MCU Control Register contains control bits for power management.

Bit

7

6

5

4

3

2

1

0

0x35

BODS

PUD

R/W

0

SE

R/W

0

SM1

R/W

0

SM0

R/W

0

BODSE

ISC01

R/W

0

ISC00

R/W

0

MCUCR

Read/Write

Initial Value

R

0

R

0

• Bit 7 – BODS: BOD Sleep

BOD disable functionality is available in some devices, only. See “Limitations” on page 37.

In order to disable BOD during sleep (see Table 7-1 on page 35) the BODS bit must be written to

logic one. This is controlled by a timed sequence and the enable bit, BODSE in MCUCR. First,

38

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

both BODS and BODSE must be set to one. Second, within four clock cycles, BODS must be

set to one and BODSE must be set to zero. The BODS bit is active three clock cycles after it is

set. A sleep instruction must be executed while BODS is active in order to turn off the BOD for

the actual sleep mode. The BODS bit is automatically cleared after three clock cycles.

In devices where Sleeping BOD has not been implemented this bit is unused and will always

read zero.

• Bit 5 – SE: Sleep Enable

The SE bit must be written to logic one to make the MCU enter the sleep mode when the SLEEP

instruction is executed. To avoid the MCU entering the sleep mode unless it is the programmer’s

purpose, it is recommended to write the Sleep Enable (SE) bit to one just before the execution of

the SLEEP instruction and to clear it immediately after waking up.

• Bits 4, 3 – SM1:0: Sleep Mode Select Bits 2..0

These bits select between the three available sleep modes as shown in Table 7-2.

Table 7-2.

SM1

Sleep Mode Select

SM0

Sleep Mode

Idle

0

1

0

1

0

1

ADC Noise Reduction

Power-down

Reserved

• Bit 2 – BODSE: BOD Sleep Enable

BOD disable functionality is available in some devices, only. See “Limitations” on page 37.

The BODSE bit enables setting of BODS control bit, as explained on BODS bit description. BOD

disable is controlled by a timed sequence.

This bit is unused in devices where software BOD disable has not been implemented and will

read as zero in those devices.

7.5.2

PRR – Power Reduction Register

The Power Reduction Register provides a method to reduce power consumption by allowing

peripheral clock signals to be disabled..

Bit

7

–

R

0

6

-

5

-

4

-

3

2

1

0

0x20

PRTIM1

R/W

0

PRTIM0

R/W

0

PRUSI

R/W

0

PRADC

R/W

0

PRR

Read/Write

Initial Value

R

0

R

0

R

0

• Bits 7:4- Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bit 3- PRTIM1: Power Reduction Timer/Counter1

Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1

is enabled, operation will continue like before the shutdown.

39

2586K–AVR–01/08

• Bit 2- PRTIM0: Power Reduction Timer/Counter0

Writing a logic one to this bit shuts down the Timer/Counter0 module. When the Timer/Counter0

is enabled, operation will continue like before the shutdown.

• Bit 1 - PRUSI: Power Reduction USI

Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When

waking up the USI again, the USI should be re initialized to ensure proper operation.

• Bit 0 - PRADC: Power Reduction ADC

Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut down.

Note that the ADC clock is also used by some parts of the analog comparator, which means that

the analogue comparator can not be used when this bit is high.

40

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ATtiny25/45/85

8. System Control and Reset

8.1

Resetting the AVR

During reset, all I/O Registers are set to their initial values, and the program starts execution

from the Reset Vector. The instruction placed at the Reset Vector must be a RJMP – Relative

Jump – instruction to the reset handling routine. If the program never enables an interrupt

source, the Interrupt Vectors are not used, and regular program code can be placed at these

locations. The circuit diagram in Figure 8-1 shows the reset logic. Electrical parameters of the

reset circuitry are given in “System and Reset Characteristics” on page 170.

Figure 8-1. Reset Logic

DATA BUS

MCU Status

Register (MCUSR)

Power-on Reset

Circuit

Brown-out

BODLEVEL [2..0]

Reset Circuit

Pull-up Resistor

SPIKE

FILTER

Watchdog

Oscillator

Delay Counters

Clock

CK

Generator

TIMEOUT

CKSEL[3:0]

SUT[1:0]

The I/O ports of the AVR are immediately reset to their initial state when a reset source goes

active. This does not require any clock source to be running.

After all reset sources have gone inactive, a delay counter is invoked, stretching the internal

reset. This allows the power to reach a stable level before normal operation starts. The time-out

period of the delay counter is defined by the user through the SUT and CKSEL Fuses. The dif-

ferent selections for the delay period are presented in “Clock Sources” on page 25.

8.2

Reset Sources

The ATtiny25/45/85 has four sources of reset:

• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset

threshold (V_POT).

• External Reset. The MCU is reset when a low level is present on the RESET pin for longer

than the minimum pulse length.

• Watchdog Reset. The MCU is reset when the Watchdog Timer period expires and the

Watchdog is enabled.

• Brown-out Reset. The MCU is reset when the supply voltage V_CCis below the Brown-out

Reset threshold (V_BOT) and the Brown-out Detector is enabled.

41

2586K–AVR–01/08

8.2.1

Power-on Reset

A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level

is defined in “System and Reset Characteristics” on page 170. The POR is activated whenever

_CCis below the detection level. The POR circuit can be used to trigger the Start-up Reset, as

V

well as to detect a failure in supply voltage.

A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the

Power-on Reset threshold voltage invokes the delay counter, which determines how long the

device is kept in RESET after V_CCrise. The RESET signal is activated again, without any delay,

when V_CCdecreases below the detection level.

Figure 8-2. MCU Start-up, RESET Tied to V_CC

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

Figure 8-3. MCU Start-up, RESET Extended Externally

V_POT

V_CC

V_RST

RESET

t_TOUT

TIME-OUT

INTERNAL

RESET

8.2.2

External Reset

An External Reset is generated by a low level on the RESET pin if enabled. Reset pulses longer

than the minimum pulse width (see “System and Reset Characteristics” on page 170) will gener-

ate a reset, even if the clock is not running. Shorter pulses are not guaranteed to generate a

reset. When the applied signal reaches the Reset Threshold Voltage – V_RST– on its positive

edge, the delay counter starts the MCU after the Time-out period – t_TOUT– has expired.

42

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

Figure 8-4. External Reset During Operation

CC

8.2.3

Brown-out Detection

ATtiny25/45/85 has an On-chip Brown-out Detection (BOD) circuit for monitoring the V_CClevel

during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be

selected by the BODLEVEL Fuses. The trigger level has a hysteresis to ensure spike free

Brown-out Detection. The hysteresis on the detection level should be interpreted as V_BOT+

_BOT+ V_HYST/2 and V_BOT-= V_BOT- V_HYST/2.

=

V

When the BOD is enabled, and V_CCdecreases to a value below the trigger level (V_BOT-in Figure

8-5), the Brown-out Reset is immediately activated. When V_CCincreases above the trigger level

(V_BOT+in Figure 8-5), the delay counter starts the MCU after the Time-out period t_TOUThas

expired.

The BOD circuit will only detect a drop in V_CCif the voltage stays below the trigger level for

longer than t_BODgiven in “System and Reset Characteristics” on page 170.

Figure 8-5. Brown-out Reset During Operation

V_BOT+

V_CC

V_BOT-

RESET

t

TOUT

TIME-OUT

INTERNAL

RESET

8.2.4

Watchdog Reset

When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On

the falling edge of this pulse, the delay timer starts counting the Time-out period t_TOUT. Refer to

“Watchdog Timer” on page 44 for details on operation of the Watchdog Timer.

43

2586K–AVR–01/08

Figure 8-6. Watchdog Reset During Operation

CC

CK

8.3

Internal Voltage Reference

ATtiny25/45/85 features an internal bandgap reference. This reference is used for Brown-out

Detection, and it can be used as an input to the Analog Comparator or the ADC.

8.3.1

Voltage Reference Enable Signals and Start-up Time

The voltage reference has a start-up time that may influence the way it should be used. The

start-up time is given in “System and Reset Characteristics” on page 170. To save power, the

reference is not always turned on. The reference is on during the following situations:

1. When the BOD is enabled (by programming the BODLEVEL [2..0] Fuse Bits).

2. When the bandgap reference is connected to the Analog Comparator (by setting the

ACBG bit in ACSR).

3. When the ADC is enabled.

Thus, when the BOD is not enabled, after setting the ACBG bit or enabling the ADC, the user

must always allow the reference to start up before the output from the Analog Comparator or

ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three

conditions above to ensure that the reference is turned off before entering Power-down mode.

8.4

Watchdog Timer

The Watchdog Timer is clocked from an On-chip Oscillator which runs at 128 kHz. By controlling

the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as shown in Table

8-3 on page 49. The WDR – Watchdog Reset – instruction resets the Watchdog Timer. The

Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs. Ten different

clock cycle periods can be selected to determine the reset period. If the reset period expires

without another Watchdog Reset, the ATtiny25/45/85 resets and executes from the Reset Vec-

tor. For timing details on the Watchdog Reset, refer to Table 8-3 on page 49.

The Wathdog Timer can also be configured to generate an interrupt instead of a reset. This can

be very helpful when using the Watchdog to wake-up from Power-down.

To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,

two different safety levels are selected by the fuse WDTON as shown in Table 8-1 Refer to

44

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

“Timed Sequences for Changing the Configuration of the Watchdog Timer” on page 45 for

details.

Table 8-1.

WDT Configuration as a Function of the Fuse Settings of WDTON

Safety

Level

WDT Initial

State

How to Disable the

WDT

How to Change Time-

out

WDTON

Unprogrammed

Programmed

1

2

Disabled

Enabled

Timed sequence

Always enabled

No limitations

Timed sequence

Figure 8-7. Watchdog Timer

WATCHDOG

128 kHz

PRESCALER

OSCILLATOR

WATCHDOG

RESET

WDP0

WDP1

WDP2

WDP3

WDE

MCU RESET

8.4.1

Timed Sequences for Changing the Configuration of the Watchdog Timer

The sequence for changing configuration differs slightly between the two safety levels. Separate

procedures are described for each level.

8.4.1.1

Safety Level 1

In this mode, the Watchdog Timer is initially disabled, but can be enabled by writing the WDE bit

to one without any restriction. A timed sequence is needed when disabling an enabled Watch-

dog Timer. To disable an enabled Watchdog Timer, the following procedure must be followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be writ-

ten to WDE regardless of the previous value of the WDE bit.

2. Within the next four clock cycles, in the same operation, write the WDE and WDP bits

as desired, but with the WDCE bit cleared.

8.4.1.2

Safety Level 2

In this mode, the Watchdog Timer is always enabled, and the WDE bit will always read as one. A

timed sequence is needed when changing the Watchdog Time-out period. To change the

Watchdog Time-out, the following procedure must be followed:

1. In the same operation, write a logical one to WDCE and WDE. Even though the WDE

always is set, the WDE must be written to one to start the timed sequence.

2. Within the next four clock cycles, in the same operation, write the WDP bits as desired,

but with the WDCE bit cleared. The value written to the WDE bit is irrelevant.

45

2586K–AVR–01/08

8.4.2

Code Example

The following code example shows one assembly and one C function for turning off the WDT.

The example assumes that interrupts are controlled (e.g., by disabling interrupts globally) so that

no interrupts will occur during execution of these functions.

Assembly Code Example⁽¹⁾

WDT_off:

wdr

; Clear WDRF in MCUSR

ldi r16, (0<<WDRF)

out MCUSR, r16

; Write logical one to WDCE and WDE

; Keep old prescaler setting to prevent unintentional Watchdog Reset

in r16, WDTCSR

ori r16, (1<<WDCE)|(1<<WDE)

out WDTCSR, r16

; Turn off WDT

ldi r16, (0<<WDE)

out WDTCSR, r16

ret

C Code Example⁽¹⁾

void WDT_off(void)

{

_WDR();

/* Clear WDRF in MCUSR */

MCUSR = 0x00

/* Write logical one to WDCE and WDE */

WDTCSR |= (1<<WDCE) | (1<<WDE);

/* Turn off WDT */

WDTCSR = 0x00;

}

Note:

1. See “Code Examples” on page 6.

46

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ATtiny25/45/85

8.5

Register Description

8.5.1

MCUSR – MCU Status Register

The MCU Status Register provides information on which reset source caused an MCU Reset.

Bit

7

–

R

0

6

–

R

0

5

–

R

0

4

–

R

0

3

2

1

0

0x34

WDRF

R/W

BORF

R/W

EXTRF

R/W

PORF

R/W

MCUSR

Read/Write

Initial Value

See Bit Description

• Bits 7..4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bit 3 – WDRF: Watchdog Reset Flag

This bit is set if a Watchdog Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 2 – BORF: Brown-out Reset Flag

This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 1 – EXTRF: External Reset Flag

This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a

logic zero to the flag.

• Bit 0 – PORF: Power-on Reset Flag

This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.

To make use of the Reset Flags to identify a reset condition, the user should read and then reset

the MCUSR as early as possible in the program. If the register is cleared before another reset

occurs, the source of the reset can be found by examining the Reset Flags.

8.5.2

WDTCR – Watchdog Timer Control Register

Bit

0x21

7

6

5

4

3

2

1

0

WDIF

WDIE

WDP3

R/W

0

WDCE

R/W

0

WDE

R/W

X

WDP2

R/W

0

WDP1

R/W

0

WDP0

R/W

0

WDTCR

Read/Write

Initial Value

R/W

0

R/W

0

• Bit 7 – WDIF: Watchdog Timeout Interrupt Flag

This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is config-

ured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt

handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit in

SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.

• Bit 6 – WDIE: Watchdog Timeout Interrupt Enable

When this bit is written to one, WDE is cleared, and the I-bit in the Status Register is set, the

Watchdog Time-out Interrupt is enabled. In this mode the corresponding interrupt is executed

instead of a reset if a timeout in the Watchdog Timer occurs.

If WDE is set, WDIE is automatically cleared by hardware when a time-out occurs. This is useful

for keeping the Watchdog Reset security while using the interrupt. After the WDIE bit is cleared,

47

2586K–AVR–01/08

the next time-out will generate a reset. To avoid the Watchdog Reset, WDIE must be set after

each interrupt.

Table 8-2.

Watchdog Timer Configuration

WDE

WDIE

Watchdog Timer State

Stopped

Action on Time-out

None

0

1

0

1

0

1

Running

Interrupt

Running

Reset

Running

Interrupt

• Bit 4 – WDCE: Watchdog Change Enable

This bit must be set when the WDE bit is written to logic zero. Otherwise, the Watchdog will not

be disabled. Once written to one, hardware will clear this bit after four clock cycles. Refer to the

description of the WDE bit for a Watchdog disable procedure. This bit must also be set when

changing the prescaler bits. See “Timed Sequences for Changing the Configuration of the

Watchdog Timer” on page 45.

• Bit 3 – WDE: Watchdog Enable

When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written

to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared if the WDCE bit

has logic level one. To disable an enabled Watchdog Timer, the following procedure must be

followed:

1. In the same operation, write a logic one to WDCE and WDE. A logic one must be writ-

ten to WDE even though it is set to one before the disable operation starts.

2. Within the next four clock cycles, write a logic 0 to WDE. This disables the Watchdog.

In safety level 2, it is not possible to disable the Watchdog Timer, even with the algorithm

described above. See “Timed Sequences for Changing the Configuration of the Watchdog

Timer” on page 45.

In safety level 1, WDE is overridden by WDRF in MCUSR. See “MCUSR – MCU Status Regis-

ter” on page 47 for description of WDRF. This means that WDE is always set when WDRF is set.

To clear WDE, WDRF must be cleared before disabling the Watchdog with the procedure

described above. This feature ensures multiple resets during conditions causing failure, and a

safe start-up after the failure.

Note:

If the watchdog timer is not going to be used in the application, it is important to go through a

watchdog disable procedure in the initialization of the device. If the Watchdog is accidentally

enabled, for example by a runaway pointer or brown-out condition, the device will be reset, which

in turn will lead to a new watchdog reset. To avoid this situation, the application software should

always clear the WDRF flag and the WDE control bit in the initialization routine.

48

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

• Bits 5, 2:0 – WDP3:0: Watchdog Timer Prescaler 3, 2, 1, and 0

The WDP3:0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is

enabled. The different prescaling values and their corresponding Timeout Periods are shown in

Table 8-3.

Watchdog Timer Prescale Select

Number of WDT Oscillator

Typical Time-out at

V_CC= 5.0V

WDP3

WDP2

WDP1

WDP0

Cycles

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

2K (2048) cycles

16 ms

32 ms

64 ms

0.125 s

0.25 s

0.5 s

4K (4096) cycles

8K (8192) cycles

16K (16384) cycles

32K (32764) cycles

64K (65536) cycles

128K (131072) cycles

256K (262144) cycles

512K (524288) cycles

1024K (1048576) cycles

1.0 s

2.0 s

4.0 s

8.0 s

Reserved⁽¹⁾

Note:

1. If selected, one of the valid settings below 0b1010 will be used.

49

2586K–AVR–01/08

9. Interrupts

This section describes the specifics of the interrupt handling as performed in ATtiny25/45/85.

For a general explanation of the AVR interrupt handling, refer to “Reset and Interrupt Handling”

on page 12.

9.1

Interrupt Vectors in ATtiny25/45/85

The interrupt vectors of ATtiny25/45/85 are described in Table 9-1below.

Table 9-1.

Vector No.

Reset and Interrupt Vectors

Program Address

Source

Interrupt Definition

External Pin, Power-on Reset,

Brown-out Reset, Watchdog Reset

1

0x0000

RESET

2

3

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

0x000A

0x000B

0x000C

0x000D

0x000E

INT0

External Interrupt Request 0

Pin Change Interrupt Request 0

Timer/Counter1 Compare Match A

Timer/Counter1 Overflow

Timer/Counter0 Overflow

EEPROM Ready

PCINT0

4

TIMER1_COMPA

TIMER1_OVF

TIMER0_OVF

EE_RDY

5

6

7

8

ANA_COMP

ADC

Analog Comparator

9

ADC Conversion Complete

Timer/Counter1 Compare Match B

Timer/Counter0 Compare Match A

Timer/Counter0 Compare Match B

Watchdog Time-out

10

11

12

13

14

15

TIMER1_COMPB

TIMER0_COMPA

TIMER0_COMPB

WDT

USI_START

USI_OVF

USI START

USI Overflow

If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular

program code can be placed at these locations. The most typical and general program setup for

the Reset and Interrupt Vector Addresses in ATtiny25/45/85 is shown in the program example

below.

Address Labels Code

Comments

0x0000

0x0001

0x0002

0x0003

0x0004

0x0005

0x0006

0x0007

0x0008

0x0009

rjmp

RESET

; Reset Handler

EXT_INT0

PCINT0

; IRQ0 Handler

; PCINT0 Handler

TIM1_COMPA

TIM1_OVF

TIM0_OVF

EE_RDY

; Timer1 CompareA Handler

; Timer1 Overflow Handler

; Timer0 Overflow Handler

; EEPROM Ready Handler

; Analog Comparator Handler

; ADC Conversion Handler

; Timer1 CompareB Handler

ANA_COMP

ADC

TIM1_COMPB

50

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

0x000A

0x000B

0x000C

0x000D

0x000E

rjmp

TIM0_COMPA

TIM0_COMPB

WDT

;

USI_START

USI_OVF

0x000F RESET: ldi

r16, low(RAMEND); Main program start

0x0010

0x0011

0x0012

0x0013

0x0014

...

ldi

out

r17, high(RAMEND); Tiny45/85 also has SPH

SPL, r16

SPH, r17

; Set Stack Pointer to top of RAM

; Tiny45/85 als has SPH

; Enable interrupts

out

sei

<instr> xxx

...

... ...

9.2

External Interrupts

The External Interrupts are triggered by the INT0 pin or any of the PCINT5..0 pins. Observe that,

if enabled, the interrupts will trigger even if the INT0 or PCINT5..0 pins are configured as out-

puts. This feature provides a way of generating a software interrupt. Pin change interrupts PCI

will trigger if any enabled PCINT5..0 pin toggles. The PCMSK Register control which pins con-

tribute to the pin change interrupts. Pin change interrupts on PCINT5..0 are detected

asynchronously. This implies that these interrupts can be used for waking the part also from

sleep modes other than Idle mode.

The INT0 interrupts can be triggered by a falling or rising edge or a low level. This is set up as

indicated in the specification for the MCU Control Register – MCUCR. When the INT0 interrupt is

enabled and is configured as level triggered, the interrupt will trigger as long as the pin is held

low. Note that recognition of falling or rising edge interrupts on INT0 requires the presence of an

I/O clock, described in “Clock Systems and their Distribution” on page 23.

9.2.1

Low Level Interrupt

A low level interrupt on INT0 is detected asynchronously. This implies that this interrupt can be

used for waking the part also from sleep modes other than Idle mode. The I/O clock is halted in

all sleep modes except Idle mode.

Note that if a level triggered interrupt is used for wake-up from Power-down, the required level

must be held long enough for the MCU to complete the wake-up to trigger the level interrupt. If

the level disappears before the end of the Start-up Time, the MCU will still wake up, but no inter-

rupt will be generated. The start-up time is defined by the SUT and CKSEL Fuses as described

in “System Clock and Clock Options” on page 23.

If the low level on the interrupt pin is removed before the device has woken up then program

execution will not be diverted to the interrupt service routine but continue from the instruction fol-

lowing the SLEEP command.

51

2586K–AVR–01/08

9.2.2

Pin Change Interrupt Timing

An example of timing of a pin change interrupt is shown in Figure 9-1.

Figure 9-1. Timing of pin change interrupts

pin_lat

pcint_in_(0)

PCINT(0)

0

x

D

Q

pcint_syn

pcint_setflag

PCIF

pin_sync

PCINT(0) in PCMSK(x)

LE

clk

PCINT(0)

pin_lat

pin_sync

pcint_in_(0)

pcint_syn

pcint_setflag

PCIF

9.3

Register Description

9.3.1

MCUCR – MCU Control Register

The External Interrupt Control Register A contains control bits for interrupt sense control.

Bit

7

6

5

4

3

2

1

0

0x35

BODS

PUD

R/W

0

SE

R/W

0

SM1

R/W

0

SM0

R/W

0

BODSE

ISC01

R/W

0

ISC00

R/W

0

MCUCR

Read/Write

Initial Value

R

0

R

0

• Bits 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0

The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-

sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the

interrupt are defined in Table 9-2. The value on the INT0 pin is sampled before detecting edges.

If edge or toggle interrupt is selected, pulses that last longer than one clock period will generate

an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level interrupt is

52

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

selected, the low level must be held until the completion of the currently executing instruction to

generate an interrupt.

Table 9-2.

Interrupt 0 Sense Control

ISC01

ISC00

Description

0

1

0

1

0

1

The low level of INT0 generates an interrupt request.

Any logical change on INT0 generates an interrupt request.

The falling edge of INT0 generates an interrupt request.

The rising edge of INT0 generates an interrupt request.

9.3.2

GIMSK – General Interrupt Mask Register

Bit

7

–

R

0

6

5

4

–

R

0

3

–

R

0

2

–

R

0

1

–

R

0

–

R

0

0x3B

INT0

R/W

0

PCIE

R/W

0

GIMSK

Read/Write

Initial Value

• Bits 7, 4:0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bit 6 – INT0: External Interrupt Request 0 Enable

When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the exter-

nal pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in the MCU

Control Register (MCUCR) define whether the external interrupt is activated on rising and/or fall-

ing edge of the INT0 pin or level sensed. Activity on the pin will cause an interrupt request even

if INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is

executed from the INT0 Interrupt Vector.

• Bit 5 – PCIE: Pin Change Interrupt Enable

When the PCIE bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin

change interrupt is enabled. Any change on any enabled PCINT5:0 pin will cause an interrupt.

The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI Interrupt

Vector. PCINT5:0 pins are enabled individually by the PCMSK0 Register.

9.3.3

GIFR – General Interrupt Flag Register

Bit

0x3A

7

6

5

4

–

R

0

3

–

R

0

2

–

R

0

1

–

R

0

–

R

0

–

INTF0

R/W

0

PCIF

R/W

0

GIFR

Read/Write

Initial Value

R

0

• Bits 7, 4:0 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bit 6 – INTF0: External Interrupt Flag 0

When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes set

(one). If the I-bit in SREG and the INT0 bit in GIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared

when INT0 is configured as a level interrupt.

53

2586K–AVR–01/08

• Bit 5 – PCIF: Pin Change Interrupt Flag

When a logic change on any PCINT5:0 pin triggers an interrupt request, PCIF becomes set

(one). If the I-bit in SREG and the PCIE bit in GIMSK are set (one), the MCU will jump to the cor-

responding Interrupt Vector. The flag is cleared when the interrupt routine is executed.

Alternatively, the flag can be cleared by writing a logical one to it.

9.3.4

PCMSK – Pin Change Mask Register

Bit

0x15

7

6

–

R

0

5

4

3

2

1

0

–

PCINT5

R/W

1

PCINT4

R/W

1

PCINT3

R/W

1

PCINT2

R/W

1

PCINT1

R/W

1

PCINT0

R/W

1

PCMSK

Read/Write

Initial Value

R

0

• Bits 7, 6 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bits 5:0 – PCINT5:0: Pin Change Enable Mask 5:0

Each PCINT5:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin.

If PCINT5:0 is set and the PCIE bit in GIMSK is set, pin change interrupt is enabled on the corre-

sponding I/O pin. If PCINT5:0 is cleared, pin change interrupt on the corresponding I/O pin is

disabled.

54

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ATtiny25/45/85

10. I/O Ports

10.1 Introduction

All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports.

This means that the direction of one port pin can be changed without unintentionally changing

the direction of any other pin with the SBI and CBI instructions. The same applies when chang-

ing drive value (if configured as output) or enabling/disabling of pull-up resistors (if configured as

input). Each output buffer has symmetrical drive characteristics with both high sink and source

capability. The pin driver is strong enough to drive LED displays directly. All port pins have indi-

vidually selectable pull-up resistors with a supply-voltage invariant resistance. All I/O pins have

protection diodes to both V_CCand Ground as indicated in Figure 10-1. Refer to “Electrical Char-

acteristics” on page 166 for a complete list of parameters.

Figure 10-1. I/O Pin Equivalent Schematic

R_pu

Pxn

Logic

See Figure

"General Digital I/O" for

Details

All registers and bit references in this section are written in general form. A lower case “x” repre-

sents the numbering letter for the port, and a lower case “n” represents the bit number. However,

when using the register or bit defines in a program, the precise form must be used. For example,

PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The physical I/O Regis-

ters and bit locations are listed in “Register Description” on page 66.

Three I/O memory address locations are allocated for each port, one each for the Data Register

– PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input Pins

I/O location is read only, while the Data Register and the Data Direction Register are read/write.

However, writing a logic one to a bit in the PINx Register, will result in a toggle in the correspond-

ing bit in the Data Register. In addition, the Pull-up Disable – PUD bit in MCUCR disables the

pull-up function for all pins in all ports when set.

Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page

56. Most port pins are multiplexed with alternate functions for the peripheral features on the

device. How each alternate function interferes with the port pin is described in “Alternate Port

Functions” on page 59. Refer to the individual module sections for a full description of the alter-

nate functions.

Note that enabling the alternate function of some of the port pins does not affect the use of the

other pins in the port as general digital I/O.

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10.2 Ports as General Digital I/O

The ports are bi-directional I/O ports with optional internal pull-ups. Figure 10-2 shows a func-

tional description of one I/O-port pin, here generically called Pxn.

Figure 10-2. General Digital I/O⁽¹⁾

PUD

Q

D

DDxn

Q _CLR

WDx

RDx

RESET

1

0

Q

D

Pxn

PORTxn

Q _CLR

RESET

WPx

WRx

SLEEP

RRx

SYNCHRONIZER

RPx

D

Q

D

L

Q

PINxn

Q

clk _I/O

WDx:

RDx:

WRx:

RRx:

RPx:

WPx:

WRITE DDRx

READ DDRx

WRITE PORTx

PUD:

PULLUP DISABLE

SLEEP CONTROL

I/O CLOCK

SLEEP:

clk_I/O

:

READ PORTx REGISTER

READ PORTx PIN

WRITE PINx REGISTER

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O

,

SLEEP, and PUD are common to all ports.

10.2.1

Configuring the Pin

Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Register

Description” on page 66, the DDxn bits are accessed at the DDRx I/O address, the PORTxn bits

at the PORTx I/O address, and the PINxn bits at the PINx I/O address.

The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,

Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input

pin.

If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is

activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has to

be configured as an output pin. The port pins are tri-stated when reset condition becomes active,

even if no clocks are running.

If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven

high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port

pin is driven low (zero).

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10.2.2

10.2.3

Toggling the Pin

Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.

Note that the SBI instruction can be used to toggle one single bit in a port.

Switching Between Input and Output

When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}

= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output

low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-

able, as a high-impedant environment will not notice the difference between a strong high driver

and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all

pull-ups in all ports.

Switching between input with pull-up and output low generates the same problem. The user

must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}

= 0b10) as an intermediate step.

Table 10-1 summarizes the control signals for the pin value.

Table 10-1. Port Pin Configurations

PUD

DDxn

PORTxn

(in MCUCR)

I/O

Pull-up

No

Comment

0

1

0

1

0

1

X

0

Input

Tri-state (Hi-Z)

Input

Yes

No

Pxn will source current if ext. pulled low.

Tri-state (Hi-Z)

1

Input

X

Output

No

Output Low (Sink)

Output High (Source)

No

10.2.4

Reading the Pin Value

Independent of the setting of Data Direction bit DDxn, the port pin can be read through the

PINxn Register bit. As shown in Figure 10-2, the PINxn Register bit and the preceding latch con-

stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value

near the edge of the internal clock, but it also introduces a delay. Figure 10-3 shows a timing dia-

gram of the synchronization when reading an externally applied pin value. The maximum and

minimum propagation delays are denoted t_pd,maxand t_pd,minrespectively.

Figure 10-3. Synchronization when Reading an Externally Applied Pin value

SYSTEM CLK

XXX

in r17, PINx

INSTRUCTIONS

SYNC LATCH

PINxn

0x00

t_{pd, max}

0xFF

r17

t_{pd, min}

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Consider the clock period starting shortly after the first falling edge of the system clock. The latch

is closed when the clock is low, and goes transparent when the clock is high, as indicated by the

shaded region of the “SYNC LATCH” signal. The signal value is latched when the system clock

goes low. It is clocked into the PINxn Register at the succeeding positive clock edge. As indi-

cated by the two arrows tpd,max and tpd,min, a single signal transition on the pin will be delayed

between ½ and 1½ system clock period depending upon the time of assertion.

When reading back a software assigned pin value, a nop instruction must be inserted as indi-

cated in Figure 10-4. The out instruction sets the “SYNC LATCH” signal at the positive edge of

the clock. In this case, the delay tpd through the synchronizer is one system clock period.

Figure 10-4. Synchronization when Reading a Software Assigned Pin Value

SYSTEM CLK

0xFF

r16

out PORTx, r16

nop

in r17, PINx

INSTRUCTIONS

SYNC LATCH

PINxn

0x00

t_pd

0xFF

r17

The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define

the port pins from 4 to 5 as input with a pull-up assigned to port pin 4. The resulting pin values

are read back again, but as previously discussed, a nop instruction is included to be able to read

back the value recently assigned to some of the pins.

Assembly Code Example⁽¹⁾

...

; Define pull-ups and set outputs high

; Define directions for port pins

ldi r16,(1<<PB4)|(1<<PB1)|(1<<PB0)

ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)

out PORTB,r16

out DDRB,r17

; Insert nop for synchronization

nop

; Read port pins

in

r16,PINB

...

Note:

1. For the assembly program, two temporary registers are used to minimize the time from pull-

ups are set on pins 0, 1 and 4, until the direction bits are correctly set, defining bit 2 and 3 as

low and redefining bits 0 and 1 as strong high drivers.

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C Code Example

unsigned char i;

...

/* Define pull-ups and set outputs high */

/* Define directions for port pins */

PORTB = (1<<PB4)|(1<<PB1)|(1<<PB0);

DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);

/* Insert nop for synchronization*/

_NOP();

/* Read port pins */

i = PINB;

...

10.2.5

Digital Input Enable and Sleep Modes

As shown in Figure 10-2, the digital input signal can be clamped to ground at the input of the

schmitt-trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in

Power-down mode to avoid high power consumption if some input signals are left floating, or

have an analog signal level close to V_CC/2.

SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt

request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by various

other alternate functions as described in “Alternate Port Functions” on page 59.

If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as

“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external interrupt

is not enabled, the corresponding External Interrupt Flag will be set when resuming from the

above mentioned Sleep mode, as the clamping in these sleep mode produces the requested

logic change.

10.2.6

Unconnected Pins

If some pins are unused, it is recommended to ensure that these pins have a defined level. Even

though most of the digital inputs are disabled in the deep sleep modes as described above, float-

ing inputs should be avoided to reduce current consumption in all other modes where the digital

inputs are enabled (Reset, Active mode and Idle mode).

The simplest method to ensure a defined level of an unused pin, is to enable the internal pull-up.

In this case, the pull-up will be disabled during reset. If low power consumption during reset is

important, it is recommended to use an external pull-up or pulldown. Connecting unused pins

directly to V_CCor GND is not recommended, since this may cause excessive currents if the pin is

accidentally configured as an output.

10.3 Alternate Port Functions

Most port pins have alternate functions in addition to being general digital I/Os. Figure 10-5

shows how the port pin control signals from the simplified Figure 10-2 can be overridden by

alternate functions. The overriding signals may not be present in all port pins, but the figure

serves as a generic description applicable to all port pins in the AVR microcontroller family.

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Figure 10-5. Alternate Port Functions⁽¹⁾

PUOExn

PUOVxn

1

0

PUD

DDOExn

DDOVxn

1

0

Q

D

DDxn

Q _CLR

WDx

RDx

PVOExn

PVOVxn

RESET

1

0

1

0

Pxn

Q

D

PORTxn

PTOExn

Q _CLR

DIEOExn

DIEOVxn

SLEEP

WPx

RESET

WRx

1

0

RRx

SYNCHRONIZER

RPx

SET

D

Q

D

L

Q

PINxn

_CLRQ

CLR

clk _I/O

DIxn

AIOxn

PUOExn: Pxn PULL-UP OVERRIDE ENABLE

PUOVxn: Pxn PULL-UP OVERRIDE VALUE

DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE

DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE

PVOExn: Pxn PORT VALUE OVERRIDE ENABLE

PVOVxn: Pxn PORT VALUE OVERRIDE VALUE

PUD:

WDx:

RDx:

RRx:

WRx:

RPx:

WPx:

PULLUP DISABLE

WRITE DDRx

READ DDRx

READ PORTx REGISTER

WRITE PORTx

READ PORTx PIN

WRITE PINx

DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE

DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE

clk_I/O

:

I/O CLOCK

SLEEP:

SLEEP CONTROL

DIxn:

DIGITAL INPUT PIN n ON PORTx

AIOxn:

ANALOG INPUT/OUTPUT PIN n ON PORTx

PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE

Note:

1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clk_I/O

,

SLEEP, and PUD are common to all ports. All other signals are unique for each pin.

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Table 10-2 summarizes the function of the overriding signals. The pin and port indexes from Fig-

ure 10-5 are not shown in the succeeding tables. The overriding signals are generated internally

in the modules having the alternate function.

Table 10-2. Generic Description of Overriding Signals for Alternate Functions

Signal Name

Full Name

Description

If this signal is set, the pull-up enable is controlled by the PUOV

signal. If this signal is cleared, the pull-up is enabled when

{DDxn, PORTxn, PUD} = 0b010.

Pull-up Override

Enable

PUOE

If PUOE is set, the pull-up is enabled/disabled when PUOV is

set/cleared, regardless of the setting of the DDxn, PORTxn,

and PUD Register bits.

Pull-up Override

Value

PUOV

DDOE

DDOV

If this signal is set, the Output Driver Enable is controlled by the

DDOV signal. If this signal is cleared, the Output driver is

enabled by the DDxn Register bit.

Data Direction

Override Enable

If DDOE is set, the Output Driver is enabled/disabled when

DDOV is set/cleared, regardless of the setting of the DDxn

Register bit.

Data Direction

Override Value

If this signal is set and the Output Driver is enabled, the port

value is controlled by the PVOV signal. If PVOE is cleared, and

the Output Driver is enabled, the port Value is controlled by the

PORTxn Register bit.

Port Value

Override Enable

PVOE

Port Value

Override Value

If PVOE is set, the port value is set to PVOV, regardless of the

setting of the PORTxn Register bit.

PVOV

PTOE

Port Toggle

Override Enable

If PTOE is set, the PORTxn Register bit is inverted.

Digital Input

Enable Override

Enable

If this bit is set, the Digital Input Enable is controlled by the

DIEOV signal. If this signal is cleared, the Digital Input Enable

is determined by MCU state (Normal mode, sleep mode).

DIEOE

DIEOV

Digital Input

Enable Override

Value

If DIEOE is set, the Digital Input is enabled/disabled when

DIEOV is set/cleared, regardless of the MCU state (Normal

mode, sleep mode).

This is the Digital Input to alternate functions. In the figure, the

signal is connected to the output of the schmitt-trigger but

before the synchronizer. Unless the Digital Input is used as a

clock source, the module with the alternate function will use its

own synchronizer.

DI

Digital Input

This is the Analog Input/Output to/from alternate functions. The

signal is connected directly to the pad, and can be used bi-

directionally.

Analog

Input/Output

AIO

The following subsections shortly describe the alternate functions for each port, and relate the

overriding signals to the alternate function. Refer to the alternate function description for further

details.

10.3.1

Alternate Functions of Port B

The Port B pins with alternate function are shown in Table 10-3.

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Table 10-3. Port B Pins Alternate Functions

Port Pin

Alternate Function

RESET: Reset Pin

dW:

debugWIRE I/O

PB5

ADC0: ADC Input Channel 0

PCINT5: Pin Change Interrupt, Source 5

XTAL2: Crystal Oscillator Output

CLKO: System Clock Output

PB4

PB3

ADC2: ADC Input Channel 2

OC1B: Timer/Counter1 Compare Match B Output

PCINT4: Pin Change Interrupt 0, Source 4

XTAL1: Crystal Oscillator Input

CLKI:

External Clock Input

ADC3: ADC Input Channel 3

OC1B: Complementary Timer/Counter1 Compare Match B Output

PCINT3: Pin Change Interrupt 0, Source 3

SCK:

Serial Clock Input

ADC1: ADC Input Channel 1

T0:

Timer/Counter0 Clock Source.

PB2

PB1

USCK: USI Clock (Three Wire Mode)

SCL :

USI Clock (Two Wire Mode)

INT0:

External Interrupt 0 Input

PCINT2: Pin Change Interrupt 0, Source 2

MISO: SPI Master Data Input / Slave Data Output

AIN1:

Analog Comparator, Negative Input

OC0B: Timer/Counter0 Compare Match B Output

OC1A: Timer/Counter1 Compare Match A Output

DO:

USI Data Output (Three Wire Mode)

PCINT1:Pin Change Interrupt 0, Source 1

MOSI:: SPI Master Data Output / Slave Data Input

AIN0:

Analog Comparator, Positive Input

OC0A: Timer/Counter0 Compare Match A output

OC1A: Complementary Timer/Counter1 Compare Match A Output

PB0

DI:

USI Data Input (Three Wire Mode)

USI Data Input (Two Wire Mode)

SDA:

AREF: External Analog Reference

PCINT0: Pin Change Interrupt 0, Source 0

• Port B, Bit 5 - RESET/dW/ADC0/PCINT5

• RESET: External Reset input is active low and enabled by unprogramming (“1”) the

RSTDISBL Fuse. Pullup is activated and output driver and digital input are deactivated when

the pin is used as the RESET pin.

• dW: When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are

unprogrammed, the debugWIRE system within the target device is activated. The RESET

port pin is configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled

and becomes the communication gateway between target and emulator.

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• ADC0: Analog to Digital Converter, Channel 0.

• PCINT5: Pin Change Interrupt source 5.

• Port B, Bit 4- XTAL2/CLKO/ADC2/OC1B/PCINT4

• XTAL2: Chip Clock Oscillator pin 2. Used as clock pin for all chip clock sources except

internal calibrateble RC Oscillator and external clock. When used as a clock pin, the pin can

not be used as an I/O pin. When using internal calibratable RC Oscillator or External clock as

a Chip clock sources, PB4 serves as an ordinary I/O pin.

• CLKO: The devided system clock can be output on the pin PB4. The divided system clock will

be output if the CKOUT Fuse is programmed, regardless of the PORTB4 and DDB4 settings.

It will also be output during reset.

• ADC2: Analog to Digital Converter, Channel 2.

• OC1B: Output Compare Match output: The PB4 pin can serve as an external output for the

Timer/Counter1 Compare Match B when configured as an output (DDB4 set). The OC1B pin

is also the output pin for the PWM mode timer function.

• PCINT4: Pin Change Interrupt source 4.

• Port B, Bit 3 - XTAL1/CLKI/ADC3/OC1B/PCINT3

• XTAL1: Chip Clock Oscillator pin 1. Used for all chip clock sources except internal

calibrateble RC oscillator. When used as a clock pin, the pin can not be used as an I/O pin.

• CLKI: Clock Input from an external clock source, see “External Clock” on page 26.

• ADC3: Analog to Digital Converter, Channel 3.

• OC1B: Inverted Output Compare Match output: The PB3 pin can serve as an external output

for the Timer/Counter1 Compare Match B when configured as an output (DDB3 set). The

OC1B pin is also the inverted output pin for the PWM mode timer function.

• PCINT3: Pin Change Interrupt source 3.

• Port B, Bit 2 - SCK/ADC1/T0/USCK/SCL/INT0/PCINT2

• SCK: Master Clock output, Slave Clock input pin for SPI channel. When the SPI is enabled as

a Slave, this pin is configured as an input regardless of the setting of DDB2. When the SPI is

enabled as a Master, the data direction of this pin is controlled by DDPB2. When the pin is

forced by the SPI to be an input, the pull-up can still be controlled by the PORTB2 bit.

• ADC1: Analog to Digital Converter, Channel 1.

• T0: Timer/Counter0 counter source.

• USCK: Three-wire mode Universal Serial Interface Clock.

• SCL: Two-wire mode Serial Clock for USI Two-wire mode.

• INT0: External Interrupt source 0.

• PCINT2: Pin Change Interrupt source 2.

• Port B, Bit 1 - MISO/AIN1/OC0B/OC1A/DO/PCINT1

• MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled as

a Master, this pin is configured as an input regardless of the setting of DDB1. When the SPI

is enabled as a Slave, the data direction of this pin is controlled by DDB1. When the pin is

forced by the SPI to be an input, the pull-up can still be controlled by the PORTB1 bit.

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• AIN1: Analog Comparator Negative Input. Configure the port pin as input with the internal

pull-up switched off to avoid the digital port function from interfering with the function of the

Analog Comparator.

• OC0B: Output Compare Match output. The PB1 pin can serve as an external output for the

Timer/Counter0 Compare Match B. The PB1 pin has to be configured as an output (DDB1

set (one)) to serve this function. The OC0B pin is also the output pin for the PWM mode timer

function.

• OC1A: Output Compare Match output: The PB1 pin can serve as an external output for the

Timer/Counter1 Compare Match B when configured as an output (DDB1 set). The OC1A pin

is also the output pin for the PWM mode timer function.

• DO: Three-wire mode Universal Serial Interface Data output. Three-wire mode Data output

overrides PORTB1 value and it is driven to the port when data direction bit DDB1 is set (one).

PORTB1 still enables the pull-up, if the direction is input and PORTB1 is set (one).

• PCINT1: Pin Change Interrupt source 1.

• Port B, Bit 0 - MOSI/AIN0/OC0A/OC1A/DI/SDA/AREF/PCINT0

• MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as

a Slave, this pin is configured as an input regardless of the setting of DDB0. When the SPI is

enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is

forced by the SPI to be an input, the pull-up can still be controlled by the PORTB0 bit.

• AIN0: Analog Comparator Positive Input. Configure the port pin as input with the internal pull-

up switched off to avoid the digital port function from interfering with the function of the

Analog Comparator.

• OC0A: Output Compare Match output. The PB0 pin can serve as an external output for the

Timer/Counter0 Compare Match A when configured as an output (DDB0 set (one)). The

OC0A pin is also the output pin for the PWM mode timer function.

• OC1A: Inverted Output Compare Match output: The PB0 pin can serve as an external output

for the Timer/Counter1 Compare Match B when configured as an output (DDB0 set). The

OC1A pin is also the inverted output pin for the PWM mode timer function.

• SDA: Two-wire mode Serial Interface Data.

• AREF: External Analog Reference for ADC. Pullup and output driver are disabled on PB0

when the pin is used as an external reference or Internal Voltage Reference with external

capacitor at the AREF pin.

• DI: Data Input in USI Three-wire mode. USI Three-wire mode does not override normal port

functions, so pin must be configure as an input for DI function.

• PCINT0: Pin Change Interrupt source 0.

Table 10-4 and Table 10-5 relate the alternate functions of Port B to the overriding signals

shown in Figure 10-5 on page 60.

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Table 10-4. Overriding Signals for Alternate Functions in PB5..PB3

Signal

Name

PB5/RESET/

ADC0/PCINT5

PB4/ADC2/XTAL2/

OC1B/PCINT4

PB3/ADC3/XTAL1/

OC1B/PCINT3

PUOE

PUOV

DDOE

DDOV

PVOE

PVOV

PTOE

RSTDISBL⁽¹⁾• DWEN⁽¹⁾

0

1

0

RSTDISBL⁽¹⁾• DWEN⁽¹⁾

0

debugWire Transmit

0

OC1B Enable

OC1B

0

OC1B

0

RSTDISBL⁽¹⁾+ (PCINT5 •

PCIE + ADC0D)

DIEOE

PCINT4 • PCIE + ADC2D

PCINT3 • PCIE + ADC3D

DIEOV

DI

ADC0D

ADC2D

ADC3D

PCINT5 Input

PCINT4 Input

ADC2 Input

PCINT3 Input

ADC3 Input

AIO

RESET Input, ADC0 Input

Note:

1. 1 when the Fuse is “0” (Programmed).

Table 10-5. Overriding Signals for Alternate Functions in PB2..PB0

PB0/MOSI/DI/SDA/AIN0/AR

EF/OC1A/OC0A/

PCINT0

Signal

Name

PB2/SCK/ADC1/T0/

USCK/SCL/INT0/PCINT2

PB1/MISO/DO/AIN1/

OC1A/OC0B/PCINT1

PUOE

PUOV

DDOE

USI_TWO_WIRE

0

USI_TWO_WIRE

0

USI_TWO_WIRE

(USI_SCL_HOLD +

PORTB2) • DDB2

DDOV

PVOE

0

(SDA + PORTB0) • DDB0

OC0B Enable + OC1A

Enable +

USI_THREE_WIRE

OC0A Enable + OC1A

Enable + (USI_TWO_WIRE

• DDB0)

USI_TWO_WIRE • DDB2

PVOV

PTOE

0

OC0B + OC1A + DO

0

OC0A + OC1A

0

USITC

PCINT2 • PCIE + ADC1D +

USISIE

PCINT0 • PCIE + AIN0D +

USISIE

DIEOE

DIEOV

DI

PCINT1 • PCIE + AIN1D

AIN1D

ADC1D

AIN0D

T0/USCK/SCL/INT0/

PCINT2 Input

PCINT1 Input

DI/SDA/PCINT0 Input

Analog Comparator

Negative Input

Analog Comparator Positive

Input

AIO

ADC1 Input

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10.4 Register Description

10.4.1

MCUCR – MCU Control Register

Bit

7

6

5

4

3

2

1

0

0x35

BODS

PUD

R/W

0

SE

R/W

0

SM1

R/W

0

SM0

R/W

0

BODSE

ISC01

R/W

0

ISC00

R/W

0

MCUCR

Read/Write

Initial Value

R

0

R

0

• Bit 6 – PUD: Pull-up Disable

When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and

PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con-

figuring the Pin” on page 56 for more details about this feature.

10.4.2

10.4.3

10.4.4

PORTB – Port B Data Register

Bit

0x18

7

6

–

R

0

5

4

3

2

1

0

–

PORTB5

PORTB4

PORTB3

PORTB2

PORTB1

PORTB0

PORTB

DDRB

PINB

Read/Write

Initial Value

R

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

DDRB – Port B Data Direction Register

Bit

7

–

R

0

6

–

R

0

5

4

3

2

1

0

0x17

DDB5

R/W

0

DDB4

R/W

0

DDB3

R/W

0

DDB2

R/W

0

DDB1

R/W

0

DDB0

R/W

0

Read/Write

Initial Value

PINB – Port B Input Pins Address

Bit

7

–

R

0

6

–

R

0

5

4

3

2

1

0

0x16

PINB5

R/W

N/A

PINB4

R/W

N/A

PINB3

R/W

N/A

PINB2

R/W

N/A

PINB1

R/W

N/A

PINB0

R/W

N/A

Read/Write

Initial Value

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11. 8-bit Timer/Counter0 with PWM

11.1 Features

• Two Independent Output Compare Units

• Double Buffered Output Compare Registers

• Clear Timer on Compare Match (Auto Reload)

• Glitch Free, Phase Correct Pulse Width Modulator (PWM)

• Variable PWM Period

• Frequency Generator

• Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B)

11.2 Overview

Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two independent Output

Compare Units, and with PWM support. It allows accurate program execution timing (event man-

agement) and wave generation.

A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 11-1. For the actual

placement of I/O pins, refer to “Pinout ATtiny25/45/85” on page 2. CPU accessible I/O Registers,

including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit loca-

tions are listed in the “Register Description” on page 80.

Figure 11-1. 8-bit Timer/Counter Block Diagram

Count

TOVn

(Int.Req.)

Clear

Control Logic

Clock Select

Direction

clk_Tn

Edge

Detector

Tn

TOP

BOTTOM

( From Prescaler )

Timer/Counter

TCNTn

=

= 0

OCnA

(Int.Req.)

Waveform

Generation

OCnA

OCnB

=

OCRnA

Fixed

TOP

Value

OCnB

(Int.Req.)

Waveform

Generation

=

OCRnB

TCCRnA

TCCRnB

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11.2.1

Registers

The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A and OCR0B) are 8-bit

registers. Interrupt request (abbreviated to Int.Req. in the figure) signals are all visible in the

Timer Interrupt Flag Register (TIFR). All interrupts are individually masked with the Timer Inter-

rupt Mask Register (TIMSK). TIFR and TIMSK are not shown in the figure.

The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on

the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter

uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source

is selected. The output from the Clock Select logic is referred to as the timer clock (clk_T0).

The double buffered Output Compare Registers (OCR0A and OCR0B) is compared with the

Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-

erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and

OC0B). See “Output Compare Unit” on page 71. for details. The Compare Match event will also

set the Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare

interrupt request.

11.2.2

Definitions

Many register and bit references in this section are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 0. A lower case “x” replaces the Output Com-

pare Unit, in this case Compare Unit A or Compare Unit B. However, when using the register or

bit defines in a program, the precise form must be used, i.e., TCNT0 for accessing

Timer/Counter0 counter value and so on.

The definitions in Table 11-1 are also used extensively throughout the document.

Table 11-1. Definitions

Constant

BOTTOM

MAX

Description

The counter reaches BOTTOM when it becomes 0x00

The counter reaches its MAXimum when it becomes 0xFF (decimal 255)

The counter reaches the TOP when it becomes equal to the highest value in the count

sequence. The TOP value can be assigned to be the fixed value 0xFF (MAX) or the

value stored in the OCR0A Register. The assignment depends on the mode of operation

TOP

11.3 Timer/Counter0 Prescaler and Clock Sources

The Timer/Counter can be clocked by an internal or an external clock source. The clock source

is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits

located in the Timer/Counter0 Control Register (TCCR0B).

11.3.1

Internal Clock Source with Prescaler

Timer/Counter0 can be clocked directly by the system clock (by setting the CS02:0 = 1). This

provides the fastest operation, with a maximum timer/counter clock frequency equal to system

clock frequency (f_{CLK_I/O}). Alternatively, one of four taps from the prescaler can be used as a

clock source. The prescaled clock has a frequency of either f_{CLK_I/O}/8, f_{CLK_I/O}/64, f_{CLK_I/O}/256, or

f_{CLK_I/O}/1024.

11.3.2

68

Prescaler Reset

The prescaler is free running, i.e. it operates independently of the Clock Select logic of

Timer/Counter0. Since the prescaler is not affected by the timer/counter’s clock select, the state

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ATtiny25/45/85

of the prescaler will have implications for situations where a prescaled clock is used. One exam-

ple of a prescaling artifact is when the timer/counter is enabled and clocked by the prescaler (6 >

CS02:0 > 1). The number of system clock cycles from when the timer is enabled to the first count

occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler divisor (8, 64,

256, or 1024).

It is possible to use the Prescaler Reset for synchronizing the Timer/Counter to program

execution.

11.3.3

External Clock Source

An external clock source applied to the T0 pin can be used as timer/counter clock (clk_T0). The T0

pin is sampled once every system clock cycle by the pin synchronization logic. The synchro-

nized (sampled) signal is then passed through the edge detector. Figure 11-2 shows a functional

equivalent block diagram of the T0 synchronization and edge detector logic. The registers are

clocked at the positive edge of the internal system clock (clk_I/O). The latch is transparent in the

high period of the internal system clock.

The edge detector generates one clk_T₀pulse for each positive (CS02:0 = 7) or negative (CS02:0

= 6) edge it detects.

Figure 11-2. T0 Pin Sampling

Tn_sync

(To Clock

Tn

D

Q

D

Q

D

Q

Select Logic)

LE

clk_I/O

Synchronization

Edge Detector

The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock cycles

from an edge has been applied to the T0 pin to the counter is updated.

Enabling and disabling of the clock input must be done when T0 has been stable for at least one

system clock cycle, otherwise it is a risk that a false timer/counter clock pulse is generated.

Each half period of the external clock applied must be longer than one system clock cycle to

ensure correct sampling. The external clock must be guaranteed to have less than half the sys-

tem clock frequency (f_ExtClk< f_{clk_I/O}/2) given a 50/50% duty cycle. Since the edge detector uses

sampling, the maximum frequency of an external clock it can detect is half the sampling fre-

quency (following the Nyquist sampling theorem). However, due to variation of the system clock

frequency and duty cycle caused by oscillator source (crystal, resonator, and capacitors) toler-

ances, it is recommended that maximum frequency of an external clock source is less than

f_{clk_I/O}/2.5.

An external clock source can not be prescaled.

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Figure 11-3. Timer/Counter0 Prescaler

clk_I/O

Clear

PSR10

T0

Synchronization

clk_T0

The synchronization logic on the input pins (T0) in Figure 11-3 is shown in Figure 11-2 on page

69.

11.4 Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

11-4 shows a block diagram of the counter and its surroundings.

Figure 11-4. Counter Unit Block Diagram

TOVn

(Int.Req.)

DATA BUS

Clock Select

count

clear

Edge

Detector

Tn

clk_Tn

TCNTn

Control Logic

direction

( From Prescaler )

bottom

top

Signal description (internal signals):

count

direction

clear

Increment or decrement TCNT0 by 1.

Select between increment and decrement.

Clear TCNT0 (set all bits to zero).

clk_Tn

top

bottom

Timer/Counter clock, referred to as clk_T0in the following.

Signalize that TCNT0 has reached maximum value.

Signalize that TCNT0 has reached minimum value (zero).

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Depending of the mode of operation used, the counter is cleared, incremented, or decremented

at each timer clock (clk_T0). clk_T0can be generated from an external or internal clock source,

selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the

timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of

whether clk_T0is present or not. A CPU write overrides (has priority over) all counter clear or

count operations.

The counting sequence is determined by the setting of the WGM01 and WGM00 bits located in

the Timer/Counter Control Register (TCCR0A) and the WGM02 bit located in the Timer/Counter

Control Register B (TCCR0B). There are close connections between how the counter behaves

(counts) and how waveforms are generated on the Output Compare output OC0A. For more

details about advanced counting sequences and waveform generation, see “Modes of Opera-

tion” on page 74.

The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected by

the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.

11.5 Output Compare Unit

The 8-bit comparator continuously compares TCNT0 with the Output Compare Registers

(OCR0A and OCR0B). Whenever TCNT0 equals OCR0A or OCR0B, the comparator signals a

match. A match will set the Output Compare Flag (OCF0A or OCF0B) at the next timer clock

cycle. If the corresponding interrupt is enabled, the Output Compare Flag generates an Output

Compare interrupt. The Output Compare Flag is automatically cleared when the interrupt is exe-

cuted. Alternatively, the flag can be cleared by software by writing a logical one to its I/O bit

location. The Waveform Generator uses the match signal to generate an output according to

operating mode set by the WGM02:0 bits and Compare Output mode (COM0x1:0) bits. The max

and bottom signals are used by the Waveform Generator for handling the special cases of the

extreme values in some modes of operation (See “Modes of Operation” on page 74.).

Figure 11-5 shows a block diagram of the Output Compare unit.

Figure 11-5. Output Compare Unit, Block Diagram

DATA BUS

OCRnx

TCNTn

= (8-bit Comparator )

OCFnx (Int.Req.)

top

bottom

FOCn

Waveform Generator

OCnx

WGMn1:0

COMnX1:0

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The OCR0x Registers are double buffered when using any of the Pulse Width Modulation

(PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the dou-

ble buffering is disabled. The double buffering synchronizes the update of the OCR0x Compare

Registers to either top or bottom of the counting sequence. The synchronization prevents the

occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output glitch-free.

The OCR0x Register access may seem complex, but this is not case. When the double buffering

is enabled, the CPU has access to the OCR0x Buffer Register, and if double buffering is dis-

abled the CPU will access the OCR0x directly.

11.5.1

Force Output Compare

In non-PWM waveform generation modes, the match output of the comparator can be forced by

writing a one to the Force Output Compare (FOC0x) bit. Forcing Compare Match will not set the

OCF0x Flag or reload/clear the timer, but the OC0x pin will be updated as if a real Compare

Match had occurred (the COM0x1:0 bits settings define whether the OC0x pin is set, cleared or

toggled).

11.5.2

11.5.3

Compare Match Blocking by TCNT0 Write

All CPU write operations to the TCNT0 Register will block any Compare Match that occur in the

next timer clock cycle, even when the timer is stopped. This feature allows OCR0x to be initial-

ized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter clock is

enabled.

Using the Output Compare Unit

Since writing TCNT0 in any mode of operation will block all Compare Matches for one timer

clock cycle, there are risks involved when changing TCNT0 when using the Output Compare

Unit, independently of whether the Timer/Counter is running or not. If the value written to TCNT0

equals the OCR0x value, the Compare Match will be missed, resulting in incorrect waveform

generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the counter is

down-counting.

The setup of the OC0x should be performed before setting the Data Direction Register for the

port pin to output. The easiest way of setting the OC0x value is to use the Force Output Com-

pare (FOC0x) strobe bits in Normal mode. The OC0x Registers keep their values even when

changing between Waveform Generation modes.

Be aware that the COM0x1:0 bits are not double buffered together with the compare value.

Changing the COM0x1:0 bits will take effect immediately.

11.6 Compare Match Output Unit

The Compare Output mode (COM0x1:0) bits have two functions. The Waveform Generator uses

the COM0x1:0 bits for defining the Output Compare (OC0x) state at the next Compare Match.

Also, the COM0x1:0 bits control the OC0x pin output source. Figure 11-6 shows a simplified

schematic of the logic affected by the COM0x1:0 bit setting. The I/O Registers, I/O bits, and I/O

pins in the figure are shown in bold. Only the parts of the general I/O Port Control Registers

(DDR and PORT) that are affected by the COM0x1:0 bits are shown. When referring to the

OC0x state, the reference is for the internal OC0x Register, not the OC0x pin. If a system reset

occur, the OC0x Register is reset to “0”.

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Figure 11-6. Compare Match Output Unit, Schematic

COMnx1

Waveform

Generator

COMnx0

FOCn

D

Q

1

0

OCn

OCnx

D

Q

PORT

D

Q

DDR

clk_I/O

The general I/O port function is overridden by the Output Compare (OC0x) from the Waveform

Generator if either of the COM0x1:0 bits are set. However, the OC0x pin direction (input or out-

put) is still controlled by the Data Direction Register (DDR) for the port pin. The Data Direction

Register bit for the OC0x pin (DDR_OC0x) must be set as output before the OC0x value is visi-

ble on the pin. The port override function is independent of the Waveform Generation mode.

The design of the Output Compare pin logic allows initialization of the OC0x state before the out-

put is enabled. Note that some COM0x1:0 bit settings are reserved for certain modes of

operation. See “Register Description” on page 80.

11.6.1

Compare Output Mode and Waveform Generation

The Waveform Generator uses the COM0x1:0 bits differently in Normal, CTC, and PWM modes.

For all modes, setting the COM0x1:0 = 0 tells the Waveform Generator that no action on the

OC0x Register is to be performed on the next Compare Match. For compare output actions in

the non-PWM modes refer to Table 11-2 on page 80. For fast PWM mode, refer to Table 11-3 on

page 81, and for phase correct PWM refer to Table 11-4 on page 81.

A change of the COM0x1:0 bits state will have effect at the first Compare Match after the bits are

written. For non-PWM modes, the action can be forced to have immediate effect by using the

FOC0x strobe bits.

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11.7 Modes of Operation

The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins, is

defined by the combination of the Waveform Generation mode (WGM02:0) and Compare Output

mode (COM0x1:0) bits. The Compare Output mode bits do not affect the counting sequence,

while the Waveform Generation mode bits do. The COM0x1:0 bits control whether the PWM out-

put generated should be inverted or not (inverted or non-inverted PWM). For non-PWM modes

the COM0x1:0 bits control whether the output should be set, cleared, or toggled at a Compare

Match (See “Compare Match Output Unit” on page 72.).

For detailed timing information refer to Figure 11-10, Figure 11-11, Figure 11-12 and Figure 11-

13 in “Timer/Counter Timing Diagrams” on page 78.

11.7.1

Normal Mode

The simplest mode of operation is the Normal mode (WGM02:0 = 0). In this mode the counting

direction is always up (incrementing), and no counter clear is performed. The counter simply

overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-

tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the same

timer clock cycle as the TCNT0 becomes zero. The TOV0 Flag in this case behaves like a ninth

bit, except that it is only set, not cleared. However, combined with the timer overflow interrupt

that automatically clears the TOV0 Flag, the timer resolution can be increased by software.

There are no special cases to consider in the Normal mode, a new counter value can be written

anytime.

The Output Compare Unit can be used to generate interrupts at some given time. Using the Out-

put Compare to generate waveforms in Normal mode is not recommended, since this will

occupy too much of the CPU time.

11.7.2

Clear Timer on Compare Match (CTC) Mode

In Clear Timer on Compare or CTC mode (WGM02:0 = 2), the OCR0A Register is used to

manipulate the counter resolution. In CTC mode the counter is cleared to zero when the counter

value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter, hence

also its resolution. This mode allows greater control of the Compare Match output frequency. It

also simplifies the operation of counting external events.

The timing diagram for the CTC mode is shown in Figure 11-7. The counter value (TCNT0)

increases until a Compare Match occurs between TCNT0 and OCR0A, and then counter

(TCNT0) is cleared.

Figure 11-7. CTC Mode, Timing Diagram

OCnx Interrupt Flag Set

TCNTn

OCn

(Toggle)

(COMnx1:0 = 1)

1

2

3

4

Period

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An interrupt can be generated each time the counter value reaches the TOP value by using the

OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating

the TOP value. However, changing TOP to a value close to BOTTOM when the counter is run-

ning with none or a low prescaler value must be done with care since the CTC mode does not

have the double buffering feature. If the new value written to OCR0A is lower than the current

value of TCNT0, the counter will miss the Compare Match. The counter will then have to count to

its maximum value (0xFF) and wrap around starting at 0x00 before the Compare Match can

occur.

For generating a waveform output in CTC mode, the OC0A output can be set to toggle its logical

level on each Compare Match by setting the Compare Output mode bits to toggle mode

(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction for

the pin is set to output. The waveform generated will have a maximum frequency of f_OC0

_{clk_I/O}/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the following

equation:

=

f

clk_I/O

f

= --------------------------------------------------

OCnx

2 ⋅ N ⋅ (1 + OCRnx)

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

As for the Normal mode of operation, the TOV0 Flag is set in the same timer clock cycle that the

counter counts from MAX to 0x00.

11.7.3

Fast PWM Mode

The fast Pulse Width Modulation or fast PWM mode (WGM02:0 = 3 or 7) provides a high fre-

quency PWM waveform generation option. The fast PWM differs from the other PWM option by

its single-slope operation. The counter counts from BOTTOM to TOP then restarts from BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 3, and OCR0A when WGM2:0 = 7.

In non-inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare

Match between TCNT0 and OCR0x, and set at BOTTOM. In inverting Compare Output mode,

the output is set on Compare Match and cleared at BOTTOM.

Due to the single-slope operation, the operating frequency of the fast PWM mode can be twice

as high as the phase correct PWM mode that use dual-slope operation. This high frequency

makes the fast PWM mode well suited for power regulation, rectification, and DAC applications.

High frequency allows physically small sized external components (coils, capacitors), and there-

fore reduces total system cost.

In fast PWM mode, the counter is incremented until the counter value matches the TOP value.

The counter is then cleared at the following timer clock cycle. The timing diagram for the fast

PWM mode is shown in Figure 11-8. The TCNT0 value is in the timing diagram shown as a his-

togram for illustrating the single-slope operation. The diagram includes non-inverted and

inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Com-

pare Matches between OCR0x and TCNT0.

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Figure 11-8. Fast PWM Mode, Timing Diagram

OCRnx Interrupt Flag Set

OCRnx Update and

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

(COMnx1:0 = 3)

OCn

1

2

3

4

5

6

7

Period

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches TOP. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0x pins.

Setting the COM0x1:0 bits to two will produce a non-inverted PWM and an inverted PWM output

can be generated by setting the COM0x1:0 to three: Setting the COM0A1:0 bits to one allowes

the AC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is not available

for the OC0B pin (See Table 11-3 on page 81). The actual OC0x value will only be visible on the

port pin if the data direction for the port pin is set as output. The PWM waveform is generated by

setting (or clearing) the OC0x Register at the Compare Match between OCR0x and TCNT0, and

clearing (or setting) the OC0x Register at the timer clock cycle the counter is cleared (changes

from TOP to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

f

clk_I/O

f

= ------------------

OCnxPWM

N ⋅ 256

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represents special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will

be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will result

in a constantly high or low output (depending on the polarity of the output set by the COM0A1:0

bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC0x to toggle its logical level on each Compare Match (COM0x1:0 = 1). The waveform

generated will have a maximum frequency of f_OC0= f_{clk_I/O}/2 when OCR0A is set to zero. This

feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the Out-

put Compare unit is enabled in the fast PWM mode.

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11.7.4

Phase Correct PWM Mode

The phase correct PWM mode (WGM02:0 = 1 or 5) provides a high resolution phase correct

PWM waveform generation option. The phase correct PWM mode is based on a dual-slope

operation. The counter counts repeatedly from BOTTOM to TOP and then from TOP to BOT-

TOM. TOP is defined as 0xFF when WGM2:0 = 1, and OCR0A when WGM2:0 = 5. In non-

inverting Compare Output mode, the Output Compare (OC0x) is cleared on the Compare Match

between TCNT0 and OCR0x while upcounting, and set on the Compare Match while down-

counting. In inverting Output Compare mode, the operation is inverted. The dual-slope operation

has lower maximum operation frequency than single slope operation. However, due to the sym-

metric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

In phase correct PWM mode the counter is incremented until the counter value matches TOP.

When the counter reaches TOP, it changes the count direction. The TCNT0 value will be equal

to TOP for one timer clock cycle. The timing diagram for the phase correct PWM mode is shown

on Figure 11-9. The TCNT0 value is in the timing diagram shown as a histogram for illustrating

the dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The

small horizontal line marks on the TCNT0 slopes represent Compare Matches between OCR0x

and TCNT0.

Figure 11-9. Phase Correct PWM Mode, Timing Diagram

OCnx Interrupt Flag Set

OCRnx Update

TOVn Interrupt Flag Set

TCNTn

(COMnx1:0 = 2)

OCn

(COMnx1:0 = 3)

OCn

1

2

3

Period

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC0x pins. Setting the COM0x1:0 bits to two will produce a non-inverted PWM. An inverted

PWM output can be generated by setting the COM0x1:0 to three: Setting the COM0A0 bits to

one allows the OC0A pin to toggle on Compare Matches if the WGM02 bit is set. This option is

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not available for the OC0B pin (See Table 11-4 on page 81). The actual OC0x value will only be

visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is

generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x

and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Com-

pare Match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for

the output when using phase correct PWM can be calculated by the following equation:

f

clk_I/O

f

= ------------------

OCnxPCPWM

N ⋅ 510

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

The extreme values for the OCR0A Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the

output will be continuously low and if set equal to MAX the output will be continuously high for

non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 11-9 OCn has a transition from high to low even though

there is no Compare Match. The point of this transition is to guaratee symmetry around BOT-

TOM. There are two cases that give a transition without Compare Match, as follows:

• OCR0A changes its value from MAX, like in Figure 11-9. When the OCR0A value is MAX the

OCn pin value is the same as the result of a down-counting Compare Match. To ensure

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-

counting Compare Match.

• The timer starts counting from a value higher than the one in OCR0A, and for that reason

misses the Compare Match and hence the OCn change that would have happened on the

way up.

11.8 Timer/Counter Timing Diagrams

The Timer/Counter is a synchronous design and the timer clock (clk_T0) is therefore shown as a

clock enable signal in the following figures. The figures include information on when Interrupt

Flags are set. Figure 11-10 contains timing data for basic Timer/Counter operation. The figure

shows the count sequence close to the MAX value in all modes other than phase correct PWM

mode.

Figure 11-10. Timer/Counter Timing Diagram, no Prescaling

clk_I/O

clk_Tn

(clk_I/O/1)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 11-11 shows the same timing data, but with the prescaler enabled.

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Figure 11-11. Timer/Counter Timing Diagram, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

TOVn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

Figure 11-12 shows the setting of OCF0B in all modes and OCF0A in all modes except CTC

mode and PWM mode, where OCR0A is TOP.

Figure 11-12. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

OCRnx

OCFnx

OCRnx - 1

OCRnx

OCRnx + 1

OCRnx + 2

OCRnx Value

Figure 11-13 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode and fast

PWM mode where OCR0A is TOP.

Figure 11-13. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres-

caler (f_{clk_I/O}/8)

clk_I/O

clk_Tn

(clk_I/O/8)

TCNTn

(CTC)

TOP - 1

TOP

BOTTOM

BOTTOM + 1

OCRnx

TOP

OCFnx

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11.9 Register Description

11.9.1

GTCCR – General Timer/Counter Control Register

Bit

7

6

5

4

3

2

1

0

0x2C

TSM

R/W

0

PWM1B

COM1B1

COM1B0

FOC1B

FOC1A

PSR1

PSR0

R/W

0

GTCCR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

• Bit 7 – TSM: Timer/Counter Synchronization Mode

Writing the TSM bit to one activates the Timer/Counter Synchronization Mode. In this mode, the

value written to PSR0 is kept, hence keeping the Prescaler Reset signal asserted. This ensures

that the timer/counter is halted and can be configured without the risk of advancing during con-

figuration. When the TSM bit is written to zero, the PSR0 bit is cleared by hardware, and the

timer/counter start counting.

• Bit 0 – PSR0: Prescaler Reset Timer/Counter0

When this bit is one, the Timer/Counter0 prescaler will be Reset. This bit is normally cleared

immediately by hardware, except if the TSM bit is set.

11.9.2

TCCR0A – Timer/Counter Control Register A

Bit

0x2A

7

6

5

4

3

–

R

0

2

–

R

0

1

0

COM0A1

COM0A0

COM0B1

COM0B0

WGM01

R/W

0

WGM00

R/W

0

TCCR0A

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

• Bits 7:6 – COM0A1:0: Compare Match Output A Mode

• Bits 5:4 – COM0B1:0: Compare Match Output B Mode

The COM0A1:0 and COM0B1:0 bits control the behaviour of Output Compare pins OC0A and

OC0B, respectively. If any of the COM0A1:0 bits are set, the OC0A output overrides the normal

port functionality of the I/O pin it is connected to. Similarly, if any of the COM0B1:0 bits are set,

the OC0B output overrides the normal port functionality of the I/O pin it is connected to. How-

ever, note that the Data Direction Register (DDR) bit corresponding to the OC0A and OC0B pins

must be set in order to enable the output driver.

When OC0A/OC0B is connected to the I/O pin, the function of the COM0A1:0/COM0B1:0 bits

depend on the WGM02:0 bit setting. Table 11-2 shows the COM0x1:0 bit functionality when the

WGM02:0 bits are set to a normal or CTC mode (non-PWM).

Table 11-2. Compare Output Mode, non-PWM Mode

COM0A1

COM0B1

COM0A0

COM0B0

Description

0

1

0

1

0

1

Normal port operation, OC0A/OC0B disconnected.

Toggle OC0A/OC0B on Compare Match

Clear OC0A/OC0B on Compare Match

Set OC0A/OC0B on Compare Match

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Table 11-3 shows the COM0x1:0 bit functionality when the WGM02:0 bits are set to fast PWM

mode.

Table 11-3. Compare Output Mode, Fast PWM Mode⁽¹⁾

COM0A1

COM0B1

COM0A0

COM0B0

Description

0

1

Normal port operation, OC0A/OC0B disconnected.

Reserved

Clear OC0A/OC0B on Compare Match, set OC0A/OC0B at BOTTOM

(non-inverting mode)

1

0

1

Set OC0A/OC0B on Compare Match, clear OC0A/OC0B at BOTTOM

(inverting mode)

Note:

1. A special case occurs when OCR0A or OCR0B equals TOP and COM0A1/COM0B1 is set. In

this case, the compare match is ignored, but the set or clear is done at BOTTOM. See “Fast

PWM Mode” on page 75 for more details.

Table 11-4 shows the COM0x1:0 bit functionality when the WGM02:0 bits are set to phase cor-

rect PWM mode.

Table 11-4. Compare Output Mode, Phase Correct PWM Mode⁽¹⁾

COM0A1

COM0B1

COM0A0

COM0B0

Description

0

1

Normal port operation, OC0A/OC0B disconnected.

Reserved

Clear OC0A/OC0B on Compare Match when up-counting.

Set OC0A/OC0B on Compare Match when down-counting.

1

0

1

Set OC0A/OC0B on Compare Match when up-counting.

Clear OC0A/OC0B on Compare Match when down-counting.

Note:

1. A special case occurs when OCR0A or OCR0B equals TOP and COM0A1/COM0B1 is set. In

this case, the Compare Match is ignored, but the set or clear is done at TOP. See “Phase Cor-

rect PWM Mode” on page 77 for more details.

• Bits 3, 2 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bits 1:0 – WGM01:0: Waveform Generation Mode

Combined with the WGM02 bit found in the TCCR0B Register, these bits control the counting

sequence of the counter, the source for maximum (TOP) counter value, and what type of wave-

form generation to be used, see Table 11-5. Modes of operation supported by the Timer/Counter

unit are: Normal mode (counter), Clear Timer on Compare Match (CTC) mode, and two types of

Pulse Width Modulation (PWM) modes (see “Modes of Operation” on page 74).

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Table 11-5. Waveform Generation Mode Bit Description

WGM

02

WGM

01

WGM Timer/Counter Mode

Update of

OCRx at

TOV Flag

Set on

Mode

00

of Operation

TOP

0xFF

OCRA

0xFF

–

0

1

2

3

4

5

6

7

0

1

0

1

0

1

0

Normal

Immediate

TOP

MAX⁽¹⁾

BOTTOM⁽²⁾

MAX⁽¹⁾

–

1

PWM, Phase Correct

CTC

0

Immediate

BOTTOM⁽²⁾

–

1

Fast PWM

0

Reserved

1

PWM, Phase Correct

Reserved

OCRA

–

TOP

BOTTOM⁽²⁾

0

–

1

Fast PWM

OCRA

BOTTOM⁽²⁾

TOP

Notes: 1. MAX

= 0xFF

2. BOTTOM = 0x00

11.9.3

TCCR0B – Timer/Counter Control Register B

Bit

7

6

5

–

R

0

4

–

R

0

3

2

1

0

0x33

FOC0A

FOC0B

WGM02

R/W

0

CS02

R/W

0

CS01

R/W

0

CS00

R/W

0

TCCR0B

Read/Write

Initial Value

W

0

W

0

• Bit 7 – FOC0A: Force Output Compare A

The FOC0A bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC0A output is

changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is implemented as a

strobe. Therefore it is the value present in the COM0A1:0 bits that determines the effect of the

forced compare.

A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0A as TOP.

The FOC0A bit is always read as zero.

• Bit 6 – FOC0B: Force Output Compare B

The FOC0B bit is only active when the WGM bits specify a non-PWM mode.

However, for ensuring compatibility with future devices, this bit must be set to zero when

TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0B bit,

an immediate Compare Match is forced on the Waveform Generation unit. The OC0B output is

changed according to its COM0B1:0 bits setting. Note that the FOC0B bit is implemented as a

strobe. Therefore it is the value present in the COM0B1:0 bits that determines the effect of the

forced compare.

A FOC0B strobe will not generate any interrupt, nor will it clear the timer in CTC mode using

OCR0B as TOP.

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The FOC0B bit is always read as zero.

• Bits 5:4 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bit 3 – WGM02: Waveform Generation Mode

See the description in the “TCCR0A – Timer/Counter Control Register A” on page 80.

• Bits 2:0 – CS02:0: Clock Select

The three Clock Select bits select the clock source to be used by the Timer/Counter.

Table 11-6. Clock Select Bit Description

CS02

CS01

CS00

Description

0

1

0

1

0

1

0

1

0

1

0

1

0

1

No clock source (Timer/Counter stopped)

clk_I/O/(No prescaling)

clk_I/O/8 (From prescaler)

clk_I/O/64 (From prescaler)

clk_I/O/256 (From prescaler)

clk_I/O/1024 (From prescaler)

External clock source on T0 pin. Clock on falling edge.

External clock source on T0 pin. Clock on rising edge.

If external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the

counter even if the pin is configured as an output. This feature allows software control of the

counting.

11.9.4

TCNT0 – Timer/Counter Register

Bit

7

6

5

4

3

2

1

0

0x32

TCNT0[7:0]

TCNT0

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Timer/Counter Register gives direct access, both for read and write operations, to the

Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Compare

Match on the following timer clock. Modifying the counter (TCNT0) while the counter is running,

introduces a risk of missing a Compare Match between TCNT0 and the OCR0x Registers.

11.9.5

OCR0A – Output Compare Register A

Bit

7

6

5

4

3

2

1

0

0x29

OCR0A[7:0]

OCR0A

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register A contains an 8-bit value that is continuously compared with the

counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC0A pin.

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11.9.6

OCR0B – Output Compare Register B

Bit

7

6

5

4

3

2

1

0

0x28

OCR0B[7:0]

OCR0B

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The Output Compare Register B contains an 8-bit value that is continuously compared with the

counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or to

generate a waveform output on the OC0B pin.

11.9.7

TIMSK – Timer/Counter Interrupt Mask Register

Bit

0x39

7

6

5

4

OCIE0A

R/W

0

3

OCIE0B

R/W

0

2

TOIE1

R/W

0

1

TOIE0

R/W

0

–

OCIE1A

OCIE1B

R/W

0

TIMSK

Read/Write

Initial Value

R

0

R/W

0

R

0

• Bits 7, 0 – Res: Reserved Bits

These bits are reserved bits and will always read as zero.

• Bit 4 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable

When the OCIE0A bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is executed

if a Compare Match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the

Timer/Counter 0 Interrupt Flag Register – TIFR0.

• Bit 3 – OCIE0B: Timer/Counter Output Compare Match B Interrupt Enable

When the OCIE0B bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter Compare Match B interrupt is enabled. The corresponding interrupt is executed if

a Compare Match in Timer/Counter occurs, i.e., when the OCF0B bit is set in the Timer/Counter

Interrupt Flag Register – TIFR0.

• Bit 1 – TOIE0: Timer/Counter0 Overflow Interrupt Enable

When the TOIE0 bit is written to one, and the I-bit in the Status Register is set, the

Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an

overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter 0 Inter-

rupt Flag Register – TIFR0.

11.9.8

TIFR – Timer/Counter Interrupt Flag Register

Bit

0x38

7

6

5

OCF1B

R/W

0

4

OCF0A

R/W

0

3

OCF0B

R/W

0

2

TOV1

R/W

0

1

TOV0

R/W

0

–

OCF1A

TIFR

Read/Write

Initial Value

R

0

R/W

0

R

0

• Bits 7, 0 – Res: Reserved Bits

These bits are reserved bits and will always read as zero.

• Bit 4– OCF0A: Output Compare Flag 0 A

The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data

in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0A is cleared by writing a logic one to

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the flag. When the I-bit in SREG, OCIE0A (Timer/Counter0 Compare Match Interrupt Enable),

and OCF0A are set, the Timer/Counter0 Compare Match Interrupt is executed.

• Bit 3 – OCF0B: Output Compare Flag 0 B

The OCF0B bit is set when a Compare Match occurs between the Timer/Counter and the data in

OCR0B – Output Compare Register0 B. OCF0B is cleared by hardware when executing the cor-

responding interrupt handling vector. Alternatively, OCF0B is cleared by writing a logic one to

the flag. When the I-bit in SREG, OCIE0B (Timer/Counter Compare B Match Interrupt Enable),

and OCF0B are set, the Timer/Counter Compare Match Interrupt is executed.

• Bit 1 – TOV0: Timer/Counter0 Overflow Flag

The bit TOV0 is set when an overflow occurs in Timer/Counter0. TOV0 is cleared by hardware

when executing the corresponding interrupt handling vector. Alternatively, TOV0 is cleared by

writing a logic one to the flag. When the SREG I-bit, TOIE0 (Timer/Counter0 Overflow Interrupt

Enable), and TOV0 are set, the Timer/Counter0 Overflow interrupt is executed.

The setting of this flag is dependent of the WGM02:0 bit setting. Refer to Table 11-5, “Waveform

Generation Mode Bit Description” on page 82.

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12. 8-bit Timer/Counter1

The Timer/Counter1 is a general purpose 8-bit Timer/Counter module that has a separate pres-

caling selection from the separate prescaler.

12.1 Timer/Counter1 Prescaler

Figure 12-1 shows the Timer/Counter1 prescaler that supports two clocking modes, a synchro-

nous clocking mode and an asynchronous clocking mode. The synchronous clocking mode uses

the system clock (CK) as the clock timebase and asynchronous mode uses the fast peripheral

clock (PCK) as the clock time base. The PCKE bit from the PLLCSR register enables the asyn-

chronous mode when it is set (‘1’).

Figure 12-1. Timer/Counter1 Prescaler

PSR1

PCKE

CK

T1CK

14-BIT

T/C PRESCALER

PCK 64/32 MHz

0

CS10

CS11

CS12

CS13

TIMER/COUNTER1 COUNT ENABLE

In the asynchronous clocking mode the clock selections are from PCK to PCK/16384 and stop,

and in the synchronous clocking mode the clock selections are from CK to CK/16384 and stop.

The clock options are described in Table 12-5 on page 92 and the Timer/Counter1 Control Reg-

ister, TCCR1. Setting the PSR1 bit in GTCCR register resets the prescaler. The PCKE bit in the

PLLCSR register enables the asynchronous mode. The frequency of the fast peripheral clock is

64 MHz (or 32 MHz in Low Speed Mode).

12.2 Counter and Compare Units

The Timer/Counter1 general operation is described in the asynchronous mode and the opera-

tion in the synchronous mode is mentioned only if there are differences between these two

modes. Figure 12-2 shows Timer/Counter 1 synchronization register block diagram and syn-

chronization delays in between registers. Note that all clock gating details are not shown in the

figure. The Timer/Counter1 register values go through the internal synchronization registers,

which cause the input synchronization delay, before affecting the counter operation. The regis-

ters TCCR1, GTCCR, OCR1A, OCR1B, and OCR1C can be read back right after writing the

register. The read back values are delayed for the Timer/Counter1 (TCNT1) register and flags

(OCF1A, OCF1B, and TOV1), because of the input and output synchronization.

The Timer/Counter1 features a high resolution and a high accuracy usage with the lower pres-

caling opportunities. It can also support two accurate, high speed, 8-bit Pulse Width Modulators

using clock speeds up to 64 MHz (or 32 MHz in Low Speed Mode). In this mode,

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Timer/Counter1 and the output compare registers serve as dual stand-alone PWMs with non-

overlapping non-inverted and inverted outputs. Refer to page 89 for a detailed description on

this function. Similarly, the high prescaling opportunities make this unit useful for lower speed

functions or exact timing functions with infrequent actions.

Figure 12-2. Timer/Counter 1 Synchronization Register Block Diagram.

8-BIT DATABUS

IO-registers

OCR1A

Input synchronization

registers

Timer/Counter1

Output synchronization

registers

OCR1A_SI

OCR1B_SI

OCR1C_SI

TCCR1_SI

GTCCR_SI

TCNT1

OCF1A

OCR1B

OCR1C

TCCR1

GTCCR

TCNT_SO

OCF1A_SO

OCF1B_SO

TOV1_SO

TCNT1

OCF1A

OCF1B

TOV1

TCNT1_SI

OCF1A_SI

OCF1B_SI

TOV1_SI

OCF1B

TOV1

PCKE

CK

S

A

S

A

PCK

SYNC

MODE

1/2 CK Delay

1 CK Delay

1/2 CK Delay

ASYNC

MODE

1..2 PCK Delay

1 PCK Delay

~1 CK Delay

No Delay

Timer/Counter1 and the prescaler allow running the CPU from any clock source while the pres-

caler is operating on the fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock in the

asynchronous mode.

Note that the system clock frequency must be lower than one third of the PCK frequency. The

synchronization mechanism of the asynchronous Timer/Counter1 needs at least two edges of

the PCK when the system clock is high. If the frequency of the system clock is too high, it is a

risk that data or control values are lost.

The following Figure 12-3 shows the block diagram for Timer/Counter1.

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Figure 12-3. Timer/Counter1 Block Diagram

T/C1 OVER- T/C1 COMPARE T/C1 COMPARE

FLOW IRQ MATCH A IRQ MATCH B IRQ

OC1A

(PB1)

OC1A

(PB0)

OC1B

(PB4)

OC1B

(PB3)

DEAD TIME GENERATOR

TIMER INT. MASK

REGISTER (TIMSK)

TIMER INT. FLAG

REGISTER (TIFR)

T/C CONTROL

REGISTER 1 (TCCR1)

GLOBAL T/C CONTROL

REGISTER (GTCCR)

TIMER/COUNTER1

(TCNT1)

T/C CLEAR

CK

T/C1 CONTROL

LOGIC

PCK

8-BIT COMPARATOR

T/C1 OUTPUT

COMPARE REGISTER

(OCR1B)

T/C1 OUTPUT

COMPARE REGISTER

(OCR1C)

T/C1 OUTPUT

COMPARE REGISTER

(OCR1A)

8-BIT DATABUS

Three status flags (overflow and compare matches) are found in the Timer/Counter Interrupt

Flag Register - TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1

and GTCCR. The interrupt enable/disable settings are found in the Timer/Counter Interrupt

Mask Register - TIMSK.

The Timer/Counter1 contains three Output Compare Registers, OCR1A, OCR1B, and OCR1C

as the data source to be compared with the Timer/Counter1 contents. In normal mode the Out-

put Compare functions are operational with all three output compare registers. OCR1A

determines action on the OC1A pin (PB1), and it can generate Timer1 OC1A interrupt in normal

mode and in PWM mode. Likewise, OCR1B determines action on the OC1B pin (PB4) and it can

generate Timer1 OC1B interrupt in normal mode and in PWM mode. OCR1C holds the

Timer/Counter maximum value, i.e. the clear on compare match value. In the normal mode an

overflow interrupt (TOV1) is generated when Timer/Counter1 counts from $FF to $00, while in

the PWM mode the overflow interrupt is generated when Timer/Counter1 counts either from $FF

to $00 or from OCR1C to $00. The inverted PWM outputs OC1A and OC1B are not connected in

normal mode.

In PWM mode, OCR1A and OCR1B provide the data values against which the Timer Counter

value is compared. Upon compare match the PWM outputs (OC1A, OC1A, OC1B, OC1B) are

generated. In PWM mode, the Timer Counter counts up to the value specified in the output com-

pare register OCR1C and starts again from $00. This feature allows limiting the counter “full”

value to a specified value, lower than $FF. Together with the many prescaler options, flexible

PWM frequency selection is provided. Table 12-3 on page 91 lists clock selection and OCR1C

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values to obtain PWM frequencies from 20 kHz to 250 kHz in 10 kHz steps and from 250 kHz to

500 kHz in 50 kHz steps. Higher PWM frequencies can be obtained at the expense of resolution.

12.2.1

12.2.2

Timer/Counter1 Initialization for Asynchronous Mode

To set Timer/Counter1 in asynchronous mode first enable PLL and then wait 100 µs for PLL to

stabilize. Next, poll the PLOCK bit until it is set and then set the PCKE bit.

Timer/Counter1 in PWM Mode

When the PWM mode is selected, Timer/Counter1 and the Output Compare Register C -

OCR1C form a dual 8-bit, free-running and glitch-free PWM generator with outputs on the

PB1(OC1A) and PB4(OC1B) pins and inverted outputs on pins PB0(OC1A) and PB3(OC1B). As

default non-overlapping times for complementary output pairs are zero, but they can be inserted

using a Dead Time Generator (see description on page 100).

Figure 12-4. The PWM Output Pair

PWM1x

t _non-overlap

=0

x = A or B

When the counter value match the contents of OCR1A or OCR1B, the OC1A and OC1B outputs

are set or cleared according to the COM1A1/COM1A0 or COM1B1/COM1B0 bits in the

Timer/Counter1 Control Register A - TCCR1, as shown in Table 12-1.

Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output

compare register OCR1C, and starting from $00 up again. A compare match with OC1C will set

an overflow interrupt flag (TOV1) after a synchronization delay following the compare event.

Table 12-1. Compare Mode Select in PWM Mode

COM11

COM10

Effect on Output Compare Pins

OC1x not connected.

0

OC1x cleared on compare match. Set whenTCNT1 = $00.

OC1x set on compare match. Cleared when TCNT1 = $00.

0

1

0

1

OC1x cleared on compare match. Set when TCNT1 = $00.

OC1x not connected.

OC1x Set on compare match. Cleared when TCNT1= $00.

OC1x not connected.

Note that in PWM mode, writing to the Output Compare Registers OCR1A or OCR1B, the data

value is first transferred to a temporary location. The value is latched into OCR1A or OCR1B

when the Timer/Counter reaches OCR1C. This prevents the occurrence of odd-length PWM

pulses (glitches) in the event of an unsynchronized OCR1A or OCR1B. See Figure 12-5 for an

example.

89

2586K–AVR–01/08

Figure 12-5. Effects of Unsynchronized OCR Latching

Compare Value changes

Counter Value

Compare Value

PWM Output OC1x

Synchronized OC1x Latch

Compare Value changes

Counter Value

Compare Value

PWM Output OC1x

Glitch

Unsynchronized OC1x Latch

During the time between the write and the latch operation, a read from OCR1A or OCR1B will

read the contents of the temporary location. This means that the most recently written value

always will read out of OCR1A or OCR1B.

When OCR1A or OCR1B contain $00 or the top value, as specified in OCR1C register, the out-

put PB1(OC1A) or PB4(OC1B) is held low or high according to the settings of

COM1A1/COM1A0. This is shown in Table 12-2.

Table 12-2. PWM Outputs OCR1x = $00 or OCR1C, x = A or B

COM1x1

COM1x0

OCR1x

$00

Output OC1x

H

0

1

0

1

L

H

L

OCR1C

$00

L

Not connected.

OCR1C

$00

H

L

OCR1C

In PWM mode, the Timer Overflow Flag - TOV1 is set when the TCNT1 counts to the OCR1C

value and the TCNT1 is reset to $00. The Timer Overflow Interrupt1 is executed when TOV1 is

set provided that Timer Overflow Interrupt and global interrupts are enabled. This also applies to

the Timer Output Compare flags and interrupts.

The frequency of the PWM will be Timer Clock 1 Frequency divided by (OCR1C value + 1). See

the following equation:

f

TCK1

f

= -----------------------------------

PWM

(OCR1C + 1)

Resolution shows how many bits are required to express the value in the OCR1C register and

can be calculated using the following equation:

90

ATtiny25/45/85

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ATtiny25/45/85

R = log2(OCR1C + 1)

Table 12-3. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode

PWM Frequency

20 kHz

Clock Selection

PCK/16

PCK/8

PCK/4

PCK/2

PCK

CS13:CS10

0101

0100

0011

0010

0001

OCR1C

199

132

199

159

132

228

199

177

159

144

132

245

228

212

199

187

177

167

159

255

212

182

159

141

127

RESOLUTION

7.6

30 kHz

7.1

40 kHz

7.6

50 kHz

7.3

60 kHz

7.1

70 kHz

7.8

80 kHz

7.6

90 kHz

7.5

100 kHz

110 kHz

120 kHz

130 kHz

140 kHz

150 kHz

160 kHz

170 kHz

180 kHz

190 kHz

200 kHz

250 kHz

300 kHz

350 kHz

400 kHz

450 kHz

500 kHz

7.3

7.2

7.1

7.9

7.8

7.7

7.6

7.5

7.4

7.3

8.0

PCK

7.7

PCK

7.5

PCK

7.3

PCK

7.1

PCK

7.0

91

2586K–AVR–01/08

12.3 Register Description

12.3.1

TCCR1 – Timer/Counter1 Control Register

Bit

7

CTC1

R/W

0

6

PWM1A

R/W

0

5

COM1A1

R/W

4

COM1A0

R/W

3

CS13

R/W

0

2

CS12

R/W

0

1

CS11

R/W

0

CS10

R/W

0

0x30

TCCR1

Read/Write

Initial value

0

• Bit 7- CTC1 : Clear Timer/Counter on Compare Match

When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle

after a compare match with OCR1C register value. If the control bit is cleared, Timer/Counter1

continues counting and is unaffected by a compare match.

• Bit 6- PWM1A: Pulse Width Modulator A Enable

When set (one) this bit enables PWM mode based on comparator OCR1A in Timer/Counter1

and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C

register value.

• Bits 5,4 - COM1A1, COM1A0: Comparator A Output Mode, Bits 1 and 0

The COM1A1 and COM1A0 control bits determine any output pin action following a compare

match with compare register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A).

Since this is an alternative function to an I/O port, the corresponding direction control bit must be

set (one) in order to control an output pin. Note that OC1A is not connected in normal mode.

Table 12-4. Comparator A Mode Select

COM1A1

COM1A0

Description

0

1

0

1

0

1

Timer/Counter Comparator A disconnected from output pin OC1A.

Toggle the OC1A output line.

Clear the OC1A output line.

Set the OC1A output line

In PWM mode, these bits have different functions. Refer to Table 12-1 on page 89 for a detailed

description.

• Bits 3:0 - CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

Table 12-5. Timer/Counter1 Prescale Select

Synchronous

Asynchronous

Clocking Mode

CS13

CS12

CS11

CS10

Clocking Mode

0

1

0

1

0

1

0

1

0

1

T/C1 stopped

PCK

T/C1 stopped

CK

PCK/2

CK/2

PCK/4

CK/4

PCK/8

CK/8

PCK/16

CK/16

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ATtiny25/45/85

Table 12-5. Timer/Counter1 Prescale Select (Continued)

Asynchronous

Synchronous

CS13

CS12

CS11

CS10

Clocking Mode

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PCK/32

CK/32

PCK/64

CK/64

PCK/128

CK/128

CK/256

CK/512

CK/1024

CK/2048

CK/4096

CK/8192

CK/16384

PCK/256

PCK/512

PCK/1024

PCK/2048

PCK/4096

PCK/8192

PCK/16384

The Stop condition provides a Timer Enable/Disable function.

12.3.2

GTCCR – General Timer/Counter1 Control Register

Bit

0x2C

7

6

5

4

COM1B0

R/W

3

FOC1B

W

2

FOC1A

W

1

PSR1

R/W

0

TSM

PWM1B

COM1B1

PSR0

R/W

0

GTCCR

Read/Write

Initial value

R/W

0

R/W

0

R/W

0

• Bit 6 - PWM1B: Pulse Width Modulator B Enable

When set (one) this bit enables PWM mode based on comparator OCR1B in Timer/Counter1

and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C

register value.

• Bits 5,4 - COM1B1, COM1B0: Comparator B Output Mode, Bits 1 and 0

The COM1B1 and COM1B0 control bits determine any output pin action following a compare

match with compare register B in Timer/Counter1. Output pin actions affect pin PB4 (OC1B).

Since this is an alternative function to an I/O port, the corresponding direction control bit must be

set (one) in order to control an output pin. Note that OC1B is not connected in normal mode.

Table 12-6. Comparator B Mode Select

COM1B1

COM1B0

Description

0

1

0

1

0

1

Timer/Counter Comparator B disconnected from output pin OC1B.

Toggle the OC1B output line.

Clear the OC1B output line.

Set the OC1B output line

In PWM mode, these bits have different functions. Refer to Table 12-1 on page 89 for a detailed

description.

93

2586K–AVR–01/08

• Bit 3 - FOC1B: Force Output Compare Match 1B

Writing a logical one to this bit forces a change in the compare match output pin PB3 (OC1B)

according to the values already set in COM1B1 and COM1B0. If COM1B1 and COM1B0 written

in the same cycle as FOC1B, the new settings will be used. The Force Output Compare bit can

be used to change the output pin value regardless of the timer value. The automatic action pro-

grammed in COM1B1 and COM1B0 takes place as if a compare match had occurred, but no

interrupt is generated. The FOC1B bit always reads as zero. FOC1B is not in use if PWM1B bit

is set.

• Bit 2 - FOC1A: Force Output Compare Match 1A

Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A)

according to the values already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written

in the same cycle as FOC1A, the new settings will be used. The Force Output Compare bit can

be used to change the output pin value regardless of the timer value. The automatic action pro-

grammed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no

interrupt is generated. The FOC1A bit always reads as zero. FOC1A is not in use if PWM1A bit

is set.

• Bit 1 - PSR1 : Prescaler Reset Timer/Counter1

When this bit is set (one), the Timer/Counter prescaler (TCNT1 is unaffected) will be reset. The

bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have

no effect. This bit will always read as zero.

12.3.3

TCNT1 – Timer/Counter1

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

0x2F

LSB

R/W

0

TCNT1

Read/Write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

This 8-bit register contains the value of Timer/Counter1.

Timer/Counter1 is realized as an up counter with read and write access. Due to synchronization

of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by one and half CPU

clock cycles in synchronous mode and at most one CPU clock cycles for asynchronous mode.

12.3.4

OCR1A –Timer/Counter1 Output Compare RegisterA

Bit

0x2E

7

6

5

4

3

2

1

0

MSB

LSB

R/W

0

OCR1A

Read/Write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The output compare register A is an 8-bit read/write register.

The Timer/Counter Output Compare Register A contains data to be continuously compared with

Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does

only occur if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and

OCR1A to the same value does not generate a compare match.

A compare match will set the compare interrupt flag OCF1A after a synchronization delay follow-

ing the compare event.

94

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ATtiny25/45/85

12.3.5

OCR1B – Timer/Counter1 Output Compare RegisterB

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

0x2B

LSB

R/W

0

OCR1B

Read/Write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The output compare register B is an 8-bit read/write register.

The Timer/Counter Output Compare Register B contains data to be continuously compared with

Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does

only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and

OCR1B to the same value does not generate a compare match.

A compare match will set the compare interrupt flag OCF1B after a synchronization delay follow-

ing the compare event.

12.3.6

OCR1C – Timer/Counter1 Output Compare RegisterC

Bit

0x2D

7

6

5

4

3

2

1

0

MSB

LSB

R/W

1

OCR1C

Read/Write

Initial value

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

The output compare register C is an 8-bit read/write register.

The Timer/Counter Output Compare Register C contains data to be continuously compared with

Timer/Counter1. A compare match does only occur if Timer/Counter1 counts to the OCR1C

value. A software write that sets TCNT1 and OCR1C to the same value does not generate a

compare match. If the CTC1 bit in TCCR1 is set, a compare match will clear TCNT1.

This register has the same function in normal mode and PWM mode.

12.3.7

TIMSK – Timer/Counter Interrupt Mask Register

Bit

0x39

7

6

5

4

OCIE0A

R/W

0

3

OCIE0B

R/W

0

2

TOIE1

R/W

0

1

TOIE0

R/W

0

-

OCIE1A

OCIE1B

R/W

0

TIMSK

Read/Write

Initial value

R

0

R/W

0

R

0

• Bit 7 - Res: Reserved Bit

This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.

• Bit 6 - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector

$003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one)

in the Timer/Counter Interrupt Flag Register.

• Bit 5 - OCIE1B: Timer/Counter1 Output Compare Interrupt Enable

When the OCIE1B bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Compare MatchB, interrupt is enabled. The corresponding interrupt at vector

$009 is executed if a compare matchB occurs. The Compare Flag in Timer/Counter1 is set (one)

in the Timer/Counter Interrupt Flag Register.

95

2586K–AVR–01/08

• Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is

executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the

Timer/Counter Interrupt Flag Register - TIFR.

• Bit 0 - Res: Reserved Bit

This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.

12.3.8

TIFR – Timer/Counter Interrupt Flag Register

Bit

0x38

7

6

5

OCF1B

R/W

0

4

OCF0A

R/W

0

3

OCF0B

R/W

0

2

TOV1

R/W

0

1

TOV0

R/W

0

-

OCF1A

TIFR

Read/Write

Initial value

R

0

R/W

0

R

0

• Bit 7 - Res: Reserved Bit

This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.

• Bit 6 - OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A

are set (one), the Timer/Counter1 A compare match interrupt is executed.

• Bit 5 - OCF1B: Output Compare Flag 1B

The OCF1B bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1B - Output Compare Register 1A. OCF1B is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF1B is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1B, and OCF1B

are set (one), the Timer/Counter1 B compare match interrupt is executed.

• Bit 2 - TOV1: Timer/Counter1 Overflow Flag

In normal mode (PWM1A=0 and PWM1B=0) the bit TOV1 is set (one) when an overflow occurs

in Timer/Counter1. The bit TOV1 is cleared by hardware when executing the corresponding

interrupt handling vector. Alternatively, TOV1 is cleared, after synchronization clock cycle, by

writing a logical one to the flag.

In PWM mode (either PWM1A=1 or PWM1B=1) the bit TOV1 is set (one) when compare match

occurs between Timer/Counter1 and data value in OCR1C - Output Compare Register 1C.

When the SREG I-bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set

(one), the Timer/Counter1 Overflow interrupt is executed.

• Bit 0 - Res: Reserved Bit

This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.

96

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ATtiny25/45/85

12.3.9

PLLCSR – PLL Control and Status Register

Bit

7

6

-

5

-

4

-

3

-

2

PCKE

R/W

0

1

0

0x27

LSM

R/W

0

PLLE

R/W

0/1

PLOCK

PLLCSR

Read/Write

Initial value

R

0

R

0

R

0

R

0

R

0

• Bit 7 - LSM: Low Speed Mode

The high speed mode is enabled as default and the fast peripheral clock is 64 MHz, but the low

speed mode can be set by writing the LSM bit to one. Then the fast peripheral clock is scaled

down to 32 MHz. The low speed mode must be set, if the supply voltage is below 2.7 volts,

because the Timer/Counter1 is not running fast enough on low voltage levels. It is highly recom-

mended that Timer/Counter1 is stopped whenever the LSM bit is changed.

Note, that LSM can not be set if PLL_CLKis used as system clock.

• Bit 6:3- Res : Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and always read as zero.

• Bit 2- PCKE: PCK Enable

The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchronous clock

mode is enabled and fast 64 MHz (or 32 MHz in Low Speed Mode) PCK clock is used as

Timer/Counter1 clock source. If this bit is cleared, the synchronous clock mode is enabled, and

system clock CK is used as Timer/Counter1 clock source. This bit can be set only if PLLE bit is

set. It is safe to set this bit only when the PLL is locked i.e the PLOCK bit is 1. The bit PCKE can

only be set, if the PLL has been enabled earlier.

• Bit 1 - PLLE: PLL Enable

When the PLLE is set, the PLL is started and if needed internal RC-oscillator is started as a PLL

reference clock. If PLL is selected as a system clock source the value for this bit is always 1.

• Bit 0 - PLOCK: PLL Lock Detector

When the PLOCK bit is set, the PLL is locked to the reference clock. The PLOCK bit should be

ignored during initial PLL lock-in sequence when PLL frequency overshoots and undershoots,

before reaching steady state. The steady state is obtained within 100 µs. After PLL lock-in it is

recommended to check the PLOCK bit before enabling PCK for Timer/Counter1.

97

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13. 8-bit Timer/Counter1 in ATtiny15 Mode

The ATtiny15 compatibility mode is selected by writing the code “0011” to the CKSEL fuses (if

any other code is written, the Timer/Counter1 is working in normal mode). When selected the

ATtiny15 compatibility mode provides an ATtiny15 backward compatible prescaler and

Timer/Counter. Furthermore, the clocking system has same clock frequencies as in ATtiny15.

13.1 Timer/Counter1 Prescaler

Figure 13-1 shows an ATtiny15 compatible prescaler. It has two prescaler units, a 10-bit pres-

caler for the system clock (CK) and a 3-bit prescaler for the fast peripheral clock (PCK). The

clocking system of the Timer/Counter1 is always synchronous in the ATtiny15 compatibility

mode, because the same RC Oscillator is used as a PLL clock source (generates the input clock

for the prescaler) and the AVR core.

Figure 13-1. Timer/Counter1 Prescaler

PSR1

CK (1.6 MHz)

CLEAR

PCK (25.6 MHz)

10-BIT T/C PRESCALER

3-BIT T/C PRESCALER

0

CS10

CS11

CS12

CS13

TIMER/COUNTER1 COUNT ENABLE

The same clock selections as in ATtiny15 can be chosen for Timer/Counter1 from the output

multiplexer, because the frequency of the fast peripheral clock is 25.6 MHz and the prescaler is

similar in the ATtiny15 compatibility mode. The clock selections are PCK, PCK/2, PCK/4, PCK/8,

CK, CK/2, CK/4, CK/8, CK/16, CK/32, CK/64, CK/128, CK/256, CK/512, CK/1024 and stop.

13.2 Counter and Compare Units

Figure 13-2 shows Timer/Counter 1 synchronization register block diagram and synchronization

delays in between registers. Note that all clock gating details are not shown in the figure. The

Timer/Counter1 register values go through the internal synchronization registers, which cause

the input synchronization delay, before affecting the counter operation. The registers TCCR1,

GTCCR, OCR1A and OCR1C can be read back right after writing the register. The read back

values are delayed for the Timer/Counter1 (TCNT1) register and flags (OCF1A and TOV1),

because of the input and output synchronization.

The Timer/Counter1 features a high resolution and a high accuracy usage with the lower pres-

caling opportunities. It can also support an accurate, high speed, 8-bit Pulse Width Modulator

(PWM) using clock speeds up to 25.6 MHz. In this mode, Timer/Counter1 and the Output Com-

pare Registers serve as a stand-alone PWM. Refer to “Timer/Counter1 in PWM Mode” on page

98

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2586K–AVR–01/08

ATtiny25/45/85

101 for a detailed description on this function. Similarly, the high prescaling opportunities make

this unit useful for lower speed functions or exact timing functions with infrequent actions.

Figure 13-2. Timer/Counter 1 Synchronization Register Block Diagram.

8-BIT DATABUS

IO-registers

OCR1A

Input synchronization

registers

Timer/Counter1

Output synchronization

registers

OCR1A_SI

TCNT1

OCR1C

OCR1C_SI

TCNT_SO

TCCR1

GTCCR

TCCR1_SI

GTCCR_SI

TCNT1

TCNT1_SI

OCF1A

TOV1

OCF1A_SO

TOV1_SO

OCF1A

TOV1

OCF1A_SI

TOV1_SI

PCKE

CK

S

A

S

A

PCK

SYNC

MODE

1..2 PCK Delay

1 PCK Delay

1PCK Delay

~1 CK Delay

No Delay

ASYNC

MODE

~1 CK Delay

No Delay

Timer/Counter1 and the prescaler allow running the CPU from any clock source while the pres-

caler is operating on the fast 25.6 MHz PCK clock in the asynchronous mode.

The following Figure 13-3 shows the block diagram for Timer/Counter1.

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2586K–AVR–01/08

Figure 13-3. Timer/Counter1 Block Diagram

T/C1 OVER- T/C1 COMPARE

FLOW IRQ MATCH A IRQ

OC1A

(PB1)

TIMER INT. MASK

REGISTER (TIMSK)

TIMER INT. FLAG

REGISTER (TIFR)

T/C CONTROL

REGISTER 1 (TCCR1)

GLOBAL T/C CONTROL

REGISTER 2 (GTCCR)

TIMER/COUNTER1

(TCNT1)

T/C CLEAR

CK

T/C1 CONTROL

LOGIC

PCK

8-BIT COMPARATOR

T/C1 OUTPUT

COMPARE REGISTER

(OCR1C)

T/C1 OUTPUT

COMPARE REGISTER

(OCR1A)

8-BIT DATABUS

Two status flags (overflow and compare match) are found in the Timer/Counter Interrupt Flag

Register - TIFR. Control signals are found in the Timer/Counter Control Registers TCCR1 and

GTCCR. The interrupt enable/disable settings are found in the Timer/Counter Interrupt Mask

Register - TIMSK.

The Timer/Counter1 contains two Output Compare Registers, OCR1A and OCR1C as the data

source to be compared with the Timer/Counter1 contents. In normal mode the Output Compare

functions are operational with OCR1A only. OCR1A determines action on the OC1A pin (PB1),

and it can generate Timer1 OC1A interrupt in normal mode and in PWM mode. OCR1C holds

the Timer/Counter maximum value, i.e. the clear on compare match value. In the normal mode

an overflow interrupt (TOV1) is generated when Timer/Counter1 counts from $FF to $00, while

in the PWM mode the overflow interrupt is generated when the Timer/Counter1 counts either

from $FF to $00 or from OCR1C to $00.

In PWM mode, OCR1A provides the data values against which the Timer Counter value is com-

pared. Upon compare match the PWM outputs (OC1A) is generated. In PWM mode, the Timer

Counter counts up to the value specified in the output compare register OCR1C and starts again

from $00. This feature allows limiting the counter “full” value to a specified value, lower than $FF.

Together with the many prescaler options, flexible PWM frequency selection is provided. Table

12-3 on page 91 lists clock selection and OCR1C values to obtain PWM frequencies from 20

kHz to 250 kHz in 10 kHz steps and from 250 kHz to 500 kHz in 50 kHz steps. Higher PWM fre-

quencies can be obtained at the expense of resolution.

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ATtiny25/45/85

13.2.1

Timer/Counter1 in PWM Mode

When the PWM mode is selected, Timer/Counter1 and the Output Compare Register A -

OCR1A form an 8-bit, free-running and glitch-free PWM generator with output on the

PB1(OC1A).

When the counter value match the content of OCR1A, the OC1A and output is set or cleared

according to the COM1A1/COM1A0 bits in the Timer/Counter1 Control Register A - TCCR1, as

shown in Table 13-1.

Timer/Counter1 acts as an up-counter, counting from $00 up to the value specified in the output

compare register OCR1C, and starting from $00 up again. A compare match with OCR1C will

set an overflow interrupt flag (TOV1) after a synchronization delay following the compare event.

Table 13-1. Compare Mode Select in PWM Mode

COM1A1

COM1A0

Effect on Output Compare Pin

0

1

0

1

0

1

OC1A not connected.

OC1A cleared on compare match. Set when TCNT1 = $00.

OC1A set on compare match. Cleared when TCNT1 = $00.

Note that in PWM mode, writing to the Output Compare Register OCR1A, the data value is first

transferred to a temporary location. The value is latched into OCR1A when the Timer/Counter

reaches OCR1C. This prevents the occurrence of odd-length PWM pulses (glitches) in the event

of an unsynchronized OCR1A. See Figure 13-4 for an e xample.

Figure 13-4. Effects of Unsynchronized OCR Latching

Compare Value changes

Counter Value

Compare Value

PWM Output OC1A

Synchronized OC1A Latch

Compare Value changes

Counter Value

Compare Value

PWM Output OC1A

Glitch

Unsynchronized OC1A Latch

During the time between the write and the latch operation, a read from OCR1A will read the con-

tents of the temporary location. This means that the most recently written value always will read

out of OCR1A.

101

2586K–AVR–01/08

When OCR1A contains $00 or the top value, as specified in OCR1C register, the output

PB1(OC1A) is held low or high according to the settings of COM1A1/COM1A0. This is shown in

Table 13-2.

Table 13-2. PWM Outputs OCR1A = $00 or OCR1C

COM1A1

COM1A0

OCR1A

$00

Output OC1A

0

1

0

1

L

H

L

OCR1C

$00

OCR1C

$00

H

L

OCR1C

In PWM mode, the Timer Overflow Flag - TOV1 is set when the TCNT1 counts to the OCR1C

value and the TCNT1 is reset to $00. The Timer Overflow Interrupt1 is executed when TOV1 is

set provided that Timer Overflow Interrupt and global interrupts are enabled. This also applies to

the Timer Output Compare flags and interrupts.

The PWM frequency can be derived from the timer/counter clock frequency using the following

equation:

f

TCK1

f = -----------------------------------

(OCR1C + 1)

The duty cycle of the PWM waveform can be calculated using the following equation:

(OCR1A + 1) × T

– T

PCK

TCK1

D = ----------------------------------------------------------------------------

(OCR1C + 1) × T

TCK1

...where T_PCKis the period of the fast peripheral clock (1/25.6 MHz = 39.1 ns).

Resolution indicates how many bits are required to express the value in the OCR1C register. It

can be calculated using the following equation:

R = log2(OCR1C + 1)

Table 13-3. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode

PWM Frequency

20 kHz

Clock Selection

PCK/16

PCK/8

CS13..CS10

0101

OCR1C

199

RESOLUTION

7.6

7.1

7.6

7.3

7.1

7.8

30 kHz

0101

132

40 kHz

0100

199

50 kHz

PCK/8

0100

159

60 kHz

PCK/8

0100

132

70 kHz

PCK/4

0011

228

102

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

Table 13-3. Timer/Counter1 Clock Prescale Select in the Asynchronous Mode (Continued)

PWM Frequency

80 kHz

Clock Selection

PCK/4

PCK/2

PCK

CS13..CS10

0011

0010

0001

OCR1C

199

177

159

144

132

245

228

212

199

187

177

167

159

255

212

182

159

141

127

RESOLUTION

7.6

7.5

7.3

7.2

7.1

7.9

7.8

7.7

7.6

7.5

7.4

7.3

8.0

7.7

7.5

7.3

7.1

7.0

90 kHz

100 kHz

110 kHz

120 kHz

130 kHz

140 kHz

150 kHz

160 kHz

170 kHz

180 kHz

190 kHz

200 kHz

250 kHz

300 kHz

350 kHz

400 kHz

450 kHz

500 kHz

PCK

13.3 Register Description

13.3.1

TCCR1 – Timer/Counter1 Control Register

Bit

7

CTC1

R/W

0

6

PWM1A

R/W

0

5

COM1A1

R/W

4

3

2

1

CS11

R/W

0

0x30

COM1A0

CS13

R/W

0

CS12

R/W

0

CS10

R/W

0

TCCR1A

Read/Write

Initial value

R/W

0

• Bit 7- CTC1 : Clear Timer/Counter on Compare Match

When the CTC1 control bit is set (one), Timer/Counter1 is reset to $00 in the CPU clock cycle

after a compare match with OCR1A register. If the control bit is cleared, Timer/Counter1 contin-

ues counting and is unaffected by a compare match.

• Bit 6 - PWM1A: Pulse Width Modulator A Enable

When set (one) this bit enables PWM mode based on comparator OCR1A in Timer/Counter1

and the counter value is reset to $00 in the CPU clock cycle after a compare match with OCR1C

register value.

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2586K–AVR–01/08

• Bits 5,4 - COM1A1, COM1A0: Comparator A Output Mode, Bits 1 and 0

The COM1A1 and COM1A0 control bits determine any output pin action following a compare

match with compare register A in Timer/Counter1. Output pin actions affect pin PB1 (OC1A).

Since this is an alternative function to an I/O port, the corresponding direction control bit must be

set (one) in order to control an output pin.

Table 13-4. Comparator A Mode Select

COM1A1

COM1A0

Description

0

1

0

1

0

1

Timer/Counter Comparator A disconnected from output pin OC1A.

Toggle the OC1A output line.

Clear the OC1A output line.

Set the OC1A output line

In PWM mode, these bits have different functions. Refer to Table 13-1 on page 101 for a

detailed description.

• Bits 3:0 - CS13, CS12, CS11, CS10: Clock Select Bits 3, 2, 1, and 0

The Clock Select bits 3, 2, 1, and 0 define the prescaling source of Timer/Counter1.

Table 13-5. Timer/Counter1 Prescale Select

CS13

CS12

CS11

CS10

T/C1 Clock

T/C1 stopped

PCK

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

PCK/2

PCK/4

PCK/8

CK

CK/2

CK/4

CK/8

CK/16

CK/32

CK/64

CK/128

CK/256

CK/512

CK/1024

The Stop condition provides a Timer Enable/Disable function.

104

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

13.3.2

GTCCR – General Timer/Counter1 Control Register

Bit

7

6

PWM1B

R/W

0

5

COM1B1

R/W

4

COM1B0

R/W

3

FOC1B

W

2

FOC1A

W

1

PSR1

R/W

0

PSR0

R/W

0

0x2C

TSM

R/W

0

GTCCR

Read/Write

Initial value

0

• Bit 2- FOC1A: Force Output Compare Match 1A

Writing a logical one to this bit forces a change in the compare match output pin PB1 (OC1A)

according to the values already set in COM1A1 and COM1A0. If COM1A1 and COM1A0 written

in the same cycle as FOC1A, the new settings will be used. The Force Output Compare bit can

be used to change the output pin value regardless of the timer value. The automatic action pro-

grammed in COM1A1 and COM1A0 takes place as if a compare match had occurred, but no

interrupt is generated. The FOC1A bit always reads as zero. FOC1A is not in use if PWM1A bit

is set.

• Bit 1- PSR1 : Prescaler Reset Timer/Counter1

When this bit is set (one), the Timer/Counter prescaler (TCNT1 is unaffected) will be reset. The

bit will be cleared by hardware after the operation is performed. Writing a zero to this bit will have

no effect. This bit will always read as zero.

13.3.3

TCNT1 – Timer/Counter1

Bit

7

MSB

R/W

0

6

5

4

3

2

1

0

0x2F

LSB

R/W

0

TCNT1

Read/Write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

This 8-bit register contains the value of Timer/Counter1.

Timer/Counter1 is realized as an up counter with read and write access. Due to synchronization

of the CPU, Timer/Counter1 data written into Timer/Counter1 is delayed by one CPU clock cycle

in synchronous mode and at most two CPU clock cycles for asynchronous mode.

13.3.4

OCR1A – Timer/Counter1 Output Compare RegisterA

Bit

0x2E

7

6

5

4

3

2

1

0

MSB

LSB

R/W

0

OCR1A

Read/Write

Initial value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The output compare register A is an 8-bit read/write register.

The Timer/Counter Output Compare Register A contains data to be continuously compared with

Timer/Counter1. Actions on compare matches are specified in TCCR1. A compare match does

only occur if Timer/Counter1 counts to the OCR1A value. A software write that sets TCNT1 and

OCR1A to the same value does not generate a compare match.

A compare match will set the compare interrupt flag OCF1A after a synchronization delay follow-

ing the compare event.

105

2586K–AVR–01/08

13.3.5

OCR1C – Timer/Counter1 Output Compare Register C

Bit

7

MSB

R/W

1

6

5

4

3

2

1

0

0x2D

LSB

R/W

1

OCR1C

Read/Write

Initial value

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

R/W

1

The Output Compare Register B - OCR1B from ATtiny15 is replaced with the output compare

register C - OCR1C that is an 8-bit read/write register. This register has the same function as the

Output Compare Register B in ATtiny15.

The Timer/Counter Output Compare Register C contains data to be continuously compared with

Timer/Counter1. A compare match does only occur if Timer/Counter1 counts to the OCR1C

value. A software write that sets TCNT1 and OCR1C to the same value does not generate a

compare match. If the CTC1 bit in TCCR1 is set, a compare match will clear TCNT1.

13.3.6

TIMSK – Timer/Counter Interrupt Mask Register

Bit

0x39

7

6

5

4

OCIE0A

R/W

0

3

OCIE0B

R/W

0

2

TOIE1

R/W

0

1

TOIE0

R/W

0

-

OCIE1A

OCIE1B

R/W

0

TIMSK

Read/Write

Initial value

R

0

R/W

0

R

0

• Bit 7 - Res: Reserved Bit

This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.

• Bit 6 - OCIE1A: Timer/Counter1 Output Compare Interrupt Enable

When the OCIE1A bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Compare MatchA, interrupt is enabled. The corresponding interrupt at vector

$003 is executed if a compare matchA occurs. The Compare Flag in Timer/Counter1 is set (one)

in the Timer/Counter Interrupt Flag Register.

• Bit 2 - TOIE1: Timer/Counter1 Overflow Interrupt Enable

When the TOIE1 bit is set (one) and the I-bit in the Status Register is set (one), the

Timer/Counter1 Overflow interrupt is enabled. The corresponding interrupt (at vector $004) is

executed if an overflow in Timer/Counter1 occurs. The Overflow Flag (Timer1) is set (one) in the

Timer/Counter Interrupt Flag Register - TIFR.

• Bit 0 - Res: Reserved Bit

This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.

13.3.7

TIFR – Timer/Counter Interrupt Flag Register

Bit

0x38

7

6

5

OCF1B

R/W

0

4

OCF0A

R/W

0

3

OCF0B

R/W

0

2

TOV1

R/W

0

1

TOV0

R/W

0

-

OCF1A

TIFR

Read/Write

Initial value

R

0

R/W

0

R

0

• Bit 7 - Res: Reserved Bit

This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.

106

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

• Bit 6 - OCF1A: Output Compare Flag 1A

The OCF1A bit is set (one) when compare match occurs between Timer/Counter1 and the data

value in OCR1A - Output Compare Register 1A. OCF1A is cleared by hardware when executing

the corresponding interrupt handling vector. Alternatively, OCF1A is cleared, after synchroniza-

tion clock cycle, by writing a logic one to the flag. When the I-bit in SREG, OCIE1A, and OCF1A

are set (one), the Timer/Counter1 A compare match interrupt is executed.

• Bit 2 - TOV1: Timer/Counter1 Overflow Flag

The bit TOV1 is set (one) when an overflow occurs in Timer/Counter1. TOV1 is cleared by hard-

ware when executing the corresponding interrupt handling vector. Alternatively, TOV1 is

cleared, after synchronization clock cycle, by writing a logical one to the flag. When the SREG I-

bit, and TOIE1 (Timer/Counter1 Overflow Interrupt Enable), and TOV1 are set (one), the

Timer/Counter1 Overflow interrupt is executed.

• Bit 0 - Res: Reserved Bit

This bit is a reserved bit in the ATtiny25/45/85 and always reads as zero.

13.3.8

PLLCSR – PLL Control and Status Register

Bit

0x27

7

6

5

-

4

-

3

-

2

PCKE

R/W

0

1

0

LSM

-

PLLE

R/W

0/1

PLOCK

PLLCSR

Read/Write

Initial value

R/W

0

R

0

R

0

R

0

R

0

R

0

• Bit 6:3- Res : Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and always read as zero.

• Bit 2 - PCKE: PCK Enable

The bit PCKE is always set in the ATtiny15 compatibility mode.

• Bit 1 - PLLE: PLL Enable

The PLL is always enabled in the ATtiny15 compatibility mode.

• Bit 0 - PLOCK: PLL Lock Detector

When the PLOCK bit is set, the PLL is locked to the reference clock. The PLOCK bit should be

ignored during initial PLL lock-in sequence when PLL frequency overshoots and undershoots,

before reaching steady state. The steady state is obtained within 100 µs. After PLL lock-in it is

recommended to check the PLOCK bit before enabling PCK for Timer/Counter1.

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2586K–AVR–01/08

14. Dead Time Generator

The Dead Time Generator is provided for the Timer/Counter1 PWM output pairs to allow driving

external power control switches safely. The Dead Time Generator is a separate block that can

be connected to Timer/Counter1 and it is used to insert dead times (non-overlapping times) for

the Timer/Counter1 complementary output pairs (OC1A-OC1A and OC1B-OC1B). The sharing

of tasks is as follows: the timer/counter generates the PWM output and the Dead Time Genera-

tor generates the non-overlapping PWM output pair from the timer/counter PWM signal. Two

Dead Time Generators are provided, one for each PWM output. The non-overlap time is adjust-

able and the PWM output and it’s complementary output are adjusted separately, and

independently for both PWM outputs.

Figure 14-1. Timer/Counter1 & Dead Time Generators

PCKE

TIMER/COUNTER1

T15M

CK

PWM GENERATOR

PWM1A

PWM1B

PCK

DT1AH

DT1AL

DT1BH

DT1BL

DEAD TIME GENERATOR

OC1A

OC1B

OC1A

The dead time generation is based on the 4-bit down counters that count the dead time, as

shown in Figure 46. There is a dedicated prescaler in front of the Dead Time Generator that can

divide the Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8. This provides for large range of

dead times that can be generated. The prescaler is controlled by two control bits DTPS11..10

from the I/O register at address 0x23. The block has also a rising and falling edge detector that

is used to start the dead time counting period. Depending on the edge, one of the transitions on

the rising edges, OC1x or OC1x is delayed until the counter has counted to zero. The compara-

tor is used to compare the counter with zero and stop the dead time insertion when zero has

been reached. The counter is loaded with a 4-bit DT1xH or DT1xL value from DT1x I/O register,

depending on the edge of the PWM generator output when the dead time insertion is started.

Figure 14-2. Dead Time Generator

DTPS11..10

T/C1 CLOCK

COMPARATOR

4-BIT COUNTER

OC1x

DEAD TIME

PRESCALER

CLOCK CONTROL

DT1x

I/O REGISTER

PWM1x

108

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

The length of the counting period is user adjustable by selecting the dead time prescaler setting

in 0x23 register, and selecting then the dead time value in I/O register DT1x. The DT1x register

consists of two 4-bit fields, DT1xH and DT1xL that control the dead time periods of the PWM

output and its’ complementary output separately. Thus the rising edge of OC1x and OC1x can

have different dead time periods. The dead time is adjusted as the number of prescaled dead

time generator clock cycles.

Figure 14-3. The Complementary Output Pair

PWM1x

OC1x

x = A or B

t _{non-overlap / rising edge}t _{non-overlap / falling edge}

14.1 Register Description

14.1.1

DTPS1 – Timer/Counter1 Dead Time Prescaler Register 1

Bit

7

6

5

4

3

2

1

DTPS11

R/W

0

DTPS10

R/W

0

0x23

DTPS1

Read/Write

Initial value

R

0

R

0

R

0

R

0

R

0

R

0

The dead time prescaler register, DTPS1 is a 2-bit read/write register.

• Bits 1:0- DTPS11:DTPS10: Dead Time Prescaler

The dedicated Dead Time prescaler in front of the Dead Time Generator can divide the

Timer/Counter1 clock (PCK or CK) by 1, 2, 4 or 8 providing a large range of dead times that can

be generated. The Dead Time prescaler is controlled by two bits DTPS11..10 from the Dead

Time Prescaler register. These bits define the division factor of the Dead Time prescaler. The

division factors are given in table 46..

Table 14-1. Division factors of the Dead Time prescaler

DTPS11

DTPS10

Prescaler divides the T/C1 clock by

0

1

0

1

0

1

1x (no division)

2x

4x

8x

109

2586K–AVR–01/08

14.1.2

DT1A – Timer/Counter1 Dead Time A

Bit

7

DT1AH3

R/W

6

DT1AH2

R/W

5

DT1AH1

R/W

4

DT1AH0

R/W

3

DT1AL3

R/W

0

2

DT1AL2

R/W

0

1

DT1AL1

R/W

0

DT1AL0

R/W

0

0x25

DT1A

Read/Write

Initial value

0

The dead time value register A is an 8-bit read/write register.

The dead time delay of is adjusted by the dead time value register, DT1A. The register consists

of two fields, DT1AH3..0 and DT1AL3..0, one for each complementary output. Therefore a differ-

ent dead time delay can be adjusted for the rising edge of OC1A and the rising edge of OC1A.

• Bits 7:4- DT1AH3:DT1AH0: Dead Time Value for OC1A Output

The dead time value for the OC1A output. The dead time delay is set as a number of the pres-

caled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the

prescaled time/counter clock period multiplied by 15.

• Bits 3:0- DT1AL3:DT1AL0: Dead Time Value for OC1A Output

The dead time value for the OC1A output. The dead time delay is set as a number of the pres-

caled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the

prescaled time/counter clock period multiplied by 15.

14.1.3

DT1B – Timer/Counter1 Dead Time B

Bit

0x24

7

6

DT1BH2

R/W

5

DT1BH1

R/W

4

DT1BH0

R/W

3

DT1BL3

R/W

0

2

DT1BL2

R/W

0

1

DT1BL1

R/W

0

DT1BL0

R/W

0

DT1BH3

DT1B

Read/Write

Initial value

R/W

0

The dead time value register Bis an 8-bit read/write register.

The dead time delay of is adjusted by the dead time value register, DT1B. The register consists

of two fields, DT1BH3:0 and DT1BL3:0, one for each complementary output. Therefore a differ-

ent dead time delay can be adjusted for the rising edge of OC1A and the rising edge of OC1A.

• Bits 7:4- DT1BH3:DT1BH0: Dead Time Value for OC1B Output

The dead time value for the OC1B output. The dead time delay is set as a number of the pres-

caled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the

prescaled time/counter clock period multiplied by 15.

• Bits 3:0- DT1BL3:DT1BL0: Dead Time Value for OC1B Output

The dead time value for the OC1B output. The dead time delay is set as a number of the pres-

caled timer/counter clocks. The minimum dead time is zero and the maximum dead time is the

prescaled time/counter clock period multiplied by 15.

110

ATtiny25/45/85

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ATtiny25/45/85

15. USI – Universal Serial Interface

15.1 Features

• Two-wire Synchronous Data Transfer (Master or Slave)

• Three-wire Synchronous Data Transfer (Master or Slave)

• Data Received Interrupt

• Wakeup from Idle Mode

• Wake-up from All Sleep Modes In Two-wire Mode

• Two-wire Start Condition Detector with Interrupt Capability

15.2 Overview

The Universal Serial Interface (USI), provides the basic hardware resources needed for serial

communication. Combined with a minimum of control software, the USI allows significantly

higher transfer rates and uses less code space than solutions based on software only. Interrupts

are included to minimize the processor load.

A simplified block diagram of the USI is shown in Figure 15-1 For actual placement of I/O pins

refer to “Pinout ATtiny25/45/85” on page 2. Device-specific I/O Register and bit locations are

listed in the “Register Descriptions” on page 118.

Figure 15-1. Universal Serial Interface, Block Diagram

(Output only)

DO

D

Q

LE

(Input/Open Drain)

DI/SDA

3

2

USIDR

USIBR

1

0

TIM0 COMP

3

2

0

1

(Input/Open Drain)

USCK/SCL

4-bit Counter

1

0

CLOCK

HOLD

[1]

Two-wire

Clock

USISR

Control Unit

2

USICR

The 8-bit USI Data Register (USIDR) contains the incoming and outgoing data. It is directly

accessible via the data bus but a copy of the contents is also placed in the USI Buffer Register

(USIBR) where it can be retrieved later. If reading the USI Data Register directly, the register

must be read as quickly as possible to ensure that no data is lost.

The most significant bit of the USI Data Register is connected to one of two output pins (depend-

ing on the mode configuration, see “USICR – USI Control Register” on page 120). There is a

transparent latch between the output of the USI Data Register and the output pin, which delays

111

2586K–AVR–01/08

the change of data output to the opposite clock edge of the data input sampling. The serial input

is always sampled from the Data Input (DI) pin independent of the configuration.

The 4-bit counter can be both read and written via the data bus, and it can generate an overflow

interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same

clock source. This allows the counter to count the number of bits received or transmitted and

generate an interrupt when the transfer is complete. Note that when an external clock source is

selected the counter counts both clock edges. This means the counter registers the number of

clock edges and not the number of data bits. The clock can be selected from three different

sources: The USCK pin, Timer/Counter0 Compare Match or from software.

The two-wire clock control unit can be configured to generate an interrupt when a start condition

has been detected on the two-wire bus. It can also be set to generate wait states by holding the

clock pin low after a start condition is detected, or after the counter overflows.

15.3 Functional Descriptions

15.3.1

Three-wire Mode

The USI three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but

does not have the slave select (SS) pin functionality. However, this feature can be implemented

in software, if required. Pin names used in this mode are DI, DO, and USCK.

Figure 15-2. Three-wire Mode Operation, Simplified Diagram

DO

DI

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USCK

SLAVE

DO

DI

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

USCK

PORTxn

MASTER

Figure 15-2 shows two USI units operating in three-wire mode, one as Master and one as Slave.

The two USI Data Registers are interconnected in such way that after eight USCK clocks, the

data in each register has been interchanged. The same clock also increments the USI’s 4-bit

counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to determine

when a transfer is completed. The clock is generated by the Master device software by toggling

the USCK pin via the PORTB register or by writing a one to bit USITC bit in USICR.

112

ATtiny25/45/85

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ATtiny25/45/85

Figure 15-3. Three-Wire Mode, Timing Diagram

( Reference )

1

2

3

4

5

6

7

8

CYCLE

USCK

DO

MSB

6

5

4

3

2

1

LSB

6

5

4

3

2

1

DI

A

B

C

D

E

The three-wire mode timing is shown in Figure 15-3 At the top of the figure is a USCK cycle ref-

erence. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The

USCK timing is shown for both external clock modes. In external clock mode 0 (USICS0 = 0), DI

is sampled at positive edges, and DO is changed (USI Data Register is shifted by one) at nega-

tive edges. In external clock mode 1 (USICS0 = 1) the opposite edges with respect to mode 0

are used. In other words, data is sampled at negative and changes the output at positive edges.

The USI clock modes corresponds to the SPI data mode 0 and 1.

Referring to the timing diagram (Figure 15-3), a bus transfer involves the following steps:

1. The slave and master devices set up their data outputs and, depending on the protocol

used, enable their output drivers (mark A and B). The output is set up by writing the

data to be transmitted to the USI Data Register. The output is enabled by setting the

corresponding bit in the Data Direction Register of Port B. Note that there is not a pre-

ferred order of points A and B in the figure, but both must be at least one half USCK

cycle before point C, where the data is sampled. This is in order to ensure that the data

setup requirement is satisfied. The 4-bit counter is reset to zero.

2. The master software generates a clock pulse by toggling the USCK line twice (C and

D). The bit values on the data input (DI) pins are sampled by the USI on the first edge

(C), and the data output is changed on the opposite edge (D). The 4-bit counter will

count both edges.

3. Step 2. is repeated eight times for a complete register (byte) transfer.

4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate that

the transfer has been completed. If USI Buffer Registers are not used the data bytes

that have been transferred must now be processed before a new transfer can be initi-

ated. The overflow interrupt will wake up the processor if it is set to Idle mode.

Depending of the protocol used the slave device can now set its output to high

impedance.

15.3.2

SPI Master Operation Example

The following code demonstrates how to use the USI as an SPI Master:

SPITransfer:

out

ldi

out

ldi

USIDR,r16

r16,(1<<USIOIF)

USISR,r16

r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)

SPITransfer_loop:

out

in

USICR,r16

r16, USISR

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sbrs

rjmp

in

r16, USIOIF

SPITransfer_loop

r16,USIDR

ret

The code is size optimized using only eight instructions (plus return). The code example

assumes that the DO and USCK pins have been enabled as outputs in DDRB. The value stored

in register r16 prior to the function is called is transferred to the slave device, and when the

transfer is completed the data received from the slave is stored back into the register r16.

The second and third instructions clear the USI Counter Overflow Flag and the USI counter

value. The fourth and fifth instructions set three-wire mode, positive edge clock, count at USITC

strobe, and toggle USCK. The loop is repeated 16 times.

The following code demonstrates how to use the USI as an SPI master with maximum speed

(f_SCK= f_CK/2):

SPITransfer_Fast:

out

ldi

USIDR,r16

r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)

r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK)

out

USICR,r16 ; MSB

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16

USICR,r17

USICR,r16 ; LSB

USICR,r17

in

r16,USIDR

ret

15.3.3

SPI Slave Operation Example

The following code demonstrates how to use the USI as an SPI slave:

init:

ldi

out

r16,(1<<USIWM0)|(1<<USICS1)

USICR,r16

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...

SlaveSPITransfer:

out

ldi

USIDR,r16

r16,(1<<USIOIF)

out USISR,r16

SlaveSPITransfer_loop:

in

r16, USISR

sbrs

rjmp

in

r16, USIOIF

SlaveSPITransfer_loop

r16,USIDR

ret

The code is size optimized using only eight instructions (plus return). The code example

assumes that the DO and USCK pins have been enabled as outputs in DDRB. The value stored

in register r16 prior to the function is called is transferred to the master device, and when the

transfer is completed the data received from the master is stored back into the register r16.

Note that the first two instructions is for initialization, only, and need only be executed once.

These instructions set three-wire mode and positive edge clock. The loop is repeated until the

USI Counter Overflow Flag is set.

15.3.4

Two-wire Mode

The USI two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate lim-

iting on outputs and without input noise filtering. Pin names used in this mode are SCL and SDA.

Figure 15-4. Two-wire Mode Operation, Simplified Diagram

VCC

SDA

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SCL

HOLD

SCL

Two-wire Clock

Control Unit

SLAVE

SDA

SCL

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

PORTxn

MASTER

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Figure 15-4 shows two USI units operating in two-wire mode, one as master and one as slave. It

is only the physical layer that is shown since the system operation is highly dependent of the

communication scheme used. The main differences between the master and slave operation at

this level is the serial clock generation which is always done by the master. Only the slave uses

the clock control unit.

Clock generation must be implemented in software, but the shift operation is done automatically

in both devices. Note that clocking only on negative edges for shifting data is of practical use in

this mode. The slave can insert wait states at start or end of transfer by forcing the SCL clock

low. This means that the master must always check if the SCL line was actually released after it

has generated a positive edge.

Since the clock also increments the counter, a counter overflow can be used to indicate that the

transfer is completed. The clock is generated by the master by toggling the USCK pin via the

PORTB register.

The data direction is not given by the physical layer. A protocol, like the one used by the TWI-

bus, must be implemented to control the data flow.

Figure 15-5. Two-wire Mode, Typical Timing Diagram

SDA

1 - 7

8

9

1 - 8

9

1 - 8

9

SCL

S

P

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

A

B

C

D

E

F

Referring to the timing diagram (Figure 15-5), a bus transfer involves the following steps:

1. The start condition is generated by the master by forcing the SDA low line while keep-

ing the SCL line high (A). SDA can be forced low either by writing a zero to bit 7 of the

USI Data Register, or by setting the corresponding bit in the PORTB register to zero.

Note that the Data Direction Register bit must be set to one for the output to be

enabled. The start detector logic of the slave device (see Figure 15-6 on page 117)

detects the start condition and sets the USISIF Flag. The flag can generate an interrupt

if necessary.

2. In addition, the start detector will hold the SCL line low after the master has forced a

negative edge on this line (B). This allows the slave to wake up from sleep or complete

other tasks before setting up the USI Data Register to receive the address. This is done

by clearing the start condition flag and resetting the counter.

3. The master set the first bit to be transferred and releases the SCL line (C). The slave

samples the data and shifts it into the USI Data Register at the positive edge of the SCL

clock.

4. After eight bits containing slave address and data direction (read or write) have been

transferred, the slave counter overflows and the SCL line is forced low (D). If the slave

is not the one the master has addressed, it releases the SCL line and waits for a new

start condition.

5. When the slave is addressed, it holds the SDA line low during the acknowledgment

cycle before holding the SCL line low again (i.e., the USI Counter Register must be set

to 14 before releasing SCL at (D)). Depending on the R/W bit the master or slave

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enables its output. If the bit is set, a master read operation is in progress (i.e., the slave

drives the SDA line) The slave can hold the SCL line low after the acknowledge (E).

6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is

given by the master (F), or a new start condition is given.

If the slave is not able to receive more data it does not acknowledge the data byte it has last

received. When the master does a read operation it must terminate the operation by forcing the

acknowledge bit low after the last byte transmitted.

15.3.5

Start Condition Detector

The start condition detector is shown in Figure 15-6. The SDA line is delayed (in the range of 50

to 300 ns) to ensure valid sampling of the SCL line. The start condition detector is only enabled

in two-wire mode.

Figure 15-6. Start Condition Detector, Logic Diagram

USISIF

CLOCK

HOLD

D Q

SDA

CLR

SCL

Write( USISIF)

The start condition detector is working asynchronously and can therefore wake up the processor

from power-down sleep mode. However, the protocol used might have restrictions on the SCL

hold time. Therefore, when using this feature the oscillator start-up time (set by CKSEL fuses,

see “Clock Systems and their Distribution” on page 23) must also be taken into consideration.

Refer to the description of the USISIF bit on page 119 for further details.

15.3.6

Clock speed considerations

Maximum frequency for SCL and SCK is f_CK/ 2. This is also the maximum data transmit and

receive rate in both two- and three-wire mode. In two-wire slave mode the Two-wire Clock Con-

trol Unit will hold the SCL low until the slave is ready to receive more data. This may reduce the

actual data rate in two-wire mode.

15.4 Alternative USI Usage

The flexible design of the USI allows it to be used for other tasks when serial communication is

not needed. Below are some examples.

15.4.1

15.4.2

15.4.3

Half-Duplex Asynchronous Data Transfer

Using the USI Data Register in three-wire mode it is possible to implement a more compact and

higher performance UART than by software, only.

4-Bit Counter

The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the

counter is clocked externally, both clock edges will increment the counter value.

12-Bit Timer/Counter

Combining the 4-bit USI counter with one of the 8-bit timer/counters creates a 12-bit counter.

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15.4.4

15.4.5

Edge Triggered External Interrupt

By setting the counter to maximum value (F) it can function as an additional external interrupt.

The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This feature

is selected by the USICS1 bit.

Software Interrupt

The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.

15.5 Register Descriptions

15.5.1

USIDR – USI Data Register

Bit

7

6

5

4

3

2

1

0

0x0F

MSB

R/W

0

LSB

R/W

0

USIDR

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

The USI Data Register can be accessed directly but a copy of the data can also be found in the

USI Buffer Register.

Depending on the USICS1:0 bits of the USI Control Register a (left) shift operation may be per-

formed. The shift operation can be synchronised to an external clock edge, to a Timer/Counter0

Compare Match, or directly to software via the USICLK bit. If a serial clock occurs at the same

cycle the register is written, the register will contain the value written and no shift is performed.

Note that even when no wire mode is selected (USIWM1:0 = 0) both the external data input

(DI/SDA) and the external clock input (USCK/SCL) can still be used by the USI Data Register.

The output pin (DO or SDA, depending on the wire mode) is connected via the output latch to

the most significant bit (bit 7) of the USI Data Register. The output latch ensures that data input

is sampled and data output is changed on opposite clock edges. The latch is open (transparent)

during the first half of a serial clock cycle when an external clock source is selected (USICS1 =

1) and constantly open when an internal clock source is used (USICS1 = 0). The output will be

changed immediately when a new MSB is written as long as the latch is open.

Note that the Data Direction Register bit corresponding to the output pin must be set to one in

order to enable data output from the USI Data Register.

15.5.2

USIBR – USI Buffer Register

Bit

7

6

5

4

3

2

1

0

0x10

MSB

R

LSB

R

USIBR

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

Instead of reading data from the USI Data Register the USI Buffer Register can be used. This

makes controlling the USI less time critical and gives the CPU more time to handle other pro-

gram tasks. USI flags as set similarly as when reading the USIDR register.

The content of the USI Data Register is loaded to the USI Buffer Register when the transfer has

been completed.

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15.5.3

USISR – USI Status Register

Bit

7

6

5

4

3

2

1

0

0x0E

USISIF

R/W

0

USIOIF

R/W

0

USIPF

R/W

0

USIDC

USICNT3

USICNT2

USICNT1

USICNT0

USISR

Read/Write

Initial Value

R

0

R/W

0

R/W

0

R/W

0

R/W

0

The Status Register contains interrupt flags, line status flags and the counter value.

• Bit 7 – USISIF: Start Condition Interrupt Flag

When two-wire mode is selected, the USISIF Flag is set (to one) when a start condition has

been detected. When three-wire mode or output disable mode has been selected any edge on

the SCK pin will set the flag.

If USISIE bit in USICR and the Global Interrupt Enable Flag are set, an interrupt will be gener-

ated when this flag is set. The flag will only be cleared by writing a logical one to the USISIF bit.

Clearing this bit will release the start detection hold of USCL in two-wire mode.

A start condition interrupt will wakeup the processor from all sleep modes.

• Bit 6 – USIOIF: Counter Overflow Interrupt Flag

This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). If the

USIOIE bit in USICR and the Global Interrupt Enable Flag are set an interrupt will also be gener-

ated when the flag is set. The flag will only be cleared if a one is written to the USIOIF bit.

Clearing this bit will release the counter overflow hold of SCL in two-wire mode.

A counter overflow interrupt will wakeup the processor from Idle sleep mode.

• Bit 5 – USIPF: Stop Condition Flag

When two-wire mode is selected, the USIPF Flag is set (one) when a stop condition has been

detected. The flag is cleared by writing a one to this bit. Note that this is not an interrupt flag.

This signal is useful when implementing two-wire bus master arbitration.

• Bit 4 – USIDC: Data Output Collision

This bit is logical one when bit 7 in the USI Data Register differs from the physical pin value. The

flag is only valid when two-wire mode is used. This signal is useful when implementing Two-wire

bus master arbitration.

• Bits 3:0 – USICNT3:0: Counter Value

These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read or

written by the CPU.

The 4-bit counter increments by one for each clock generated either by the external clock edge

detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC strobe

bits. The clock source depends on the setting of the USICS1:0 bits.

For external clock operation a special feature is added that allows the clock to be generated by

writing to the USITC strobe bit. This feature is enabled by choosing an external clock source

(USICS1 = 1) and writing a one to the USICLK bit.

Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input

(USCK/SCL) can still be used by the counter.

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15.5.4

USICR – USI Control Register

Bit

7

6

5

4

3

2

1

0

0x0D

USISIE

R/W

0

USIOIE

R/W

0

USIWM1

USIWM0

USICS1

R/W

0

USICS0

R/W

0

USICLK

USITC

USICR

Read/Write

Initial Value

R/W

0

R/W

0

W

0

W

0

The USI Control Register includes bits for interrupt enable, setting the wire mode, selecting the

clock and clock strobe.

• Bit 7 – USISIE: Start Condition Interrupt Enable

Setting this bit to one enables the start condition detector interrupt. If there is a pending interrupt

and USISIE and the Global Interrupt Enable Flag are set to one the interrupt will be executed

immediately. Refer to the USISIF bit description on page 119 for further details.

• Bit 6 – USIOIE: Counter Overflow Interrupt Enable

Setting this bit to one enables the counter overflow interrupt. If there is a pending interrupt and

USIOIE and the Global Interrupt Enable Flag are set to one the interrupt will be executed imme-

diately. Refer to the USIOIF bit description on page 119 for further details.

• Bit 5:4 – USIWM1:0: Wire Mode

These bits set the type of wire mode to be used, as shown in Table 15-1 below.

Table 15-1. Relationship between USIWM1:0 and USI Operation

USIWM1

USIWM0

Description

Outputs, clock hold, and start detector disabled.

0

Port pins operates as normal.

Three-wire mode. Uses DO, DI, and USCK pins.

The Data Output (DO) pin overrides the corresponding bit in the PORTB register.

However, the corresponding DDRB bit still controls the data direction. When the port pin is

set as input the pin pull-up is controlled by the PORTB bit.

0

1

The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal port operation.

When operating as master, clock pulses are software generated by toggling the PORTB

register, while the data direction is set to output. The USITC bit in the USICR Register can

be used for this purpose.

Two-wire mode. Uses SDA (DI) and SCL (USCK) pins ⁽¹⁾

.

The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and use open-

collector output drives. The output drivers are enabled by setting the corresponding bit for

SDA and SCL in the DDRB register.

When the output driver is enabled for the SDA pin it will force the line SDA low if the output

of the USI Data Register or the corresponding bit in the PORTB register is zero.

Otherwise, the SDA line will not be driven (i.e., it is released). When the SCL pin output

driver is enabled the SCL line will be forced low if the corresponding bit in the PORTB

register is zero, or by the start detector. Otherwise the SCL line will not be driven.

1

0

The SCL line is held low when a start detector detects a start condition and the output is

enabled. Clearing the Start Condition Flag (USISIF) releases the line. The SDA and SCL

pin inputs is not affected by enabling this mode. Pull-ups on the SDA and SCL port pin are

disabled in Two-wire mode.

Two-wire mode. Uses SDA and SCL pins.

1

Same operation as in two-wire mode above, except that the SCL line is also held low

when a counter overflow occurs, and until the Counter Overflow Flag (USIOIF) is cleared.

Note:

1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively

to avoid confusion between the modes of operation.

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Basically only the function of the outputs are affected by these bits. Data and clock inputs are

not affected by the mode selected and will always have the same function. The counter and USI

Data Register can therefore be clocked externally and data input sampled, even when outputs

are disabled.

• Bit 3:2 – USICS1:0: Clock Source Select

These bits set the clock source for the USI Data Register and counter. The data output latch

ensures that the output is changed at the opposite edge of the sampling of the data input

(DI/SDA) when using external clock source (USCK/SCL). When software strobe or

Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and

therefore the output is changed immediately.

Clearing the USICS1:0 bits enables software strobe option. When using this option, writing a

one to the USICLK bit clocks both the USI Data Register and the counter. For external clock

source (USICS1 = 1), the USICLK bit is no longer used as a strobe, but selects between external

clocking and software clocking by the USITC strobe bit.

Table 15-2 shows the relationship between the USICS1:0 and USICLK setting and clock source

used for the USI Data Register and the 4-bit counter.

Table 15-2. Relationship between the USICS1:0 and USICLK Setting

USICS1 USICS0 USICLK Clock Source

4-bit Counter Clock Source

No Clock

0

1

0

1

0

1

0

1

0

1

X

0

1

No Clock

Software clock strobe (USICLK)

Timer/Counter0 Compare Match

External, positive edge

External, negative edge

External, positive edge

External, negative edge

Software clock strobe (USICLK)

Timer/Counter0 Compare Match

External, both edges

Software clock strobe (USITC)

• Bit 1 – USICLK: Clock Strobe

Writing a one to this bit location strobes the USI Data Register to shift one step and the counter

to increment by one, provided that the software clock strobe option has been selected by writing

USICS1:0 bits to zero. The output will change immediately when the clock strobe is executed,

i.e., during the same instruction cycle. The value shifted into the USI Data Register is sampled

the previous instruction cycle.

When an external clock source is selected (USICS1 = 1), the USICLK function is changed from

a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select the

USITC strobe bit as clock source for the 4-bit counter (see Table 15-2).

The bit will be read as zero.

• Bit 0 – USITC: Toggle Clock Port Pin

Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0.

The toggling is independent of the setting in the Data Direction Register, but if the PORT value is

to be shown on the pin the corresponding DDR pin must be set as output (to one). This feature

allows easy clock generation when implementing master devices.

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When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one, writ-

ing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detection of

when the transfer is done when operating as a master device.

The bit will read as zero.

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16. Analog Comparator

The Analog Comparator compares the input values on the positive pin AIN0 and negative pin

AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin

AIN1, the Analog Comparator output, ACO, is set. The comparator can trigger a separate inter-

rupt, exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator

output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown

in Figure 16-1.

Figure 16-1. Analog Comparator Block Diagram

INTERNAL 1.1V

REFERENCE

ACBG

ACME

ADEN

ADC MULTIPLEXER

OUTPUT⁽¹⁾

Notes: 1. See Table 16-1 below.

See Figure 1-1 on page 2 and Table 10-5 on page 65 for Analog Comparator pin placement.

16.1 Analog Comparator Multiplexed Input

When the Analog to Digital Converter (ADC) is configurated as single ended input channel, it is

possible to select any of the ADC3..0 pins to replace the negative input to the Analog Compara-

tor. The ADC multiplexer is used to select this input, and consequently, the ADC must be

switched off to utilize this feature. If the Analog Comparator Multiplexer Enable bit (ACME in

ADCSRB) is set and the ADC is switched off (ADEN in ADCSRA is zero), MUX1..0 in ADMUX

select the input pin to replace the negative input to the Analog Comparator, as shown in Table

16-1. If ACME is cleared or ADEN is set, AIN1 is applied to the negative input to the Analog

Comparator.

Table 16-1. Analog Comparator Multiplexed Input

ACME

ADEN

MUX1..0

Analog Comparator Negative Input

0

1

x

1

0

xx

00

01

10

11

AIN1

ADC0

ADC1

ADC2

ADC3

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16.2 Register Description

16.2.1

ADCSRB – ADC Control and Status Register B

Bit

7

6

5

4

–

R

0

3

–

R

0

2

1

0

0x03

BIN

R/W

0

ACME

R/W

0

IPR

R/W

0

ADTS2

R/W

0

ADTS1

R/W

0

ADTS0

R/W

0

ADCSRB

Read/Write

Initial Value

• Bit 6 – ACME: Analog Comparator Multiplexer Enable

When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the

ADC multiplexer selects the negative input to the Analog Comparator. When this bit is written

logic zero, AIN1 is applied to the negative input of the Analog Comparator. For a detailed

description of this bit, see “Analog Comparator Multiplexed Input” on page 123.

16.2.2

ACSR – Analog Comparator Control and Status Register

Bit

0x08

7

6

5

4

3

2

–

R

0

1

0

ACD

ACBG

ACO

ACI

ACIE

R/W

0

ACIS1

R/W

0

ACIS0

R/W

0

ACSR

Read/Write

Initial Value

R/W

0

R/W

0

R

R/W

0

N/A

• Bit 7 – ACD: Analog Comparator Disable

When this bit is written logic one, the power to the Analog Comparator is switched off. This bit

can be set at any time to turn off the Analog Comparator. This will reduce power consumption in

Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must be

disabled by clearing the ACIE bit in ACSR. Otherwise an interrupt can occur when the bit is

changed.

• Bit 6 – ACBG: Analog Comparator Bandgap Select

When this bit is set, a fixed bandgap reference voltage replaces the positive input to the Analog

Comparator. When this bit is cleared, AIN0 is applied to the positive input of the Analog Compar-

ator. When the bandgap reference is used as input to the Analog Comparator, it will take a

certain time for the voltage to stabilize. If not stabilized, the first conversion may give a wrong

value. See “Internal Voltage Reference” on page 44.

• Bit 5 – ACO: Analog Comparator Output

The output of the Analog Comparator is synchronized and then directly connected to ACO. The

synchronization introduces a delay of 1 - 2 clock cycles.

• Bit 4 – ACI: Analog Comparator Interrupt Flag

This bit is set by hardware when a comparator output event triggers the interrupt mode defined

by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is set

and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-

rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.

• Bit 3 – ACIE: Analog Comparator Interrupt Enable

When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog Com-

parator interrupt is activated. When written logic zero, the interrupt is disabled.

• Bit 2 – Res: Reserved Bit

This bit is a reserved bit in the ATtiny25/45/85 and will always read as zero.

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• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select

These bits determine which comparator events that trigger the Analog Comparator interrupt. The

different settings are shown in Table 16-2.

Table 16-2. ACIS1/ACIS0 Settings

ACIS1

ACIS0

Interrupt Mode

0

1

0

1

0

1

Comparator Interrupt on Output Toggle.

Reserved

Comparator Interrupt on Falling Output Edge.

Comparator Interrupt on Rising Output Edge.

When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by

clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when the

bits are changed.

16.2.3

DIDR0 – Digital Input Disable Register 0

Bit

0x14

7

6

5

4

3

2

1

0

–

ADC0D

R/W

0

ADC2D

R/W

0

ADC3D

R/W

0

ADC1D

R/W

0

AIN1D

R/W

0

AIN0D

R/W

0

DIDR0

Read/Write

Initial Value

R

0

R

0

• Bits 1, 0 – AIN1D, AIN0D: AIN1, AIN0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the AIN1/0 pin is disabled. The corre-

sponding PIN Register bit will always read as zero when this bit is set. When an analog signal is

applied to the AIN1/0 pin and the digital input from this pin is not needed, this bit should be writ-

ten logic one to reduce power consumption in the digital input buffer.

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17. Analog to Digital Converter

17.1 Features

• 10-bit Resolution

• 1 LSB Integral Non-linearity

• ± 2 LSB Absolute Accuracy

• 65 - 260 µs Conversion Time

• Up to 15 kSPS at Maximum Resolution

• Four Multiplexed Single Ended Input Channels

• Two differential input channels with selectable gain

• Temperature sensor input channel

• Optional Left Adjustment for ADC Result Readout

• 0 - V_CCADC Input Voltage Range

• Selectable 1.1V / 2.56V ADC Voltage Reference

• Free Running or Single Conversion Mode

• ADC Start Conversion by Auto Triggering on Interrupt Sources

• Interrupt on ADC Conversion Complete

• Sleep Mode Noise Cancele

• Unipolar / Bibilar Input Mode

• Input Polarity Reversal Mode

17.2 Overview

The ATtiny25/45/85 features a 10-bit successive approximation Analog to Digital Converter

(ADC). The ADC is connected to a 4-channel Analog Multiplexer which allows one differential

voltage input and four single-ended voltage inputs constructed from the pins of Port B. The dif-

ferential input (PB3, PB4 or PB2, PB5) is equipped with a programmable gain stage, providing

amplification step of 26 dB (20x) on the differential input voltage before the A/D conversion. The

single-ended voltage inputs refer to 0V (GND).

The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC is

held at a constant level during conversion. A block diagram of the ADC is shown in Figure 17-1

on page 127.

Internal voltage references of nominally 1.1V or 2.56V are provided On-chip. The Internal volt-

age reference of 2.56V can optionally be externally decoupled at the AREF (PB0) pin by a

capacitor, for better noise performance. Alternatively, V_CCcan be used as voltage reference for

single ended channels. There is also an option to use an external voltage reference and turn-off

the internal voltage reference. These options are selected using the REFS2..0 bits of the

ADMUX control register.

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Figure 17-1. Analog to Digital Converter Block Schematic

ADC CONVERSION

COMPLETE IRQ

INTERRUPT

FLAGS

ADTS[2:0]

8-BIT DATA BUS

15

0

ADC CTRL. & STATUS B

REGISTER (ADCSRB)

ADC CTRL. & STATUS A

REGISTER (ADCSRA)

ADC MULTIPLEXER

SELECT (ADMUX)

ADC DATA REGISTER

(ADCH/ADCL)

BIN

IPR

TRIGGER

SELECT

MUX DECODER

V

PRESCALER

CC

START

AREF

CONVERSION LOGIC

INTERNAL 1.1V/2.56V

REFERENCE

TEMPERATURE

SENSOR

SAMPLE & HOLD

COMPARATOR

10-BIT DAC

-

ADC4

+

ADC3

ADC2

ADC1

ADC0

SINGLE ENDED / DIFFERENTIAL SELECTION

INPUT

MUX

ADC MULTIPLEXER

OUTPUT

GAIN

AMPLIFIER

+

-

NEG.

INPUT

MUX

17.3 Operation

The ADC converts an analog input voltage to a 10-bit digital value through successive approxi-

mation. The minimum value represents GND and the maximum value represents the voltage on

V

_CC, the voltage on the AREF pin or an internal 1.1V / 2.56V voltage reference.

The voltage reference for the ADC may be selected by writing to the REFS2:0 bits in ADMUX.

The VCC supply, the AREF pin or an internal 1.1V / 2.56V voltage reference may be selected as

the ADC voltage reference. Optionally the internal 2.56V voltage reference may be decoupled

by an external capacitor at the AREF pin to improve noise immunity.

The analog input channel and differential gain are selected by writing to the MUX3..0 bits in

ADMUX. Any of the four ADC input pins ADC3..0 can be selected as single ended inputs to the

ADC. ADC2 or ADC0 can be selected as positive input and ADC0, ADC1, ADC2 or ADC3 can

be selected as negative input to the differential gain amplifier.

If differential channels are selected, the differential gain stage amplifies the voltage difference

between the selected input pair by the selected gain factor, 1x or 20x, according to the setting of

the MUX3:0 bits in ADMUX. This amplified value then becomes the analog input to the ADC. If

single ended channels are used, the gain amplifier is bypassed altogether.

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If ADC0 or ADC2 is selected as both the positive and negative input to the differential gain

amplifier (ADC0-ADC0 or ADC2-ADC2), the remaining offset in the gain stage and conversion

circuitry can be measured directly as the result of the conversion. This figure can be subtracted

from subsequent conversions with the same gain setting to reduce offset error to below 1 LSW.

The on-chip temperature sensor is selected by writing the code “1111” to the MUX3..0 bits in

ADMUX register when the ADC4 channel is used as an ADC input.

The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Voltage reference and

input channel selections will not go into effect until ADEN is set. The ADC does not consume

power when ADEN is cleared, so it is recommended to switch off the ADC before entering power

saving sleep modes.

The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and

ADCL. By default, the result is presented right adjusted, but can optionally be presented left

adjusted by setting the ADLAR bit in ADMUX.

If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data

registers belongs to the same conversion. Once ADCL is read, ADC access to data registers is

blocked. This means that if ADCL has been read, and a conversion completes before ADCH is

read, neither register is updated and the result from the conversion is lost. When ADCH is read,

ADC access to the ADCH and ADCL Registers is re-enabled.

The ADC has its own interrupt which can be triggered when a conversion completes. When ADC

access to the data registers is prohibited between reading of ADCH and ADCL, the interrupt will

trigger even if the result is lost.

17.4 Starting a Conversion

A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.

This bit stays high as long as the conversion is in progress and will be cleared by hardware

when the conversion is completed. If a different data channel is selected while a conversion is in

progress, the ADC will finish the current conversion before performing the channel change.

Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering is

enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA. The trigger source is

selected by setting the ADC Trigger Select bits, ADTS in ADCSRB (see description of the ADTS

bits for a list of the trigger sources). When a positive edge occurs on the selected trigger signal,

the ADC prescaler is reset and a conversion is started. This provides a method of starting con-

versions at fixed intervals. If the trigger signal still is set when the conversion completes, a new

conversion will not be started. If another positive edge occurs on the trigger signal during con-

version, the edge will be ignored. Note that an Interrupt Flag will be set even if the specific

interrupt is disabled or the Global Interrupt Enable bit in SREG is cleared. A conversion can thus

be triggered without causing an interrupt. However, the Interrupt Flag must be cleared in order to

trigger a new conversion at the next interrupt event.

Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon

as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-

stantly sampling and updating the ADC Data Register. The first conversion must be started by

writing a logical one to the ADSC bit in ADCSRA. In this mode the ADC will perform successive

conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.

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Figure 17-2. ADC Auto Trigger Logic

ADTS[2:0]

PRESCALER

CLK_ADC

START

ADIF

ADATE

SOURCE 1

.

CONVERSION

LOGIC

.

EDGE

DETECTOR

SOURCE n

ADSC

If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to

one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be

read as one during a conversion, independently of how the conversion was started.

17.5 Prescaling and Conversion Timing

Figure 17-3. ADC Prescaler

ADEN

START

Reset

7-BIT ADC PRESCALER

CK

ADPS0

ADPS1

ADPS2

ADC CLOCK SOURCE

By default, the successive approximation circuitry requires an input clock frequency between 50

kHz and 200 kHz to get maximum resolution. If a lower resolution than 10 bits is needed, the

input clock frequency to the ADC can be higher than 200 kHz to get a higher sample rate. It is

not recommended to use a higher input clock frequency than 1 MHz.

The ADC module contains a prescaler, which generates an acceptable ADC clock frequency

from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA.

The prescaler starts counting from the moment the ADC is switched on by setting the ADEN bit

in ADCSRA. The prescaler keeps running for as long as the ADEN bit is set, and is continuously

reset when ADEN is low.

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When initiating a single ended conversion by setting the ADSC bit in ADCSRA, the conversion

starts at the following rising edge of the ADC clock cycle.

A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is switched

on (ADEN in ADCSRA is set) takes 25 ADC clock cycles in order to initialize the analog circuitry,

as shown in Figure 17-4 below.

Figure 17-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)

Conversion

Cycle Number

1

2

12

13

14

15

16

17

18

19

20

21

22

23

24

25

1

2

3

ADC Clock

ADEN

ADSC

ADIF

Sign and MSB of Result

LSB of Result

ADCH

ADCL

MUX and REFS

Update

Conversion

Complete

MUX and REFS

Update

Sample & Hold

The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal conver-

sion and 13.5 ADC clock cycles after the start of an first conversion. When a conversion is

complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conversion

mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a new

conversion will be initiated on the first rising ADC clock edge.

Figure 17-5. ADC Timing Diagram, Single Conversion

One Conversion

Next Conversion

1

2

3

4

5

6

7

8

9

10

11

12

13

1

2

3

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

Sign and MSB of Result

LSB of Result

ADCL

Sample & Hold

Conversion

Complete

MUX and REFS

Update

MUX and REFS

Update

When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This assures

a fixed delay from the trigger event to the start of conversion. In this mode, the sample-and-hold

takes place two ADC clock cycles after the rising edge on the trigger source signal. Three addi-

tional CPU clock cycles are used for synchronization logic.

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Figure 17-6. ADC Timing Diagram, Auto Triggered Conversion

One Conversion

Next Conversion

1

2

3

4

5

6

7

8

9

10

11

12

13

1

2

Cycle Number

ADC Clock

Trigger

Source

ADATE

ADIF

ADCH

ADCL

Sign and MSB of Result

LSB of Result

Sample &

Hold

Prescaler

Reset

Conversion

Complete

Prescaler

Reset

MUX and REFS

Update

In Free Running mode, a new conversion will be started immediately after the conversion com-

pletes, while ADSC remains high.

Figure 17-7. ADC Timing Diagram, Free Running Conversion

One Conversion

Next Conversion

11

12

13

1

2

3

4

Cycle Number

ADC Clock

ADSC

ADIF

ADCH

ADCL

Sign and MSB of Result

LSB of Result

Sample & Hold

Conversion

Complete

MUX and REFS

Update

For a summary of conversion times, see Table 17-1.

Table 17-1. ADC Conversion Time

Sample & Hold

Total Conversion Time

Condition

(Cycles from Start of Conversion)

(Cycles)

First conversion

13.5

1.5

2

25

Normal conversions

Auto Triggered conversions

13

13.5

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17.6 Changing Channel or Reference Selection

The MUX3:0 and REFS2:0 bits in the ADMUX Register are single buffered through a temporary

register to which the CPU has random access. This ensures that the channels and voltage refer-

ence selection only takes place at a safe point during the conversion. The channel and voltage

reference selection is continuously updated until a conversion is started. Once the conversion

starts, the channel and voltage reference selection is locked to ensure a sufficient sampling time

for the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion

completes (ADIF in ADCSRA is set). Note that the conversion starts on the following rising ADC

clock edge after ADSC is written. The user is thus advised not to write new channel or voltage

reference selection values to ADMUX until one ADC clock cycle after ADSC is written.

If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special

care must be taken when updating the ADMUX Register, in order to control which conversion

will be affected by the new settings.

If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the

ADMUX Register is changed in this period, the user cannot tell if the next conversion is based

on the old or the new settings. ADMUX can be safely updated in the following ways:

a. When ADATE or ADEN is cleared.

b. During conversion, minimum one ADC clock cycle after the trigger event.

c. After a conversion, before the Interrupt Flag used as trigger source is cleared.

When updating ADMUX in one of these conditions, the new settings will affect the next ADC

conversion.

17.6.1

ADC Input Channels

When changing channel selections, the user should observe the following guidelines to ensure

that the correct channel is selected:

In Single Conversion mode, always select the channel before starting the conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wait for the conversion to complete before changing the channel selection.

In Free Running mode, always select the channel before starting the first conversion. The chan-

nel selection may be changed one ADC clock cycle after writing one to ADSC. However, the

simplest method is to wait for the first conversion to complete, and then change the channel

selection. Since the next conversion has already started automatically, the next result will reflect

the previous channel selection. Subsequent conversions will reflect the new channel selection.

17.6.2

ADC Voltage Reference

The voltage reference for the ADC (V_REF) indicates the conversion range for the ADC. Single

ended channels that exceed V_REFwill result in codes close to 0x3FF. V_REFcan be selected as

either V_CC, or internal 1.1V / 2.56V voltage reference, or external AREF pin. The first ADC con-

version result after switching voltage reference source may be inaccurate, and the user is

advised to discard this result.

17.7 ADC Noise Canceler

The ADC features a noise canceler that enables conversion during sleep mode to reduce noise

induced from the CPU core and other I/O peripherals. The noise canceler can be used with ADC

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ATtiny25/45/85

Noise Reduction and Idle mode. To make use of this feature, the following procedure should be

used:

• Make sure that the ADC is enabled and is not busy converting. Single Conversion mode must

be selected and the ADC conversion complete interrupt must be enabled.

• Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conversion once the

CPU has been halted.

• If no other interrupts occur before the ADC conversion completes, the ADC interrupt will wake

up the CPU and execute the ADC Conversion Complete interrupt routine. If another interrupt

wakes up the CPU before the ADC conversion is complete, that interrupt will be executed,

and an ADC Conversion Complete interrupt request will be generated when the ADC

conversion completes. The CPU will remain in active mode until a new sleep command is

executed.

Note that the ADC will not be automatically turned off when entering other sleep modes than Idle

mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before enter-

ing such sleep modes to avoid excessive power consumption.

17.8 Analog Input Circuitry

The analog input circuitry for single ended channels is illustrated in Figure 17-8. An analog

source applied to ADCn is subjected to the pin capacitance and input leakage of that pin, regard-

less of whether that channel is selected as input for the ADC. When the channel is selected, the

source must drive the S/H capacitor through the series resistance (combined resistance in the

input path).

Figure 17-8. Analog Input Circuitry

I_IH

ADCn

1..100 kΩ

C_S/H= 14 pF

I_IL

V_CC/2

The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or

less. If such a source is used, the sampling time will be negligible. If a source with higher imped-

ance is used, the sampling time will depend on how long time the source needs to charge the

S/H capacitor, with can vary widely. The user is recommended to only use low impedant sources

with slowly varying signals, since this minimizes the required charge transfer to the S/H

capacitor.

Signal components higher than the Nyquist frequency (f_ADC/2) should not be present to avoid

distortion from unpredictable signal convolution. The user is advised to remove high frequency

components with a low-pass filter before applying the signals as inputs to the ADC.

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17.9 Noise Canceling Techniques

Digital circuitry inside and outside the device generates EMI which might affect the accuracy of

analog measurements. If conversion accuracy is critical, the noise level can be reduced by

applying the following techniques:

• Keep analog signal paths as short as possible.

• Make sure analog tracks run over the analog ground plane.

• Keep analog tracks well away from high-speed switching digital tracks.

• If any port pin is used as a digital output, it mustn’t switch while a conversion is in progress.

• Place bypass capacitors as close to V_CCand GND pins as possible.

Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as

described in Section 17.7 on page 132. This is especially the case when system clock frequency

is above 1 MHz, or when the ADC is used for reading the internal temperature sensor, as

described in Section 17.12 on page 137. A good system design with properly placed, external

bypass capacitors does reduce the need for using ADC Noise Reduction Mode

17.10 ADC Accuracy Definitions

An n-bit single-ended ADC converts a voltage linearly between GND and V_REFin 2ⁿsteps

(LSBs). The lowest code is read as 0, and the highest code is read as 2ⁿ-1.

Several parameters describe the deviation from the ideal behavior, as follows:

• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition

(at 0.5 LSB). Ideal value: 0 LSB.

Figure 17-9. Offset Error

Output Code

Ideal ADC

Actual ADC

Offset

Error

V_REF

Input Voltage

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• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last

transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum).

Ideal value: 0 LSB

Figure 17-10. Gain Error

Gain

Error

Output Code

Ideal ADC

Actual ADC

V_REF

Input Voltage

• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum

deviation of an actual transition compared to an ideal transition for any code. Ideal value: 0

LSB.

Figure 17-11. Integral Non-linearity (INL)

Output Code

Ideal ADC

Actual ADC

V_REFInput Voltage

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• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval

between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB.

Figure 17-12. Differential Non-linearity (DNL)

Output Code

0x3FF

1 LSB

DNL

0x000

0

V_REFInput Voltage

• Quantization Error: Due to the quantization of the input voltage into a finite number of codes,

a range of input voltages (1 LSB wide) will code to the same value. Always ± 0.5 LSB.

• Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared to

an ideal transition for any code. This is the compound effect of offset, gain error, differential

error, non-linearity, and quantization error. Ideal value: ± 0.5 LSB.

17.11 ADC Conversion Result

After the conversion is complete (ADIF is high), the conversion result can be found in the ADC

Result Registers (ADCL, ADCH). The form of the conversion result depends on the type of the

conversio as there are three types of conversions: single ended conversion, unipolar differential

conversion and bipolar differential conversion.

17.11.1 Single Ended Conversion

For single ended conversion, the result is

V

⋅ 1024

IN

ADC = --------------------------

V

REF

where V_INis the voltage on the selected input pin and V_REFthe selected voltage reference (see

Table 17-3 on page 138 and Table 17-4 on page 139). 0x000 represents analog ground, and

0x3FF represents the selected voltage reference minus one LSB. The result is presented in one-

sided form, from 0x3FF to 0x000.

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17.11.2 Unipolar Differential Conversion

If differential channels and an unipolar input mode are used, the result is

(V

– V

) ⋅ 1024

NEG

POS

-------------------------------------------------------

ADC =

⋅ GAIN

V

REF

where V^POSis the voltage on the positive input pin, VNEG the voltage on the negative input pin,

and V^REFthe selected voltage reference (see Table 17-3 on page 138 and Table 17-4 on page

139). The voltage on the positive pin must always be larger than the voltage on the negative pin

or otherwise the voltage difference is saturated to zero. The result is presented in one-sided

form, from 0x000 (0d) to 0x3FF (+1023d). The GAIN is either 1x or 20x.

17.11.3 Bipolar Differential Conversion

As default the ADC converter operates in the unipolar input mode, but the bipolar input mode

can be selected by writting the BIN bit in the ADCSRB to one. In the bipolar input mode two-

sided voltage differences are allowed and thus the voltage on the negative input pin can also be

larger than the voltage on the positive input pin. If differential channels and a bipolar input mode

are used, the result is

(V

– V

) ⋅ 512

NEG

POS

----------------------------------------------------

ADC =

⋅ GAIN

V

REF

where V^POSis the voltage on the positive input pin, VNEG the voltage on the negative input pin,

and V^REFthe selected voltage reference. The result is presented in two’s complement form, from

0x200 (-512d) through 0x000 (+0d) to 0x1FF (+511d). The GAIN is either 1x or 20x.

However, if the signal is not bipolar by nature (9 bits + sign as the 10th bit), this scheme loses

one bit of the converter dynamic range. Then, if the user wants to perform the conversion with

the maximum dynamic range, the user can perform a quick polarity check of the result and use

the unipolar differential conversion with selectable differential input pairs (see the Input Polarity

Reversal mode ie. the IPR bit in the ADCSRB register on page 135). When the polarity check is

performed, it is sufficient to read the MSB of the result (ADC9 in ADCH). If the bit is one, the

result is negative, and if this bit is zero, the result is positive.

17.12 Temperature Measurement

The temperature measurement is based on an on-chip temperature sensor that is coupled to a

single ended ADC4 channel. Selecting the ADC4 channel by writing the MUX3..0 bits in ADMUX

register to “1111” enables the temperature sensor. The internal 1.1V reference must also be

selected for the ADC reference source in the temperature sensor measurement. When the tem-

perature sensor is enabled, the ADC converter can be used in single conversion mode to

measure the voltage over the temperature sensor.

The measured voltage has a linear relationship to the temperature as described in Table 17-2

The sensitivity is approximately 1 LSB / °C and the accuracy depends on the method of user cal-

ibration. Typically, the measurement accuracy after a single temperature calibration is ±10°C,

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assuming calibration at room temperature. Better accuracies are achieved by using two

temperature points for calibration.

Table 17-2. Temperature vs. Sensor Output Voltage (Typical Case)

Temperature

ADC

-40 °C

+25 °C

+85 °C

230 LSB

300 LSB

370 LSB

The values described in Table 17-2 are typical values. However, due to process variation the

temperature sensor output voltage varies from one chip to another. To be capable of achieving

more accurate results the temperature measurement can be calibrated in the application soft-

ware. The sofware calibration can be done using the formula:

T = k * [(ADCH << 8) | ADCL] + T_OS

where ADCH and ADCL are the ADC data registers, k is the fixed slope coefficient and T_OSis the

temperature sensor offset. Typically, k is very close to 1.0 and in single-point calibration the

coefficient may be omitted. Where higher accuracy is required the slope coefficient should be

evaluated based on measurements at two temperatures.

17.13 Register Description

17.13.1 ADMUX – ADC Multiplexer Selection Register

Bit

7

REFS1

R/W

0

6

REFS0

R/W

0

5

ADLAR

R/W

0

4

REFS2

R/W

0

3

MUX3

R/W

0

2

MUX2

R/W

0

1

MUX1

R/W

0

MUX0

R/W

0

0x07

ADMUX

Read/Write

Initial Value

• Bit 7:6,4 – REFS2:REFS0: Voltage Reference Selection Bits

These bits select the voltage reference (V_REF) for the ADC, as shown in Table 17-3. If these bits

are changed during a conversion, the change will not go in effect until this conversion is

complete (ADIF in ADCSR is set). Whenever these bits are changed, the next conversion will

take 25 ADC clock cycles. When differential channels and gain are used, using V_CCor an

external AREF higher than (V_CC- 1V) as a voltage reference is not recommended as this will

affect the ADC accuracy.

Table 17-3. Voltage Reference Selections for ADC

REFS2

REFS1

REFS0

Voltage Reference (V_REF) Selection

X

0

V_CCused as Voltage Reference, disconnected from PB0 (AREF).

External Voltage Reference at PB0 (AREF) pin, Internal Voltage

Reference turned off.

X

0

1

0

1

0

1

Internal 1.1V Voltage Reference.

Reserved

Internal 2.56V Voltage Reference without external bypass

capacitor, disconnected from PB0 (AREF)⁽¹⁾.

1

0

1

Internal 2.56V Voltage Reference with external bypass capacitor at

PB0 (AREF) pin⁽¹⁾.

Note:

1. The device requries a supply voltage of 3V in order to generate 2.56V reference voltage.

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•

Bit 5 – ADLAR: ADC Left Adjust Result

The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register.

Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. Changing the

ADLAR bit will affect the ADC Data Register immediately, regardless of any ongoing conver-

sions. For a comple te description of this bit, see “ADCL and ADCH – The ADC Data Register”

on page 141.

• Bits 3:0 – MUX3:0: Analog Channel and Gain Selection Bits

The value of these bits selects which combination of analog inputs are connected to the ADC. In

case of differential input (ADC0 - ADC1 or ADC2 - ADC3), gain selection is also made with these

bits. Selecting ADC2 or ADC0 as both inputs to the differential gain stage enables offset mea-

surements. Selecting the single-ended channel ADC4 enables the temperature sensor. Refer to

Table 17-4 for details. If these bits are changed during a conversion, the change will not go into

effect until this conversion is complete (ADIF in ADCSRA is set).

Table 17-4. Input Channel Selections

Single Ended

Input

Positive

Negative

MUX3..0

0000

0001

0010

0011

0100

0101 ⁽¹⁾

0110

0111

1000

1001

1010

1011

1100

1101

1110

1111

Differential Input Differential Input

Gain

ADC0 (PB5)

ADC1 (PB2)

ADC2 (PB4)

ADC3 (PB3)

N/A

ADC2 (PB4)

ADC0 (PB5)

ADC2 (PB4)

ADC3 (PB3)

ADC0 (PB5)

ADC1 (PB2)

1x

20x

1x

20x

1x

N/A

20x

1x

20x

V_BG

GND

N/A

ADC4 ⁽²⁾

1.

2.

For offset calibration, only. See “Operation” on page 127.

For temperature sensor.

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17.13.2 ADCSRA – ADC Control and Status Register A

Bit

7

6

5

4

3

2

1

0

0x06

ADEN

ADSC

ADATE

ADIF

ADIE

ADPS2

ADPS1

ADPS0

ADCSRA

Read/Write

Initial Value

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

R/W

0

• Bit 7 – ADEN: ADC Enable

Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the

ADC off while a conversion is in progress, will terminate this conversion.

• Bit 6 – ADSC: ADC Start Conversion

In Single Conversion mode, write this bit to one to start each conversion. In Free Running mode,

write this bit to one to start the first conversion. The first conversion after ADSC has been written

after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,

will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-

tion of the ADC.

ADSC will read as one as long as a conversion is in progress. When the conversion is complete,

it returns to zero. Writing zero to this bit has no effect.

• Bit 5 – ADATE: ADC Auto Trigger Enable

When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-

version on a positive edge of the selected trigger signal. The trigger source is selected by setting

the ADC Trigger Select bits, ADTS in ADCSRB.

• Bit 4 – ADIF: ADC Interrupt Flag

This bit is set when an ADC conversion completes and the data registers are updated. The ADC

Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set. ADIF is

cleared by hardware when executing the corresponding interrupt handling vector. Alternatively,

ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-Write on

ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI instructions

are used.

• Bit 3 – ADIE: ADC Interrupt Enable

When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-

rupt is activated.

• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits

These bits determine the division factor between the system clock frequency and the input clock

to the ADC.

Table 17-5. ADC Prescaler Selections

ADPS2

ADPS1

ADPS0

Division Factor

0

1

0

1

0

1

0

1

0

2

4

8

16

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Table 17-5. ADC Prescaler Selections (Continued)

ADPS2

ADPS1

ADPS0

Division Factor

1

0

1

0

1

32

64

128

17.13.3 ADCL and ADCH – The ADC Data Register

17.13.3.1 ADLAR = 0

Bit

15

14

13

12

11

10

9

8

0x05

0x04

–

ADC9

ADC8

ADCH

ADCL

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADC1

ADC0

7

R

0

6

R

0

5

R

0

4

R

0

3

R

0

2

R

0

1

R

0

R

0

Read/Write

Initial Value

0

17.13.3.2

ADLAR = 1

Bit

15

14

13

12

11

10

9

8

0x05

0x04

ADC9

ADC8

ADC7

ADC6

ADC5

ADC4

ADC3

ADC2

ADCH

ADCL

ADC1

ADC0

–

5

–

4

–

3

–

2

–

1

–

0

7

R

0

6

R

0

Read/Write

Initial Value

R

0

R

0

R

0

R

0

R

0

R

0

When an ADC conversion is complete, the result is found in these two registers.

When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently, if

the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read

ADCH. Otherwise, ADCL must be read first, then ADCH.

The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from

the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the result

is right adjusted.

• Bits 9:0 - ADC9:0: ADC Conversion Result

These bits represent the result from the conversion, as detailed in “ADC Conversion Result” on

page 136.

17.13.4 ADCSRB – ADC Control and Status Register B

Bit

7

BIN

R/W

0

6

ACME

R/W

0

5

IPR

R/W

0

4

–

3

–

2

ADTS2

R/W

0

1

ADTS1

R/W

0

ADTS0

R/W

0

0x03

ADCSRB

Read/Write

Initial Value

R

0

R

0

• Bit 7 – BIN: Bipolar Input Mode

The gain stage is working in the unipolar mode as default, but the bipolar mode can be selected

by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided conversions

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are supported and the voltage on the positive input must always be larger than the voltage on

the negative input. Otherwise the result is saturated to the voltage reference. In the bipolar mode

two-sided conversions are supported and the result is represented in the two’s complement

form. In the unipolar mode the resolution is 10 bits and the bipolar mode the resolution is 9 bits +

1 sign bit.

• Bit 5 – IPR: Input Polarity Reversal

The Input Polarity mode allows software selectable differential input pairs and full 10 bit ADC

resolution, in the unipolar input mode, assuming a pre-determined input polarity. If the input

polarity is not known it is actually possible to determine the polarity first by using the bipolar input

mode (with 9 bit resolution + 1 sign bit ADC measurement). And once determined, set or clear

the polarity reversal bit, as needed, for a succeeding 10 bit unipolar measurement.

• Bits 4:3 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and will always read as zero.

• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source

If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger

an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect. A conversion

will be triggered by the rising edge of the selected Interrupt Flag. Note that switching from a trig-

ger source that is cleared to a trigger source that is set, will generate a positive edge on the

trigger signal. If ADEN in ADCSRA is set, this will start a conversion. Switching to Free Running

mode (ADTS[2:0]=0) will not cause a trigger event, even if the ADC Interrupt Flag is set.

Table 17-6. ADC Auto Trigger Source Selections

ADTS2

ADTS1

ADTS0

Trigger Source

0

1

0

1

0

1

0

1

0

1

0

1

0

Free Running mode

Analog Comparator

External Interrupt Request 0

Timer/Counter0 Compare Match A

Timer/Counter0 Overflow

Timer/Counter0 Compare Match B

Pin Change Interrupt Request

17.13.5 DIDR0 – Digital Input Disable Register 0

Bit

7

–

R

0

6

–

R

0

5

4

3

2

1

0

0x14

ADC0D

R/W

0

ADC2D

R/W

0

ADC3D

R/W

0

ADC1D

R/W

0

AIN1D

R/W

0

AIN0D

R/W

0

DIDR0

Read/Write

Initial Value

• Bits 5:2 – ADC3D:ADC0D: ADC3:0 Digital Input Disable

When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-

abled. The corresponding PIN register bit will always read as zero when this bit is set. When an

analog signal is applied to the ADC3:0 pin and the digital input from this pin is not needed, this

bit should be written logic one to reduce power consumption in the digital input buffer.

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18. debugWIRE On-chip Debug System

18.1 Features

• Complete Program Flow Control

• Emulates All On-chip Functions, Both Digital and Analog , except RESET Pin

• Real-time Operation

• Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)

• Unlimited Number of Program Break Points (Using Software Break Points)

• Non-intrusive Operation

• Electrical Characteristics Identical to Real Device

• Automatic Configuration System

• High-Speed Operation

• Programming of Non-volatile Memories

18.2 Overview

The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the

program flow, execute AVR instructions in the CPU and to program the different non-volatile

memories.

18.3 Physical Interface

When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unprogrammed,

the debugWIRE system within the target device is activated. The RESET port pin is configured

as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes the commu-

nication gateway between target and emulator.

Figure 18-1 shows the schematic of a target MCU, with debugWIRE enabled, and the emulator

connector. The system clock is not affected by debugWIRE and will always be the clock source

selected by the CKSEL Fuses.

Figure 18-1. The debugWIRE Setup

1.8 - 5.5V

VCC

dW

dW(RESET)

GND

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When designing a system where debugWIRE will be used, the following observations must be

made for correct operation:

• Pull-Up resistor on the dW/(RESET) line must be in the range of 10k to 20 kΩ. However, the

pull-up resistor is optional.

• Connecting the RESET pin directly to V_CCwill not work.

• Capacitors inserted on the RESET pin must be disconnected when using debugWire.

• All external reset sources must be disconnected.

18.4 Software Break Points

debugWIRE supports Program memory Break Points by the AVR Break instruction. Setting a

Break Point in AVR Studio^®will insert a BREAK instruction in the Program memory. The instruc-

tion replaced by the BREAK instruction will be stored. When program execution is continued, the

stored instruction will be executed before continuing from the Program memory. A break can be

inserted manually by putting the BREAK instruction in the program.

The Flash must be re-programmed each time a Break Point is changed. This is automatically

handled by AVR Studio through the debugWIRE interface. The use of Break Points will therefore

reduce the Falsh Data retention. Devices used for debugging purposes should not be shipped to

end customers.

18.5 Limitations of debugWIRE

The debugWIRE communication pin (dW) is physically located on the same pin as External

Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is

enabled.

The debugWIRE system accurately emulates all I/O functions when running at full speed, i.e.,

when the program in the CPU is running. When the CPU is stopped, care must be taken while

accessing some of the I/O Registers via the debugger (AVR Studio).

A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep

modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse should

be disabled when debugWire is not used.

In Asynchronous Mode and in ATtiny15 Compatibility Mode, Timer/Counter1 is running freely

and cannot be single-stepped by the debugger.

18.6 Register Description

The following section describes the registers used with the debugWire.

18.6.1

DWDR – debugWire Data Register

Bit

0x22

7

6

5

4

3

2

1

0

DWDR7

DWDR6

R/W

0

DWDR5

R/W

0

DWDR4

R/W

0

DWDR3

R/W

0

DWDR2

R/W

0

DWDR1

R/W

0

DWDR0

R/W

0

DWDR

Read/Write

Initial Value

R/W

0

The DWDR Register provides a communication channel from the running program in the MCU

to the debugger. This register is only accessible by the debugWIRE and can therefore not be

used as a general purpose register in the normal operations.

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19. Self-Programming the Flash

The device provides a Self-Programming mechanism for downloading and uploading program

code by the MCU itself. The Self-Programming can use any available data interface and associ-

ated protocol to read code and write (program) that code into the Program memory. The SPM

instruction is disabled by default but it can be enabled by programming the SELFPRGEN fuse

(to “0”).

The Program memory is updated in a page by page fashion. Before programming a page with

the data stored in the temporary page buffer, the page must be erased. The temporary page

buffer is filled one word at a time using SPM and the buffer can be filled either before the Page

Erase command or between a Page Erase and a Page Write operation:

Alternative 1, fill the buffer before a Page Erase

• Fill temporary page buffer

• Perform a Page Erase

• Perform a Page Write

Alternative 2, fill the buffer after Page Erase

• Perform a Page Erase

• Fill temporary page buffer

• Perform a Page Write

If only a part of the page needs to be changed, the rest of the page must be stored (for example

in the temporary page buffer) before the erase, and then be re-written. When using alternative 1,

the Boot Loader provides an effective Read-Modify-Write feature which allows the user software

to first read the page, do the necessary changes, and then write back the modified data. If alter-

native 2 is used, it is not possible to read the old data while loading since the page is already

erased. The temporary page buffer can be accessed in a random sequence. It is essential that

the page address used in both the Page Erase and Page Write operation is addressing the same

page.

19.1 Performing Page Erase by SPM

To execute Page Erase, set up the address in the Z-pointer, write “00000011” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE in the Z-register. Other bits in the Z-pointer will

be ignored during this operation.

Note:

The CPU is halted during the Page Erase operation.

19.2 Filling the Temporary Buffer (Page Loading)

To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write

“00000001” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The

content of PCWORD in the Z-register is used to address the data in the temporary buffer. The

temporary buffer will auto-erase after a Page Write operation or by writing the CTPB bit in

SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than

one time to each address without erasing the temporary buffer.

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If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be

lost.

19.3 Performing a Page Write

To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and

execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored.

The page address must be written to PCPAGE. Other bits in the Z-pointer must be written to

zero during this operation.

Note:

The CPU is halted during the Page Write operation.

19.4 Addressing the Flash During Self-Programming

The Z-pointer is used to address the SPM commands.

Bit

15

Z15

Z7

7

14

Z14

Z6

6

13

Z13

Z5

5

12

Z12

Z4

4

11

Z11

Z3

3

10

Z10

Z2

2

9

8

ZH (R31)

ZL (R30)

Z9

Z1

1

Z8

Z0

0

Since the Flash is organized in pages (see Table 20-8 on page 154), the Program Counter can

be treated as having two different sections. One section, consisting of the least significant bits, is

addressing the words within a page, while the most significant bits are addressing the pages.

This is shown in Figure 19-1. Note that the Page Erase and Page Write operations are

addressed independently. Therefore it is of major importance that the software addresses the

same page in both the Page Erase and Page Write operation.

The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses the

Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.

Figure 19-1. Addressing the Flash During SPM⁽¹⁾

BIT 15

ZPCMSB

ZPAGEMSB

1

0

Z - REGISTER

PCMSB

PAGEMSB

PROGRAM

COUNTER

PCPAGE

PCWORD

PAGE ADDRESS

WORD ADDRESS

WITHIN THE FLASH

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

Note:

1. The different variables used in Figure 19-1 are listed in Table 20-8 on page 154.

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19.5 EEPROM Write Prevents Writing to SPMCSR

Note that an EEPROM write operation will block all software programming to Flash. Reading the

Fuses and Lock bits from software will also be prevented during the EEPROM write operation. It

is recommended that the user checks the status bit (EEPE) in the EECR Register and verifies

that the bit is cleared before writing to the SPMCSR Register.

19.6 Reading Lock, Fuse and Signature Data from Software

It is possible to read fuse and lock bits from firmware. In addition, firmware can also read data

from the device signature imprint table (see page 153).

Note:

Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are unpro-

grammed, will be read as one.

19.6.1

Reading Lock Bits from Firmware

Issuing an LPM instruction within three CPU cycles after RFLB and SELFPRGEN bits have

been set in SPMCSR will return lock bit values in the destination register. The RFLB and SELF-

PRGEN bits automatically clear upon completion of reading the lock bits, or if no LPM instruction

is executed within three CPU cycles, or if no SPM instruction is executed within four CPU cycles.

When RFLB and SELFPRGEN are cleared LPM functions normally.

To read the lock bits, follow the below procedure:

1. Load the Z-pointer with 0x0001.

2. Set RFLB and SELFPRGEN bits in SPMCSR.

3. Issue an LPM instruction within three clock cycles.

4. Read the lock bits from the LPM destination register.

If successful, the contents of the destination register are as follows.

Bit

Rd

7

–

6

–

5

–

4

–

3

–

2

–

1

0

LB2

LB1

See section “Program And Data Memory Lock Bits” on page 151 for more information.

Reading Fuse Bits from Firmware

19.6.2

The algorithm for reading fuse bytes is similar to the one described above for reading lock bits,

only the addresses are different. To read the Fuse Low Byte (FLB), follow the below procedure:

1. Load the Z-pointer with 0x0000.

2. Set RFLB and SELFPRGEN bits in SPMCSR.

3. Issue an LPM instruction within three clock cycles.

4. Read the FLB from the LPM destination register.

If successful, the contents of the destination register are as follows.

Bit

Rd

7

6

5

4

3

2

1

0

FLB7

FLB6

FLB5

FLB4

FLB3

FLB2

FLB1

FLB0

Refer to Table 20-5 on page 153 for a detailed description and mapping of the Fuse Low Byte.

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2586K–AVR–01/08

To read the Fuse High Byte (FHB), simply replace the address in the Z-pointer with 0x0003 and

repeat the procedure above. If successful, the contents of the destination register are as follows.

Bit

Rd

7

6

5

4

3

2

1

0

FHB7

FHB6

FHB5

FHB4

FHB3

FHB2

FHB1

FHB0

Refer to Table 20-4 on page 152 for detailed description and mapping of the Fuse High Byte.

To read the Fuse Extended Byte (FEB), replace the address in the Z-pointer with 0x0002 and

repeat the previous procedure. If successful, the contents of the destination register are as

follows.

Bit

Rd

7

6

5

4

3

2

1

0

FEB7

FEB6

FEB5

FEB4

FEB3

FEB2

FEB1

FEB0

Refer to Table 20-3 on page 152 for detailed description and mapping of the Fuse Extended

Byte.

19.6.3

Reading Device Signature Imprint Table from Firmware

To read the contents of the device signature imprint table, follow the below procedure:

1. Load the Z-pointer with the table index.

2. Set RSIG and SPMEN bits in SPMCSR.

3. Issue an LPM instruction within three clock cycles.

4. Read table data from the LPM destination register.

See program example below.

Assembly Code Example⁽¹⁾

DSIT_read:

; Uses Z-pointer as table index

ldi ZH, 0

ldi ZL, 1

; Preload SPMCSR bits into R16, then write to SPMCSR

ldi r16, (1<<RSIG)|(1<<SPMEN)

out SPMCSR, r16

; Issue LPM. Table data will be returned into r17

lpm r17, Z

ret

Note:

1. See “Code Examples” on page 6.

If successful, the contents of the destination register are as described in section “Device Signa-

ture Imprint Table” on page 153.

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19.7 Preventing Flash Corruption

During periods of low V_CC, the Flash program can be corrupted because the supply voltage is

too low for the CPU and the Flash to operate properly. These issues are the same as for board

level systems using the Flash, and the same design solutions should be applied.

A Flash program corruption can be caused by two situations when the voltage is too low. First, a

regular write sequence to the Flash requires a minimum voltage to operate correctly. Secondly,

the CPU itself can execute instructions incorrectly, if the supply voltage for executing instructions

is too low.

Flash corruption can easily be avoided by following these design recommendations (one is

sufficient):

1. Keep the AVR RESET active (low) during periods of insufficient power supply voltage.

This can be done by enabling the internal Brown-out Detector (BOD) if the operating

voltage matches the detection level. If not, an external low V_CCreset protection circuit

can be used. If a reset occurs while a write operation is in progress, the write operation

will be completed provided that the power supply voltage is sufficient.

2. Keep the AVR core in Power-down sleep mode during periods of low V_CC. This will pre-

vent the CPU from attempting to decode and execute instructions, effectively protecting

the SPMCSR Register and thus the Flash from unintentional writes.

19.8 Programming Time for Flash when Using SPM

The calibrated RC Oscillator is used to time Flash accesses. Table 19-1 shows the typical pro-

gramming time for Flash accesses from the CPU.

Table 19-1. SPM Programming Time⁽¹⁾

Symbol

Min Programming Time

Max Programming Time

Flash write (Page Erase, Page Write, and

write Lock bits by SPM)

3.7 ms

4.5 ms

Note:

1. Minimum and maximum programming time is per individual operation.

19.9 Register Description

19.9.1

SPMCSR – Store Program Memory Control and Status Register

The Store Program Memory Control and Status Register contains the control bits needed to con-

trol the Program memory operations.

Bit

7

–

R

0

6

–

R

0

5

4

3

2

1

0

0x37

RSIG

R/W

0

CTPB

R/W

0

RFLB

R/W

0

PGWRT

R/W

0

PGERS

R/W

0

SPMEN

R/W

0

SPMCSR

Read/Write

Initial Value

• Bits 7:6 – Res: Reserved Bits

These bits are reserved bits in the ATtiny25/45/85 and always read as zero.

• Bit 5 – RSIG: Read Device Signature Imprint Table

Issuing an LPM instruction within three cycles after RSIG and SPMEN bits have been set in

SPMCSR will return the selected data (depending on Z-pointer value) from the device signature

imprint table into the destination register. See “Device Signature Imprint Table” on page 153 for

details.

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• Bit 4 – CTPB: Clear Temporary Page Buffer

If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will be

cleared and the data will be lost.

• Bit 3 – RFLB: Read Fuse and Lock Bits

An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Register,

will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the destina-

tion register. See “EEPROM Write Prevents Writing to SPMCSR” on page 147 for details.

• Bit 2 – PGWRT: Page Write

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Write, with the data stored in the temporary buffer. The page address is

taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The PGWRT bit

will auto-clear upon completion of a Page Write, or if no SPM instruction is executed within four

clock cycles. The CPU is halted during the entire Page Write operation.

• Bit 1 – PGERS: Page Erase

If this bit is written to one at the same time as SPMEN, the next SPM instruction within four clock

cycles executes Page Erase. The page address is taken from the high part of the Z-pointer. The

data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion of a Page Erase,

or if no SPM instruction is executed within four clock cycles. The CPU is halted during the entire

Page Write operation.

• Bit 0 – SPMEN: Store Program Memory Enable

This bit enables the SPM instruction for the next four clock cycles. If set to one together with

RSIG, CTPB, RFLB, PGWRT or PGERS, the following LPM/SPM instruction will have a special

meaning, as described elsewhere.

If only SPMEN is written, the following SPM instruction will store the value in R1:R0 in the tem-

porary page buffer addressed by the Z-pointer. The LSB of the Z-pointer is ignored. The SPMEN

bit will auto-clear upon completion of an SPM instruction, or if no SPM instruction is executed

within four clock cycles. During Page Erase and Page Write, the SPMEN bit remains high until

the operation is completed.

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20. Memory Programming

This section describes the different methods for Programming the ATtiny25/45/85 memories.

20.1 Program And Data Memory Lock Bits

ATtiny25/45/85 provides two Lock bits which can be left unprogrammed (“1”) or can be pro-

grammed (“0”) to obtain the additional security listed in Table 20-2. Lock bits can be erased to

“1” with the Chip Erase command, only.

Program memory can be read out via the debugWIRE interface when the DWEN fuse is pro-

grammed, even if the Lock Bits are set. Thus, when Lock Bit security is required debugWIRE

should always be disabled (by clearing the DWEN fuse).

Table 20-1. Lock Bit Byte⁽¹⁾

Lock Bit

Bit No

Description

Default Value

7

6

5

4

3

2

1

0

–

1 (unprogrammed)

–

LB2

LB1

Lock bit

Note:

1. “1” means unprogrammed, “0” means programmed

Table 20-2. Lock Bit Protection Modes⁽¹⁾⁽²⁾

Memory Lock Bits Protection Type

LB Mode

LB2

LB1

1

2

1

No memory lock features enabled.

Further programming of the Flash and EEPROM is disabled in

High-voltage and Serial Programming mode. The Fuse bits are

locked in both Serial and High-voltage Programming mode.⁽¹⁾

debugWire is disabled.

1

0

Further programming and verification of the Flash and EEPROM

is disabled in High-voltage and Serial Programming mode. The

Fuse bits are locked in both Serial and High-voltage

Programming mode.⁽¹⁾debugWire is disabled.

3

Notes: 1. Program the Fuse bits before programming the LB1 and LB2.

2. “1” means unprogrammed, “0” means programmed

Lock bits can also be read by device firmware. See section “Reading Lock, Fuse and Signature

Data from Software” on page 147.

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20.2 Fuse Bytes

ATtiny25/45/85 has three fuse bytes, as described in Table 20-3, Table 20-4, and Table 20-5.

Note that fuses are read as logical zero, “0”, when programmed.

Table 20-3. Fuse Extended Byte

Fuse High Byte

Bit No Description

Default Value

7

6

5

4

3

2

1

0

-

1 (unprogrammed)

-

SELFPRGEN ⁽¹⁾

Self-programming enabled

Notes: 1. Enables SPM instruction. See “Self-Programming the Flash” on page 145.

Table 20-4. Fuse High Byte

Fuse High Byte

RSTDISBL ^{(1) (2)}

DWEN ^{(1) (2) (3)}

Bit No Description

Default Value

7

6

External reset disabled

1 (unprogrammed)

DebugWIRE enabled

0 (programmed)

Serial program and data download

enabled

SPIEN ⁽⁴⁾

WDTON ⁽⁵⁾

EESAVE

5

4

3

(SPI prog. enabled)

Watchdog timer always on

1 (unprogrammed)

(EEPROM not preserved)

EEPROM preserves chip erase

BODLEVEL2 ⁽⁶⁾

BODLEVEL1 ⁽⁶⁾

BODLEVEL0 ⁽⁶⁾

2

1

0

Brown-out Detector trigger level

1 (unprogrammed)

Notes: 1. Controls use of RESET pin. See “Alternate Functions of Port B” on page 61.

2. After this fuse has been programmed device can be programmed via high-voltage serial mode,

only.

3. Must be unprogrammed when lock bit security is required. See “Program And Data Memory

Lock Bits” on page 151.

4. This fuse is not accessible in SPI programming mode.

5. See “WDTCR – Watchdog Timer Control Register” on page 47 for details.

6. See table “BODLEVEL Fuse Coding” on page 171.

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Table 20-5. Fuse Low Byte

Fuse Low Byte

CKDIV8 ⁽¹⁾

CKOUT ⁽²⁾

SUT1 ⁽³⁾

Bit No Description

Default Value

7

6

5

4

3

2

1

0

Clock divided by 8

0 (programmed)

Clock output enabled

Start-up time setting

Clock source setting

1 (unprogrammed)

1 (unprogrammed)⁽³⁾

0 (programmed)⁽³⁾

0 (programmed)⁽⁴⁾

1 (unprogrammed)⁽⁴⁾

0 (programmed)⁽⁴⁾

SUT0 ⁽³⁾

CKSEL3 ⁽⁴⁾

CKSEL2 ⁽⁴⁾

CKSEL1 ⁽⁴⁾

CKSEL0 ⁽⁴⁾

Notes: 1. See “System Clock Prescaler” on page 31 for details.

2. Allows system clock to be output on pin. See “Clock Output Buffer” on page 32 for details.

3. The default value gives maximum start-up time for the default clock source. See Table 6-7 on

page 28 for details.

4. The default setting selects internal, 8MHz RC oscillator. See Table 6-6 on page 28 for details.

Note that fuse bits are locked if Lock Bit 1 (LB1) is programmed. Fuse bits should be pro-

grammed before lock bits. The status of fuse bits is not affected by chip erase.

Lock bits can also be read by device firmware. See section “Reading Lock, Fuse and Signature

Data from Software” on page 147.

20.2.1

Latching of Fuses

Fuse values are latched when the device enters programming mode and changes to fuse values

will have no effect until the part leaves programming mode. This does not apply to the EESAVE

Fuse which takes effect once it is programmed. Fuses are also latched on power-up.

20.3 Device Signature Imprint Table

The device signature imprint table is a dedicated memory area used for storing miscellaneous

device information, such as the device signature and oscillator calibaration data. Most of this

memory segment is reserved for internal use, as outlined in Table 20-6.

Table 20-6. Contents of Device Signature Imprint Table.

Address

0x00

High Byte

Signature byte 0 ⁽¹⁾

0x01

Calibration data for internal oscillator at 8.0 MHz ⁽²⁾

Signature byte 1 ⁽¹⁾

0x02

0x03

Calibration data for internal oscillator at 6.4 MHz ⁽²⁾

Signature byte 2 ⁽¹⁾

0x04

0x05 ... 0x2A

Reserved for internal use

Notes: 1. See section “Signature Bytes” for more information.

2. See section “Calibration Bytes” for more information.

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20.3.1

Signature Bytes

All Atmel microcontrollers have a three-byte signature code which identifies the device. This

code can be read in both serial and high-voltage programming mode, even when the device is

locked.

Signature bytes can also be read by the device firmware. See section “Reading Lock, Fuse and

Signature Data from Software” on page 147.

The three signature bytes reside in a separate address space called the device signature imprint

table. The signature data for ATtiny25/45/85 is given in Table 20-7.

Table 20-7. Device Signature Bytes

Part

Signature Byte 0

Signature Byte 1

Signature Byte 0

ATtiny25

ATtiny45

ATtiny85

0x1E

0x91

0x92

0x93

0x08

0x06

0x0B

20.3.2

Calibration Bytes

The device signature imprint table of ATtiny25/45/85 contains two bytes of calibration data for

the internal RC Oscillator, as shown in Table 20-6 on page 153. In normal mode of operation the

calibration data for 9.6 MHz operation is automatically fetched and written to the OSCCAL regis-

ter during reset. In ATtiny15 compatibility mode the calibraiton data for 4.8 MHz operation is

used instead. This procedure guarantees the internal oscillator is always calibrated to the cor-

rect frequency.

Calibration bytes can also be read by the device firmware. See section “Reading Lock, Fuse and

Signature Data from Software” on page 147.

20.4 Page Size

Table 20-8. No. of Words in a Page and No. of Pages in the Flash

Device

Flash Size

Page Size

PCWORD

No. of Pages

PCPAGE

PCMSB

1K words

(2K bytes)

ATtiny25

16 words

PC[3:0]

64

PC[9:4]

9

2K words

(4K bytes)

ATtiny45

ATtiny85

32 words

PC[4:0]

64

PC[10:5]

PC[11:5]

10

11

4K words

(8K bytes)

128

Table 20-9. No. of Words in a Page and No. of Pages in the EEPROM

EEPROM

Device

ATtiny25

ATtiny45

ATtiny85

Size

Page Size

4 bytes

PCWORD

EEA[1:0]

No. of Pages

PCPAGE

EEA[6:2]

EEA[7:2]

EEA[8:2]

EEAMSB

128 bytes

256 bytes

512 bytes

32

64

6

7

8

4 bytes

128

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20.5 Serial Downloading

Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus while

RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and MISO (out-

put). See below.

Figure 20-1. Serial Programming and Verify⁽¹⁾

+1.8 - 5.5V

VCC

MOSI

MISO

SCK

RESET

GND

Notes: 1. If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the

CLKI pin.

After RESET is set low, the Programming Enable instruction needs to be executed first before

program/erase operations can be executed.

Table 20-10. Pin Mapping Serial Programming

Symbol

MOSI

MISO

SCK

Pins

PB0

PB1

PB2

I/O

Description

Serial Data in

Serial Data out

Serial Clock

I

O

I

Note:

In Table 20-10 above, the pin mapping for SPI programming is listed. Not all parts use the SPI

pins dedicated for the internal SPI interface.

When programming the EEPROM, an auto-erase cycle is built into the self-timed programming

operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase

instruction. The Chip Erase operation turns the content of every memory location in both the

Program and EEPROM arrays into 0xFF.

Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high periods

for the serial clock (SCK) input are defined as follows:

Low: > 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck>= 12 MHz

High: > 2 CPU clock cycles for f_ck< 12 MHz, 3 CPU clock cycles for f_ck>= 12 MHz

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20.5.1

Serial Programming Algorithm

When writing serial data to the ATtiny25/45/85, data is clocked on the rising edge of SCK.

When reading data from the ATtiny25/45/85, data is clocked on the falling edge of SCK. See

Figure 21-4 and Figure 21-5 for timing details.

To program and verify the ATtiny25/45/85 in the Serial Programming mode, the following

sequence is recommended (see four byte instruction formats in Table 20-12):

1. Power-up sequence:

Apply power between V_CCand GND while RESET and SCK are set to “0”. In some sys-

tems, the programmer can not guarantee that SCK is held low during power-up. In this

case, RESET must be given a positive pulse of at least two CPU clock cycles duration

after SCK has been set to “0”.

2. Wait for at least 20 ms and enable serial programming by sending the Programming

Enable serial instruction to pin MOSI.

3. The serial programming instructions will not work if the communication is out of syn-

chronization. When in sync. the second byte (0x53), will echo back when issuing the

third byte of the Programming Enable instruction. Whether the echo is correct or not, all

four bytes of the instruction must be transmitted. If the 0x53 did not echo back, give

RESET a positive pulse and issue a new Programming Enable command.

4. The Flash is programmed one page at a time. The memory page is loaded one byte at

a time by supplying the 5 LSB of the address and data together with the Load Program

memory Page instruction. To ensure correct loading of the page, the data low byte must

be loaded before data high byte is applied for a given address. The Program memory

Page is stored by loading the Write Program memory Page instruction with the 6 MSB

of the address. If polling (RDY/BSY) is not used, the user must wait at least t_{WD_FLASH}

before issuing the next page. (See Table 20-11.) Accessing the serial programming

interface before the Flash write operation completes can result in incorrect

programming.

5. A: The EEPROM array is programmed one byte at a time by supplying the address and

data together with the appropriate Write instruction. An EEPROM memory location is

first automatically erased before new data is written. If polling (RDY/BSY) is not used,

the user must wait at least t_{WD_EEPROM}before issuing the next byte. (See Table 20-11.)

In a chip erased device, no 0xFFs in the data file(s) need to be programmed.

B: The EEPROM array is programmed one page at a time. The Memory page is loaded

one byte at a time by supplying the 2 LSB of the address and data together with the

Load EEPROM Memory Page instruction. The EEPROM Memory Page is stored by

loading the Write EEPROM Memory Page Instruction with the 6 MSB of the address.

When using EEPROM page access only byte locations loaded with the Load EEPROM

Memory Page instruction is altered. The remaining locations remain unchanged. If poll-

ing (RDY/BSY) is not used, the used must wait at least t_{WD_EEPROM}before issuing the

next page (See Table 20-9). In a chip erased device, no 0xFF in the data file(s) need to

be programmed.

6. Any memory location can be verified by using the Read instruction which returns the

content at the selected address at serial output MISO.

7. At the end of the programming session, RESET can be set high to commence normal

operation.

8. Power-off sequence (if needed):

Set RESET to “1”.

Turn V_CCpower off.

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20.5.2

Serial Programming Instruction set

Table 20-11. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location

Symbol

Minimum Wait Delay

4.5 ms

t_{WD_FLASH}

t_{WD_EEPROM}

t_{WD_ERASE}

t_{WD_FUSE}

4.0 ms

4.5 ms

Table 20-12 on page 157 and Figure 20-2 on page 158 describes the Instruction set.

Table 20-12. Serial Programming Instruction Set

Instruction Format

Instruction/Operation

Byte 1

$AC

Byte 2

Byte 3

$00

Byte4

$00

Programming Enable

$53

$80

$00

Chip Erase (Program Memory/EEPROM)

Poll RDY/BSY

$AC

$00

$F0

$00

data byte out

Load Instructions

Load Extended Address byte⁽¹⁾

Load Program Memory Page, High byte

Load Program Memory Page, Low byte

Load EEPROM Memory Page (page access)

Read Instructions

$4D

$48

$40

$C1

$00

adr MSB

$00

Extended adr

adr LSB

$00

high data byte in

low data byte in

data byte in

adr LSB

0000 000aa

Read Program Memory, High byte

Read Program Memory, Low byte

Read EEPROM Memory

Read Lock bits

$28

$20

$A0

$58

$30

$50

$58

$50

$38

adr MSB

$00

adr LSB

00aa aaaa

$00

high data byte out

low data byte out

data byte out

$00

Read Signature Byte

$00

0000 000aa

$00

Read Fuse bits

$00

Read Fuse High bits

$08

$00

Read Extended Fuse Bits

Read Calibration Byte

$08

$00

Write Instructions⁽⁶⁾

Write Program Memory Page

Write EEPROM Memory

Write EEPROM Memory Page (page access)

Write Lock bits

$4C

$C0

$C2

$AC

adr MSB

$00

adr LSB

00aa aaaa

00aa aa00

$00

data byte in

$00

$E0

data byte in

Write Fuse bits

$A0

$00

Write Fuse High bits

$A8

$00

Write Extended Fuse Bits

$A4

$00

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Notes: 1. Not all instructions are applicable for all parts.

2. a = address

3. Bits are programmed ‘0’, unprogrammed ‘1’.

4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’) .

5. Refer to the correspondig section for Fuse and Lock bits, Calibration and Signature bytes and Page size.

6. Instructions accessing program memory use a word address. This address may be random within the page range.

7. See htt://www.atmel.com/avr for Application Notes regarding programming and programmers.

If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until

this bit returns ‘0’ before the next instruction is carried out.

Within the same page, the low data byte must be loaded prior to the high data byte.

After data is loaded to the page buffer, program the EEPROM page, see Figure 20-2 on page

158.

Figure 20-2. Serial Programming Instruction example

Serial Programming Instruction

Load Program Memory Page (High/Low Byte)/

Load EEPROM Memory Page (page access)

Write Program Memory Page/

Write EEPROM Memory Page

Byte 1

Byte 2

Byte 3

Byte 4

Byte 1

Byte 2

Byte 3

Byte 4

Adr MSB

Adr LSB

Adr MSB

Adr LSB

Bit 15 B

0

Bit 15 B

0

Page Buffer

Page Offset

Page 0

Page 1

Page 2

Page Number

Page N-1

Program Memory/

EEPROM Memory

20.6 High-voltage Serial Programming

This section describes how to program and verify Flash Program memory, EEPROM Data mem-

ory, Lock bits and Fuse bits in the ATtiny25/45/85.

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Figure 20-3. High-voltage Serial Programming

+11.5 - 12.5V

+4.5 - 5.5V

PB5

PB3

VCC

PB2

(RESET)

SCI

SDO

SII

PB1

PB0

GND

SDI

Table 20-13. Pin Name Mapping

Signal Name in High-voltage

Serial Programming Mode

Pin Name

PB0

I/O

Function

Serial Data Input

SDI

SII

I

PB1

I

Serial Instruction Input

SDO

SCI

PB2

O

I

Serial Data Output

PB3

Serial Clock Input (min. 220ns period)

The minimum period for the Serial Clock Input (SCI) during High-voltage Serial Programming is

220 ns.

Table 20-14. Pin Values Used to Enter Programming Mode

SDI

SII

Symbol

Value

Prog_enable[0]

Prog_enable[1]

Prog_enable[2]

0

SDO

20.7 High-voltage Serial Programming Algorithm

To program and verify the ATtiny25/45/85 in the High-voltage Serial Programming mode, the fol-

lowing sequence is recommended (See instruction formats in Table 20-16):

20.7.1

Enter High-voltage Serial Programming Mode

The following algorithm puts the device in High-voltage Serial Programming mode:

1. Set Prog_enable pins listed in Table 20-14 to “000”, RESET pin and V_CCto 0V.

2. Apply 4.5 - 5.5V between V_CCand GND. Ensure that V_CCreaches at least 1.8V within

the next 20 µs.

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3. Wait 20 - 60 µs, and apply 11.5 - 12.5V to RESET.

4. Keep the Prog_enable pins unchanged for at least 10 µs after the High-voltage has

been applied to ensure the Prog_enable Signature has been latched.

5. Release the Prog_enable[2] pin to avoid drive contention on the Prog_enable[2]/SDO

pin.

6. Wait at least 300 µs before giving any serial instructions on SDI/SII.

7. Exit Programming mode by power the device down or by bringing RESET pin to 0V.

If the rise time of the V_CCis unable to fulfill the requirements listed above, the following alterna-

tive algorithm can be used:

1. Set Prog_enable pins listed in Table 20-14 to “000”, RESET pin and V_CCto 0V.

2. Apply 4.5 - 5.5V between V_CCand GND.

3. Monitor V_CC, and as soon as V_CCreaches 0.9 - 1.1V, apply 11.5 - 12.5V to RESET.

4. Keep the Prog_enable pins unchanged for at least 10 µs after the High-voltage has

been applied to ensure the Prog_enable Signature has been latched.

5. Release the Prog_enable[2] pin to avoid drive contention on the Prog_enable[2]/SDO

pin.

6. Wait until V_CCactually reaches 4.5 - 5.5V before giving any serial instructions on

SDI/SII.

7. Exit Programming mode by power the device down or by bringing RESET pin to 0V.

Table 20-15. High-voltage Reset Characteristics

Minimum High-voltage Period for

Supply Voltage

RESET Pin High-voltage Threshold

Latching Prog_enable

V_CC

V_HVRST

11.5V

t_HVRST

100 ns

4.5V

5.5V

20.7.2

Considerations for Efficient Programming

The loaded command and address are retained in the device during programming. For efficient

programming, the following should be considered.

• The command needs only be loaded once when writing or reading multiple memory

locations.

• Skip writing the data value 0xFF that is the contents of the entire EEPROM (unless the

EESAVE Fuse is programmed) and Flash after a Chip Erase.

• Address High byte needs only be loaded before programming or reading a new 256 word

window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes

reading.

20.7.3

Chip Erase

The Chip Erase will erase the Flash and EEPROM⁽¹⁾memories plus Lock bits. The Lock bits are

not reset until the Program memory has been completely erased. The Fuse bits are not

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changed. A Chip Erase must be performed before the Flash and/or EEPROM are re-

programmed.

Note:

1. The EEPROM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.

1. Load command “Chip Erase” (see Table 20-16).

2. Wait after Instr. 3 until SDO goes high for the “Chip Erase” cycle to finish.

3. Load Command “No Operation”.

20.7.4

Programming the Flash

The Flash is organized in pages, see Table 20-12 on page 157. When programming the Flash,

the program data is latched into a page buffer. This allows one page of program data to be pro-

grammed simultaneously. The following procedure describes how to program the entire Flash

memory:

1. Load Command “Write Flash” (see Table 20-16).

2. Load Flash Page Buffer.

3. Load Flash High Address and Program Page. Wait after Instr. 3 until SDO goes high for

the “Page Programming” cycle to finish.

4. Repeat 2 through 3 until the entire Flash is programmed or until all data has been

programmed.

5. End Page Programming by Loading Command “No Operation”.

When writing or reading serial data to the ATtiny25/45/85, data is clocked on the rising edge of

the serial clock, see Figure 20-5, Figure 21-6 and Table 21-11 for details.

Figure 20-4. Addressing the Flash which is Organized in Pages

PCMSB

PAGEMSB

PROGRAM

COUNTER

PCPAGE

PCWORD

PAGE ADDRESS

WITHIN THE FLASH

WORD ADDRESS

WITHIN A PAGE

PROGRAM MEMORY

PAGE

INSTRUCTION WORD

PCWORD[PAGEMSB:0]:

00

01

02

PAGEEND

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Figure 20-5. High-voltage Serial Programming Waveforms

SDI

PB0

MSB

LSB

SII

PB1

MSB

SDO

MSB

LSB

PB2

SCI

0

1

2

3

4

5

6

7

8

9

10

PB3

20.7.5

Programming the EEPROM

The EEPROM is organized in pages, see Table 21-10 on page 174. When programming the

EEPROM, the data is latched into a page buffer. This allows one page of data to be pro-

grammed simultaneously. The programming algorithm for the EEPROM Data memory is as

follows (refer to Table 20-16):

1. Load Command “Write EEPROM”.

2. Load EEPROM Page Buffer.

3. Program EEPROM Page. Wait after Instr. 2 until SDO goes high for the “Page Program-

ming” cycle to finish.

4. Repeat 2 through 3 until the entire EEPROM is programmed or until all data has been

programmed.

5. End Page Programming by Loading Command “No Operation”.

20.7.6

20.7.7

Reading the Flash

The algorithm for reading the Flash memory is as follows (refer to Table 20-16):

1. Load Command "Read Flash".

2. Read Flash Low and High Bytes. The contents at the selected address are available at

serial output SDO.

Reading the EEPROM

The algorithm for reading the EEPROM memory is as follows (refer to Table 20-16):

1. Load Command “Read EEPROM”.

2. Read EEPROM Byte. The contents at the selected address are available at serial out-

put SDO.

20.7.8

20.7.9

Programming and Reading the Fuse and Lock Bits

The algorithms for programming and reading the Fuse Low/High bits and Lock bits are shown in

Table 20-16.

Reading the Signature Bytes and Calibration Byte

The algorithms for reading the Signature bytes and Calibration byte are shown in Table 20-16.

20.7.10 Power-off sequence

Set SCI to “0”. Set RESET to “1”. Turn V_CCpower off.

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Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85

Instruction Format

Instruction

Instr.1/5

Instr.2/6

Instr.3

Instr.4

Operation Remarks

SDI

SII

0_1000_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Wait after Instr.3 until SDO

goes high for the Chip Erase

cycle to finish.

Chip Erase

SDO

SDI

SII

0_0001_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

Load “Write

Flash”

Command

Enter Flash Programming

code.

SDO

Repeat after Instr. 1 - 5 until

the entire page buffer is filled

or until all data within the

page is filled. See Note 1.

SDI

SII

0_bbbb_bbbb _00

0_0000_1100_00

x_xxxx_xxxx_xx

0_eeee_eeee_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_dddd_dddd_00

0_0011_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1101_00

x_xxxx_xxxx_xx

SDO

Load Flash

Page Buffer

SDI

SII

0_0000_0000_00

0_0111_1100_00

x_xxxx_xxxx_xx

Instr 5.

SDO

Wait after Instr 3 until SDO

goes high. Repeat Instr. 2 - 3

for each loaded Flash Page

until the entire Flash or all

data is programmed. Repeat

Instr. 1 for a new 256 byte

page. See Note 1.

Load Flash

High Address

and Program

Page

SDI

SII

0_0000_000a_00

0_0001_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

SDO

SDI

SII

0_0000_0010_00

0_0100_1100_00

x_xxxx_xxxx_xx

Load “Read

Flash”

Command

Enter Flash Read mode.

SDO

SDI

SII

0_bbbb_bbbb_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_0000_000a_00

0_0001_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

q_qqqq_qqqx_xx

Repeat Instr. 1, 3 - 6 for each

new address. Repeat Instr. 2

for a new 256 byte page.

Read Flash

Low and High

Bytes

SDO

SDI

SII

0_0000_0000_00

0_0111_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1100_00

p_pppp_pppx_xx

Instr 5 - 6.

SDO

SDI

SII

0_0001_0001_00

0_0100_1100_00

x_xxxx_xxxx_xx

Load “Write

EEPROM”

Command

Enter EEPROM Programming

mode.

SDO

Repeat Instr. 1 - 5 until the

entire page buffer is filled or

until all data within the page is

filled. See Note 2.

SDI

SII

0_00bb_bbbb_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_aaaa_aaaa_00

0_0001_1100_00

x_xxxx_xxxx_xx

0_eeee_eeee_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1101_00

x_xxxx_xxxx_xx

Load

EEPROM

Page Buffer

SDO

SDI

SII

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Instr. 5

SDO

Wait after Instr. 2 until SDO

goes high. Repeat Instr. 1 - 2

for each loaded EEPROM

page until the entire

EEPROM or all data is

programmed.

SDI

SII

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Program

EEPROM

Page

SDO

163

2586K–AVR–01/08

Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued)

Instruction Format

Instruction

Instr.1/5

Instr.2/6

Instr.3

Instr.4

Operation Remarks

Repeat Instr. 1 - 6 for each

new address. Wait after Instr.

6 until SDO goes high. See

Note 3.

SDI

SII

0_bbbb_bbbb_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_aaaa_aaaa_00

0_0001_1100_00

x_xxxx_xxxx_xx

0_eeee_eeee_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1101_00

x_xxxx_xxxx_xx

Write

EEPROM

Byte

SDO

SDI

SII

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Instr. 6

SDO

SDI

SII

0_0000_0011_00

0_0100_1100_00

x_xxxx_xxxx_xx

Load “Read

EEPROM”

Command

Enter EEPROM Read mode.

SDO

SDI

SII

0_bbbb_bbbb_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_aaaa_aaaa_00

0_0001_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

q_qqqq_qqq0_00

Read

EEPROM

Byte

Repeat Instr. 1, 3 - 4 for each

new address. Repeat Instr. 2

for a new 256 byte page.

SDO

SDI

SII

0_0100_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_A987_6543_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Wait after Instr. 4 until SDO

goes high. Write A - 3 = “0” to

program the Fuse bit.

Write Fuse

Low Bits

SDO

SDI

SII

0_0100_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_000F_EDCB_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1100_00

x_xxxx_xxxx_xx

Wait after Instr. 4 until SDO

goes high. Write F - B = “0” to

program the Fuse bit.

Write Fuse

High Bits

SDO

SDI

SII

0_0100_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_000J_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0110_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1110_00

x_xxxx_xxxx_xx

Wait after Instr. 4 until SDO

goes high. Write J = “0” to

program the Fuse bit.

Write Fuse

Extended Bits

SDO

SDI

SII

0_0010_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0021_00

0_0010_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_0100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

x_xxxx_xxxx_xx

Wait after Instr. 4 until SDO

goes high. Write 2 - 1 = “0” to

program the Lock bit.

Write Lock

Bits

SDO

SDI

SII

0_0000_0100_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

A_9876_543x_xx

Read Fuse

Low Bits

Reading A - 3 = “0” means

the Fuse bit is programmed.

SDO

SDI

SII

0_0000_0100_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1010_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1110_00

x_xxFE_DCBx_xx

Read Fuse

High Bits

Reading F - B = “0” means

the Fuse bit is programmed.

SDO

SDI

SII

0_0000_0100_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1010_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1110_00

x_xxxx_xxJx_xx

Read Fuse

Extended Bits

Reading J = “0” means the

Fuse bit is programmed.

SDO

SDI

SII

0_0000_0100_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1100_00

x_xxxx_x21x_xx

Read Lock

Bits

Reading 2, 1 = “0” means the

Lock bit is programmed.

SDO

164

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

Table 20-16. High-voltage Serial Programming Instruction Set for ATtiny25/45/85 (Continued)

Instruction Format

Instruction

Instr.1/5

Instr.2/6

Instr.3

Instr.4

Operation Remarks

SDI

SII

0_0000_1000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_00bb_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0110_1100_00

q_qqqq_qqqx_xx

Read

Signature

Bytes

Repeats Instr 2 4 for each

signature byte address.

SDO

SDI

SII

0_0000_1000_00

0_0100_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0000_1100_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1000_00

x_xxxx_xxxx_xx

0_0000_0000_00

0_0111_1100_00

p_pppp_pppx_xx

Read

Calibration

Byte

SDO

SDI

SII

0_0000_0000_00

0_0100_1100_00

x_xxxx_xxxx_xx

Load “No

Operation”

Command

SDO

Note:

a = address high bits, b = address low bits, d = data in high bits, e = data in low bits, p = data out high bits, q = data out low bits,

x = don’t care, 1 = Lock Bit1, 2 = Lock Bit2, 3 = CKSEL0 Fuse, 4 = CKSEL1 Fuse, 5 = SUT0 Fuse, 6 = SUT1 Fuse, 7 = CKDIV8,

Fuse, 8 = WDTON Fuse, 9 = EESAVE Fuse, A = SPIEN Fuse, B = RSTDISBL Fuse, C = BODLEVEL0 Fuse, D= BODLEVEL1

Fuse, E = MONEN Fuse, F = SPMEN Fuse

Notes: 1. For page sizes less than 256 words, parts of the address (bbbb_bbbb) will be parts of the page address.

2. For page sizes less than 256 bytes, parts of the address (bbbb_bbbb) will be parts of the page address.

3. The EEPROM is written page-wise. But only the bytes that are loaded into the page are actually written to the EEPROM.

Page-wise EEPROM access is more efficient when multiple bytes are to be written to the same page. Note that auto-erase

of EEPROM is not available in High-voltage Serial Programming, only in SPI Programming.

165

2586K–AVR–01/08

21. Electrical Characteristics

21.1 Absolute Maximum Ratings*

*NOTICE:

Stresses beyond those listed under “Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or

other conditions beyond those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions for extended periods may affect

device reliability.

Operating Temperature.................................. -55°C to +125°C

Storage Temperature..................................... -65°C to +150°C

Voltage on any Pin except RESET

with respect to Ground ................................-0.5V to V_CC+0.5V

Voltage on RESET with respect to Ground......-0.5V to +13.0V

Maximum Operating Voltage ............................................ 6.0V

DC Current per I/O Pin ............................................... 40.0 mA

DC Current V_CCand GND Pins................................ 200.0 mA

21.2 DC Characteristics

Table 21-1.

DC Characteristics. T_A= -40°C to 85°C ⁽¹⁾

Parameter Condition

_CC= 1.8V - 2.4V

Symbol

Min.⁽²⁾

Typ.

Max.⁽³⁾

Units

-0.5

0.2V_CC

0.3V_CC

Input Low-voltage, except

XTAL1 and RESET pin

V

V_IL

V_CC= 2.4V - 5.5V

0.7V_CC

0.6V_CC

V_CC+0.5

Input High-voltage, except

XTAL1 and RESET pin

V

_CC= 1.8V - 2.4V

V

V_IH

V_CC= 2.4V - 5.5V

V_CC+0.5

Input Low-voltage, XTAL1 pin,

External Clock Selected

V_IL1

V_IH1

V_IL2

V_IH2

V_IL3

V_CC= 1.8V - 5.5V

-0.5

0.1V_CC

V

0.8V_CC

0.7V_CC

V_CC+0.5

Input High-voltage, XTAL1 pin,

External Clock Selected

V_CC= 1.8V - 2.4V

V_CC= 2.4V - 5.5V

V

Input Low-voltage,

RESET pin

V

V_CC= 1.8V - 5.5V

-0.5

0.2V_CC

Input High-voltage,

RESET pin

V

_CC= 1.8V - 5.5V

_CC= 1.8V - 2.4V

0.9V_CC

V_CC+0.5

V

-0.5

0.2V_CC

0.3V_CC

Input Low-voltage,

RESET pin as I/O

V

V_CC= 2.4V - 5.5V

0.7V_CC

0.6V_CC

V_CC+0.5

Input High-voltage,

RESET pin as I/O

V

_CC= 1.8V - 2.4V

V

V_IH3

V_OL

V_OH

I_IL

V_CC= 2.4V - 5.5V

Output Low-voltage,⁽⁴⁾

I_OL= 10 mA, V_CC= 5V

I_OL= 5 mA, V_CC= 3V

0.6

0.5

V

Port B (except RESET) ⁽⁶⁾

Output High-voltage, ⁽⁵⁾

I_OH= -10 mA, V_CC= 5V

I_OH= -5 mA, V_CC= 3V

4.3

2.5

V

Port B (except RESET) ⁽⁶⁾

Input Leakage

Current I/O Pin

Vcc = 5.5V, pin low

(absolute value)

< 0.05

1

µA

Input Leakage

Current I/O Pin

Vcc = 5.5V, pin high

(absolute value)

I_IH

166

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

Table 21-1.

Symbol

R_RST

DC Characteristics. T_A= -40°C to 85°C ⁽¹⁾(Continued)

Parameter

Condition

Min.⁽²⁾

30

Typ.

Max.⁽³⁾

60

Units

kΩ

Reset Pull-up Resistor

I/O Pin Pull-up Resistor

Vcc = 5.5V, input low

Active 1MHz, V_CC= 2V

Active 4MHz, V_CC= 3V

Active 8MHz, V_CC= 5V

Idle 1MHz, V_CC= 2V

Idle 4MHz, V_CC= 3V

Idle 8MHz, V_CC= 5V

WDT enabled, V_CC= 3V

WDT disabled, V_CC= 3V

R_pu

20

50

kΩ

0.3

1.5

5

0.55

2.5

8

mA

µA

Power Supply Current

0.1

0.35

1.2

0.2

0.6

2

(7)

I_CC

10

Power-down mode⁽⁸⁾

2

µA

Notes: 1. Typical values at 25°C. Maximum values are characterised and not production test limits.

2. “Min” means the lowest value where the pin is guaranteed to be read as high.

3. “Max” means the highest value where the pin is guaranteed to be read as low.

4. Although each I/O port can sink more than the test conditions (10 mA at V_CC= 5V, 5 mA at V_CC= 3V) under steady state

conditions (non-transient), the following must be observed:

1] The sum of all IOL, for all ports, should not exceed 60 mA.

If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test condition.

5. Although each I/O port can source more than the test conditions (10 mA at V_CC= 5V, 5 mA at V_CC= 3V) under steady state

conditions (non-transient), the following must be observed:

1] The sum of all IOH, for all ports, should not exceed 60 mA.

If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current

greater than the listed test condition.

6. The RESET pin must tolerate high voltages when entering and operating in programming modes and, as a consequence,

has a weak drive strength as compared to regular I/O pins. See Figure 22-23, Figure 22-24, Figure 22-25, and Figure 22-26

(starting on page 188).

7. All I/O modules are turned off (PRR = 0xFF) for all I_CCvalues.

8. Brown-Out Detection (BOD) disabled.

167

2586K–AVR–01/08

21.3 Speed Grades

Figure 21-1. Maximum Frequency vs. V_CC

10 MHz

Safe Operating Area

4 MHz

1.8V

2.7V

5.5V

Figure 21-2. Maximum Frequency vs. V_CC

20 MHz

10 MHz

Safe Operating Area

2.7V

4.5V

5.5V

168

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

21.4 Clock Characteristics

21.4.1

Calibrated Internal RC Oscillator Accuracy

It is possible to manually calibrate the internal oscillator to be more accurate than default factory

calibration. Please note that the oscillator frequency depends on temperature and voltage. Volt-

age and temperature characteristics can be found in Figure 22-38 on page 196 and Figure 22-

39 on page 196.

Table 21-2. Calibration Accuracy of Internal RC Oscillator

Calibration

Method

Accuracy at given Voltage

& Temperature⁽¹⁾

Target Frequency

V_CC

Temperature

Factory

Calibration

8.0 MHz ⁽²⁾

3V

25°C

±10%

±1%

Fixed voltage within:

1.8V - 5.5V⁽³⁾

Fixed temperature

within:

Fixed frequency within:

6 – 8 MHz

User

Calibration

2.7V - 5.5V⁽⁴⁾

-40°C - 85°C

Notes: 1. Accuracy of oscillator frequency at calibration point (fixed temperature and fixed voltage).

2. ATtiny25/V, only: 6.4 MHz in ATtiny15 Compatibility Mode.

3. Voltage range for ATtiny25V/45V/85V.

4. Voltage range for ATtiny25/45/85.

21.4.2

External Clock Drive

Figure 21-3. External Clock Drive Waveforms

V_IH1

V_IL1

21.4.3

External Clock Drive

Table 21-3. External Clock Drive

V_CC= 1.8 - 5.5V

V_CC= 2.7 - 5.5V

V_CC= 4.5 - 5.5V

Symbol

1/t_CLCL

t_CLCL

Parameter

Min.

Max.

Min.

0

Max.

Min.

0

Max.

Units

MHz

ns

Clock Frequency

0

4

10

20

Clock Period

250

100

40

50

20

t_CHCX

t_CLCX

High Time

ns

Low Time

40

ns

t_CLCH

Rise Time

2.0

2

1.6

2

0.5

2

μs

t_CHCL

Fall Time

μs

Δt_CLCL

Change in period from one clock cycle to the next

%

169

2586K–AVR–01/08

21.5 System and Reset Characteristics

Table 21-4. Reset, Brown-out and Internal Voltage Characteristics

Symbol

Parameter

Condition

Min⁽¹⁾

Typ⁽¹⁾

Max⁽¹⁾

Units

V_RST

RESET Pin Threshold Voltage

V_CC= 3V

0.2 V_CC

0.9 V_CC

V

Minimum pulse width on

RESET Pin

t_RST

V_HYST

t_BOD

V_CC= 3V

2.5

µs

mV

µs

Brown-out Detector Hysteresis

50

2

Min Pulse Width on

Brown-out Reset

Bandgap reference

voltage

V_CC= 5.5V

T_A= 25°C

V_BG

t_BG

I_BG

1.0

1.1

40

15

1.2

70

V

Bandgap reference

start-up time

V_CC= 2.7V

T_A= 25°C

µs

µA

Bandgap reference

current consumption

V_CC= 2.7V

T_A= 25°C

Note:

1. Values are guidelines only.

Two versions of power-on reset have been implemented, as follows.

Standard Power-On Reset

21.5.1

This implementation of power-on reset existed in early versions of ATtiny25/45/85. The table

below describes the characteristics of this power-on reset and it is valid for the following devices,

only:

• ATtiny25, revision D, and older

• ATtiny45, revision F, and older

• ATtiny85, revision B, and newer

Note:

Revisions are marked on the package (packages 8P3 and 8S2: bottom, package 20M1: top)

Table 21-5. Characteristics of Standard Power-On Reset. T_A= -40 - 85°C

Symbol

V_POR

Parameter

Min⁽¹⁾

Typ⁽¹⁾

Max⁽¹⁾

1.4

Units

V

Release threshold of power-on reset ⁽²⁾

Activation threshold of power-on reset ⁽³⁾

Power-on slope rate

0.7

1.0

V_POA

0.05

0.01

0.9

1.3

V

SR_ON

4.5

V/ms

Note:

1. Values are guidelines, only

2. Threshold where device is released from reset when voltage is rising

3. The power-on reset will not work unless the supply voltage has been below V_POA

170

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

21.5.2

Enhanced Power-On Reset

This implementation of power-on reset exists in newer versions of ATtiny25/45/85. The table

below describes the characteristics of this power-on reset and it is valid for the following devices,

only:

• ATtiny25, revision E, and newer

• ATtiny45, revision G, and newer

• ATtiny85, revision C, and newer

Table 21-6. Characteristics of Enhanced Power-On Reset. T_A= -40 - 85°C

Symbol

V_POR

Parameter

Min⁽¹⁾

Typ⁽¹⁾

Max⁽¹⁾

1.6

Units

V

Release threshold of power-on reset ⁽²⁾

Activation threshold of power-on reset ⁽³⁾

Power-On Slope Rate

1.1

1.4

V_POA

0.6

1.3

1.6

V

SR_ON

0.01

V/ms

Note:

1. Values are guidelines, only

2. Threshold where device is released from reset when voltage is rising

3. The Power-on Reset will not work unless the supply voltage has been below V_POT(falling)

21.6 Brown-Out Detection

Table 21-7. BODLEVEL Fuse Coding

BODLEVEL [2:0] Fuses

Min⁽¹⁾

Typ⁽¹⁾

BOD Disabled

Max⁽¹⁾

Units

111

110

101

100

0XX

1.7

2.5

4.1

1.8

2.7

4.3

2.0

2.9

4.5

V

Reserved

Note:

1. V_BOTmay be below nominal minimum operating voltage for some devices. For devices where

this is the case, the device is tested down to V_CC= V_BOTduring the production test. This guar-

antees that a Brown-out Reset will occur before V_CCdrops to a voltage where correct

operation of the microcontroller is no longer guaranteed.

171

2586K–AVR–01/08

21.7 ADC Characteristics – Preliminary

Table 21-8. ADC Characteristics, Single Ended Channels. -40°C - 85°C

Symbol

Parameter

Condition

Min⁽¹⁾

Typ⁽¹⁾

Max⁽¹⁾

Units

Resolution

10

Bits

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

2

3

LSB

V_REF= 4V, V_CC= 4V,

ADC clock = 1 MHz

Absolute accuracy

(Including INL, DNL, and

Quantization, Gain and

Offset errors)

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

1.5

2.5

1

LSB

Noise Reduction Mode

V_REF= 4V, V_CC= 4V,

ADC clock = 1 MHz

Noise Reduction Mode

Integral Non-linearity (INL)

(Accuracy after offset and gain

calibration)

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

Differential Non-linearity (DNL)

Gain Error

0.5

2.5

1.5

LSB

V_REF= 4V, V_CC= 4V,

ADC clock = 200 kHz

V_REF= 4V, V_CC= 4V,

Offset Error

ADC clock = 200 kHz

Conversion Time

Free Running Conversion

14

50

280

1000

V_REF

µs

kHz

V

Clock Frequency

V_IN

Input Voltage

GND

Input Bandwidth

38.4

kHz

V

AREF

V_INT

External Reference Voltage

Internal Voltage Reference

2.0

1.0

V_CC

1.2

1.1

32

V

R_REF

R_AIN

kΩ

MΩ

LSB

Analog Input Resistance

ADC Output

100

0

1023

Note:

1. Values are preliminary for ATtiny25 and ATtiny85.

172

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

Table 21-9. ADC Characteristics, Differential Channels (Unipolar Mode), T_A= -40°C to 85°C

Symbol Parameter

Condition

Gain = 1x

Gain = 20x

Gain = 1x

Min⁽¹⁾

Typ⁽¹⁾

Max⁽¹⁾

10

Units

Bits

Resolution

10

Bits

V

_REF= 4V, V_CC= 5V

10.0

20.0

4.0

TBD

LSB

Absolute accuracy

(Including INL, DNL, and Quantization, Gain

and Offset Errors)

ADC clock = 50 - 200 kHz

Gain = 20x

V_REF= 4V, V_CC= 5V

ADC clock = 50 - 200 kHz

Gain = 1x

V_REF= 4V, V_CC= 5V

ADC clock = 50 - 200 kHz

Integral Non-Linearity (INL)

(Accuracy after Offset and Gain Calibration)

Gain = 20x

V_REF= 4V, V_CC= 5V

ADC clock = 50 - 200 kHz

10.0

Gain = 1x

Gain = 20x

Gain = 1x

10.0

15.0

TBD

LSB

Gain Error

V

_REF= 4V, V_CC= 5V

3.0

4.0

TBD

LSB

ADC clock = 50 - 200 kHz

Offset Error

Gain = 20x

V_REF= 4V, V_CC= 5V

ADC clock = 50 - 200 kHz

Conversion Time

Free Running Conversion

70

50

280

200

µs

kHz

V

Clock Frequency

V_IN

Input Voltage

GND

V_CC

V_DIFF

Input Differential Voltage

Input Bandwidth

V_REF/Gain

V

4

kHz

V

AREF

V_INT

External Reference Voltage

Internal Voltage Reference

Reference Input Resistance

Analog Input Resistance

2.0

1.0

V_CC- 1.0

1.2

1.1

32

V

R_REF

R_AIN

kΩ

MΩ

LSB

100

ADC Conversion Output

0

1023

Note:

1. Values are preliminary for ATtiny25 and ATtiny85.

173

2586K–AVR–01/08

21.8 Serial Programming Characteristics

Figure 21-4. Serial Programming Waveforms

SERIAL DATA INPUT

(MOSI)

MSB

LSB

SERIAL DATA OUTPUT

(MISO)

MSB

SERIAL CLOCK INPUT

(SCK)

SAMPLE

Figure 21-5. Serial Programming Timing

MOSI

t_OVSH

t_SLSH

t_SHOX

SCK

t_SHSL

MISO

t_SLIV

Table 21-10. Serial Programming Characteristics, T_A= -40°C to 85°C, V_CC= 1.8 - 5.5V (Unless

Otherwise Noted)

Symbol

1/t_CLCL

t_CLCL

Parameter

Min

0

Typ

Max

Units

MHz

ns

Oscillator Frequency (ATtiny25V/45V/85V)

Oscillator Period (ATtiny25V/45V/85V)

Oscillator Freq. (ATtiny25/45/85, VCC = 2.7 - 5.5V)

Oscillator Period (ATtiny25/45/85, VCC = 2.7 - 5.5V)

Oscillator Freq. (ATtiny25/45/85, V_CC= 4.5V - 5.5V)

Oscillator Period (ATtiny25/45/85, V_CC= 4.5V - 5.5V)

SCK Pulse Width High

4

250

0

1/t_CLCL

t_CLCL

1/t_CLCL

t_CLCL

10

20

MHz

ns

100

0

MHz

ns

50

t_SHSL

2 t_CLCL*

ns

t_SLSH

SCK Pulse Width Low

2 t_CLCL

ns

*

t_OVSH

t_SHOX

Note:

MOSI Setup to SCK High

t_CLCL

2 t_CLCL

ns

MOSI Hold after SCK High

ns

1. 2 t_CLCLfor f_ck< 12 MHz, 3 t_CLCLfor f_ck>= 12 MHz

174

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

21.9 High-voltage Serial Programming Characteristics

Figure 21-6. High-voltage Serial Programming Timing

SDI (PB0), SII (PB1)

t_IVSH

t_SLSH

t_SHIX

SCI (PB3)

t_SHSL

SDO (PB2)

t_SHOV

Table 21-11. High-voltage Serial Programming Characteristics T_A= 25°C ± 10%, V_CC= 5.0V ±

10% (Unless otherwise noted)

Symbol

t_SHSL

Parameter

Min

125

50

Typ

Max

Units

ns

SCI (PB3) Pulse Width High

t_SLSH

SCI (PB3) Pulse Width Low

ns

t_IVSH

SDI (PB0), SII (PB1) Valid to SCI (PB3) High

SDI (PB0), SII (PB1) Hold after SCI (PB3) High

SCI (PB3) High to SDO (PB2) Valid

Wait after Instr. 3 for Write Fuse Bits

ns

t_SHIX

50

ns

t_SHOV

16

ns

t_{WLWH_PFB}

2.5

ms

175

2586K–AVR–01/08

22. Typical Characteristics

The data contained in this section is largely based on simulations and characterization of similar

devices in the same process and design methods. Thus, the data should be treated as indica-

tions of how the part will behave.

The following charts show typical behavior. These figures are not tested during manufacturing.

All current consumption measurements are performed with all I/O pins configured as inputs and

with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as clock

source.

The power consumption in Power-down mode is independent of clock selection.

The current consumption is a function of several factors such as: operating voltage, operating

frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient tempera-

ture. The dominating factors are operating voltage and frequency.

The current drawn from capacitive loaded pins may be estimated (for one pin) as C_L*V_CC*f where

C_L= load capacitance, V_CC= operating voltage and f = average switching frequency of I/O pin.

The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to

function properly at frequencies higher than the ordering code indicates.

The difference between current consumption in Power-down mode with Watchdog Timer

enabled and Power-down mode with Watchdog Timer disabled represents the differential cur-

rent drawn by the Watchdog Timer.

22.1 Active Supply Current

Figure 22-1. Active Supply Current vs. Low frequency (0.1 - 1.0 MHz)

ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY

0.1 -1.0 MHz

1,2

5.5 V

1

0,8

0,6

0,4

0,2

0

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

1

Frequency (MHz)

176

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

Figure 22-2. Active Supply Current vs. Frequency (1 - 20 MHz)

ACTIVE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

14

12

10

8

5.5 V

5.0 V

4.5 V

4.0V

6

3.3V

4

2.7V

2

1.8V

0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

Figure 22-3. Active Supply Current vs. V_CC(Internal RC oscillator, 8 MHz)

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 8 MHz

7

-40 ˚C

6

5

4

3

2

1

0

25 ˚C

85 ˚C

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

177

2586K–AVR–01/08

Figure 22-4. Active Supply Current vs. V_CC(Internal RC Oscillator, 1 MHz)

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 1 MHz

1,6

25 ˚C

85 ˚C

-40 ˚C

1,4

1,2

1

0,8

0,6

0,4

0,2

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

Figure 22-5. Active Supply Current vs. V_CC(Internal RC Oscillator, 128 kHz)

ACTIVE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 128 KHz

0,25

-40 ˚C

25 ˚C

85 ˚C

0,2

0,15

0,1

0,05

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

178

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

22.2 Idle Supply Current

Figure 22-6. Idle Supply Current vs. low Frequency (0.1 - 1.0 MHz)

IDLE SUPPLY CURRENT vs. LOW FREQUENCY

0.1 - 1.0 MHz

0,25

0,2

0,15

0,1

0,05

0

5.5 V

5.0 V

4.5 V

4.0 V

3.3 V

2.7 V

1.8 V

0

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

1

Frequency (MHz)

Figure 22-7. Idle Supply Current vs. Frequency (1 - 20 MHz)

IDLE SUPPLY CURRENT vs. FREQUENCY

1 - 20 MHz

4

3,5

3

5.5 V

5.0 V

4.5 V

2,5

2

4.0V

1,5

1

3.3V

2.7V

0,5

0

1.8V

0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

179

2586K–AVR–01/08

Figure 22-8. Idle Supply Current vs. V_CC(Internal RC Oscillator, 8 MHz)I

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 8 MHz

1,8

85 ˚C

25 ˚C

-40 ˚C

1,6

1,4

1,2

1

0,8

0,6

0,4

0,2

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

Figure 22-9. Idle Supply Current vs. V_CC(Internal RC Oscilllator, 1 MHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 1 MHz

0,5

85 ˚C

0,45

0,4

25 ˚C

-40 ˚C

0,35

0,3

0,25

0,2

0,15

0,1

0,05

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

180

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

Figure 22-10. Idle Supply Current vs. V_CC(Internal RC Oscillator, 128 kHz)

IDLE SUPPLY CURRENT vs. V_CC

INTERNAL RC OSCILLATOR, 128 kHz

0,1

0,09

0,08

0,07

0,06

0,05

0,04

0,03

0,02

0,01

0

-40 ˚C

25 ˚C

85 ˚C

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

22.3 Supply Current of I/O modules

The tables and formulas below can be used to calculate the additional current consumption for

the different I/O modules in Active and Idle mode. The enabling or disabling of the I/O modules

are controlled by the Power Reduction Register. See “PRR – Power Reduction Register” on

page 39 for details.

Table 22-1. Additional Current Consumption for the different I/O modules (absolute values)

PRR bit

Typical numbers

V_CC= 3V, f = 4MHz

300 uA

V_CC= 2V, f = 1MHz

V_CC= 5V, f = 8MHz

1100 uA

PRTIM1

PRTIM0

PRUSI

45 uA

5 uA

30 uA

110 uA

5 uA

25 uA

100 uA

PRADC

15 uA

85 uA

340 uA

Table 22-2. Additional Current Consumption (percentage) in Active and Idle mode

Additional Current consumption

compared to Active with external clock

(see Figure 22-1 and Figure 22-2)

Additional Current consumption

compared to Idle with external clock

(see Figure 22-6 and Figure 22-7)

PRR bit

PRTIM1

PRTIM0

PRUSI

20 %

2 %

5 %

80 %

10 %

25 %

PRADC

181

2586K–AVR–01/08

It is possible to calculate the typical current consumption based on the numbers from Table 22-2

for other V_CCand frequency settings that listed in Table 22-1.

22.3.1

Example

Calculate the expected current consumption in idle mode with USI, TIMER0, and ADC enabled

at V_CC= 2.0V and f = 1MHz. From Table 22-2 on page 181, third column, we see that we need to

add 10% for the USI, 25% for the ADC, and 10% for the TIMER0 module. Reading from Figure

22-9, we find that the idle current consumption is ~0,18mA at V_CC= 2.0V and f = 1MHz. The total

current consumption in idle mode with USI, TIMER0, and ADC enabled, gives:

I

= 0,18mA × (1 + 0,1 + 0,25 + 0,1) ≈ 0,261mA

CC

22.4 Power-down Supply Current

Figure 22-11. Power-down Supply Current vs. V_CC(Watchdog Timer Disabled)

POWER-DOWN SUPPLY CURRENT vs. V_CC

WATCHDOG TIMER DISABLED

1.4

85 ˚C

1.2

1

0.8

0.6

0.4

0.2

0

-40 ˚C

25 ˚C

1.5

2

2.5

3

3.5

_CC(V)

4

4.5

5

5.5

V

182

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

Figure 22-12. Power-down Supply Current vs. V_CC(Watchdog Timer Enabled)

POWER-DOWN SUPPLY CURRENT vs. V_CC

WATCHDOG TIMER ENABLED

14

12

10

8

-40 ˚C

25 ˚C

85 ˚C

6

4

2

0

1.5

2

2.5

3

3.5

4

4.5

5

5.5

V_CC(V)

22.5 Pin Pull-up

Figure 22-13. I/O Pin Pull-up Resistor Current vs. Input Voltage (V_CC= 1.8V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_CC= 1.8V

60

50

40

30

20

25 ˚C

85 ˚C

-40 ˚C

10

0

0,2

0,4

0,6

0,8

1

1,2

1,4

1,6

1,8

2

V_OP(V)

183

2586K–AVR–01/08

Figure 22-14. I/O Pin Pull-up Resistor Current vs. Input Voltage (V_CC= 2.7V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_CC= 2.7V

80

70

60

50

40

30

20

25 ˚C

85 ˚C

10

0

-40 ˚C

0

0,5

1

1,5

2

2,5

3

V_OP(V)

Figure 22-15. I/O Pin Pull-up Resistor Current vs. Input Voltage (V_CC= 5V)

I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE

V_CC= 5V

160

140

120

100

80

60

25 ˚C

40

85 ˚C

20

-40 ˚C

0

1

2

3

4

5

6

V_OP(V)

184

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

Figure 22-16. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V_CC= 1.8V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

V_CC= 1.8V

40

35

30

25

20

15

10

5

25 ˚C

-40 ˚C

85 ˚C

0

0,2

0,4

0,6

0,8

1

1,2

1,4

1,6

1,8

2

V_RESET(V)

Figure 22-17. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V_CC= 2.7V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

V_CC=2.7V

60

50

40

30

20

25 ˚C

10

-40 ˚C

85 ˚C

0

0,5

1

1,5

2

2,5

3

V_RESET(V)

185

2586K–AVR–01/08

Figure 22-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage (V_CC= 5V)

RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE

V_CC= 5V

120

100

80

60

40

25 ˚C

20

-40 ˚C

85 ˚C

0

1

2

3

4

5

6

V_RESET(V)

22.6 Pin Driver Strength

Figure 22-19. I/O Pin Output Voltage vs. Sink Current (V_CC= 3V)

I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

V_CC= 3V

1,2

1

85

0,8

0,6

0,4

0,2

0

25

-40

0

5

10

15

20

25

I_OL(mA)

186

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

Figure 22-20. I/O Pin Output Voltage vs. Sink Current (V_CC= 5V)

I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

V_CC= 5V

0,6

0,5

0,4

0,3

0,2

0,1

0

85

25

-40

0

5

10

15

20

25

I_OL(mA)

Figure 22-21. I/O Pin Output Voltage vs. Source Current (V_CC= 3V)

I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

V_CC= 3V

3,5

3

-40

2,5

25

2

85

1,5

1

0,5

0

5

10

15

20

25

I_OH(mA)

187

2586K–AVR–01/08

Figure 22-22. I/O Pin Output Voltage vs. Source Current (V_CC= 5V)

I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

V_CC= 5V

5,1

5

4,9

4,8

4,7

4,6

-40

25

4,5

85

4,4

0

5

10

15

20

25

I_OH(mA)

Figure 22-23. Reset Pin Output Voltage vs. Sink Current (V_CC= 3V)

RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

V_CC= 3V

1.5

85 °C

1

0 °C

-45 °C

0.5

0

0.5

1

1.5

2

2.5

3

I_OL(mA)

188

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

Figure 22-24. Reset Pin Output Voltage vs. Sink Current (V_CC= 5V)

RESET AS I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT

V

_CC= 5V

1

0.8

0.6

0.4

0.2

0

85 °C

0 °C

-45 °C

0

0.5

1

1.5

2

2.5

3

I_OL(mA)

Figure 22-25. Reset Pin Output Voltage vs. Source Current (V_CC= 3V)

RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

V_CC= 3V

3.5

3

2.5

2

1.5

1

-45 °C

25 °C

85 °C

0.5

0

0.5

1

1.5

2

I_OH(mA)

189

2586K–AVR–01/08

Figure 22-26. Reset Pin Output Voltage vs. Source Current (V_CC= 5V)

RESET AS I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT

V_CC= 5V

5

4.5

4

3.5

3

-45 °C

25 °C

85 °C

2.5

0

0.5

1

1.5

2

I_OH(mA)

22.7 Pin Threshold and Hysteresis

Figure 22-27. I/O Pin Input Threshold Voltage vs. V_CC(V_IH, IO Pin Read as ‘1’)

I/O PIN INPUT THRESHOLD VOLTAGE vs. V_CC

VIH, IO PIN READ AS '1'

3

-40 ˚C

85 ˚C

25 ˚C

2,5

2

1,5

1

0,5

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

190

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

Figure 22-28. I/O Pin Input Threshold Voltage vs. V_CC(V_IL, IO Pin Read as ‘0’)

I/O PIN INPUT THRESHOLD VOLTAGE vs. V_CC

VIL, IO PIN READ AS '0'

3

2,5

2

85 ˚C

25 ˚C

-40 ˚C

1,5

1

0,5

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

Figure 22-29. I/O Pin Input Hysteresis vs. V_CC

I/O PIN INPUT HYSTERESIS vs. V_CC

0,6

0,5

0,4

0,3

0,2

0,1

0

-40 ˚C

85 ˚C

25 ˚C

1,5

2

2,5

3

3,5

_CC(V)

4

4,5

5

5,5

V

191

2586K–AVR–01/08

Figure 22-30. Reset Input Threshold Voltage vs. V_CC(V_IH, IO Pin Read as ‘1’)

RESET INPUT THRESHOLD VOLTAGE vs. VCC

VIH, IO PIN READ AS '1'

2,5

2

85 °C

25 °C

-40 °C

1,5

1

0,5

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

VCC (V)

Figure 22-31. Reset Input Threshold Voltage vs, V_CC(V_IL, IO Pin Read as ‘0’)

RESET INPUT THRESHOLD VOLTAGE vs. VCC

VIL, IO PIN READ AS '0'

2,5

2

85 °C

25 °C

-40 °C

1,5

1

0,5

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

VCC (V)

192

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

Figure 22-32. Reset Pin Input Hysteresis vs. V_CC

RESET PIN INPUT HYSTERESIS vs. VCC

0,5

0,45

0,4

0,35

0,3

0,25

0,2

0,15

0,1

-40 °C

25 °C

85 °C

0,05

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

VCC (V)

22.8 BOD Threshold and Analog Comparator Offset

Figure 22-33. BOD Threshold vs. Temperature (BOD Level is 4.3V)

BOD THRESHOLDS vs. TEMPERATURE

4,4

4,38

4,36

4,34

4,32

4,3

Rising VCC

Falling VCC

4,28

4,26

-50 -40 -30 -20 -10

0

10

20

30

40

50

60

70

80

90

100

Temperature (C)

193

2586K–AVR–01/08

Figure 22-34. BOD Threshold vs. Temperature (BOD Level is 2.7V)

BOD THRESHOLDS vs. TEMPERATURE

2,8

2,78

2,76

2,74

2,72

2,7

Rising VCC

Falling VCC

2,68

-50 -40 -30 -20 -10

0

10

20

30

40

50

60

70

80

90

100

Temperature (C)

Figure 22-35. BOD Threshold vs. Temperature (BOD Level is 1.8V)

BOD THRESHOLDS vs. TEMPERATURE

1,85

1,845

1,84

Rising VCC

1,835

1,83

1,825

1,82

1,815

1,81

Falling VCC

1,805

1,8

1,795

-50 -40 -30 -20 -10

0

10

20

30

40

50

60

70

80

90

100

Temperature (C)

194

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

22.9 Internal Oscillator Speed

Figure 22-36. Watchdog Oscillator Frequency vs. V_CC

WATCHDOG OSCILLATOR FREQUENCY vs. V_CC

0,128

0,126

0,124

0,122

0,12

-40 ˚C

25 ˚C

0,118

0,116

0,114

0,112

85 ˚C

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

Figure 22-37. Watchdog Oscillator Frequency vs. Temperature

WATCHDOG OSCILLATOR FREQUENCY vs. TEMPERATURE

0,12

0,118

0,116

0,114

0,112

0,11

1.8 V

2.7 V

3.3 V

4.0 V

5.5 V

0,108

-40 -30 -20 -10

0

10

20

30

40

50

60

70

80

90 100

Temperature

195

2586K–AVR–01/08

Figure 22-38. Calibrated 8 MHz RC Oscillator Frequency vs. V_CC

CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. V_CC

8,2

85 ˚C

25 ˚C

8,1

8

7,9

7,8

7,7

7,6

7,5

-40 ˚C

1,5

2

2,5

3

3,5

_CC(V)

4

4,5

5

5,5

V

Figure 22-39. Calibrated 8 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

8,15

3.0 V

5.0 V

8,1

8,05

8

7,95

7,9

7,85

7,8

7,75

7,7

-60

-40

-20

0

20

40

60

80

100

Temperature

196

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

Figure 22-40. Calibrated 8 MHz RC Oscillator Frequency vs. OSCCAL Value

CALIBRATED 8 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

18

85 ˚C

16

14

12

10

8

25 ˚C

-40 ˚C

6

4

2

0

16

32

48

64

80

96 112 128 144 160 176 192 208 224 240

OSCCAL (X1)

Figure 22-41. Calibrated 1.6 MHz RC Oscillator Frequency vs. V_CC

CALIBRATED 1.6 MHz RC OSCILLATOR FREQUENCY vs. V_CC

1,65

1,6

85 ˚C

25 ˚C

1,55

1,5

-40 ˚C

1,45

1,4

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

197

2586K–AVR–01/08

Figure 22-42. Calibrated 1.6 MHz RC Oscillator Frequency vs. Temperature

CALIBRATED 1.6MHz RC OSCILLATOR FREQUENCY vs. TEMPERATURE

1,64

3.0 V

1,62

5.0 V

1,6

1,58

1,56

1,54

1,52

1,5

-60

-40

-20

0

20

40

60

80

100

Temperature

Figure 22-43. Calibrated 1.6 MHz RC Oscillator Frequency vs. OSCCAL Value

CALIBRATED 1.6 MHz RC OSCILLATOR FREQUENCY vs. OSCCAL VALUE

4,5

85 ˚C

4

3,5

3

25 ˚C

-40 ˚C

2,5

2

1,5

1

0,5

0

16

32

48

64

80

96 112 128 144 160 176 192 208 224 240

OSCCAL (X1)

198

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

22.10 Current Consumption of Peripheral Units

Figure 22-44. Brownout Detector Current vs. V_CC

BROWNOUT DETECTOR CURRENT vs. VCC

30

25

20

15

10

5

85 °C

25 °C

-40 °C

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

VCC (V)

Figure 22-45. ADC Current vs. V_CC(AREF = AV_CC

)

ADC CURRENT vs. VCC

AREF = AVCC

250

200

150

100

50

85 °C

25 °C

-40 °C

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

VCC (V)

199

2586K–AVR–01/08

Figure 22-46. Analog Comparator Current vs. V_CC

ANALOG COMPARATOR CURRENT vs. VCC

50

45

40

35

30

25

20

15

10

5

85 °C

25 °C

-40 °C

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

VCC (V)

Figure 22-47. Programming Current vs. V_CC

PROGRAMMING CURRENT vs. Vcc

Ext Clk

12

10

8

-40 °C

25 °C

6

85 °C

4

2

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

VCC (V)

200

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

22.11 Current Consumption in Reset and Reset Pulsewidth

Figure 22-48. Reset Supply Current vs, V_CC(0.1 - 1.0 MHz, Excluding Current Through The

Reset Pull-up)

RESET SUPPLY CURRENT vs. V_CC

0.1 - 1.0 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP

0,16

5.5 V

0,14

5.0 V

0,12

4.5 V

0,1

4.0 V

0,08

3.3 V

0,06

2.7 V

0,04

1.8 V

0,02

0

0,1

0,2

0,3

0,4

0,5

0,6

0,7

0,8

0,9

1

Frequency (MHz)

Figure 22-49. Reset Supply Current vs. V_CC(1 - 20 MHz, Excluding Current Through The Reset

Pull-up)

RESET SUPPLY CURRENT vs. V_CC

1 - 20 MHz, EXCLUDING CURRENT THROUGH THE RESET PULLUP

2,5

5.5 V

5.0 V

2

4.5 V

1,5

4.0V

1

3.3V

0,5

2.7V

1.8V

0

2

4

6

8

10

12

14

16

18

20

Frequency (MHz)

201

2586K–AVR–01/08

Figure 22-50. Minimum Reset Pulse Width vs, V_CC

MINIMUM RESET PULSE WIDTH vs. V_CC

2500

2000

1500

1000

500

85 ˚C

25 ˚C

-40 ˚C

0

1,5

2

2,5

3

3,5

4

4,5

5

5,5

V_CC(V)

202

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

23. Register Summary

Address

Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Page

0x3F

0x3E

0x3D

0x3C

0x3B

0x3A

0x39

0x38

0x37

0x36

0x35

0x34

0x33

0x32

0x31

0x30

0x2F

0x2E

0x2D

0x2C

0x2B

0x2A

0x29

0x28

0x27

0x26

0x25

0x24

0x23

0x22

0x21

0x20

0x1F

0x1E

0x1D

0x1C

0x1B

0x1A

0x19

0x18

0x17

0x16

0x15

0x14

0x13

0x12

0x11

0x10

0x0F

0x0E

0x0D

0x0C

0x0B

0x0A

0x09

0x08

0x07

0x06

0x05

0x04

0x03

0x02

0x01

0x00

SREG

I

–

T

–

H

–

S

–

V

–

N

–

Z

C

page 8

page 11

SPH

SP9

SP1

SP8

SP0

SPL

SP7

SP6

SP5

SP4

SP3

SP2

Reserved

GIMSK

GIFR

–

INT0

INTF0

OCIE1A

OCF1A

–

PCIE

PCIF

–

page 53

–

TIMSK

OCIE1B

OCF1B

RSIG

OCIE0A

OCF0A

CTPB

OCIE0B

OCF0B

RFLB

TOIE1

TOV1

PGWRT

TOIE0

TOV0

PGERS

–

page 84/page 106

page 84

TIFR

SPMCSR

Reserved

MCUCR

MCUSR

TCCR0B

TCNT0

OSCCAL

TCCR1

TCNT1

OCR1A

OCR1C

GTCCR

OCR1B

TCCR0A

OCR0A

OCR0B

PLLCSR

CLKPR

DT1A

SPMEN

page 149

BODS

–

PUD

–

SE

–

SM1

SM0

BODSE

BORF

CS02

ISC01

EXTRF

CS01

ISC00

PORF

CS00

page 38,page 52, page 66,

page 47,

–

WDRF

WGM02

FOC0A

FOC0B

–

page 82

Timer/Counter0

page 83

Oscillator Calibration Register

page 32

CTC1

PWM1A

COM1A1

COM1A0

CS13

CS12

CS11

CS10

page 92, page 103

page 94, page 105

Timer/Counter1

Timer/Counter1 Output Compare Register A

Timer/Counter1 Output Compare Register C

page 95, page 106

page 80, page 93, page

TSM

PWM1B

COM1B1

Timer/Counter1 Output Compare Register B

COM0B1 COM0B0

COM1B0

FOC1B

FOC1A

PSR1

PSR0

page 95

page 80

COM0A1

COM0A0

–

WGM01

WGM00

Timer/Counter0 – Output Compare Register A

Timer/Counter0 – Output Compare Register B

page 83

page 84

LSM

CLKPCE

DT1AH3

DT1BH3

-

–

PCKE

CLKPS2

DT1AL2

DT1BL2

-

PLLE

PLOCK

CLKPS0

DT1AL0

DT1BL0

DTPS10

page 97, page 107

page 33

–

CLKPS3

DT1AL3

DT1BL3

-

CLKPS1

DT1AL1

DT1BL1

DTPS11

DT1AH2

DT1BH2

-

DT1AH1

DT1BH1

-

DT1AH0

DT1BH0

-

page 110

page 109

page 144

page 47

DT1B

DTPS1

DWDR

DWDR[7:0]

WDTCR

PRR

WDIF

–

WDIE

WDP3

WDCE

WDE

WDP2

WDP1

PRUSI

WDP0

PRADC

EEAR8

EEAR0

PRTIM1

PRTIM0

page 37

EEARH

EEARL

EEDR

page 20

EEAR7

–

EEAR6

–

EEAR5

EEPM1

EEAR4

EEAR3

EEAR2

EEMPE

EEAR1

EEPE

page 20

EEPROM Data Register

page 20

EECR

EEPM0

EERIE

EERE

page 21

Reserved

PORTB

DDRB

–

PORTB5

DDB5

PORTB4

DDB4

PORTB3

DDB3

PORTB2

DDB2

PORTB1

DDB1

PORTB0

DDB0

page 66

PINB

PINB5

PINB4

PINB3

PINB2

PINB1

PINB0

page 66

PCMSK

DIDR0

PCINT5

ADC0D

PCINT4

ADC2D

PCINT3

ADC3D

PCINT2

ADC1D

PCINT1

AIN1D

PCINT0

AIN0D

page 54

page 125, page 142

page 10

GPIOR2

GPIOR1

GPIOR0

USIBR

General Purpose I/O Register 2

General Purpose I/O Register 1

General Purpose I/O Register 0

USI Buffer Register

page 10

page 118

page 119

page 120

USIDR

USI Data Register

USISR

USISIF

USISIE

USIOIF

USIOIE

USIPF

USIDC

USICNT3

USICS1

USICNT2

USICS0

USICNT1

USICLK

USICNT0

USITC

USICR

USIWM1

USIWM0

Reserved

ACSR

–

ACD

REFS1

ADEN

ACBG

REFS0

ADSC

ACO

ACI

REFS2

ADIF

ACIE

MUX3

ADIE

–

ACIS1

MUX1

ADPS1

ACIS0

MUX0

ADPS0

page 124

page 138

ADMUX

ADCSRA

ADCH

ADLAR

ADATE

MUX2

ADPS2

page 140

ADC Data Register High Byte

ADC Data Register Low Byte

page 141

ADCL

page 141

ADCSRB

Reserved

BIN

ACME

IPR

–

ADTS2

ADTS1

ADTS0

page 124, page 141

–

203

2586K–AVR–01/08

Note:

1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses

should never be written.

2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these

registers, the value of single bits can be checked by using the SBIS and SBIC instructions.

3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI

instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The

CBI and SBI instructions work with registers 0x00 to 0x1F only.

204

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

24. Instruction Set Summary

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ARITHMETIC AND LOGIC INSTRUCTIONS

ADD

ADC

ADIW

SUB

SUBI

SBC

SBCI

SBIW

AND

ANDI

OR

Rd, Rr

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rdl,K

Rd, Rr

Rd, K

Rd, Rr

Rd, K

Rd, Rr

Rd

Add two Registers

Rd ← Rd + Rr

Z,C,N,V,H

Z,C,N,V,S

Z,C,N,V,H

Z,C,N,V,S

Z,N,V

1

2

1

2

1

Add with Carry two Registers

Add Immediate to Word

Subtract two Registers

Subtract Constant from Register

Subtract with Carry two Registers

Subtract with Carry Constant from Reg.

Subtract Immediate from Word

Logical AND Registers

Logical AND Register and Constant

Logical OR Registers

Rd ← Rd + Rr + C

Rdh:Rdl ← Rdh:Rdl + K

Rd ← Rd - Rr

Rd ← Rd - K

Rd ← Rd - Rr - C

Rd ← Rd - K - C

Rdh:Rdl ← Rdh:Rdl - K

Rd ← Rd • Rr

Rd ← Rd • K

Z,N,V

Rd ← Rd v Rr

Z,N,V

ORI

Logical OR Register and Constant

Exclusive OR Registers

One’s Complement

Rd ← Rd v K

Z,N,V

EOR

COM

NEG

SBR

CBR

INC

Rd ← Rd ⊕ Rr

Rd ← 0xFF − Rd

Rd ← 0x00 − Rd

Rd ← Rd v K

Z,N,V

Z,C,N,V

Z,C,N,V,H

Z,N,V

Rd

Two’s Complement

Rd,K

Rd

Set Bit(s) in Register

Clear Bit(s) in Register

Increment

Rd ← Rd • (0xFF - K)

Rd ← Rd + 1

Z,N,V

DEC

TST

Rd

Decrement

Rd ← Rd − 1

Z,N,V

Rd

Test for Zero or Minus

Clear Register

Rd ← Rd • Rd

Rd ← Rd ⊕ Rd

Rd ← 0xFF

Z,N,V

CLR

SER

Rd

Z,N,V

Rd

Set Register

None

BRANCH INSTRUCTIONS

RJMP

IJMP

k

Relative Jump

PC ← PC + k + 1

None

I

2

Indirect Jump to (Z)

PC ← Z

RCALL

ICALL

RET

Relative Subroutine Call

Indirect Call to (Z)

PC ← PC + k + 1

3

PC ← Z

3

Subroutine Return

PC ← STACK

4

RETI

Interrupt Return

PC ← STACK

4

CPSE

CP

Rd,Rr

Compare, Skip if Equal

Compare

if (Rd = Rr) PC ← PC + 2 or 3

Rd − Rr

None

Z, N,V,C,H

None

1/2/3

1

Rd,Rr

CPC

Rd,Rr

Compare with Carry

Rd − Rr − C

1

CPI

Rd,K

Compare Register with Immediate

Skip if Bit in Register Cleared

Skip if Bit in Register is Set

Skip if Bit in I/O Register Cleared

Skip if Bit in I/O Register is Set

Branch if Status Flag Set

Branch if Status Flag Cleared

Branch if Equal

Rd − K

1

SBRC

SBRS

SBIC

Rr, b

if (Rr(b)=0) PC ← PC + 2 or 3

if (Rr(b)=1) PC ← PC + 2 or 3

if (P(b)=0) PC ← PC + 2 or 3

if (P(b)=1) PC ← PC + 2 or 3

if (SREG(s) = 1) then PC←PC+k + 1

if (SREG(s) = 0) then PC←PC+k + 1

if (Z = 1) then PC ← PC + k + 1

if (Z = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (C = 0) then PC ← PC + k + 1

if (C = 1) then PC ← PC + k + 1

if (N = 1) then PC ← PC + k + 1

if (N = 0) then PC ← PC + k + 1

if (N ⊕ V= 0) then PC ← PC + k + 1

if (N ⊕ V= 1) then PC ← PC + k + 1

if (H = 1) then PC ← PC + k + 1

if (H = 0) then PC ← PC + k + 1

if (T = 1) then PC ← PC + k + 1

if (T = 0) then PC ← PC + k + 1

if (V = 1) then PC ← PC + k + 1

if (V = 0) then PC ← PC + k + 1

if ( I = 1) then PC ← PC + k + 1

if ( I = 0) then PC ← PC + k + 1

1/2/3

1/2

Rr, b

P, b

s, k

k

SBIS

BRBS

BRBC

BREQ

BRNE

BRCS

BRCC

BRSH

BRLO

BRMI

BRPL

BRGE

BRLT

BRHS

BRHC

BRTS

BRTC

BRVS

BRVC

BRIE

BRID

k

Branch if Not Equal

k

Branch if Carry Set

k

Branch if Carry Cleared

Branch if Same or Higher

Branch if Lower

k

Branch if Minus

k

Branch if Plus

k

Branch if Greater or Equal, Signed

Branch if Less Than Zero, Signed

Branch if Half Carry Flag Set

Branch if Half Carry Flag Cleared

Branch if T Flag Set

k

Branch if T Flag Cleared

Branch if Overflow Flag is Set

Branch if Overflow Flag is Cleared

Branch if Interrupt Enabled

Branch if Interrupt Disabled

k

BIT AND BIT-TEST INSTRUCTIONS

SBI

P,b

Rd

Set Bit in I/O Register

Clear Bit in I/O Register

Logical Shift Left

I/O(P,b) ← 1

None

2

1

CBI

LSL

LSR

ROL

I/O(P,b) ← 0

None

Rd(n+1) ← Rd(n), Rd(0) ← 0

Rd(n) ← Rd(n+1), Rd(7) ← 0

Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)

Z,C,N,V

Logical Shift Right

Rotate Left Through Carry

205

2586K–AVR–01/08

Mnemonics

Operands

Description

Operation

Flags

#Clocks

ROR

Rd

Rotate Right Through Carry

Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)

Z,C,N,V

1

ASR

SWAP

BSET

BCLR

BST

BLD

SEC

CLC

SEN

CLN

SEZ

CLZ

SEI

Rd

s

Arithmetic Shift Right

Swap Nibbles

Rd(n) ← Rd(n+1), n=0..6

Z,C,N,V

Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)

None

Flag Set

SREG(s) ← 1

SREG(s) ← 0

T ← Rr(b)

Rd(b) ← T

C ← 1

SREG(s)

s

Flag Clear

SREG(s)

Rr, b

Rd, b

Bit Store from Register to T

Bit load from T to Register

Set Carry

T

None

C

N

Z

Clear Carry

C ← 0

Set Negative Flag

N ← 1

Clear Negative Flag

Set Zero Flag

N ← 0

Z ← 1

Clear Zero Flag

Z ← 0

Z

Global Interrupt Enable

Global Interrupt Disable

Set Signed Test Flag

Clear Signed Test Flag

Set Twos Complement Overflow.

Clear Twos Complement Overflow

Set T in SREG

I ← 1

I

CLI

I ← 0

I

SES

CLS

SEV

CLV

SET

CLT

SEH

CLH

S ← 1

S

V

T

S ← 0

V ← 1

V ← 0

T ← 1

Clear T in SREG

T ← 0

T

Set Half Carry Flag in SREG

Clear Half Carry Flag in SREG

H ← 1

H

H ← 0

DATA TRANSFER INSTRUCTIONS

MOV

MOVW

LDI

LD

Rd, Rr

Rd, K

Move Between Registers

Copy Register Word

Rd ← Rr

None

1

2

3

Rd+1:Rd ← Rr+1:Rr

Load Immediate

Rd ← K

Rd, X

Load Indirect

Rd ← (X)

LD

Rd, X+

Rd, - X

Rd, Y

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect

Rd ← (X), X ← X + 1

X ← X - 1, Rd ← (X)

Rd ← (Y)

LD

Rd, Y+

Rd, - Y

Rd,Y+q

Rd, Z

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Indirect

Rd ← (Y), Y ← Y + 1

Y ← Y - 1, Rd ← (Y)

Rd ← (Y + q)

Rd ← (Z)

LD

LDD

LD

Rd, Z+

Rd, -Z

Rd, Z+q

Rd, k

Load Indirect and Post-Inc.

Load Indirect and Pre-Dec.

Load Indirect with Displacement

Load Direct from SRAM

Store Indirect

Rd ← (Z), Z ← Z+1

Z ← Z - 1, Rd ← (Z)

Rd ← (Z + q)

Rd ← (k)

LD

LDD

LDS

ST

X, Rr

(X) ← Rr

ST

X+, Rr

- X, Rr

Y, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect

(X) ← Rr, X ← X + 1

X ← X - 1, (X) ← Rr

(Y) ← Rr

ST

Y+, Rr

- Y, Rr

Y+q,Rr

Z, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Indirect

(Y) ← Rr, Y ← Y + 1

Y ← Y - 1, (Y) ← Rr

(Y + q) ← Rr

ST

STD

ST

(Z) ← Rr

ST

Z+, Rr

-Z, Rr

Z+q,Rr

k, Rr

Store Indirect and Post-Inc.

Store Indirect and Pre-Dec.

Store Indirect with Displacement

Store Direct to SRAM

Load Program Memory

Load Program Memory and Post-Inc

Store Program Memory

In Port

(Z) ← Rr, Z ← Z + 1

Z ← Z - 1, (Z) ← Rr

(Z + q) ← Rr

ST

STD

STS

LPM

SPM

IN

(k) ← Rr

R0 ← (Z)

Rd, Z

Rd ← (Z)

Rd, Z+

Rd ← (Z), Z ← Z+1

(z) ← R1:R0

Rd, P

P, Rr

Rr

Rd ← P

1

2

OUT

PUSH

POP

Out Port

P ← Rr

Push Register on Stack

Pop Register from Stack

STACK ← Rr

Rd ← STACK

Rd

MCU CONTROL INSTRUCTIONS

NOP

No Operation

Sleep

None

1

SLEEP

WDR

(see specific descr. for Sleep function)

(see specific descr. for WDR/Timer)

For On-chip Debug Only

Watchdog Reset

Break

1

BREAK

N/A

206

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

25. Ordering Information

25.1 ATtiny25

Speed (MHz)⁽³⁾

Power Supply

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATtiny25V-10PU

ATtiny25V-10SU

ATtiny25V-10SSU

ATtiny25V-10MU

8P3

8S2

Industrial

(-40°C to 85°C)

10

1.8 - 5.5V

2.7 - 5.5V

S8S1

20M1

ATtiny25-20PU

ATtiny25-20SU

ATtiny25-20SSU

ATtiny25-20MU

8P3

8S2

Industrial

(-40°C to 85°C)

20

S8S1

20M1

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V_CC,see Figure 21.3 on page 168

Package Type

8P3

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S2

8-lead, 0.200" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)

8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC)

20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

S8S1

20M1

207

2586K–AVR–01/08

25.2 ATtiny45

Speed (MHz)⁽³⁾

Power Supply

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATtiny45V-10PU

ATtiny45V-10SU

ATtiny45V-10MU

8P3

Industrial

(-40°C to 85°C)

10

20

1.8 - 5.5V

8S2

20M1

ATtiny45-20PU

ATtiny45-20SU

ATtiny45-20MU

8P3

Industrial

(-40°C to 85°C)

2.7 - 5.5V

8S2

20M1

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V_CC,see Figure 21.3 on page 168

Package Type

8P3

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S2

8-lead, 0.200" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)

20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

20M1

208

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

25.3 ATtiny85

Speed (MHz)⁽³⁾

Power Supply

Ordering Code⁽²⁾

Package⁽¹⁾

Operational Range

ATtiny85V-10PU

ATtiny85V-10SU

ATtiny85V-10MU

8P3

Industrial

(-40°C to 85°C)

10

20

1.8 - 5.5V

8S2

20M1

ATtiny85-20PU

ATtiny85-20SU

ATtiny85-20MU

8P3

Industrial

(-40°C to 85°C)

2.7 - 5.5V

8S2

20M1

Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information

and minimum quantities.

2. Pb-free packaging complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also

Halide free and fully Green.

3. For Speed vs. V_CC,see Figure 21.3 on page 168

Package Type

8P3

8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)

8S2

8-lead, 0.200" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)

20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)

20M1

209

2586K–AVR–01/08

26. Packaging Information

26.1 8P3

E

1

E1

N

Top View

c

eA

End View

COMMON DIMENSIONS

(Unit of Measure = inches)

D

e

MIN

MAX

NOM

NOTE

SYMBOL

D1

A2 A

A

0.210

0.195

0.022

0.070

0.045

0.014

0.400

2

A2

b

0.115

0.014

0.045

0.030

0.008

0.355

0.005

0.300

0.240

0.130

0.018

0.060

0.039

0.010

0.365

5

6

b2

b3

c

D

3

4

3

b2

L

D1

E

b3

4 PLCS

0.310

0.250

0.325

0.280

b

E1

e

0.100 BSC

0.300 BSC

0.130

Side View

eA

L

4

2

0.115

0.150

Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.

2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.

3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.

4. E and eA measured with the leads constrained to be perpendicular to datum.

5. Pointed or rounded lead tips are preferred to ease insertion.

6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).

01/09/02

TITLE

DRAWING NO.

REV.

2325 Orchard Parkway

San Jose, CA 95131

8P3, 8-lead, 0.300" Wide Body, Plastic Dual

In-line Package (PDIP)

8P3

B

R

210

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

26.2 8S2

1

3

2

C

1

H

E

E1

N

Top View

e

L

B

A^N

θ

TOP VIEW

END VIEWW

e

b

COMMON DIMENSIONS

D

(Unit of Measure = mm)

A

COMMON DIMENSIONS

(Unit of Measure = mm)

MIN

MAX

NOM

–

NOTE

SYMBOL

Side View

A1

MIN

1.70

MAX

2.16

NOTE

SYMBOL

A

–

1.75

A1

0.05

0.25

A2

L

B

–

0.51

b

0.35

0.48

5

C

–

0.25

C

0.15

0.35

D

–

5.13

–

5.00

5.35

D

E

–

4.00

E1

5.18

5.40

2, 3

e

1.27 BSC

E

7.70

8.26

E

H

L

–

0.51

–

6.20

0.85

SIDE VIEW

L

θ

–

0°

1.27

8°

End View

e

1.27 BSC

4

Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.

2. Mismatch of the upper and lower dies and resin burrs are not included.

3. It is recommended that upper and lower cavities be equal. If they are different, the larger dimension shall be regarded.

4. Determines the true geometric position.

This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.

Note:

5. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.

4/7/06

10/10/01

TITLE

DRAWING NO.

REV.

TITLE

DRAWING NO.

REV.

2325 Orchard Parkway

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing

8S2, 8-lead, 0.209" Body, Plastic Small

2325 Orchard Parkway

8S1

A

8S2

D

R

San Jose, CA 95131

Small Outline (JEDEC SOIC)

R

Outline Package (EIAJ)

San Jose, CA 95131

211

2586K–AVR–01/08

26.3 S8S1

1

3

2

H

N

Top View

e

B

A

D

COMMON DIMENSIONS

(Unit of Measure = mm)

Side View

MIN

–

MAX

1.75

0.51

0.25

5.00

4.00

NOM

NOTE

SYMBOL

A

B

C

D

E

e

–

A2

L

–

1.27 BSC

E

H

L

–

6.20

1.27

End View

Note:

This drawing is for general information only. Refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums, etc.

10/10/01

TITLE

DRAWING NO.

REV.

2325 Orchard Parkway

San Jose, CA 95131

8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing

8S1

A

R

Small Outline (JEDEC SOIC)

212

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

26.4 20M1

D

1

2

Pin 1 ID

SIDE VIEW

E

3

TOP VIEW

A2

A1

D2

A

0.08

C

1

2

Pin #1

Notch

(0.20 R)

COMMON DIMENSIONS

(Unit of Measure = mm)

3

E2

MIN

0.70

–

MAX

0.80

0.05

b

NOM

0.75

NOTE

SYMBOL

A

A1

A2

b

0.01

L

0.20 REF

0.23

0.18

2.45

0.35

0.30

2.75

0.55

e

D

4.00 BSC

2.60

D2

E

BOTTOM VIEW

4.00 BSC

2.60

E2

e

0.50 BSC

0.40

Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.

Note:

L

10/27/04

DRAWING NO. REV.

20M1

TITLE

2325 Orchard Parkway

San Jose, CA 95131

20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm,

2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)

A

R

213

2586K–AVR–01/08

27. Errata

27.1 Errata ATtiny25

The revision letter in this section refers to the revision of the ATtiny25 device.

27.1.1

27.1.2

Rev D and E

Rev B and C

No known errata.

• EEPROM read may fail at low supply voltage / low clock frequency

1. EEPROM read may fail at low supply voltage / low clock frequency

Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in

invalid data.

Problem Fix/Workaround

Do not use the EEPROM when clock frequency is below 1 MHz and supply voltage is below

2V. If operating frequency can not be raised above 1 MHz then supply voltage should be

more than 3V. Similarly, if supply voltage can not be raised above 2V then operating fre-

quency should be more than 2 MHz.

This feature is known to be temperature dependent but it has not been characterised.

Guidelines are given for room temperature, only.

27.1.3

Rev A

Not sampled.

214

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

27.2 Errata ATtiny45

The revision letter in this section refers to the revision of the ATtiny45 device.

27.2.1

27.2.2

Rev F and G

Rev D and E

No known errata

• EEPROM read may fail at low supply voltage / low clock frequency

1. EEPROM read may fail at low supply voltage / low clock frequency

Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in

invalid data.

Problem Fix/Workaround

Do not use the EEPROM when clock frequency is below 1 MHz and supply voltage is below

2V. If operating frequency can not be raised above 1 MHz then supply voltage should be

more than 3V. Similarly, if supply voltage can not be raised above 2V then operating fre-

quency should be more than 2 MHz.

This feature is known to be temperature dependent but it has not been characterised.

Guidelines are given for room temperature, only.

27.2.3

Rev B and C

• PLL not locking

• EEPROM read from application code does not work in Lock Bit Mode 3

• EEPROM read may fail at low supply voltage / low clock frequency

• Timer Counter 1 PWM output generation on OC1B- XOC1B does not work correctly

1. PLL not locking

When at frequencies below 6.0 MHz, the PLL will not lock

Problem fix / Workaround

When using the PLL, run at 6.0 MHz or higher.

2. EEPROM read from application code does not work in Lock Bit Mode 3

When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does

not work from the application code.

Problem Fix/Work around

Do not set Lock Bit Protection Mode 3 when the application code needs to read from

EEPROM.

3. EEPROM read may fail at low supply voltage / low clock frequency

Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in

invalid data.

Problem Fix/Workaround

Do not use the EEPROM when clock frequency is below 1 MHz and supply voltage is below

2V. If operating frequency can not be raised above 1 MHz then supply voltage should be

215

2586K–AVR–01/08

more than 3V. Similarly, if supply voltage can not be raised above 2V then operating fre-

quency should be more than 2 MHz.

This feature is known to be temperature dependent but it has not been characterised.

Guidelines are given for room temperature, only.

4. Timer Counter 1 PWM output generation on OC1B – XOC1B does not work correctly

Timer Counter1 PWM output OC1B-XOC1B does not work correctly. Only in the case when

the control bits, COM1B1 and COM1B0 are in the same mode as COM1A1 and COM1A0,

respectively, the OC1B-XOC1B output works correctly.

Problem Fix/Work around

The only workaround is to use same control setting on COM1A(1:0) and COM1B(1:0) con-

trol bits, see table 14-4 in the data sheet. The problem has been fixed for Tiny45 rev D.

27.2.4

Rev A

• Too high power down power consumption

• DebugWIRE looses communication when single stepping into interrupts

• PLL not locking

• EEPROM read from application code does not work in Lock Bit Mode 3

• EEPROM read may fail at low supply voltage / low clock frequency

1. Too high power down power consumption

Three situations will lead to a too high power down power consumption. These are:

– An external clock is selected by fuses, but the I/O PORT is still enabled as an output.

– The EEPROM is read before entering power down.

– VCC is 4.5 volts or higher.

Problem fix / Workaround

– When using external clock, avoid setting the clock pin as Output.

– Do not read the EEPROM if power down power consumption is important.

– Use VCC lower than 4.5 Volts.

2. DebugWIRE looses communication when single stepping into interrupts

When receiving an interrupt during single stepping, debugwire will loose

communication.

Problem fix / Workaround

– When singlestepping, disable interrupts.

– When debugging interrupts, use breakpoints within the interrupt routine, and run into

the interrupt.

3. PLL not locking

When at frequencies below 6.0 MHz, the PLL will not lock

Problem fix / Workaround

When using the PLL, run at 6.0 MHz or higher.

4. EEPROM read from application code does not work in Lock Bit Mode 3

216

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does

not work from the application code.

Problem Fix/Work around

Do not set Lock Bit Protection Mode 3 when the application code needs to read from

EEPROM.

5. EEPROM read may fail at low supply voltage / low clock frequency

Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in

invalid data.

Problem Fix/Workaround

Do not use the EEPROM when clock frequency is below 1 MHz and supply voltage is below

2V. If operating frequency can not be raised above 1 MHz then supply voltage should be

more than 3V. Similarly, if supply voltage can not be raised above 2V then operating fre-

quency should be more than 2 MHz.

This feature is known to be temperature dependent but it has not been characterised.

Guidelines are given for room temperature, only.

217

2586K–AVR–01/08

27.3 Errata ATtiny85

The revision letter in this section refers to the revision of the ATtiny85 device.

27.3.1

27.3.2

Rev B and C

Rev A

No known errata.

• EEPROM read may fail at low supply voltage / low clock frequency

1. EEPROM read may fail at low supply voltage / low clock frequency

Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in

invalid data.

Problem Fix/Workaround

Do not use the EEPROM when clock frequency is below 1 MHz and supply voltage is below

2V. If operating frequency can not be raised above 1 MHz then supply voltage should be

more than 3V. Similarly, if supply voltage can not be raised above 2V then operating fre-

quency should be more than 2 MHz.

This feature is known to be temperature dependent but it has not been characterised.

Guidelines are given for room temperature, only.

218

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

28. Datasheet Revision History

28.1 Rev. 2586K-01/08

1. Updated Document Template.

2. Added Sections:

– “Data Retention” on page 6

– “Low Level Interrupt” on page 51

– “Device Signature Imprint Table” on page 153

3. Updated Sections:

– “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24

– “System Clock and Clock Options” on page 23

– “Internal PLL in ATtiny15 Compatibility Mode” on page 24

– “Sleep Modes” on page 35

– “Software BOD Disable” on page 36

– “External Interrupts” on page 51

– “Timer/Counter1 in PWM Mode” on page 101

– “USI – Universal Serial Interface” on page 111

– “Temperature Measurement” on page 137

– “Reading Lock, Fuse and Signature Data from Software” on page 147

– “Program And Data Memory Lock Bits” on page 151

– “Fuse Bytes” on page 152

– “Signature Bytes” on page 154

– “Calibration Bytes” on page 154

– “System and Reset Characteristics” on page 170

4. Added Figures:

– “Reset Pin Output Voltage vs. Sink Current (VCC = 3V)” on page 188

– “Reset Pin Output Voltage vs. Sink Current (VCC = 5V)” on page 189

– “Reset Pin Output Voltage vs. Source Current (VCC = 3V)” on page 189

– “Reset Pin Output Voltage vs. Source Current (VCC = 5V)” on page 190

5. Updated Figure:

– “Reset Logic” on page 41

6. Updated Tables:

– “Start-up Times for Internal Calibrated RC Oscillator Clock” on page 28

– “Start-up Times for Internal Calibrated RC Oscillator Clock (in ATtiny15 Mode)” on

page 28

– “Start-up Times for the 128 kHz Internal Oscillator” on page 29

– “Compare Mode Select in PWM Mode” on page 89

– “Compare Mode Select in PWM Mode” on page 101

– “DC Characteristics. TA = -40×C to 85×C (1)” on page 166

– “Calibration Accuracy of Internal RC Oscillator” on page 169

– “ADC Characteristics – Preliminary” on page 172

219

2586K–AVR–01/08

7. Updated Code Example in Section:

– “Write” on page 17

8. Updated Bit Descriptions in:

– “MCUCR – MCU Control Register” on page 38

– “Bits 7:6 – COM0A1:0: Compare Match Output A Mode” on page 80

– “Bits 5:4 – COM0B1:0: Compare Match Output B Mode” on page 80

– “Bits 2:0 – ADTS2:0: ADC Auto Trigger Source” on page 142

– “SPMCSR – Store Program Memory Control and Status Register” on page 149.

9. Updated description of feature “EEPROM read may fail at low supply voltage / low clock

frequency” in Sections:

– “Errata ATtiny25” on page 214

– “Errata ATtiny45” on page 215

– “Errata ATtiny85” on page 218

10. Updated Package Description in Sections:

– “ATtiny25” on page 207

– “ATtiny45” on page 208

– “ATtiny85” on page 209

11. Updated Package Drawing:

– “S8S1” on page 212

12. Updated Order Codes for:

– “ATtiny25” on page 207

28.2 Rev. 2586J-12/06

1.

Updated “Low Power Consumption” on page 1.

2.

3.

4.

Updated description of instruction length in “Architectural Overview” , starting on

page 7.

Updated Flash size in “In-System Re-programmable Flash Program Memory” on

page 15.

Updated cross-references in sections “Atomic Byte Programming” , “Erase” and

“Write” , starting on page 17.

5.

6.

7.

Updated “Atomic Byte Programming” on page 17.

Updated “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24.

Replaced single clocking system figure with two: Figure 6-2 and Figure 6-3 on page

24.

8.

Updated Table 6-1 on page 25, Table 6-12 on page 30 and Table 6-6 on page 28.

Updated “Calibrated Internal Oscillator” on page 27.

Updated Table 6-5 on page 27.

9.

10.

11.

12.

13.

14.

15.

16.

17.

Updated “OSCCAL – Oscillator Calibration Register” on page 32.

Updated “CLKPR – Clock Prescale Register” on page 33.

Updated “Power-down Mode” on page 36.

Updated “Bit 0” in “PRR – Power Reduction Register” on page 39.

Added footnote to Table 8-3 on page 49.

Updated Table 10-5 on page 65.

Deleted “Bits 7, 2” in “MCUCR – MCU Control Register” on page 66.

220

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

18.

Updated and moved section “Timer/Counter0 Prescaler and Clock Sources”, now

located on page 68.

19.

20.

Updated “Timer/Counter1 Initialization for Asynchronous Mode” on page 89.

Updated bit description in “PLLCSR – PLL Control and Status Register” on page 97

and “PLLCSR – PLL Control and Status Register” on page 107.

Added recommended maximum frequency in“Prescaling and Conversion Timing” on

page 129.

21.

22.

23.

24.

25.

Updated Figure 17-8 on page 133 .

Updated “Temperature Measurement” on page 137.

Updated Table 17-3 on page 138.

Updated bit R/W descriptions in:

“TIMSK – Timer/Counter Interrupt Mask Register” on page 84,

“TIFR – Timer/Counter Interrupt Flag Register” on page 84,

“TIMSK – Timer/Counter Interrupt Mask Register” on page 95,

“TIFR – Timer/Counter Interrupt Flag Register” on page 96,

“PLLCSR – PLL Control and Status Register” on page 97,

“TIMSK – Timer/Counter Interrupt Mask Register” on page 106,

“TIFR – Timer/Counter Interrupt Flag Register” on page 106,

“PLLCSR – PLL Control and Status Register” on page 107 and

“DIDR0 – Digital Input Disable Register 0” on page 142.

Added limitation to “Limitations of debugWIRE” on page 144.

Updated “DC Characteristics” on page 166.

26.

27.

28.

29.

30.

31.

32.

33.

34.

35.

36.

Updated Table 21-7 on page 171.

Updated Figure 21-6 on page 175.

Updated Table 21-11 on page 175.

Updated Table 22-1 on page 181.

Updated Table 22-2 on page 181.

Updated Table 22-30, Table 22-31 and Table 22-32, starting on page 192.

Updated Table 22-33, Table 22-34 and Table 22-35, starting on page 193.

Updated Table 22-37 on page 195.

Updated Table 22-44, Table 22-45, Table 22-46 and Table 22-47, starting on page

199.

28.3 Rev. 2586I-09/06

1.

2.

All Characterization data moved to “Electrical Characteristics” on page 166.

All Register Descriptions are gathered up in seperate sections in the end of each

chapter.

3.

Updated Table 11-3 on page 81, Table 11-5 on page 82, Table 11-6 on page 83 and

Table 20-4 on page 152.

4.

5.

6.

7.

8.

9.

Updated “Calibrated Internal Oscillator” on page 27.

Updated Note in Table 7-1 on page 35.

Updated “System Control and Reset” on page 41.

Updated Register Description in “I/O Ports” on page 55.

Updated Features in “USI – Universal Serial Interface” on page 111.

Updated Code Example in “SPI Master Operation Example” on page 113 and “SPI

Slave Operation Example” on page 114.

10.

Updated “Analog Comparator Multiplexed Input” on page 123.

221

2586K–AVR–01/08

11.

12.

13.

Updated Figure 17-1 on page 127.

Updated “Signature Bytes” on page 154.

Updated “Electrical Characteristics” on page 166.

28.4 Rev. 2586H-06/06

1.

2.

3.

Updated “Calibrated Internal Oscillator” on page 27.

Updated Table 6.5.1 on page 32.

Added Table 21-2 on page 169.

28.5 Rev. 2586G-05/06

1.

Updated “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24.

Updated “Default Clock Source” on page 31.

2.

3.

Updated “Low-Frequency Crystal Oscillator” on page 29.

Updated “Calibrated Internal Oscillator” on page 27.

Updated “Clock Output Buffer” on page 32.

4.

5.

6.

Updated “Power Management and Sleep Modes” on page 35.

Added “Software BOD Disable” on page 36.

7.

8.

Updated Figure 16-1 on page 123.

9.

Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 124.

Added note for Table 17-2 on page 129.

10.

11.

Updated “Register Summary” on page 203.

28.6 Rev. 2586F-04/06

1.

2.

3.

Updated “Digital Input Enable and Sleep Modes” on page 59.

Updated Table 20-16 on page 163.

Updated “Ordering Information” on page 207.

28.7 Rev. 2586E-03/06

1.

2.

3.

4.

5.

Updated Features in “Analog to Digital Converter” on page 126.

Updated Operation in “Analog to Digital Converter” on page 126.

Updated Table 17-2 on page 138.

Updated Table 17-3 on page 138.

Updated “Errata” on page 214.

28.8 Rev. 2586D-02/06

1.

Updated Table 6-12 on page 30, Table 6-10 on page 29, Table 6-3 on page 26,

Table 6-9 on page 29, Table 6-5 on page 27, Table 9-1 on page 50,Table 17-4 on

page 139, Table 20-16 on page 163, Table 21-8 on page 172.

Updated “Timer/Counter1 in PWM Mode” on page 89.

2.

3.

4.

5.

6.

Updated text “Bit 2 - TOV1: Timer/Counter1 Overflow Flag” on page 96.

Updated values in “DC Characteristics” on page 166.

Updated “Register Summary” on page 203.

Updated “Ordering Information” on page 207.

222

ATtiny25/45/85

2586K–AVR–01/08

ATtiny25/45/85

7.

8.

9.

Updated Rev B and C in “Errata ATtiny45” on page 215.

All references to power-save mode are removed.

Updated Register Adresses.

28.9 Rev. 2586C-06/05

1.

2.

3.

4.

5.

6.

Updated “Features” on page 1.

Updated Figure 1-1 on page 2.

Updated Code Examples on page 18 and page 19.

Moved “Temperature Measurement” to Section 17.12 page 137.

Updated “Register Summary” on page 203.

Updated “Ordering Information” on page 207.

28.10 Rev. 2586B-05/05

1.

CLKI added, instances of EEMWE/EEWE renamed EEMPE/EEPE, removed some

TBD.

Removed “Preliminary Description” from “Temperature Measurement” on page 137.

Updated “Features” on page 1.

2.

3.

4.

5.

6.

7.

8.

9.

Updated Figure 1-1 on page 2 and Figure 8-1 on page 41.

Updated Table 7-2 on page 39, Table 10-4 on page 65, Table 10-5 on page 65

Updated “Serial Programming Instruction set” on page 157.

Updated SPH register in “Instruction Set Summary” on page 205.

Updated “DC Characteristics” on page 166.

Updated “Ordering Information” on page 207.

Updated “Errata” on page 214.

28.11 Rev. 2586A-02/05

Initial revision.

223

2586K–AVR–01/08

224

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ATtiny25/45/85

Table of Contents

Features..................................................................................................... 1

Pin Configurations ................................................................................... 2

1

2

3

1.1

Pin Descriptions .................................................................................................2

Overview ................................................................................................... 4

2.1

Block Diagram ...................................................................................................4

About ......................................................................................................... 6

3.1

3.2

3.3

Resources .........................................................................................................6

Code Examples .................................................................................................6

Data Retention ...................................................................................................6

4

AVR CPU Core .......................................................................................... 7

4.1

4.2

4.3

4.4

4.5

4.6

4.7

4.8

Introduction ........................................................................................................7

Architectural Overview .......................................................................................7

ALU – Arithmetic Logic Unit ...............................................................................8

Status Register ..................................................................................................8

General Purpose Register File ........................................................................10

Stack Pointer ...................................................................................................11

Instruction Execution Timing ...........................................................................12

Reset and Interrupt Handling ...........................................................................12

5

6

7

AVR Memories ........................................................................................ 15

5.1

5.2

5.3

5.4

5.5

In-System Re-programmable Flash Program Memory ....................................15

SRAM Data Memory ........................................................................................15

EEPROM Data Memory ..................................................................................16

I/O Memory ......................................................................................................20

Register Description ........................................................................................20

System Clock and Clock Options ......................................................... 23

6.1

6.2

6.3

6.4

6.5

Clock Systems and their Distribution ...............................................................23

Clock Sources .................................................................................................25

System Clock Prescaler ..................................................................................31

Clock Output Buffer .........................................................................................32

Register Description ........................................................................................32

Power Management and Sleep Modes ................................................. 35

7.1

Sleep Modes ....................................................................................................35

i

2586K–AVR–01/08

7.2

7.3

7.4

7.5

Software BOD Disable .....................................................................................36

Power Reduction Register ...............................................................................37

Minimizing Power Consumption ......................................................................37

Register Description ........................................................................................38

8

9

System Control and Reset .................................................................... 41

8.1

8.2

8.3

8.4

8.5

Resetting the AVR ...........................................................................................41

Reset Sources .................................................................................................41

Internal Voltage Reference ..............................................................................44

Watchdog Timer ..............................................................................................44

Register Description ........................................................................................47

Interrupts ................................................................................................ 50

9.1

9.2

9.3

Interrupt Vectors in ATtiny25/45/85 .................................................................50

External Interrupts ...........................................................................................51

Register Description ........................................................................................52

10 I/O Ports .................................................................................................. 55

10.1

10.2

10.3

10.4

Introduction ......................................................................................................55

Ports as General Digital I/O .............................................................................56

Alternate Port Functions ..................................................................................59

Register Description ........................................................................................66

11 8-bit Timer/Counter0 with PWM ............................................................ 67

11.1

11.2

11.3

11.4

11.5

11.6

11.7

11.8

11.9

Features ..........................................................................................................67

Overview ..........................................................................................................67

Timer/Counter0 Prescaler and Clock Sources ................................................68

Counter Unit ....................................................................................................70

Output Compare Unit .......................................................................................71

Compare Match Output Unit ............................................................................72

Modes of Operation .........................................................................................74

Timer/Counter Timing Diagrams .....................................................................78

Register Description ........................................................................................80

12 8-bit Timer/Counter1 .............................................................................. 86

12.1

12.2

12.3

Timer/Counter1 Prescaler ...............................................................................86

Counter and Compare Units ............................................................................86

Register Description ........................................................................................92

13 8-bit Timer/Counter1 in ATtiny15 Mode ............................................... 98

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ATtiny25/45/85

13.1

13.2

13.3

Timer/Counter1 Prescaler ...............................................................................98

Counter and Compare Units ............................................................................98

Register Description ......................................................................................103

14 Dead Time Generator ........................................................................... 108

14.1

Register Description ......................................................................................109

15 USI – Universal Serial Interface .......................................................... 111

15.1

15.2

15.3

15.4

15.5

Features ........................................................................................................111

Overview ........................................................................................................111

Functional Descriptions .................................................................................112

Alternative USI Usage ...................................................................................117

Register Descriptions ....................................................................................118

16 Analog Comparator ............................................................................. 123

16.1

16.2

Analog Comparator Multiplexed Input ...........................................................123

Register Description ......................................................................................124

17 Analog to Digital Converter ................................................................ 126

17.1

17.2

17.3

17.4

17.5

17.6

17.7

17.8

17.9

Features ........................................................................................................126

Overview ........................................................................................................126

Operation .......................................................................................................127

Starting a Conversion ....................................................................................128

Prescaling and Conversion Timing ................................................................129

Changing Channel or Reference Selection ...................................................132

ADC Noise Canceler .....................................................................................132

Analog Input Circuitry ....................................................................................133

Noise Canceling Techniques .........................................................................134

17.10 ADC Accuracy Definitions .............................................................................134

17.11 ADC Conversion Result .................................................................................136

17.12 Temperature Measurement ...........................................................................137

17.13 Register Description ......................................................................................138

18 debugWIRE On-chip Debug System .................................................. 143

18.1

18.2

18.3

18.4

18.5

Features ........................................................................................................143

Overview ........................................................................................................143

Physical Interface ..........................................................................................143

Software Break Points ...................................................................................144

Limitations of debugWIRE .............................................................................144

iii

2586K–AVR–01/08

18.6

Register Description ......................................................................................144

19 Self-Programming the Flash ............................................................... 145

19.1

19.2

19.3

19.4

19.5

19.6

19.7

19.8

19.9

Performing Page Erase by SPM ....................................................................145

Filling the Temporary Buffer (Page Loading) .................................................145

Performing a Page Write ...............................................................................146

Addressing the Flash During Self-Programming ...........................................146

EEPROM Write Prevents Writing to SPMCSR ..............................................147

Reading Lock, Fuse and Signature Data from Software ...............................147

Preventing Flash Corruption ..........................................................................149

Programming Time for Flash when Using SPM ............................................149

Register Description ......................................................................................149

20 Memory Programming ......................................................................... 151

20.1

20.2

20.3

20.4

20.5

20.6

20.7

Program And Data Memory Lock Bits ...........................................................151

Fuse Bytes .....................................................................................................152

Device Signature Imprint Table .....................................................................153

Page Size ......................................................................................................154

Serial Downloading ........................................................................................155

High-voltage Serial Programming ..................................................................158

High-voltage Serial Programming Algorithm .................................................159

21 Electrical Characteristics .................................................................... 166

21.1

21.2

21.3

21.4

21.5

21.6

21.7

21.8

21.9

Absolute Maximum Ratings* .........................................................................166

DC Characteristics .........................................................................................166

Speed Grades ...............................................................................................168

Clock Characteristics .....................................................................................169

System and Reset Characteristics ................................................................170

Brown-Out Detection .....................................................................................171

ADC Characteristics – Preliminary ................................................................172

Serial Programming Characteristics ..............................................................174

High-voltage Serial Programming Characteristics .........................................175

22 Typical Characteristics ........................................................................ 176

22.1

22.2

22.3

22.4

22.5

Active Supply Current ....................................................................................176

Idle Supply Current ........................................................................................179

Supply Current of I/O modules ......................................................................181

Power-down Supply Current ..........................................................................182

Pin Pull-up .....................................................................................................183

iv

ATtiny25/45/85

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ATtiny25/45/85

22.6

22.7

22.8

22.9

Pin Driver Strength ........................................................................................186

Pin Threshold and Hysteresis ........................................................................190

BOD Threshold and Analog Comparator Offset ............................................193

Internal Oscillator Speed ...............................................................................195

22.10 Current Consumption of Peripheral Units ......................................................199

22.11 Current Consumption in Reset and Reset Pulsewidth ..................................201

23 Register Summary ............................................................................... 203

24 Instruction Set Summary .................................................................... 205

25 Ordering Information ........................................................................... 207

25.1

25.2

25.3

ATtiny25 ........................................................................................................207

ATtiny45 ........................................................................................................208

ATtiny85 ........................................................................................................209

26 Packaging Information ........................................................................ 210

26.1

26.2

26.3

26.4

8P3 ................................................................................................................210

8S2 ................................................................................................................211

S8S1 ..............................................................................................................212

20M1 ..............................................................................................................213

27 Errata ..................................................................................................... 214

27.1

27.2

27.3

Errata ATtiny25 ..............................................................................................214

Errata ATtiny45 ..............................................................................................215

Errata ATtiny85 ..............................................................................................218

28 Datasheet Revision History ................................................................ 219

28.1

28.2

28.3

28.4

28.5

28.6

28.7

28.8

28.9

Rev. 2586K-01/08 ..........................................................................................219

Rev. 2586J-12/06 ..........................................................................................220

Rev. 2586I-09/06 ...........................................................................................221

Rev. 2586H-06/06 .........................................................................................222

Rev. 2586G-05/06 .........................................................................................222

Rev. 2586F-04/06 ..........................................................................................222

Rev. 2586E-03/06 ..........................................................................................222

Rev. 2586D-02/06 .........................................................................................222

Rev. 2586C-06/05 .........................................................................................223

28.10 Rev. 2586B-05/05 ..........................................................................................223

28.11 Rev. 2586A-02/05 ..........................................................................................223

Table of Contents....................................................................................... i

v

2586K–AVR–01/08

vi

ATtiny25/45/85

2586K–AVR–01/08

Headquarters

International

Atmel Corporation

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Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

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2586K–AVR–01/08


型号：	ATTINY45V-10SU-SL383
厂家：	ATMEL
描述：	Microcontroller ATM 异步传输模式微控制器
文件：	总231页 (文件大小：4335K)
中文：	中文翻译
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ATTINY45V-10SU-SL383 [ATMEL]

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