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ATTINY5

更新时间：2025-07-09 08:14:02
品牌：ATMEL
描述：8-bit Microcontroller with 512/1024 Bytes In-System Programmable Flash

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ATTINY5 概述

8-bit Microcontroller with 512/1024 Bytes In-System Programmable Flash 8 -bit微控制器512/1024字节的系统内可编程闪存

ATTINY5 数据手册

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Features  
• High Performance, Low Power AVR® 8-Bit Microcontroller  
• Advanced RISC Architecture  
– 54 Powerful Instructions – Most Single Clock Cycle Execution  
– 16 x 8 General Purpose Working Registers  
– Fully Static Operation  
– Up to 12 MIPS Throughput at 12 MHz  
• Non-volatile Program and Data Memories  
– 512/1024 Bytes of In-System Programmable Flash Program Memory  
– 32 Bytes Internal SRAM  
8-bit  
– Flash Write/Erase Cycles: 10,000  
– Data Retention: 20 Years at 85oC / 100 Years at 25oC  
• Peripheral Features  
Microcontroller  
with 512/1024  
Bytes In-System  
Programmable  
Flash  
– One 16-bit Timer/Counter with Prescaler and Two PWM Channels  
– Programmable Watchdog Timer with Separate On-chip Oscillator  
– 4-channel, 8-bit Analog to Digital Converter (1)  
– On-chip Analog Comparator  
• Special Microcontroller Features  
– In-System Programmable (2)  
– External and Internal Interrupt Sources  
– Low Power Idle, ADC Noise Reduction, and Power-down Modes  
– Enhanced Power-on Reset Circuit  
– Programmable Supply Voltage Level Monitor with Interrupt and Reset  
– Internal Calibrated Oscillator  
ATtiny4/5/9/10  
Preliminary  
• I/O and Packages  
– 6-pin SOT: Four Programmable I/O Lines  
• Operating Voltage:  
– 1.8 – 5.5V  
• Programming Voltage:  
– 5V  
• Speed Grade  
– 0 – 4 MHz @ 1.8 – 5.5V  
– 0 – 8 MHz @ 2.7 – 5.5V  
– 0 – 12 MHz @ 4.5 – 5.5V  
• Industrial Temperature Range  
• Low Power Consumption  
– Active Mode:  
• 200µA at 1MHz and 1.8V  
– Idle Mode:  
• 25µA at 1MHz and 1.8V  
– Power-down Mode:  
• < 0.1µA at 1.8V  
Note:  
1. The Analog to Digital Converter (ADC) is available in ATtiny5/10, only  
2. At 5V, only  
8127CS–AVR–10/09  
1. Pin Configurations  
Figure 1-1. Pinout of ATtiny4/5/9/10  
SOT-23  
(PCINT0/TPIDATA/OC0A/ADC0/AIN0) PB0  
GND  
(PCINT1/TPICLK/CLKI/ICP0/OC0B/ADC1/AIN1) PB1  
1
2
3
6
5
4
PB3 (RESET/PCINT3/ADC3)  
VCC  
PB2 (T0/CLKO/PCINT2/INT0/ADC2)  
1.1  
Pin Description  
1.1.1  
VCC  
Supply voltage.  
Ground.  
1.1.2  
1.1.3  
GND  
Port B (PB3..PB0)  
This is a 4-bit, bi-directional I/O port with internal pull-up resistors, individually selectable for  
each bit. The output buffers have symmetrical drive characteristics, with both high sink and  
source capability. As inputs, the port pins that are externally pulled low will source current if pull-  
up resistors are activated. Port pins are tri-stated when a reset condition becomes active, even if  
the clock is not running.  
The port also serves the functions of various special features of the ATtiny4/5/9/10, as listed on  
page 36.  
1.1.4  
RESET  
Reset input. A low level on this pin for longer than the minimum pulse length will generate a  
reset, even if the clock is not running and provided the reset pin has not been disabled. The min-  
imum pulse length is given in Table 16-4 on page 119. Shorter pulses are not guaranteed to  
generate a reset.  
The reset pin can also be used as a (weak) I/O pin.  
2
ATtiny4/5/9/10  
8127CS–AVR–10/09  
ATtiny4/5/9/10  
2. Overview  
ATtiny4/5/9/10 are low-power CMOS 8-bit microcontrollers based on the compact AVR  
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the  
ATtiny4/5/9/10 achieve throughputs approaching 1 MIPS per MHz, allowing the system designer  
to optimize power consumption versus processing speed.  
Figure 2-1. Block Diagram  
VCC  
RESET  
PROGRAMMING  
LOGIC  
PROGRAM  
COUNTER  
INTERNAL  
OSCILLATOR  
CALIBRATED  
OSCILLATOR  
PROGRAM  
FLASH  
STACK  
POINTER  
WATCHDOG  
TIMER  
TIMING AND  
CONTROL  
INSTRUCTION  
REGISTER  
RESET FLAG  
REGISTER  
SRAM  
INSTRUCTION  
DECODER  
MCU STATUS  
REGISTER  
GENERAL  
PURPOSE  
REGISTERS  
CONTROL  
LINES  
X
Y
Z
TIMER/  
COUNTER0  
INTERRUPT  
UNIT  
ALU  
ISP  
STATUS  
REGISTER  
INTERFACE  
8-BIT DATA BUS  
DATA REGISTER  
PORT B  
DIRECTION  
REG. PORT B  
ANALOG  
COMPARATOR  
ADC  
DRIVERS  
PORT B  
PB3:0  
GND  
The AVR core combines a rich instruction set with 16 general purpose working registers and  
system registers. All registers are directly connected to the Arithmetic Logic Unit (ALU), allowing  
two independent registers to be accessed in one single instruction executed in one clock cycle.  
The resulting architecture is compact and code efficient while achieving throughputs up to ten  
times faster than conventional CISC microcontrollers.  
3
8127CS–AVR–10/09  
The ATtiny4/5/9/10 provide the following features: 512/1024 byte of In-System Programmable  
Flash, 32 bytes of SRAM, four general purpose I/O lines, 16 general purpose working registers,  
a 16-bit timer/counter with two PWM channels, internal and external interrupts, a programmable  
watchdog timer with internal oscillator, an internal calibrated oscillator, and four software select-  
able power saving modes. ATtiny5/10 are also equipped with a four-channel, 8-bit Analog to  
Digital Converter (ADC).  
Idle mode stops the CPU while allowing the SRAM, timer/counter, ADC (ATtiny5/10, only), ana-  
log comparator, and interrupt system to continue functioning. ADC Noise Reduction mode  
minimizes switching noise during ADC conversions by stopping the CPU and all I/O modules  
except the ADC. In Power-down mode registers keep their contents and all chip functions are  
disabled until the next interrupt or hardware reset. In Standby mode, the oscillator is running  
while the rest of the device is sleeping, allowing very fast start-up combined with low power  
consumption.  
The device is manufactured using Atmel’s high density non-volatile memory technology. The on-  
chip, in-system programmable Flash allows program memory to be re-programmed in-system by  
a conventional, non-volatile memory programmer.  
The ATtiny4/5/9/10 AVR are supported by a suite of program and system development tools,  
including macro assemblers and evaluation kits.  
2.1  
Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10  
A comparison of the devices is shown in Table 2-1.  
Table 2-1.  
Differences between ATtiny4, ATtiny5, ATtiny9 and ATtiny10  
Device  
Flash  
ADC  
No  
Signature  
ATtiny4  
ATtiny5  
ATtiny9  
ATtiny10  
512 bytes  
512 bytes  
1024 bytes  
1024 bytes  
0x1E 0x8F 0x0A  
0x1E 0x8F 0x09  
0x1E 0x90 0x08  
0x1E 0x90 0x03  
Yes  
No  
Yes  
4
ATtiny4/5/9/10  
8127CS–AVR–10/09  
ATtiny4/5/9/10  
3. General Information  
3.1  
Resources  
A comprehensive set of drivers, application notes, data sheets and descriptions on development  
tools are available for download at http://www.atmel.com/avr.  
3.2  
Code Examples  
This documentation contains simple code examples that briefly show how to use various parts of  
the device. These code examples assume that the part specific header file is included before  
compilation. Be aware that not all C compiler vendors include bit definitions in the header files  
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-  
tation for more details.  
3.3  
3.4  
Data Retention  
Reliability Qualification results show that the projected data retention failure rate is much less  
than 1 PPM over 20 years at 85°C or 100 years at 25°C.  
Disclaimer  
Typical values contained in this datasheet are based on simulations and characterization of  
other AVR microcontrollers manufactured on the same process technology. Min and Max values  
will be available after the device has been characterized.  
5
8127CS–AVR–10/09  
4. Register Summary  
Address  
Name  
Bit 7  
Bit 6  
Bit 5  
Bit 4  
Bit 3  
Bit 2  
Bit 1  
Bit 0  
Page  
0x3F  
0x3E  
0x3D  
0x3C  
0x3B  
0x3A  
0x39  
0x38  
0x37  
0x36  
0x35  
0x34  
0x33  
0x32  
0x31  
0x30  
0x2F  
0x2E  
0x2D  
0x2C  
0x2B  
0x2A  
0x29  
0x28  
0x27  
0x26  
0x25  
0x24  
0x23  
0x22  
0x21  
0x20  
0x1F  
0x1E  
0x1D  
0x1C  
0x1B  
0x1A  
0x19  
0x18  
0x17  
0x16  
0x15  
0x14  
0x13  
0x12  
0x11  
0x10  
0x0F  
0x0E  
0x0D  
0x0C  
0x0B  
0x0A  
0x09  
0x08  
0x07  
0x06  
0x05  
0x04  
0x03  
0x02  
0x01  
0x00  
SREG  
SPH  
I
T
H
S
V
N
Z
C
Page 12  
Page 12  
Page 12  
Page 12  
Page 34  
Page 25  
Page 21  
Stack Pointer High Byte  
Stack Pointer Low Byte  
SPL  
CCP  
CPU Change Protection Byte  
RSTFLR  
SMCR  
–
–
–
–
–
–
–
–
WDRF  
SM2  
–
EXTRF  
SM0  
PORF  
SE  
SM1  
OSCCAL  
Reserved  
CLKMSR  
CLKPSR  
PRR  
Oscillator Calibration Byte  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
CLKMS1  
CLKPS1  
PRADC  
VLM1  
CLKMS0  
CLKPS0  
PRTIM0  
VLM0  
Page 21  
Page 22  
Page 26  
Page 33  
Page 115  
Page 115  
Page 32  
–
–
–
CLKPS3  
CLKPS2  
–
–
–
–
VLMCSR  
NVMCMD  
NVMCSR  
WDTCSR  
Reserved  
GTCCR  
TCCR0A  
TCCR0B  
TCCR0C  
TIMSK0  
TIFR0  
VLMF  
–
VLMIE  
VLM2  
–
NVM Comman  
NVMBSY  
WDIF  
–
–
–
–
–
–
–
WDP1  
–
–
WDP0  
–
WDIE  
WDP3  
–
WDE  
WDP2  
–
–
–
–
–
TSM  
COM0A1  
ICNC0  
FOC0A  
–
–
COM0A0  
ICES0  
FOC0B  
–
–
COM0B1  
–
–
–
–
–
–
PSR  
WGM00  
CS00  
–
Page 79  
Page 73  
Page 75  
Page 76  
Page 78  
Page 79  
Page 77  
Page 77  
Page 77  
Page 77  
Page 77  
Page 77  
Page 78  
Page 78  
COM0B0  
–
WGM01  
CS01  
–
WGM03  
WGM02  
CS02  
–
–
–
–
–
–
–
–
ICIE0  
ICF0  
OCIE0B  
OCF0B  
OCIE0A  
OCF0A  
TOIE0  
TOV0  
–
–
TCNT0H  
TCNT0L  
OCR0AH  
OCR0AL  
OCR0BH  
OCR0BL  
ICR0H  
Timer/Counter0 – Counter Register High Byte  
Timer/Counter0 – Counter Register Low Byte  
Timer/Counter0 – Compare Register A High Byte  
Timer/Counter0 – Compare Register A Low Byte  
Timer/Counter0 – Compare Register B High Byte  
Timer/Counter0 – Compare Register B Low Byte  
Timer/Counter0 - Input Capture Register High Byte  
Timer/Counter0 - Input Capture Register Low Byte  
ICR0L  
Reserved  
Reserved  
ACSR  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ACIC  
–
ACD  
–
ACO  
ACI  
–
ACIE  
ACIS1  
–
ACIS0  
–
Page 81  
Reserved  
ADCSRA  
ADCSRB  
ADMUX  
Reserved  
ADCL  
–
–
–
–
ADEN  
ADSC  
ADATE  
ADIF  
–
ADIE  
ADPS2  
ADTS2  
–
ADPS1  
ADTS1  
MUX1  
–
ADPS0  
ADTS0  
MUX0  
–
Page 93  
Page 94  
Page 93  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ADC Conversion Result  
Page 95  
Reserved  
DIDR0  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
ADC3D  
ADC2D  
ADC1D  
ADC0D  
Page 82, Page 95  
Reserved  
EICRA  
–
–
–
–
–
–
ISC01  
ISC00  
Page 37  
Page 38  
Page 38  
Page 39  
Page 39  
Page 39  
EIFR  
–
–
–
INTF0  
EIMSK  
–
–
–
INT0  
PCICR  
–
–
–
PCIE0  
PCIFR  
–
–
–
PCIF0  
PCMSK  
Reserved  
Reserved  
Reserved  
PORTCR  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
Reserved  
PUEB  
PCINT3  
PCINT2  
PCINT1  
PCINT0  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
BBMB  
–
Page 50  
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
PUEB3  
PORTB3  
DDRB3  
PINB3  
PUEB2  
PORTB2  
DDRB2  
PINB2  
PUEB1  
PORTB1  
DDRB1  
PINB1  
PUEB0  
PORTB0  
DDRB0  
PINB0  
Page 50  
Page 51  
Page 51  
Page 51  
PORTB  
DDRB  
PINB  
6
ATtiny4/5/9/10  
8127CS–AVR–10/09  
ATtiny4/5/9/10  
Note:  
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses  
should never be written.  
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these  
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.  
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI  
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The  
CBI and SBI instructions work with registers 0x00 to 0x1F only.  
4. The ADC is available in ATtiny5/10, only.  
7
8127CS–AVR–10/09  
5. Instruction Set Summary  
Mnemonics  
Operands  
Description  
Operation  
Flags  
#Clocks  
ARITHMETIC AND LOGIC INSTRUCTIONS  
ADD  
ADC  
SUB  
SUBI  
SBC  
SBCI  
AND  
ANDI  
OR  
Rd, Rr  
Rd, Rr  
Rd, Rr  
Rd, K  
Rd, Rr  
Rd, K  
Rd, Rr  
Rd, K  
Rd, Rr  
Rd, K  
Rd, Rr  
Rd  
Add without Carry  
Add with Carry  
Rd ← Rd + Rr  
Z,C,N,V,S,H  
Z,C,N,V,S,H  
Z,C,N,V,S,H  
Z,C,N,V,S,H  
Z,C,N,V,S,H  
Z,C,N,V,S,H  
Z,N,V,S  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rd ← Rd + Rr + C  
Rd ← Rd - Rr  
Rd ← Rd - K  
Subtract without Carry  
Subtract Immediate  
Subtract with Carry  
Rd ← Rd - Rr - C  
Rd ← Rd - K - C  
Rd ← Rd • Rr  
Rd ← Rd • K  
Subtract Immediate with Carry  
Logical AND  
Logical AND with Immediate  
Logical OR  
Z,N,V,S  
Rd ← Rd v Rr  
Rd ← Rd v K  
Z,N,V,S  
ORI  
Logical OR with Immediate  
Exclusive OR  
Z,N,V,S  
EOR  
COM  
NEG  
SBR  
CBR  
INC  
Rd ← Rd ⊕ Rr  
Rd ← $FF − Rd  
Rd ← $00 − Rd  
Rd ← Rd v K  
Z,N,V,S  
One’s Complement  
Two’s Complement  
Set Bit(s) in Register  
Clear Bit(s) in Register  
Increment  
Z,C,N,V,S  
Z,C,N,V,S,H  
Z,N,V,S  
Rd  
Rd,K  
Rd,K  
Rd  
Rd ← Rd • ($FFh - K)  
Rd ← Rd + 1  
Z,N,V,S  
Z,N,V,S  
DEC  
TST  
CLR  
SER  
Rd  
Decrement  
Rd ← Rd − 1  
Z,N,V,S  
Rd  
Test for Zero or Minus  
Clear Register  
Rd ← Rd • Rd  
Rd ← Rd ⊕ Rd  
Rd ← $FF  
Z,N,V,S  
Rd  
Z,N,V,S  
Rd  
Set Register  
None  
BRANCH INSTRUCTIONS  
RJMP  
IJMP  
k
Relative Jump  
PC ← PC + k + 1  
None  
None  
None  
None  
None  
I
2
2
Indirect Jump to (Z)  
PC(15:0) ← Z, PC(21:16) ← 0  
PC ← PC + k + 1  
RCALL  
ICALL  
RET  
k
Relative Subroutine Call  
Indirect Call to (Z)  
3/4  
3/4  
4/5  
4/5  
1/2/3  
1
PC(15:0) ← Z, PC(21:16) ← 0  
PC ← STACK  
Subroutine Return  
RETI  
Interrupt Return  
PC ← STACK  
CPSE  
CP  
Rd,Rr  
Compare, Skip if Equal  
Compare  
if (Rd = Rr) PC ← PC + 2 or 3  
Rd − Rr  
None  
Z, C,N,V,S,H  
Z, C,N,V,S,H  
Z, C,N,V,S,H  
None  
Rd,Rr  
CPC  
Rd,Rr  
Compare with Carry  
Rd − Rr − C  
1
CPI  
Rd,K  
Compare with Immediate  
Skip if Bit in Register Cleared  
Skip if Bit in Register is Set  
Skip if Bit in I/O Register Cleared  
Skip if Bit in I/O Register is Set  
Branch if Status Flag Set  
Branch if Status Flag Cleared  
Branch if Equal  
Rd − K  
1
SBRC  
SBRS  
SBIC  
Rr, b  
if (Rr(b)=0) PC ← PC + 2 or 3  
if (Rr(b)=1) PC ← PC + 2 or 3  
if (I/O(A,b)=0) PC ← PC + 2 or 3  
if (I/O(A,b)=1) PC ← PC + 2 or 3  
if (SREG(s) = 1) then PC←PC+k + 1  
if (SREG(s) = 0) then PC←PC+k + 1  
if (Z = 1) then PC ← PC + k + 1  
if (Z = 0) then PC ← PC + k + 1  
if (C = 1) then PC ← PC + k + 1  
if (C = 0) then PC ← PC + k + 1  
if (C = 0) then PC ← PC + k + 1  
if (C = 1) then PC ← PC + k + 1  
if (N = 1) then PC ← PC + k + 1  
if (N = 0) then PC ← PC + k + 1  
if (N ⊕ V= 0) then PC ← PC + k + 1  
if (N ⊕ V= 1) then PC ← PC + k + 1  
if (H = 1) then PC ← PC + k + 1  
if (H = 0) then PC ← PC + k + 1  
if (T = 1) then PC ← PC + k + 1  
if (T = 0) then PC ← PC + k + 1  
if (V = 1) then PC ← PC + k + 1  
if (V = 0) then PC ← PC + k + 1  
if ( I = 1) then PC ← PC + k + 1  
if ( I = 0) then PC ← PC + k + 1  
1/2/3  
1/2/3  
1/2/3  
1/2/3  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
1/2  
Rr, b  
None  
None  
A, b  
A, b  
s, k  
s, k  
k
SBIS  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
BRBS  
BRBC  
BREQ  
BRNE  
BRCS  
BRCC  
BRSH  
BRLO  
BRMI  
BRPL  
BRGE  
BRLT  
BRHS  
BRHC  
BRTS  
BRTC  
BRVS  
BRVC  
BRIE  
BRID  
k
Branch if Not Equal  
k
Branch if Carry Set  
k
Branch if Carry Cleared  
Branch if Same or Higher  
Branch if Lower  
k
k
k
Branch if Minus  
k
Branch if Plus  
k
Branch if Greater or Equal, Signed  
Branch if Less Than Zero, Signed  
Branch if Half Carry Flag Set  
Branch if Half Carry Flag Cleared  
Branch if T Flag Set  
k
k
k
k
k
Branch if T Flag Cleared  
Branch if Overflow Flag is Set  
Branch if Overflow Flag is Cleared  
Branch if Interrupt Enabled  
Branch if Interrupt Disabled  
k
k
k
k
BIT AND BIT-TEST INSTRUCTIONS  
LSL  
Rd  
Rd  
Rd  
Rd  
Rd  
Rd  
s
Logical Shift Left  
Rd(n+1) ← Rd(n), Rd(0) ← 0  
Rd(n) ← Rd(n+1), Rd(7) ← 0  
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)  
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)  
Rd(n) ← Rd(n+1), n=0..6  
Z,C,N,V,H  
Z,C,N,V  
Z,C,N,V,H  
Z,C,N,V  
Z,C,N,V  
None  
1
1
1
1
1
1
1
LSR  
Logical Shift Right  
Rotate Left Through Carry  
Rotate Right Through Carry  
Arithmetic Shift Right  
Swap Nibbles  
ROL  
ROR  
ASR  
SWAP  
BSET  
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)  
SREG(s) ← 1  
Flag Set  
SREG(s)  
8
ATtiny4/5/9/10  
8127CS–AVR–10/09  
ATtiny4/5/9/10  
Mnemonics  
Operands  
Description  
Operation  
Flags  
#Clocks  
BCLR  
SBI  
s
Flag Clear  
SREG(s) ← 0  
I/O(A, b) ← 1  
I/O(A, b) ← 0  
T ← Rr(b)  
Rd(b) ← T  
C ← 1  
SREG(s)  
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
A, b  
Set Bit in I/O Register  
Clear Bit in I/O Register  
None  
CBI  
A, b  
None  
BST  
BLD  
SEC  
CLC  
SEN  
CLN  
SEZ  
CLZ  
SEI  
Rr, b  
Rd, b  
Bit Store from Register to T  
Bit load from T to Register  
Set Carry  
T
None  
C
C
N
N
Z
Clear Carry  
C ← 0  
Set Negative Flag  
N ← 1  
Clear Negative Flag  
Set Zero Flag  
N ← 0  
Z ← 1  
Clear Zero Flag  
Z ← 0  
Z
Global Interrupt Enable  
Global Interrupt Disable  
Set Signed Test Flag  
Clear Signed Test Flag  
Set Two’s Complement Overflow.  
Clear Two’s Complement Overflow  
Set T in SREG  
I ← 1  
I
CLI  
I ← 0  
I
SES  
CLS  
SEV  
CLV  
SET  
CLT  
SEH  
CLH  
S ← 1  
S
S
V
V
T
S ← 0  
V ← 1  
V ← 0  
T ← 1  
Clear T in SREG  
T ← 0  
T
Set Half Carry Flag in SREG  
Clear Half Carry Flag in SREG  
H ← 1  
H
H
H ← 0  
DATA TRANSFER INSTRUCTIONS  
MOV  
LDI  
LD  
Rd, Rr  
Rd, K  
Rd, X  
Rd, X+  
Rd, - X  
Rd, Y  
Rd, Y+  
Rd, - Y  
Rd, Z  
Rd, Z+  
Rd, -Z  
Rd, k  
X, Rr  
Copy Register  
Rd ← Rr  
Rd ← K  
Rd ← (X)  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
None  
1
1
Load Immediate  
Load Indirect  
1/2  
2
LD  
Load Indirect and Post-Increment  
Load Indirect and Pre-Decrement  
Load Indirect  
Rd ← (X), X ← X + 1  
X ← X - 1, Rd ← (X)  
Rd ← (Y)  
LD  
2/3  
1/2  
2
LD  
LD  
Load Indirect and Post-Increment  
Load Indirect and Pre-Decrement  
Load Indirect  
Rd ← (Y), Y ← Y + 1  
Y ← Y - 1, Rd ← (Y)  
Rd ← (Z)  
LD  
2/3  
1/2  
2
LD  
LD  
Load Indirect and Post-Increment  
Load Indirect and Pre-Decrement  
Store Direct from SRAM  
Store Indirect  
Rd ← (Z), Z ← Z+1  
Z ← Z - 1, Rd ← (Z)  
Rd ← (k)  
LD  
2/3  
1
LDS  
ST  
(X) ← Rr  
1
ST  
X+, Rr  
- X, Rr  
Y, Rr  
Store Indirect and Post-Increment  
Store Indirect and Pre-Decrement  
Store Indirect  
(X) ← Rr, X ← X + 1  
X ← X - 1, (X) ← Rr  
(Y) ← Rr  
1
ST  
2
ST  
1
ST  
Y+, Rr  
- Y, Rr  
Z, Rr  
Store Indirect and Post-Increment  
Store Indirect and Pre-Decrement  
Store Indirect  
(Y) ← Rr, Y ← Y + 1  
Y ← Y - 1, (Y) ← Rr  
(Z) ← Rr  
1
ST  
2
ST  
1
ST  
Z+, Rr  
-Z, Rr  
k, Rr  
Store Indirect and Post-Increment.  
Store Indirect and Pre-Decrement  
Store Direct to SRAM  
(Z) ← Rr, Z ← Z + 1  
Z ← Z - 1, (Z) ← Rr  
(k) ← Rr  
1
ST  
2
STS  
IN  
1
Rd, A  
A, Rr  
In from I/O Location  
Rd ← I/O (A)  
1
OUT  
PUSH  
POP  
Out to I/O Location  
I/O (A) ← Rr  
1
Rr  
Push Register on Stack  
Pop Register from Stack  
STACK ← Rr  
2
Rd  
Rd ← STACK  
2
MCU CONTROL INSTRUCTIONS  
BREAK  
Break  
None  
(see specific descr. for Break)  
1
1
1
1
NOP  
No Operation  
Sleep  
None  
None  
None  
SLEEP  
WDR  
(see specific descr. for Sleep)  
(see specific descr. for WDR)  
Watchdog Reset  
9
8127CS–AVR–10/09  
6. Ordering Information  
6.1  
ATtiny4  
Speed (MHz)  
Power Supply  
Ordering Code(2)  
Package(1)  
Operational Range  
Industrial  
12  
1.8 - 5.5V  
ATtiny4-TSHR(3)(4)  
6ST1  
(-40°C to 85°C)(4)  
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information  
and minimum quantities.  
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also  
Halide free and fully Green.  
3. Topside marking for ATtiny4: T4x (x stands for “die revision”).  
4. Bottomside marking for ATtiny4: zHzzz [H stands for (-40°C to 85°C)].  
Package Type  
6ST1  
6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)  
10  
ATtiny4/5/9/10  
8127CS–AVR–10/09  
ATtiny4/5/9/10  
6.2  
ATtiny5  
Speed (MHz)  
Power Supply  
Ordering Code(2)  
Package(1)  
Operational Range  
Industrial  
12  
1.8 - 5.5V  
ATtiny5-TSHR(3)(4)  
6ST1  
(-40°C to 85°C)(4)  
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information  
and minimum quantities.  
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also  
Halide free and fully Green.  
3. Topside marking for ATtiny5: T5x (x stands for “die revision”).  
4. Bottomside marking for ATtiny5: zHzzz [H stands for (-40°C to 85°C)].  
Package Type  
6ST1  
6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)  
11  
8127CS–AVR–10/09  
6.3  
ATtiny9  
Speed (MHz)  
Power Supply  
Ordering Code(2)  
Package(1)  
Operational Range  
Industrial  
12  
1.8 - 5.5V  
ATtiny9-TSHR(3)(4)  
6ST1  
(-40°C to 85°C)(4)  
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information  
and minimum quantities.  
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also  
Halide free and fully Green.  
3. Topside marking for ATtiny9: T9x (x stands for “die revision”).  
4. Bottomside marking for ATtiny9: zHzzz [H stands for (-40°C to 85°C)].  
Package Type  
6ST1  
6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)  
12  
ATtiny4/5/9/10  
8127CS–AVR–10/09  
ATtiny4/5/9/10  
6.4  
ATtiny10  
Speed (MHz)  
Power Supply  
Ordering Code(2)  
Package(1)  
Operational Range  
Industrial  
12  
1.8 - 5.5V  
ATtiny10-TSHR(3)(4)  
6ST1  
(-40°C to 85°C)(4)  
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information  
and minimum quantities.  
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also  
Halide free and fully Green.  
3. Topside marking for ATtiny10: T10x (x stands for “die revision”).  
4. Bottomside marking for ATtiny10: zHzzz [H stands for (-40°C to 85°C)].  
Package Type  
6ST1  
6-lead, 2.90 x 1.60 mm Plastic Small Outline Package (SOT23)  
13  
8127CS–AVR–10/09  
7. Packaging Information  
7.1  
6ST1  
D
5
A
6
4
A2  
A1  
E
E1  
A
Pin #1 ID  
C
0.10  
SEATING PLANE  
A
1
3
2
C
Side View  
b
e
Top View  
A2  
A
C
0.10  
SEATING PLANE  
c
0.25  
C
A1  
SEATING PLANE  
View A-A  
C
SEE VIEW B  
O
L
View B  
COMMON DIMENSIONS  
(Unit of Measure = mm)  
MIN  
–
MAX  
1.45  
0.15  
1.30  
3.00  
3.00  
1.75  
0.55  
NOM  
NOTE  
SYMBOL  
A
A1  
A2  
D
E
–
0
–
0.90  
2.80  
2.60  
1.50  
0.30  
–
2.90  
2.80  
1.60  
0.45  
0.95 BSC  
–
2
E1  
L
Notes: 1. This package is compliant with JEDEC specification MO-178 Variation AB  
2. Dimension D does not include mold Flash, protrusions or gate burrs.  
Mold Flash, protrustion or gate burrs shall not exceed 0.25 mm per end.  
3. Dimension b does not include dambar protrusion. Allowable dambar  
protrusion shall not cause the lead width to exceed the maximum  
b dimension by more than 0.08 mm  
e
b
0.30  
0.09  
0°  
0.50  
0.20  
8°  
3
c
–
θ
–
4. Die is facing down after trim/form.  
6/30/08  
GPC  
TAQ  
DRAWING NO.  
TITLE  
REV.  
6ST1, 6-lead, 2.90 x 1.60 mm Plastic Small Outline  
Package Drawing Contact:  
packagedrawings@atmel.com  
6ST1  
A
Package (SOT23)  
14  
ATtiny4/5/9/10  
8127CS–AVR–10/09  
ATtiny4/5/9/10  
8. Errata  
The revision letters in this section refer to the revision of the corresponding ATtiny4/5/9/10  
device.  
8.1  
ATtiny4  
8.1.1  
Rev. D  
• ESD HBM (ESD STM 5.1) level ±1000V  
• Lock bits re-programming  
1. ESD HBM (ESD STM 5.1) level ±1000V  
The device meets ESD HBM (ESD STM 5.1) level ±1000V.  
Problem Fix / Workaround  
Always use proper ESD protection measures (Class 1C) when handling integrated circuits  
before and during assembly.  
2. Lock bits re-programming  
Attempt to re-program Lock bits to present, or lower protection level (tampering attempt),  
causes erroneously one, random line of Flash program memory to get erased. The Lock bits  
will not get changed, as they should not.  
Problem Fix / Workaround  
Do not attempt to re-program Lock bits to present, or lower protection level.  
8.1.2  
Rev. A – C  
Not sampled.  
8.2  
ATtiny5  
8.2.1  
Rev. D  
• ESD HBM (ESD STM 5.1) level ±1000V  
• Lock bits re-programming  
1. ESD HBM (ESD STM 5.1) level ±1000V  
The device meets ESD HBM (ESD STM 5.1) level ±1000V.  
Problem Fix / Workaround  
Always use proper ESD protection measures (Class 1C) when handling integrated circuits  
before and during assembly.  
2. Lock bits re-programming  
Attempt to re-program Lock bits to present, or lower protection level (tampering attempt),  
causes erroneously one, random line of Flash program memory to get erased. The Lock bits  
will not get changed, as they should not.  
Problem Fix / Workaround  
Do not attempt to re-program Lock bits to present, or lower protection level.  
8.2.2  
Rev. A – C  
Not sampled.  
15  
8127CS–AVR–10/09  
8.3  
ATtiny9  
8.3.1  
Rev. D  
• ESD HBM (ESD STM 5.1) level ±1000V  
• Lock bits re-programming  
1. ESD HBM (ESD STM 5.1) level ±1000V  
The device meets ESD HBM (ESD STM 5.1) level ±1000V.  
Problem Fix / Workaround  
Always use proper ESD protection measures (Class 1C) when handling integrated circuits  
before and during assembly.  
2. Lock bits re-programming  
Attempt to re-program Lock bits to present, or lower protection level (tampering attempt),  
causes erroneously one, random line of Flash program memory to get erased. The Lock bits  
will not get changed, as they should not.  
Problem Fix / Workaround  
Do not attempt to re-program Lock bits to present, or lower protection level.  
8.3.2  
Rev. A – C  
Not sampled.  
8.4  
ATtiny10  
8.4.1  
Rev. C – D  
• ESD HBM (ESD STM 5.1) level ±1000V  
• Lock bits re-programming  
1. ESD HBM (ESD STM 5.1) level ±1000V  
The device meets ESD HBM (ESD STM 5.1) level ±1000V.  
Problem Fix / Workaround  
Always use proper ESD protection measures (Class 1C) when handling integrated circuits  
before and during assembly.  
2. Lock bits re-programming  
Attempt to re-program Lock bits to present, or lower protection level (tampering attempt),  
causes erroneously one, random line of Flash program memory to get erased. The Lock bits  
will not get changed, as they should not.  
Problem Fix / Workaround  
Do not attempt to re-program Lock bits to present, or lower protection level.  
8.4.2  
Rev. A – B  
Not sampled.  
16  
ATtiny4/5/9/10  
8127CS–AVR–10/09  
ATtiny4/5/9/10  
9. Datasheet Revision History  
9.1  
Rev. 8127C – 10/09  
1. Updated values and notes:  
– Table 16-1 in Section 16.2 “DC Characteristics” on page 116  
– Table 16-3 in Section 16.4 “Clock Characteristics” on page 118  
– Table 16-6 in Section 16.5.2 “VCC Level Monitor” on page 119  
– Table 16-9 in Section 16.8 “Serial Programming Characteristics” on page 121  
2. Updated Figure 16-1 in Section 16.3 “Speed Grades” on page 117  
3. Added Typical Characteristics Figure 17-36 in Section 17.2.7 “Analog Comparator Off-  
set” on page 140. Also, updated some other plots in Typical Characteristics.  
4. Added topside and bottomside marking notes in Section 6. “Ordering Information” on  
page 10, up to page 13  
5. Added ESD errata, see Section 8. “Errata” on page 15  
6. Added Lock bits re-programming errata, see Section 8. “Errata” on page 15  
9.2  
Rev. 8127B – 08/09  
1. Updated document template  
2. Expanded document to also cover devices ATtiny4, ATtiny5 and ATtiny9  
3. Added section:  
– “Comparison of ATtiny4, ATtiny5, ATtiny9 and ATtiny10” on page 4  
4. Updated sections:  
– “ADC Clock – clkADC” on page 18  
– “Starting from Idle / ADC Noise Reduction / Standby Mode” on page 20  
– “ADC Noise Reduction Mode” on page 24  
– “Analog to Digital Converter” on page 25  
– “SMCR – Sleep Mode Control Register” on page 25  
– “PRR – Power Reduction Register” on page 26  
– “Alternate Functions of Port B” on page 48  
– “Overview” on page 83  
– “Physical Layer of Tiny Programming Interface” on page 96  
– “Overview” on page 107  
– “ADC Characteristics (ATtiny5/10, only)” on page 120  
– “Supply Current of I/O Modules” on page 122  
– “Register Summary” on page 6  
– “Ordering Information” on page 10  
5. Added figure:  
– “Using an External Programmer for In-System Programming via TPI” on page 97  
6. Updated figure:  
– “Data Memory Map (Byte Addressing)” on page 15  
7. Added table:  
– “Number of Words and Pages in the Flash (ATtiny4/5)” on page 109  
17  
8127CS–AVR–10/09  
8. Updated tables:  
– “Active Clock Domains and Wake-up Sources in Different Sleep Modes” on page 23  
– “Reset and Interrupt Vectors” on page 35  
– “Number of Words and Pages in the Flash (ATtiny9/10)” on page 109  
– “Signature codes” on page 110  
9.3  
Rev. 8127A – 04/09  
1. Initial revision  
18  
ATtiny4/5/9/10  
8127CS–AVR–10/09  
ATtiny4/5/9/10  
19  
8127CS–AVR–10/09  
Headquarters  
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Atmel Corporation  
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8127CS–AVR–10/09  

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