ATTINY85V-10SH [ATMEL]
8-bit Microcontroller with 2/4/8KBytes In-System Programmable Flash; 8位微控制器与2/4 / 8K字节的系统内可编程闪存
| 型号： | ATTINY85V-10SH |
| 厂家： | 
ATMEL |
| 描述： | 8-bit Microcontroller with 2/4/8KBytes In-System Programmable Flash |
| 文件： | 总30页 (文件大小：728K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• Non-volatile Program and Data Memories
– 2/4/8K Bytes of In-System Programmable Program Memory Flash
• Endurance: 10,000 Write/Erase Cycles
– 128/256/512 Bytes In-System Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 128/256/512 Bytes Internal SRAM
8-bit
Microcontroller
with 2/4/8K
Bytes In-System
Programmable
Flash
– Programming Lock for Self-Programming Flash Program and EEPROM Data
Security
• Peripheral Features
– 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 8-bit High Speed Timer/Counter with Separate Prescaler
• 2 High Frequency PWM Outputs with Separate Output Compare Registers
• Programmable Dead Time Generator
– USI – Universal Serial Interface with Start Condition Detector
– 10-bit ADC
• 4 Single Ended Channels
ATtiny25/V
ATtiny45/V
ATtiny85/V *
• 2 Differential ADC Channel Pairs with Programmable Gain (1x, 20x)
• Temperature Measurement
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
* Preliminary
Summary
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
• I/O and Packages
– Six Programmable I/O Lines
– 8-pin PDIP, 8-pin SOIC, 20-pad QFN/MLF, and 8-pin TSSOP (only ATtiny45/V)
• Operating Voltage
– 1.8 - 5.5V for ATtiny25V/45V/85V
– 2.7 - 5.5V for ATtiny25/45/85
• Speed Grade
– ATtiny25V/45V/85V: 0 – 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny25/45/85: 0 – 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
• Industrial Temperature Range
• Low Power Consumption
– Active Mode:
• 1 MHz, 1.8V: 300 µA
– Power-down Mode:
• 0.1 µA at 1.8V
Rev. 2586LS–AVR–06/10
1. Pin Configurations
Figure 1-1. Pinout ATtiny25/45/85
PDIP/SOIC/TSSOP
(PCINT5/RESET/ADC0/dW) PB5
1
2
3
4
8
7
6
5
VCC
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
GND
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
NOTE: TSSOP only for ATtiny45/V
QFN/MLF
1
15
14
13
12
11
(PCINT5/RESET/ADC0/dW) PB5
(PCINT3/XTAL1/CLKI/OC1B/ADC3) PB3
VCC
2
3
4
5
PB2 (SCK/USCK/SCL/ADC1/T0/INT0/PCINT2)
DNC
PB1 (MISO/DO/AIN1/OC0B/OC1A/PCINT1)
PB0 (MOSI/DI/SDA/AIN0/OC0A/OC1A/AREF/PCINT0)
DNC
DNC
(PCINT4/XTAL2/CLKO/OC1B/ADC2) PB4
NOTE: Bottom pad should be soldered to ground.
DNC: Do Not Connect
1.1
Pin Descriptions
1.1.1
VCC
Supply voltage.
1.1.2
1.1.3
GND
Ground.
Port B (PB5:PB0)
Port B is a 6-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The
Port B output buffers have symmetrical drive characteristics with both high sink and source
capability. As inputs, Port B pins that are externally pulled low will source current if the pull-up
2
ATtiny25/45/85
2586L–AVR–06/10
ATtiny25/45/85
resistors are activated. The Port B pins are tri-stated when a reset condition becomes active,
even if the clock is not running.
Port B also serves the functions of various special features of the ATtiny25/45/85 as listed in
“Alternate Functions of Port B” on page 62.
On ATtiny25, the programmable I/O ports PB3 and PB4 (pins 2 and 3) are exchanged in
ATtiny15 Compatibility Mode for supporting the backward compatibility with ATtiny15.
1.1.4
RESET
Reset input. A low level on this pin for longer than the minimum pulse length will generate a
reset, even if the clock is not running and provided the reset pin has not been disabled. The min-
imum pulse length is given in Table 21-4 on page 170. Shorter pulses are not guaranteed to
generate a reset.
The reset pin can also be used as a (weak) I/O pin.
3
2586L–AVR–06/10
2. Overview
The ATtiny25/45/85 is a low-power CMOS 8-bit microcontroller based on the AVR enhanced
RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny25/45/85
achieves throughputs approaching 1 MIPS per MHz allowing the system designer to optimize
power consumption versus processing speed.
2.1
Block Diagram
Figure 2-1. Block Diagram
8-BIT DATABUS
CALIBRATED
INTERNAL
OSCILLATOR
PROGRAM
COUNTER
STACK
POINTER
WATCHDOG
TIMER
TIMING AND
CONTROL
VCC
MCU CONTROL
REGISTER
PROGRAM
FLASH
SRAM
MCU STATUS
REGISTER
GND
GENERAL
PURPOSE
REGISTERS
INSTRUCTION
REGISTER
TIMER/
COUNTER0
X
Y
Z
INSTRUCTION
DECODER
TIMER/
COUNTER1
UNIVERSAL
SERIAL
INTERFACE
CONTROL
LINES
ALU
INTERRUPT
UNIT
STATUS
REGISTER
PROGRAMMING
LOGIC
DATA
EEPROM
OSCILLATORS
DATA REGISTER
PORT B
DATA DIR.
REG.PORT B
ADC /
ANALOG COMPARATOR
PORT B DRIVERS
RESET
PB[0:5]
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
4
ATtiny25/45/85
2586L–AVR–06/10
ATtiny25/45/85
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATtiny25/45/85 provides the following features: 2/4/8K bytes of In-System Programmable
Flash, 128/256/512 bytes EEPROM, 128/256/256 bytes SRAM, 6 general purpose I/O lines, 32
general purpose working registers, one 8-bit Timer/Counter with compare modes, one 8-bit high
speed Timer/Counter, Universal Serial Interface, Internal and External Interrupts, a 4-channel,
10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three software select-
able power saving modes. Idle mode stops the CPU while allowing the SRAM, Timer/Counter,
ADC, Analog Comparator, and Interrupt system to continue functioning. Power-down mode
saves the register contents, disabling all chip functions until the next Interrupt or Hardware
Reset. ADC Noise Reduction mode stops the CPU and all I/O modules except ADC, to minimize
switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny25/45/85 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators and Evaluation kits.
5
2586L–AVR–06/10
3. About
3.1
3.2
Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
Code Examples
This documentation contains simple code examples that briefly show how to use various parts of
the device. These code examples assume that the part specific header file is included before
compilation. Be aware that not all C compiler vendors include bit definitions in the header files
and interrupt handling in C is compiler dependent. Please confirm with the C compiler documen-
tation for more details.
For I/O Registers located in the extended I/O map, “IN”, “OUT”, “SBIS”, “SBIC”, “CBI”, and “SBI”
instructions must be replaced with instructions that allow access to extended I/O. Typically, this
means “LDS” and “STS” combined with “SBRS”, “SBRC”, “SBR”, and “CBR”. Note that not all
AVR devices include an extended I/O map.
3.3
Data Retention
Reliability Qualification results show that the projected data retention failure rate is much less
than 1 PPM over 20 years at 85°C or 100 years at 25°C.
6
ATtiny25/45/85
2586L–AVR–06/10
ATtiny25/45/85
4. Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x3F
0x3E
0x3D
0x3C
0x3B
0x3A
0x39
0x38
0x37
0x36
0x35
0x34
0x33
0x32
0x31
0x30
0x2F
0x2E
0x2D
0x2C
0x2B
0x2A
0x29
0x28
0x27
0x26
0x25
0x24
0x23
0x22
0x21
0x20
0x1F
0x1E
0x1D
0x1C
0x1B
0x1A
0x19
0x18
0x17
0x16
0x15
0x14
0x13
0x12
0x11
0x10
0x0F
0x0E
0x0D
0x0C
0x0B
0x0A
0x09
0x08
0x07
0x06
0x05
0x04
0x03
0x02
0x01
0x00
SREG
I
–
T
–
H
–
S
–
V
–
N
–
Z
C
page 8
page 11
page 11
SPH
SP9
SP1
SP8
SP0
SPL
SP7
SP6
SP5
SP4
SP3
SP2
Reserved
GIMSK
GIFR
–
–
–
–
–
–
–
INT0
INTF0
OCIE1A
OCF1A
–
PCIE
PCIF
–
–
–
–
–
page 53
page 53
–
–
–
–
–
TIMSK
OCIE1B
OCF1B
RSIG
OCIE0A
OCF0A
CTPB
OCIE0B
OCF0B
RFLB
TOIE1
TOV1
PGWRT
TOIE0
TOV0
PGERS
–
–
pages 84, 106
page 84
TIFR
SPMCSR
Reserved
MCUCR
MCUSR
TCCR0B
TCNT0
OSCCAL
TCCR1
TCNT1
OCR1A
OCR1C
GTCCR
OCR1B
TCCR0A
OCR0A
OCR0B
PLLCSR
CLKPR
DT1A
SPMEN
page 149
BODS
–
PUD
–
SE
–
SM1
SM0
BODSE
BORF
CS02
ISC01
EXTRF
CS01
ISC00
PORF
CS00
pages 38, 52, 66
page 47,
–
–
WDRF
WGM02
FOC0A
FOC0B
–
page 82
Timer/Counter0
page 83
Oscillator Calibration Register
page 32
CTC1
PWM1A
COM1A1
COM1A0
CS13
CS12
CS11
CS10
pages 92, 103
pages 94, 105
pages 95, 105
pages 95, 106
pages 80, 93, 105
page 95
Timer/Counter1
Timer/Counter1 Output Compare Register A
Timer/Counter1 Output Compare Register C
TSM
PWM1B
COM1B1
Timer/Counter1 Output Compare Register B
COM0B1 COM0B0
COM1B0
FOC1B
FOC1A
PSR1
PSR0
COM0A1
COM0A0
–
WGM01
WGM00
page 80
Timer/Counter0 – Output Compare Register A
Timer/Counter0 – Output Compare Register B
page 83
page 84
LSM
CLKPCE
DT1AH3
DT1BH3
-
–
–
–
–
PCKE
CLKPS2
DT1AL2
DT1BL2
-
PLLE
PLOCK
CLKPS0
DT1AL0
DT1BL0
DTPS10
pages 97, 107
page 33
–
–
–
CLKPS3
DT1AL3
DT1BL3
-
CLKPS1
DT1AL1
DT1BL1
DTPS11
DT1AH2
DT1BH2
-
DT1AH1
DT1BH1
-
DT1AH0
DT1BH0
-
page 110
page 110
page 109
page 144
page 47
DT1B
DTPS1
DWDR
DWDR[7:0]
WDTCR
PRR
WDIF
–
WDIE
WDP3
WDCE
WDE
WDP2
WDP1
PRUSI
WDP0
PRADC
EEAR8
EEAR0
PRTIM1
PRTIM0
page 37
EEARH
EEARL
EEDR
page 20
EEAR7
–
EEAR6
–
EEAR5
EEPM1
EEAR4
EEAR3
EEAR2
EEMPE
EEAR1
EEPE
page 20
EEPROM Data Register
page 20
EECR
EEPM0
EERIE
EERE
page 21
Reserved
Reserved
Reserved
PORTB
DDRB
–
–
–
–
–
–
–
–
–
–
–
–
–
PORTB5
DDB5
PORTB4
DDB4
PORTB3
DDB3
PORTB2
DDB2
PORTB1
DDB1
PORTB0
DDB0
page 66
page 66
PINB
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
page 66
PCMSK
DIDR0
PCINT5
ADC0D
PCINT4
ADC2D
PCINT3
ADC3D
PCINT2
ADC1D
PCINT1
AIN1D
PCINT0
AIN0D
page 54
pages 125, 142
page 10
GPIOR2
GPIOR1
GPIOR0
USIBR
General Purpose I/O Register 2
General Purpose I/O Register 1
General Purpose I/O Register 0
USI Buffer Register
page 10
page 10
page 118
page 118
page 119
page 120
USIDR
USI Data Register
USISR
USISIF
USISIE
USIOIF
USIOIE
USIPF
USIDC
USICNT3
USICS1
USICNT2
USICS0
USICNT1
USICLK
USICNT0
USITC
USICR
USIWM1
USIWM0
Reserved
Reserved
Reserved
Reserved
ACSR
–
–
–
–
ACD
REFS1
ADEN
ACBG
REFS0
ADSC
ACO
ACI
REFS2
ADIF
ACIE
MUX3
ADIE
–
ACIS1
MUX1
ADPS1
ACIS0
MUX0
ADPS0
page 124
page 138
ADMUX
ADCSRA
ADCH
ADLAR
ADATE
MUX2
ADPS2
page 140
ADC Data Register High Byte
ADC Data Register Low Byte
page 141
ADCL
page 141
ADCSRB
Reserved
Reserved
Reserved
BIN
ACME
IPR
–
–
ADTS2
ADTS1
ADTS0
pages 124, 141
–
–
–
7
2586L–AVR–06/10
Note:
1. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
2. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
3. Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most other AVRs, the CBI and SBI
instructions will only operation the specified bit, and can therefore be used on registers containing such Status Flags. The
CBI and SBI instructions work with registers 0x00 to 0x1F only.
8
ATtiny25/45/85
2586L–AVR–06/10
ATtiny25/45/85
5. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add two Registers
Rd ← Rd + Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ← Rd + Rr + C
Rdh:Rdl ← Rdh:Rdl + K
Rd ← Rd - Rr
Rd ← Rd - K
Rd ← Rd - Rr - C
Rd ← Rd - K - C
Rdh:Rdl ← Rdh:Rdl - K
Rd ← Rd • Rr
Rd ← Rd • K
Z,N,V
Rd ← Rd v Rr
Z,N,V
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
Rd ← Rd v K
Z,N,V
EOR
COM
NEG
SBR
CBR
INC
Rd ← Rd ⊕ Rr
Rd ← 0xFF − Rd
Rd ← 0x00 − Rd
Rd ← Rd v K
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Rd
Two’s Complement
Rd,K
Rd,K
Rd
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd ← Rd • (0xFF - K)
Rd ← Rd + 1
Z,N,V
Z,N,V
DEC
TST
Rd
Decrement
Rd ← Rd − 1
Z,N,V
Rd
Test for Zero or Minus
Clear Register
Rd ← Rd • Rd
Rd ← Rd ⊕ Rd
Rd ← 0xFF
Z,N,V
CLR
SER
Rd
Z,N,V
Rd
Set Register
None
BRANCH INSTRUCTIONS
RJMP
IJMP
k
k
Relative Jump
PC ← PC + k + 1
None
None
None
None
None
I
2
2
Indirect Jump to (Z)
PC ← Z
RCALL
ICALL
RET
Relative Subroutine Call
Indirect Call to (Z)
PC ← PC + k + 1
3
PC ← Z
3
Subroutine Return
PC ← STACK
4
RETI
Interrupt Return
PC ← STACK
4
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC ← PC + 2 or 3
Rd − Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
Rd,Rr
CPC
Rd,Rr
Compare with Carry
Rd − Rr − C
1
CPI
Rd,K
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd − K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b)=0) PC ← PC + 2 or 3
if (Rr(b)=1) PC ← PC + 2 or 3
if (P(b)=0) PC ← PC + 2 or 3
if (P(b)=1) PC ← PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ← PC + k + 1
if (Z = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 0) then PC ← PC + k + 1
if (C = 1) then PC ← PC + k + 1
if (N = 1) then PC ← PC + k + 1
if (N = 0) then PC ← PC + k + 1
if (N ⊕ V= 0) then PC ← PC + k + 1
if (N ⊕ V= 1) then PC ← PC + k + 1
if (H = 1) then PC ← PC + k + 1
if (H = 0) then PC ← PC + k + 1
if (T = 1) then PC ← PC + k + 1
if (T = 0) then PC ← PC + k + 1
if (V = 1) then PC ← PC + k + 1
if (V = 0) then PC ← PC + k + 1
if ( I = 1) then PC ← PC + k + 1
if ( I = 0) then PC ← PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
Rr, b
P, b
P, b
s, k
s, k
k
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
k
Branch if Not Equal
k
Branch if Carry Set
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
k
k
k
Branch if Minus
k
Branch if Plus
k
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
k
k
k
k
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
k
k
k
k
BIT AND BIT-TEST INSTRUCTIONS
SBI
P,b
P,b
Rd
Rd
Rd
Set Bit in I/O Register
Clear Bit in I/O Register
Logical Shift Left
I/O(P,b) ← 1
None
2
2
1
1
1
CBI
LSL
LSR
ROL
I/O(P,b) ← 0
None
Rd(n+1) ← Rd(n), Rd(0) ← 0
Rd(n) ← Rd(n+1), Rd(7) ← 0
Rd(0)←C,Rd(n+1)← Rd(n),C←Rd(7)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Logical Shift Right
Rotate Left Through Carry
9
2586L–AVR–06/10
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ROR
Rd
Rotate Right Through Carry
Rd(7)←C,Rd(n)← Rd(n+1),C←Rd(0)
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Rd
Rd
s
Arithmetic Shift Right
Swap Nibbles
Rd(n) ← Rd(n+1), n=0..6
Z,C,N,V
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
None
Flag Set
SREG(s) ← 1
SREG(s) ← 0
T ← Rr(b)
Rd(b) ← T
C ← 1
SREG(s)
s
Flag Clear
SREG(s)
Rr, b
Rd, b
Bit Store from Register to T
Bit load from T to Register
Set Carry
T
None
C
C
N
N
Z
Clear Carry
C ← 0
Set Negative Flag
N ← 1
Clear Negative Flag
Set Zero Flag
N ← 0
Z ← 1
Clear Zero Flag
Z ← 0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
I ← 1
I
CLI
I ← 0
I
SES
CLS
SEV
CLV
SET
CLT
SEH
CLH
S ← 1
S
S
V
V
T
S ← 0
V ← 1
V ← 0
T ← 1
Clear T in SREG
T ← 0
T
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H ← 1
H
H
H ← 0
DATA TRANSFER INSTRUCTIONS
MOV
MOVW
LDI
LD
Rd, Rr
Rd, Rr
Rd, K
Move Between Registers
Copy Register Word
Rd ← Rr
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
Rd+1:Rd ← Rr+1:Rr
Load Immediate
Rd ← K
Rd, X
Load Indirect
Rd ← (X)
LD
Rd, X+
Rd, - X
Rd, Y
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Rd ← (X), X ← X + 1
X ← X - 1, Rd ← (X)
Rd ← (Y)
LD
LD
LD
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Rd ← (Y), Y ← Y + 1
Y ← Y - 1, Rd ← (Y)
Rd ← (Y + q)
Rd ← (Z)
LD
LDD
LD
LD
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Rd ← (Z), Z ← Z+1
Z ← Z - 1, Rd ← (Z)
Rd ← (Z + q)
Rd ← (k)
LD
LDD
LDS
ST
X, Rr
(X) ← Rr
ST
X+, Rr
- X, Rr
Y, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
(X) ← Rr, X ← X + 1
X ← X - 1, (X) ← Rr
(Y) ← Rr
ST
ST
ST
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
(Y) ← Rr, Y ← Y + 1
Y ← Y - 1, (Y) ← Rr
(Y + q) ← Rr
ST
STD
ST
(Z) ← Rr
ST
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
(Z) ← Rr, Z ← Z + 1
Z ← Z - 1, (Z) ← Rr
(Z + q) ← Rr
ST
STD
STS
LPM
LPM
LPM
SPM
IN
(k) ← Rr
R0 ← (Z)
Rd, Z
Rd ← (Z)
Rd, Z+
Rd ← (Z), Z ← Z+1
(z) ← R1:R0
Rd, P
P, Rr
Rr
Rd ← P
1
1
2
2
OUT
PUSH
POP
Out Port
P ← Rr
Push Register on Stack
Pop Register from Stack
STACK ← Rr
Rd ← STACK
Rd
MCU CONTROL INSTRUCTIONS
NOP
No Operation
Sleep
None
None
None
None
1
1
SLEEP
WDR
(see specific descr. for Sleep function)
(see specific descr. for WDR/Timer)
For On-chip Debug Only
Watchdog Reset
Break
1
BREAK
N/A
10
ATtiny25/45/85
2586L–AVR–06/10
ATtiny25/45/85
6. Ordering Information
6.1
ATtiny25
Speed (MHz) (3)
Power Supply
Ordering Code (1)
Package (2)
Operational Range
ATtiny25V-10PU
ATtiny25V-10SU
ATtiny25V-10SH
ATtiny25V-10SSU
ATtiny25V-10SSH
ATtiny25V-10MU
8P3
8S2
8S2
S8S1
S8S1
20M1
Industrial
10
20
1.8 - 5.5V
(-40°C to +85°C) (4)
ATtiny25-20PU
ATtiny25-20SU
ATtiny25-20SH
ATtiny25-20SSU
ATtiny25-20SSH
ATtiny25-20MU
8P3
8S2
8S2
S8S1
S8S1
20M1
Industrial
2.7 - 5.5V
(-40°C to +85°C) (4)
ATtiny25V-10SSN
ATtiny25V-10SSNR
S8S1
S8S1
Industrial
10
20
1.8 - 5.5V
2.7 - 5.5V
(-40°C to +105°C) (5)
ATtiny25-20SSN
ATtiny25-20SSNR
S8S1
S8S1
Industrial
(-40°C to +105°C) (5)
Notes: 1. Code indicators:
– H: NiPdAu lead finish
– U or N: matte tin
– R: tape & reel
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-
ous Substances (RoHS).
3. For Speed vs. VCC, see 21.3 “Speed” on page 168.
4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-
tion and minimum quantities.
5. For Typical and Electrical characteristics for this device please consult Appendix A, ATtiny25/V Specification at 105°C.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.200" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
8-lead, 0.150" Wide, Plastic Gull-Wing Small Outline (JEDEC SOIC)
20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
S8S1
20M1
11
2586L–AVR–06/10
6.2
ATtiny45
Speed (MHz) (3)
Power Supply
Ordering Code (1)
Package (2)
Operational Range
ATtiny45V-10PU
ATtiny45V-10SU
ATtiny45V-10SH
ATtiny45V-10XU
ATtiny45V-10XUR
ATtiny45V-10MU
8P3
8S2
8S2
8X
8X
20M1
Industrial
10
20
1.8 - 5.5V
(-40°C to +85°C) (4)
ATtiny45-20PU
ATtiny45-20SU
ATtiny45-20SH
ATtiny45-20XU
ATtiny45-20XUR
ATtiny45-20MU
8P3
8S2
8S2
8X
8X
20M1
Industrial
2.7 - 5.5V
(-40°C to +85°C) (4)
Notes: 1. Code indicators:
– H: NiPdAu lead finish
– U: matte tin
– R: tape & reel
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-
ous Substances (RoHS).
3. For Speed vs. VCC, see 21.3 “Speed” on page 168.
4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-
tion and minimum quantities.
Package Type
8P3
8S2
8X
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8-lead, 0.200" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
8-lead, 4.4 mm Wide, Plastic Thin Shrink Small Outline Package (TSSOP)
20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
20M1
12
ATtiny25/45/85
2586L–AVR–06/10
ATtiny25/45/85
6.3
ATtiny85
Speed (MHz) (3)
Power Supply
Ordering Code (1)
Package (2)
Operational Range
ATtiny85V-10PU
ATtiny85V-10SU
ATtiny85V-10SH
ATtiny85V-10MU
8P3
8S2
8S2
20M1
Industrial
10
20
1.8 - 5.5V
(-40°C to +85°C) (4)
ATtiny85-20PU
ATtiny85-20SU
ATtiny85-20SH
ATtiny85-20MU
8P3
8S2
8S2
20M1
Industrial
2.7 - 5.5V
(-40°C to +85°C) (4)
Notes: 1. Code indicators:
– H: NiPdAu lead finish
– U: matte tin
2. All packages are Pb-free, halide-free and fully green and they comply with the European directive for Restriction of Hazard-
ous Substances (RoHS).
3. For Speed vs. VCC, see 21.3 “Speed” on page 168.
4. These devices can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering informa-
tion and minimum quantities.
Package Type
8P3
8-lead, 0.300" Wide, Plastic Dual Inline Package (PDIP)
8S2
8-lead, 0.200" Wide, Plastic Gull-Wing Small Outline (EIAJ SOIC)
20-pad, 4 x 4 x 0.8 mm Body, Quad Flat No-Lead/Micro Lead Frame Package (QFN/MLF)
20M1
13
2586L–AVR–06/10
7. Packaging Information
7.1
8P3
E
1
E1
N
Top View
c
eA
End View
COMMON DIMENSIONS
(Unit of Measure = inches)
D
e
MIN
MAX
NOM
NOTE
SYMBOL
D1
A2 A
A
0.210
0.195
0.022
0.070
0.045
0.014
0.400
2
A2
b
0.115
0.014
0.045
0.030
0.008
0.355
0.005
0.300
0.240
0.130
0.018
0.060
0.039
0.010
0.365
5
6
6
b2
b3
c
D
3
3
4
3
b2
L
D1
E
b3
4 PLCS
0.310
0.250
0.325
0.280
b
E1
e
0.100 BSC
0.300 BSC
0.130
Side View
eA
L
4
2
0.115
0.150
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-001, Variation BA for additional information.
2. Dimensions A and L are measured with the package seated in JEDEC seating plane Gauge GS-3.
3. D, D1 and E1 dimensions do not include mold Flash or protrusions. Mold Flash or protrusions shall not exceed 0.010 inch.
4. E and eA measured with the leads constrained to be perpendicular to datum.
5. Pointed or rounded lead tips are preferred to ease insertion.
6. b2 and b3 maximum dimensions do not include Dambar protrusions. Dambar protrusions shall not exceed 0.010 (0.25 mm).
01/09/02
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8P3, 8-lead, 0.300" Wide Body, Plastic Dual
In-line Package (PDIP)
8P3
B
R
14
ATtiny25/45/85
2586L–AVR–06/10
ATtiny25/45/85
7.2
8S2
C
1
E
E1
L
N
θ
TOP VIEW
ENNDD VVIIEEWW
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.70
0.05
0.35
0.15
5.13
5.18
7.70
0.51
0°
MAX
2.16
0.25
0.48
0.35
5.35
5.40
8.26
0.85
8°
NOM
NOTE
SYMBOL
A1
A
A1
b
4
4
C
D
E1
E
D
2
L
SIDE VIEW
θ
e
1.27 BSC
3
Notes: 1. This drawing is for general information only; refer to EIAJ Drawing EDR-7320 for additional information.
2. Mismatch of the upper and lower dies and resin burrs aren't included.
3. Determines the true geometric position.
4. Values b,C apply to plated terminal. The standard thickness of the plating layer shall measure between 0.007 to .021 mm.
4/15/08
GPC
DRAWING NO.
TITLE
REV.
8S2, 8-lead, 0.208” Body, Plastic Small
Outline Package (EIAJ)
Package Drawing Contact:
packagedrawings@atmel.com
STN
8S2
F
15
2586L–AVR–06/10
7.3
S8S1
1
E1 E
N
Top View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
5.79
3.81
1.35
0.1
MAX
6.20
3.99
1.75
0.25
4.98
0.25
0.51
1.27
NOM
NOTE
SYMBOL
A1
E
D
E1
A
Side View
A1
D
C
b
4.80
0.17
0.31
0.4
L
L
End View
e
1.27 BSC
0o
8o
Notes: 1. This drawing is for general information only; refer to JEDEC Drawing MS-012 for proper dimensions, tolerances, datums,etc.
7/28/03
TITLE
DRAWING NO.
REV.
S8S1, 8-lead, 0.150" Wide Body, Plastic Gull Wing Small
Outline (JEDEC SOIC)
2325 Orchard Parkway
San Jose, CA 95131
S8S1
A
R
16
ATtiny25/45/85
2586L–AVR–06/10
ATtiny25/45/85
7.4
8X
C
1
End View
E
E1
L
Ø
Top View
e
b
COMMON DIMENSIONS
(Unit of Measure = mm)
A
MIN
1.05
0.05
0.25
–
MAX
1.20
0.15
0.30
–
NOM
1.10
0.10
–
NOTE
SYMBOL
A1
A
A1
b
C
D
E1
E
0.127
3.05
4.40
6.40
0.65 TYP
0.60
–
2.90
4.30
6.20
3.10
4.50
6.60
D
Side View
e
L
0.50
0o
0.70
8o
Ø
Note: These drawings are for general information only. Refer to JEDEC Drawing MO-153AC.
4/14/05
TITLE
DRAWING NO.
REV.
2325 Orchard Parkway
San Jose, CA 95131
8X, 8-lead, 4.4 mm Body Width, Plastic Thin Shrink
8X
A
R
Small Outline Package (TSSOP)
17
2586L–AVR–06/10
7.5
20M1
D
1
2
Pin 1 ID
SIDE VIEW
E
3
TOP VIEW
A2
A1
D2
A
0.08
C
1
2
Pin #1
Notch
(0.20 R)
COMMON DIMENSIONS
(Unit of Measure = mm)
3
E2
MIN
0.70
–
MAX
0.80
0.05
b
NOM
0.75
NOTE
SYMBOL
A
A1
A2
b
0.01
L
0.20 REF
0.23
0.18
2.45
2.45
0.35
0.30
2.75
2.75
0.55
e
D
4.00 BSC
2.60
D2
E
BOTTOM VIEW
4.00 BSC
2.60
E2
e
0.50 BSC
0.40
Reference JEDEC Standard MO-220, Fig. 1 (SAW Singulation) WGGD-5.
Note:
L
10/27/04
DRAWING NO. REV.
20M1
TITLE
2325 Orchard Parkway
San Jose, CA 95131
20M1, 20-pad, 4 x 4 x 0.8 mm Body, Lead Pitch 0.50 mm,
2.6 mm Exposed Pad, Micro Lead Frame Package (MLF)
A
R
18
ATtiny25/45/85
2586L–AVR–06/10
ATtiny25/45/85
8. Errata
8.1
Errata ATtiny25
The revision letter in this section refers to the revision of the ATtiny25 device.
8.1.1
8.1.2
Rev D and E
Rev B and C
No known errata.
• EEPROM read may fail at low supply voltage / low clock frequency
1. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in
invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1 MHz and supply voltage is below
2V. If operating frequency can not be raised above 1 MHz then supply voltage should be
more than 3V. Similarly, if supply voltage can not be raised above 2V then operating fre-
quency should be more than 2 MHz.
This feature is known to be temperature dependent but it has not been characterised.
Guidelines are given for room temperature, only.
8.1.3
Rev A
Not sampled.
19
2586L–AVR–06/10
8.2
Errata ATtiny45
The revision letter in this section refers to the revision of the ATtiny45 device.
8.2.1
8.2.2
Rev F and G
Rev D and E
No known errata
• EEPROM read may fail at low supply voltage / low clock frequency
1. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in
invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1 MHz and supply voltage is below
2V. If operating frequency can not be raised above 1 MHz then supply voltage should be
more than 3V. Similarly, if supply voltage can not be raised above 2V then operating fre-
quency should be more than 2 MHz.
This feature is known to be temperature dependent but it has not been characterised.
Guidelines are given for room temperature, only.
8.2.3
Rev B and C
• PLL not locking
• EEPROM read from application code does not work in Lock Bit Mode 3
• EEPROM read may fail at low supply voltage / low clock frequency
• Timer Counter 1 PWM output generation on OC1B- XOC1B does not work correctly
1. PLL not locking
When at frequencies below 6.0 MHz, the PLL will not lock
Problem fix / Workaround
When using the PLL, run at 6.0 MHz or higher.
2. EEPROM read from application code does not work in Lock Bit Mode 3
When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does
not work from the application code.
Problem Fix/Work around
Do not set Lock Bit Protection Mode 3 when the application code needs to read from
EEPROM.
3. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in
invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1 MHz and supply voltage is below
2V. If operating frequency can not be raised above 1 MHz then supply voltage should be
20
ATtiny25/45/85
2586L–AVR–06/10
ATtiny25/45/85
more than 3V. Similarly, if supply voltage can not be raised above 2V then operating fre-
quency should be more than 2 MHz.
This feature is known to be temperature dependent but it has not been characterised.
Guidelines are given for room temperature, only.
4. Timer Counter 1 PWM output generation on OC1B – XOC1B does not work correctly
Timer Counter1 PWM output OC1B-XOC1B does not work correctly. Only in the case when
the control bits, COM1B1 and COM1B0 are in the same mode as COM1A1 and COM1A0,
respectively, the OC1B-XOC1B output works correctly.
Problem Fix/Work around
The only workaround is to use same control setting on COM1A[1:0] and COM1B[1:0] control
bits, see table 14-4 in the data sheet. The problem has been fixed for Tiny45 rev D.
8.2.4
Rev A
• Too high power down power consumption
• DebugWIRE looses communication when single stepping into interrupts
• PLL not locking
• EEPROM read from application code does not work in Lock Bit Mode 3
• EEPROM read may fail at low supply voltage / low clock frequency
1. Too high power down power consumption
Three situations will lead to a too high power down power consumption. These are:
– An external clock is selected by fuses, but the I/O PORT is still enabled as an output.
– The EEPROM is read before entering power down.
– VCC is 4.5 volts or higher.
Problem fix / Workaround
– When using external clock, avoid setting the clock pin as Output.
– Do not read the EEPROM if power down power consumption is important.
– Use VCC lower than 4.5 Volts.
2. DebugWIRE looses communication when single stepping into interrupts
When receiving an interrupt during single stepping, debugwire will loose
communication.
Problem fix / Workaround
– When singlestepping, disable interrupts.
– When debugging interrupts, use breakpoints within the interrupt routine, and run into
the interrupt.
3. PLL not locking
When at frequencies below 6.0 MHz, the PLL will not lock
Problem fix / Workaround
When using the PLL, run at 6.0 MHz or higher.
4. EEPROM read from application code does not work in Lock Bit Mode 3
21
2586L–AVR–06/10
When the Memory Lock Bits LB2 and LB1 are programmed to mode 3, EEPROM read does
not work from the application code.
Problem Fix/Work around
Do not set Lock Bit Protection Mode 3 when the application code needs to read from
EEPROM.
5. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in
invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1 MHz and supply voltage is below
2V. If operating frequency can not be raised above 1 MHz then supply voltage should be
more than 3V. Similarly, if supply voltage can not be raised above 2V then operating fre-
quency should be more than 2 MHz.
This feature is known to be temperature dependent but it has not been characterised.
Guidelines are given for room temperature, only.
22
ATtiny25/45/85
2586L–AVR–06/10
ATtiny25/45/85
8.3
Errata ATtiny85
The revision letter in this section refers to the revision of the ATtiny85 device.
8.3.1
8.3.2
Rev B and C
Rev A
No known errata.
• EEPROM read may fail at low supply voltage / low clock frequency
1. EEPROM read may fail at low supply voltage / low clock frequency
Trying to read EEPROM at low clock frequencies and/or low supply voltage may result in
invalid data.
Problem Fix/Workaround
Do not use the EEPROM when clock frequency is below 1 MHz and supply voltage is below
2V. If operating frequency can not be raised above 1 MHz then supply voltage should be
more than 3V. Similarly, if supply voltage can not be raised above 2V then operating fre-
quency should be more than 2 MHz.
This feature is known to be temperature dependent but it has not been characterised.
Guidelines are given for room temperature, only.
23
2586L–AVR–06/10
9. Datasheet Revision History
9.1
Rev. 2586L-06/10
1. Added:
– TSSOP for ATtiny45 in “Features” on page 1, Pinout Figure 1-1 on page 2, Ordering
Information in Section 6.2 “ATtiny45” on page 12, and Packaging Information in
Section 7.4 “8X” on page 17
– Table 6-11, “Capacitance of Low-Frequency Crystal Oscillator,” on page 29
– Figure 22-36 on page 196 and Figure 22-37 on page 196, Typical Characteristics
plots for Bandgap Voltage vs. VCC and Temperature
– Extended temperature in Section 6.1 “ATtiny25” on page 11, Ordering Information
– Tape & reel part numbers in Ordering Information, in Section 6.1 “ATtiny25” on page
11 and Section 6.2 “ATtiny45” on page 12
2. Updated:
– “Features” on page 1, removed Preliminary from ATtiny25
– Section 8.4.2 “Code Example” on page 46
– “PCMSK – Pin Change Mask Register” on page 54, Bit Descriptions
– “TCCR1 – Timer/Counter1 Control Register” on page 92 and “GTCCR – General
Timer/Counter1 Control Register” on page 93, COM bit descriptions clarified
– Section 20.3.2 “Calibration Bytes” on page 154, frequencies (8 MHz, 6.4 MHz)
– Table 20-11, “Minimum Wait Delay Before Writing the Next Flash or EEPROM
Location,” on page 157, value for tWD_ERASE
– Table 20-16, “High-voltage Serial Programming Instruction Set for ATtiny25/45/85,”
on page 163
– Table 21-1, “DC Characteristics. TA = -40°C to +85°C,” on page 166, notes adjusted
– Table 21-11, “Serial Programming Characteristics, TA = -40°C to +85°C, VCC = 1.8 -
5.5V (Unless Otherwise Noted),” on page 175, added tSLIV
– Bit syntax throughout the datasheet, e.g. from CS02:0 to CS0[2:0].
9.2
Rev. 2586K-01/08
1. Updated Document Template.
2. Added Sections:
– “Data Retention” on page 6
– “Low Level Interrupt” on page 51
– “Device Signature Imprint Table” on page 153
3. Updated Sections:
– “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24
– “System Clock and Clock Options” on page 23
– “Internal PLL in ATtiny15 Compatibility Mode” on page 24
– “Sleep Modes” on page 35
– “Software BOD Disable” on page 36
– “External Interrupts” on page 51
24
ATtiny25/45/85
2586L–AVR–06/10
ATtiny25/45/85
– “Timer/Counter1 in PWM Mode” on page 101
– “USI – Universal Serial Interface” on page 111
– “Temperature Measurement” on page 137
– “Reading Lock, Fuse and Signature Data from Software” on page 147
– “Program And Data Memory Lock Bits” on page 151
– “Fuse Bytes” on page 152
– “Signature Bytes” on page 154
– “Calibration Bytes” on page 154
– “System and Reset Characteristics” on page 170
4. Added Figures:
– “Reset Pin Output Voltage vs. Sink Current (VCC = 3V)” on page 189
– “Reset Pin Output Voltage vs. Sink Current (VCC = 5V)” on page 190
– “Reset Pin Output Voltage vs. Source Current (VCC = 3V)” on page 190
– “Reset Pin Output Voltage vs. Source Current (VCC = 5V)” on page 191
5. Updated Figure:
– “Reset Logic” on page 41
6. Updated Tables:
– “Start-up Times for Internal Calibrated RC Oscillator Clock” on page 28
– “Start-up Times for Internal Calibrated RC Oscillator Clock (in ATtiny15 Mode)” on
page 28
– “Start-up Times for the 128 kHz Internal Oscillator” on page 29
– “Compare Mode Select in PWM Mode” on page 89
– “Compare Mode Select in PWM Mode” on page 101
– “DC Characteristics. TA = -40°C to +85°C” on page 166
– “Calibration Accuracy of Internal RC Oscillator” on page 169
– “ADC Characteristics” on page 172
7. Updated Code Example in Section:
– “Write” on page 17
8. Updated Bit Descriptions in:
– “MCUCR – MCU Control Register” on page 38
– “Bits 7:6 – COM0A[1:0]: Compare Match Output A Mode” on page 80
– “Bits 5:4 – COM0B[1:0]: Compare Match Output B Mode” on page 80
– “Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source” on page 142
– “SPMCSR – Store Program Memory Control and Status Register” on page 149.
9. Updated description of feature “EEPROM read may fail at low supply voltage / low
clock frequency” in Sections:
– “Errata ATtiny25” on page 19
– “Errata ATtiny45” on page 20
– “Errata ATtiny85” on page 23
10. Updated Package Description in Sections:
– “ATtiny25” on page 11
25
2586L–AVR–06/10
– “ATtiny45” on page 12
– “ATtiny85” on page 13
11. Updated Package Drawing:
– “S8S1” on page 16
12. Updated Order Codes for:
– “ATtiny25” on page 11
9.3
Rev. 2586J-12/06
1.
2.
3.
Updated “Low Power Consumption” on page 1.
Updated description of instruction length in “Architectural Overview” .
Updated Flash size in “In-System Re-programmable Flash Program Memory” on
page 15.
4.
Updated cross-references in sections “Atomic Byte Programming” , “Erase” and
“Write” , starting on page 17.
5.
Updated “Atomic Byte Programming” on page 17.
6.
Updated “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24.
Replaced single clocking system figure with two: Figure 6-2 and Figure 6-3.
Updated Table 6-1 on page 25, Table 6-13 on page 30 and Table 6-6 on page 28.
Updated “Calibrated Internal Oscillator” on page 27.
Updated Table 6-5 on page 27.
7.
8.
9.
10.
11.
12.
13.
14.
15.
16.
17.
18.
Updated “OSCCAL – Oscillator Calibration Register” on page 32.
Updated “CLKPR – Clock Prescale Register” on page 33.
Updated “Power-down Mode” on page 36.
Updated “Bit 0” in “PRR – Power Reduction Register” on page 39.
Added footnote to Table 8-3 on page 49.
Updated Table 10-5 on page 65.
Deleted “Bits 7, 2” in “MCUCR – MCU Control Register” on page 66.
Updated and moved section “Timer/Counter0 Prescaler and Clock Sources”, now
located on page 68.
19.
20.
Updated “Timer/Counter1 Initialization for Asynchronous Mode” on page 89.
Updated bit description in “PLLCSR – PLL Control and Status Register” on page 97
and “PLLCSR – PLL Control and Status Register” on page 107.
Added recommended maximum frequency in“Prescaling and Conversion Timing” on
page 129.
21.
22.
23.
24.
Updated Figure 17-8 on page 133 .
Updated “Temperature Measurement” on page 137.
Updated Table 17-3 on page 138.
26
ATtiny25/45/85
2586L–AVR–06/10
ATtiny25/45/85
25.
Updated bit R/W descriptions in:
“TIMSK – Timer/Counter Interrupt Mask Register” on page 84,
“TIFR – Timer/Counter Interrupt Flag Register” on page 84,
“TIMSK – Timer/Counter Interrupt Mask Register” on page 95,
“TIFR – Timer/Counter Interrupt Flag Register” on page 96,
“PLLCSR – PLL Control and Status Register” on page 97,
“TIMSK – Timer/Counter Interrupt Mask Register” on page 106,
“TIFR – Timer/Counter Interrupt Flag Register” on page 106,
“PLLCSR – PLL Control and Status Register” on page 107 and
“DIDR0 – Digital Input Disable Register 0” on page 142.
Added limitation to “Limitations of debugWIRE” on page 144.
Updated “DC Characteristics” on page 166.
26.
27.
28.
29.
30.
31.
32.
33.
34.
35.
36.
Updated Table 21-7 on page 171.
Updated Figure 21-6 on page 176.
Updated Table 21-12 on page 176.
Updated Table 22-1 on page 182.
Updated Table 22-2 on page 182.
Updated Table 22-30, Table 22-31 and Table 22-32, starting on page 193.
Updated Table 22-33, Table 22-34 and Table 22-35, starting on page 194.
Updated Table 22-39 on page 197.
Updated Table 22-46, Table 22-47, Table 22-48 and Table 22-49.
9.4
Rev. 2586I-09/06
1.
2.
All Characterization data moved to “Electrical Characteristics” on page 166.
All Register Descriptions are gathered up in seperate sections in the end of each
chapter.
3.
Updated Table 11-3 on page 81, Table 11-5 on page 82, Table 11-6 on page 83 and
Table 20-4 on page 152.
4.
5.
6.
7.
8.
9.
Updated “Calibrated Internal Oscillator” on page 27.
Updated Note in Table 7-1 on page 35.
Updated “System Control and Reset” on page 41.
Updated Register Description in “I/O Ports” on page 55.
Updated Features in “USI – Universal Serial Interface” on page 111.
Updated Code Example in “SPI Master Operation Example” on page 113 and “SPI
Slave Operation Example” on page 114.
10.
11.
12.
13.
Updated “Analog Comparator Multiplexed Input” on page 123.
Updated Figure 17-1 on page 127.
Updated “Signature Bytes” on page 154.
Updated “Electrical Characteristics” on page 166.
9.5
Rev. 2586H-06/06
1.
2.
3.
Updated “Calibrated Internal Oscillator” on page 27.
Updated Table 6.5.1 on page 32.
Added Table 21-2 on page 169.
27
2586L–AVR–06/10
9.6
Rev. 2586G-05/06
1.
Updated “Internal PLL for Fast Peripheral Clock Generation - clkPCK” on page 24.
Updated “Default Clock Source” on page 31.
2.
3.
Updated “Low-Frequency Crystal Oscillator” on page 29.
Updated “Calibrated Internal Oscillator” on page 27.
Updated “Clock Output Buffer” on page 32.
4.
5.
6.
Updated “Power Management and Sleep Modes” on page 35.
Added “Software BOD Disable” on page 36.
7.
8.
Updated Figure 16-1 on page 123.
9.
Updated “Bit 6 – ACBG: Analog Comparator Bandgap Select” on page 124.
Added note for Table 17-2 on page 129.
10.
11.
Updated “Register Summary” on page 7.
9.7
9.8
Rev. 2586F-04/06
1.
2.
3.
Updated “Digital Input Enable and Sleep Modes” on page 59.
Updated Table 20-16 on page 163.
Updated “Ordering Information” on page 11.
Rev. 2586E-03/06
1.
2.
3.
4.
5.
Updated Features in “Analog to Digital Converter” on page 126.
Updated Operation in “Analog to Digital Converter” on page 126.
Updated Table 17-2 on page 138.
Updated Table 17-3 on page 138.
Updated “Errata” on page 19.
9.9
Rev. 2586D-02/06
1.
Updated Table 6-13 on page 30, Table 6-10 on page 29, Table 6-3 on page 26,
Table 6-9 on page 29, Table 6-5 on page 27, Table 9-1 on page 50,Table 17-4 on
page 139, Table 20-16 on page 163, Table 21-8 on page 172.
Updated “Timer/Counter1 in PWM Mode” on page 89.
Updated text “Bit 2 – TOV1: Timer/Counter1 Overflow Flag” on page 97.
Updated values in “DC Characteristics” on page 166.
Updated “Register Summary” on page 7.
2.
3.
4.
5.
6.
7.
8.
9.
Updated “Ordering Information” on page 11.
Updated Rev B and C in “Errata ATtiny45” on page 20.
All references to power-save mode are removed.
Updated Register Adresses.
9.10 Rev. 2586C-06/05
1.
2.
3.
4.
5.
6.
Updated “Features” on page 1.
Updated Figure 1-1 on page 2.
Updated Code Examples on page 18 and page 19.
Moved “Temperature Measurement” to Section 17.12 page 137.
Updated “Register Summary” on page 7.
Updated “Ordering Information” on page 11.
28
ATtiny25/45/85
2586L–AVR–06/10
ATtiny25/45/85
9.11 Rev. 2586B-05/05
1.
CLKI added, instances of EEMWE/EEWE renamed EEMPE/EEPE, removed some
TBD.
Removed “Preliminary Description” from “Temperature Measurement” on page 137.
Updated “Features” on page 1.
2.
3.
4.
5.
6.
7.
8.
9.
Updated Figure 1-1 on page 2 and Figure 8-1 on page 41.
Updated Table 7-2 on page 39, Table 10-4 on page 65, Table 10-5 on page 65
Updated “Serial Programming Instruction set” on page 157.
Updated SPH register in “Instruction Set Summary” on page 9.
Updated “DC Characteristics” on page 166.
Updated “Ordering Information” on page 11.
Updated “Errata” on page 19.
9.12 Rev. 2586A-02/05
Initial revision.
29
2586L–AVR–06/10
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2586L–AVR–06/10
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