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ATUC128L3U-AUT [ATMEL]

RISC Microcontroller, 32-Bit, FLASH, AVR RISC CPU, 50MHz, CMOS, PQFP64, TQFP-64;
ATUC128L3U-AUT
型号： ATUC128L3U-AUT
厂家： ATMEL    ATMEL
描述：

RISC Microcontroller, 32-Bit, FLASH, AVR RISC CPU, 50MHz, CMOS, PQFP64, TQFP-64

时钟 微控制器 外围集成电路
文件： 总45页 (文件大小：404K)
中文：  中文翻译
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Features  
• High-performance, Low-power 32-bit Atmel® AVR® Microcontroller  
– Compact Single-cycle RISC Instruction Set Including DSP Instructions  
– Read-modify-write Instructions and Atomic Bit Manipulation  
– Performance  
• Up to 64DMIPS Running at 50MHz from Flash (1 Flash Wait State)  
• Up to 36DMIPS Running at 25MHz from Flash (0 Flash Wait State)  
– Memory Protection Unit (MPU)  
• Secure Access Unit (SAU) providing User-defined Peripheral Protection  
• picoPower® Technology for Ultra-low Power Consumption  
• Multi-hierarchy Bus System  
– High-performance Data Transfers on Separate Buses for Increased Performance  
– 12 Peripheral DMA Channels improve Speed for Peripheral Communication  
• Internal High-speed Flash  
32-bit Atmel  
AVR  
Microcontroller  
– 256Kbytes, 128Kbytes, and 64Kbytes Versions  
– Single-cycle Access up to 25MHz  
ATUC256L3U  
ATUC128L3U  
ATUC64L3U  
ATUC256L4U  
ATUC128L4U  
ATUC64L4U  
– FlashVault Technology Allows Pre-programmed Secure Library Support for End  
User Applications  
– Prefetch Buffer Optimizing Instruction Execution at Maximum Speed  
– 100,000 Write Cycles, 15-year Data Retention Capability  
– Flash Security Locks and User-defined Configuration Area  
• Internal High-speed SRAM, Single-cycle Access at Full Speed  
– 32Kbytes (256Kbytes and 128Kbytes Flash) and 16Kbytes (64Kbytes Flash)  
• Interrupt Controller (INTC)  
– Autovectored Low-latency Interrupt Service with Programmable Priority  
• External Interrupt Controller (EIC)  
• Peripheral Event System for Direct Peripheral to Peripheral Communication  
• System Functions  
– Power and Clock Manager  
Summary  
– SleepWalking Power Saving Control  
– Internal System RC Oscillator (RCSYS)  
– 32KHz Oscillator  
– Multipurpose Oscillator, Phase Locked Loop (PLL), and Digital Frequency Locked  
Loop (DFLL)  
• Windowed Watchdog Timer (WDT)  
• Asynchronous Timer (AST) with Real-time Clock Capability  
– Counter or Calendar Mode Supported  
• Frequency Meter (FREQM) for Accurate Measuring of Clock Frequency  
• Universal Serial Bus (USBC)  
– Full Speed and Low Speed USB Device Support  
– Multi-packet Ping-pong Mode  
• Six 16-bit Timer/Counter (TC) Channels  
– External Clock Inputs, PWM, Capture, and Various Counting Capabilities  
• 36 PWM Channels (PWMA)  
– 12-bit PWM with a Source Clock up to 150MHz  
• Four Universal Synchronous/Asynchronous Receiver/Transmitters (USART)  
– Independent Baudrate Generator, Support for SPI  
– Support for Hardware Handshaking  
32142DS–06/2013  
 
ATUC64/128/256L3/4U  
• One Master/Slave Serial Peripheral Interface (SPI) with Chip Select Signals  
– Up to 15 SPI Slaves can be Addressed  
• Two Master and Two Slave Two-wire Interfaces (TWI), 400kbit/s I2C-compatible  
• One 8-channel Analog-to-digital Converter (ADC) with up to 12 Bits Resolution  
– Internal Temperature Sensor  
• Eight Analog Comparators (AC) with Optional Window Detection  
• Capacitive Touch (CAT) Module  
– Hardware-assisted Atmel® AVR® QTouch® and Atmel® AVR® QMatrix Touch Acquisition  
– Supports QTouch and QMatrix Capture from Capacitive Touch Sensors  
• QTouch Library Support  
– Capacitive Touch Buttons, Sliders, and Wheels  
– QTouch and QMatrix Acquisition  
• Audio Bitstream DAC (ABDACB) Suitable for Stereo Audio  
• Inter-IC Sound (IISC) Controller  
– Compliant with Inter-IC Sound (I2S) Specification  
• On-chip Non-intrusive Debug System  
– Nexus Class 2+, Runtime Control, Non-intrusive Data and Program Trace  
– aWire Single-pin Programming Trace and Debug Interface, Muxed with Reset Pin  
– NanoTrace Provides Trace Capabilities through JTAG or aWire Interface  
• 64-pin TQFP/QFN (51 GPIO Pins), 48-pin TQFP/QFN/TLLGA (36 GPIO Pins)  
• Six High-drive I/O Pins (64-pin Packages), Four High-drive I/O Pins (48-pin Packages)  
• Single 1.62-3.6V Power Supply  
2
32142DS–06/2013  
ATUC64/128/256L3/4U  
1. Description  
The Atmel® AVR® ATUC64/128/256L3/4U is a complete system-on-chip microcontroller based  
on the AVR32 UC RISC processor running at frequencies up to 50MHz. AVR32 UC is a high-  
performance 32-bit RISC microprocessor core, designed for cost-sensitive embedded applica-  
tions, with particular emphasis on low power consumption, high code density, and high  
performance.  
The processor implements a Memory Protection Unit (MPU) and a fast and flexible interrupt con-  
troller for supporting modern and real-time operating systems. The Secure Access Unit (SAU) is  
used together with the MPU to provide the required security and integrity.  
Higher computation capability is achieved using a rich set of DSP instructions.  
The ATUC64/128/256L3/4U embeds state-of-the-art picoPower technology for ultra-low power  
consumption. Combined power control techniques are used to bring active current consumption  
down to 174µA/MHz, and leakage down to 220nA while still retaining a bank of backup regis-  
ters. The device allows a wide range of trade-offs between functionality and power consumption,  
giving the user the ability to reach the lowest possible power consumption with the feature set  
required for the application.  
The Peripheral Direct Memory Access (DMA) controller enables data transfers between periph-  
erals and memories without processor involvement. The Peripheral DMA controller drastically  
reduces processing overhead when transferring continuous and large data streams.  
The ATUC64/128/256L3/4U incorporates on-chip Flash and SRAM memories for secure and  
fast access. The FlashVault technology allows secure libraries to be programmed into the  
device. The secure libraries can be executed while the CPU is in Secure State, but not read by  
non-secure software in the device. The device can thus be shipped to end customers, who will  
be able to program their own code into the device to access the secure libraries, but without risk  
of compromising the proprietary secure code.  
The External Interrupt Controller (EIC) allows pins to be configured as external interrupts. Each  
external interrupt has its own interrupt request and can be individually masked.  
The Peripheral Event System allows peripherals to receive, react to, and send peripheral events  
without CPU intervention. Asynchronous interrupts allow advanced peripheral operation in low  
power sleep modes.  
The Power Manager (PM) improves design flexibility and security. The Power Manager supports  
SleepWalking functionality, by which a module can be selectively activated based on peripheral  
events, even in sleep modes where the module clock is stopped. Power monitoring is supported  
by on-chip Power-on Reset (POR), Brown-out Detector (BOD), and Supply Monitor (SM). The  
device features several oscillators, such as Phase Locked Loop (PLL), Digital Frequency  
Locked Loop (DFLL), Oscillator 0 (OSC0), and system RC oscillator (RCSYS). Either of these  
oscillators can be used as source for the system clock. The DFLL is a programmable internal  
oscillator from 20 to 150MHz. It can be tuned to a high accuracy if an accurate reference clock is  
running, e.g. the 32KHz crystal oscillator.  
The Watchdog Timer (WDT) will reset the device unless it is periodically serviced by the soft-  
ware. This allows the device to recover from a condition that has caused the system to be  
unstable.  
The Asynchronous Timer (AST) combined with the 32KHz crystal oscillator supports powerful  
real-time clock capabilities, with a maximum timeout of up to 136 years. The AST can operate in  
counter or calendar mode.  
3
32142DS–06/2013  
 
ATUC64/128/256L3/4U  
The Frequency Meter (FREQM) allows accurate measuring of a clock frequency by comparing it  
to a known reference clock.  
The Full-speed USB 2.0 device interface (USBC) supports several USB classes at the same  
time, thanks to the rich end-point configuration.  
The device includes six identical 16-bit Timer/Counter (TC) channels. Each channel can be inde-  
pendently programmed to perform frequency measurement, event counting, interval  
measurement, pulse generation, delay timing, and pulse width modulation.  
The Pulse Width Modulation controller (PWMA) provides 12-bit PWM channels which can be  
synchronized and controlled from a common timer. 36 PWM channels are available, enabling  
applications that require multiple PWM outputs, such as LCD backlight control. The PWM chan-  
nels can operate independently, with duty cycles set individually, or in interlinked mode, with  
multiple channels changed at the same time.  
The ATUC64/128/256L3/4U also features many communication interfaces, like USART, SPI,  
and TWI, for communication intensive applications. The USART supports different communica-  
tion modes, like SPI Mode and LIN Mode.  
A general purpose 8-channel ADC is provided, as well as eight analog comparators (AC). The  
ADC can operate in 10-bit mode at full speed or in enhanced mode at reduced speed, offering  
up to 12-bit resolution. The ADC also provides an internal temperature sensor input channel.  
The analog comparators can be paired to detect when the sensing voltage is within or outside  
the defined reference window.  
The Capacitive Touch (CAT) module senses touch on external capacitive touch sensors, using  
the QTouch technology. Capacitive touch sensors use no external mechanical components,  
unlike normal push buttons, and therefore demand less maintenance in the user application.  
The CAT module allows up to 17 touch sensors, or up to 16 by 8 matrix sensors to be interfaced.  
All touch sensors can be configured to operate autonomously without software interaction,  
allowing wakeup from sleep modes when activated.  
Atmel offers the QTouch library for embedding capacitive touch buttons, sliders, and wheels  
functionality into AVR microcontrollers. The patented charge-transfer signal acquisition offers  
robust sensing and includes fully debounced reporting of touch keys as well as Adjacent Key  
Suppression® (AKS®) technology for unambiguous detection of key events. The easy-to-use  
QTouch Suite toolchain allows you to explore, develop, and debug your own touch applications.  
The Audio Bitstream DAC (ABDACB) converts a 16-bit sample value to a digital bitstream with  
an average value proportional to the sample value. Two channels are supported, making the  
ABDAC particularly suitable for stereo audio.  
The Inter-IC Sound Controller (IISC) provides a 5-bit wide, bidirectional, synchronous, digital  
audio link with external audio devices. The controller is compliant with the Inter-IC Sound (I2S)  
bus specification.  
The ATUC64/128/256L3/4U integrates a class 2+ Nexus 2.0 On-chip Debug (OCD) System,  
with non-intrusive real-time trace and full-speed read/write memory access, in addition to basic  
runtime control. The NanoTrace interface enables trace feature for aWire- or JTAG-based  
debuggers. The single-pin aWire interface allows all features available through the JTAG inter-  
face to be accessed through the RESET pin, allowing the JTAG pins to be used for GPIO or  
peripherals.  
4
32142DS–06/2013  
ATUC64/128/256L3/4U  
2. Overview  
2.1  
Block Diagram  
Figure 2-1. Block Diagram  
MCKO  
MDO[5..0]  
MSEO[1..0]  
EVTI_N  
LOCAL BUS  
LOCAL BUS  
INTERFACE  
AVR32UC CPU  
EVTO_N  
NEXUS  
CLASS 2+  
OCD  
TCK  
MEMORY PROTECTION UNIT  
JTAG  
TDO  
32/16 KB  
SRAM  
TDI  
TMS  
INTERFACE  
INSTR  
DATA  
INTERFACE  
INTERFACE  
DATAOUT  
aWire  
RESET_N  
M
M
M
S
S/M  
SAU  
256/128/64  
KB  
FLASH  
HIGH SPEED  
BUS MATRIX  
S
DP  
USB 2.0  
Interface  
8EP  
S
M
S
S
DM  
CONFIGURATION  
REGISTERS BUS  
PERIPHERAL  
DMA  
CONTROLLER  
HSB-PB  
BRIDGE A  
HSB-PB  
BRIDGE B  
DIS  
VDIVEN  
CSA[16:0]  
CSB[16:0]  
SMP  
POWER MANAGER  
CAPACITIVE TOUCH  
MODULE  
CLOCK  
CONTROLLER  
PA  
PB  
SYNC  
SLEEP  
CONTROLLER  
USART0  
USART1  
USART2  
USART3  
RXD  
TXD  
CLK  
RESET  
CONTROLLER  
RTS, CTS  
SCK  
MISO, MOSI  
GCLK_IN[2..0]  
GCLK[9..0]  
SPI  
NPCS[3..0]  
RCSYS  
TWCK  
RC32OUT  
RC32K  
RC120M  
OSC32K  
OSC0  
TWI MASTER 0  
TWI MASTER 1  
PA  
PB  
TWD  
SYSTEM CONTROL  
INTERFACE  
TWALM  
XIN32  
XOUT32  
TWCK  
XIN0  
XOUT0  
TWI SLAVE 0  
TWI SLAVE 1  
TWD  
DFLL  
TWALM  
PLL  
ADP[1..0]  
TRIGGER  
AD[8..0]  
8-CHANNEL ADC  
INTERFACE  
ADVREFP  
ISCK  
IWS  
ISDI  
ISDO  
IMCK  
INTER-IC SOUND  
CONTROLLER  
INTERRUPT  
CONTROLLER  
CLK  
AUDIO BITSTREAM  
DAC  
EXTINT[5..1]  
NMI  
EXTERNAL INTERRUPT  
CONTROLLER  
DAC0, DAC1  
DACN0, DACN1  
ACBP[3..0]  
ACBN[3..0]  
ACAP[3..0]  
ACAN[3..0]  
ACREFN  
PWMA[35..0]  
PWM CONTROLLER  
AC INTERFACE  
ASYNCHRONOUS  
TIMER  
OUT[1..0]  
IN[7..0]  
GLUE LOGIC  
CONTROLLER  
WATCHDOG  
TIMER  
FREQUENCY METER  
A[2..0]  
B[2..0]  
TIMER/COUNTER 0  
TIMER/COUNTER 1  
CLK[2..0]  
5
32142DS–06/2013  
 
 
ATUC64/128/256L3/4U  
2.2  
Configuration Summary  
Table 2-1.  
Configuration Summary  
ATUC256L3U ATUC128L3U  
Feature  
ATUC64L3U  
64KB  
ATUC256L4U ATUC128L4U  
ATUC64L4U  
64KB  
Flash  
256KB  
128KB  
256KB  
128KB  
SRAM  
32KB  
16KB  
32KB  
16KB  
GPIO  
51  
6
36  
4
High-drive pins  
External Interrupts  
TWI  
6
2
USART  
4
Peripheral DMA Channels  
Peripheral Event System  
SPI  
12  
1
1
Asynchronous Timers  
Timer/Counter Channels  
PWM channels  
Frequency Meter  
Watchdog Timer  
Power Manager  
Secure Access Unit  
Glue Logic Controller  
1
6
36  
1
1
1
1
1
Digital Frequency Locked Loop 20-150MHz (DFLL)  
Phase Locked Loop 40-240MHz (PLL)  
Crystal Oscillator 0.45-16MHz (OSC0)  
Crystal Oscillator 32KHz (OSC32K)  
RC Oscillator 120MHz (RC120M)  
Oscillators  
RC Oscillator 115kHz (RCSYS)  
RC Oscillator 32kHz (RC32K)  
ADC  
8-channel 12-bit  
Temperature Sensor  
Analog Comparators  
Capacitive Touch Module  
JTAG  
1
8
1
1
1
1
aWire  
USB  
Audio Bitstream DAC  
IIS Controller  
Max Frequency  
Packages  
1
0
0
1
50MHz  
TQFP64/QFN64  
TQFP48/QFN48/TLLGA48  
6
32142DS–06/2013  
 
ATUC64/128/256L3/4U  
3. Package and Pinout  
3.1  
Package  
The device pins are multiplexed with peripheral functions as described in Section .  
Figure 3-1. ATUC64/128/256L4U TQFP48/QFN48 Pinout  
PA15  
PA16  
PA17  
PA19  
PA18  
VDDIO  
GND  
PB11  
GND  
PA10  
PA12  
VDDIO  
37  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
PA21  
PB10  
RESET_N  
PB04  
PB05  
GND  
VDDCORE  
VDDIN  
PB14  
PB13  
PA01  
PA02  
7
32142DS–06/2013  
 
 
ATUC64/128/256L3/4U  
Figure 3-2. ATUC64/128/256L4U TLLGA48 Pinout  
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
PA21  
PB10  
RESET_N  
PB04  
PB05  
PA16  
PA17  
PA19  
PA18  
VDDIO  
GND  
PB11  
GND  
PA10  
PA12  
VDDIO  
38  
39  
40  
41  
42  
43  
44  
45  
46  
47  
48  
GND  
VDDCORE  
VDDIN  
PB14  
PB13  
PA01  
8
32142DS–06/2013  
ATUC64/128/256L3/4U  
Figure 3-3. ATUC64/128/256L3U TQFP64/QFN64 Pinout  
PA15  
PA16  
PA17  
PA19  
PA18  
PB23  
PB24  
PB11  
PB15  
PB16  
PB17  
PB18  
PB25  
PA10  
PA12  
VDDIO  
49  
50  
51  
52  
53  
54  
55  
56  
57  
58  
59  
60  
61  
62  
63  
64  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
22  
21  
20  
19  
18  
17  
PA21  
PB10  
RESET_N  
PB04  
PB05  
GND  
VDDCORE  
VDDIN  
PB27  
PB14  
PB13  
PB26  
PB01  
PA07  
PA01  
PA02  
9
32142DS–06/2013  
ATUC64/128/256L3/4U  
Peripheral Multiplexing on I/O lines  
3.1.1  
Multiplexed Signals  
Each GPIO line can be assigned to one of the peripheral functions. The following table  
describes the peripheral signals multiplexed to the GPIO lines.  
Table 3-1.  
GPIO Controller Function Multiplexing  
G
PI  
O
GPIO Function  
48-  
pin  
64-  
pin  
Pin  
Name  
Pad  
Type  
Supply  
A
B
C
D
E
F
G
H
Normal  
I/O  
USART0-  
TXD  
USART1-  
RTS  
SPI-  
NPCS[2]  
PWMA-  
PWMA[0]  
SCIF-  
GCLK[0]  
CAT-  
CSA[2]  
11  
14  
13  
4
15  
18  
17  
6
PA00  
PA01  
PA02  
PA03  
PA04  
PA05  
0
1
2
3
4
5
VDDIO  
Normal  
I/O  
USART0-  
RXD  
USART1-  
CTS  
SPI-  
NPCS[3]  
USART1-  
CLK  
PWMA-  
PWMA[1]  
ACIFB-  
ACAP[0]  
TWIMS0-  
TWALM  
CAT-  
CSA[1]  
VDDIO  
VDDIO  
VDDIO  
VDDIO  
VDDIO  
High-  
drive I/O  
USART0-  
RTS  
ADCIFB-  
TRIGGER  
USART2-  
TXD  
PWMA-  
PWMA[2]  
ACIFB-  
ACBP[0]  
USART0-  
CLK  
CAT-  
CSA[3]  
TC0-A0  
TC0-B0  
TC0-B1  
TC0-A1  
Normal  
I/O  
USART0-  
CTS  
SPI-  
NPCS[1]  
USART2-  
TXD  
PWMA-  
PWMA[3]  
ACIFB-  
ACBN[3]  
USART0-  
CLK  
CAT-  
CSB[3]  
Normal  
I/O  
TWIMS0-  
TWCK  
USART1-  
RXD  
PWMA-  
PWMA[4]  
ACIFB-  
ACBP[1]  
CAT-  
CSA[7]  
28  
12  
38  
16  
SPI-MISO  
SPI-MOSI  
Normal  
I/O (TWI)  
TWIMS1-  
TWCK  
USART1-  
TXD  
PWMA-  
PWMA[5]  
ACIFB-  
ACBN[0]  
TWIMS0-  
TWD  
CAT-  
CSB[7]  
High-  
drive I/O,  
5V  
USART2-  
TXD  
USART1-  
CLK  
PWMA-  
PWMA[6]  
EIC-  
EXTINT[2]  
SCIF-  
GCLK[1]  
CAT-  
CSB[1]  
10  
14  
19  
PA06  
PA07  
6
7
VDDIO  
VDDIO  
SPI-SCK  
TC0-B0  
tolerant  
EIC-  
NMI  
Normal  
I/O (TWI)  
SPI-  
NPCS[0]  
USART2-  
RXD  
TWIMS1-  
TWALM  
TWIMS0-  
TWCK  
PWMA-  
PWMA[7]  
ACIFB-  
ACAN[0]  
CAT-  
CSB[2]  
(EXTINT[0])  
High-  
drive I/O  
USART1-  
TXD  
SPI-  
NPCS[2]  
ADCIFB-  
ADP[0]  
PWMA-  
PWMA[8]  
CAT-  
CSA[4]  
3
3
PA08  
PA09  
PA10  
PA11  
PA12  
PA13  
PA14  
PA15  
PA16  
8
VDDIO  
VDDIO  
VDDIO  
VDDIN  
VDDIO  
VDDIN  
VDDIO  
VDDIO  
VDDIO  
TC0-A2  
TC0-B2  
TC0-A0  
High-  
drive I/O  
USART1-  
RXD  
SPI-  
NPCS[3]  
ADCIFB-  
ADP[1]  
PWMA-  
PWMA[9]  
SCIF-  
GCLK[2]  
EIC-  
EXTINT[1]  
CAT-  
CSB[4]  
2
2
9
Normal  
I/O  
TWIMS0-  
TWD  
PWMA-  
PWMA[10]  
ACIFB-  
ACAP[1]  
SCIF-  
GCLK[2]  
CAT-  
CSA[5]  
46  
27  
47  
26  
36  
37  
38  
62  
35  
63  
34  
48  
49  
50  
10  
11  
12  
13  
14  
15  
16  
Normal  
I/O  
PWMA-  
PWMA[11]  
Normal  
I/O  
USART2-  
CLK  
PWMA-  
PWMA[12]  
ACIFB-  
ACAN[1]  
SCIF-  
GCLK[3]  
CAT-  
CSB[5]  
TC0-CLK1  
TC0-A0  
CAT-SMP  
Normal  
I/O  
GLOC-  
OUT[0]  
GLOC-  
IN[7]  
SCIF-  
GCLK[2]  
PWMA-  
PWMA[13]  
EIC-  
EXTINT[2]  
CAT-  
CSA[0]  
CAT-SMP  
Normal  
I/O  
ADCIFB-  
AD[0]  
USART2-  
RTS  
PWMA-  
PWMA[14]  
SCIF-  
GCLK[4]  
CAT-  
CSA[6]  
TC0-CLK2  
TC0-CLK1  
TC0-CLK0  
CAT-SMP  
Normal  
I/O  
ADCIFB-  
AD[1]  
GLOC-  
IN[6]  
PWMA-  
PWMA[15]  
CAT-  
SYNC  
EIC-  
EXTINT[3]  
CAT-  
CSB[6]  
Normal  
I/O  
ADCIFB-  
AD[2]  
GLOC-  
IN[5]  
PWMA-  
PWMA[16]  
ACIFB-  
ACREFN  
EIC-  
EXTINT[4]  
CAT-  
CSA[8]  
10  
32142DS–06/2013  
 
ATUC64/128/256L3/4U  
Table 3-1.  
GPIO Controller Function Multiplexing  
Normal  
I/O (TWI)  
USART2-  
CTS  
TWIMS1-  
TWD  
PWMA-  
PWMA[17]  
CAT-  
CSB[8]  
39  
51  
53  
PA17  
17  
VDDIO  
TC0-A1  
TC0-B1  
CAT-SMP  
CAT-DIS  
Normal  
I/O  
ADCIFB-  
AD[4]  
GLOC-  
IN[4]  
PWMA-  
PWMA[18]  
CAT-  
SYNC  
EIC-  
EXTINT[5]  
CAT-  
CSB[0]  
41  
40  
25  
PA18  
18  
VDDIO  
SCIF-  
GCLK_IN[  
0]  
Normal  
I/O  
ADCIFB-  
AD[5]  
TWIMS1-  
TWALM  
PWMA-  
PWMA[19]  
CAT-  
CSA[10]  
52  
33  
PA19  
PA20  
19  
20  
VDDIO  
VDDIN  
TC0-A2  
TC0-A1  
CAT-SYNC  
Normal  
I/O  
USART2-  
TXD  
GLOC-  
IN[3]  
PWMA-  
PWMA[20]  
SCIF-  
RC32OUT  
CAT-  
CSA[12]  
Normal  
I/O (TWI,  
5V  
tolerant,  
SMBus)  
PWMA-  
PWMAOD  
[21]  
USART2-  
RXD  
TWIMS0-  
TWD  
ADCIFB-  
TRIGGER  
PWMA-  
PWMA[21]  
SCIF-  
GCLK[0]  
CAT-  
SMP  
24  
32  
PA21  
21  
VDDIN  
TC0-B1  
TC0-B2  
Normal  
I/O  
USART0-  
CTS  
USART2-  
CLK  
PWMA-  
PWMA[22]  
ACIFB-  
ACBN[2]  
CAT-  
CSB[10]  
9
6
13  
8
PA22  
PB00  
PB01  
PB02  
PB03  
22  
32  
33  
34  
35  
VDDIO  
VDDIO  
VDDIO  
VDDIO  
VDDIO  
CAT-SMP  
TC0-A1  
TC0-B1  
TC0-A2  
TC0-B2  
Normal  
I/O  
USART3-  
TXD  
ADCIFB-  
ADP[0]  
SPI-  
NPCS[0]  
PWMA-  
PWMA[23]  
ACIFB-  
ACAP[2]  
CAT-  
CSA[9]  
TC1-A0  
TC1-A1  
High-  
drive I/O  
USART3-  
RXD  
ADCIFB-  
ADP[1]  
PWMA-  
PWMA[24]  
CAT-  
CSB[9]  
20  
9
SPI-SCK  
SPI-MISO  
SPI-MOSI  
Normal  
I/O  
USART3-  
RTS  
USART3-  
CLK  
PWMA-  
PWMA[25]  
ACIFB-  
ACAN[2]  
SCIF-  
GCLK[1]  
CAT-  
CSB[11]  
7
8
Normal  
I/O  
USART3-  
CTS  
USART3-  
CLK  
PWMA-  
PWMA[26]  
ACIFB-  
ACBP[2]  
CAT-  
CSA[11]  
10  
TC1-A2  
Normal  
I/O (TWI,  
5V  
tolerant,  
SMBus)  
PWMA-  
PWMAOD  
[27]  
USART1-  
RTS  
USART1-  
CLK  
TWIMS0-  
TWALM  
PWMA-  
PWMA[27]  
TWIMS1-  
TWCK  
CAT-  
CSA[14]  
21  
29  
PB04  
36  
VDDIN  
TC1-A0  
Normal  
I/O (TWI,  
5V  
tolerant,  
SMBus)  
PWMA-  
PWMAOD  
[28]  
USART1-  
CTS  
USART1-  
CLK  
TWIMS0-  
TWCK  
PWMA-  
PWMA[28]  
SCIF-  
GCLK[3]  
CAT-  
CSB[14]  
20  
30  
28  
42  
PB05  
PB06  
37  
38  
VDDIN  
VDDIO  
TC1-B0  
TC1-A1  
EIC-  
NMI  
Normal  
I/O  
USART3-  
TXD  
ADCIFB-  
AD[6]  
GLOC-  
IN[2]  
PWMA-  
PWMA[29]  
ACIFB-  
ACAN[3]  
CAT-  
CSB[13]  
(EXTINT[0])  
Normal  
I/O  
USART3-  
RXD  
ADCIFB-  
AD[7]  
GLOC-  
IN[1]  
PWMA-  
PWMA[30]  
ACIFB-  
ACAP[3]  
EIC-  
EXTINT[1]  
CAT-  
CSA[13]  
31  
32  
29  
43  
44  
39  
PB07  
PB08  
PB09  
39  
40  
41  
VDDIO  
VDDIO  
VDDIO  
TC1-B1  
TC1-A2  
TC1-B2  
Normal  
I/O  
USART3-  
RTS  
ADCIFB-  
AD[8]  
GLOC-  
IN[0]  
PWMA-  
PWMA[31]  
CAT-  
SYNC  
EIC-  
EXTINT[2]  
CAT-  
CSB[12]  
Normal  
I/O  
USART3-  
CTS  
USART3-  
CLK  
PWMA-  
PWMA[32]  
ACIFB-  
ACBN[1]  
EIC-  
EXTINT[3]  
CAT-  
CSB[15]  
SCIF-  
GCLK_IN[  
1]  
Normal  
I/O  
USART1-  
TXD  
USART3-  
CLK  
GLOC-  
OUT[1]  
PWMA-  
PWMA[33]  
EIC-  
EXTINT[4]  
CAT-  
CSB[16]  
23  
31  
PB10  
42  
VDDIN  
TC1-CLK0  
Normal  
I/O  
USART1-  
RXD  
ADCIFB-  
TRIGGER  
PWMA-  
PWMA[34]  
CAT-  
VDIVEN  
EIC-  
EXTINT[5]  
CAT-  
CSA[16]  
44  
5
56  
7
PB11  
PB12  
PB13  
PB14  
43  
44  
45  
46  
VDDIO  
VDDIO  
VDDIN  
VDDIN  
TC1-CLK1  
TC1-CLK2  
USBC-DM  
USBC-DP  
Normal  
I/O  
TWIMS1-  
TWALM  
CAT-  
SYNC  
PWMA-  
PWMA[35]  
ACIFB-  
ACBP[3]  
SCIF-  
GCLK[4]  
CAT-  
CSA[15]  
USART3-  
TXD  
PWMA-  
PWMA[7]  
ADCIFB-  
ADP[1]  
SCIF-  
GCLK[5]  
CAT-  
CSB[2]  
15  
16  
22  
23  
USB I/O  
USB I/O  
TC1-A1  
TC1-B1  
USART3-  
RXD  
PWMA-  
PWMA[24]  
SCIF-  
GCLK[5]  
CAT-  
CSB[9]  
11  
32142DS–06/2013  
ATUC64/128/256L3/4U  
Table 3-1.  
GPIO Controller Function Multiplexing  
High-  
drive I/O  
ABDACB-  
CLK  
IISC-  
IMCK  
PWMA-  
PWMA[8]  
SCIF-  
GCLK[3]  
CAT-  
CSB[4]  
57  
58  
59  
60  
4
PB15  
PB16  
PB17  
PB18  
PB19  
PB20  
PB21  
PB22  
PB23  
PB24  
47  
48  
49  
50  
51  
52  
53  
54  
55  
56  
VDDIO  
VDDIO  
VDDIO  
VDDIO  
VDDIO  
VDDIO  
VDDIO  
VDDIO  
VDDIO  
VDDIO  
SPI-SCK  
TC0-CLK2  
Normal  
I/O  
ABDACB-  
DAC[0]  
USART0-  
TXD  
PWMA-  
PWMA[9]  
SCIF-  
GCLK[2]  
CAT-  
CSA[5]  
IISC-ISCK  
IISC-IWS  
IISC-ISDI  
IISC-ISDO  
Normal  
I/O  
ABDACB-  
DAC[1]  
USART0-  
RXD  
PWMA-  
PWMA[10]  
CAT-  
CSB[5]  
Normal  
I/O  
ABDACB-  
DACN[0]  
USART0-  
RTS  
PWMA-  
PWMA[12]  
CAT-  
CSA[0]  
Normal  
I/O  
ABDACB-  
DACN[1]  
USART0-  
CTS  
PWMA-  
PWMA[20]  
EIC-  
EXTINT[1]  
CAT-  
CSA[12]  
Normal  
I/O  
TWIMS1-  
TWD  
USART2-  
RXD  
SPI-  
NPCS[1]  
PWMA-  
PWMA[21]  
USART1-  
RTS  
USART1-  
CLK  
CAT-  
CSA[14]  
5
TC0-A0  
TC0-B0  
Normal  
I/O  
TWIMS1-  
TWCK  
USART2-  
TXD  
SPI-  
NPCS[2]  
PWMA-  
PWMA[28]  
USART1-  
CTS  
USART1-  
CLK  
CAT-  
CSB[14]  
40  
41  
54  
55  
Normal  
I/O  
TWIMS1-  
TWALM  
SPI-  
NPCS[3]  
PWMA-  
PWMA[27]  
ADCIFB-  
TRIGGER  
SCIF-  
GCLK[0]  
CAT-  
CSA[8]  
TC0-CLK0  
TC0-A2  
Normal  
I/O  
USART2-  
RTS  
USART2-  
CLK  
PWMA-  
PWMA[0]  
SCIF-  
GCLK[6]  
CAT-  
CSA[4]  
SPI-MISO  
SPI-MOSI  
CAT-SMP  
Normal  
I/O  
USART2-  
CTS  
USART2-  
CLK  
PWMA-  
PWMA[1]  
ADCIFB-  
ADP[1]  
SCIF-  
GCLK[7]  
CAT-  
CSA[2]  
TC0-B2  
SCIF-  
GCLK_IN[  
2]  
Normal  
I/O  
SPI-  
NPCS[0]  
USART1-  
RXD  
PWMA-  
PWMA[2]  
SCIF-  
GCLK[8]  
CAT-  
CSA[3]  
61  
21  
PB25  
PB26  
57  
58  
VDDIO  
VDDIO  
TC0-A1  
TC0-B1  
Normal  
I/O  
USART1-  
TXD  
PWMA-  
PWMA[3]  
ADCIFB-  
ADP[0]  
SCIF-  
GCLK[9]  
CAT-  
CSB[3]  
SPI-SCK  
EIC-  
NMI  
Normal  
I/O  
USART1-  
RXD  
PWMA-  
PWMA[4]  
ADCIFB-  
ADP[1]  
CAT-  
CSA[9]  
24  
PB27  
59  
VDDIN  
TC0-CLK1  
(EXTINT[0])  
3.2  
See Section 3.3 for a description of the various peripheral signals.  
Refer to ”Electrical Characteristics” on page 991 for a description of the electrical properties of  
the pin types used.  
3.2.1  
TWI, 5V Tolerant, and SMBUS Pins  
Some normal I/O pins offer TWI, 5V tolerance, and SMBUS features. These features are only  
available when either of the TWI functions or the PWMAOD function in the PWMA are selected  
for these pins.  
Refer to the ”Electrical Characteristics” on page 991 for a description of the electrical properties  
of the TWI, 5V tolerance, and SMBUS pins.  
12  
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ATUC64/128/256L3/4U  
3.2.2  
Peripheral Functions  
Each GPIO line can be assigned to one of several peripheral functions. The following table  
describes how the various peripheral functions are selected. The last listed function has priority  
in case multiple functions are enabled on the same pin.  
Table 3-2.  
Function  
Peripheral Functions  
Description  
GPIO Controller Function multiplexing  
Nexus OCD AUX port connections  
aWire DATAOUT  
GPIO and GPIO peripheral selection A to H  
OCD trace system  
aWire output in two-pin mode  
JTAG debug port  
JTAG port connections  
Oscillators  
OSC0, OSC32  
3.2.3  
JTAG Port Connections  
If the JTAG is enabled, the JTAG will take control over a number of pins, irrespectively of the I/O  
Controller configuration.  
Table 3-3.  
JTAG Pinout  
48-pin  
64-pin  
15  
Pin name  
PA00  
JTAG pin  
TCK  
11  
14  
13  
4
18  
PA01  
TMS  
17  
PA02  
TDO  
6
PA03  
TDI  
3.2.4  
Nexus OCD AUX Port Connections  
If the OCD trace system is enabled, the trace system will take control over a number of pins, irre-  
spectively of the I/O Controller configuration. Two different OCD trace pin mappings are  
possible, depending on the configuration of the OCD AXS register. For details, see the AVR32  
UC Technical Reference Manual.  
Table 3-4.  
Pin  
Nexus OCD AUX Port Connections  
AXS=1  
PA05  
PA10  
PA18  
PA17  
PA16  
PA15  
PA14  
AXS=0  
PB08  
PB00  
PB04  
PB05  
PB03  
PB02  
PB09  
EVTI_N  
MDO[5]  
MDO[4]  
MDO[3]  
MDO[2]  
MDO[1]  
MDO[0]  
13  
32142DS–06/2013  
 
ATUC64/128/256L3/4U  
Table 3-4.  
Pin  
Nexus OCD AUX Port Connections  
AXS=1  
PA04  
PA06  
PA07  
PA11  
AXS=0  
PA04  
EVTO_N  
MCKO  
PB01  
PB11  
PB12  
MSEO[1]  
MSEO[0]  
3.2.5  
Oscillator Pinout  
The oscillators are not mapped to the normal GPIO functions and their muxings are controlled  
by registers in the System Control Interface (SCIF). Please refer to the SCIF chapter for more  
information about this.  
Table 3-5.  
Oscillator Pinout  
48-pin  
64-pin  
3
Pin Name  
PA08  
Oscillator Pin  
XIN0  
3
46  
26  
2
62  
34  
2
PA10  
XIN32  
PA13  
XIN32_2  
XOUT0  
PA09  
47  
25  
63  
33  
PA12  
XOUT32  
XOUT32_2  
PA20  
3.2.6  
Other Functions  
The functions listed in Table 3-6 are not mapped to the normal GPIO functions. The aWire DATA  
pin will only be active after the aWire is enabled. The aWire DATAOUT pin will only be active  
after the aWire is enabled and the 2_PIN_MODE command has been sent. The WAKE_N pin is  
always enabled. Please refer to Section 6.1.4.2 on page 45 for constraints on the WAKE_N pin.  
Table 3-6.  
Other Functions  
48-pin  
64-pin  
35  
Pin Name  
PA11  
Function  
WAKE_N  
27  
22  
11  
30  
RESET_N  
PA00  
aWire DATA  
aWire DATAOUT  
15  
14  
32142DS–06/2013  
 
ATUC64/128/256L3/4U  
3.3  
Signal Descriptions  
The following table gives details on signal name classified by peripheral.  
Table 3-7.  
Signal Descriptions List  
Active  
Level  
Signal Name  
Function  
Type  
Comments  
Audio Bitstream DAC - ABDACB  
CLK  
D/A Clock out  
Output  
Output  
DAC1 - DAC0  
D/A Bitstream out  
DACN1 - DACN0  
D/A Inverted bitstream out  
Output  
Analog Comparator Interface - ACIFB  
ACAN3 - ACAN0  
ACAP3 - ACAP0  
ACBN3 - ACBN0  
ACBP3 - ACBP0  
ACREFN  
Negative inputs for comparators "A"  
Analog  
Analog  
Analog  
Analog  
Analog  
Positive inputs for comparators "A"  
Negative inputs for comparators "B"  
Positive inputs for comparators "B"  
Common negative reference  
ADC Interface - ADCIFB  
AD8 - AD0  
ADP1 - ADP0  
TRIGGER  
Analog Signal  
Analog  
Output  
Input  
Drive Pin for resistive touch screen  
External trigger  
aWire - AW  
DATA  
aWire data  
I/O  
I/O  
DATAOUT  
aWire data output for 2-pin mode  
Capacitive Touch Module - CAT  
CSA16 - CSA0  
CSB16 - CSB0  
DIS  
Capacitive Sense A  
Capacitive Sense B  
I/O  
I/O  
Discharge current control  
SMP signal  
Analog  
Output  
Input  
SMP  
SYNC  
Synchronize signal  
Voltage divider enable  
VDIVEN  
Output  
External Interrupt Controller - EIC  
NMI (EXTINT0)  
Non-Maskable Interrupt  
Input  
EXTINT5 - EXTINT1  
External interrupt  
Input  
Glue Logic Controller - GLOC  
Input  
IN7 - IN0  
Inputs to lookup tables  
OUT1 - OUT0  
Outputs from lookup tables  
Output  
Inter-IC Sound (I2S) Controller - IISC  
15  
32142DS–06/2013  
 
ATUC64/128/256L3/4U  
Table 3-7.  
IMCK  
ISCK  
Signal Descriptions List  
I2S Master Clock  
I2S Serial Clock  
Output  
I/O  
ISDI  
I2S Serial Data In  
I2S Serial Data Out  
I2S Word Select  
Input  
Output  
I/O  
ISDO  
IWS  
JTAG module - JTAG  
TCK  
TDI  
Test Clock  
Input  
Input  
Test Data In  
TDO  
TMS  
Test Data Out  
Test Mode Select  
Output  
Input  
Power Manager - PM  
Input  
RESET_N  
Reset  
Low  
Pulse Width Modulation Controller - PWMA  
PWMA35 - PWMA0  
PWMA channel waveforms  
Output  
Output  
PWMAOD35 -  
PWMAOD0  
PWMA channel waveforms, open drain  
mode  
Not all channels support open  
drain mode  
System Control Interface - SCIF  
GCLK9 - GCLK0  
Generic Clock Output  
Output  
Input  
GCLK_IN2 - GCLK_IN0 Generic Clock Input  
RC32OUT  
XIN0  
RC32K output at startup  
Output  
Analog/  
Digital  
Crystal 0 Input  
Analog/  
Digital  
XIN32  
Crystal 32 Input (primary location)  
Crystal 32 Input (secondary location)  
Analog/  
Digital  
XIN32_2  
XOUT0  
Crystal 0 Output  
Analog  
Analog  
Analog  
XOUT32  
XOUT32_2  
Crystal 32 Output (primary location)  
Crystal 32 Output (secondary location)  
Serial Peripheral Interface - SPI  
MISO  
Master In Slave Out  
Master Out Slave In  
I/O  
I/O  
MOSI  
NPCS3 - NPCS0  
SCK  
SPI Peripheral Chip Select  
Clock  
I/O  
Low  
I/O  
Timer/Counter - TC0, TC1  
A0  
A1  
A2  
Channel 0 Line A  
Channel 1 Line A  
Channel 2 Line A  
I/O  
I/O  
I/O  
16  
32142DS–06/2013  
ATUC64/128/256L3/4U  
Table 3-7.  
B0  
Signal Descriptions List  
Channel 0 Line B  
I/O  
I/O  
B1  
Channel 1 Line B  
B2  
Channel 2 Line B  
I/O  
CLK0  
CLK1  
CLK2  
Channel 0 External Clock Input  
Input  
Input  
Input  
Channel 1 External Clock Input  
Channel 2 External Clock Input  
Two-wire Interface - TWIMS0, TWIMS1  
TWALM  
TWCK  
TWD  
SMBus SMBALERT  
I/O  
I/O  
I/O  
Low  
Two-wire Serial Clock  
Two-wire Serial Data  
Universal Synchronous Asynchronous Receiver Transmitter - USART0, USART1, USART2, USART3  
CLK  
CTS  
RTS  
RXD  
TXD  
Clock  
I/O  
Clear To Send  
Request To Send  
Receive Data  
Transmit Data  
Input  
Low  
Low  
Output  
Input  
Output  
Note:  
1. ADCIFB: AD3 does not exist.  
Table 3-8.  
Signal Description List, Continued  
Active  
Level  
Signal Name  
Function  
Type  
Comments  
Power  
Power  
Input/Output  
VDDCORE  
VDDIO  
Core Power Supply / Voltage Regulator Output  
I/O Power Supply  
1.62V to 1.98V  
1.62V to 3.6V. VDDIO should  
always be equal to or lower than  
VDDIN.  
Power Input  
VDDANA  
ADVREFP  
VDDIN  
Analog Power Supply  
Analog Reference Voltage  
Voltage Regulator Input  
Analog Ground  
Power Input  
Power Input  
Power Input  
Ground  
1.62V to 1.98V  
1.62V to 1.98V  
1.62V to 3.6V(1)  
GNDANA  
GND  
Ground  
Ground  
Auxiliary Port - AUX  
MCKO  
Trace Data Output Clock  
Trace Data Output  
Output  
Output  
MDO5 - MDO0  
17  
32142DS–06/2013  
ATUC64/128/256L3/4U  
Table 3-8.  
Signal Description List, Continued  
Active  
Signal Name  
Function  
Type  
Output  
Input  
Level  
Comments  
MSEO1 - MSEO0  
EVTI_N  
Trace Frame Control  
Event In  
Low  
Low  
EVTO_N  
Event Out  
Output  
General Purpose I/O pin  
PA22 - PA00  
PB27 - PB00  
Parallel I/O Controller I/O Port 0  
Parallel I/O Controller I/O Port 1  
I/O  
I/O  
Note:  
1. See Section 6. on page 40  
3.4  
I/O Line Considerations  
3.4.1  
JTAG Pins  
The JTAG is enabled if TCK is low while the RESET_N pin is released. The TCK, TMS, and TDI  
pins have pull-up resistors when JTAG is enabled. The TCK pin always has pull-up enabled dur-  
ing reset. The TDO pin is an output, driven at VDDIO, and has no pull-up resistor. The JTAG  
pins can be used as GPIO pins and multiplexed with peripherals when the JTAG is disabled.  
Please refer to Section 3.2.3 on page 13 for the JTAG port connections.  
3.4.2  
3.4.3  
PA00  
Note that PA00 is multiplexed with TCK. PA00 GPIO function must only be used as output in the  
application.  
RESET_N Pin  
The RESET_N pin is a schmitt input and integrates a permanent pull-up resistor to VDDIN. As  
the product integrates a power-on reset detector, the RESET_N pin can be left unconnected in  
case no reset from the system needs to be applied to the product.  
The RESET_N pin is also used for the aWire debug protocol. When the pin is used for debug-  
ging, it must not be driven by external circuitry.  
3.4.4  
TWI Pins PA21/PB04/PB05  
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and  
inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have  
the same characteristics as other GPIO pins. Selected pins are also SMBus compliant (refer to  
Section on page 10). As required by the SMBus specification, these pins provide no leakage  
path to ground when the ATUC64/128/256L3/4U is powered down. This allows other devices on  
the SMBus to continue communicating even though the ATUC64/128/256L3/4U is not powered.  
After reset a TWI function is selected on these pins instead of the GPIO. Please refer to the  
GPIO Module Configuration chapter for details.  
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3.4.5  
3.4.6  
TWI Pins PA05/PA07/PA17  
When these pins are used for TWI, the pins are open-drain outputs with slew-rate limitation and  
inputs with spike filtering. When used as GPIO pins or used for other peripherals, the pins have  
the same characteristics as other GPIO pins.  
After reset a TWI function is selected on these pins instead of the GPIO. Please refer to the  
GPIO Module Configuration chapter for details.  
GPIO Pins  
All the I/O lines integrate a pull-up resistorProgramming of this pull-up resistor is performed  
independently for each I/O line through the GPIO Controllers. After reset, I/O lines default as  
inputs with pull-up resistors disabled, except PA00 which has the pull-up resistor enabled. PA20  
selects SCIF-RC32OUT (GPIO Function F) as default enabled after reset.  
3.4.7  
3.4.8  
High-drive Pins  
The six pins PA02, PA06, PA08, PA09, PB01, and PB15 have high-drive output capabilities.  
Refer to Section 34. on page 991 for electrical characteristics.  
USB Pins PB13/PB14  
When these pins are used for USB, the pins are behaving according to the USB specification.  
When used as GPIO pins or used for other peripherals, the pins have the same behaviour as  
other normal I/O pins, but the characteristics are different. Refer to Section 34. on page 991 for  
electrical characteristics.  
To be able to use the USB I/O the VDDIN power supply must be 3.3V nominal.  
3.4.9  
RC32OUT Pin  
3.4.9.1  
Clock output at startup  
After power-up, the clock generated by the 32kHz RC oscillator (RC32K) will be output on PA20,  
even when the device is still reset by the Power-On Reset Circuitry. This clock can be used by  
the system to start other devices or to clock a switching regulator to rise the power supply volt-  
age up to an acceptable value.  
The clock will be available on PA20, but will be disabled if one of the following conditions are  
true:  
• PA20 is configured to use a GPIO function other than F (SCIF-RC32OUT)  
• PA20 is configured as a General Purpose Input/Output (GPIO)  
• The bit FRC32 in the Power Manager PPCR register is written to zero (refer to the Power  
Manager chapter)  
The maximum amplitude of the clock signal will be defined by VDDIN.  
Once the RC32K output on PA20 is disabled it can never be enabled again.  
3.4.9.2  
XOUT32_2 function  
PA20 selects RC32OUT as default enabled after reset. This function is not automatically dis-  
abled when the user enables the XOUT32_2 function on PA20. This disturbs the oscillator and  
may result in the wrong frequency. To avoid this, RC32OUT must be disabled when XOUT32_2  
is enabled.  
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3.4.10  
ADC Input Pins  
These pins are regular I/O pins powered from the VDDIO. However, when these pins are used  
for ADC inputs, the voltage applied to the pin must not exceed 1.98V. Internal circuitry ensures  
that the pin cannot be used as an analog input pin when the I/O drives to VDD. When the pins  
are not used for ADC inputs, the pins may be driven to the full I/O voltage range.  
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4. Mechanical Characteristics  
4.1  
Thermal Considerations  
4.1.1  
Thermal Data  
Table 4-1 summarizes the thermal resistance data depending on the package.  
Table 4-1.  
Symbol  
JA  
Thermal Resistance Data  
Parameter  
Condition  
Package  
TQFP48  
TQFP48  
QFN48  
Typ  
54.4  
15.7  
26.0  
1.6  
Unit  
Junction-to-ambient thermal resistance Still Air  
Junction-to-case thermal resistance  
C/W  
JC  
JA  
Junction-to-ambient thermal resistance Still Air  
Junction-to-case thermal resistance  
C/W  
C/W  
C/W  
C/W  
JC  
QFN48  
JA  
Junction-to-ambient thermal resistance Still Air  
Junction-to-case thermal resistance  
TLLGA48  
TLLGA48  
TQFP64  
TQFP64  
QFN64  
25.4  
12.7  
52.9  
15.5  
22.9  
1.6  
JC  
JA  
Junction-to-ambient thermal resistance Still Air  
Junction-to-case thermal resistance  
JC  
JA  
Junction-to-ambient thermal resistance Still Air  
Junction-to-case thermal resistance  
JC  
QFN64  
4.1.2  
Junction Temperature  
The average chip-junction temperature, TJ, in °C can be obtained from the following:  
1. = T + P    
T
JA  
J
A
D
2. TJ = TA + PD  HEATSINK + JC   
where:  
• JA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 4-1.  
• JC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in  
Table 4-1.  
• HEAT SINK = cooling device thermal resistance (°C/W), provided in the device datasheet.  
• PD = device power consumption (W) estimated from data provided in Section 34.4 on page  
992.  
• TA = ambient temperature (°C).  
From the first equation, the user can derive the estimated lifetime of the chip and decide if a  
cooling device is necessary or not. If a cooling device is to be fitted on the chip, the second  
equation should be used to compute the resulting average chip-junction temperature TJ in °C.  
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4.2  
Package Drawings  
Figure 4-1. TQFP-48 Package Drawing  
Table 4-2.  
Device and Package Maximum Weight  
140  
mg  
Table 4-3.  
Package Characteristics  
Moisture Sensitivity Level  
MSL3  
Table 4-4.  
Package Reference  
JEDEC Drawing Reference  
JESD97 Classification  
MS-026  
E3  
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Figure 4-2. QFN-48 Package Drawing  
Note:  
The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability.  
Table 4-5.  
Device and Package Maximum Weight  
Package Characteristics  
140  
mg  
Table 4-6.  
Moisture Sensitivity Level  
MSL3  
Table 4-7.  
Package Reference  
JEDEC Drawing Reference  
JESD97 Classification  
M0-220  
E3  
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Figure 4-3. TLLGA-48 Package Drawing  
Table 4-8.  
Device and Package Maximum Weight  
39.3  
mg  
Table 4-9.  
Package Characteristics  
Moisture Sensitivity Level  
MSL3  
Table 4-10. Package Reference  
JEDEC Drawing Reference  
JESD97 Classification  
N/A  
E4  
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Figure 4-4. TQFP-64 Package Drawing  
Table 4-11. Device and Package Maximum Weight  
300  
mg  
Table 4-12. Package Characteristics  
Moisture Sensitivity Level  
MSL3  
Table 4-13. Package Reference  
JEDEC Drawing Reference  
JESD97 Classification  
MS-026  
E3  
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Figure 4-5. QFN-64 Package Drawing  
Note:  
The exposed pad is not connected to anything internally, but should be soldered to ground to increase board level reliability.  
Table 4-14. Device and Package Maximum Weight  
200  
mg  
Table 4-15. Package Characteristics  
Moisture Sensitivity Level  
MSL3  
Table 4-16. Package Reference  
JEDEC Drawing Reference  
JESD97 Classification  
M0-220  
E3  
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4.3  
Soldering Profile  
Table 4-17 gives the recommended soldering profile from J-STD-20.  
Table 4-17. Soldering Profile  
Profile Feature  
Green Package  
3°C/s max  
150-200°C  
60-150 s  
Average Ramp-up Rate (217°C to Peak)  
Preheat Temperature 175°C 25°C  
Time Maintained Above 217°C  
Time within 5C of Actual Peak Temperature  
Peak Temperature Range  
30 s  
260°C  
Ramp-down Rate  
6°C/s max  
8 minutes max  
Time 25C to Peak Temperature  
A maximum of three reflow passes is allowed per component.  
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5. Ordering Information  
Table 5-1.  
Ordering Information  
Temperature Operating  
Device  
Ordering Code  
Carrier Type  
ES  
Package  
Package Type  
Range  
ATUC256L3U-AUTES  
ATUC256L3U-AUT  
ATUC256L3U-AUR  
ATUC256L3U-Z3UTES  
ATUC256L3U-Z3UT  
ATUC256L3U-Z3UR  
ATUC128L3U-AUT  
ATUC128L3U-AUR  
ATUC128L3U-Z3UT  
ATUC128L3U-Z3UR  
ATUC64L3U-AUT  
N/A  
Tray  
TQFP 64  
Industrial (-40C to 85C)  
N/A  
Tape & Reel  
ES  
ATUC256L3U  
JESD97 Classification E3  
Tray  
QFN 64  
Industrial (-40C to 85C)  
Tape & Reel  
Tray  
TQFP 64  
QFN 64  
TQFP 64  
QFN 64  
Tape & Reel  
Tray  
ATUC128L3U  
ATUC64L3U  
JESD97 Classification E3 Industrial (-40C to 85C)  
JESD97 Classification E3 Industrial (-40C to 85C)  
Tape & Reel  
Tray  
ATUC64L3U-AUR  
ATUC64L3U-Z3UT  
ATUC64L3U-Z3UR  
Tape & Reel  
Tray  
Tape & Reel  
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Table 5-1.  
Device  
Ordering Information  
Temperature Operating  
Range  
Ordering Code  
Carrier Type  
ES  
Package  
Package Type  
ATUC256L4U-AUTES  
ATUC256L4U-AUT  
ATUC256L4U-AUR  
ATUC256L4U-ZAUTES  
ATUC256L4U-ZAUT  
ATUC256L4U-ZAUR  
ATUC256L4U-D3HES  
ATUC256L4U-D3HT  
ATUC256L4U-D3HR  
ATUC128L4U-AUT  
ATUC128L4U-AUR  
ATUC128L4U-ZAUT  
ATUC128L4U-ZAUR  
ATUC128L4U-D3HT  
ATUC128L4U-D3HR  
ATUC64L4U-AUT  
N/A  
Tray  
TQFP 48  
Industrial (-40C to 85C)  
Tape & Reel  
ES  
JESD97 Classification E3  
N/A  
ATUC256L4U  
Tray  
QFN 48  
Industrial (-40C to 85C)  
Tape & Reel  
ES  
N/A  
Tray  
TLLGA 48  
JESD97 Classification E4  
JESD97 Classification E3  
Tape & Reel  
Tray  
TQFP 48  
QFN 48  
Tape & Reel  
Tray  
ATUC128L4U  
Tape & Reel  
Tray  
TLLGA 48  
TQFP 48  
QFN 48  
JESD97 Classification E4 Industrial (-40C to 85C)  
JESD97 Classification E3  
Tape & Reel  
Tray  
ATUC64L4U-AUR  
Tape & Reel  
Tray  
ATUC64L4U-ZAUT  
ATUC64L4U-ZAUR  
ATUC64L4U-D3HT  
ATUC64L4U-D3HR  
ATUC64L4U  
Tape & Reel  
Tray  
TLLGA 48  
JESD97 Classification E4  
Tape & Reel  
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6. Errata  
6.1  
Rev. C  
6.1.1  
SCIF  
1. The RC32K output on PA20 is not always permanently disabled  
The RC32K output on PA20 may sometimes re-appear.  
Fix/Workaround  
Before using RC32K for other purposes, the following procedure has to be followed in order  
to properly disable it:  
- Run the CPU on RCSYS  
- Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT  
- Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as  
one  
- Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as  
zero.  
2. PLLCOUNT value larger than zero can cause PLLEN glitch  
Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN sig-  
nal during asynchronous wake up.  
Fix/Workaround  
The lock-masking mechanism for the PLL should not be used.  
The PLLCOUNT field of the PLL Control Register should always be written to zero.  
3. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature  
The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any loca-  
tion in the SCIF memory range.  
Fix/Workaround  
None.  
6.1.2  
SPI  
1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0  
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI  
module will not start a data transfer.  
Fix/Workaround  
Disable mode fault detection by writing a one to MR.MODFDIS.  
2. Disabling SPI has no effect on the SR.TDRE bit  
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered  
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is  
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer  
is empty, and this data will be lost.  
Fix/Workaround  
Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the  
SPI and PDCA.  
3. SPI disable does not work in SLAVE mode  
SPI disable does not work in SLAVE mode.  
Fix/Workaround  
Read the last received data, then perform a software reset by writing a one to the Software  
Reset bit in the Control Register (CR.SWRST).  
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4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and  
NCPHA=0  
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one  
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,  
then an additional pulse will be generated on SCK.  
Fix/Workaround  
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1  
if CSRn.CPOL=1 and CSRn.NCPHA=0.  
5. SPI mode fault detection enable causes incorrect behavior  
When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate  
properly.  
Fix/Workaround  
Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.  
6. SPI RDR.PCS is not correct  
The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not  
correctly indicate the value on the NPCS pins at the end of a transfer.  
Fix/Workaround  
Do not use the PCS field of the SPI RDR.  
6.1.3  
TWI  
1. SMBALERT bit may be set after reset  
The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after  
system reset.  
Fix/Workaround  
After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.  
2. Clearing the NAK bit before the BTF bit is set locks up the TWI bus  
When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-  
ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to  
attempt to continue transmitting data, thus locking up the bus.  
Fix/Workaround  
Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been  
set.  
6.1.4  
TC  
1. Channel chaining skips first pulse for upper channel  
When chaining two channels using the Block Mode Register, the first pulse of the clock  
between the channels is skipped.  
Fix/Workaround  
Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle  
for the upper channel. After the dummy cycle has been generated, indicated by the  
SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real  
values.  
6.1.5  
CAT  
1. CAT QMatrix sense capacitors discharged prematurely  
At the end of a QMatrix burst charging sequence that uses different burst count values for  
different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the periph-  
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eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency.  
This results in premature loss of charge from the sense capacitors and thus increased vari-  
ability of the acquired count values.  
Fix/Workaround  
Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11,  
13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register.  
2. Autonomous CAT acquisition must be longer than AST source clock period  
When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the  
CAT bus clock is turned off, the CAT will start several acquisitions if the period of the AST  
source clock is larger than one CAT acquisition. One AST clock period after the AST trigger,  
the CAT clock will automatically stop and the CAT acquisition can be stopped prematurely,  
ruining the result.  
Fix/Workaround  
Always ensure that the ATCFG1.max field is set so that the duration of the autonomous  
touch acquisition is greater than one clock period of the AST source clock.  
6.1.6  
aWire  
1. aWire MEMORY_SPEED_REQUEST command does not return correct CV  
The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to  
the formula in the aWire Debug Interface chapter.  
Fix/Workaround  
Issue  
a
dummy read to address 0x100000000 before issuing the  
MEMORY_SPEED_REQUEST command and use this formula instead:  
7faw  
fsab = ----------------  
CV – 3  
6.1.7  
Flash  
1. Corrupted data in flash may happen after flash page write operations  
After a flash page write operation from an external in situ programmer, reading (data read or  
code fetch) in flash may fail. This may lead to an exception or to others errors derived from  
this corrupted read access.  
Fix/Workaround  
Before any flash page write operation, each write in the page buffer must preceded by a  
write in the page buffer with 0xFFFF_FFFF content at any address in the page.  
6.2  
Rev. B  
6.2.1  
SCIF  
1. The RC32K output on PA20 is not always permanently disabled  
The RC32K output on PA20 may sometimes re-appear.  
Fix/Workaround  
Before using RC32K for other purposes, the following procedure has to be followed in order  
to properly disable it:  
- Run the CPU on RCSYS  
- Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT  
- Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as  
one  
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- Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as  
zero.  
2. PLLCOUNT value larger than zero can cause PLLEN glitch  
Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN sig-  
nal during asynchronous wake up.  
Fix/Workaround  
The lock-masking mechanism for the PLL should not be used.  
The PLLCOUNT field of the PLL Control Register should always be written to zero.  
3. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature  
The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any loca-  
tion in the SCIF memory range.  
Fix/Workaround  
None.  
6.2.2  
WDT  
1. WDT Control Register does not have synchronization feedback  
When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN),  
Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchro-  
nizer is started to propagate the values to the WDT clcok domain. This synchronization  
takes a finite amount of time, but only the status of the synchronization of the EN bit is  
reflected back to the user. Writing to the synchronized fields during synchronization can lead  
to undefined behavior.  
Fix/Workaround  
-When writing to the affected fields, the user must ensure a wait corresponding to 2 clock  
cycles of both the WDT peripheral bus clock and the selected WDT clock source.  
-When doing writes that changes the EN bit, the EN bit can be read back until it reflects the  
written value.  
6.2.3  
SPI  
1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0  
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI  
module will not start a data transfer.  
Fix/Workaround  
Disable mode fault detection by writing a one to MR.MODFDIS.  
2. Disabling SPI has no effect on the SR.TDRE bit  
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered  
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is  
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer  
is empty, and this data will be lost.  
Fix/Workaround  
Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the  
SPI and PDCA.  
3. SPI disable does not work in SLAVE mode  
SPI disable does not work in SLAVE mode.  
Fix/Workaround  
Read the last received data, then perform a software reset by writing a one to the Software  
Reset bit in the Control Register (CR.SWRST).  
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4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and  
NCPHA=0  
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one  
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,  
then an additional pulse will be generated on SCK.  
Fix/Workaround  
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1  
if CSRn.CPOL=1 and CSRn.NCPHA=0.  
5. SPI mode fault detection enable causes incorrect behavior  
When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate  
properly.  
Fix/Workaround  
Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.  
6. SPI RDR.PCS is not correct  
The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not  
correctly indicate the value on the NPCS pins at the end of a transfer.  
Fix/Workaround  
Do not use the PCS field of the SPI RDR.  
6.2.4  
TWI  
1. TWIS may not wake the device from sleep mode  
If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condi-  
tion, the CPU may not wake upon a TWIS address match. The request is NACKed.  
Fix/Workaround  
When using the TWI address match to wake the device from sleep, do not switch to sleep  
modes deeper than Frozen. Another solution is to enable asynchronous EIC wake on the  
TWIS clock (TWCK) or TWIS data (TWD) pins, in order to wake the system up on bus  
events.  
2. SMBALERT bit may be set after reset  
The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after  
system reset.  
Fix/Workaround  
After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.  
3. Clearing the NAK bit before the BTF bit is set locks up the TWI bus  
When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-  
ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to  
attempt to continue transmitting data, thus locking up the bus.  
Fix/Workaround  
Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been  
set.  
6.2.5  
PWMA  
1. The SR.READY bit cannot be cleared by writing to SCR.READY  
The Ready bit in the Status Register will not be cleared when writing a one to the corre-  
sponding bit in the Status Clear register. The Ready bit will be cleared when the Busy bit is  
set.  
Fix/Workaround  
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ATUC64/128/256L3/4U  
Disable the Ready interrupt in the interrupt handler when receiving the interrupt. When an  
operation that triggers the Busy/Ready bit is started, wait until the ready bit is low in the Sta-  
tus Register before enabling the interrupt.  
6.2.6  
TC  
1. Channel chaining skips first pulse for upper channel  
When chaining two channels using the Block Mode Register, the first pulse of the clock  
between the channels is skipped.  
Fix/Workaround  
Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle  
for the upper channel. After the dummy cycle has been generated, indicated by the  
SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real  
values.  
6.2.7  
CAT  
1. CAT QMatrix sense capacitors discharged prematurely  
At the end of a QMatrix burst charging sequence that uses different burst count values for  
different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the periph-  
eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency.  
This results in premature loss of charge from the sense capacitors and thus increased vari-  
ability of the acquired count values.  
Fix/Workaround  
Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11,  
13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register.  
2. Autonomous CAT acquisition must be longer than AST source clock period  
When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the  
CAT bus clock is turned off, the CAT will start several acquisitions if the period of the AST  
source clock is larger than one CAT acquisition. One AST clock period after the AST trigger,  
the CAT clock will automatically stop and the CAT acquisition can be stopped prematurely,  
ruining the result.  
Fix/Workaround  
Always ensure that the ATCFG1.max field is set so that the duration of the autonomous  
touch acquisition is greater than one clock period of the AST source clock.  
3. CAT consumes unnecessary power when disabled or when autonomous touch not  
used  
A CAT prescaler controlled by the ATCFG0.DIV field will be active even when the CAT mod-  
ule is disabled or when the autonomous touch feature is not used, thereby causing  
unnecessary power consumption.  
Fix/Workaround  
If the CAT module is not used, disable the CLK_CAT clock in the PM module. If the CAT  
module is used but the autonomous touch feature is not used, the power consumption of the  
CAT module may be reduced by writing 0xFFFF to the ATCFG0.DIV field.  
6.2.8  
aWire  
1. aWire MEMORY_SPEED_REQUEST command does not return correct CV  
The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to  
the formula in the aWire Debug Interface chapter.  
Fix/Workaround  
35  
32142DS–06/2013  
ATUC64/128/256L3/4U  
Issue  
a
dummy read to address 0x100000000 before issuing the  
MEMORY_SPEED_REQUEST command and use this formula instead:  
7faw  
fsab = ----------------  
CV – 3  
6.2.9  
Flash  
1. Corrupted data in flash may happen after flash page write operations  
After a flash page write operation from an external in situ programmer, reading (data read or  
code fetch) in flash may fail. This may lead to an exception or to others errors derived from  
this corrupted read access.  
Fix/Workaround  
Before any flash page write operation, each write in the page buffer must preceded by a  
write in the page buffer with 0xFFFF_FFFF content at any address in the page.  
6.3  
Rev. A  
6.3.1  
Device  
1. JTAGID is wrong  
The JTAGID reads 0x021DF03F for all devices.  
Fix/Workaround  
None.  
6.3.2  
FLASHCDW  
1. General-purpose fuse programming does not work  
The general-purpose fuses cannot be programmed and are stuck at 1. Please refer to the  
Fuse Settings chapter in the FLASHCDW for more information about what functions are  
affected.  
Fix/Workaround  
None.  
2. Set Security Bit command does not work  
The Set Security Bit (SSB) command of the FLASHCDW does not work. The device cannot  
be locked from external JTAG, aWire, or other debug accesses.  
Fix/Workaround  
None.  
3. Flash programming time is longer than specified  
36  
32142DS–06/2013  
 
ATUC64/128/256L3/4U  
The flash programming time is now:  
Table 6-1.  
Flash Characteristics  
Symbol Parameter  
Conditions  
Min  
Typ  
7.5  
7.5  
1
Max  
Unit  
TFPP  
TFPE  
TFFP  
TFEA  
Page programming time  
Page erase time  
f
CLK_HSB= 50MHz  
Fuse programming time  
Full chip erase time (EA)  
ms  
9
JTAG chip erase time  
(CHIP_ERASE)  
TFCE  
fCLK_HSB= 115kHz  
250  
Fix/Workaround  
None.  
4. Power Manager  
5. Clock Failure Detector (CFD) can be issued while turning off the CFD  
While turning off the CFD, the CFD bit in the Status Register (SR) can be set. This will  
change the main clock source to RCSYS.  
Fix/Workaround  
Solution 1: Enable CFD interrupt. If CFD interrupt is issues after turning off the CFD, switch  
back to original main clock source.  
Solution 2: Only turn off the CFD while running the main clock on RCSYS.  
6. Sleepwalking in idle and frozen sleep mode will mask all other PB clocks  
If the CPU is in idle or frozen sleep mode and a module is in a state that triggers sleep walk-  
ing, all PB clocks will be masked except the PB clock to the sleepwalking module.  
Fix/Workaround  
Mask all clock requests in the PM.PPCR register before going into idle or frozen mode.  
2. Unused PB clocks are running  
Three unused PBA clocks are enabled by default and will cause increased active power  
consumption.  
Fix/Workaround  
Disable the clocks by writing zeroes to bits [27:25] in the PBA clock mask register.  
6.3.3  
SCIF  
1. The RC32K output on PA20 is not always permanently disabled  
The RC32K output on PA20 may sometimes re-appear.  
Fix/Workaround  
Before using RC32K for other purposes, the following procedure has to be followed in order  
to properly disable it:  
- Run the CPU on RCSYS  
- Disable the output to PA20 by writing a zero to PM.PPCR.RC32OUT  
- Enable RC32K by writing a one to SCIF.RC32KCR.EN, and wait for this bit to be read as  
one  
- Disable RC32K by writing a zero to SCIF.RC32KCR.EN, and wait for this bit to be read as  
zero.  
2. PLL lock might not clear after disable  
37  
32142DS–06/2013  
ATUC64/128/256L3/4U  
Under certain circumstances, the lock signal from the Phase Locked Loop (PLL) oscillator  
may not go back to zero after the PLL oscillator has been disabled. This can cause the prop-  
agation of clock signals with the wrong frequency to parts of the system that use the PLL  
clock.  
Fix/Workaround  
PLL must be turned off before entering STOP, DEEPSTOP or STATIC sleep modes. If PLL  
has been turned off, a delay of 30us must be observed after the PLL has been enabled  
again before the SCIF.PLL0LOCK bit can be used as a valid indication that the PLL is  
locked.  
3. PLLCOUNT value larger than zero can cause PLLEN glitch  
Initializing the PLLCOUNT with a value greater than zero creates a glitch on the PLLEN sig-  
nal during asynchronous wake up.  
Fix/Workaround  
The lock-masking mechanism for the PLL should not be used.  
The PLLCOUNT field of the PLL Control Register should always be written to zero.  
4. RCSYS is not calibrated  
The RCSYS is not calibrated and will run faster than 115.2kHz. Frequencies around 150kHz  
can be expected.  
Fix/Workaround  
If a known clock source is available the RCSYS can be runtime calibrated by using the fre-  
quency meter (FREQM) and tuning the RCSYS by writing to the RCCR register in SCIF.  
5. Writing 0x5A5A5A5A to the SCIF memory range will enable the SCIF UNLOCK feature  
The SCIF UNLOCK feature will be enabled if the value 0x5A5A5A5A is written to any loca-  
tion in the SCIF memory range.  
Fix/Workaround  
None.  
6.3.4  
WDT  
1. Clearing the Watchdog Timer (WDT) counter in second half of timeout period will  
issue a Watchdog reset  
If the WDT counter is cleared in the second half of the timeout period, the WDT will immedi-  
ately issue a Watchdog reset.  
Fix/Workaround  
Use twice as long timeout period as needed and clear the WDT counter within the first half  
of the timeout period. If the WDT counter is cleared after the first half of the timeout period,  
you will get a Watchdog reset immediately. If the WDT counter is not cleared at all, the time  
before the reset will be twice as long as needed.  
2. WDT Control Register does not have synchronization feedback  
When writing to the Timeout Prescale Select (PSEL), Time Ban Prescale Select (TBAN),  
Enable (EN), or WDT Mode (MODE) fieldss of the WDT Control Register (CTRL), a synchro-  
nizer is started to propagate the values to the WDT clcok domain. This synchronization  
takes a finite amount of time, but only the status of the synchronization of the EN bit is  
reflected back to the user. Writing to the synchronized fields during synchronization can lead  
to undefined behavior.  
Fix/Workaround  
-When writing to the affected fields, the user must ensure a wait corresponding to 2 clock  
cycles of both the WDT peripheral bus clock and the selected WDT clock source.  
-When doing writes that changes the EN bit, the EN bit can be read back until it reflects the  
written value.  
38  
32142DS–06/2013  
ATUC64/128/256L3/4U  
6.3.5  
GPIO  
1. Clearing Interrupt flags can mask other interrupts  
When clearing interrupt flags in a GPIO port, interrupts on other pins of that port, happening  
in the same clock cycle will not be registered.  
Fix/Workaround  
Read the PVR register of the port before and after clearing the interrupt to see if any pin  
change has happened while clearing the interrupt. If any change occurred in the PVR  
between the reads, they must be treated as an interrupt.  
6.3.6  
SPI  
1. SPI data transfer hangs with CSR0.CSAAT==1 and MR.MODFDIS==0  
When CSR0.CSAAT==1 and mode fault detection is enabled (MR.MODFDIS==0), the SPI  
module will not start a data transfer.  
Fix/Workaround  
Disable mode fault detection by writing a one to MR.MODFDIS.  
2. Disabling SPI has no effect on the SR.TDRE bit  
Disabling SPI has no effect on the SR.TDRE bit whereas the write data command is filtered  
when SPI is disabled. Writing to TDR when SPI is disabled will not clear SR.TDRE. If SPI is  
disabled during a PDCA transfer, the PDCA will continue to write data to TDR until its buffer  
is empty, and this data will be lost.  
Fix/Workaround  
Disable the PDCA, add two NOPs, and disable the SPI. To continue the transfer, enable the  
SPI and PDCA.  
3. SPI disable does not work in SLAVE mode  
SPI disable does not work in SLAVE mode.  
Fix/Workaround  
Read the last received data, then perform a software reset by writing a one to the Software  
Reset bit in the Control Register (CR.SWRST).  
4. SPI bad serial clock generation on 2nd chip_select when SCBR=1, CPOL=1, and  
NCPHA=0  
When multiple chip selects (CS) are in use, if one of the baudrates equal 1 while one  
(CSRn.SCBR=1) of the others do not equal 1, and CSRn.CPOL=1 and CSRn.NCPHA=0,  
then an additional pulse will be generated on SCK.  
Fix/Workaround  
When multiple CS are in use, if one of the baudrates equals 1, the others must also equal 1  
if CSRn.CPOL=1 and CSRn.NCPHA=0.  
5. SPI mode fault detection enable causes incorrect behavior  
When mode fault detection is enabled (MR.MODFDIS==0), the SPI module may not operate  
properly.  
Fix/Workaround  
Always disable mode fault detection before using the SPI by writing a one to MR.MODFDIS.  
6. SPI RDR.PCS is not correct  
The PCS (Peripheral Chip Select) field in the SPI RDR (Receive Data Register) does not  
correctly indicate the value on the NPCS pins at the end of a transfer.  
Fix/Workaround  
Do not use the PCS field of the SPI RDR.  
39  
32142DS–06/2013  
ATUC64/128/256L3/4U  
6.3.7  
TWI  
1. TWIS may not wake the device from sleep mode  
If the CPU is put to a sleep mode (except Idle and Frozen) directly after a TWI Start condi-  
tion, the CPU may not wake upon a TWIS address match. The request is NACKed.  
Fix/Workaround  
When using the TWI address match to wake the device from sleep, do not switch to sleep  
modes deeper than Frozen. Another solution is to enable asynchronous EIC wake on the  
TWIS clock (TWCK) or TWIS data (TWD) pins, in order to wake the system up on bus  
events.  
2. SMBALERT bit may be set after reset  
The SMBus Alert (SMBALERT) bit in the Status Register (SR) might be erroneously set after  
system reset.  
Fix/Workaround  
After system reset, clear the SR.SMBALERT bit before commencing any TWI transfer.  
3. Clearing the NAK bit before the BTF bit is set locks up the TWI bus  
When the TWIS is in transmit mode, clearing the NAK Received (NAK) bit of the Status Reg-  
ister (SR) before the end of the Acknowledge/Not Acknowledge cycle will cause the TWIS to  
attempt to continue transmitting data, thus locking up the bus.  
Fix/Workaround  
Clear SR.NAK only after the Byte Transfer Finished (BTF) bit of the same register has been  
set.  
4. TWIS stretch on Address match error  
When the TWIS stretches TWCK due to a slave address match, it also holds TWD low for  
the same duration if it is to be receiving data. When TWIS releases TWCK, it releases TWD  
at the same time. This can cause a TWI timing violation.  
Fix/Workaround  
None.  
5. TWIM TWALM polarity is wrong  
The TWALM signal in the TWIM is active high instead of active low.  
Fix/Workaround  
Use an external inverter to invert the signal going into the TWIM. When using both TWIM  
and TWIS on the same pins, the TWALM cannot be used.  
6.3.8  
PWMA  
1. The SR.READY bit cannot be cleared by writing to SCR.READY  
The Ready bit in the Status Register will not be cleared when writing a one to the corre-  
sponding bit in the Status Clear register. The Ready bit will be cleared when the Busy bit is  
set.  
Fix/Workaround  
Disable the Ready interrupt in the interrupt handler when receiving the interrupt. When an  
operation that triggers the Busy/Ready bit is started, wait until the ready bit is low in the Sta-  
tus Register before enabling the interrupt.  
6.3.9  
TC  
1. Channel chaining skips first pulse for upper channel  
When chaining two channels using the Block Mode Register, the first pulse of the clock  
between the channels is skipped.  
40  
32142DS–06/2013  
ATUC64/128/256L3/4U  
Fix/Workaround  
Configure the lower channel with RA = 0x1 and RC = 0x2 to produce a dummy clock cycle  
for the upper channel. After the dummy cycle has been generated, indicated by the  
SR.CPCS bit, reconfigure the RA and RC registers for the lower channel with the real  
values.  
6.3.10  
6.3.11  
ADCIFB  
1. ADCIFB DMA transfer does not work with divided PBA clock  
DMA requests from the ADCIFB will not be performed when the PBA clock is slower than  
the HSB clock.  
Fix/Workaround  
Do not use divided PBA clock when the PDCA transfers from the ADCIFB.  
CAT  
1. CAT QMatrix sense capacitors discharged prematurely  
At the end of a QMatrix burst charging sequence that uses different burst count values for  
different Y lines, the Y lines may be incorrectly grounded for up to n-1 periods of the periph-  
eral bus clock, where n is the ratio of the PB clock frequency to the GCLK_CAT frequency.  
This results in premature loss of charge from the sense capacitors and thus increased vari-  
ability of the acquired count values.  
Fix/Workaround  
Enable the 1kOhm drive resistors on all implemented QMatrix Y lines (CSA 1, 3, 5, 7, 9, 11,  
13, and/or 15) by writing ones to the corresponding odd bits of the CSARES register.  
2. Autonomous CAT acquisition must be longer than AST source clock period  
When using the AST to trigger CAT autonomous touch acquisition in sleep modes where the  
CAT bus clock is turned off, the CAT will start several acquisitions if the period of the AST  
source clock is larger than one CAT acquisition. One AST clock period after the AST trigger,  
the CAT clock will automatically stop and the CAT acquisition can be stopped prematurely,  
ruining the result.  
Fix/Workaround  
Always ensure that the ATCFG1.max field is set so that the duration of the autonomous  
touch acquisition is greater than one clock period of the AST source clock.  
3. CAT consumes unnecessary power when disabled or when autonomous touch not  
used  
A CAT prescaler controlled by the ATCFG0.DIV field will be active even when the CAT mod-  
ule is disabled or when the autonomous touch feature is not used, thereby causing  
unnecessary power consumption.  
Fix/Workaround  
If the CAT module is not used, disable the CLK_CAT clock in the PM module. If the CAT  
module is used but the autonomous touch feature is not used, the power consumption of the  
CAT module may be reduced by writing 0xFFFF to the ATCFG0.DIV field.  
4. CAT module does not terminate QTouch burst on detect  
The CAT module does not terminate a QTouch burst when the detection voltage is  
reached on the sense capacitor. This can cause the sense capacitor to be charged more  
than necessary. Depending on the dielectric absorption characteristics of the capacitor, this  
can lead to unstable measurements.  
Fix/Workaround  
Use the minimum possible value for the MAX field in the ATCFG1, TG0CFG1, and  
TG1CFG1 registers.  
41  
32142DS–06/2013  
ATUC64/128/256L3/4U  
6.3.12  
aWire  
1. aWire MEMORY_SPEED_REQUEST command does not return correct CV  
The aWire MEMORY_SPEED_REQUEST command does not return a CV corresponding to  
the formula in the aWire Debug Interface chapter.  
Fix/Workaround  
Issue  
a
dummy read to address 0x100000000 before issuing the  
MEMORY_SPEED_REQUEST command and use this formula instead:  
7faw  
fsab = ----------------  
CV – 3  
6.3.13  
Flash  
1. Corrupted data in flash may happen after flash page write operations  
After a flash page write operation from an external in situ programmer, reading (data read or  
code fetch) in flash may fail. This may lead to an exception or to others errors derived from  
this corrupted read access.  
Fix/Workaround  
Before any flash page write operation, each write in the page buffer must preceded by a  
write in the page buffer with 0xFFFF_FFFF content at any address in the page.  
6.3.14  
I/O Pins  
1. PA05 is not 3.3V tolerant.  
PA05 should be grounded on the PCB and left unused if VDDIO is above 1.8V.  
Fix/Workaround  
None.  
2. No pull-up on pins that are not bonded  
PB13 to PB27 are not bonded on UC3L0256/128, but has no pull-up and can cause current  
consumption on VDDIO/VDDIN if left undriven.  
Fix/Workaround  
Enable pull-ups on PB13 to PB27 by writing 0x0FFFE000 to the PUERS1 register in the  
GPIO.  
3. PA17 has low ESD tolerance  
PA17 only tolerates 500V ESD pulses (Human Body Model).  
Fix/Workaround  
Care must be taken during manufacturing and PCB design.  
42  
32142DS–06/2013  
ATUC64/128/256L3/4U  
7. Datasheet Revision History  
Please note that the referring page numbers in this section are referred to this document. The  
referring revision in this section are referring to the document revision.  
7.1  
Rev. D – 06/2013  
1.  
Updated the datasheet with a new ATmel blue logo and the last page.  
Added Flash errata.  
2.  
7.2  
Rev. C – 01/2012  
1.  
2.  
Description: DFLL frequency is 20 to 150MHz, not 40 to 150MHz.  
Block Diagram: GCLK_IN is input, not output. CAT SMP corrected from I/O to output. SPI  
NPCS corrected from output to I/O.  
3,  
4,  
Package and Pinout: EXTINT0 in Signal Descriptions table is NMI.  
Supply and Startup Considerations: In 1.8V single supply mode figure, the input voltage is  
1.62-1.98V, not 1.98-3.6V. “On system start-up, the DFLL is disabled” is replaced by “On  
system start-up, all high-speed clocks are disabled”.  
5,  
6,  
ADCIFB: PRND signal removed from block diagram.  
Electrical Charateristics: Added 64-pin package information to I/O Pin Characteristics tables  
and Digital Clock Characteristics table.  
7,  
8.  
Mechanical Characteristics: QFN48 Package Drawing updated. Note that the package drawing  
for QFN48 is correct in datasheet rev A, but wrong in rev B. Added notes to package drawings.  
Summary: Removed Programming and Debugging chapter, added Processor and Architecture  
chapter.  
7.3  
7.4  
Rev. B – 12/2011  
1.  
JTAG Data Registers subchapter added in the Programming and Debugging chapter,  
containing JTAG IDs.  
Rev. A – 12/2011  
1.  
Initial revision.  
43  
32142DS–06/2013  
 
 
 
 
 
ATUC64/128/256L3/4U  
Table of Contents  
Features..................................................................................................... 1  
Description ............................................................................................... 3  
Overview ................................................................................................... 5  
1
2
2.1  
2.2  
Block Diagram ...................................................................................................5  
Configuration Summary .....................................................................................6  
3
4
Package and Pinout ................................................................................. 7  
3.1  
3.2  
3.3  
3.4  
Package .............................................................................................................7  
See Section 3.3 for a description of the various peripheral signals. ................12  
Signal Descriptions ..........................................................................................15  
I/O Line Considerations ...................................................................................18  
Mechanical Characteristics ................................................................... 21  
4.1  
4.2  
4.3  
Thermal Considerations ..................................................................................21  
Package Drawings ...........................................................................................22  
Soldering Profile ..............................................................................................27  
5
6
Ordering Information ............................................................................. 28  
Errata ....................................................................................................... 30  
6.1  
6.2  
6.3  
Rev. C ..............................................................................................................30  
Rev. B ..............................................................................................................32  
Rev. A ..............................................................................................................36  
7
Datasheet Revision History .................................................................. 43  
7.1  
7.2  
7.3  
7.4  
Rev. D – 06/2013 .............................................................................................43  
Rev. C – 01/2012 .............................................................................................43  
Rev. B – 12/2011 .............................................................................................43  
Rev. A – 12/2011 .............................................................................................43  
Table of Contents....................................................................................... i  
i
32142DS–06/2013  
 
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