ATV2500B_14 [ATMEL]
High-performance, High-density Programmable Logic Device;
| 型号： | ATV2500B_14 |
| 厂家： | 
ATMEL |
| 描述： | High-performance, High-density Programmable Logic Device |
| 文件： | 总21页 (文件大小：762K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High-performance, High-density Programmable Logic Device
– Typical 7 ns Pin-to-pin Delay
– Fully Connected Logic Array with 416 Product Terms
• Flexible Output Macrocell
– 48 Flip-flops – Two per Macrocell
– 72 Sum Terms
– All Flip-flops, I/O Pins Feed in Independently
– Achieves Over 80% Gate Utilization
• Enhanced Macrocell Configuration Selections
– D- or T-type Flip-flops
– Product Term or Direct Input Pin Clocking
– Registered or Combinatorial Internal Feedback
• Several Power Saving Options
High-speed
High-density
UV-erasable
Programmable
Logic Device
Device
ICC, Standby
110 mA
30 mA
ATV2500B
ATV2500BQ
ATV2500BL
2 mA
ATV2500BQL 2 mA
• Backward Compatible with ATV2500H/L Software
• Proven and Reliable High-speed UV EPROM Process
• Reprogrammable – Tested 100% for Programmability
• 40-lead Dual-in-line and 44-lead Surface Mount Packages
ATV2500B
ATV2500BQ
ATV2500BQL
Block Diagram
Pin Configurations
LCC/PLCC
DIP
Pin Name
Function
CLK/IN
IN
1
2
3
4
5
6
7
8
9
40 IN
39 IN
IN
Logic Inputs
IN
38 IN
I/O2
I/O3
I/O4
7
8
9
39 I/O7
38 I/O8
37 I/O9
36 I/O10
35 I/O11
34 GND
33 GND
32 I/O23
31 I/O22
30 I/O21
29 I/O20
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
37 IN
36 I/O6
35 I/O7
34 I/O8
33 I/O9
32 I/O10
31 I/O11
30 GND
29 I/O23
28 I/O22
27 I/O21
26 I/O20
25 I/O19
24 I/O18
23 IN
CLK/IN
Pin Clock and
Input
I/O5 10
VCC 11
VCC 12
I/O17 13
I/O16 14
I/O15 15
I/O14 16
I/O13 17
I/O
Bi-directional
Buffers
VCC 10
I/O17 11
I/O16 12
I/O15 13
I/O14 14
I/O13 15
I/O12 16
IN 17
I/O 0,2,4..
I/O 1,3,5..
GND
“Even” I/O Buffers
“Odd” I/O Buffers
Ground
IN 18
IN 19
22 IN
VCC
+5V Supply
IN 20
21 IN
Note:
For ATV2500BQ and
ATV2500BQL (PLCC/LCC
package only) pin 4 and
pin 26 connections are not
required.
Rev. 0249J–05/00
Functional Logic Diagram ATV2500B
Note:
1. Not required for PLCC versions of ATV2500BQ or ATV2500BQL, making them compatible with ATV2500H and ATV2500L
pinout.
ATV2500B(Q)(L)
2
ATV2500B(Q)(L)
Each of the options significantly reduces total system
power and enhances system reliability.
Description
The ATV2500Bs are the highest density PLDs available in
a 40- or 44-lead package. With their fully connected logic
array and flexible macrocell structure, high-gate utilization
is easily obtainable.
Functional Logic Diagram Description
The ATV2500B functional logic diagram describes the
interconnections between the input, feedback pins and
logic cells. All interconnections are routed through the
single global bus.
The ATV2500Bs are organized around a single universal
and-or array. All pins and feedback terms are always avail-
able to every macrocell. Each of the 38 logic pins are array
inputs, as are the outputs of each flip-flop.
The ATV2500Bs are straightforward and uniform PLDs.
The 24 macrocells are numbered 0 through 23. Each mac-
rocell contains 17 AND gates. All AND gates have 172
inputs. The five lower product terms provide AR1, CK1,
CK2, AR2, and OE. These are: one asynchronous reset
and clock per flip-flop, and an output enable. The top 12
product terms are grouped into three sum terms, which are
used as shown in the macrocell diagrams.
In the ATV2500Bs, four product terms are input to each
sum term. Furthermore, each macrocell’s three sum terms
can be combined to provide up to 12 product terms per
sum term with no performance penalty. Each flip-flop is
individually selectable to be either D- or T-type, providing
further logic compaction. Also, 24 of the flip-flops may be
bypassed to provide internal combinatorial feedback to the
logic array.
Eight synchronous preset terms are distributed in a 2/4 pat-
tern. The first four macrocells share Preset 0, the next two
share Preset 1, and so on, ending with the last two macro-
cells sharing Preset 7.
Product terms provide individual clocks and asynchronous
resets for each flip-flop. The flip-flops may also be individu-
ally configured to have direct input pin clocking. Each
output has its own enable product term. Eight synchronous
preset product terms serve local groups of either four or
eight flip-flops. Register preload functions are provided to
simplify testing. All registers automatically reset upon
power-up.
The 14 dedicated inputs and their complements use the
numbered positions in the global bus as shown. Each mac-
rocell provides six inputs to the global bus: (left to right)
feedback F2(1) true and false, flip-flop Q1 true and false,
and the pin true and false. The positions occupied by these
signals in the global bus are the six numbers in the bus dia-
gram next to each macrocell.
Several low-power device options allow selection of the
optimum solution for many power-sensitive applications.
Note:
1. Either the flip-flop input (D/T2) or output (Q2) may be
3
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC which may under-
shoot to -2.0V for pulses of less than 20 ns.
Maximum output pin voltage is VCC + 0.75V DC
which may overshoot to +7.0V for pulses of less
than 20 ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Integrated UV Erase Dose..............................7258 W•sec/cm2
DC and AC Operating Conditions
Commercial
Industrial
Military
0°C - 70°C
-40°C - 85°C
(Ambient)
-55°C - 125°C
Operating Temperature
(Ambient)
(Case)
VCC Power Supply
5V 5%
5V 10%
5V 10%
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
4
Max
6
Units
Conditions
CIN
pF
pF
VIN = 0V
COUT
8
12
VOUT = 0V
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
ATV2500B(Q)(L)
4
ATV2500B(Q)(L)
Output Logic, Registered(1)
S2 = 0
Terms in
S1
0
S0
0
D/T1
D/T2
4
Output Configuration
Registered (Q1); Q2 FB
Registered (Q1); Q2 FB
Registered (Q1); D/T2 FB
8
12
8
1
0
4(1)
4
1
1
Output
S3
0
Configuration
S6
0
Q1 CLOCK
CK1
Active Low
1
Active High
1
CK1 • PIN1
S4
0
Register 1 Type
S7
0
Q2 CLOCK
CK2
D
T
1
1
CK2 • PIN1
S5
0
Register 2 Type
D
T
1
Output Logic, Combinatiorial(1)
S2 = 1
S1
Terms in
S5
S0
D/T1
4(1)
D/T2
Output Configuration
Combinatorial (8 Terms);
Q2 FB
X
X
X
1
0
0
1
1
1
0
4
Combinatorial (4 Terms);
Q2 FB
1
0
1
1
4
4
4(1)
4
Combinatorial (12 Terms);
Q2 FB
4(1)
4(1)
4
Combinatorial (8 Terms);
D/T2 FB
Combinatorial (4 Terms);
D/T2 FB
0
4
Note:
1. These four terms are shared with D/T1.
Clock Option
Note:
1. These diagrams show equivalent logic functions, not
necessarily the actual circuit implementation.
5
DC Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
IIL
Input Load Current
VIN = -0.1V to VCC + 1V
10
µA
Output Leakage
Current
ILO
VOUT = -0.1V to VCC + 0.1V
10
µA
Com.
110
110
30
30
2
190
210
70
85
5
mA
mA
mA
mA
mA
mA
mA
mA
ATV2500B
Ind., Mil.
Com.
ATV2500BQ
ATV2500BL
ATV2500BQL
VCC = MAX,
IN = GND or
VCC f = 0 MHz,
Outputs Open
Power Supply
Current,
Standby
Ind., Mil.
Com.
V
ICC
Ind., Mil.
Com.
2
10
4
2
Ind., Mil.
2
5
Output Short
Circuit Current
IOS
VIL
VIH
VOUT = 0.5V
-120
0.8
mA
V
Input Low Voltage
Input High Voltage
MIN ≤ VCC ≤ MAX
-0.6
2.0
VCC
+
V
0.75
IOL = 8 mA
Com., Ind.
Mil.
0.5
0.5
V
V
V
Output Low
Voltage
VIN = VIH or VIL,
VCC = 4.5V
VOL
I
I
I
OL = 6 mA
OH = -100 µA
VCC - 0.3
2.4
Output High
Voltage
VOH
VCC = MIN
OH = -4.0 mA
Note:
1. See ICC versus frequency characterization curves.
ATV2500B(Q)(L)
6
ATV2500B(Q)(L)
AC Waveforms(1) Input Pin Clock
AC Waveforms(1) Product Term Clock
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
7
Register AC Characteristics, Input Pin Clock
-12
-15
-20
-25
-30
Symbol Parameter
Units
ns
Min
Max
7.5
4
Min
Max
10
5
Min
Max
11
6
Min
Max
12
7
Min
Max
15
8
tCOS
tCFS
tSIS
tSFS
tHS
Clock to Output
Clock to Feedback
Input Setup Time
Feedback Setup Time
Hold Time
0
7
0
9
0
14
14
0
0
20
20
0
0
23
23
0
ns
ns
7
9
ns
0
0
ns
tWS
tPS
Clock Width
5
6
7
8
9
ns
Clock Period
10
12
14
16
18
ns
External Feedback 1/(tSIS + tCOS
)
69
90
52
71
83
40
50
71
31
37
62
26
32
55
MHz
MHz
MHz
FMAXS
Internal Feedback 1/(tSFS + tCFS
No Feedback 1/(tPS
)
)
100
Asynchronous Reset/Preset
Recovery Time
tARS
7
12
15
20
25
ns
ATV2500B(Q)(L)
8
ATV2500B(Q)(L)
Register AC Characteristics, Product Term Clock
-12
-15
-20
-25
-30
Symbol Parameter
Units
ns
Min
Max
12
7
Min
Max
15
Min
Max
20
Min
Max
22
Min
Max
25
tCOA
tCFA
tSIA
tSFA
tHA
Clock to Output
Clock to Feedback
Input Setup Time
Feedback Setup Time
Hold Time
3
4
5
5
12
10
10
8
16
12
15
10
12
14
28
18
13
19
10
13
15
30
20
ns
ns
4
5
ns
3
5
10
11
22
ns
tWA
tPA
Clock Width
5.5
11
7.5
15
ns
Clock Period
ns
External Feedback 1/(tSIA + tCOA
)
62.5
90
50
58
66
33
38
45
27
36
36
23
24
33
MHz
MHz
MHz
FMAXA
Internal Feedback 1/(tSFA + tCFA
)
No Feedback 1/(tPS
)
90
Asynchronous Reset/Preset
Recovery Time
tARA
3
8
12
15
18
ns
AC Waveforms(1) Combinatorial Outputs and Feedback
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
9
AC Characteristics
-12
-15
-20
-25
-30
Symbol Parameter
Units
Min
Max
Min
Max
Min
Max
Min
Max
Min
Max
tPD1
tPD2
tPD3
tPD4
Input to Non-registered Output
12
15
20
25
30
ns
Feedback to Non-registered
Output
12
8
15
11
11
20
15
15
25
18
18
30
20
20
ns
ns
ns
Input to Non-registered Feedback
Feedback to Non-registered
Feedback
8
tEA1
tER1
tEA2
tER2
tAW
Input to Output Enable
12
12
12
12
15
15
15
15
20
20
20
20
25
25
25
25
30
30
30
30
ns
ns
ns
ns
ns
Input to Output Disable
Feedback to Output Enable
Feedback to Output Disable
Asynchronous Reset Width
6
8
12
15
18
Asynchronous Reset to
Registered Output
tAP
15
12
18
15
22
19
28
25
30
30
ns
ns
Asynchronous Reset to
Registered Feedback
tAPF
Input Test Waveforms and
Measurement Levels
Output Test Load
Preload and Observability of Registered Outputs
The ATV2500Bs registers are provided with circuitry to
allow loading of each register asynchronously with either a
high or a low. This feature will simplify testing since any
state can be forced into the registers to control test
sequencing. A VIH level on the odd I/O pins will force the
appropriate register high; a VIL will force it low, independent
of the polarity or other configuration bit settings.
SMP lead 23 is pulsed high, the data on the I/O pins is
placed into the 12 registers chosen by the Q select and
even/odd select pins.
Register 2 observability mode is entered by placing an
10.25V to 10.75V signal on pin/lead 2. In this mode, the
contents of the buried register bank will appear on the
associated outputs when the OE control signals are active.
The PRELOAD state is entered by placing an 10.25V to
10.75V signal on SMP lead 42. When the preload clock
ATV2500B(Q)(L)
10
ATV2500B(Q)(L)
Level Forced on
Odd I/O Pin
during
PRELOAD Cycle
Q Select Pin
State
Even Q1 State
after Cycle
Even Q2 State
after Cycle
Odd Q1 State
after Cycle
Odd Q2 State
after Cycle
Even/Odd Select
VIH/VIL
VIH/VIL
VIH/VIL
VIH/VIL
Low
High
Low
High
Low
Low
High
High
High/Low
X
X
X
X
X
X
High/Low
X
High/Low
X
X
X
X
X
High/Low
Power-up Reset
.
The registers in the ATV2500Bs are designed to reset dur-
ing power-up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. The output
state will depend on the polarity of the output buffer.
This feature is critical for state as nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock pin or
terms high, and
3. The clock pin, and any signals from which clock
terms are derived, must remain stable during tPR
.
Parameter
Description
Typ
600
3.8
Max
1000
4.5
Units
ns
tPR
Power-up Reset Time
Power-up Reset Voltage
VRST
V
11
running on separate clocks. Individual flip-flop clock
source selection further allows mixing higher
performance pin clocking and flexible product term
clocking within one design.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of ATV2500B fuse patterns. Once programmed, the out-
puts will read programmed during verify. The security fuse
should be programmed last, as its effect is immediate.
• A Total of 48 Registers – The ATV2500B provides two
flip-flops per macrocell – a total of 48. Each register has
its own clock and reset terms, as well as its own sum
term.
The security fuse also inhibits Preload and Q2
observability.
• Independent I/O Pin and Feedback Paths – Each I/O
pin on the ATV2500B has a dedicated input path. Each
of the 48 registers has its own feedback term into the
array as well. These features, combined with individual
product terms for each I/O’s output enable, facilitate true
bi-directional I/O design.
Atmel CMOS PLDs
The ATV2500Bs utilize an advanced 0.65-micron CMOS
EPROM technology. This technology’s state of the art fea-
tures are the optimum combination for PLDs:
• CMOS technology provides high speed, low power, and
high noise immunity.
• Combinable Sum Terms – Each output macrocell’s
three sum terms may be combined into a single term.
This provides a fan in of up to 12 product terms per sum
term with no speed penalty.
• EPROM technology is the most cost effective method for
producing PLDs – surpassing bipolar fusible link
technology in low cost, while providing the necessary
reprogrammability.
Programming Software Support
As with all other Atmel PLDs, several third party PLD devel-
opment software products and programmers will support
the ATV2500Bs.
• EPROM reprogrammability, which is 100% tested before
shipment, provides inherently better programmability and
reliability than one-time fusible PLDs.
Several third party programmers will support the
ATV2500B as well. Additionally, the ATV2500B may be
programmed to perform the ATV2500H/Ls functional sub-
set (no T-type flip-flops, pin clocking or D/T2 feedback)
using the ATV2500H/L JEDEC file. In this case, the
ATV2500B becomes a direct replacement or speed
upgrade for the ATV2500H/L (additional GND connections
are required). Please refer to the Programmable Logic
Development Tools section for a complete PLD software
and programmer listing.
Using the ATV2500Bs Many Advanced
Features
The ATV2500Bs advanced flexibility packs more usable
gates into 44 leads than other PLDs. Some of the
ATV2500Bs key features are:
• Fully Connected Logic Array – Each array input is
always available to every product term. This makes logic
placement a breeze.
• Selectable D- and T-Type Registers – Each ATV2500B
flip-flop can be individually configured as either D- or T-
type. Using the T-type configuration, JK and SR flip-flops
are also easily created. These options allow more
efficient product term usage.
Erasure Characteristics
The entire memory array of an ATV2500B is erased after
exposure to ultraviolet light at a wavelength of 2537 Å.
Complete erasure is assured after a minimum of 20 min-
utes exposure using 12,000 µW/cm2 intensity lamps
spaced one inch away from the chip. Minimum erase time
for lamps at other intensity ratings can be calculated from
the minimum integrated erasure dose of 15 W•sec/cm2. To
prevent unintentional erasure, an opaque label is recom-
mended to cover the clear window on any UV erasable
PLD which will be subjected to continuous fluorescent
indoor lighting or sunlight.
• Buried Combinatorial Feedback – Each macrocell’s
Q2 register may be bypassed to feed its input (D/T2)
directly back to the logic array. This provides further logic
expansion capability without using precious pin
resources.
• Selectable Synchronous/Asynchronous Clocking –
Each of the ATV2500Bs flip-flops has a dedicated clock
product term. This removes the constraint that all
registers use the same clock. Buried state machines,
counters and registers can all coexist in one device while
ATV2500B(Q)(L)
12
ATV2500B(Q)(L)
Note:
1. All normalized values referenced to maximum specification in AC Characteristics of data sheet.
13
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE (VCC=5V,TA=25°C)
0
-1
-2
-3
-4
-5
I
O
H
m
A
3.5
3.8
4.1
4.4
4.7
5.0
OUTPUT VOLTAGE (V)
OUTPUT SOURCE CURRENT
vs. OUTPUT VOLTAGE (VCC=5V,TA=25°C)
0
-20
-40
-60
-80
I
O
H
m
A
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
OUTPUT VOLTAGE (V)
NORMALIZED TPD
vs. AMBIENT TEMPERATURE(VCC = 5V)
1.3
1.2
1.1
1.0
0.9
0.8
ATV2500B(L)
N
O
R
M
T
P
D
ATV2500BQ(L)
-55
-25
5
35
65
95
125
AMBIENT TEMPERATURE(C)
NORMALIZED TCO
vs. SUPPLYVOLTAGE (TA=25°C)
NORMALIZED TCO
vs. AMBIENT TEMPERATURE(VCC = 5V)
1.3
1.3
1.2
N
O
R
M
N
O
R
M
1.2
1.1
1.0
ATV2500B(L)
1.1
1.0
0.9
0.8
ATV2500BQ(L)
ATV2500B(L)
ATV2500BQ(L)
T
C
O
T
C
O
0.9
0.8
4.50
4.75
5.00
5.25
5.50
-55
-25
5
35
65
95
125
AMBIENT TEMPERATURE(C)
SUPPLYVOLTAGE (V)
Note:
1. All normalized values referenced to maximum specification in AC Characteristics of data sheet.
ATV2500B(Q)(L)
14
ATV2500B(Q)(L)
Note:
1. All normalized values referenced to maximum specification in AC Characteristics of data sheet.
15
Ordering Information
tPD
tCOS
Ext. fMAXS
(ns)
(ns)
(MHz)
Ordering Code
Package
Operation Range
12
15
7.5
10
69
52
ATV2500B-12JC
ATV2500B-12KC
44J
Commercial
44KW
(0°C to 70°C)
ATV2500B-15JC
ATV2500B-15KC
44J
Commercial
44KW
(0°C to 70°C)
ATV2500B-15JI
ATV2500B-15KI
44J
Industrial
44KW
(-40°C to 85°C)
ATV2500B-15KM
ATV2500B-15LM
44KW
44LW
Military
(-55°C to 125°C)
ATV2500B-15KM/883
ATV2500B-15LM/883
44KW
44LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
20
11
40
ATV2500BL-20JC
ATV2500BL-20KC
44J
Commercial
44KW
(0°C to 70°C)
ATV2500BL-20JI
ATV2500BL-20KI
44J
Industrial
44KW
(-40°C to 85°C)
ATV2500BL-20KM
ATV2500BL-20LM
44KW
44LW
Military
(-55°C to 125°C)
ATV2500BL-20KM/883
ATV2500BL-20LM/883
44KW
44LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
20
11
40
ATV2500BQ-20DC
ATV2500BQ-20JC
ATV2500BQ-20KC
ATV2500BQ-20PC
40DW6
44J
Commercial
(0°C to 70°C)
44KW
40P6
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
40DW6
44J
40-pin, 0.600" Wide, Ceramic, Dual Inline Package (Cerdip)
44-lead, Plastic J-leaded Chip Carrier OTP (PLCC)
44KW
40P6
44LW
44-lead, Windowed, Ceramic J-leaded Chip Carrier (JLCC)
40-pin, 0.600" Wide, Plastic, Dual Inline Package OTP (PDIP)
44-pad, Windowed, Ceramic Leadless Chip Carrier (LCC)
ATV2500B(Q)(L)
16
ATV2500B(Q)(L)
Ordering Information (Continued)
tPD
tCOS
Ext. fMAXS
(ns)
(ns)
(MHz)
Ordering Code
Package
Operation Range
25
12
31
ATV2500BQ-25DC
ATV2500BQ-25JC
ATV2500BQ-25KC
ATV2500BQ-25PC
40DW6
44J
Commercial
(0°C to 70°C)
44KW
40P6
ATV2500BQ-25DI
ATV2500BQ-25JI
ATV2500BQ-25KI
ATV2500BQ-25PI
40DW6
44J
Industrial
(-40°C to 85°C)
44KW
40P6
ATV2500BQ-25DM
ATV2500BQ-25KM
ATV2500BQ-25LM
40DW6
44KW
44LW
Military/883C
(-55°C to 125°C)
ATV2500BQ-25DM/883
ATV2500BQ-25KM/883
ATV2500BQ-25LM/883
40DW6
44KW
44LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
25
25
30
12
12
31
31
ATV2500BQL-25DC
ATV2500BQL-25JC
ATV2500BQL-25KC
ATV2500BQL-25PC
40DW6
44J
Commercial
(0°C to 70°C)
44KW
40P6
ATV2500BQL-25DI
ATV2500BQL-25JI
ATV2500BQL-25KI
ATV2500BQL-25PI
40DW6
44J
Industrial
(-40°C to 85°C)
44KW
40P6
15
15
26
26
ATV2500BQL-30DM
ATV2500BQL-30KM
ATV2500BQL-30LM
40DW6
44KW
44LW
Military/883C
(-55°C to 125°C)
ATV2500BQL-30DM/883
ATV2500BQL-30KM/883
ATV2500BQL-30LM/883
40DW6
44KW
44LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
40DW6
44J
40-pin, 0.600" Wide, Ceramic, Dual Inline Package (Cerdip)
44-lead, Plastic J-leaded Chip Carrier OTP (PLCC)
44KW
40P6
44LW
44-lead, Windowed, Ceramic J-leaded Chip Carrier (JLCC)
40-pin, 0.600" Wide, Plastic, Dual Inline Package OTP (PDIP)
44-pad, Windowed, Ceramic Leadless Chip Carrier (LCC)
17
Ordering Information (Continued)
tPD
tCOS
Ext. fMAXS
(ns)
(ns)
(MHz)
Ordering Code
Package
Operation Range
15
20
25
30
10
11
12
15
52
40
31
26
5962 - 9154504MXX
5962 - 9154504MYX
44LW
44KW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
5962 - 9154505MXX
5962 - 9154505MYX
44LW
44KW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
5962 - 9154506MXX
5962 - 9154506MYX
5962 - 9154506MQA
44LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
44KW
40DW6
5962 - 9154507MXX
5962 - 9154507MYX
5962 - 9154507MQA
44LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
44KW
40DW6
Using “C” Product for Industrial
To use commercial product for Industrial temperature ranges, down-grade one speed grade from the “I” to the “C” device
(7 ns “C” = 10 ns “I”) and de-rate power by 30%.
Package Type
40DW6
44J
40-pin, 0.600" Wide, Ceramic, Dual Inline Package (Cerdip)
44-lead, Plastic J-leaded Chip Carrier OTP (PLCC)
44KW
40P6
44LW
44-lead, Windowed, Ceramic J-leaded Chip Carrier (JLCC)
40-pin, 0.600" Wide, Plastic, Dual Inline Package OTP (PDIP)
44-pad, Windowed, Ceramic Leadless Chip Carrier (LCC)
ATV2500B(Q)(L)
18
Packaging Information
40DW6, 40-pin, 0.600” Wide, Windowed, Ceramic
44J, 44-lead, Plastic J-leaded Chip Carrier (PLCC)
Dual Inline Package (Cerdip)
Dimensions in Inches and (Millimeters)
MIL-STD-1835 D-5 CONFIG A
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AC
.045(1.14) X 30° - 45°
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
.012(.305)
.008(.203)
.630(16.0)
.590(15.0)
.656(16.7)
SQ
.650(16.5)
.032(.813)
.026(.660)
.021(.533)
.013(.330)
.695(17.7)
.685(17.4)
SQ
.043(1.09)
.020(.508)
.120(3.05)
.050(1.27) TYP
.500(12.7) REF SQ
.090(2.29)
.180(4.57)
.165(4.19)
.022(.559) X 45° MAX (3X)
44KW, 44-lead, Windowed, Ceramic J-leaded Chip
Carrier (JLCC)
40P6, 40-pin, 0.600” Wide, Plastic Dual Inline
Package (PDIP)
Dimensions in Inches and (Millimeters)
MIL-STD-1835 CJ1
Dimensions in Inches and (Millimeters)
JEDED STANDARD MS-011 AC
2.07(52.6)
2.04(51.8)
PIN
1
.035(.889) X 45°
.045(1.14) X 45°
.010(.254)
.006(.152)
.566(14.4)
.530(13.5)
.630(16.0)
.590(15.0)
.665(16.9)
.645(16.4)
SQ
.032(.813)
.026(.660)
.090(2.29)
MAX
.021(.533)
.017(.432)
.695(17.7)
.685(17.4)
1.900(48.26) REF
SQ
.220(5.59)
MAX
.005(.127)
MIN
.045(1.14)
.050(1.27) TYP
.500(12.7) REF SQ
.035(.889)
.120(3.05)
.090(2.29)
SEATING
PLANE
.065(1.65)
.015(.381)
.161(4.09)
.125(3.18)
.180(4.57)
.156(3.96)
.022(.559)
.014(.356)
.065(1.65)
.041(1.04)
.110(2.79)
.090(2.29)
.630(16.0)
.590(15.0)
0
15
REF
.025(.635) RADIUS MAX (3X)
.012(.305)
.008(.203)
.690(17.5)
.610(15.5)
ATV2500B(Q)(L)
19
ATV2500B(Q)(L)
Packaging Information
44LW, 44-pad, Windowed, Ceramic Leadless Chip
Carrier (LCC)
Dimensions in Inches and (Millimeters)*
MIL-STD-1835 C-5
*Controlling dimension: millimeters
20
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Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard war-
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