ATV2500H-35JC [ATMEL]
High-Density UV-Erasable Programmable Logic Device; 高密度的紫外线可擦除可编程逻辑器件
| 型号： | ATV2500H-35JC |
| 厂家： | 
ATMEL |
| 描述： | High-Density UV-Erasable Programmable Logic Device |
| 文件： | 总15页 (文件大小：665K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Third Generation Programmable Logic Structure
– Easily Achieves Gate Utilization Factors of 80 Percent
• Increased Logic Flexibility
– 86 Inputs and 72 Sum Terms
• Flexible Output Macrocell
– 48 Flip-Flops - 2 per Macrocell
– 3 Sum Terms - Can Be OR'ed and Shared
• High-Speed
• Low-Power — Less than 0.5 mA Typical (ATV2500L)
• Multiple Feedback Paths Provide for Buried State Machines
and I/O Bus Compatibility
High-Density
UV-Erasable
Programmable
Logic Device
• Asynchronous Clocks and Resets
– Multiple Synchronous Presets - One per Four or Eight Flip-Flops
• Proven and Reliable High Speed CMOS EPROM Process
– 2000V ESD Protection
– 200 mA Latchup Immunity
• Reprogrammable - Tested 100% for Programmability
• 40-pin Dual-In-line and 44-Lead Surface Mount Packages
Block Diagram
ATV2500H
ATV2500L
Description
The ATV2500H/L is the most powerful programmable logic device available in a 40-
pin package. Increased product terms, sum terms, and flip-flops translate into many
more usable gates. High gate utilization is easily obtainable.
The ATV2500H/L is organized around a global bus. All pin and feedback terms are
always available to every logic cell. Each of the 38 logic pins and their complements
are array inputs, as well as the true and false outputs of each of the 48 flip-flops.
(continued)
DIP
PLCC/LCC
Pin Configurations
IN
IN
1
2
3
4
5
6
7
8
9
40 IN
Pin Name Function
39 IN
IN
38 IN
I/O2
I/O3
I/O4
7
8
9
39 I/O7
38 I/O8
37 I/O9
36 I/O10
35 I/O11
34 GND
33 GND
32 I/O23
31 I/O22
30 I/O21
29 I/O20
IN
Logic Inputs
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
37 IN
36 I/O6
35 I/O7
34 I/O8
33 I/O9
32 I/O10
31 I/O11
30 GND
29 I/O23
28 I/O22
27 I/O21
26 I/O20
25 I/O19
24 I/O18
23 IN
I/O5 10
VCC 11
VCC 12
I/O17 13
I/O16 14
I/O15 15
I/O14 16
I/O13 17
I/O
Bidirectional Buffers
I/O, 0,2,4.. “Even” I/O Buffers
I/O, 1,3,5.. “Odd” I/O Buffers
VCC 10
I/O17 11
I/O16 12
I/O15 13
I/O14 14
I/O13 15
I/O12 16
IN 17
*
No Internal Connection
+5V Supply
VCC
* = No Connect
IN 18
IN 19
22 IN
Rev. 0025E–05/98
IN 20
21 IN
There are 416 product terms available. Four product terms
are input to each sum term. The three sum terms per logic
cell can be combined to provide up to twelve product terms,
combinatorial and registered. Independent of output config-
uration, the two flip-flops are always usable, and always
have at least four product term inputs.
Product terms are available providing asynchronous
resets, flip-flop clocks, and output enables. One reset and
one clock term are provided per flip-flop, with one enable
term per output. Eight product terms provide local synchro-
nous presets, divided up into banks of four and eight flip-
flops. Register preload and buried register observability
simplify testing. The device has an internal power up clear
function.
Functional Logic Diagram ATV2500H/L
ATV2500H/L
2
ATV2500H/L
twelve product terms are grouped into three sum terms,
which are used as shown in the macrocell diagrams.
Functional Logic Diagram Description
The ATV2500H/L Functional Logic Diagram describes the
interconnections between the input, feedback pins and
logic cells. All interconnections are routed through the glo-
bal bus.
Eight synchronous preset terms are distributed in a 2/4 pat-
tern. The first four macrocells share Preset 0, the next two
share Preset 1, and so on, ending with the last two macro-
cells sharing Preset 7.
The ATV2500H/L is a straightforward and uniform PLD.
The twenty-four macrocells are numbered 0 through 23.
Each macrocell contains 17 AND gates. All AND gates
have 172 inputs. The five lower product terms provide AR1,
CK1, CK2, AR2, and OE. These are: one asynchronous
reset and clock per flip-flop, and an output enable. The top
The fourteen dedicated inputs and their complements use
the numbered positions in the global bus as shown. Each
macrocell provides six inputs to the global bus: (left to right)
flip-flop Q2 true and false, flip-flop Q1 true and false, and
the pin true and false. The positions occupied by these sig-
nals in the global bus are the six numbers in the bus dia-
gram next to each macrocell.
Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias............................... -55°C to + 125°C
Storage Temperature.................................... -65°C to + 150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V dc, which may under-
shoot to -2.0V for pulses of less than 20 ns. Max-
imum output pin voltage is Vcc + 0.75V dc, which
may overshoot to 7.0V for pulses of less than 20
ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Integrated UV Erase Dose..............................7258 W.sec/cm2
3
Output Logic, Registered
Output Logic, Combinatorial
These diagrams show equivalent logic functions, not necessarily the actual circuit implementation.
Terms In
Terms In
S2
0
S1
0
S0
0
D1
D2
4
Output Configuration
Registered (Q1)
S2
S1
0
S0
0
D1
4(1)
4
D2
4
Output Configuration
Combinatorial (8 Terms)
Combinatorial (4 Terms)
8
1
1
0
1
0
12
4(1)
Registered (Q1)
0
1
4
4(1)
4(1) Combinatorial (12 Terms)
Note:
1. These 4 terms are shared with D1.
1
1
0
Note:
1. These 4 terms are shared with D1.
S3
0
Output Configuration
Active Low
S3
0
Output Configuration
Active Low
1
Active High
1
Active High
DC and AC Operating
ATV2500H-25
0°C - 70°C
ATV2500H/L-30
0°C - 70°C
ATV2500H/L-35
Operating
Temperature
(Case)
Com.
Ind.
0°C - 70°C
-40°C - 85°C
-55°C - 125°C
5V ± 10%
-40°C - 85°C
-55°C - 125°C
5V ± 10%
-40°C - 85°C
-55°C - 125°C
5V ± 10%
Mil.
VCC Power Supply
ATV2500H/L
4
ATV2500H/L
DC Characteristics
Symbol Parameter
Condition
Min
Typ
Max
10
Units
µA
ILI
Input Load Current
VIN = -0.1V to VCC + 1V
VOUT = -0.1V to VCC + 0.1V
ILO
Output Leakage
Current
10
µA
ICC
Power Supply
Current
VCC = MAX,
VIN = GND or VCC
Outputs Open
ATV2500L
Com.
0.5
0.5
80
5
mA
mA
mA
mA
mA
Ind.,Mil.
10
ATV2500H Com.
Ind.,Mil.
160
180
-120
80
(1)
IOS
VIL
Output Short
Circuit Current
VOUT = 0.5V
Input Low Voltage
Input High Voltage
Output Low Voltage
-0.6
2.0
0.8
VCC + 0.75
0.5
V
V
V
VIH
VOL
VIN = VIH or VIL,
IOL = 8 mA Com,Ind; 6 mA Mil.
VOH
Output High Voltage IOH = -100 µA
OH = -4.0 mA
VCC - 0.3
2.4
V
V
I
Note:
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. This parame-
ter is only sampled and is not 100% tested. See Absolute Maximum Ratings.
Pin Capacitance (f = MHz, T = 25°C)(1)
Typ
Max
Units
pF
Conditions
VIN = OV
CIN
4
6
COUT
Note:
8
12
pF
VOUT = OV
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
5
AC Waveforms(1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics for the ATV2500L
ATV2500L-30
ATV2500L-35
Symbol
Parameter
Min
Max
Min
Max
Units
tPD
Input or Feedback to
30
35
ns
Non-Registered Output
tEA
tER
tCO
tCF
tSI1
tSI2
Input to Output Enable
Input to Output Disable
Clock to Output
30
30
30
20
35
35
35
20
ns
ns
ns
ns
ns
ns
5
5
Clock to Feedback
10
20
20
15
22
22
Input Setup Time, Output Register
Input Setup
Time, Buried Register(1)
tSF
tH1
tH2
tW
Feedback Setup Time
10
10
5
15
15
5
ns
ns
Hold Time, Output Register
Hold Time, Buried Register(1)
Clock Width
ns
15
30
17
35
ns
tP
Clock Period
ns
FMAX
tAW
tAR
tAP
Maximum Frequency (1/tP)
Asynchronous Reset Width
Asynchronous Reset Recovery Time
33
30
28
35
MHz
ns
18
18
20
20
ns
Asynchronous Reset to
Registered Output Reset
ns
Note:
1. Buried registers include all 24 Q2 registers and any of the 24 Q1 registers in macrocells configured as combinatorial.
ATV2500H/L
6
ATV2500H/L
AC Characteristics for the ATV2500H
ATV2500H-25
ATV2500H-30
ATV2500H-35
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Units
tPD
Input or Feedback to
25
30
35
ns
Non-Registered Output
tEA
tER
tCO
tCF
tSI1
Input to Output Enable
Input to Output Disable
Clock to Output
25
25
25
18
30
30
30
20
35
35
35
20
ns
ns
ns
ns
ns
10
10
10
12
12
12
15
15
15
Clock to Feedback
Input Setup
Time, Output Register
tSI2
Input Setup
5
5
5
ns
Time, Buried Register(1)
tSF
tH1
tW
Feedback Setup Time
Hold Time
7
5
10
5
15
5
ns
ns
Clock Width
10
25
12
30
15
35
ns
tP
Clock Period
ns
FMAX
tAW
Maximum Frequency (1/tP)
40
25
33
30
28
35
MHz
ns
Asynchronous Reset
Width
15
15
18
18
20
20
tAR
Asynchronous Reset
Recovery Time
ns
ns
tAP
Note:
Asynchronous Reset to
Registered Output Reset
1. Buried registers include all 24 Q2 registers and any of the 24 Q1 registers in macrocells configured as combinatorial.
Input Test Waveforms and
Measurement Levels
Output Test Loads
tR, tF < 5 ns (10% to 90%)
7
Preload and Observability of Registered Outputs
The ATV2500H/L's registers are provided with circuitry to
allow loading of each register asynchronously with either a
high or a low. This feature will simplify testing since any
state can be forced into the registers to control test
sequencing. A VIH level on the Odd I/O pins will force the
appropriate register high; a VIL will force it low, independent
of the polarity or other configuration bit settings.
clock term is pulsed high, (pin 21 on the DIP, pin 23 on the
SMP) the data on the I/O pins is placed into the 12 regis-
ters chosen by the Q select and even/odd select pins.
Register 2 observability mode is entered by placing an 11V
to 14V signal on pin 2 (DIP or SMP). In this mode, the con-
tents of the buried register bank will appear on the associ-
ated outputs when the OE control signals are active.
The preload state is entered by placing an 11V to 14V sig-
nal on pin 38 on the DIP and pin 42 on the SMP. When the
Level forced on Odd
I/O pin during
preload cycle.
Q Select
pin state
Even/
Odd select
Even Q1 state
after cycle
Even Q2 state
after cycle
Odd Q1 state
after cycle
Odd Q2 state
after cycle
VIH
VIL
VIH
VIL
VIH
VIL
VIH
VIL
Low
Low
High
High
Low
Low
High
High
Low
Low
Low
Low
High
High
High
High
High
Low
X
X
X
X
X
X
X
High
Low
X
X
X
X
X
X
X
High
Low
X
X
X
X
X
X
X
High
Low
X
X
X
Power-Up Reset
The registers in the ATV2500H/L are designed to reset dur-
ing power-up. At a point delayed slightly from VCC crossing
3.8V, all registers will be reset to the low state. The output
state will depend on the polarity of the output buffer.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock term
high,
Parameter Description Min
Typ
Max
Units
tPR
Power-Up
600
1000
ns
3. The signals from which the clock is derived must
remain stable during tPR.
Reset Time
ATV2500H/L
8
ATV2500H/L
• Independent I/O Pin and Feedback Paths -
Security Fuse Usage
Each I/O pin on the ATV2500/H has a dedicated input path.
Each of the 48 registers has individual feedback terms into
the array. This feature, combined with individual product
terms for each I/O's output enable, facilitates designs using
bi-directional I/O buses.
A single fuse is provided to prevent unauthorized copying
of the ATV2500H/L fuse patterns. Once programmed, the
outputs will read programmed during verify. The security
fuse should be programmed last, as its effect is immediate.
The security fuse also inhibits preload and Q2 observabil-
ity.
• Three Sum Terms per Macrocell -
The ATV2500H/L macrocell can be configured with one
SUM term feeding the output, and still have two SUM terms
feeding the flip-flops. This is the simplest method for inter-
facing with an I/O bus, and no flip-flops need be sacrificed.
Atmel CMOS PLDs
Atmel's Erasable Programmable Logic Devices utilize an
advanced 1.25-micron CMOS EPROM technology. This
technology's state of the art features are the optimum com-
bination for PLDs:
• Combinable Sum Terms -
Each output macrocell's three SUM terms can be combined
in an OR gate before the output or the register. This pro-
vides up to twelve product terms per output or flip-flop.
When the registered output configuration is chosen, eight
terms are automatically available to D1. The four terms
feeding D2 can also be shared with D1, giving it a total of
twelve. In the combinatorial mode, four, eight, or twelve
terms can feed the output, with the middle four still driving
D1 and the bottom four still driving D2.
• CMOS technology provides high speed, low power, and
high noise immunity.
• EPROM technology is the most cost effective method for
producing PLDs - surpassing bipolar fusible link
technology in low cost, while providing the necessary
reprogrammability.
• EPROM reprogrammability, which is 100% tested before
shipment, provides inherently better programmability and
reliability than one-time fusible PLDs.
Programming Software Support
• Atmel's EPROM process has proven extremely reliable
in the volume production of a full line of advanced
EPROM memory products, from 64K to one-megabit
devices.
Software which is capable of transforming Boolean equa-
tions, state machine descriptions and truth tables into
JEDEC files for the ATV2500H/L is currently available from
several PLD software vendors. Please refer to the Pro-
grammable Logic Development Tools section for a com-
plete listing of the PLD software support.
Using the ATV2500H/L's Many
Advanced Features
The ATV2500H/L's flexibility puts more usable gates in 40
pins than other PLDs. Some of the ATV2500H/L's key fea-
tures are:
Erasure Characteristics
The entire memory array of an ATV2500H/L is erased after
exposure to ultraviolet light at a wavelength of 2537 Å.
Complete erasure is assured after a minimum of twenty
minutes exposure using 12,000 µW/cm2 intensity lamps
spaced one inch away from the chip. Minimum erase time
for lamps at other intensity ratings can be calculated from
the minimum integrated erasure dose of fifteen W•sec/cm2.
To prevent unintentional erasure, an opaque label is rec-
ommended to cover the clear window on any UV erasable
PLD which will be subjected to continuous fluorescent
indoor lighting or sunlight.
• Asynchronous Clocks -
Each of the flip-flops in the ATV2500H/L has a dedicated
product term driving the clock. The user is no longer con-
strained to using one clock for all the registers. Buried state
machines, counters, and registers can all coexist in one
device, while running on separate clocks. The ATV2500H/L
clock period matches that of similar synchronous devices.
• A Total of 48 Registers -
The ATV2500H/L provides two flip-flops for each output
macrocell - a total of 48. Each register has its own clock
and reset product terms, as well as its own sum term.
9
Note:
All normalized values referenced to maximum specification in AC characteristics section of datasheet.
ATV2500H/L
10
ATV2500H/L
11
Ordering Information
tPD
tCO
fMAX
(ns)
(ns)
(MHz)
Ordering Code
Package
Operation Range
25
25
40
ATV2500H-25DC
ATV2500H-25JC
ATV2500H-25KC
ATV2500H-25LC
ATV2500H-25PC
40DW6
44J
Commercial
(0°C to 70°C)
44KW
44LW
40P6
ATV2500H-25DI
ATV2500H-25JI
ATV2500H-25KI
ATV2500H-25LI
ATV2500H-25PI
40DW6
44J
Industrial
(-40°C to 85°C)
44KW
44LW
40P6
ATV2500H-25DM
ATV2500H-25KM
ATV2500H-25LM
40DW6
44KW
44LW
Military
(-55°C to 125°C)
ATV2500H-25DM/883
ATV2500H-25KM/883
ATV2500H-25LM/883
40DW6
44KW
44LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
30
35
25
30
35
25
33
28
40
ATV2500H-30DC
ATV2500H-30JC
ATV2500H-30KC
ATV2500H-30LC
ATV2500H-30PC
40DW6
44J
Commercial
(0°C to 70°C)
44KW
44LW
40P6
ATV2500H-30DI
ATV2500H-30JI
ATV2500H-30KI
ATV2500H-30LI
ATV2500H-30PI
40DW6
44J
Industrial
(-40°C to 85°C)
44KW
44LW
40P6
ATV2500H-35DC
ATV2500H-35JC
ATV2500H-35KC
ATV2500H-35LC
ATV2500H-35PC
40DW6
44J
Commercial
(0°C to 70°C)
44KW
44LW
40P6
ATV2500H-35DI
ATV2500H-35JI
ATV2500H-35KI
ATV2500H-35LI
ATV2500H-35PI
40DW6
44J
Industrial
(-40°C to 85°C)
44KW
44LW
40P6
5962-91545 02M QA
5962-91545 02M XX
5962-91545 02M YX
40DW6
44LW
Military/833C
(-55°C to 125°C)
44KW
Class B, Fully Compliant
ATV2500H/L
12
ATV2500H/L
Ordering Information (Continued)
tPD
tCO
fMAX
(ns)
(ns)
(MHz)
Ordering Code
Package
Operation Range
30
30
33
ATV2500L-30DC
ATV2500L-30JC
ATV2500L-30KC
ATV2500L-30LC
ATV2500L-30PC
40DW6
44J
Commercial
(0°C to 70°C)
44KW
44LW
40P6
ATV2500L-30DI
ATV2500L-30JI
ATV2500L-30KI
ATV2500L-30LI
ATV2500L-30PI
40DW6
44J
Industrial
(-40°C to 85°C)
44KW
44LW
40P6
ATV2500L-30DM
ATV2500L-30KM
ATV2500L-30LM
40DW6
44KW
44LW
Military
(-55°C to 125°C)
ATV2500L-30DM/883
ATV2500L-30KM/883
ATV2500L-30LM/883
40DW6
44KW
44LW
Military
(-55°C to 125°C)
Class B, Fully Compliant
35
35
28
ATV2500L-35DC
ATV2500L-35JC
ATV2500L-35KC
ATV2500L-35LC
ATV2500L-35PC
40DW6
44J
Commercial
(0°C to 70°C)
44KW
44LW
40P6
ATV2500L-35DI
ATV2500L-35JI
ATV2500L-35KI
ATV2500L-35LI
ATV2500L-35PI
40DW6
44J
Industrial
(-40°C to 85°C)
44KW
44LW
40P6
30
30
33
5962-91545 03M QA
5962-91545 03M XX
5962-91545 03M YX
40DW6
44LW
Military/833C
(-55°C to 125°C)
44KW
Class B, Fully Compliant
Package Type
40DW6
44J
40-Lead, 0.600" Wide Windowed, Ceramic Dual In-line Package (Cerdip)
44-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC)
44KW
44LW
40P6
44-Lead, Windowed, Ceramic J-Leaded Chip Carrier (JLCC)
44-Pad, Windowed, Ceramic Leadless Chip Carrier (LCC)
40-Lead, 0.600" Wide Plastic Dual In-line Package OTP (PDIP)
13
Packaging Information
40DW6, 40-Lead, 0.600" Wide Windowed, Ceramic
44J, 44-Lead, Plastic J-Leaded Chip Carrier OTP
(PLCC)
Dimensions in Inches and (Millimeters)
Dual In-line Package (Cerdip)
Dimensions in Inches and (Millimeters)
MIL-STD-1835 D-5 CONFIG A
.045(1.14) X 30° - 45°
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
.012(.305)
.008(.203)
.630(16.0)
.590(15.0)
.656(16.7)
.650(16.5)
SQ
.032(.813)
.026(.660)
.021(.533)
.013(.330)
.695(17.7)
.685(17.4)
SQ
.043(1.09)
.020(.508)
.120(3.05)
.050(1.27) TYP
.500(12.7) REF SQ
.090(2.29)
.180(4.57)
.165(4.19)
.022(.559) X 45° MAX (3X)
44KW, 44-Lead, Windowed, Ceramic J-Leaded Chip
44LW, 44-Pad, Windowed, Ceramic Leadless Chip
Carrier (JLCC)
Carrier (LCC)
Dimensions in Inches and (Millimeters)
MIL-STD-1835 C-J1
Dimensions in Inches and (Millimeters)
MIL-STD-1835 C-5
.035(.889) X 45°
.045(1.14) X 45°
.010(.254)
.006(.152)
.630(16.0)
.590(15.0)
.665(16.9)
.645(16.4)
SQ
.032(.813)
.026(.660)
.021(.533)
.017(.432)
.695(17.7)
.685(17.4)
SQ
.045(1.14)
.050(1.27) TYP
.500(12.7) REF SQ
.035(.889)
.120(3.05)
.090(2.29)
.180(4.57)
.156(3.96)
.025(.635) RADIUS MAX (3X)
ATV2500H/L
14
ATV2500H/L
Packaging Information
40P6, 40-Lead, 0.600" Wide Plastic Dual Inline
Package OTP (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 AC
2.07(52.6)
2.04(51.8)
PIN
1
.566(14.4)
.530(13.5)
.090(2.29)
MAX
1.900(48.26) REF
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.161(4.09)
.125(3.18)
.022(.559)
.014(.356)
.065(1.65)
.041(1.04)
.110(2.79)
.090(2.29)
.630(16.0)
.590(15.0)
0
15
REF
.012(.305)
.008(.203)
.690(17.5)
.610(15.5)
15
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