ATV750BL-15NC [ATMEL]
OT PLD, 15ns, CMOS, CQCC28, CERAMIC, LCC-28;
| 型号： | ATV750BL-15NC |
| 厂家： | 
ATMEL |
| 描述： | OT PLD, 15ns, CMOS, CQCC28, CERAMIC, LCC-28 可编程逻辑器件 输入元件 异步传输模式 ATM 时钟 |
| 文件： | 总16页 (文件大小：740K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Advanced, High-Speed Programmable Logic Device-Superset of 22V10
– Improved Performance - 7.5 ns tPD, 95 MHz External Operation
– Enhanced Logic Flexibility
– Backward Compatible with ATV750/L Software and Hardware
• New Flip-Flop Features
– D- or T-Type
– Product Term or Direct Input Pin Clocking
• High-Speed Erasable Programmable Logic Devices
– 7.5 ns Maximum Pin-to-Pin Delay
High-Speed
Device
ICC, Stand-By
125 mA
UV-Erasable
Programmable
Logic Device
ATV750B
ATV750BL
15 mA
• Highest Density Programmable Logic Available in a 24-Pin Package
• Increased Logic Flexibility
– 42 Array Inputs, 20 Sum Terms and 20 Flip-Flops
• Enhanced Output Logic Flexibility
– All 20 Flip-Flops Feed Back Internally
– 10 Flip-Flops are Also Available as Outputs
• Full Military, Commercial and Industrial Temperature Ranges
ATV750B
Logic Diagram
Description
The ATV750Bs are twice as powerful as most other 24-pin programmable logic
devices. Increased product terms, sum terms, flip-flops and output logic configurations
translate into more usable gates. High-speed logic and uniform, predictable delays
guarantee fast in-system performance.
(continued)
Pin Configurations
DIP/SOIC
PLCC/LCC
Pin Name Function
CLK
IN
Clock
Logic Inputs
I/O
*
Bidirectional Buffers
No Internal Connection
+5V Supply
VCC
Rev. 0301D–05/98
Top View
Each of the ATV750B’s 22 logic pins can be used as an
input. Ten of these can be used as inputs, outputs or bi-
directional I/O pins. Each flip-flop is individually config-
urable as either D- or T-type. Each flip-flop output is fed
back into the array independently. This allows burying of all
the sum terms and flip-flops.
Product terms provide individual clocks and asynchronous
resets for each flip-flop. Each flip-flop may also be individu-
ally configured to have direct input pin controlled clocking.
Each output has its own enable product term. One product
term provides a common synchronous preset for all flip-
flops. Register preload functions are provided to simplify
testing. All registers automatically reset upon power up.
There are 171 total product terms available. A variable for-
mat is used to assign between four to eight product terms
per sum term. There are two sum terms per output, provid-
ing added flexibility. Much more logic can be replaced by
this device than by any other 24-pin PLD. With 20 sum
terms and flip-flops, complex state machines are easily
implemented with logic to spare.
The ATV750BL is a low power device with speeds as fast
as 15 ns. The ATV750BL provides the optimum low power
PLD solution, with full CMOS output levels. This device sig-
nificantly reduces total system power, thereby allowing bat-
tery-powered operation.
Abosute Maximum Rating*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Temperature Under Bias................................ -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Note:
1. Minimum voltage is -0.6V DC which may under-
shoot to -2.0V for pulses of less than 20 ns.Maxi-
mum output pin voltage is VCC + 0.75V DC which
may overshoot to +7.0V for pulses of less than 20
ns.
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Integrated UV Erase Dose..............................7258 W•sec/cm2
Logic Options
Combinatorial Output
Registered Output
Combined Terms
Separate Terms
Combined Terms
Separate Terms
ATV750B
2
ATV750B
Clock MUX
CKMUX
CKi
TO
LOGIC
CELL
CLK
PIN
CLOCK
PRODUCT
TERM
SELECT
Output Options
DC and AC Operating Conditions(1)
Commercial
Commercial
-7, -10, -15
0°C - 70°C
5V ± 5%
-25
Industrial
-40°C - 85°C
5V ± 10%
Military
-55°C - 125°C
5V ± 10%
Operating Temperature (Case)
0°C - 70°C
5V ± 10%
V
CC Power Supply
Note:
1. See ordering information for valid speed and temperature combination.
3
DC Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
ILI
Input Load Current VIN = -0.1V to VCC + 1V
10
µA
Output Leakage
VOUT = -0.1V to VCC + 0.1V
Current
ILO
10
µA
Com.
125
125
125
125
15
180
190
180
190
30
mA
mA
mA
mA
mA
mA
B-7, -10
Ind.,Mil.
Com.
V
V
CC = MAX,
IN = MAX,
Power Supply
Current, Standby
ICC
B-15, -25
BL-15
Ind.,Mil.
Com.
Outputs Open
Ind.,Mil.
15
30
Output Short
Circuit Current
(1)
IOS
VIL
VOUT = 0.5V
-120
mA
Input Low Voltage
Input High Voltage
4.5 ≤ VCC ≤ 5.5V
-0.6
2.0
0.8
VCC + 0.75
0.5
V
V
V
V
V
V
V
VIH
IOL = 16 mA
Com.,Ind.
Mil.
Output Low
Voltage
VIN = VIH or VIL,
VOL
I
OL = 12 mA
0.5
VCC = MIN
IOL = 24 mA
Com.
0.8
IOH = -100 µA
VCC - 0.3
2.4
Output High
Voltage
VIN = VIH or VIL,
VCC = MIN
VOH
I
OH = -4.0 mA
Notes: 1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec.
Input Test Waveforms and
Measurement Levels
Output Test Load
tR, tF < 3 ns (10% to 90%)
ATV750B
4
ATV750B
AC Waveforms, Product Term Clock(1)
Note:
1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics, Product Term Clock(1)
-7
-10
B/BL-15
B/BL-25
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Units
Input or Feedback to
Non-Registered Output
tPD
7.5
10
15
25
ns
tEA
tER
tCO
tCF
tS
Input to Output Enable
Input to Output Disable
Clock to Output
7.5
7.5
7.5
5
10
10
10
7.5
15
15
12
9
25
25
20
10
ns
ns
3
1
4
4
5
5
6
5
ns
Clock to Feedback
Input Setup Time
Feedback Setup Time
Hold Time
ns
3
4
8/12
7
14
7
ns
tSF
tH
3
4
ns
1
2
5/7
14
7
5/7
17
8.5
ns
tP
Clock Period
7
11
5.5
ns
tW
Clock Width
3.5
ns
External Feedback 1/(tS+tCO
)
95
71
86
90
50/41
62
29
58
58
MHz
MHz
MHz
ns
FMAX
Internal Feedback 1/(tSF+tCF
No Feedback 1/(tP)
)
125
142
71
tAW
tAR
tAP
Asynchronous Reset Width
5
3
10
10
15
15
20
20
Asynchronous Reset
Recovery Time
ns
Asynchronous Reset to
Registered Output Reset
8
12
15
25
ns
ns
tSP
Note:
Setup Time, Synchronous Preset
4
7
8
15
1. See ordering information for valid part numbers.
5
AC Waveforms, Input Pin Clock(1)
Notes: 1. Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics, Input Pin Clock
B/BL
-15
B/BL
-25
-7
-10
Symbol
Parameter
Min
Max
Min
Max
Min
Max
Min
Max
Units
Input or Feedback to
Non-Registered Output
tPD
7.5
10
15
25
ns
tEA
Input to Output Enable
Input to Output Disable
Clock to Output
7.5
7.5
6.5
3.5
10
10
7
15
15
25
25
12
7
ns
ns
tER
tCOS
tCFS
tSS
0
0
0
0
0
0
6.5
5.5
0
0
ns
Clock to Feedback
Input Setup Time
Feedback Setup Time
Hold Time
5
ns
4
5
8/12.5
9/15
9
ns
tSFS
tHS
4
5
7
0
ns
0
0
0
ns
tPS
Clock Period
7
10
5
12
6
16
8
ns
tWS
Clock Width
3.5
ns
External Feedback 1/(tSS+tCOS
)
95
83
69/52
80
48/37
62
MHz
MHz
MHz
ns
FMAXS
Internal Feedback 1/(tSFS+tCFS
No Feedback 1/(tPS
)
133
142
100
100
)
83
62
tAW
Asynchronous Reset Width
5
10
15
20
5
10
15
25
ns
Asynchronous Reset
Recovery Time
tARS
8
10
15
25
ns
ns
Asynchronous Reset to
Registered Output Reset
tAP
5
5/9
11
15
Setup Time, Synchronous
Preset
tSPS
ATV750B
6
ATV750B
Functional Logic Diagram ATV750B, Upper Half
7
Functional Logic Diagram ATV750B, Lower Half
ATV750B
8
ATV750B
Preload of Registered Outputs
The ATV750B’s registers are provided with circuitry to
allow loading of each register asynchronously with either a
high or a low. This feature will simplify testing since any
state can be forced into the registers to control test
sequencing. A VIH level on the I/O pin will force the register
high; a VIL will force it low, independent of the output polar-
ity. The PRELOAD state is entered by placing a 10.25V to
10.75V signal on pin 8 on DIPs, and lead 10 on SMDs.
When the clock term is pulsed high, the data on the I/O
pins is placed into the register chosen by the Select Pin.
Level forced on registered
output pin during PRELOAD cycle
Select Pin State
Register #0 State after cycle
Register #1 State after cycle
VIH
VIL
VIH
VIL
Low
Low
High
High
High
Low
X
X
X
High
Low
X
Power Up Reset
The registers in the ATV750Bs are designed to reset during
power up. At a point delayed slightly from VCC crossing
VRST, all registers will be reset to the low state. The output
state will depend on the polarity of the output buffer.
This feature is critical for state machine initialization. How-
ever, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the fol-
lowing conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock terms or
pin high, and
Parameter Description
Typ
600 1000
3.8 4.5
Max
Units
ns
tPR
Power-Up Reset Time
3. The clock pin, or signals from which clock terms are
derived, must remain stable during tPR.
VRST
Power-Up Reset Voltage
V
Pin Capacitance
f = 1 MHz, T = 25°C(1)
Typ
5
Max
8
Units
pF
Conditions
VIN = 0V
CIN
COUT
6
8
pF
VOUT = 0V
9
Using the ATV750B’s Many Advanced
Features
The ATV750B’s advanced flexibility packs more usable
gates into 24-pins than any other logic device. The
ATV750Bs start with the popular 22V10 architecture, and
add several enhanced features:
Synchronous Preset and
Asynchronous Reset
One synchronous preset line is provided for all 20 registers
in the ATV750B. The appropriate input signals to cause the
internal clocks to go to a high state must be received during
a synchronous preset. Appropriate setup and hold times
must be met, as shown in the switching waveform diagram.
• Selectable D- and T-Type Registers -
Each ATV750B flip-flop can be individually configured as
either D- or T-type. Using the T-type configuration, JK
and SR flip-flops are also easily created. These options
allow more efficient product term usage.
An individual asynchronous reset line is provided for each
of the 20 flip-flops. Both master and slave halves of the flip-
flops are reset when the input signals received force the
internal resets high.
• Selectable Asynchronous Clocks -
Each of the ATV750B’s flip-flops may be clocked by its
own clock product term or directly from Pin 1 (SMD Lead
2). This removes the constraint that all registers must
use the same clock. Buried state machines, counters
and registers can all coexist in one device while running
on separate clocks. Individual flip-flop clock source
selection further allows mixing higher performance pin
clocking and flexible product term clocking within one
design.
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATV750B fuse patterns. Once the security fuse is
programmed, all fuses will appear programmed during ver-
ify.
The security fuse should be programmed last, as its effect
is immediate.
Erasure Characteristics
• A Full Bank of Ten More Registers -
The ATV750B provides two flip-flops per output logic cell
for a total of 20. Each register has its own sum term, its
own reset term and its own clock term.
The entire memory array of an ATV750B is erased after
exposure to ultraviolet light at a wavelength of 2537 Å.
Complete erasure is assured after a minimum of 20 min-
utes exposure using 12,000 µW/cm2 intensity lamps
spaced one inch away from the chip. Minimum erase time
for lamps at other intensity ratings can be calculated from
the minimum integrated erasure dose of 15 W•sec/cm2. To
prevent unintentional erasure, an opaque label is recom-
mended to cover the clear window on any UV erasable
PLD which will be subjected to continuous fluorescent
indoor lighting or sunlight.
• Independent I/O Pin and Feedback Paths -
Each I/O pin on the ATV750B has a dedicated input path.
Each of the 20 registers has its own feedback terms into
the array as well. This feature, combined with individual
product terms for each I/O’s output enable, facilitates
true bi-directional I/O design.
Programming Software Support
As with all other Atmel PLDs, several third party develop-
ment software products support the ATV750Bs. Several
third party programmers support the ATV750B as well.
Additionally, the ATV750B may be programmed to perform
the ATV750/L’s functional subset (no T-type flip-flops or pin
clocking) using the ATV750/L JEDEC file. In this case, the
ATV750B becomes a direct replacement or speed upgrade
for the ATV750/L. The ATV750/L programming algorithm is
different from the ATV750B algorithm. Choose the appro-
priate device in your programmer menu to ensure proper
programming. Please refer to the Programmable Logic
Development Tools section for a complete PLD software
and programmer listing.
Atmel CMOS PLDs
The ATV750B utilizes an advanced 0.65-micron CMOS
EPROM technology. This technology’s state of the art fea-
tures are the optimum combination for PLDs:
• CMOS technology provides high speed, low power, and
high noise immunity.
• EPROM technology is the most cost effective method for
producing PLDs - surpassing bipolar fusible link
technology in low cost, while providing the necessary
reprogrammability.
• EPROM reprogrammability, which is 100% tested before
shipment, provides inherently better programmability and
reliability than one-time fusible PLDs.
ATV750B
10
ATV750B
11
ATV750B
12
ATV750B
Ordering Information
Ext.
tPD
(ns)
tCOS
(ns)
fMAXS
(MHz)
Ordering Code
Package
Operation Range
7.5
10
6.5
95
83
ATV750B-7JC
ATV750B-7PC
28J
Commercial
24P3
(0°C to 70°C)
7
ATV750B-10JC
ATV750B-10PC
ATV750B-10SC
28J
Commercial
24P3
24S
(0°C to 70°C)
ATV750B-10JI
ATV750B-10PI
ATV750B-10SI
28J
Industrial
24P3
24S
(-40°C to 85°C)
ATV750B-10DM/883
ATV750B-10LM/883
24DW3
28LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
15
10
58
ATV750B-15JC
ATV750B-15PC
ATV750B-15SC
28J
Commercial
24P3
24S
(0°C to 70°C)
ATV750B-15JI
ATV750B-15PI
ATV750B-15SI
28J
Industrial
24P3
24S
(-40°C to 85°C)
ATV750B-15DM/883
ATV750B-15LM/883
24DW3
28LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
25
15
41
ATV750B-25JC
ATV750B-25PC
ATV750B-25SC
28J
Commercial
24P3
24S
(0°C to 70°C)
ATV750B-25JI
ATV750B-25PI
ATV750B-25SI
28J
Industrial
24P3
24S
(-40°C to 85°C)
10
15
7
9
83
58
5962-88726 08 LA
5962-88726 08 3X
24DW3
28LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
5962-88726 09 LA
5962-88726 09 3X
24DW3
28LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
13
Ordering Information
Ext.
tPD
(ns)
tCOS
(ns)
fMAXS
(MHz)
Ordering Code
Package
Operation Range
15
9
92
ATV750BL-15JC
ATV750BL-15PC
ATV750BL-15SC
28J
Commercial
24P3
24S
(0°C to 70°C)
ATV750BL-15JI
ATV750BL-15PI
ATV750BL-15SI
28J
Industrial
24P3
24S
(-40°C to 85°C)
ATV750BL-15DM/883
ATV750BL-15LM/883
24DW3
28LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
25
15
15
37
92
ATV750BL-25JC
ATV750BL-25PC
ATV750BL-25SC
28J
Commercial
24P3
24S
(0°C to 70°C)
ATV750BL-25JI
ATV750BL-25PI
ATV750BL-25SI
28J
Industrial
24P3
24S
(-40°C to 85°C)
9
5962-88726 11 LX
5962-88726 11 3X
24DW3
28LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
Package Type
24DW3
28J
24-Lead, 0.300" Wide, Windowed, Ceramic Dual Inline Package (Cerdip)
28-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC)
28LW
24P3
24S
28-Pad, Windowed, Ceramic Leadless Chip Carrier (LCC)
24-Lead, 0.300" Wide, Plastic Dual Inline Package OTP (PDIP)
24-Lead, 0.300" Wide, Plastic Gull Wing Small Outline OTP (SOIC)
ATV750B
14
ATV750B
Packaging Information
24DW3, 24-Lead, 0.300" Wide, WIndowed, Ceramic
28J, 28-Lead, Plastic J-Leaded Chip Carrier (PLCC)
Dual Inline Package (Cerdip)
Dimensions in Inches and (Millimeters)
MIL-STD-1835 D-9 CONFIG A
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-018 AB
.045(1.14) X 30° - 45°
.045(1.14) X 45° PIN NO. 1
IDENTIFY
.012(.305)
.008(.203)
.430(10.9)
.390(9.91)
.021(.533)
.013(.330)
SQ
.456(11.6)
.450(11.4)
SQ
.032(.813)
.026(.660)
.495(12.6)
.485(12.3)
SQ
.050(1.27) TYP
.043(1.09)
.300(7.62) REF SQ
.020(.508)
.120(3.05)
.090(2.29)
.180(4.57)
.165(4.19)
.022(.559) X 45° MAX (3X)
28LW, 28-Pad, Windowed, Ceramic Leadless Chip
24P3, 24-Lead, 0.300" Wide, Plastic Dual Inline
Carrier (LCC)
Package (PDIP)
Dimensions in Inches and (Millimeters)*
MIL-STD-1835 C-4
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 AF
1.27(32.3)
1.25(31.7)
PIN
1
.266(6.76)
.250(6.35)
.090(2.29)
MAX
1.100(27.94) REF
.200(5.06)
MAX
.005(.127)
MIN
SEATING
PLANE
.070(1.78)
.020(.508)
.023(.584)
.014(.356)
.151(3.84)
.125(3.18)
.065(1.65)
.040(1.02)
.110(2.79)
.090(2.29)
.325(8.26)
.300(7.62)
0
15
REF
.012(.305)
.008(.203)
.400(10.2) MAX
*Controlling dimension: millimeters
15
Packaging Information
24S, 24-Lead, 0.300" Wide, Plastic Gull Wing Small
Outline (SOIC)
Dimensions in Inches and (Millimeters)
.020(.508)
.013(.330)
.299(7.60) .420(10.7)
.291(7.39) .393(9.98)
PIN 1 ID
.050(1.27) BSC
.616(15.6)
.105(2.67)
.598(15.2)
.092(2.34)
.012(.305)
.003(.076)
.013(.330)
.009(.229)
.050(1.27)
0
REF
.015(.381)
8
© Atmel Corporation 1998.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the
Company’s standard warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s
website. The Company assumes no responsibility for any errors which may appear in this document, reserves
the right to change devices or specifications detailed herein at any time without notice, and does not make any
commitment to update the information contained herein. No licenses to patents or other intellectual property of
Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not
authorized for use as critical components in life support devices or systems.
Atmel Headquarters, 2325 Orchard Parkway, San Jose, CA 95131, TEL (408) 441-0311, FAX (408) 487-2600
Atmel Colorado Springs, 1150 E. Cheyenne Mtn. Blvd., Colorado Springs, CO 80906, TEL (719) 576-3300, FAX (719) 540-1759
Atmel Rousset, Zone Industrielle, 13106 Rousset Cedex, France, TEL (33) 4 42 53 60 00, FAX (33) 4 42 53 60 01
®
™
Marks bearing and/or are registered trademarks and trademarks of Atmel Corporation.
Printed on recycled paper.
0301D–05/98/xM
Terms and product names in this document may be trademarks of others.
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