ATXMEGA128A4U-AU [ATMEL]
8/16-bit Atmel XMEGA A4U Microcontroller; 8位/ 16位爱特梅尔XMEGA微控制器A4U型号: | ATXMEGA128A4U-AU |
厂家: | ATMEL |
描述: | 8/16-bit Atmel XMEGA A4U Microcontroller |
文件: | 总121页 (文件大小:4723K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• High-performance, Low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller
• Non-volatile Program and Data Memories
– 16K - 128KBytes of In-System Self-Programmable Flash
– 4K - 8KBytes Boot Code Section with Independent Lock Bits
– 1K - 2KBytes EEPROM
– 2K - 8KBytes Internal SRAM
• Peripheral Features
– Four-channel DMA Controller
– Eight-channel Event System
– Five 16-bit Timer/Counters
8/16-bit Atmel
XMEGA A4U
Microcontroller
Three Timer/Counters with 4 Output Compare or Input Capture channels
Two Timer/Counters with 2 Output Compare or Input Capture channels
High-Resolution Extensions on all Timer/Counters
Advanced Waveform Extension on one Timer/Counter
– One USB device Interface
USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
32 Endpoints with full configuration flexibility
– Five USARTs with IrDA support for one USART
– Two Two-Wire Interfaces with dual address match (I2C and SMBus compatible)
– Two Serial Peripheral Interfaces (SPIs)
– AES and DES Crypto Engine
– CRC-16 (CRC-CCITT) and CRC-32 (IEEE 802.3) Generator
– 16-bit Real Time Counter with Separate Oscillator
– One Twelve-channel, 12-bit, 2MSPS Analog to Digital Converter
– One Two-channel, 12-bit, 1MSPS Digital to Analog Converter
– Two Analog Comparators with Window compare function, and current source feature
– External Interrupts on all General Purpose I/O pins
– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
– QTouch® library support
ATxmega128A4U
ATxmega64A4U
ATxmega32A4U
ATxmega16A4U
Capacitive touch buttons, sliders and wheels
Up to 64 sense channels
• Special Microcontroller Features
Preliminary
– Power-on Reset and Programmable Brown-out Detection
– Internal and External Clock Options with PLL and Prescaler
– Programmable Multi-level Interrupt Controller
– Five Sleep Modes
– Programming and Debug Interfaces
PDI (Program and Debug Interface)
• I/O and Packages
– 34 Programmable I/O Pins
– 44 - lead TQFP
– 44 - pad VQFN/QFN
– 49 - ball VFBGA
• Operating Voltage
– 1.6 – 3.6V
• Operating Frequency
– 0 – 12MHz from 1.6V
– 0 – 32MHz from 2.7V
Typical Applications
• Industrial control
• Factory automation
• Building control
• Board control
• Climate control
• RF and ZigBee
• USB Connectivity
• Sensor control
• Optical
• Low power battery applications
• Power tools
• HVAC
• Utility Metering
• Medical Applications
• White Goods
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XMEGA A4U
1. Ordering Information
Ordering Code
Flash (Bytes) EEPROM (Bytes) SRAM (Bytes) Speed (MHz) Power Supply Package(1)(2)(3)
Temp
ATxmega128A4U-AU
ATxmega64A4U-AU
ATxmega32A4U-AU
ATxmega16A4U-AU
ATxmega128A4U-MH
ATxmega64A4U-MH
ATxmega32A4U-MH
ATxmega16A4U-MH
ATxmega128A4U-CU
ATxmega64A4U-CU
ATxmega32A4U-CU
ATxmega16A4U-CU
128K + 8K
64K + 4K
32K + 4K
16K + 4K
128K + 8K
64K + 4K
32K + 4K
16K + 4K
128K + 8K
64K + 4K
32K + 4K
16K + 4K
2K
2K
1K
1K
2K
2K
1K
1K
2K
2K
1K
1K
8K
4K
4K
2K
8K
4K
4K
2K
8K
4K
4K
2K
44A
44M1
49C2
32
1.6 - 3.6V
-40°C - 85°C
Notes: 1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also
Halide free and fully Green.
3. For packaging information see ”Packaging information” on page 61.
Package Type
44A
44-Lead, 10 x 10mm Body Size, 1.0mm Body Thickness, 0.8mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
44-Pad, 7x7x1mm Body, Lead Pitch 0.50mm, 5.20mm Exposed Pad, Thermally Enhanced Plastic Very Thin Quad No Lead Package (VQFN)
49-Ball (7 x 7 Array), 0.65mm Pitch, 5.0 x 5.0 x 1.0mm, Very Thin, Fine-Pitch Ball Grid Array Package (VFBGA)
44M1
49C2
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2. Pinout/Block Diagram
Figure 2-1. Block Diagram and QFN/TQFP pinout
Power / Ground
Programming, debug, test
Digital function
Analog function
External clock / Crystal pins
General Purpose I/O
Port R
PA5
PA6
PA7
PB0
PB1
PB2
PB3
GND
VCC
PC0
PC1
1
2
33
32
31
30
29
28
27
26
25
24
23
PE3
DATA BUS
OSC/CLK
Control
Crypto /
Power
PE2
VCC
GND
PE1
PE0
PD7
PD6
PD5
PD4
PD3
Watchdog
CRC
Supervision
AREF
ADC
Real Time
Counter
Watchdog
Timer
Reset
Controller
Sleep
Controller
3
AC0:1
4
Event System
Controller
Interrupt
Controller
Prog/Debug
Interface
OCD
5
BUS
matrix
TEMPREF
VREF
AREF
DAC
6
DMA
Controller
CPU
7
FLASH
EEPROM
SRAM
8
DATA BUS
9
EVENT ROUTING NETWORK
10
11
Port C
Port D
Port E
Note:
For full details on pinout and pin functions refer to ”Pinout and Pin Functions” on page 51.
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Figure 2-2. BGA pinout
Top view
Bottom view
1
2
3
4
5
6
7
7
6
5
4
3
2
1
A
B
C
D
E
F
A
B
C
D
E
F
G
G
Table 2-1.
A
BGA pinout
1
2
3
4
5
6
PA3
AVCC
GND
PR1
PR0
PDI_DATA
PE3
RESET/
PA4
PA1
PA0
GND
PE2
VCC
B
C
D
E
F
PDI_CLK
PA5
PB1
GND
VCC
PC1
PA2
PB2
GND
PC0
PC2
PA6
PB3
PC3
PC4
PC5
PA7
PB0
GND
PC6
PC7
GND
GND
PD4
PD0
GND
PE1
PD7
PD5
PD1
VCC
GND
PE0
PD6
PD3
PD2
G
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3. Overview
The Atmel® AVR® XMEGA® is a family of low power, high performance and peripheral rich 8/16-
bit microcontrollers based on the AVR® enhanced RISC architecture. By executing instructions
in a single clock cycle, AVR achieves throughputs CPU approaching 1Million Instructions Per
Second (MIPS) per MHz allowing the system designer to optimize power consumption versus
processing speed.
Atmel AVR CPU combines a rich instruction set with 32 general purpose working registers. All
the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two indepen-
dent registers to be accessed in one single instruction, executed in one clock cycle. The
resulting architecture is more code efficient while achieving throughputs many times faster than
conventional single-accumulator or CISC based microcontrollers.
The XMEGA A4U devices provide the following features: In-System Programmable Flash with
Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel DMA Controller,
eight-channel Event System, Programmable Multi-level Interrupt Controller, 34 general purpose
I/Opins, 16-bit Real Time Counter, five flexible 16-bit Timer/Counters with compare and PWM
channels, one USB 2.0 full speed (12Mbps) Device Interface, five USARTs, two Two Wire Serial
Interfaces (TWIs), two Serial Peripheral Interfaces (SPIs), AES and DES crypto engine, one
Twelve-channel, 12-bit ADC with optional differential input with programmable gain, one Two-
channel 12-bit DAC, two analog comparators with window mode, programmable Watchdog
Timer with separate Internal Oscillator, accurate internal oscillators with PLL and prescaler and
programmable Brown-Out Detection.
The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,
is available.
All XMEGA devices have five software selectable power saving modes. The Idle mode stops the
CPU while allowing the SRAM, DMA Controller, Event System, Interrupt Controller and all
peripherals to continue functioning. The Power-down mode saves the SRAM and register con-
tents but stops the oscillators, disabling all other functions until the next TWI or pin-change
interrupt, or Reset. In Power-save mode, the asynchronous Real Time Counter continues to run,
allowing the application to maintain a timer base while the rest of the device is sleeping. In
Standby mode, the Crystal/Resonator Oscillator is kept running while the rest of the device is
sleeping. This allows very fast start-up from external crystal combined with low power consump-
tion. In Extended Standby mode, both the main Oscillator and the Asynchronous Timer continue
to run. To further reduce power consumption, the peripheral clock to each individual peripheral
can optionally be stopped in Active mode and Idle sleep mode.
Atmel offers the QTouch® library for embedding capacitive touch buttons, sliders and wheels
functionality into AVR microcontrollers.
The device is manufactured using Atmel's high-density nonvolatile memory technology. The pro-
gram Flash memory can be reprogrammed in-system through the PDI. A Bootloader running in
the device can use any interface to download the application program to the Flash memory. The
Bootloader software in the Boot Flash section will continue to run while the Application Flash
section is updated, providing true Read-While-Write operation. By combining an 8/16-bit RISC
CPU with In-System Self-Programmable Flash, the Atmel XMEGA A4U is a powerful microcon-
troller family that provides a highly flexible and cost effective solution for embedded applications.
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The Atmel® AVR® XMEGA® devices are supported with a full suite of program and system
development tools including: C compilers, macro assemblers, program debugger/simulators,
programmers, and evaluation kits.
3.1
Block Diagram
Figure 3-1. XMEGA A4U Block Diagram
PR[0..1]
XTAL1/
TOSC1
Digital function
Analog function
Programming, debug, test
Oscillator/Crystal/Clock
General Purpose I/O
XTAL2/
TOSC2
Oscillator
Circuits/
Clock
Real Time
Counter
Watchdog
Oscillator
PORT R (2)
Generation
DATA BUS
SRAM
Watchdog
Timer
PA[0..7]
PORT A (8)
Event System
Controller
Oscillator
Control
VCC
GND
Power
Supervision
POR/BOD &
RESET
ACA
DMA
Controller
Sleep
Controller
ADCA
RESET/
AREFA
Int. Refs.
Tempref
AREFB
Prog/Debug
Controller
PDI_CLK
BUS Matrix
PDI
PDI_DATA
AES
DES
CRC
OCD
Interrupt
Controller
CPU
PB[0..7]
PORT B (8)
DACB
NVM Controller
Flash
EEPROM
IRCOM
DATA BUS
EVENT ROUTING NETWORK
PORT C (8)
PORT D (8)
PORT E (4)
TOSC1 (optional)
TOSC2
(optional)
PC[0..7]
PD[0..7]
PE[0..3]
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XMEGA A4U
4. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
4.1
Recommended reading
• XMEGA® AU Manual
• XMEGA Application Notes
This device data sheet only contains part specific information with a short description of each
peripheral and module. The XMEGA AU Manual describes the modules and peripherals in
depth. The XMEGA application notes contain example code and show applied use of the mod-
ules and peripherals.
All documentations are available from www.atmel.com/avr.
5. Capacitive touch sensing
The Atmel® QTouch® Library provides a simple to use solution to realize touch sensitive inter-
faces on most Atmel AVR® microcontrollers. The patented charge-transfer signal acquisition
offers robust sensing and includes fully debounced reporting of touch keys and includes Adja-
cent Key Suppression® (AKS™) technology for unambiguous detection of key events. The
QTouch Library includes support for the QTouch and QMatrix® acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch Library
for the AVR Microcontroller. This is done by using a simple set of APIs to define the touch chan-
nels and sensors, and then calling the touch sensing API’s to retrieve the channel information
and determine the touch sensor states.
The QTouch Library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the
Atmel QTouch Library User Guide - also available for download from the Atmel website.
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6. AVR CPU
6.1
Features
• 8/16-bit high performance AVR RISC Architecture
– 142 instructions
– Hardware multiplier
•32x8-bit registers directly connected to the ALU
• Stack in SRAM
• Stack Pointer accessible in I/O memory space
• Direct addressing of up to 16Mbytes of program and 16Mbytes of data memory
• True 16/24-bit access to 16/24-bit I/O registers
• Support for 8-, 16- and 32-bit Arithmetic
• Configuration Change Protection of system critical features
6.2
Overview
The Atmel® AVR® XMEGA® devices use the 8/16-bit AVR CPU. The main function of the CPU is
to execute the code and perform all calculations. The CPU is able to access memories, perform
calculations, control peripherals, and execute the program from the FLASH memory. Interrupt
handling is described in a separate section, refer to ”Interrupts and Programmable Multi-level
Interrupt Controller” on page 26.
Figure 6-1 on page 8 shows the CPU block diagram of the AVR CPU architecture.
Figure 6-1. Block Diagram of the AVR CPU architecture
In order to maximize performance and parallelism, the AVR uses a Harvard architecture with
separate memories and buses for program and data. Instructions in the program memory are
executed with a single level pipelining. While one instruction is being executed, the next instruc-
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XMEGA A4U
tion is pre-fetched from the Program Memory. This enables instructions to be executed in every
clock cycle.
The program memory is In-System Self-Programmable Flash memory.
6.3
ALU - Arithmetic Logic Unit
The Arithmetic Logic Unit (ALU) supports arithmetic and logic operations between registers or
between a constant and a register. Single register operations can also be executed. The ALU
operates in direct connection with all the 32 general purpose registers. In a single clock cycle,
arithmetic operations between general purpose registers or between a register and an immedi-
ate are executed and the result is stored back in the Register File. After an arithmetic or logic
operation, the Status Register is updated to reflect information about the result of the operation.
The ALU operations are divided into three main categories – arithmetic, logical, and bit-func-
tions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for efficient
implementation of 32-bit arithmetic. The hardware multiplier supports signed and unsigned mul-
tiplication and fractional format.
6.4
Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the Flash Program
Memory ‘0’. The Program Counter (PC) addresses the next instruction to be fetched. After a
reset, the PC is set to location ‘0’.
Program flow is provided by conditional and unconditional jump and call instructions, capable of
addressing the whole address space directly. Most AVR instructions use a 16-bit word format,
while a limited number uses a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack
is allocated in the general data SRAM, and consequently the Stack size is only limited by the
total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to the
highest address in the internal SRAM. The SP is read/write accessible in the I/O memory space,
enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
6.5
Register File
The Register File consists of 32 x 8-bit general purpose working registers with single clock cycle
access time. The Register File supports the following input/output schemes:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit address register pointers for data space
addressing - enabling efficient address calculations. One of these address pointers can also be
used as an address pointer for look up tables in Flash program memory.
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XMEGA A4U
7. Memories
7.1
Features
• Flash Program Memory
– One linear address space
– In-System Programmable
– Self-Programming and Bootloader support
– Application Section for application code
– Application Table Section for application code or data storage
– Boot Section for application code or bootloader code
– Separate read/write protection lock bits for all sections
– CRC Generator support for CRC check of a selectable flash program memory section
• Data Memory
– One linear address space
– Single cycle access from CPU
– SRAM
– EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
– I/O Memory
Configuration and Status registers for all peripherals and modules
16bit-accessible General Purpose Register for global variables or flags
– Bus arbitration
Safe and deterministic handling of priority between CPU, DMA Controller, and other bus
masters
– Separate buses for SRAM, EEPROM, and I/O Memory
Simultaneous bus access for CPU and DMA Controller
• Production Signature Row Memory for factory programmed data
– ID for each microcontroller device type
– Serial number for each device
– Calibration bytes for factory calibrated peripherals
• User Signature Row
– One flash page in size
– Can be read and written from software
– Content is kept after chip erase
7.2
Overview
The Atmel® AVR® architecture has two main memory spaces, the Program Memory and the
Data Memory. Executable code can only reside in the Program Memory, while data can be
stored both in the Program Memory and the Data Memory. The Data Memory includes both
SRAM, and EEPROM Memory for nonvolatile data storage. All memory spaces are linear and
require no memory bank switching.
The available memory size configurations are shown in ”Ordering Information” on page 2. In
addition each device has a Flash memory signature row for calibration data, device identifica-
tion, serial number etc.
Non Volatile Memory (NVM) spaces can be locked for further write and read/write operations.
This prevents unrestricted access to the application software.
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7.3
Flash Program Memory
The Atmel® AVR® XMEGA® devices contain On-chip In-System Reprogrammable Flash mem-
ory for program storage. The Flash memory can be accessed for read and write both from an
external programmer through the PDI, or from application software running in the device.
All AVR instructions are 16- or 32-bit wide, each Flash address location is 16-bit.
The Flash memory is organized in two main sections, the Application Section and the Boot
Loader section. The size of the different sections are fixed, but device dependent. These two
sections have separate lock bits and can have different levels of protection. The Store Program
Memory (SPM) instruction, used to write to the Flash from the application software, will only
operate when executed from the Boot Loader Section.
The Application Section contains an Application Table Section with separate lock settings. This
enables safe storage of Non-volatile data in the Program Memory.
Figure 7-1. Flash Program Memory (Hexadecimal address)
Word Address
0
Application Section (Bytes)
(128K/64K/32K/16K)
...
EFFF
F000
/
/
/
/
/
77FF
7800
7FFF
8000
87FF
/
/
/
/
/
37FF
3800
3FFF
4000
47FF
/
/
/
/
/
17FF
1800
1FFF
2000
27FF
Application Table Section (Bytes)
(4K/4K/4K/4K)
FFFF
10000
10FFF
Boot Section (Bytes)
(8K/4K/4K/4K)
The Application Table Section and Boot Section can also be used for general application
software.
7.4
Data Memory
The Data memory contains the I/O Memory, internal SRAM, optionally memory mapped
EEPROM, and external memory if available. The data memory is organized as one continuous
memory section, see Figure 7-2 on page 12. To simplify development, I/O Memory, EEPROM
and SRAM will always have the same start addresses for all XMEGA devices.
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XMEGA A4U
Figure 7-2. Data Memory Map (Hexadecimal address)
Byte Address
ATxmega64A4U
Byte Address
ATxmega32A4U
Byte Address
ATxmega16A4U
0
0
0
FFF
I/O Registers
(4 KB)
I/O Registers
(4 KB)
I/O Registers
(4 KB)
FFF
1000
17FF
FFF
1000
13FF
1000
13FF
EEPROM
(2K)
EEPROM
(1K)
EEPROM
(1K)
RESERVED
RESERVED
RESERVED
2000
2FFF
2000
2FFF
2000
27FF
Internal SRAM
(4K)
Internal SRAM
(4K)
Internal SRAM
(2K)
Byte Address
ATxmega128A4U
0
FFF
I/O Registers
(4 KB)
1000
17FF
EEPROM
(2K)
RESERVED
2000
3FFF
Internal SRAM
(8K)
7.4.1
I/O Memory
The Status and configuration registers for peripherals and modules, including the CPU, are
addressable through I/O memory locations. All I/O locations can be accessed by the load
(LD/LDS/LDD) and store (ST/STS/STD) instructions, which is used to transfer data between the
32 registers in the Register File and the I/O memory. The IN and OUT instructions can address
I/O memory locations in the range 0x00 - 0x3F directly. In the address range 0x00 - 0x1F, sin-
gle- cycle instructions for manipulation and checking of individual bits are available.
The I/O memory address for all peripherals and modules in XMEGA A4U is shown in the
”Peripheral Module Address Map” on page 56.
7.4.2
7.4.3
SRAM Data Memory
The devices have internal SRAM memory for data storage.
EEPROM Data Memory
The devices have internal EEPROM memory for non-volatile data storage. It is addressable
either in a separate data space or it can be memory mapped into the normal data memory
space. The EEPROM memory supports both byte and page access.
7.5
Production Signature Row
The Production Signature Row is a separate memory section for factory programmed data. It
contains calibration data for functions such as oscillators and analog modules.
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XMEGA A4U
The production signature row also contains an ID that identifies each microcontroller device
type, and a serial number that is unique for each manufactured device. The device ID for the
devices is shown in Table 7-1 on page 13. The serial number consists of the production LOT
number, wafer number, and wafer coordinates for the device.
The production signature row can not be written or erased, but it can be read from both applica-
tion software and external programming.
Table 7-1.
Device ID bytes for XMEGA A4U devices.
Device
Device ID bytes
Byte 2
Byte 1
94
Byte 0
1E
ATxmega16A4U
ATxmega32A4U
ATxmega64A4U
ATxmega128A4U
41
41
46
46
95
1E
96
1E
97
1E
7.6
User Signature Row
The User Signature Row is a separate memory section that is fully accessible (read and write)
from application software and external programming. It is one flash page in size, and is meant
for static user parameter storage, such as calibration data, custom serial numbers or identifica-
tion numbers, random number seeds etc. This section is not erased by Chip Erase commands
that erase the Flash, and requires a dedicated erase command. This ensures parameter storage
during multiple program/erase session and on-chip debug sessions.
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7.7
Flash and EEPROM Page Size
The Flash Program Memory and EEPROM data memory are organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 14 shows the Flash Program Memory organization. Flash write and erase
operations are performed on one page at a time, while reading the Flash is done one byte at a
time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant bits in
the address (FPAGE) give the page number and the least significant address bits (FWORD)
give the word in the page.
Table 7-2.
Number of words and Pages in the Flash.
Devices
Flash
Size
Page Size
FWORD
FPAGE
Application
Boot
No of Pages
(words)
128
Size
No of Pages
Size
4K
ATxmega16A4U
ATxmega32A4U
ATxmega64A4U
ATxmega128A4U
16K + 4K
32K + 4K
64K + 4K
128K + 8K
Z[6:0]
Z[6:0]
Z[6:0]
Z[8:0]
Z[13:7]
Z[14:7]
Z[15:7]
Z[16:7]
16K
32K
64
16
16
16
32
128
128
256
512
4K
128
64K
4K
128
128K
8K
Table 7-3 on page 14 shows EEPROM memory organization for the XMEGA A4U devices.
EEPROM write and erase operations can be performed one page or one byte at a time, while
reading the EEPROM is done one byte at a time. For EEPROM access the NVM Address Regis-
ter (ADDR[m:n]) is used for addressing. The most significant bits in the address (E2PAGE) give
the page number and the least significant address bits (E2BYTE) give the byte in the page.
Table 7-3.
Number of Bytes and Pages in the EEPROM.
Devices
EEPROM
Size
1K
Page Size
E2BYTE
E2PAGE
No of Pages
(Bytes)
32
ATxmega16A4U
ATxmega32A4U
ATxmega64A4U
ATxmega128A4U
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
ADDR[10:5]
ADDR[10:5]
ADDR[10:5]
ADDR[10:5]
32
32
64
64
1K
32
2K
32
2K
32
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XMEGA A4U
8. DMAC - Direct Memory Access Controller
8.1
Features
• The DMA Controller allows data transfers with minimal CPU intervention
– from data memory to data memory
– from data memory to peripheral
– from peripheral to data memory
– from peripheral to peripheral
• Four DMA Channels with separate
– transfer triggers
– interrupt vectors
– addressing modes
• Programmable channel priority
• From 1byte to 16Mbytes of data in a single transaction
• Multiple addressing modes
– Static
– Increment
– Decrement
• Optional reload of source and destination address at the end of each
– Burst
– Block
– Transaction
• Optional Interrupt on end of transaction
• Optional connection to CRC Generator module for CRC on DMA data
8.2
Overview
The 4-channel Direct Memory Access (DMA) Controller can transfer data between memories
and peripherals, and thus offload these tasks from the CPU. It enables high data transfer rates
with minimum CPU intervention, and frees up CPU time. The 4 DMA channels enable up to four
independent and parallel transfers.
The DMA Controller can move data between SRAM and peripherals, between SRAM locations
and between peripheral registers directly. With access to all peripherals the DMA Controller can
handle automatic transfer of data to/from communication modules, as well as data retrieval from
ADC conversions, or data transfer to or from port pins. The DMA Controller can also read from
memory mapped EEPROM.
Data transfers are done in continues bursts of 1, 2, 4 or 8bytes. They build block transfers of
configurable size from 1 to 64Kbytes. A repeat counter can be used to repeat each block trans-
fer for single transactions up to 16Mbytes. Source and destination addressing can be static,
incremental or decremental. Automatic reload of source and/or destination address can be done
after each burst, block transfer, or when transaction is complete. Application software, peripher-
als and events can trigger DMA transfers.
The four DMA channels have individual configuration and control settings. This include source,
destination, transfer triggers and transaction sizes. They have individual interrupt settings. Inter-
rupt requests can be generated both when a transaction is complete or if the DMA Controller
detects an error on a DMA channel.
To allow for continuous transfers, two channels can be interlinked so that the second takes over
the transfer when the first is finished and vice versa.
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9. Event System
9.1
Features
• System for direct peripheral to peripheral communication and signaling
• Peripherals can directly send, receive and react to peripheral events
– CPU and DMA controller independent operation
– 100% predictable signal timing
– Short and guaranteed response time
• 8 Event Channels for up to 8 different and parallel signal routines and configurations
• Events can be sent and/or used by most peripherals, clock system and software
• Additional functions include
– Quadrature Decoders
– Digital Filtering of I/O pin change
• Works in Active mode and Idle sleep mode
9.2
Overview
The Event System is system for direct peripheral to peripheral communication and signaling. It
enables the possibility for a change in one peripheral to automatically trigger actions in others
peripherals. It is designed for having a predictable system for short and guaranteed response
time between peripherals. It is simple and powerful since it allows for autonomous peripheral
control and interaction without use of interrupts, CPU or DMA Controller resources. It also
enables synchronized timing of actions in several peripheral modules.
The change in a peripheral is referred to as an event, and is it usually the same as the interrupt
conditions for the peripheral. These events can be directly passed to other peripherals using a
dedicated routing network called the Event Routing Network. How events are routed and used
by other peripherals is configured in software.
Figure 9-1 on page 17 shows a basic block diagram of all connected peripherals. The Event
System can directly connect together Analog and Digital converters, Analog Comparators, I/O
ports pins, the Real-time Counter, Timer/Counters, IR Communication Module (IRCOM), and
USB. It can also be used to trigger DMA transactions (DMA Controller). Events can also be gen-
erated from software and the Peripheral Clock.
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Figure 9-1. Event system block diagram
CPU /
Software
DMA
Controller
Event Routing Network
clkPER
Prescaler
ADC
AC
Real Time
Counter
Event
System
Controller
Timer /
Counters
DAC
USB
Port pins
IRCOM
The Event Routing Network consists of eight software configurable multiplexers that control how
events are routed and used. This is called Event Channels and it enables up to eight parallel
event configurations and routings. The maximum routing latency between two peripherals is two
Peripheral clock cycles. The Event System works in both Active mode and Idle sleep mode.
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10. System Clock and Clock options
10.1 Features
• Fast start-up time
• Safe run-time clock switching
• Internal Oscillators:
– 32MHz run-time calibrated and tuneable oscillator
– 2MHz run-time calibrated oscillator
– 32.768kHz calibrated oscillator
– 32kHz Ultra Low Power (ULP) oscillator with 1kHz output
• External clock options
– 0.4 - 16MHz Crystal Oscillator
– 32 kHz Crystal Oscillator
– External clock
• PLL with 20 - 128MHz output frequency
– Internal and external clock options and 1 to 31x multiplication
– Lock detector
• Clock Prescalers with 1 to 2048x division
• Fast peripheral clocks running at 2 and 4 times the CPU clock frequency
• Automatic Run-Time Calibration of internal oscillators
• External oscillator and PLL lock failure detection with optional non maskable interrupt
10.2 Overview
The flexible clock system supports a large number of clock sources. It incorporates both accu-
rate internal oscillators, and external crystal oscillators and resonator support. A high frequency
Phase Locked Loop (PLL) and clock prescalers can be used to generate a wide range of clock
frequencies. A calibration feature (DFLL) is available, and can be used for automatic runtime
calibration of the internal oscillators to remove frequency drift over voltage and temperate. An
Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and switch to inter-
nal oscillator if the external oscillator or PLL fails.
When a reset occur, all clock sources except 32kHz Ultra Low Power oscillator are disabled.
After reset, the device will always start up running from the 2MHz internal oscillator. During nor-
mal operation, the System Clock source and prescalers can be changed from software at any
time.
Figure 10-1 on page 19 presents the principal clock system in the XMEGA. All of the clocks do
not need to be active at a given time. The clocks to the CPU and peripherals can be stopped
using sleep modes and power reduction registers.
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Figure 10-1. The Clock system, clock sources and clock distribution
Real Time
Counter
Non-Volatile
Memory
Peripherals
RAM
AVR CPU
clkPER
clkPER2
clkPER4
clkCPU
USB
clkUSB
System Clock Prescalers
clkSYS
Prescaler
Brown-out
Detector
Watchdog
Timer
clkRTC
System Clock Multiplexer
(SCLKSEL)
RTCSRC
USBSRC
PLL
PLLSRC
XOSCSEL
32 kHz
Int. ULP
32.768 kHz
Int. OSC
32.768 kHz
TOSC
0.4 – 16 MHz
XTAL
32 MHz
Int. Osc
2 MHz
Int. Osc
10.3 Clock Options
10.3.1
32kHz Ultra Low Power Internal Oscillator
This oscillator provides an approximate 32kHz clock. The 32kHz Ultra Low Power (ULP) Internal
Oscillator is a very low power clock source, and it is not designed for high accuracy. The oscilla-
tor employs a built in prescaler providing a 1kHz output. The oscillator is automatically
enabled/disabled when used as clock source for any part of the device. This oscillator can be
selected as clock source for the RTC.
10.3.2
32.768kHz Calibrated Internal Oscillator
This oscillator provides an approximate 32.768kHz clock. A factory-calibrated value is written to
the 32.768kHz oscillator calibration register during reset to ensure that the oscillator is running-
within its specification. The calibration register can also be written from software for run-time
calibration of the oscillator frequency. The oscillator employs a built in prescaler providing both a
32.768kHz output and a 1.024kHz output.
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10.3.3
32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between TOSC1 and TOSC2 pins and enable a
dedicated low frequency oscillator input circuit. A low power mode with reduced voltage swing
on TOSC2 is available. This oscillator can be used as clock source for the System Clock, RTC
and as the DFLL reference clock.
10.3.4
10.3.5
0.4 - 16MHz Crystal Oscillator
The 0.4 - 16MHz Crystal Oscillator is a driver intended for driving both external resonators and
crystals ranging from 400kHz to 16MHz.
2MHz Run-time Calibrated Internal Oscillator
The 2MHz Run-time Calibrated Internal Oscillator is the default system clock source after reset.
It is calibrated during production to provide a default frequency which is close to its nominal fre-
quency. A Digital Frequency Looked Loop (DFLL) that can be enabled for automatic run-time
calibration of the oscillator to compensate for temperature and voltage drift to optimize the oscil-
lator accuracy.
10.3.6
32MHz Run-time Calibrated Internal Oscillator
The 32MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during production to provide a default frequency which is close to its nominal frequency. A DFLL
that can be enabled for automatic run-time calibration of the oscillator to compensate for temper-
ature and voltage drift to optimize the oscillator accuracy This oscillator can also be adjusted
and calibrated to any frequency between 30 and 55MHz.
10.3.7
10.3.8
External Clock input
The external clock input gives the possibility to connect a clock from an external source to
XTAL1.
PLL with Multiplication factor 1 - 31x
The PLL provides the possibility of multiplying a frequency by any number from 1 to 31. In com-
bination with the prescalers, this gives a wide range of output frequencies from all clock sources.
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11. Power Management and Sleep Modes
11.1 Features
• Power management for adjusting power consumption and enabled functions
• 5 sleep modes:
– Idle
– Power-down
– Power-save
– Standby
– Extended standby
• Power Reduction register to disable clock and turn off unused peripherals in Active and Idle
mode
11.2 Overview
Various sleep modes and clock gating are implemented in order to tailor power consumption to
the application's requirement. This enables the microcontroller to stop unused modules to save
power.
All sleep modes are available and can be entered from Active mode. In Active mode the CPU is
executing application code. When the device enters sleep mode, program execution is stopped
and interrupts or reset is used to wake the device again. The application code decides when and
what sleep mode to enter. Interrupts from enabled peripherals and all enabled reset sources can
restore the microcontroller from sleep to Active mode.
In addition, Power Reduction registers provide a method to stop the clock to individual peripher-
als from software. When this is done, the current state of the peripheral is frozen and there is no
power consumption from that peripheral. This reduces the power consumption in Active mode
and Idle sleep mode and enable much more fine-tuned power management than sleep modes
alone.
11.3 Sleep Modes
11.3.1
Idle Mode
In Idle mode the CPU and Non-Volatile Memory are stopped, but all peripherals including the
Interrupt Controller, Event System and DMA Controller are kept running. Any enabled interrupt
will wake the device.
11.3.2
Power-down Mode
In Power-down mode all clocks, including the Real Time Counter clock source are stopped. This
only allows operation of asynchronous modules that does not require a running clock. The only
interrupts that can wake up the MCU are the Two Wire Interface address match interrupt, asyn-
chronous port interrupts and USB resume interrupt.
11.3.3
Power-save Mode
Power-save mode is identical to Power-down, with one exception, if the Real Time Counter
(RTC) is enabled, it will keep running during sleep and the device can also wake up from either
RTC Overflow or Compare Match interrupt.
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11.3.4
11.3.5
Standby Mode
Standby mode is identical to Power-down with the exception that the enabled system clock
sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces
the wake-up time.
Extended Standby Mode
Extended Standby mode is identical to Power-save mode with the exception that the enabled
system clock sources are kept running while the CPU and Peripheral clocks are stopped. This
reduces the wake-up time.
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12. System Control and Reset
12.1 Features
• Reset the microcontroller and set it to its initial state when a reset source goes active
• Multiple reset sources that cover different situations
– Power-On Reset
– External Reset
– Watchdog Reset
– Brown-Out Reset
– PDI reset
– Software reset
• Asynchronous operation
– No running system clock in the device is required for the reset
• Reset Status Register for reading the reset source from the application code
12.2 Overview
The Reset System issues a microcontroller reset and set the device to its initial state. This is for
situation where operation should not start or continue, for example when the microcontroller
operates below its power supply rating. If a reset source goes active, the device enters and be
kept in reset until all reset sources have released their reset. The I/O pins are immediately
tristated.
The program counter is set to the Reset Vector location and all I/O registers are set to the initial
value. The SRAM content is kept, but not guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated
before the device starts running from the Reset Vector address. By default this is the lowest pro-
gram memory address, '0', but it is possible to move the Reset Vector to the lowest address in
the Boot Section.
The reset functionality is asynchronous, so no running system clock is required to reset the
device. The software reset feature makes it possible to issue a controlled system reset from the
user software.
The reset status register has individual status flags for each reset source. It is cleared at Power-
on Reset, it shows which sources that have issued a reset since the last power-on.
12.3 Reset Sources
12.3.1
Power-On Reset
The device is reset when the supply voltage VCC is below the Power-on Reset threshold
voltage.
12.3.2
12.3.3
External Reset
The device is reset when a low level is present on the RESET pin.
Watchdog Reset
The device is reset when the Watchdog Timer period expires and the Watchdog Reset is
enabled. The Watchdog Timer runs from a dedicated oscillator independent of the System
Clock. For more details see ”WDT - Watchdog Timer” on page 25.
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12.3.4
Brown-Out Reset
The device is reset when the supply voltage VCC is below the Brown-Out Reset threshold volt-
age and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable.
12.3.5
12.3.6
PDI reset
The MCU can be reset through the Program and Debug Interface (PDI).
Software reset
The MCU can be reset by the CPU writing to a special I/O register through a timed sequence.
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13. WDT - Watchdog Timer
13.0.1
Features
• Issues a device reset if the timer is not reset before its timeout period
• Asynchronously operation from dedicated oscillator
– 1kHz output of the 32kHz Ultra Low Power oscillator
• 11 selectable timeout periods, from 8ms to 8s.
• Two operation modes
– Normal mode
– Window mode
• Configuration lock to prevent unwanted changes
13.1 Overview
The Watchdog Timer (WDT) is a system function for monitoring correct program operation. It
makes it possible to recover from error situations such as run-away or dead-lock code. The WDT
is a timer, configured to a predefined timeout period and is constantly running when enabled. If
the WDT is not reset within the timeout period, it will issue a microcontroller reset. The WDT is
reset by executing the WDR (Watchdog Timer Reset) instruction from the application code.
The window mode makes it possible to define a time slot window inside the total timeout period
where WDT must be reset within. If the WDT is reset too early or too late and outside this win-
dow, a system reset will be issued. Compared to the normal mode, this can also catch situations
where a code error also causes constant WDR execution.
The WDT will run in Active mode and all sleep modes if enabled. It is asynchronous and runs
from a CPU independent clock source, and will continue to operate to issue a system reset even
if the main clocks fail. The Configuration Change Protection mechanism ensures that the WDT
settings cannot be changed by accident. For increased safety, a fuse for locking the WDT set-
tings is available.
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14. Interrupts and Programmable Multi-level Interrupt Controller
14.1 Features
• Short and predictable interrupt response time
• Separate interrupt configuration and vector address for each interrupt
• Programmable Multi-level Interrupt Controller
– Interrupt prioritizing according to level and vector address
– 3 selectable interrupt levels for all interrupts: Low, Medium and High
– Selectable round-robin priority scheme within low level interrupts
– Non-Maskable Interrupts for critical functions
• Interrupt vectors can be moved from the Application Section to the Boot Loader Section
14.2 Overview
Atmel® AVR® XMEGA® have a Programmable Multi-level Interrupt Controller (PMIC). Interrupts
signal a change of state in peripherals, and this can be used to alter program execution. Periph-
erals can have one or more interrupts, and all are individually enabled and configured. When an
interrupt is enabled and configured, it will generate an interrupt request when the interrupt condi-
tion is present. The Programmable Multi-level Interrupt Controller (PMIC) controls the handling
and prioritizing of interrupt requests. When an interrupt request is acknowledged by the PMIC,
the program counter is set to point to the interrupt vector, and the interrupt handler can be
executed.
All peripherals can select between three different priority levels for their interrupts; low, medium
and high. Interrupts are prioritized according to their level and their interrupt vector address.
Medium level interrupts will interrupt low level interrupt handlers. High level interrupts will inter-
rupt both medium and low level interrupt handlers. Within each level, the interrupt priority is
decided from the interrupt vector address, where the lowest interrupt vector address has the
highest interrupt priority. Low level interrupts have an optional round-robin scheduling scheme to
ensure that all interrupts are serviced within a certain amount of time.
Non-Maskable Interrupts (NMI) is also supported and can be used for critical functions. If a boot-
loader is used, it is possible to move the interrupt vectors from the Application Section to the
Boot Loader Sections so interrupts can be used and executed also during self-programming.
14.3 Interrupt vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address
for specific interrupts in each peripheral. The base addresses for the XMEGA A4U devices are
shown in Table 14-1 on page 27. Offset addresses for each interrupt available in the peripheral
are described for each peripheral in the XMEGA AU manual. For peripherals or modules that
have only one interrupt, the interrupt vector is shown in Table 14-1 on page 27. The program
address is the word address.
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Table 14-1. Reset and Interrupt Vectors
Program Address
(Base Address)
0x000
0x002
0x004
0x008
0x00C
0x014
0x018
0x01C
0x028
0x030
0x032
0x038
0x03E
0x040
0x044
0x056
0x05A
0x05E
0x06A
0x074
0x080
0x084
0x088
0x08E
0x09A
0x0A6
0x0AE
0x0B0
0x0B6
0x0FA
Source
Interrupt Description
RESET
OSCF_INT_vect
PORTC_INT_base
PORTR_INT_base
DMA_INT_base
RTC_INT_base
TWIC_INT_base
TCC0_INT_base
TCC1_INT_base
SPIC_INT_vect
Crystal Oscillator Failure Interrupt vector (NMI)
Port C Interrupt base
Port R Interrupt base
DMA Controller Interrupt base
Real Time Counter Interrupt base
Two-Wire Interface on Port C Interrupt base
Timer/Counter 0 on port C Interrupt base
Timer/Counter 1 on port C Interrupt base
SPI on port C Interrupt vector
USARTC0_INT_base
USARTC1_INT_base
AES_INT_vect
USART 0 on port C Interrupt base
USART 1 on port C Interrupt base
AES Interrupt vector
NVM_INT_base
PORTB_INT_base
PORTE_INT_base
TWIE_INT_base
TCE0_INT_base
TCE1_INT_base
USARTE0_INT_base
PORTD_INT_base
PORTA_INT_base
ACA_INT_base
ADCA_INT_base
TCD0_INT_base
TCD1_INT_base
SPID_INT_vector
USARTD0_INT_base
USARTD1_INT_base
USB_INT_base
Non-Volatile Memory Interrupt base
Port B Interrupt base
Port E Interrupt base
Two-Wire Interface on Port E Interrupt base
Timer/Counter 0 on port E Interrupt base
Timer/Counter 1 on port E Interrupt base
USART 0 on port E Interrupt base
Port D Interrupt base
Port A Interrupt base
Analog Comparator on Port A Interrupt base
Analog to Digital Converter on Port A Interrupt base
Timer/Counter 0 on port D Interrupt base
Timer/Counter 1 on port D Interrupt base
SPI on port D Interrupt vector
USART 0 on port D Interrupt base
USART 1 on port D Interrupt base
USB on port D Interrupt base
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15. I/O Ports
15.1 Features
• General purpose input and output pins with several and individual configuration options
• Output driver with configurable driver and pull settings:
– Totem-pole
– Wired-AND
– Wired-OR
– Bus-keeper
– Inverted I/O
• Input with synchronous and/or asynchronous sensing with port interrupts and events
– Sense both edges
– Sense rising edges
– Sense falling edges
– Sense low level
• Optimal pull-up and pull-down resistor on input and Wired-OR/AND configurations
• Optional slew rate control
• Asynchronous pin change sensing that can wake-up the device from all sleep modes
• Two port interrupts with pin masking per I/O port
• Efficient and safe access to port pins
– Hardware read-modify-write through dedicated Toggle/Clear/Set registers
– Configuration of multiple pins in a single operation
– Mapping of port registers into bit-accessible I/O memory space
• Peripheral Clocks output on port pin
• Real Time Counter Clock output to port pin
• Event Channel output on port pin
• Remap of digital peripheral pin functions
– Selectable USART, SPI and Timer/Counter input/output pin locations
15.2 Overview
One port consists of up to 8 pins ranging from pin 0 to 7. Each port pin can be configured as
input or output with configurable driver and pull settings. They also implement synchronous and
asynchronous input sensing with interrupts and events for selectable pin change conditions.
Asynchronous pin-change sensing means that a pin change can wake the device from all sleep
modes, included the modes where no clocks are running.
All functions are individual and configurable per pin, but several pins can be configured in one
single operation. The pins have hardware Read-Modify-Write (RMW) functionality for safe and
correct change of drive value and/or pull resistor configuration. The direction of one port pin can
be changed without unintentionally changing the direction of any other pin.
The port pin configuration also controls input and output selection of other device function. It is
possible to have both the peripheral clock and the real time clock output to a port pin, and avail-
able for external use. The same applies to events from the Event System that can be used to
synchronize and control external functions. Other digital peripherals such as USART, SPI and
Timer/Counters can be remapped to selectable pin location in order to optimize pinout versus
application needs.
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15.3 Output Driver
All port pins (Pn) have programmable output configuration. The port pins also have configurable
slew rate limitation to reduce electromagnetic emission.
15.3.1
Push-pull
Figure 15-1. I/O configuration - Totem-pole
DIRn
OUTn
INn
Pn
15.3.2
Pull-down
Figure 15-2. I/O configuration - Totem-pole with pull-down (on input)
DIRn
OUTn
INn
Pn
15.3.3
Pull-up
Figure 15-3. I/O configuration - Totem-pole with pull-up (on input)
DIRn
OUTn
INn
Pn
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15.3.4
Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as
a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’.
Figure 15-4. I/O configuration - Totem-pole with bus-keeper
DIRn
Pn
OUTn
INn
15.3.5
Others
Figure 15-5. Output configuration - Wired-OR with optional pull-down
OUTn
Pn
INn
Figure 15-6. I/O configuration - Wired-AND with optional pull-up
INn
Pn
OUTn
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15.4 Input sensing
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports,
and the configuration is shown in Figure 15-7 on page 31.
Figure 15-7. Input sensing system overview
Asynchronous sensing
EDGE
DETECT
Interrupt
Control
IREQ
Synchronous sensing
Pn
Synchronizer
INn
EDGE
DETECT
Q
Q
D
D
Event
INVERTED I/O
R
R
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
15.5 Alternate Port Functions
In addition to the input/output functions on all port pins, most pins have alternate functions. This
means that other modules or peripherals connected to the port can use the port pins for their
functions, such as communication or pulse-width modulation. ”Pinout and Pin Functions” on
page 51 shows which modules on peripherals that enable alternate functions on a pin, and
which alternate function is available on a pin.
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16. T/C - 16-bit Timer/Counter
16.1 Features
• Five 16-bit Timer/Counters
– Three Timer/Counters of type 0
– Two Timer/Counters of type 1
• 32-bit Timer/Counter support by cascading two Timer/Counters
• Up to 3 Compare or Capture (CC) Channels
– 3 CC Channels for Timer/Counter of type 0
– 2 CC Channels for Timer/Counter of type 1
• Double Buffered Timer Period Setting
• Double Buffered Compare or Capture Channels
• Waveform Generation:
– Frequency Generation
– Single Slope Pulse Width Modulation
– Dual Slope Pulse Width Modulation
• Input Capture:
– Input Capture with noise cancelling
– Frequency capture
– Pulse width capture
– 32-bit input capture
• Timer Overflow and Error interrupts / events
• One Compare Match or Input Capture interrupt / event per CC Channel
• Can be used with Event System for
– Quadrature Decoding
– Count and direction control
– Capture
• Can be used with DMA and trigger DMA transactions
• High-Resolution Extension
– Increases frequency and waveform resolution by 4x (2-bit), or 8x (3-bit)
• Advanced Waveform Extension
– Low and High-side output with programmable Dead-Time Insertion (DTI)
• Event controlled fault protection for safe disabling of external drivers
16.2 Overview
There are five flexible 16-bit Timer/Counters (TC). Their capabilities include accurate program
execution timing, frequency and waveform generation, and input capture with time and fre-
quency measurement of digital signals. Two Timer/Counters can be cascaded to create 32-bit
Timer/Counter with optional 32-bit capture.
A Timer/Counter consists of a Base Counter and a set of Compare or Capture (CC) channels.
The Base Counter can be used to count clock cycles or events. It has direction control and
period setting that can be used for timing. The CC channels can be used together with the Base
Counter to do compare match control, frequency generation and pulse width waveform modula-
tion, or various input capture operations. A Timer/Counter can be configured for either capture or
compare functions, and not perform both at the same time.
A Timer/Counter can be clocked and timed from the Peripheral Clock with optional prescaling or
the Event System. The Event System can also be used for direction control, capture trigger or to
synchronize operations.
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Figure 16-1. Overview of a Timer/Counter and closely related peripherals
Timer/Counter
Base Counter
Timer Period
Counter
Prescaler
clkPER
Control Logic
Event
System
clkPER4
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
AWeX
Pattern
Generation
Fault
Dead-Time
Insertion
Capture
Comparator
Control
Protection
Waveform
Buffer
Generation
The only difference between Timer/Counter type 0 and 1 is the number of CC Channels.
Timer/Counter 0 has four CC channels, and Timer/Counter 1 has two CC channels. All informa-
tion related to CC channel 3 and 4 is only valid for Timer/Counter 0.
Some Timer/Counters have extensions to enable more specialized waveform and frequency
generation. The Advanced Waveform Extension (AWeX) is intended for motor control and other
power control applications. It enables Low- and High Side output with Dead Time Insertion, and
fault protection for disabling and shutdown of drivers. It can also generate a synchronized bit
pattern across the port pins.See ”Hi-Res - High Resolution Extension” on page 35 for more
details.
The High Resolution (Hi-Res) extension can be used to increase the waveform output resolution
by up to eight times, by using internal clock source running up to four times faster than the
Peripheral Clock. See ”AWeX - Advanced Waveform Extension” on page 34 for more details.
PORTC and PORTD each has one Timer/Counter 0 and one Timer/Counter1. PORTE has one
Timer/Conter0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCD1 and TCE0,
respectively.
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17. AWeX - Advanced Waveform Extension
17.1 Features
• Wafeform output with complementary output from each Compare channel
• 4 Dead-Time Insertion (DTI) Units
– 8-bit Resolution
– Separate High and Low Side Dead-Time Setting
– Double Buffered Dead-Time
– Optionally halts Timer during Dead-Time Insertion
• Pattern Generation unit creating synchronised bit pattern across the port pins
– Double buffered pattern generation
– Optionally distribution of one Compare channel output across the port pins
• Event controlled Fault Protection for instant and predictably fault triggering
17.2 Overview
The Advanced Waveform Extension (AWeX) provides extra functions to the Timer/Counter in
Waveform Generation (WG) modes. It is primarily intended for different types of motor control
and other power control applications. It enables Low- and High Side output with Dead Time
Insertion, and fault protection for disabling and shutdown of drivers. It can also generate a syn-
chronized bit pattern across the port pins.
Each of the waveform generator outputs from the Timer/Counter 0 are split into a complimentary
pair of outputs when any AWeX features are enabled. These output pairs go through a Dead-
Time Insertion (DTI) unit that generates the non-inverted Low Side (LS) and inverted High Side
(HS) of the WG output with dead time insertion between LS and HS switching. The DTI output
will override the normal port value according to the port override setting.
The Pattern Generation unit can be used to generate a synchronized bit pattern across the port
it is connected to. In addition, the WG output from the Compare Channel A can be distributed to
and override all the port pins. When the Pattern Generator unit is enabled the DTI unit is
bypassed.
The Fault Protection unit is connected to the Event System, enabling any event to trigger a fault
condition that will disable the AWeX output. The Event System ensure predictable and instant
fault reaction, and gives great flexibility in the selection of fault triggers.
The AWEX is available for TCC0. The notation of this is AWEXC.
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18. Hi-Res - High Resolution Extension
18.1 Features
• Increases Waveform Generator resolution by up to 8 times (3-bit)
• Supports Frequency, Single Slope PWM and Dual Slope PWM generation
• Supports the AWeX when this is used for the same Timer/Counter
18.2 Overview
The Hi-Resolution (Hi-Res) Extension is able to increase the resolution of the waveform genera-
tion output by a factor of four or eight. It can be used for a Timer/Counter doing Frequency,
Single Slope PWM or Dual Slope PWM generation. It can also be used with the AWeX if this is
used for the same Timer/Counter.
Atmel® AVR® XMEGA® A4U have three Hi-Res Extensions that each can be enabled for each
Timer/Counters pair on PORTC, PORTD and PORTE. The notation of these are HIRESC,
HIRESD and HIRESE, respectively.
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19. RTC - 16-bit Real-Time Counter
19.1 Features
• 16-bit resolution
• Selectable clock source
– 32.768kHz external crystal
– External clock
– 32.768kHz internal oscillator
– 32kHz internal ULP oscillator
• Programmable 10-bit clock prescaling
• One Compare register
• One Period register
• Clear Counter on period overflow
• Optional Interrupt/ Event on overflow and compare match
19.2 Overview
The 16-bit Real Time Counter (RTC) is a counter that typically runs continuously, including in
low power sleep modes, to keep track of time. It can wake up the device from sleep modes
and/or interrupt the device at regular intervals.
The reference clock is typically the 1.024kHz output from a high accuracy crystal of 32.768kHz,
and this is the configuration most optimized for low power consumption. The faster 32.768kHz
output can be selected if the RTC needs a higher resolution than 1mS. The RTC can also be
clocked from an external clock signal, the internal 32.768kHz oscillator or the internal 32kHz
ULP oscillator.
The RTC includes a 10-bit programmable prescaler that can scale down the reference clock
before it reaches the Counter. A wide range of resolution and time-out periods can be config-
ured. With a 32.768kHz clock source the maximum resolution of 30.5µs, time-out periods range
up to 2000seconds. With a resolution of 1 second, the maximum time-out period is over 18hours
(65536seconds). The RTC can give a compare interrupt and/or event when the counter equals
the Compare register value, and an overflow interrupt and/event when it equals the Period regis-
ter value.
Figure 19-1. Real Time Counter overview
External Clock
TOSC1
32.768kHz Crystal Osc
TOSC2
32.768kHz Int. Osc
32kHz int ULP (DIV32)
PER
RTCSRC
TOP/
clkRTC
10-bit
=
=
Overflow
CNT
prescaler
”match”/
Compare
COMP
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20. USB - Universal Serial Bus Interface
20.1 Features
• One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface
• Integrated on-chip USB transceiver, no external components needed
• 16 endpoint addresses with full endpoint flexibility for up to 32 endpoints
– One input endpoint per endpoint address
– One output endpoint per endpoint address
• Endpoint address transfer type selectable to
– Control transfers
– Interrupt transfers
– Bulk transfers
– Isochronous transfers
• Configurable data payload size per endpoint, up to 1023bytes
• Endpoint configuration and data buffers located in internal SRAM
– Configurable location for endpoint configuration data
– Configurable location for each endpoint's data buffer
• Built in Direct Memory Access (DMA) to internal SRAM for
– Endpoint configurations
– Read and write of endpoint data
• Ping-Pong operation for higher throughput and double buffered operation
– Input and output endpoint data buffers used in a single direction
– CPU/DMA controller can update data buffer during transfer
• Multi-Packet transfer for reduced interrupt load and software intervention
– Data payload exceeding max packet size is transferred in one continuous transfer
– No interrupts or software interaction on packet transaction level
• Transaction Complete FIFO for easy flow management when using multiple endpoints
– Tracks all completed transactions in a first come, first serve work-queue
• Clock selection independent of System Clock source selection
• Connection to Event System
• On chip debug possibilities during USB transactions
20.2 Overview
The USB interface is an USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compli-
ant interface.
It supports 16 endpoint addresses. All endpoint addresses have one input and one output end-
point, for a total of 32 endpoints. Each endpoint address is fully configurable and can be
configured for any of the four transfer types: control, interrupt, bulk or isochronous. The data
payload size is also selectable and it supports data payloads up to 1023bytes.
No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to
keep the configuration for each endpoint address, and the data buffer for each endpoint. The
memory locations used for endpoint configurations and data buffers are fully configurable. The
amount of memory allocated is fully dynamic according to the number of endpoints in use, and
the configuration of these. The USB module has built-in Direct Memory Access (DMA) and will
read/write data from/to the SRAM when a USB transaction takes place.
To maximise throughput, an endpoint address can be configured for Ping-Pong operation. When
this is done, the input and output endpoints are both used in the same direction. The CPU or
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DMA Controller can then read/write one data buffer while the USB module writes/reads the
other, and vice versa. This gives double buffered communication.
Multi-packet transfer enables a data payload exceeding the maximum packet size of an end-
pointto be transferred as multiple packets without software intervention. This reduce the CPU
intervention and the interrupts needed for USB transfers.
For low power operation, the USB module can put the microcontroller in any sleep mode when
the USB bus is idle and a suspend condition is given. Upon bus resume, the USB module can
wake the microcontroller from any sleep mode.
PORTD has one USB. Notation of this is USB.
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21. TWI - Two Wire Interface
21.1 Features
• Two Identical Two Wire Interface peripherals
• Bi-directional two-wire communication interface
– Phillips I2C compatible
– System Management Bus (SMBus) compatible
• Bus master and slave operation supported
– Slave operation
– Single bus master operation
– Bus master in multi-master bus environment
– Multi-master arbitration
• Flexible slave address match functions
– 7-bit and General Call Address Recognition in Hardware
– 10-bit addressing supported
– Address mask register for dual address match or address range masking
– Optional software address recognition for unlimited number of addresses
• Slave can operate in all sleep modes
• Slave address match can wake device from all sleep modes
• 100kHz and 400kHz bus frequency support
• Slew-rate limited output drivers
• Input filter for bus noise and spike suppression
• Support arbitration between START/Repeated START and Data Bit (SMBus)
• Slave arbitration allows support for Address Resolve Protocol (ARP) (SMBus)
21.2 Overview
The Two Wire Interface is a bi-directional two-wire communication interface. It is I2C and System
Management Bus (SMBus) compatible. The only external hardware needed to implement the
bus is one pull-up resistor on each bus line.
The TWI module supports master and slave functionality. The master and slave functionality are
separated from each other and can be enabled and configured separately. The master module
supports multi-master bus operation and arbitration. It contains the baud rate generator. Both
100kHz and 400kHz bus frequency is supported.
The slave module implements 7-bit address match and general address call recognition in hard-
ware. 10-bit addressing is also supported. A dedicated address mask register can act as a
second address match register or as a register for address range masking. The slave continues
to operate in all sleep modes, including Power down mode. This enables the slave to wake up
the device from all sleep modes on TWI address match. It is possible to disable the address
matching to let this be handled in software instead. Smart Mode can be enabled to auto trigger
operations and reduce software complexity.
The TWI module will detect START and STOP conditions, bus collision and bus errors. Arbitra-
tion lost, errors, collision and clock hold on the bus is also detected and indicated in separate
status flags available in both master and slave mode.
It is possible to disable the TWI drivers in the device, and enable a 4-wire digital interface for
connecting to an external TWI bus driver. This can be used for applications where the device
operates from a different VCC voltage than used by the TWI bus.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE,
respectively.
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22. SPI - Serial Peripheral Interface
22.1 Features
• Two Identical SPI peripherals
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• Interrupt Flag at the End of Transmission
• Write collision flag to indicate data collision
• Wake-up from Idle Mode
• Double Speed Master Mode
22.2 Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using
three or four pins. It allows fast communication between an XMEGA device and peripheral
devices or other microcontrollers. The SPI supports full duplex communication.
A device connected to the bus must act as a master or slave. The master initiates and controls
all data transactions, and data is transferred both to and from the device simultaneously.
PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID,
respectively.
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23. USART
23.1 Features
• Five Identical USART peripherals
• Full Duplex Operation
• Asynchronous or Synchronous Operation
– Synchronous clock rates up to 1/2 o the device clock frequency
– Asynchronous clock rates up to 1/8 of the device clock frequency
• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
• Fractional Baud Rate Generator
– Can generate desired baud rate from any system clock frequency
– No need for external oscillator with certain frequencies
• Built in error detection and correction schemes
– Odd or Even Parity Generation and Parity Check
– Data Over Run and Framing Error Detection
– Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
• Separate Interrupts for
– Transmit Complete
– Transmit Data Register Empty
– Receive Complete
• Multi-Processor Communication Mode
– Addressing scheme to address a specific devices on a multi-device bus
– Enable unaddressed devices to automatically ignore all frames
• Master SPI Mode
– Double Buffered Operation
– Configurable Data Order
– High Speed Operation up to 1/2 of the peripheral clock frequency
• IRCOM Module for IrDA compliant pulse modulation/demodulation
23.2 Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
fast and flexible serial communication module. The USART supports full duplex communication,
and both asynchronous and clocked synchronous operation. The USART can also be set in
Master SPI mode and be used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide
range of standards. The USART is buffered in both direction, enabling continued data transmis-
sion without any delay between frames. There are separate interrupts for receive and transmit
complete, enabling fully interrupt driven communication. Frame error and buffer overflow are
detected in hardware and indicated with separate status flags. Even or odd parity generation
and parity check can also be enabled.
The Clock Generation logic has a fractional baud rate generator that is able to generate a wide
range of USART baud rates from any system clock frequencies. This remove the need to use
an external crystal oscillator with a certain frequency in order to achieve a required baud rate. It
also includes support external clock input in synchronous slave operation.
One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modula-
tion and demodulation for baud rates up to 115.2kbps.
PORTC and PORTD each has two USARTs. PORTE has one USART. Notation of these periph-
erals are USARTC0, USARTC1, USARTD0, USARTD1 and USARTE0, respectively.
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24. IRCOM - IR Communication Module
24.1 Features
• Pulse modulation/demodulation for infrared communication
• IrDA Compatible for baud rates up to 115.2kbps
• Selectable pulse modulation scheme
– 3/16 of baud rate period
– Fixed pulse period, 8-bit programmable
– Pulse modulation disabled
• Built in filtering
• Can be connected to and used by one USART at a time
24.2 Overview
The Infrared Communication Module (IRCOM) is used for IrDA communication with baud rates
up to 115.2kbps. There is one IRCOM available which can be connected to any USART to
enable infrared pulse coding/decoding for that USART.
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25. AES and DES Crypto Engine
25.1 Features
• Data Encryption Standard (DES) CPU instruction
• Advanced Encryption Standard (AES) Crypto module
• DES Instruction
– Encryption and Decryption
– Single-cycle DES instruction
– Encryption/Decryption in 16 clock cycles per 8-byte block
• AES Crypto Module
– Encryption and Decryption
– Supports 128-bit keys
– Supports XOR data load mode to the State memory for Cipher Block Chaining
– Encryption/Decryption in 375 clock cycles per 16-byte block
25.2 Overview
The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two com-
monly used standards for cryptography. These are supported through an AES peripheral
module and a DES CPU instruction, and the communication interfaces and the CPU can use
these for fast encrypted communication and secure data storage.
DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must
be loaded into the Register file, and then the DES instruction must be executed 16 times to
encrypt/decrypt the data block.
The AES Crypto Module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key.
The key and data must be loaded into the key and state memory in the module before encryp-
tion/ decryption is started. It takes 375 Peripheral clock cycles before the encryption/decryption
is done. The encrypted/encrypted data can then be read out, and an optional interrupt can be
generated. The AES Crypto Module also has DMA support with transfer triggers when encryp-
tion/decryption is done and optional auto-start of encryption/decryption when the state memory
is fully loaded.
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26. CRC - Cyclic Redundancy Check Generator
26.1 Features
• Cyclic Redundancy Check (CRC) Generation and Checking for
– Communication Data
– Program or Data in Flash memory
– Data in SRAM memory and I/O memory space
• Integrated with Flash memory, DMA Controller and CPU
– Continuous CRC on data going through a DMA Channel
– Automatic CRC of the complete, or selectable range of the Flash memory
– CPU can load data to CRC Generator through I/O interface
• CRC polynomial software selectable to
– CRC-16 (CRC-CCITT)
– CRC-32 (IEEE 802.3)
• Zero remainder detection
26.2 Overview
A Cyclic Redundancy Check (CRC) is a test algorithm used to detect accidental errors on data,
and is commonly used to determine the correctness of a data transmission, data memory and
program memory. A CRC takes a data stream or block of data as input and generates a 16- or
32-bit output that can be kept with the data and used as checksum. When the same data is later
received or read, the device or application repeats the calculation. If the new CRC calculation
does not match the one calculated earlier, the block contains a data error. The application will
then detect this and may take corrective action such as requesting the data to be sent again.
Typically, an n-bit CRC, applied to a data block of arbitrary length, will detect any single error
burst not longer than n bits (in other words, any single alteration that spans no more than n bits
of the data), and will detect a fraction 1-2-n of all longer error bursts.The CRC module in XMEGA
supports two commonly used CRC polynomials; CRC-16 (CRC-CCITT) and CRC-32
(IEEE 802.3).
• CRC-16:
x16+x12+x5+1
Polynomial:
Hex value:
0x1021
• CRC-32:
x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
Polynomial:
Hex value:
0x04C11DB7
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27. ADC - 12-bit Analog to Digital Converter
27.1 Features
• One Analog to Digital Converter (ADC)
• 12-bit resolution
• Up to 2Million Samples Per Second
– 4 inputs can be sampled within 1.5µs
– Down to 2.5µs conversion time with 8-bit resolution
– Down to 3.5µs conversion time with 12-bit resolution
• Differential and Single-ended input
– Up to 16 single-ended inputs
– 16x4 differential inputs without gain
– 16x4 differential input with gain
• Built in differential gain stage
– 1/2x, 1x, 2x, 4x, 8x, 16x, 32x and 64x gain options
• Single, continues and scan conversion options
• 4 internal inputs
– Internal Temperature sensor
– DAC Output
– VCC voltage divided by 10
– 1.1V Bandgap voltage
• 4 conversion channels with individual input control and result registers
– Enable 4 parallel configurations and results
• Internal and external reference options
• Compare function for accurate monitoring of user defined thresholds
• Optional event triggered conversion for accurate timing
• Optional DMA transfer of conversion results
• Optional interrupt/event on compare result
27.2 Overview
The Analog to Digital Converter (ADC) converts analog signals to digital values. The ADC has
12-bit resolution and is capable of converting up to 2 Million Samples Per Second (MSPS). The
input selection is flexible, and both single-ended and differential measurements can be done.
For differential measurements an optional gain stage is available to increase the dynamic range.
In addition several internal signal inputs are available. The ADC can provide both signed and
unsigned results.
This is a pipelined ADC that consists of several consecutive stages. The pipelined design allows
high sample rate at a low System Clock frequency. It also means that a new input can be sam-
pled and a new ADC conversion started while other ADC conversions are still ongoing. This
remove dependencies between sample rate and propagation delay.
The ADC has four conversion channels (Channel 0-3) with individual input selection, result reg-
isters and conversion start control. The ADC can then keep and use four parallel configurations
and results, and this will ease use for applications with high data throughput or multiple modules
using the ADC independently. It is possible to use DMA to move ADC results directly to memory
or peripherals when conversions are done.
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Both internal and external reference voltages can be used. An integrated temperature sensor is
available for use with the ADC. The output from the DAC, VCC/10 and the Bandgap voltage can
also be measured by the ADC.
The ADC has a compare function for accurate monitoring of user defined thresholds with mini-
mum software intervention required.
Figure 27-1. ADC overview
Compare
Register
Internal
signals
ADC0
•
•
•
<
>
VINP
CH0 Result
CH1 Result
CH2 Result
CH3 Result
ADC15
Threshold
(Int Req)
ADC4
•
½x - 64x
ADC
•
•
ADC7
Int. signals
Internal
signals
VINN
ADC0
•
•
•
Internal 1.00V
Internal VCC/1.6V
Internal VCC/2
AREFA
Reference
Voltage
ADC3
Int. signals
AREFB
Four inputs can be sampled within 1.5µs without any intervention by the application.
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (prop-
agation delay) from 3.5µs for 12-bit to 2.5µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This
eases calculation when the result is represented as a signed integer (signed 16-bit number).
PORTA has one ADC. Notation of this peripheral is ADCA.
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28. DAC - 12-bit Digital to Analog Converter
28.1 Features
• One Digital to Analog Converter (DAC)
• 12-bit resolution
• Two independents and continues-time channels per DAC
• Up to 1Million Samples Per Second conversion rate per DAC channel
• Built in calibration that removes
– Offset error
– Gain error
• Multiple conversion trigger sources
– On new available data
– Events from the Event System
• High drive capabilities and support for
– Resistive load
– Capacitive load
– Combined resistive and capacitive load
• Internal and external reference options
• DAC output available as input to Analog Comparator and ADC
• Low Power mode with reduced drive strength
• Optional DMA transfer of data
28.2 Overview
The Digital to Analog Converter (DAC) converts digital values to voltages. The DAC has two
channels, 12-bit resolution, and is capable of converting 1Million Samples Per Second (MSPS)
on each channels. The built-in calibration system can remove offset and gain error when loaded
with calibration values from software.
Figure 28-1. DAC overview
DMA req
(Data Empty)
D
A
T
12
Output
Driver
CH0DATA
DAC0
A
To
AC/ADC
Int.
driver
Trigger
Select
Enable
CTRLA
Enable
AVCC
Internal 1.00V
AREFA
Reference
selection
CTRLB
Internal Output
enable
AREFB
Trigger
Select
D
A
T
12
Output
Driver
CH1DATA
DAC1
A
DMA req
(Data Empty)
A DAC conversion is automatically started when new data to be converted is available. Event
from the Event System can also be used, and this enable synchronized and timed conversions
between the DAC and other peripherals such as a Timer/Counter. The DMA Controller can be
used to transfer data to the DAC.
The DAC has high drive strengths and is capable of driving both resistive and capacitive loads,
and a load which is a combination of this. A low power mode is available, and this will reduce the
drive strengths of the output. Both internal and external voltage reference can be used. The
DAC output is also internally available for use as input to the Analog Comparator or ADC.
PORTB has one DAC. Notation of this peripheral is DACB.
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29. AC - Analog Comparator
29.1 Features
• Two Analog Comparators
• Selectable propagation delay vs current consumption
• Selectable hysteresis
– No
– Small
– Large
• Analog Comparator output available on pin
• Flexible Input Selection
– All pins on the port
– Output from the DAC
– Bandgap reference voltage.
– A 64-level programmable voltage scaler of the internal VCC voltage
• Interrupt and event generation on
– Rising edge
– Falling edge
– Toggle
• Window function interrupt and event generation on
– Signal above window
– Signal inside window
– Signal below window
• Constant current source with configurable output pin selection
29.2 Overview
The Analog Comparator (AC) compares the voltage level on two inputs and gives a digital output
based on this comparison. The Analog Comparator may be configured to give interrupt requests
and/or events upon several different combinations of input change.
Two important properties of the Analog Comparator when it comes to the dynamic behavior, are
hysteresis and propagation delay. Both these parameters may be adjusted in order to find the
optimal operation for each application.
The input section includes analog port pins, several internal signals and a 64-level programma-
ble voltage scaler. The analog comparator output state can also be directly available on a pin for
use by external devices. Using as pair they can also be set in Window mode to monitor a signal
compared to a voltage window instead of a voltage level.
A constant current source can be enabled, and output on a selectable pin. This can be used to
replace for example external resistors used to charge capacitors in capacitive touch sensing
applications.
The Analog Comparators are always grouped in pairs on each port. They have identical behav-
ior but separate control registers.
PORTA has one AC pair. Notation of this peripheral is ACA.
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Figure 29-1. Analog comparator overview
Pin Input
AC0OUT
Pin Input
Hysteresis
DAC
Enable
Interrupt
Interrupts
Sensititivity
Interrupt
Mode
Control
Voltage
Scaler
ACnMUXCTRL
ACnCTRL
WINCTRL
&
Events
Window
Function
Enable
Bandgap
Hysteresis
Pin Input
AC1OUT
Pin Input
The window function is realized by connecting the external inputs of the two analog comparators
in a pair as shown in Figure 29-2.
Figure 29-2. Analog comparator window function
+
AC0
Upper limit of window
-
Interrupts
Interrupt
Input signal
sensitivity
Events
control
+
AC1
Lower limit of window
-
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30. Programming and Debugging
30.1 Features
• Programming
– External programming through the PDI
Minimal protocol overhead for fast operation
Built in error detection and handling for reliable operation
– Bootloader support for programming through any communication interface
• Debugging
– Non-Intrusive Real-Time On-Chip Debug System
– No software or hardware resources required from device expect pin connection
– Program Flow Control
Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor
– Unlimited Number of User Program Breakpoints
– Unlimited Number of User Data Breakpoints, break on:
Data location read, write or both read and write
Data location content equal or not equal to a value
Data location content is greater or smaller than a value
Data location content is within or outside a range
– No limitation on device clock frequency
• Program and Debug Interface (PDI)
– 2-pin interface for external programming and debugging
– Uses the Reset pin and a dedicated pin
– No I/O pins required during programming or debugging
30.2 Overview
Atmel® AVR® XMEGA® devices together with Atmel’s development tool chain include the neces-
sary functions for efficient development. All external programming and debugging are done
through the Program and Debug Interface (PDI).
The Program and Debug Interface is 2-pin interface that uses the Reset pin and a dedicated pin.
No I/O pins are required during programming or debugging.
In addition to the PDI, programming can also be done through a bootloader. A bootloader in the
device can use any other communication interface such as UART, TWI or SPI to download and
program new application code to the Flash memory.
Debug is supported through a on-chip debug system that offers Non-Intrusive Real-Time debug.
It does not require any software or hardware resources expect for the device expect pin connec-
tion. Using Atmel’s tool chain, it offers complete program flow control and has supported for
unlimited number of program and complex data breakpoints. Application debug can be done
from C and high level language source code level, as well as assembler and disassembler level.
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31. Pinout and Pin Functions
The device pinout is shown in ”Pinout/Block Diagram” on page 3. In addition to general purpose
I/O functionality, each pin can have several alternate functions. This will depend on which
peripheral is enabled and connected to the actual pin. Only one of the pin functions can be used
at time.
31.1 Alternate Pin Functions Description
The tables below shows the notation and description for all pin functions.
Operation/Power Supply
31.1.1
VCC
Digital supply voltage
Analog supply voltage
Ground
AVCC
GND
31.1.2
31.1.3
Port Interrupt functions
SYNC
Port pin with full synchronous and limited asynchronous interrupt function
Port pin with full synchronous and full asynchronous interrupt function
ASYNC
Analog functions
ACn
Analog Comparator input pin n
Analog Comparator n Output
ACnOUT
ADCn
DACn
AREF
Analog to Digital Converter input pin n
Digital to Analog Converter output pin n
Analog Reference input pin
31.1.4
Timer/Counter and AWeX functions
OCnxLS
OCnxHS
Output Compare Channel x Low Side for Timer/Counter n
Output Compare Channel x High Side for Timer/Counter n
51
8387A–AVR–07/11
XMEGA A4U
31.1.5
Communication functions
SCL
SDA
XCKn
RXDn
TXDn
SS
Serial Clock for TWI
Serial Data for TWI
Transfer Clock for USART n
Receiver Data for USART n
Transmitter Data for USART n
Slave Select for SPI
MOSI
MISO
SCK
D-
Master Out Slave In for SPI
Master In Slave Out for SPI
Serial Clock for SPI
Data- for USB
D+
Data+ for USB
31.1.6
Oscillators, Clock and Event
TOSCn
XTALn
Timer Oscillator pin n
Input/Output for Oscillator pin n
Peripheral Clock Output
Event Channel 0 Output
RTC Clock Source Output
CLKOUT
EVOUT
RTCOUT
31.1.7
Debug/System functions
RESET
Reset pin
PDI_CLK
PDI_DATA
Program and Debug Interface Clock pin
Program and Debug Interface Data pin
52
8387A–AVR–07/11
XMEGA A4U
31.2 Alternate Pin Functions
he tables below show the primary/default function for each pin on a port in the first column, the
pin number in the second column, and then all alternate pin functions in the remaining columns.
The head row shows what peripheral that enable and use the alternate pin functions.
For better flexibility, some alternate functions also have selectable pin locations for their func-
tions, this is noted under the the first table where this apply.
Table 31-1. Port A - Alternate functions
PORT A
PIN #
INTERRUPT
ADCA
POS/GAINPOS
ADCA
NEG
ADCA
GAINNEG
ACA
POS
ACA
NEG
ACA
OUT
REFA
GND
AVCC
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
38
39
40
41
42
43
44
1
SYNC
SYNC
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC0
ADC1
ADC2
ADC3
AC0
AC1
AC2
AC3
AC4
AC5
AC6
AC0
AC1
AREF
SYNC/ASYNC
SYNC
AC3
AC5
AC7
SYNC
ADC4
ADC5
ADC6
ADC7
SYNC
2
SYNC
AC1OUT
AC0OUT
3
SYNC
Table 31-2. Port B - Alternate functions
PORT B
PIN #
INTERRUPT
ADCA
DACB
REFB
POS/GAINPOS
PB0
PB1
PB2
PB3
4
5
6
7
SYNC
SYNC
ADC8
AREF
ADC9
SYNC/ASYNC
SYNC
ADC10
DAC0
DAC1
ADC11
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8387A–AVR–07/11
XMEGA A4U
Table 31-3. Port C - Alternate functions
PORT C
GND
VCC
PC0
PIN #
INTERRUPT
TCC0(1)
AWEXC
TCC1
USARTC0(2)
USARTC1
SPIC(3)
TWIC
EVENTOUT(5)
CLOCKOUT(4)
8
9
10
11
12
13
14
15
16
17
SYNC
SYNC
OC0A
OC0B
OC0C
OC0D
OC0ALS
OC0AHS
OC0BLS
OC0BHS
OC0CLS
OC0CHS
OC0DLS
OC0DHS
SDA
SCL
PC1
XCK0
RXD0
TXD0
PC2
SYNC/ASYNC
SYNC
PC3
PC4
SYNC
OC1A
OC1B
SS
PC5
SYNC
XCK1
RXD1
TXD1
MOSI
MISO
SCK
PC6
SYNC
clkRTC
clkPER
PC7
SYNC
EVOUT
Notes: 1. Pin mapping of all TC0 can optionally be moved to high nibble of port.
2. Pin mapping of all USART0 can optionally be moved to high nibble of port.
3. Pins MOSI and SCK for all SPI can optionally be swapped.
4. CLKOUT can optionally be moved between port C, D and E and between pin 4 and 7.
5. EVOUT can optionally be moved between port C, D and E and between pin 4 and 7.
Table 31-4. Port D - Alternate functions
PORT D
GND
VCC
PD0
PIN #
INTERRUPT
TCD0
TCD1
USBD
USARTD0
USARTD1
SPID
CLOCKOUT
EVENTOUT
18
19
20
SYNC
SYNC
OC0A
OC0B
OC0C
OC0D
PD1
21
XCK0
RXD0
TXD0
PD2
22
SYNC/ASYNC
SYNC
PD3
23
PD4
24
SYNC
OC1A
OC1B
SS
PD5
25
SYNC
XCK1
RXD1
TXD1
MOSI
MISO
SCK
PD6
26
SYNC
D-
PD7
27
SYNC
D+
clkPER
EVOUT
Table 31-5. Port E - Alternate functions
PORT E
PIN #
INTERRUPT
TCE0
USARTE0
TWIE
SDA
SCL
PE0
28
SYNC
OC0A
OC0B
PE1
29
SYNC
XCK0
GND
VCC
PE2
30
31
32
SYNC/ASYNC
SYNC
OC0C
OC0D
RXD0
TXD0
PE3
33
54
8387A–AVR–07/11
XMEGA A4U
Table 31-6. Port R- Alternate functions
PORT R
PIN #
INTERRUPT
PDI
XTAL
TOSC(1)
PDI
34
PDI_DATA
PDI_CLOCK
RESET
PRO
35
36
SYNC
SYNC
XTAL2
XTAL1
TOSC2
TOSC1
PR1
37
Note:
1. TOSC pins can optionally be moved to PE2/PE3
55
8387A–AVR–07/11
XMEGA A4U
32. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in XMEGA A4U. For
complete register description and summary for each peripheral module, refer to the XMEGA AU
Manual.
Base Address
Name
Description
0x0000
0x0010
0x0014
0x0018
0x001C
0x0030
0x0040
0x0048
0x0050
0x0060
0x0068
0x0070
0x0078
0x0080
0x0090
0x00A0
0x00B0
0x00C0
0x00D0
0x0100
0x0180
0x01C0
0x0200
0x0240
0x0300
0x0320
0x0380
0x0400
0x0480
0x04A0
0x04C0
0x0600
0x0620
0x0640
0x0660
0x0680
0x07E0
0x0800
0x0840
0x0880
0x0890
0x08A0
0x08B0
0x08C0
0x08F8
0x0900
0x0940
0x0990
0x09A0
0x09B0
0x09C0
0x0A00
0x0A80
0x0A90
0x0AA0
GPIO
General Purpose IO Registers
Virtual Port 0
Virtual Port 1
Virtual Port 2
Virtual Port 3
CPU
Clock Control
Sleep Controller
Oscillator Control
DFLL for the 32MHz Internal Oscillator
DFLL for the 2MHz Internal Oscillator
Power Reduction
Reset Controller
Watch-Dog Timer
MCU Control
Programmable Multilevel Interrupt Controller
Port Configuration
AES Module
CRC Module
VPORT0
VPORT1
VPORT2
VPORT3
CPU
CLK
SLEEP
OSC
DFLLRC32M
DFLLRC2M
PR
RST
WDT
MCU
PMIC
PORTCFG
AES
CRC
DMA
EVSYS
NVM
ADCA
ADCB
DACA
DACB
ACA
RTC
TWIC
TWIE
USB
PORTA
PORTB
PORTC
PORTD
PORTE
PORTR
TCC0
DMA Controller
Event System
Non Volatile Memory (NVM) Controller
Analog to Digital Converter on port A
Analog to Digital Converter on port B
Digital to Analog Converter on port A
Digital to Analog Converter on port B
Analog Comparator pair on port A
Real Time Counter
Two Wire Interface on port C
Two Wire Interface on port E
USB Device
Port A
Port B
Port C
Port D
Port E
Port R
Timer/Counter 0 on port C
Timer/Counter 1 on port C
Advanced Waveform Extension on port C
High Resolution Extension on port C
USART 0 on port C
TCC1
AWEXC
HIRESC
USARTC0
USARTC1
SPIC
IRCOM
TCD0
TCD1
HIRESD
USARTD0
USARTD1
SPID
USART 1 on port C
Serial Peripheral Interface on port C
Infrared Communication Module
Timer/Counter 0 on port D
Timer/Counter 1 on port D
High Resolution Extension on port D
USART 0 on port D
USART 1 on port D
Serial Peripheral Interface on port D
Timer/Counter 0 on port E
Advanced Waveform Extension on port E
High Resolution Extension on port E
USART 0 on port E
TCE0
AWEXE
HIRESE
USARTE0
56
8387A–AVR–07/11
XMEGA A4U
33. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
Arithmetic and Logic Instructions
ADD
ADC
Rd, Rr
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add without Carry
Rd
Rd
Rd
Rd
Rd
Rd
Rd
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
Rd + Rr
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,C,N,V,S
Z,C,N,V,S,H
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
None
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
1/2
Add with Carry
Rd + Rr + C
Rd + 1:Rd + K
Rd - Rr
ADIW
SUB
Add Immediate to Word
Subtract without Carry
Subtract Immediate
Subtract with Carry
Subtract Immediate with Carry
Subtract Immediate from Word
Logical AND
SUBI
SBC
Rd - K
Rd - Rr - C
Rd - K - C
Rd + 1:Rd - K
Rd • Rr
SBCI
SBIW
AND
ANDI
OR
Rd + 1:Rd
Rd
Logical AND with Immediate
Logical OR
Rd
Rd • K
Rd
Rd v Rr
ORI
Logical OR with Immediate
Exclusive OR
Rd
Rd v K
EOR
COM
NEG
SBR
Rd
Rd ⊕ Rr
One’s Complement
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd
$FF - Rd
Rd
Rd
$00 - Rd
Rd,K
Rd,K
Rd
Rd
Rd v K
CBR
INC
Rd
Rd • ($FFh - K)
Rd + 1
Rd
DEC
TST
Rd
Decrement
Rd
Rd - 1
Rd
Test for Zero or Minus
Clear Register
Rd
Rd • Rd
CLR
Rd
Rd
Rd ⊕ Rd
SER
Rd
Set Register
Rd
$FF
MUL
MULS
MULSU
FMUL
FMULS
FMULSU
DES
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
K
Multiply Unsigned
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
Rd x Rr (UU)
Rd x Rr (SS)
Rd x Rr (SU)
Rd x Rr<<1 (UU)
Rd x Rr<<1 (SS)
Rd x Rr<<1 (SU)
Z,C
Multiply Signed
Z,C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Data Encryption
Z,C
Z,C
Z,C
Z,C
if (H = 0) then R15:R0
else if (H = 1) then R15:R0
←
←
Encrypt(R15:R0, K)
Decrypt(R15:R0, K)
Branch Instructions
RJMP
IJMP
k
Relative Jump
PC
←
PC + k + 1
None
None
2
2
Indirect Jump to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
0
EIJMP
Extended Indirect Jump to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
EIND
None
2
JMP
k
k
Jump
PC
PC
←
←
k
None
None
None
3
RCALL
ICALL
Relative Call Subroutine
Indirect Call to (Z)
PC + k + 1
2 / 3(1)
2 / 3(1)
PC(15:0)
PC(21:16)
←
←
Z,
0
EICALL
Extended Indirect Call to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
EIND
None
3(1)
57
8387A–AVR–07/11
XMEGA A4U
Mnemonics
CALL
RET
Operands
Description
Operation
Flags
None
None
I
#Clocks
3 / 4(1)
4 / 5(1)
4 / 5(1)
1 / 2 / 3
1
k
call Subroutine
PC
PC
←
←
←
←
k
Subroutine Return
STACK
STACK
PC + 2 or 3
RETI
Interrupt Return
PC
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC
None
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Rd,Rr
Rd - Rr
CPC
Rd,Rr
Compare with Carry
Rd - Rr - C
1
CPI
Rd,K
Compare with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd - K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b) = 0) PC
if (Rr(b) = 1) PC
if (I/O(A,b) = 0) PC
If (I/O(A,b) =1) PC
if (SREG(s) = 1) then PC
if (SREG(s) = 0) then PC
if (Z = 1) then PC
if (Z = 0) then PC
if (C = 1) then PC
if (C = 0) then PC
if (C = 0) then PC
if (C = 1) then PC
if (N = 1) then PC
if (N = 0) then PC
if (N ⊕ V= 0) then PC
if (N ⊕ V= 1) then PC
if (H = 1) then PC
if (H = 0) then PC
if (T = 1) then PC
if (T = 0) then PC
if (V = 1) then PC
if (V = 0) then PC
if (I = 1) then PC
if (I = 0) then PC
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
1 / 2 / 3
1 / 2 / 3
2 / 3 / 4
2 / 3 / 4
1 / 2
Rr, b
A, b
A, b
s, k
s, k
k
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
1 / 2
1 / 2
k
Branch if Not Equal
1 / 2
k
Branch if Carry Set
1 / 2
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
1 / 2
k
1 / 2
k
1 / 2
k
Branch if Minus
1 / 2
k
Branch if Plus
1 / 2
k
Branch if Greater or Equal, Signed
Branch if Less Than, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
BRID
k
1 / 2
Data Transfer Instructions
MOV
MOVW
LDI
Rd, Rr
Rd, Rr
Rd, K
Rd, k
Copy Register
Rd
Rd+1:Rd
Rd
←
←
←
←
←
Rr
None
None
None
None
None
None
1
Copy Register Pair
Load Immediate
Rr+1:Rr
1
K
1
LDS
LD
Load Direct from data space
Load Indirect
Rd
(k)
(X)
2(1)(2)
1(1)(2)
1(1)(2)
Rd, X
Rd, X+
Rd
LD
Load Indirect and Post-Increment
Rd
X
←
←
(X)
X + 1
LD
Rd, -X
Load Indirect and Pre-Decrement
X ← X - 1,
Rd ← (X)
←
←
X - 1
(X)
None
2(1)(2)
LD
LD
Rd, Y
Load Indirect
Rd ← (Y)
←
(Y)
None
None
1(1)(2)
1(1)(2)
Rd, Y+
Load Indirect and Post-Increment
Rd
Y
←
←
(Y)
Y + 1
58
8387A–AVR–07/11
XMEGA A4U
Mnemonics
Operands
Description
Operation
Flags
#Clocks
LD
Rd, -Y
Load Indirect and Pre-Decrement
Y
Rd
←
←
Y - 1
(Y)
None
2(1)(2)
LDD
LD
Rd, Y+q
Rd, Z
Load Indirect with Displacement
Load Indirect
Rd
Rd
←
←
(Y + q)
(Z)
None
None
None
2(1)(2)
1(1)(2)
1(1)(2)
LD
Rd, Z+
Load Indirect and Post-Increment
Rd
Z
←
←
(Z),
Z+1
LD
Rd, -Z
Load Indirect and Pre-Decrement
Z
Rd
←
←
Z - 1,
(Z)
None
2(1)(2)
LDD
STS
ST
Rd, Z+q
k, Rr
Load Indirect with Displacement
Store Direct to Data Space
Store Indirect
Rd
(k)
(X)
←
←
←
(Z + q)
Rd
None
None
None
None
2(1)(2)
2(1)
X, Rr
Rr
1(1)
ST
X+, Rr
Store Indirect and Post-Increment
(X)
X
←
←
Rr,
X + 1
1(1)
ST
-X, Rr
Store Indirect and Pre-Decrement
X
(X)
←
←
X - 1,
Rr
None
2(1)
ST
ST
Y, Rr
Store Indirect
(Y)
←
Rr
None
None
1(1)
1(1)
Y+, Rr
Store Indirect and Post-Increment
(Y)
Y
←
←
Rr,
Y + 1
ST
-Y, Rr
Store Indirect and Pre-Decrement
Y
(Y)
←
←
Y - 1,
Rr
None
2(1)
STD
ST
Y+q, Rr
Z, Rr
Store Indirect with Displacement
Store Indirect
(Y + q)
(Z)
←
←
Rr
Rr
None
None
None
2(1)
1(1)
1(1)
ST
Z+, Rr
Store Indirect and Post-Increment
(Z)
Z
←
←
Rr
Z + 1
ST
-Z, Rr
Store Indirect and Pre-Decrement
Store Indirect with Displacement
Load Program Memory
Z
(Z + q)
R0
←
←
←
←
Z - 1
Rr
None
None
None
None
None
2(1)
2(1)
3
STD
LPM
LPM
LPM
Z+q,Rr
(Z)
Rd, Z
Load Program Memory
Rd
(Z)
3
Rd, Z+
Load Program Memory and Post-Increment
Rd
Z
←
←
(Z),
Z + 1
3
ELPM
ELPM
ELPM
Extended Load Program Memory
Extended Load Program Memory
R0
Rd
←
←
(RAMPZ:Z)
(RAMPZ:Z)
None
None
None
3
3
3
Rd, Z
Rd, Z+
Extended Load Program Memory and Post-
Increment
Rd
Z
←
←
(RAMPZ:Z),
Z + 1
SPM
SPM
Store Program Memory
(RAMPZ:Z)
←
R1:R0
None
None
-
-
Z+
Store Program Memory and Post-Increment
by 2
(RAMPZ:Z)
Z
←
←
R1:R0,
Z + 2
IN
Rd, A
A, Rr
Rr
In From I/O Location
Out To I/O Location
Rd
I/O(A)
STACK
Rd
←
←
←
←
I/O(A)
Rr
None
None
None
None
None
1
1
OUT
PUSH
POP
XCH
Push Register on Stack
Pop Register from Stack
Exchange RAM location
Rr
1(1)
2(1)
2
Rd
STACK
Z, Rd
Temp
Rd
(Z)
←
←
←
Rd,
(Z),
Temp
LAS
LAC
Z, Rd
Z, Rd
Load and Set RAM location
Load and Clear RAM location
Temp
Rd
(Z)
←
←
←
Rd,
(Z),
Temp v (Z)
None
None
2
2
(Z)
Rd
←
←
($FF – Rd) • (Z)
(Z)
59
8387A–AVR–07/11
XMEGA A4U
Mnemonics
Operands
Description
Operation
Flags
#Clocks
LAT
Z, Rd
Load and Toggle RAM location
(Z)
Rd
←
←
Rd ⊕ (Z)
(Z)
None
2
Bit and Bit-test Instructions
LSL
Rd
Rd
Rd
Rd
Logical Shift Left
Rd(n+1)
Rd(0)
C
←
←
←
Rd(n),
0,
Rd(7)
Z,C,N,V,H
Z,C,N,V
1
1
1
1
LSR
ROL
ROR
Logical Shift Right
Rd(n)
Rd(7)
C
←
←
←
Rd(n+1),
0,
Rd(0)
Rotate Left Through Carry
Rotate Right Through Carry
Rd(0)
Rd(n+1)
C
←
←
←
C,
Rd(n),
Rd(7)
Z,C,N,V,H
Z,C,N,V
Rd(7)
Rd(n)
C
←
←
←
C,
Rd(n+1),
Rd(0)
ASR
SWAP
BSET
BCLR
SBI
Rd
Arithmetic Shift Right
Swap Nibbles
Rd(n)
←
↔
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
Rd(n+1), n=0..6
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rd
Rd(3..0)
Rd(7..4)
None
s
Flag Set
SREG(s)
1
SREG(s)
s
Flag Clear
SREG(s)
0
SREG(s)
A, b
A, b
Rr, b
Rd, b
Set Bit in I/O Register
Clear Bit in I/O Register
Bit Store from Register to T
Bit load from T to Register
Set Carry
I/O(A, b)
1
None
CBI
I/O(A, b)
0
None
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
T
Rr(b)
T
1
T
Rd(b)
C
C
N
N
Z
None
C
C
N
N
Z
Clear Carry
0
Set Negative Flag
1
Clear Negative Flag
Set Zero Flag
0
1
Clear Zero Flag
Z
0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
I
1
I
CLI
I
0
I
SES
CLS
SEV
CLV
SET
CLT
S
1
S
S
V
V
T
S
0
V
1
V
0
T
1
Clear T in SREG
T
0
T
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H
H
1
H
H
0
MCU Control Instructions
BREAK
NOP
Break
(See specific descr. for BREAK)
None
None
None
None
1
1
1
1
No Operation
Sleep
SLEEP
WDR
(see specific descr. for Sleep)
(see specific descr. for WDR)
Watchdog Reset
Notes: 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external
RAM interface.
2. One extra cycle must be added when accessing Internal SRAM.
60
8387A–AVR–07/11
XMEGA A4U
34. Packaging information
34.1 44A
PIN 1 IDENTIFIER
PIN 1
e
B
E1
E
D1
D
C
0°~7°
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
11.75
9.90
11.75
9.90
0.30
0.09
0.45
0.15
1.00
12.00
10.00
12.00
10.00
–
1.05
12.25
D1
E
10.10 Note 2
12.25
Notes:
E1
B
10.10 Note 2
0.45
1. This package conforms to JEDEC reference MS-026, Variation ACB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
C
–
0.20
3. Lead coplanarity is 0.10 mm maximum.
L
–
0.75
e
0.80 TYP
2010-10-20
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
44A, 44-lead, 10 x 10 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
44A
C
R
61
8387A–AVR–07/11
XMEGA A4U
34.2 44M1
D
Marked Pin# 1 ID
E
SEATING PLANE
A1
A3
TOP VIEW
A
K
L
Pin #1 Corner
SIDE VIEW
D2
Pin #1
Triangle
Option A
COMMON DIMENSIONS
(Unit of Measure = mm)
1
2
3
MIN
0.80
–
MAX
1.00
0.05
NOM
0.90
NOTE
SYMBOL
A
E2
Option B
Option C
A1
A3
b
0.02
Pin #1
Chamfer
(C 0.30)
0.20 REF
0.23
0.18
6.90
5.00
6.90
0.30
7.10
5.40
7.10
D
7.00
D2
E
5.20
K
Pin #1
Notch
(0.20 R)
e
b
7.00
E2
e
5.00
5.20
0.50 BSC
0.64
5.40
BOTTOM VIEW
L
0.59
0.20
0.69
0.41
Note: JEDEC Standard MO-220, Fig. 1 (SAW Singulation) VKKD-3.
K
0.26
9/26/08
GPC
ZWS
DRAWING NO.
TITLE
REV.
44M1, 44-pad, 7 x 7 x 1.0 mm Body, Lead
Pitch 0.50 mm, 5.20 mm Exposed Pad,Thermally
Enhanced Plastic Very Thin Quad Flat No
Lead Package (VQFN)
Package Drawing Contact:
packagedrawings@atmel.com
44M1
H
62
8387A–AVR–07/11
XMEGA A4U
34.3 49C2
E
A1 BALL ID
0.10
D
A1
A2
TOP VIEW
A
SIDE VIEW
E1
G
F
e
E
D
C
B
A
D1
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.00
–
NOM
–
NOTE
SYMBOL
A
1
2
3
4
5
6
7
A1
A2
D
0.20
0.65
4.90
–
A1 BALL CORNER
49 - Ø0.35 0.05
b
e
–
–
5.00
5.10
BOTTOM VIEW
D1
E
3.90 BSC
5.00
4.90
0.30
5.10
0.40
E1
b
3.90 BSC
0.35
e
0.65 BSC
3/14/08
GPC
CBD
DRAWING NO.
TITLE
REV.
49C2, 49-ball (7 x 7 Array), 0.65 mm Pitch,
5.0 x 5.0 x 1.0 mm, Very Thin, Fine-Pitch
Ball Grid Array Package (VFBGA)
Package Drawing Contact:
packagedrawings@atmel.com
49C2
A
63
8387A–AVR–07/11
XMEGA A4U
35. Electrical Characteristics
All typical values are measured at T = 25°C unless other temperature condition is given. All min-
imum and maximum values are valid across operating temperature and voltage unless other
conditions are given.
35.1 Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature.................................... -55°C to +85°C
Storage Temperature..................................... -65°C to +150°C
Voltage on any Pin with respect to Ground..-0.5V to VCC+0.5V
Maximum Operating Voltage ............................................ 4.0V
DC Current per I/O Pin ................................................ 20.0mA
DC Current VCC and GND Pins................................. 200.0mA
35.2 DC Characteristics
Table 35-1. Current Consumption for Active and sleep modes
Symbol Parameter
Condition
Min
Typ
50
Max
Units
VCC = 1.8V
32kHz, Ext. Clk
V
CC = 3.0V
CC = 1.8V
CC = 3.0V
CC = 1.8V
130
260
540
460
0.96
9.8
V
V
V
µA
1MHz, Ext. Clk
Active Power
consumption(1)
600
1.4
12
2MHz, Ext. Clk
32MHz, Ext. Clk
32kHz, Ext. Clk
V
CC = 3.0V
CC = 1.8V
mA
µA
ICC
V
2.4
VCC = 3.0V
CC = 1.8V
VCC = 3.0V
3.9
V
62
1MHz, Ext. Clk
2MHz, Ext. Clk
Idle Power
118
125
237
3.8
consumption(1)
VCC = 1.8V
225
350
5.5
1
VCC = 3.0V
32MHz, Ext. Clk
T = 25°C
mA
µA
0.1
VCC = 3.0V
VCC = 3.0V
T = 85°C
1.2
4.5
Power-down power
consumption
WDT and Sampled BOD enabled,
T = 25°C
ICC
1.2
2.4
3
7
WDT and Sampled BOD enabled,
T=85°C
64
8387A–AVR–07/11
XMEGA A4U
Table 35-1. Current Consumption for Active and sleep modes (Continued)
Symbol Parameter
Condition
Min
Typ
1.2
Max
Units
RTC on ULP clock, WDT and
sampled BOD enabled, T = 25°C
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
1.2
0.5
2
2
Power-save power
RTC on 1.024kHz low power
32.768kHz TOSC, T = 25°C
consumption(2)
0.7
ICC
µA
0.9
3
RTC from low power 32.768kHz
TOSC, T = 25°C
1.15
3.5
Current through RESET pin
substracted
Reset power consumption
VCC = 3.0V
320
Module and peripheral power consumption(3)
ULP oscillator
1
27
32.768kHz int. oscillator
85
2MHz int. oscillator
DFLL enabled with 32.768kHz int. osc. as reference
115
270
460
220
0.015
1
32MHz int. oscillator
DFLL enabled with 32.768kHz int. osc. as reference
Multiplication factor = 10x
PLL
µA
Real Time Counter
Watchdog Timer
Continuous mode
138
1.2
BOD
Sampled mode, include ULP oscillator
Internal 1.0V reference
Temperature sensor
100
95
ICC
3.05
2.61
2.16
1.75
1.63
CURRLIMIT = LOW
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
Normal mode
250 kSPS
ADC
VREF = Ext ref
mA
250kSPS’
DAC
AC
VREF = Ext ref
No load
Low Power mode
1.06
High Speed Mode
Low Power Mode
330
130
108
16
DMA
615KBps between I/O registers and SRAM
µA
Timer/Counter
USART
Rx and Tx enabled, 9600 BAUD
2.5
3.6
Flash memory and EEPROM programming
mA
Notes: 1. All Power Reduction Registers set.
2. Maximum limits are based on characterization and not tested in production.
65
8387A–AVR–07/11
XMEGA A4U
3. All parameters measured as the difference in current consumption between module enabled and disabled. All data at
VCC = 3.0V, ClkSYS = 1MHz External clock without prescaling, T = 25°C unless other conditiond are given .
35.3 Operating Voltage and Frequency
Table 35-2. Operating voltage and frequency
Symbol
Parameter
Condition
VCC = 1.6V
CC = 1.8V
Min
0
Typ
Max
12
Units
V
0
12
ClkCPU
CPU clock frequency
MHz
VCC = 2.7V
VCC = 3.6V
0
32
0
32
The maximum System clock frequency of the Atmel® AVR® XMEGA A4U devices is depending
on VCC. As shown in Figure 35-1 on page 66 the Frequency vs. VCC curve is linear between
1.8V < VCC < 2.7V.
Figure 35-1. Maximum Frequency vs. Vcc
MHz
32
Safe Operating Area
12
V
1.6
1.8
2.7
3.6
66
8387A–AVR–07/11
XMEGA A4U
35.4 Wakeup time from sleep
Table 35-3. Device wakeup time from sleep modes with various system clock sources
Symbol Parameter
Condition
External 2MHz clock
Min
Typ
2
Max
Units
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
External 2MHz clock
120
2
Wake-up time from Idle
0.17
2
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
External 2MHz clock
120
2
Wake-up time from Standby
0.17
2
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
External 2MHz clock
120
2
Wake-up time from Extend
Standby
twakeup
µs
0.17
4.5
320
8.8
5
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
External 2MHz clock
Wake-up time from Power-save
Wake-up time from Power-down
4.5
320
8.8
5
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
67
8387A–AVR–07/11
XMEGA A4U
35.5 I/O Pin Characteristics
The I/O pins complies with the JEDEC LVTTL and LVCSMOS specification and the high- and
low level input and output voltage limits reflect or exceed this specification.
Table 35-4. I/O Pin Characteristics
Symbol Parameter
Condition
VCC = 3.0 - 3.6V
CC = 2.3 - 2.7V
Min
2
Typ
Max
VCC+0.3
VCC+0.3
VCC+0.3
0.8
Units
VIH
High Level Input Voltage
V
1.7
VCC = 1.6 - 2.7V
VCC = 3.0 - 3.6V
0.7*VCC
-0.3
-0.3
-0.3
2.4
VIL
Low Level Input Voltage
High Level Output Voltage
Low Level Output Voltage
Output Low Voltage GPIO
Output High Voltage GPIO
VCC = 2.3 - 2.7V
0.7
VCC = 1.6 - 2.7V
VCC = 3.0 - 3.6V
0.2*VCC
IOH = -2mA
IOH = -1mA
IOH = -2mA
IOL = 2mA
IOL = 1mA
IOL = 2mA
IOL = 15mA
IOL = 10mA
IOL = 5mA
IOH = -8mA
IOH = -6mA
IOH = -2mA
3.19
2.43
2.37
0.05
0.03
0.05
0.4
VOH
VOL
VOL
VOH
2.0
V
CC = 2.3 - 2.7V
VCC = 3.0 - 3.6V
CC = 2.3 - 2.7V
1.7
V
0.4
0.4
V
0.7
VCC = 3.3V
CC = 3.0V
0.76
0.64
0.46
V
0.265
0.18
2.86
2.66
1.64
<0.001
<0.001
27
VCC = 1.8V
VCC = 3.3V
2.6
2.1
1.4
VCC = 3.0V
VCC = 1.8V
IIN
IIL
Input Leakage Current I/O pin
Input Leakage Current I/O pin
I/O pin Pull/Buss keeper Resistor
Reset pin Pull-up Resistor
Input hysteresis
0.1
0.1
µA
RP
kΩ
V
RRST
25
0.2
4
tr
Pad rise time
No load
nS
slew rate limitation
7
68
8387A–AVR–07/11
XMEGA A4U
35.6 ADC Characteristics
Table 35-5. ADC Characteristics
Symbol
Parameter
Condition(2)
Min
Typ
Max
Units
RES
Resolution
8
12
12
Bits
ClkADC
cycles
Conversion time (latency)
Sampling Time
(RES+2)/2+(GAIN !=0), RES = 8 or 2
5
8
1/2 ClkADC cycle
0.25
100
5
2000
µS
Max is 1/4 of Peripheral clock frequency
Measuring internal signals
ClkADC
ADC Clock frequency
kHz
100
125
100
2000
CURRLIMIT = LOW
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
100
1500
fADC
Sample rate
kSPS
100
1000
100
500
AVCC
VREF
Rin
Analog supply voltage
Reference voltage
VCC- 0.3
1
VCC+ 0.3
AVCC- 0.6
V
Input resistance
Switched
4.0
4.4
>10
7
kΩ
pF
Cin
Input capacitance
Switched
RAREF
CAREF
Reference input resistance
(leackage only)
MΩ
pF
Reference input capacitance Static load
Start-up time
ADC clock cycles
12
7
24
ClkADC
cycles
After changing reference or input mode
After ADC flush
7
ADC settling time
1
1
Vin
Vin
Input range
-0.1
-VREF
-ΔV
AVCC+ 0.1
Conversion range
Conversion range
Differential mode, Vinp - Vinn
VREF
V
Single ended unsigned mode, Vinp
VREF-ΔV
VCC-1.0V < VREF< VCC-0.6V
500kSPS
1.2
1.5
1.0
1.5
0.8
2
3
INL(1)
Integral non-linearity
V
CC-1.0V < VREF< VCC-0.6V
CC-1.0V < VREF< VCC-0.6V
2
2000kSPS
LSB
3
500kSPS,
guaranteed
monotonic
V
1.2
0.5
0.8
0.5
1.5
1.2
1.5
DNL(1)
Differential non-linearity
Offset Error
2000kSPS, VCC-1.0V < VREF< VCC-0.6V
guaranteed
monotonic
-1
mV
Temperature drift
<0.01
<0.6
mV/K
mV/V
Operating voltage drift
69
8387A–AVR–07/11
XMEGA A4U
Table 35-5. ADC Characteristics (Continued)
Symbol
Parameter
Condition(2)
External reference
AVCC/1.6
Min
Typ
1
Max
Units
10
Differential
mode
mV
AVCC/2.0
8
Gain Error
Bandgap
5
Temperature drift
<0.02
<0.5
mV/K
mV/V
Operating voltage drift
Notes: 1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Table 35-6. ADC Gain Stage Characteristics
Symbol
Rin
Parameter
Condition
Switched in normal mode
Switched in normal mode
Gain stage output
Min
Typ
4.0
4.4
Max
Units
kΩ
pF
Input resistance
Input capacitance
Signal range
Cin
0
VCC- 0.6
V
ClkADC
cycles
Propagation delay
ADC conversion rate
Same as ADC
1
Clock rate
100
1000
4
kHz
INL(1)
Integral Non-Linearity
All gain settings
500kSPS
2.0
0.9
LSB
All gain setting, guaranteed
DNL(1)
Differential Non-Linearity
1.5
monotonic
1x gain, normal mode
8x gain, normal mode
64x gain, normal mode
1x gain, normal mode
8x gain normal mode
64x gain normal mode
-0.8
-2.5
-3.5
-2
Gain Error
%
Offset Error, input
refered
-5
mV
-4
Note:
1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% input voltage range.
70
8387A–AVR–07/11
XMEGA A4U
35.7 DAC Characteristics
Table 35-7. DAC Characteristics
Symbol
RES
Parameter
Condition
Min
1.0
Typ
Max
12
Units
Bits
V
Input Resolution
AVREF
Rchannel
External reference voltage
DC output impedance
V
CC-0.6
50
Ω
Linear output voltage range
Reference input resistance
Reference input capacitance Static load
Minimum Resistance load
0.15
AVCC-0.15
RAREF
CAREF
>10
7
MΩ
pF
kΩ
pF
nF
1
100
Maximum capacitance laod
1000Ω serial resistance
1
AVCC/1000
10
Operating within specification
Safe operation
Output sink/source
mA
Ox
Enable, reset to code
0
VCC = 1.6V
VREF= Ext 1.0V
2.0
1.5
2.0
1.5
3.0
3.0
1.5
3
2.5
4
VCC = 3.6V
VCC = 1.6V
VREF=AVCC
INL(1)
Integral non-linearity
VCC = 3.6V
4
VCC = 1.6V
VREF=INT1V
VCC = 3.6V
VREF=Ext 1.0V, VCC = 1.6V
guaranteed
3
LSB
VCC = 3.6V
VCC = 1.6V
VCC = 3.6V
0.6
1.0
0.6
1.5
3.5
1.5
monotonic
VREF=AVCC,
guaranteed
monotonic
DNL(1)
Differential Non-Linearity
VCC = 1.6V
VCC = 3.6V
3.0
3.0
<4
4
VREF=INT1V
Gain error
After calibration
Gain calibration step size
Gain calibration drift
Offset error
VREF= Ext 1.0V
After calibration
<0.2
<1
1
mV/K
LSB
Offset calibration step size
Fout=Fclk/4,
Cload=100pF,
Max step size
0
0
1000
1000
Fclk
Conversion rate
kSPS
Note:
1. Maximum numbers are based on characterisation and not tested in production, and valid for 5% to 95% output voltage range.
71
8387A–AVR–07/11
XMEGA A4U
35.8 Analog Comparator Characteristics
Table 35-8. Analog Comparator Characteristics
Symbol Parameter
Condition
Min
Typ
< 10
<1000
Max
Units
mV
pA
Voff
Ilk
Input Offset Voltage
Input Leakage Current
Input voltage range
AC startup time
-0.1
AVCC+ 0.1
V
100
0
µs
Vhys1
Vhys2
Hysteresis, None
mode = High Speed (HS)
mode = Low Power (LP)
mode = HS
14
30
30
60
90
95
200
200
0.5
5
Hysteresis, Small
Hysteresis, Large
mV
Vhys3
mode = LP
VCC = 3.0V, T= 85°C mode = HS
mode = HS
100
500
1
tdelay
Propagation delay
ns
VCC = 3.0V, T= 85°C mode = LP
mode = LP
64-Level Voltage Scaler
Integral non-linearity (INL)
LSB
%
Current source accuracy after calibration
Current source calibration range
4
6
µA
35.9 Bandgap and Internal 1.0V Reference Characteristics
Table 35-9. Bandgap and Internal 1.0V Reference Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
As reference for ADC or DAC
As input voltage to ADC and AC
1 ClkPER + 2.5µs
Startup time
µs
1.5
1.1
1
Bandgap voltage
V
INT1V
Internal 1.00V reference
T= 85°C, After calibration
0.99
1.01
Variation over voltage and temperature
0.5
%
72
8387A–AVR–07/11
XMEGA A4U
35.10 Brownout Detection Characteristics
Table 35-10. Brownout Detection Characteristics(1)
Symbol Parameter
Condition
Min
Typ
1.62
1.81
2.01
2.21
2.41
2.61
2.81
3.00
0,4
Max
Units
BOD level 0 falling Vcc
1.62
1.72
BOD level 1 falling Vcc
BOD level 2 falling Vcc
BOD level 3 falling Vcc
V
BOD level 4 falling Vcc
BOD level 5 falling Vcc
BOD level 6 falling Vcc
BOD level 7 falling Vcc
Continous mode
Sampled mode
tBOD
Detection time
µs
%
1000
1.6
VHYST
Hysteresis
Note:
1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level.
35.11 External Reset Characteristics
Table 35-11. External Reset Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
tEXT
Minimum reset pulse width
90
1000
ns
VCC = 2.7 - 3.6V
VCC = 1.6 - 2.7V
0.50*VCC
0.40*VCC
VRST
Reset threshold voltage
V
35.12 Power-on Reset Characteristics
Table 35-12. Power-on Reset Characteristics
Symbol Parameter
Condition
VCC falls faster than 1V/ms
CC falls at 1V/ms or slower
Min
0.4
0.8
Typ
1.0
1.2
1.3
Max
Units
VPOT-
POR threshold voltage falling VCC
POR threshold voltage rising VCC
V
V
VPOT+
1.59
73
8387A–AVR–07/11
XMEGA A4U
35.13 Flash and EEPROM Memory Characteristics
Table 35-13. Endurance and Data Retention
Symbol Parameter
Condition
Min
10K
10K
100
25
Typ
Max
Units
25°C
85°C
25°C
55°C
25°C
85°C
25°C
55°C
Write/Erase cycles
Cycle
Flash
Data retention
Year
Cycle
Year
80K
30K
100
25
Write/Erase cycles
Data retention
EEPROM
Table 35-14. Programming time
Symbol Parameter
Chip Erase
Condition
Min
Typ(1)
50
6
Max
Units
Flash, EEPROM(2) and SRAM Erase
Page Erase
Flash
Page Write
6
Page WriteAutomatic Page Erase and Write
Page Erase
12
6
ms
EEPROM
Page Write
6
Page WriteAutomatic Page Erase and Write
12
Notes: 1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
35.14 Clock and Oscillator Characteristics
35.14.1 Calibrated 32.768kHz Internal Oscillator characteristics
Table 35-15. Calibrated 32.768kHz Internal Oscillator characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
Frequency
32.768
kHz
Factory calibration accuracy
User calibration accuracy
T = 85°C, VCC = 3.0V
-0.5
-0.5
0.5
0.5
%
74
8387A–AVR–07/11
XMEGA A4U
35.14.2 Calibrated 2MHz RC Internal Oscillator characteristics
Table 35-16. Calibrated 2MHz Internal Oscillator characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
DFLL can tune to this frequency over
voltage and temperature
Frequency range
1.8
2.0
2.2
MHz
Factory calibration accuracy
User calibration accuracy
DFLL calibration stepsize
T = 85°C, VCC= 3.0V
-1.5
-0.2
1.5
0.2
%
0.21
35.14.3 Calibrated and tunable 32MHz Internal Oscillator characteristics
Table 35-17. Calibrated 32MHz Internal Oscillator characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
DFLL can tune to this frequency over
voltage and temperature
Frequency range
30
32
55
MHz
Factory calibration accuracy
User calibration accuracy
DFLL calibration step size
T = 85°C, VCC= 3.0V
-1.5
-0.2
1.5
0.2
%
0.22
35.14.4 32kHz Internal ULP Oscillator characteristics
Table 35-18. 32kHz Internal ULP Oscillator characteristics
Symbol Parameter
Output frequency
Condition
Min
Typ
Max
Units
38
kHz
35.14.5 Internal Phase Locked Loop (PLL) characteristics
Table 35-19. Calibrated 32MHz Internal Oscillator characteristics
Symbol Parameter
Condition
Min
0.4
20
Typ
Max
64
Units
fIN
Input Frequnecy
Output frequnecy must be within fOUT
32
MHz
fOUT
Ouput frequnecy (1)
20
128
Start-up time
re-lock time
25
25
µs
1.
The maximum ouput frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than 4 times the
maximum CPU frequency.
75
8387A–AVR–07/11
XMEGA A4U
35.14.6 External 32.768kHz Crystal Oscillator and TOSC characteristics
Table 35-20. External 32.768kHz Crystal Oscillator and TOSC characteristics
Symbol Parameter
Condition
Crystal load capacitance 6.5pF
Crystal load capacitance 9.0pF
Normal mode
Min
Typ
Max
60
Units
Recommended crystal equivalent
series resistance (ESR)
ESR/R1
kΩ
35
4.7
5.2
CIN_TOSC Input capacitance between TOSC pins
pF
Low power mode
capacitance load matched to
crystal specification
Recommended Safety factor
3
Note:
1. See Figure 35-2 on page 76 for definition
Figure 35-2. TOSC input capacitance
CL1
CL2
Device internal
External
TOSC1
TOSC2
32.768 KHz crystal
The input capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal
when oscillating without external capacitors.
35.14.7 External Clock Characteristics
Figure 35-3. External Clock Drive Waveform
tCH
tCH
tCR
tCF
VIH1
VIL1
tCL
tCK
76
8387A–AVR–07/11
XMEGA A4U
Table 35-21. External Clock used as System Clock without prescaling
Symbol Parameter
Condition
Min
0
Typ
Max
12
Units
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
1/tCK
Clock Frequency(1)
MHz
0
32
V
CC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
CC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
83.3
31.5
30.0
12.5
30.0
12.5
tCK
Clock Period
V
tCH
Clock High Time
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
tCL
Clock Low Time
ns
10
3
tCR
Rise Time (for maximum frequency)
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
10
3
tCF
Fall Time (for maximum frequency)
ΔtCK
Change in period from one clock cycle to the next
10
%
Note:
1. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters
with supply voltage conditions.
Table 35-22. External Clock with prescaler(1) for System Clock
Symbol Parameter Condition
Min
0
Typ
Max
90
Units
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
1/tCK
Clock Frequency(2)
MHz
0
142
11
7
tCK
Clock Period
V
V
V
CC = 1.6 - 1.8V
CC = 2.7 - 3.6V
CC = 1.6 - 1.8V
4.5
2.4
4.5
2.4
tCH
Clock High Time
Clock Low Time
ns
%
tCL
VCC = 2.7 - 3.6V
tCR
tCF
Rise Time (for maximum frequency)
1.5
1.5
10
Fall Time (for maximum frequency)
ΔtCK
Change in period from one clock cycle to the next
Notes: 1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters
with supply voltage conditions
77
8387A–AVR–07/11
XMEGA A4U
35.15 SPI Characteristics
Figure 35-4. SPI Interface Requirements in Master mode
SS
tMOS
tSCKR
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
tMIH
tSCK
MISO
(Data Input)
MSB
LSB
tMOH
tMOH
MOSI
(Data Output)
MSB
LSB
Figure 35-5. SPI Timing Requirements in Slave mode
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
tSIH
tSSCK
MOSI
(Data Input)
MSB
LSB
tSOSSS
tSOS
tSOSSH
MISO
(Data Output)
MSB
LSB
78
8387A–AVR–07/11
XMEGA A4U
Table 35-23. SPI Timing Characteristics and Requirements
Symbol Parameter
Condition
Min
Typ
Max
Units
(See Table 21-4 in
XMEGA AU Manual)
tSCK
SCK Period
Master
tSCKW
tSCKR
tSCKF
tMIS
SCK high/low width
SCK Rise time
Master
Master
Master
Master
Master
Master
Master
0.5*SCK
2.7
2.7
SCK Fall time
MISO setup to SCK
MISO hold after SCK
MOSI setup SCK
MOSI hold after SCK
10
tMIH
10
tMOS
tMOH
0.5*SCK
1
tSSCK
tSSCKW
tSSCKR
tSSCKF
tSIS
Slave SCK Period
SCK high/low width
SCK Rise time
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
4*t ClkPER
2*t ClkPER
ns
1600
1600
SCK Fall time
MOSI setup to SCK
MOSI hold after SCK
SS setup to SCK
3
t ClkPER
21
tSIH
tSSS
tSSH
SS hold after SCK
MISO setup SCK
20
tSOS
8
13
11
8
tSOH
MISO hold after SCK
MISO setup after SS low
MISO hold after SS high
tSOSS
tSOSH
79
8387A–AVR–07/11
XMEGA A4U
35.16 Two-Wire Interface Characteristics
Table 2-1 describes the requirements for devices connected to the Two Wire Serial Bus. The
XMEGA Two-Wire Interface meets or exceeds these requirements under the noted conditions.
Timing symbols refer to Figure 35-6.
Figure 35-6. Two-Wire Interface Bus Timing
tof
tHIGH
tLOW
tr
SCL
SDA
tHD;DAT
tSU;STA
tSU;STO
tSU;DAT
tHD;STA
tBUF
Table 35-24. Two Wire Serial Bus Characteristics
Unit
s
Symbol Parameter
Condition
Min
Typ
Max
VIH
VIL
Vhys
VOL
tr
Input High Voltage
0.7VCC
0.5
VCC+0.5
0.3*VCC
Input Low Voltage
V
(1)
Hysteresis of Schmitt Trigger Inputs
Output Low Voltage
0.05VCC
3mA, sink current
0
20+0.1Cb
20+0.1Cb
0
0.4
300
250
50
(1)(2)
(1)(2)
Rise Time for both SDA and SCL
Output Fall Time from VIHmin to VILmax
Spikes Suppressed by Input Filter
Input Current for each I/O Pin
Capacitance for each I/O Pin
SCL Clock Frequency
tof
10pF < Cb < 400pF(2)
0.1VCC < VI < 0.9VCC
ns
tSP
II
-10
10
µA
pF
CI
10
fSCL
fPER(3)>max(10fSCL, 250kHz)
fSCL ≤ 100kHz
0
400
kHz
VCC – 0.4V
----------------------------
3mA
300ms
Cb
----------------
RP
Value of Pull-up resistor
Ω
fSCL > 100kHz
fSCL ≤ 100kHz
4.0
0.6
4.7
1.3
4.0
0.6
tHD;STA
Hold Time (repeated) START condition
Low Period of SCL Clock
fSCL > 100kHz
fSCL ≤ 100kHz
tLOW
f
SCL > 100kHz
µs
fSCL ≤ 100kHz
fSCL > 100kHz
fSCL ≤ 100kHz
fSCL > 100kHz
tHIGH
High Period of SCL Clock
tSU;STA
Set-up time for a repeated START condition
80
8387A–AVR–07/11
XMEGA A4U
Table 35-24. Two Wire Serial Bus Characteristics (Continued)
Unit
Symbol Parameter
Condition
fSCL ≤ 100kHz
SCL > 100kHz
fSCL ≤ 100kHz
SCL > 100kHz
Min
0
Typ
Max
3.45
0.9
s
tHD;DAT
tSU;DAT
tSU;STO
tBUF
Data hold time
f
0
250
100
4.0
0.6
4.7
1.3
Data setup time
f
µs
fSCL ≤ 100kHz
fSCL > 100kHz
fSCL ≤ 100kHz
fSCL > 100kHz
Setup time for STOP condition
Bus free time between a STOP and START
condition
Notes: 1. Required only for fSCL > 100kHz
2. Cb = Capacitance of one bus line in pF
3. fPER = Peripheral clock frequency
81
8387A–AVR–07/11
XMEGA A4U
36. Typical Characteristics
36.1 Active Supply Current
Figure 36-1. Active Supply Current vs. Frequency
fSYS = 0 - 1.0MHz External clock, T = 25°C
700
600
500
400
300
200
100
0
3.3V
3.0V
2.7V
2.2V
1.8V
0
0.2
0.4
0.6
0.8
1
Frequency [MHz]
Figure 36-2. Active supply current vs. frequency
fSYS = 1 - 32MHz External clock, T = 25°C
12
10
8
3.3V
3.0V
2.7V
6
2.2V
4
1.8V
2
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
82
8387A–AVR–07/11
XMEGA A4U
Figure 36-3. Active Supply Current vs. Vcc
fSYS = 1.0MHz External Clock
0.8
0.7
0.6
0.5
0.4
0.3
0.2
-40°C
25°C
85°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 36-4. Active Supply Current vs. VCC
fSYS = 2.0MHz internal oscillator
1.5
1.4
1.3
1.2
1.1
1.0
0.9
0.8
0.7
0.6
0.5
0.4
-40°C
25°C
85°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
83
8387A–AVR–07/11
XMEGA A4U
36.2 Idle Supply Current
Figure 36-5. Idle Supply Current vs. Frequency
fSYS = 0 - 1.0MHz, T = 25°C
140
120
100
80
3.3V
3.0V
2.7V
2.2V
1.8V
60
40
20
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
Figure 36-6. Idle Supply Current vs. Frequency
fSYS = 1 - 32MHz, T = 25°C
4.5
4.0
3.5
3.0
2.5
2.0
1.5
3.3V
3.0V
2.7V
2.2V
1.0
1.8V
0.5
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
84
8387A–AVR–07/11
XMEGA A4U
Figure 36-7. Idle Supply Current vs. Vcc
fSYS = 32.768kHz internal oscillator
33
32
31
30
29
28
27
-40°C
85°C
25°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 36-8. Idle Supply Current vs. Vcc
fSYS = 1.0MHz internal oscillator
160
150
140
130
120
110
100
90
85 °C
25 °C
-40 °C
80
70
60
50
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
85
8387A–AVR–07/11
XMEGA A4U
Figure 36-9. Idle Supply Current vs. Vcc
fSYS = 2.0MHz internal oscillator
410
380
350
320
290
260
230
200
170
-40°C
25°C
85°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 36-10. Idle Supply Current vs. Vcc
fSYS = 32MHz internal oscillator
5.6
5.4
5.2
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
-40°C
25°C
85°C
2.7
2.8
2.9
3
3.1
3.2
CC [V]
3.3
3.4
3.5
3.6
V
86
8387A–AVR–07/11
XMEGA A4U
Figure 36-11. Idle Supply Current vs. Vcc
fSYS = 32MHz internal oscillator, prescaled to 8MHz
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
-40 °C
25 °C
85 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
36.3 Power-down Supply Current
Figure 36-12. Power-down Supply Current vs. Temperature
All functions disabled
3.3V
3.0V
2.7V
1.2
1
2.2V
1.8V
0.8
0.6
0.4
0.2
0
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
87
8387A–AVR–07/11
XMEGA A4U
Figure 36-13. Power-down Supply Current vs. Temperature
With WDT and sampled BOD enabled.
2.6
2.3
2
3.3V
3.0V
2.7V
2.2V
1.8V
1.7
1.4
1.1
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
36.4 Pin Pull-up
Figure 36-14. Reset and I/O Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
70
60
50
40
30
20
10
0
-40 °C
25 °C
85 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
V
RESET [V]
88
8387A–AVR–07/11
XMEGA A4U
Figure 36-15. Reset and I/O Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V
120
108
96
84
72
60
48
36
24
12
0
-40 °C
25 °C
85 °C
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
VRESET [V]
Figure 36-16. Reset and I/O Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V
130
117
104
91
78
65
52
39
26
13
0
-40 °C
25 °C
85 °C
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
V
RESET [V]
89
8387A–AVR–07/11
XMEGA A4U
36.5 Pin Output Voltage vs. Sink/Source Current
Figure 36-17. I/O Pin Output Voltage vs. Source Current
Vcc = 1.8V
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
0
-1
85 °C
25 °C
-20 °C
-2
-3
-4
-5
-6
-7
-8
-9
-10
V
PIN [V]
Figure 36-18. I/O Pin Output Voltage vs. Source Current
Vcc = 3.0V
1.5
1.65
1.8
1.95
2.1
2.25
2.4
2.55
2.7
2.85
3
0
-2
85 °C
25 °C
-40 °C
-4
-6
-8
-10
-12
-14
-16
-18
-20
VPIN [V]
90
8387A–AVR–07/11
XMEGA A4U
Figure 36-19. I/O Pin Output Voltage vs. Source Current
Vcc = 3.3V
1.8
1.95
2.1
2.25
2.4
2.55
2.7
2.85
3
3.15
3.3
0
-2
85 °C
25 °C
-40 °C
-4
-6
-8
-10
-12
-14
-16
-18
-20
V
PIN [V]
Figure 36-20. I/O Pin Output Voltage vs. Source Current
T = 25°C
3.6
3.3
3
3.6 V
3.3 V
2.7 V
2.7
2.4
2.1
1.8
1.5
1.2
0.9
0.6
0.3
0
2.2 V
1.8 V
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
I
PIN [mA]
91
8387A–AVR–07/11
XMEGA A4U
Figure 36-21. I/O Pin Output Voltage vs. Sink Current
Vcc = 1.8V
2.75
2.5
2.25
2
85°C
20°C
1.75
1.5
1.25
1
-40°C
0.75
0.5
0.25
0
0
2.5
5
7.5
10
12.5
15
17.5
20
IPIN [mA]
Figure 36-22. I/O Pin Output Voltage vs. Sink Current
T= 25°C
2
1.8
1.6
1.4
1.2
1
1.8 V
2.2 V
2.7 V
3.3 V
0.8
0.6
0.4
0.2
0
3.6 V
0
2
4
6
8
10
12
14
16
18
20
I
PIN [mA]
92
8387A–AVR–07/11
XMEGA A4U
Figure 36-23. I/O Pin Sink Current vs. Output Voltage
Vcc = 3.0V
20
18
16
14
12
10
8
-20 °C
25 °C
85 °C
6
4
2
0
0
0.05
0.1
0.15
0.2
0.25
0.3
0.35
0.4
0.45
0.5
VPIN [V]
Figure 36-24. I/O Pin Sink Current vs. Output Voltage
Vcc = 3.3V
22
20
18
16
14
12
10
8
-20 °C
25 °C
85 °C
6
4
2
0
0
0.05
0.1
0.15
0.2
0.25
PIN [V]
0.3
0.35
0.4
0.45
0.5
V
93
8387A–AVR–07/11
XMEGA A4U
36.6 Pin Thresholds and Hysteresis
Figure 36-25. I/O Pin Input Threshold Voltage vs. VCC
T = 25°C
1.85
1.7
VIH
VIL
1.55
1.4
1.25
1.1
0.95
0.8
0.65
0.5
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 36-26. I/O Pin Input Hysteresis vs. VCC
T = 25°C
0.315
0.3
0.285
0.27
0.255
0.24
0.225
0.21
0.195
0.18
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
94
8387A–AVR–07/11
XMEGA A4U
Figure 36-27. Reset Input Threshold Voltage vs. VCC
VIH - I/O Pin Read as “1”
-40°C
25°C
85°C
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 36-28. Reset Input Threshold Voltage vs. VCC
VIL - I/O Pin Read as “0”
-40°C
25°C
85°C
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
0.6
0.5
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
95
8387A–AVR–07/11
XMEGA A4U
36.7 Bod characteristics
Figure 36-29. BOD Thresholds vs. Temperature
BOD Level = 1.6V
1.629
1.626
1.623
1.62
Rising Vcc
Falling Vcc
1.617
1.614
1.611
1.608
1.605
1.602
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
Figure 36-30. BOD Thresholds vs. Temperature
BOD Level = 2.6V
2.648
2.642
2.636
2.63
Rising Vcc
2.624
2.618
2.612
2.606
2.6
Falling Vcc
2.594
2.588
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
96
8387A–AVR–07/11
XMEGA A4U
36.8 Oscillators
36.8.1
Internal 1kHz Oscillator
Figure 36-31. 1kHz Ouput from Internal ULP Oscillator Frequency vs. Temperature
1.17
1.16
1.15
1.14
1.13
1.12
1.11
1.1
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.09
25
30
35
40
45
50
55
60
65
70
75
80
85
Temperature [°C]
36.8.2
32.768kHz Internal Oscillator
Figure 36-32. 32.768kHz Internal Oscillator Frequency vs. Temperature
1.8V
2.2V
2.7V
3.3V
3.0V
32.81
32.79
32.77
32.75
32.73
32.71
32.69
32.67
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
97
8387A–AVR–07/11
XMEGA A4U
36.8.3
2MHz Internal Oscillator
Figure 36-33. 2MHz Internal Oscillator CALA Calibration Step Size
VCC = 3V
0.32 %
0.29 %
0.26 %
0.23 %
0.20 %
0.17 %
0.14 %
-40°C
25°C
85°C
0
10
20
30
40
50
60
70
80
90 100 110 120 130
CALA
Figure 36-34. 2MHz Internal Oscillator Frequency vs. Temperature
2.15
2.14
2.13
2.12
2.11
2.1
2.09
2.08
2.07
2.06
2.05
2.04
2.03
2.02
2.01
2
3.3V
3.0V
2.7V
2.2V
1.8V
1.99
1.98
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
98
8387A–AVR–07/11
XMEGA A4U
Figure 36-35. 2MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from 32.768kHz internal oscillator
2.005
2.004
2.003
2.002
2.001
2
2.7V
2.2V
3.3V
3.0V
1.8V
1.999
1.998
1.997
1.996
1.995
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
36.8.4
32MHZ Internal Oscillator
Figure 36-36. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
35.7
35.2
34.7
34.2
33.7
33.2
32.7
32.2
31.7
3.3V
3.0V
2.7V
2.2V
1.8V
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
99
8387A–AVR–07/11
XMEGA A4U
Figure 36-37. 32MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from 32.768kHz internal oscillator
2.2V
3.0V
2.7V
1.8V
32.06
32.04
32.02
32
3.3V
31.98
31.96
31.94
31.92
31.9
31.88
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
Figure 36-38. 32MHz Internal Oscillator CALA Calibration Step Size
VCC = 3.0V
0.36 %
0.34 %
0.32 %
0.30 %
0.28 %
0.26 %
0.24 %
0.22 %
0.20 %
0.18 %
0.16 %
0.14 %
0.12 %
85°C
25°C
-40°C
0
10
20
30
40
50
60
70
80
90 100 110 120 130
CALA
100
8387A–AVR–07/11
XMEGA A4U
36.8.5
32MHz Internal Oscillator Calibrated to 48MHZ
Figure 36-39. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL disabled
53.5
52.5
51.5
50.5
49.5
48.5
47.5
3.3V
3.0V
2.7V
2.2V
1.8V
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
Figure 36-40. 48MHz Internal Oscillator Frequency vs. Temperature
DFLL enabled, from 32.768kHz internal oscillator
48.08
48.05
48.02
47.99
47.96
47.93
47.9
2.2V
3.3V
1.8V
3.0V
2.7V
47.87
47.84
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
101
8387A–AVR–07/11
XMEGA A4U
36.9 Analog comparator characteristics
Figure 36-41. AC current consumption vs. Vcc
Low-power mode
147
142
137
132
127
122
117
112
85°C
25°C
-40°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 36-42. AC current consumption vs. Vcc
High speed mode
360
350
340
330
320
310
300
290
280
85°C
25°C
-40°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
102
8387A–AVR–07/11
XMEGA A4U
Figure 36-43. Analog comparator hysteresis vs. Vcc
High-speed mode, small hysteresis
19
18
17
16
15
14
13
12
11
10
9
85°C
-40°C
25°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 36-44. Analog comparator hysteresis vs. Vcc
High-speed mode, large hysteresis
40
38
36
34
32
30
28
26
24
22
20
85°C
25°C
-40°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
103
8387A–AVR–07/11
XMEGA A4U
Figure 36-45. Analog comparator propagation delay vs. Vcc
High-speed mode
170
147
124
101
78
85°C
25°C
-40°C
55
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 36-46. Analog comparator propagation delay vs. temperature
High-speed mode.
170
147
124
101
78
1.6V
2.7V
3.6V
55
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
104
8387A–AVR–07/11
XMEGA A4U
Figure 36-47. Analog comparator propagation delay vs. temperature
Low-power mode
260
250
240
230
220
210
200
190
180
170
1.6V
2.7V
3.6V
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
36.10 ADC characteristics
Figure 36-48. Gain Error vs. External VREF
T = 25°C, VCC = 3.6V, ADC sampling speed = 500kSPS
3
2
Single-ended Signed
Differential Mode
1
0
-1
-2
-3
-4
Single-ended Unsigned
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF
105
8387A–AVR–07/11
XMEGA A4U
Figure 36-49. Gain Error vs. VCC
T = 25°C, VREF= External 1.0V, ADC sampling speed = 500kSPS
2.2
1.9
1.6
1.3
1
Single-ended Signed
Differential Mode
0.7
0.4
0.1
-0.2
-0.5
Single-ended Unsigned
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
2.6
3.4
3.6
VCC [V]
Figure 36-50. Offset Error vs. External VREF
T = 25°C, VCC = 3.6V, ADC sampling speed = 500kSPS
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.8
3
-1
-1.1
-1.2
-1.3
-1.4
-1.5
-1.6
-1.7
-1.8
-1.9
-2
Differential Mode
VREF [V]
106
8387A–AVR–07/11
XMEGA A4U
Figure 36-51. Offset Error vs. VCC
T = 25°C, VREF = External 1.0V, ADC sampling rate = 500kSPS.
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
-0.3
-0.4
-0.5
-0.6
-0.7
-0.8
-0.9
-1
Differential Mode
-1.1
-1.2
VCC [V]
Figure 36-52. Gain Error vs. Temperature
VCC = 3.0V, VREF = External 2.0V
3
2
Single-ended Signed
Differential Mode
1
0
-1
-2
-3
-4
Single-ended Unsigned
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [ºC]
107
8387A–AVR–07/11
XMEGA A4U
Figure 36-53. INL error vs. External VREF
T = 25°C, VCC = 3.6V.
1.8
1.7
1.6
1.5
Differential Mode
Single-ended Unsigned
1.4
1.3
1.2
1.1
1
0.9
0.8
0.7
Single-ended Signed
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
Figure 36-54. DNL error vs. External VREF
T = 25°C, VCC = 3.6V
0.9
0.88
0.86
Differential Mode
0.84
0.82
0.8
Single-ended Signed
0.78
0.76
0.74
0.72
Single-ended Unsigned
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
108
8387A–AVR–07/11
XMEGA A4U
Figure 36-55. INL error vs. Sample Rate
T = 25°C, VCC = 3.6V, VREF = 3.0V External Reference.
1.4
1.35
1.3
Differential Mode
1.25
1.2
Single-ended Unsigned
1.15
1.1
1.05
1
Single-ended Signed
0.95
0.9
500
650
800
950
1100
1250
1400
1550
1700
1850
2000
ADC Sample Rate [kSPS]
Figure 36-56. DNL error vs. Sample Rate
T = 25°C, VCC = 3.6V, VREF = 3.0V External Reference.
0.9
0.89
0.88
0.87
0.86
0.85
0.84
0.83
0.82
0.81
0.8
Differential Mode
Single-ended Signed
Single-ended Unsigned
0.79
500
650
800
950
1100
1250
1400
1550
1700
1850
2000
ADC Sample Rate [kSPS]
109
8387A–AVR–07/11
XMEGA A4U
36.11 DAC characteristics
Figure 36-57. DNL error vs. External VREF
VCC = 3.6V
0.9
0.85
0.8
0.75
0.7
0.65
0.6
25ºC
1.6
1.8
2
2.2
2.4
VREF [V]
2.6
2.8
3
Figure 36-58. INL error vs. External VREF
VCC = 3.6V
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
25ºC
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
110
8387A–AVR–07/11
XMEGA A4U
36.12 PDI characteristics
Figure 36-59. Maximum PDI speed vs. Vcc
32
29.5
27
25°C
-40°C
85°C
24.5
22
19.5
17
14.5
12
1.6
1.85
2.1
2.35
2.6
2.85
3.1
3.35
3.6
VCC [V]
36.13 Power-on reset characteristics
Figure 36-60. Power-on reset threshold vs. temperature.
1.295
1.285
Rising Vcc
1.275
Falling Vcc
1.265
1.255
1.245
-45 -35 -25 -15 -5
5
15
25 35 45 55 65 75 85
Temperature [°C]
111
8387A–AVR–07/11
XMEGA A4U
Figure 36-61. Power-on reset current consumption vs. Vcc.
2000
1800
1600
1400
1200
1000
800
-40°C
25°C
85°C
600
400
200
0
1.6 1.7 1.8 1.9
2
2.1 2.2 2.3 2.4 2.5 2.6 2.7 2.8 2.9
VCC [V]
3
3.1 3.2 3.3
36.14 Bandgap and internal 1.0V characteristics
Figure 36-62. Internal 1.0V reference voltage vs. temperature.
1.004
1.002
1
1.8V
2.2V
2.7V
3.2V
3.6V
0.998
0.996
0.994
0.992
0.99
0.988
0.986
-45 -35 -25 -15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
112
8387A–AVR–07/11
XMEGA A4U
36.15 Reset pin characteristics
Figure 36-63. Minimum Reset Pulse vs. Vcc.
130
125
120
115
110
105
100
95
85°C
90
25°C
-40°C
85
80
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
113
8387A–AVR–07/11
XMEGA A4U
37. Errata
37.1 ATxmega16A4U, ATxmega32A4U
37.1.1
rev. E
• CRC fails for Range CRC when end address is the last word address of a flash section
• AWeX fault protection restore is not done correct in Pattern Generation Mode
1. CRC fails for Range CRC when end address is the last word address of a flash section
If boot read lock is enabled, the range CRC cannot end on the last address of the application
section. If application table read lock is enabled, the range CRC cannot end on the last
address before the application table.
Problem fix/Workaround
Ensure that the end address used in Range CRC does not end at the last address before a
section with read lock enabled. Instead, use the dedicated CRC commands for complete
applications sections.
2. AWeX fault protection restore is not done correctly in Pattern Generation Mode
When a fault is detected the OUTOVEN register is cleared, and when fault condition is
cleared, OUTOVEN is restored according to the corresponding enabled DTI channels. For
Common Waveform Channel Mode (CWCM), this has no effect as the OUTOVEN is correct
after restoring from fault. For Pattern Generation Mode (PGM), OUTOVEN should instead
have been restored according to the DTILSBUF register.
Problem fix/Workaround
For CWCM no workaround is required.
For PGM in latched mode, disable the DTI channels before returning from the fault condi-
tion. Then, set correct OUTOVEN value and enable the DTI channels, before the direction
(DIR) register is written to enable the correct outputs again.
For PGM in cycle-by-cycle mode there is no workaround.
37.1.2
rev. A - D
Not sampled.
114
8387A–AVR–07/11
XMEGA A4U
38. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revision in this section are referring to the document revision.
38.1 8387A – 07/11
1.
Initial revision.
115
8387A–AVR–07/11
XMEGA A4U
Table of Contents
Features..................................................................................................... 1
Typical Applications ................................................................................ 1
Ordering Information ............................................................................... 2
Pinout/Block Diagram .............................................................................. 3
1
2
3
Overview ................................................................................................... 5
3.1Block Diagram ...........................................................................................................6
4
Resources ................................................................................................. 7
4.1Recommended reading .............................................................................................7
5
6
Capacitive touch sensing ........................................................................ 7
AVR CPU ................................................................................................... 8
6.1Features ....................................................................................................................8
6.2Overview ...................................................................................................................8
6.3ALU - Arithmetic Logic Unit .......................................................................................9
6.4Program Flow ............................................................................................................9
6.5Register File ..............................................................................................................9
7
Memories ................................................................................................ 10
7.1Features ..................................................................................................................10
7.2Overview .................................................................................................................10
7.3Flash Program Memory ...........................................................................................11
7.4Data Memory ...........................................................................................................11
7.5Production Signature Row .......................................................................................12
7.6User Signature Row ................................................................................................13
7.7Flash and EEPROM Page Size ...............................................................................14
8
9
DMAC - Direct Memory Access Controller .......................................... 15
8.1Features ..................................................................................................................15
8.2Overview .................................................................................................................15
Event System ......................................................................................... 16
9.1Features ..................................................................................................................16
9.2Overview .................................................................................................................16
10 System Clock and Clock options ......................................................... 18
10.1Features ................................................................................................................18
i
8387A–AVR–07/11
XMEGA A4U
10.2Overview ...............................................................................................................18
10.3Clock Options ........................................................................................................19
11 Power Management and Sleep Modes ................................................. 21
11.1Features ................................................................................................................21
11.2Overview ...............................................................................................................21
11.3Sleep Modes .........................................................................................................21
12 System Control and Reset .................................................................... 23
12.1Features ................................................................................................................23
12.2Overview ...............................................................................................................23
12.3Reset Sources .......................................................................................................23
13 WDT - Watchdog Timer ......................................................................... 25
13.1Overview ...............................................................................................................25
14 Interrupts and Programmable Multi-level Interrupt Controller .......... 26
14.1Features ................................................................................................................26
14.2Overview ...............................................................................................................26
14.3Interrupt vectors ....................................................................................................26
15 I/O Ports .................................................................................................. 28
15.1Features ................................................................................................................28
15.2Overview ...............................................................................................................28
15.3Output Driver .........................................................................................................29
15.4Input sensing .........................................................................................................31
15.5Alternate Port Functions ........................................................................................31
16 T/C - 16-bit Timer/Counter ..................................................................... 32
16.1Features ................................................................................................................32
16.2Overview ...............................................................................................................32
17 AWeX - Advanced Waveform Extension .............................................. 34
17.1Features ................................................................................................................34
17.2Overview ...............................................................................................................34
18 Hi-Res - High Resolution Extension ..................................................... 35
18.1Features ................................................................................................................35
18.2Overview ...............................................................................................................35
19 RTC - 16-bit Real-Time Counter ............................................................ 36
19.1Features ................................................................................................................36
ii
8387A–AVR–07/11
XMEGA A4U
19.2Overview ...............................................................................................................36
20 USB - Universal Serial Bus Interface ................................................... 37
20.1Features ................................................................................................................37
20.2Overview ...............................................................................................................37
21 TWI - Two Wire Interface ....................................................................... 39
21.1Features ................................................................................................................39
21.2Overview ...............................................................................................................39
22 SPI - Serial Peripheral Interface ............................................................ 40
22.1Features ................................................................................................................40
22.2Overview ...............................................................................................................40
23 USART ..................................................................................................... 41
23.1Features ................................................................................................................41
23.2Overview ...............................................................................................................41
24 IRCOM - IR Communication Module .................................................... 42
24.1Features ................................................................................................................42
24.2Overview ...............................................................................................................42
25 AES and DES Crypto Engine ................................................................ 43
25.1Features ................................................................................................................43
25.2Overview ...............................................................................................................43
26 CRC - Cyclic Redundancy Check Generator ....................................... 44
26.1Features ................................................................................................................44
26.2Overview ...............................................................................................................44
27 ADC - 12-bit Analog to Digital Converter ............................................. 45
27.1Features ................................................................................................................45
27.2Overview ...............................................................................................................45
28 DAC - 12-bit Digital to Analog Converter ............................................. 47
28.1Features ................................................................................................................47
28.2Overview ...............................................................................................................47
29 AC - Analog Comparator ....................................................................... 48
29.1Features ................................................................................................................48
29.2Overview ...............................................................................................................48
30 Programming and Debugging .............................................................. 50
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XMEGA A4U
30.1Features ................................................................................................................50
30.2Overview ...............................................................................................................50
31 Pinout and Pin Functions ...................................................................... 51
31.1Alternate Pin Functions Description ......................................................................51
31.2Alternate Pin Functions .........................................................................................53
32 Peripheral Module Address Map .......................................................... 56
33 Instruction Set Summary ...................................................................... 57
34 Packaging information .......................................................................... 61
34.144A ........................................................................................................................61
34.244M1 .....................................................................................................................62
34.349C2 ......................................................................................................................63
35 Electrical Characteristics ...................................................................... 64
35.1Absolute Maximum Ratings* .................................................................................64
35.2DC Characteristics ................................................................................................64
35.3Operating Voltage and Frequency ........................................................................66
35.4Wakeup time from sleep ........................................................................................67
35.5I/O Pin Characteristics ...........................................................................................68
35.6ADC Characteristics .............................................................................................69
35.7DAC Characteristics .............................................................................................71
35.8Analog Comparator Characteristics .......................................................................72
35.9Bandgap and Internal 1.0V Reference Characteristics .........................................72
35.10Brownout Detection Characteristics ....................................................................73
35.11External Reset Characteristics ............................................................................73
35.12Power-on Reset Characteristics ..........................................................................73
35.13Flash and EEPROM Memory Characteristics .....................................................74
35.14Clock and Oscillator Characteristics ....................................................................74
35.15SPI Characteristics ..............................................................................................78
35.16Two-Wire Interface Characteristics .....................................................................80
36 Typical Characteristics .......................................................................... 82
36.1Active Supply Current ............................................................................................82
36.2Idle Supply Current ................................................................................................84
36.3Power-down Supply Current .................................................................................87
36.4Pin Pull-up .............................................................................................................88
36.5Pin Output Voltage vs. Sink/Source Current .........................................................90
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36.6Pin Thresholds and Hysteresis ..............................................................................94
36.7Bod characteristics ................................................................................................96
36.8Oscillators ..............................................................................................................97
36.9Analog comparator characteristics ......................................................................102
36.10ADC characteristics ...........................................................................................105
36.11DAC characteristics ...........................................................................................110
36.12PDI characteristics ............................................................................................111
36.13Power-on reset characteristics ..........................................................................111
36.14Bandgap and internal 1.0V characteristics ........................................................112
36.15Reset pin characteristics ...................................................................................113
37 Errata ..................................................................................................... 114
37.1ATxmega16A4U, ATxmega32A4U ......................................................................114
38 Datasheet Revision History ................................................................ 115
38.18387A – 07/11 .....................................................................................................115
Table of Contents....................................................................................... i
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