ATXMEGA64B1 [ATMEL]
8/16-bit Atmel XMEGA B1 Microcontroller; 8位/ 16位爱特梅尔XMEGA微控制器B1
| 型号： | ATXMEGA64B1 |
| 厂家： | 
ATMEL |
| 描述： | 8/16-bit Atmel XMEGA B1 Microcontroller |
| 文件： | 总138页 (文件大小：6465K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
8/16-bit Atmel XMEGA B1 Microcontroller
ATxmega128B1; ATxmega64B1
Features
High-performance, low-power Atmel® AVR® XMEGA® 8/16-bit Microcontroller
Nonvolatile program and data memories
64K - 128KBytes of in-system self-programmable flash
4K - 8KBytes boot section
2KBytes EEPROM
4K - 8KBytes internal SRAM
Peripheral Features
Two-channel DMA controller
Four-channel event system
Three 16-bit timer/counters
Two timer/counters with 4 output compare or input capture channels
One timer/counter with 2 output compare or input capture channels
High resolution extensions one timer/counter
Advanced waveform extension (AWeX) on one timer/counter
Split mode on two timer/counters
One USB device interface
USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant
32 Endpoints with full configuration flexibility
Two USARTs with IrDA support for one USART
AES and DES crypto engine
CRC-16 (CRC-CCITT) and CRC-32 (IEEE® 802.3) generator
One two-wire interface with dual address match (I2C and SMBus compatible)
One serial peripheral interface (SPI)
16-bit Real Time Counter (RTC) with separate oscillator
Liquid Crystal Display
Up to 4x40 segment driver
Built in contrast control
ASCII character mapping
Flexible SWAP of segment and common terminals buses
Two eight-channel, 12-bit, 300 thousand SPS Analog to Digital Converters
Four Analog Comparators with window compare function, and current source
feature
External interrupts on all General Purpose I/O pins
Programmable watchdog timer with separate on-chip ultra low power oscillator
QTouch® library support
Capacitive touch buttons, sliders and wheels
Special microcontroller features
Power-on reset and programmable brown-out detection
Internal and external clock options with PLL
Programmable multilevel interrupt controller
Five sleep modes
Programming and debug interfaces
JTAG (IEEE 1149.1 Compliant) interface, including boundary scan
PDI (Program and Debug Interface)
I/O and Packages
53 Programmable I/O pins
100-lead TQFP
Operating Voltage
1.6 – 3.6V
Operating frequency
0 – 12MHz from 1.6V
0 – 32MHz from 2.7V
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1.
Ordering Information
Flash
EEPROM
(Bytes)
SRAM
(Bytes)
Power
Supply
Ordering Code
ATxmega128B1-AU
ATxmega64B1-AU
(Bytes)
128K + 8K
64K + 4K
Speed (MHz)
Package(1)(2)(3)
Temp
2K
2K
8K
4K
32
1.6 - 3.6V
100A
-40C - 85C
Notes:
1. This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.
2. Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
3. For packaging information, see “Errata” on page 131.
Package Type
100-lead, 14 x 14mm body size, 1.0mm body thickness, 0.5mm lead pitch, thin profile plastic quad flat package (TQFP)
100A
Typical Applications
Industrial control
Factory automation
Building control
Board control
Climate control
RF and ZigBee®
USB connectivity
Sensor control
Optical
Low power battery applications
Power tools
HVAC
Utility metering
White goods
Medical applications
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2.
Pinout/Block Diagram
Figure 2-1. Block diagram and pinout
Power
LCD
Ground
Programming, debug, test
External clock / Crystal pins
General Purpose I/O
Digital function
Analog function / Oscillators
VCC
PC0
1
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
CAPH
CAPL
VLCD
BIAS2
BIAS1
VCC
2
PC1
3
Port B
Port A
Port R
PC2
4
PC3
5
PC4
6
PC5
7
GND
EVENT ROUTING NETWORK
DATA BUS
PC6
8
SEG0
SEG1
SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
SEG8
SEG9
SEG10
SEG11
SEG12
SEG13
SEG14
SEG15
SEG16
SEG17
PC7
9
OSC/CLK
Control
Watchdog
Oscillator
Power
TC0:1
USART0
SPI
TEMPREF
VREF
Supervision
GND
VCC
PD0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
Real Time
Counter
Sleep
Controller
Reset
Controller
TWI
Event System
Controller
Interrupt
Controller
Prog/Debug
Interface
OCD
PD1
USB
PD2
Watchdog
Timer
DMA
Controller
PDI / RESET
PDI
TC0
BUS
Controller
CPU
Crypto / CRC
EEPROM
GND
VCC
PE0
USART0
IRCOM
FLASH
SRAM
DATA BUS
PE1
SEG
LCD Controller
PE2
Port G
Port M
PE3
PE4
PE5
PE6
Note:
1. For full details on pinout and alternate pin functions refer to “Pinout and Pin Functions” on page 52.
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3.
Overview
The Atmel® AVR® XMEGA® is a family of low power, high performance, and peripheral rich 8/16-bit microcontrollers
based on the AVR enhanced RISC architecture. By executing instructions in a single clock cycle, the Atmel AVR XMEGA
devices achieve CPU throughput approaching one million instructions per second (MIPS) per megahertz, allowing the
system designer to optimize power consumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All 32 registers are directly
connected to the arithmetic logic unit (ALU), allowing two independent registers to be accessed in a single instruction,
executed in one clock cycle. The resulting architecture is more code efficient while achieving throughputs many times
faster than conventional single-accumulator or CISC based microcontrollers.
The Atmel AVR XMEGA B1 devices provide the following features: in-system programmable flash with read-while-write
capabilities; internal EEPROM and SRAM; two-channel DMA controller, four-channel event system and programmable
multilevel interrupt controller, 53 general purpose I/O lines, real-time counter (RTC); Liquid Crystal Display supporting up
to 4x40 segment driver, ASCII character mapping and built-in contrast control (LCD); three flexible, 16-bit timer/counters
with compare and PWM channels; two USARTs; one two-wire serial interface (TWI); one full speed USB 2.0 interface;
one serial peripheral interface (SPI); AES and DES cryptographic engine; two 8-channel, 12-bit ADCs with
programmable gain; four analog comparators (ACs) with window mode; programmable watchdog timer with separate
internal oscillator; accurate internal oscillators with PLL and prescaler; and programmable brown-out detection.
The program and debug interface (PDI), a fast, two-pin interface for programming and debugging, is available. The
devices also have an IEEE std. 1149.1 compliant JTAG interface, and this can also be used for on-chip debug and
programming.
The ATx devices have five software selectable power saving modes. The idle mode stops the CPU while allowing the
SRAM, DMA controller, event system, interrupt controller, and all peripherals to continue functioning. The power-down
mode saves the SRAM and register contents, but stops the oscillators, disabling all other functions until the next TWI,
USB resume, or pin-change interrupt, or reset. In power-save mode, the asynchronous real-time counter continues to
run, allowing the application to maintain a timer base while the rest of the device is sleeping. In power-save mode, the
LCD controller is allowed to refresh data to the panel. In standby mode, the external crystal oscillator keeps running while
the rest of the device is sleeping. This allows very fast startup from the external crystal, combined with low power
consumption. In extended standby mode, both the main oscillator and the asynchronous timer continue to run, and the
LCD controller is allowed to refresh data to the panel. To further reduce power consumption, the peripheral clock to each
individual peripheral can optionally be stopped in active mode and idle sleep mode.
Atmel offers a free QTouch® library for embedding capacitive touch buttons, sliders and wheels functionality into AVR
microcontrollers.
The devices are manufactured using Atmel high-density, nonvolatile memory technology. The program flash memory can
be reprogrammed in-system through the PDI or JTAG interfaces. A boot loader running in the device can use any
interface to download the application program to the flash memory. The boot loader software in the boot flash section will
continue to run while the application flash section is updated, providing true read-while-write operation. By combining an
8/16-bit RISC CPU with in-system, self-programmable flash, the Atmel XMEGA B1 is a powerful microcontroller family
that provides a highly flexible and cost effective solution for many embedded applications.
The atmel AVR ATx devices are supported with a full suite of program and system development tools, including C
compilers, macro assemblers, program debugger/simulators, programmers, and evaluation kits.
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3.1
Block Diagram
Figure 3-1. XMEGA B1 Block Diagram
Power
LCD
PR[0..1]
Ground
Programming, debug, test
External clock / Crystal pins
General Purpose I/O
Digital function
Analog function / Oscillators
XTAL1 /
TOSC1
XTAL2 /
TOSC2
Oscillator
Circuits/
Clock
PORT R (2)
Generation
Real Time
Counter
Watchdog
Oscillator
EVENT ROUTING NETWORK
DATA BUS
SRAM
Watchdog
Timer
Event System
Controller
Oscillator
Control
PA[0..7]
PORT A (8)
VCC
GND
Power
Supervision
POR/BOD &
RESET
DMA
Controller
Sleep
Controller
ACA
ADCA
RESET /
PDI_CLK
PDI
Prog/Debug
Controller
BUS Matrix
PDI_DATA
AREFA
VCC/10
Int. Refs.
Tempref
AREFB
JTAG
PORT B
AES
DES
CRC
OCD
LCD POWER[0..4]
COM[0..3]
SEG[0..23]
Interrupt
Controller
CPU
LCD
ADCB
ACB
SEG[31..24] /
PM[0..7]
NVM Controller
PORT M (8)
PORT G (8)
PB[0..7]/
JTAG
PORT B (8)
SEG[39..32] /
PG[0..7]
Flash
EEPROM
DATA BUS
EVENT ROUTING NETWORK
To Clock
Generator
PORT C (8)
PORT D (3)
PORT E (8)
TOSC1
(Alternate)
TOSC2
PE[0..7]
PC[0..7]
PD[0..2]
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4.
Resources
A comprehensive set of development tools, application notes and datasheets are available for download on
http://www.atmel.com/avr.
4.1
Recommended reading
XMEGA B Manual
XMEGA Application Notes
This device data sheet only contains part specific information with a short description of each peripheral and module. The
XMEGA B Manual describes the modules and peripherals in depth. The XMEGA application notes contain example code
and show applied use of the modules and peripherals.
All documentations are available from www.atmel.com/avr.
5.
Capacitive touch sensing
The Atmel QTouch® library provides a simple to use solution to realize touch sensitive interfaces on most Atmel AVR
microcontrollers. The patented charge-transfer signal acquisition offers robust sensing and includes fully debounced
reporting of touch keys and includes Adjacent key suppression® (AKS®) technology for unambiguous detection of key
events. The QTouch library includes support for the QTouch and QMatrix acquisition methods.
Touch sensing can be added to any application by linking the appropriate Atmel QTouch library for the AVR
Microcontroller. This is done by using a simple set of APIs to define the touch channels and sensors, and then calling the
touch sensing API’s to retrieve the channel information and determine the touch sensor states.
The QTouch library is FREE and downloadable from the Atmel website at the following location:
www.atmel.com/qtouchlibrary. For implementation details and other information, refer to the Atmel QTouch library user
guide - also available for download from the Atmel website.
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6.
AVR CPU
6.1
Features
• 8/16-bit, high-performance Atmel AVR RISC CPU
– 142 instructions
– Hardware multiplier
• 32x8-bit registers directly connected to the ALU
• Stack in RAM
• Stack pointer accessible in I/O memory space
• Direct addressing of up to 16MB of program memory and 16MB of data memory
• True 16/24-bit access to 16/24-bit I/O registers
• Efficient support for 8-, 16-, and 32-bit arithmetic
• Configuration change protection of system-critical features
6.2
6.3
Overview
All AVR XMEGA devices use the 8/16-bit AVR CPU. The main function of the CPU is to execute the code and perform all
calculations. The CPU is able to access memories, perform calculations, control peripherals, and execute the program in
the flash memory. Interrupt handling is described in a separate section, refer to “Interrupts and Programmable Multilevel
Interrupt Controller” on page 26.
Architectural Overview
In order to maximize performance and parallelism, the AVR CPU uses a Harvard architecture with separate memories
and buses for program and data. Instructions in the program memory are executed with single-level pipelining. While one
instruction is being executed, the next instruction is pre-fetched from the program memory. This enables instructions to
be executed on every clock cycle. For details of all AVR instructions, refer to http://www.atmel.com/avr.
Figure 6-1. Block Diagram of the AVR CPU architecture.
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed in the ALU. After an arithmetic operation, the status register is
updated to reflect information about the result of the operation.
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The ALU is directly connected to the fast-access register file. The 32 x 8-bit general purpose working registers all have
single clock cycle access time allowing single-cycle arithmetic logic unit (ALU) operation between registers or between a
register and an immediate. Six of the 32 registers can be used as three 16-bit address pointers for program and data
space addressing, enabling efficient address calculations.
The memory spaces are linear. The data memory space and the program memory space are two different memory
spaces.
The data memory space is divided into I/O registers and SRAM. In addition, the EEPROM can be memory mapped in the
data memory.
All I/O status and control registers reside in the lowest 4KB addresses of the data memory. This is referred to as the I/O
memory space. The lowest 64 addresses can be accessed directly, or as the data space locations from 0x00 to 0x3F.
The rest is the extended I/O memory space, ranging from 0x0040 to 0x0FFF. I/O registers here must be accessed as
data space locations using load (LD/LDS/LDD) and store (ST/STS/STD) instructions.
The SRAM holds data. Code execution from SRAM is not supported. It can easily be accessed through the five different
addressing modes supported in the AVR architecture. The first SRAM address is 0x2000.
Data addresses 0x1000 to 0x1FFF are reserved for memory mapping of EEPROM.
The program memory is divided in two sections, the application program section and the boot program section. Both
sections have dedicated lock bits for write and read/write protection. The SPM instruction that is used for self-
programming of the application flash memory must reside in the boot program section. The application section contains
an application table section with separate lock bits for write and read/write protection. The application table section can
be used for save storing of nonvolatile data in the program memory.
6.4
ALU - Arithmetic Logic Unit
The arithmetic logic unit (ALU) supports arithmetic and logic operations between registers or between a constant and a
register. Single-register operations can also be executed. The ALU operates in direct connection with all 32 general
purpose registers. In a single clock cycle, arithmetic operations between general purpose registers or between a register
and an immediate are executed and the result is stored in the register file. After an arithmetic or logic operation, the
status register is updated to reflect information about the result of the operation.
ALU operations are divided into three main categories – arithmetic, logical, and bit functions. Both 8- and 16-bit
arithmetic is supported, and the instruction set allows for efficient implementation of 32-bit aritmetic. The hardware
multiplier supports signed and unsigned multiplication and fractional format.
6.4.1 Hardware Multiplier
The multiplier is capable of multiplying two 8-bit numbers into a 16-bit result. The hardware multiplier supports different
variations of signed and unsigned integer and fractional numbers:
Multiplication of unsigned integers
Multiplication of signed integers
Multiplication of a signed integer with an unsigned integer
Multiplication of unsigned fractional numbers
Multiplication of signed fractional numbers
Multiplication of a signed fractional number with an unsigned one
A multiplication takes two CPU clock cycles.
6.5
Program Flow
After reset, the CPU starts to execute instructions from the lowest address in the flash programmemory ‘0.’ The program
counter (PC) addresses the next instruction to be fetched.
Program flow is provided by conditional and unconditional jump and call instructions capable of addressing the whole
address space directly. Most AVR instructions use a 16-bit word format, while a limited number use a 32-bit format.
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During interrupts and subroutine calls, the return address PC is stored on the stack. The stack is allocated in the general
data SRAM, and consequently the stack size is only limited by the total SRAM size and the usage of the SRAM. After
reset, the stack pointer (SP) points to the highest address in the internal SRAM. The SP is read/write accessible in the
I/O memory space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can easily be
accessed through the five different addressing modes supported in the AVR CPU.
6.6
Status Register
The status register (SREG) contains information about the result of the most recently executed arithmetic or logic
instruction. This information can be used for altering program flow in order to perform conditional operations. Note that
the status register is updated after all ALU operations, as specified in the instruction set reference. This will in many
cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code.
The status register is not automatically stored when entering an interrupt routine nor restored when returning from an
interrupt. This must be handled by software.
The status register is accessible in the I/O memory space.
6.7
Stack and Stack Pointer
The stack is used for storing return addresses after interrupts and subroutine calls. It can also be used for storing
temporary data. The stack pointer (SP) register always points to the top of the stack. It is implemented as two 8-bit
registers that are accessible in the I/O memory space. Data are pushed and popped from the stack using the PUSH and
POP instructions. The stack grows from a higher memory location to a lower memory location. This implies that pushing
data onto the stack decreases the SP, and popping data off the stack increases the SP. The SP is automatically loaded
after reset, and the initial value is the highest address of the internal SRAM. If the SP is changed, it must be set to point
above address 0x2000, and it must be defined before any subroutine calls are executed or before interrupts are enabled.
During interrupts or subroutine calls, the return address is automatically pushed on the stack. The return address can be
two or three bytes, depending on program memory size of the device. For devices with 128KB or less of program
memory, the return address is two bytes, and hence the stack pointer is decremented/incremented by two. For devices
with more than 128KB of program memory, the return address is three bytes, and hence the SP is
decremented/incremented by three. The return address is popped off the stack when returning from interrupts using the
RETI instruction, and from subroutine calls using the RET instruction.
The SP is decremented by one when data are pushed on the stack with the PUSH instruction, and incremented by one
when data is popped off the stack using the POP instruction.
To prevent corruption when updating the stack pointer from software, a write to SPL will automatically disable interrupts
for up to four instructions or until the next I/O memory write.
6.8
Register File
The register file consists of 32 x 8-bit general purpose working registers with single clock cycle access time. The register
file supports the following input/output schemes:
One 8-bit output operand and one 8-bit result input
Two 8-bit output operands and one 8-bit result input
Two 8-bit output operands and one 16-bit result input
One 16-bit output operand and one 16-bit result input
Six of the 32 registers can be used as three 16-bit address register pointers for data space addressing, enabling efficient
address calculations. One of these address pointers can also be used as an address pointer for lookup tables in flash
program memory.
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7.
Memories
7.1
Features
• Flash program memory
– One linear address space
– In-system programmable
– Self-programming and boot loader support
– Application section for application code
– Application table section for application code or data storage
– Boot section for application code or bootloader code
– Separate read/write protection lock bits for all sections
– Built in fast CRC check of a selectable flash program memory section
• Data memory
– One linear address space
– Single-cycle access from CPU
– SRAM
– EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
– I/O memory
Configuration and status registers for all peripherals and modules
4 bit-accessible general purpose registers for global variables or flags
– Bus arbitration
Safe and deterministic handling of priority between CPU, DMA controller, and other bus masters
– Separate buses for SRAM, EEPROM and I/O memory
Simultaneous bus access for CPU and DMA controller
• Production signature row memory for factory programmed data
– ID for each microcontroller device type
– Serial number for each device
– Calibration bytes for factory calibrated peripherals
• User signature row
– One flash page in size
– Can be read and written from software
– Content is kept after chip erase
7.2
Overview
The Atmel AVR architecture has two main memory spaces, the program memory and the data memory. Executable code
can reside only in the program memory, while data can be stored in the program memory and the data memory. The data
memory includes the internal SRAM, and EEPROM for nonvolatile data storage. All memory spaces are linear and
require no memory bank switching. Nonvolatile memory (NVM) spaces can be locked for further write and read/write
operations. This prevents unrestricted access to the application software.
A separate memory section contains the fuse bytes. These are used for configuring important system functions, and can
only be written by an external programmer.
The available memory size configurations are shown in “Ordering Information” on page 2. In addition, each device has a
Flash memory signature row for calibration data, device identification, serial number etc.
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7.3
Flash Program Memory
The Atmel AVR XMEGA devices contain on-chip, in-system reprogrammable flash memory for program storage. The
flash memory can be accessed for read and write from an external programmer through the PDI or from application
software running in the device.
All AVR CPU instructions are 16 or 32 bits wide, and each flash location is 16 bits wide. The flash memory is organized
in two main sections, the application section and the boot loader section. The sizes of the different sections are fixed, but
device-dependent. These two sections have separate lock bits, and can have different levels of protection. The store
program memory (SPM) instruction, which is used to write to the flash from the application software, will only operate
when executed from the boot loader section.
The application section contains an application table section with separate lock settings. This enables safe storage of
nonvolatile data in the program memory.
Figure 7-1. Flash program memory (Hexadecimal address).
Word Address
ATxmega128B1
ATxmega64B1
0
0
Application section (bytes)
(128K/64K)
...
EFFF
F000
/
/
/
/
/
77FF
7800
7FFF
8000
87FF
Application table section (bytes)
(8K/4K)
FFFF
10000
10FFF
Boot section (bytes)
(8K/4K)
7.3.1 Application Section
The Application section is the section of the flash that is used for storing the executable application code. The protection
level for the application section can be selected by the boot lock bits for this section. The application section can not store
any boot loader code since the SPM instruction cannot be executed from the application section.
7.3.2 Application Table Section
The application table section is a part of the application section of the flash memory that can be used for storing data.
The size is identical to the boot loader section. The protection level for the application table section can be selected by
the boot lock bits for this section. The possibilities for different protection levels on the application section and the
application table section enable safe parameter storage in the program memory. If this section is not used for data,
application code can reside here.
7.3.3 Boot Loader Section
While the application section is used for storing the application code, the boot loader software must be located in the boot
loader section because the SPM instruction can only initiate programming when executing from this section. The SPM
instruction can access the entire flash, including the boot loader section itself. The protection level for the boot loader
section can be selected by the boot loader lock bits. If this section is not used for boot loader software, application code
can be stored here.
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7.3.4 Production Signature Row
The production signature row is a separate memory section for factory programmed data. It contains calibration data for
functions such as oscillators and analog modules. Some of the calibration values will be automatically loaded to the
corresponding module or peripheral unit during reset. Other values must be loaded from the signature row and written to
the corresponding peripheral registers from software. For details on calibration conditions, refer to “Electrical
Characteristics” on page 67.
The production signature row also contains an ID that identifies each microcontroller device type and a serial number for
each manufactured device. The serial number consists of the production lot number, wafer number, and wafer
coordinates for the device. The device ID for the available devices is shown in Table 7-1 on page 12.
The production signature row cannot be written or erased, but it can be read from application software and external
programmers.
Table 7-1. Device ID bytes for XMEGA B1 devices.
Device
Device ID bytes
Byte 2
52
Byte 1
96
Byte 0
1E
ATxmega64B1
ATxmega128B1
4D
97
1E
7.3.5 User Signature Row
The user signature row is a separate memory section that is fully accessible (read and write) from application software
and external programmers. It is one flash page in size, and is meant for static user parameter storage, such as calibration
data, custom serial number, identification numbers, random number seeds, etc. This section is not erased by chip erase
commands that erase the flash, and requires a dedicated erase command. This ensures parameter storage during
multiple program/erase operations and on-chip debug sessions.
7.4
Fuses and Lock bits
The fuses are used to configure important system functions, and can only be written from an external programmer. The
application software can read the fuses. The fuses are used to configure reset sources such as brownout detector and
watchdog, startup configuration, JTAG enable, and JTAG user ID.
The lock bits are used to set protection levels for the different flash sections (i.e., if read and/or write access should be
blocked). Lock bits can be written by external programmers and application software, but only to stricter protection levels.
Chip erase is the only way to erase the lock bits. To ensure that flash contents are protected even during chip erase, the
lock bits are erased after the rest of the flash memory has been erased.
An unprogrammed fuse or lock bit will have the value one, while a programmed fuse or lock bit will have the value zero.
Both fuses and lock bits are reprogrammable like the flash program memory.
7.5
Data Memory
The data memory contains the I/O memory, internal SRAM and optionally memory mapped EEPROM. The data memory
is organized as one continuous memory section, see Figure 7-2 on page 13. To simplify development, I/O Memory,
EEPROM and SRAM will always have the same start addresses for all XMEGA devices.
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Figure 7-2. Data memory map (hexadecimal address).
Byte Address
ATxmega128B1
Byte Address
ATxmega64B1
0
0
I/O Registers (4K)
I/O Registers (4KB)
FFF
1000
17FF
FFF
1000
17FF
EEPROM (2K)
RESERVED
EEPROM (2K)
RESERVED
2000
3FFF
2000
2FFF
Internal SRAM (8K)
Internal SRAM (4K)
7.6
7.7
EEPROM
XMEGA B1 devices have EEPROM for nonvolatile data storage. It is either addressable in a separate data space
(default) or memory mapped and accessed in normal data space. The EEPROM supports both byte and page access.
Memory mapped EEPROM allows highly efficient EEPROM reading and EEPROM buffer loading. When doing this,
EEPROM is accessible using load and store instructions. Memory mapped EEPROM will always start at hexadecimal
address 0x1000.
I/O Memory
The status and configuration registers for peripherals and modules, including the CPU, are addressable through I/O
memory locations. All I/O locations can be accessed by the load (LD/LDS/LDD) and store (ST/STS/STD) instructions,
which are used to transfer data between the 32 registers in the register file and the I/O memory. The IN and OUT
instructions can address I/O memory locations in the range of 0x00 to 0x3F directly. In the address range 0x00 - 0x1F,
single-cycle instructions for manipulation and checking of individual bits are available.
The I/O memory address for all peripherals and modules in XMEGA B1 is shown in the “Peripheral Module Address Map”
on page 59.
7.7.1 General Purpose I/O Registers
The lowest 4 I/O memory addresses are reserved as general purpose I/O registers. These registers can be used for
storing global variables and flags, as they are directly bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
7.8
7.9
Data Memory and Bus Arbitration
Since the data memory is organized as four separate sets of memories, the different bus masters (CPU, DMA controller
read and DMA controller write, etc.) can access different memory sections at the same time.
Memory Timing
Read and write access to the I/O memory takes one CPU clock cycle. A write to SRAM takes one cycle, and a read from
SRAM takes two cycles. For burst read (DMA), new data are available every cycle. EEPROM page load (write) takes one
cycle, and three cycles are required for read. For burst read, new data are available every second cycle. Refer to the
instruction summary for more details on instructions and instruction timing.
7.10 Device ID and Revision
Each device has a three-byte device ID. This ID identifies Atmel as the manufacturer of the device and the device type. A
separate register contains the revision number of the device.
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7.11 JTAG Disable
It is possible to disable the JTAG interface from the application software. This will prevent all external JTAG access to the
device until the next device reset or until JTAG is enabled again from the application software. As long as JTAG is
disabled, the I/O pins required for JTAG can be used as normal I/O pins.
7.12 I/O Memory Protection
Some features in the device are regarded as critical for safety in some applications. Due to this, it is possible to lock the
I/O register related to the clock system, the event system, and the advanced waveform extensions. As long as the lock is
enabled, all related I/O registers are locked and they can not be written from the application software. The lock registers
themselves are protected by the configuration change protection mechanism.
7.13 Flash and EEPROM Page Size
The flash program memory and EEPROM data memory are organized in pages. The pages are word accessible for the
flash and byte accessible for the EEPROM.
Table 7-2 on page 14 shows the Flash Program Memory organization. Flash write and erase operations are performed
on one page at a time, while reading the Flash is done one byte at a time. For Flash access the Z-pointer (Z[m:n]) is used
for addressing. The most significant bits in the address (FPAGE) give the page number and the least significant address
bits (FWORD) give the word in the page.
Table 7-2. Number of words and Pages in the Flash.
Devices
PC size
Flash
Page Size
words
FWORD
FPAGE
Application
Boot
No of
pages
No of
pages
bits
bytes
Size
Size
ATxmega64B1
ATxmega128B1
16
17
64K + 4K
128
128
Z[7:1]
Z[8:1]
Z[16:8]
Z[17:9]
64K
128K
256
4K
8K
16
128K + 8K
512
32
Table 7-3 on page 14 shows EEPROM memory organization for the XMEGA B1 devices. EEEPROM write and erase
operations can be performed one page or one byte at a time, while reading the EEPROM is done one byte at a time. For
EEPROM access the NVM address register (ADDR[m:n]) is used for addressing. The most significant bits in the address
(E2PAGE) give the page number and the least significant address bits (E2BYTE) give the byte in the page.
Table 7-3. Number of Bytes and Pages in the EEPROM.
Devices
EEPROM
Size
2K
Page Size
bytes
32
E2BYTE
E2PAGE
No of Pages
ATxmega64B1
ATxmega128B1
ADDR[4:0]
ADDR[4:0]
ADDR[10:5]
ADDR[10:5]
64
64
2K
32
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8.
DMAC – Direct Memory Access Controller
8.1
Features
• Allows high speed data transfers with minimal CPU intervention
– from data memory to data memory
– from data memory to peripheral
– from peripheral to data memory
– from peripheral to peripheral
• Two DMA channels with separate
– transfer triggers
– interrupt vectors
– addressing modes
• Programmable channel priority
• From 1 byte to 16MB of data in a single transaction
– Up to 64KB block transfers with repeat
– 1, 2, 4, or 8 byte burst transfers
• Multiple addressing modes
– Static
– Incremental
– Decremental
• Optional reload of source and destination addresses at the end of each
– Burst
– Block
– Transaction
• Optional interrupt on end of transaction
• Optional connection to CRC generator for CRC on DMA data
8.2
Overview
The two-channel direct memory access (DMA) controller can transfer data between memories and peripherals, and thus
offload these tasks from the CPU. It enables high data transfer rates with minimum CPU intervention, and frees up CPU
time. The four DMA channels enable up to four independent and parallel transfers.
The DMA controller can move data between SRAM and peripherals, between SRAM locations and directly between
peripheral registers. With access to all peripherals, the DMA controller can handle automatic transfer of data to/from
communication modules. The DMA controller can also read from memory mapped EEPROM.
Data transfers are done in continuous bursts of 1, 2, 4, or 8 bytes. They build block transfers of configurable size from 1
byte to 64KB. A repeat counter can be used to repeat each block transfer for single transactions up to 16MB. Source and
destination addressing can be static, incremental or decremental. Automatic reload of source and/or destination
addresses can be done after each burst or block transfer, or when a transaction is complete. Application software,
peripherals, and events can trigger DMA transfers.
The two DMA channels have individual configuration and control settings. This include source, destination, transfer
triggers, and transaction sizes. They have individual interrupt settings. Interrupt requests can be generated when a
transaction is complete or when the DMA controller detects an error on a DMA channel.
To allow for continuous transfers, the channels can be interlinked so that the second takes over the transfer when the
first is finished, and vice versa.
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9.
Event System
9.1
Features
• System for direct peripheral-to-peripheral communication and signaling
• Peripherals can directly send, receive, and react to peripheral events
– CPU and DMA controller independent operation
– 100% predictable signal timing
– Short and guaranteed response time
• Four event channels for up to four different and parallel signal routings and configurations
• Events can be sent and/or used by most peripherals, clock system, and software
• Additional functions include
– Quadrature decoders
– Digital filtering of I/O pin state
• Works in active mode and idle sleep mode
9.2
Overview
The event system enables direct peripheral-to-peripheral communication and signaling. It allows a change in one
peripheral’s state to automatically trigger actions in other peripherals. It is designed to provide a predictable system for
short and predictable response times between peripherals. It allows for autonomous peripheral control and interaction
without the use of interrupts, CPU, or DMA controller resources, and is thus a powerful tool for reducing the complexity,
size and execution time of application code. It also allows for synchronized timing of actions in several peripheral
modules.
A change in a peripheral’s state is referred to as an event, and usually corresponds to the peripheral’s interrupt
conditions. Events can be directly passed to other peripherals using a dedicated routing network called the event routing
network. How events are routed and used by the peripherals is configured in software.
Figure 9-1 on page 17 shows a basic diagram of all connected peripherals. The event system can directly connect
together analog and digital converters, analog comparators, I/O port pins, the real-time counter, timer/counters, IR
communication module (IRCOM), and USB interface. It can also be used to trigger DMA transactions (DMA controller).
Events can also be generated from software and the peripheral clock.
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Figure 9-1. Event system overview and connected peripherals.
CPU /
Software
DMA
Controller
Event Routing Network
clkPER
Prescaler
Real Time
Counter
ADC
AC
Event
System
Controller
Timer /
Counters
USB
Port pins
IRCOM
The event routing network consists of four software-configurable multiplexers that control how events are routed and
used. These are called event channels, and allow for up to four parallel event configurations and routings. The maximum
routing latency is two peripheral clock cycles. The event system works in both active mode and idle sleep mode.
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10. System Clock and Clock options
10.1 Features
• Fast start-up time
• Safe run-time clock switching
• Internal oscillators:
– 32MHz run-time calibrated oscillator
– 2MHz run-time calibrated oscillator
– 32.768kHz calibrated oscillator
– 32kHz ultra low power (ULP) oscillator with 1kHz output
• External clock options
– 0.4MHz - 16MHz crystal oscillator
– 32.768kHz crystal oscillator
– External clock
• PLL with 20MHz - 128MHz output frequency
– Internal and external clock options and 1x to 31x multiplication
– Lock detector
• Clock prescalers with 1x to 2048x division
• Fast peripheral clocks running at 2 and 4 times the CPU clock
• Automatic run-time calibration of internal oscillators
• External oscillator and PLL lock failure detection with optional non-maskable interrupt
10.2 Overview
Atmel AVR XMEGA devices have a flexible clock system supporting a large number of clock sources. It incorporates
both accurate internal oscillators and external crystal oscillator and resonator support. A high-frequency phase locked
loop (PLL) and clock prescalers can be used to generate a wide range of clock frequencies. A calibration feature (DFLL)
is available, and can be used for automatic run-time calibration of the internal oscillators to remove frequency drift over
voltage and temperature. An oscillator failure monitor can be enabled to issue a non-maskable interrupt and switch to the
internal oscillator if the external oscillator or PLL fails.
When a reset occurs, all clock sources except the 32kHz ultra low power oscillator are disabled. After reset, the device
will always start up running from the 2MHz internal oscillator. During normal operation, the system clock source and
prescalers can be changed from software at any time.
Figure 10-1 on page 19 presents the principal clock system in the XMEGA B1 family of divices. Not all of the clocks need
to be active at a given time. The clocks for the CPU and peripherals can be stopped using sleep modes and power
reduction registers, as described in “Power Management and Sleep Modes” on page 21.
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Figure 10-1. The Clock system, clock sources and clock distribution.
Real Time
Counter
Non-Volatile
Memory
LCD
Peripherals
RAM
AVR CPU
clkPER
clkCPU
clkPER2
clkPER4
clkRTC
clkLCD
USB
clkUSB
Prescaler
System Clock Prescalers
clkSYS
Watchdog
Timer
Brown-out
Detector
System Clock Multiplexer
(SCLKSEL)
RTCSRC
USBSRC
PLL
PLLSRC
XOSCSEL
32 kHz
Int. ULP
32.768 kHz
Int. OSC
32.768 kHz
TOSC
0.4 – 16 MHz
XTAL
32 MHz
Int. Osc
2 MHz
Int. Osc
10.3 Clock Sources
The clock sources are divided in two main groups: internal oscillators and external clock sources. Most of the clock
sources can be directly enabled and disabled from software, while others are automatically enabled or disabled,
depending on peripheral settings. After reset, the device starts up running from the 2MHz internal oscillator. The other
clock sources, DFLLs and PLL, are turned off by default.
The internal oscillators do not require any external components to run. For details on characteristics and accuracy of the
internal oscillators, refer to the device datasheet.
10.3.1 32kHz Ultra Low Power Internal Oscillator
This oscillator provides an approximate 32kHz clock. The 32kHz ultra low power (ULP) internal oscillator is a very low
power clock source, and it is not designed for high accuracy.The oscillator employs a built-in prescaler that provides a
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1kHz output. The oscillator is automatically enabled/disabled when it is used as clock source for any part of the device.
This oscillator can be selected as the clock source for the RTC and for LCD.
10.3.2 32.768kHz Calibrated Internal Oscillator
This oscillator provides an approximate 32.768kHz clock. It is calibrated during production to provide a default frequency
close to its nominal frequency. The calibration register can also be written from software for run-time calibration of the
oscillator frequency. The oscillator employs a built-in prescaler, which provides both a 32.768kHz output and a 1.024kHz
output. This oscillator can be used as a clock source for the system clock, RTC and LCD, and as the DFLL reference
clock.
10.3.3 32.768kHz Crystal Oscillator
A 32.768kHz crystal oscillator can be connected between the TOSC1 and TOSC2 pins and enables a dedicated low
frequency oscillator input circuit. A low power mode with reduced voltage swing on TOSC2 is available. This oscillator
can be used as a clock source for the system clock, RTC and LCD, and as the DFLL reference clock.
10.3.4 0.4 - 16MHz Crystal Oscillator
This oscillator can operate in four different modes optimized for different frequency ranges, all within 0.4MHz - 16MHz.
10.3.5 2MHz Run-time Calibrated Internal Oscillator
The 2MHz run-time calibrated internal oscillator is the default system clock source after reset. It is calibrated during
production to provide a default frequency close to its nominal frequency. A DFLL can be enabled for automatic run-time
calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator accuracy.
10.3.6 32MHz Run-time Calibrated Internal Oscillator
The 32MHz run-time calibrated internal oscillator is a high-requency oscillator. It is calibrated during production to
provide a default frequency close to its nominal frequency. A digital frequency looked loop (DFLL) can be enabled for
automatic run-time calibration of the oscillator to compensate for temperature and voltage drift and optimize the oscillator
accuracy. This oscillator can also be adjusted and calibrated to any frequency between 30MHz and 55MHz. The
production signature row contains 48 MHz calibration values intended used when the oscillator is used a full-speed USB
clock source.
10.3.7 External Clock Sources
The XTAL1 and XTAL2 pins can be used to drive an external oscillator, either a quartz crystal or a ceramic resonator.
XTAL1 or each pin of port C can be used as input for an external clock signal. The TOSC1 and TOSC2 pins is dedicated
to driving a 32.768kHz crystal oscillator.
10.3.8 PLL with 1x-31x Multiplication Factor
The built-in phase locked loop (PLL) can be used to generate a high-frequency system clock. The PLL has a user-
selectable multiplication factor of from 1 to 31. In combination with the prescalers, this gives a wide range of output
frequencies from all clock sources.
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11. Power Management and Sleep Modes
11.1 Features
• Power management for adjusting power consumption and functions
• Five sleep modes
– Idle
– Power down
– Power save
– Standby
– Extended standby
• Power reduction register to disable clock and turn off unused peripherals in active and idle modes
11.2 Overview
Various sleep modes and clock gating are provided in order to tailor power consumption to application requirements.
This enables the XMEGA microcontroller to stop unused modules to save power.
All sleep modes are available and can be entered from active mode. In active mode, the CPU is executing application
code. When the device enters sleep mode, program execution is stopped and interrupts or a reset is used to wake the
device again. The application code decides which sleep mode to enter and when. Interrupts from enabled peripherals
and all enabled reset sources can restore the microcontroller from sleep to active mode.
In addition, power reduction registers provide a method to stop the clock to individual peripherals from software. When
this is done, the current state of the peripheral is frozen, and there is no power consumption from that peripheral. This
reduces the power consumption in active mode and idle sleep modes and enables much more fine-tuned power
management than sleep modes alone.
11.3 Sleep Modes
Sleep modes are used to shut down modules and clock domains in the microcontroller in order to save power. XMEGA
microcontrollers have five different sleep modes tuned to match the typical functional stages during application
execution. A dedicated sleep instruction (SLEEP) is available to enter sleep mode. Interrupts are used to wake the
device from sleep, and the available interrupt wake-up sources are dependent on the configured sleep mode. When an
enabled interrupt occurs, the device will wake up and execute the interrupt service routine before continuing normal
program execution from the first instruction after the SLEEP instruction. If other, higher priority interrupts are pending
when the wake-up occurs, their interrupt service routines will be executed according to their priority before the interrupt
service routine for the wake-up interrupt is executed. After wake-up, the CPU is halted for four cycles before execution
starts.
The content of the register file, SRAM and registers are kept during sleep. If a reset occurs during sleep, the device will
reset, start up, and execute from the reset vector.
11.3.1 Idle Mode
In idle mode the CPU and nonvolatile memory are stopped (note that any ongoing programming will be completed), but
all peripherals, including the interrupt controller, event system and DMA controller are kept running. Any enabled
interrupt will wake the device.
11.3.2 Power-down Mode
In power-down mode, all clocks, including the real-time counter clock source, are stopped. This allows operation only of
asynchronous modules that do not require a running clock. The only interrupts that can wake up the MCU are the two-
wire interface address match interrupt, asynchronous port interrupts, and the USB resume interrupt.
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11.3.3 Power-save Mode
Power-save mode is identical to power down, with two exceptions:
1. If the real-time counter (RTC) is enabled, it will keep running during sleep, and the device can also wake up from
either an RTC overflow or compare match interrupt.
2. If the liquid crystal display controller (LCD) is enabled, it will keep running during sleep, and the device can wake
up from LCD frame completed interrupt.
11.3.4 Standby Mode
Standby mode is identical to power down, with the exception that the enabled system clock sources are kept running
while the CPU, peripheral, RTC and LCD clocks are stopped. This reduces the wake-up time.
11.3.5 Extended Standby Mode
Extended standby mode is identical to power-save mode, with the exception that the enabled system clock sources are
kept running while the CPU and peripheral clocks are stopped. This reduces the wake-up time.
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12. System Control and Reset
12.1 Features
• Reset the microcontroller and set it to initial state when a reset source goes active
• Multiple reset sources that cover different situations
– Power-on reset
– External reset
– Watchdog reset
– Brownout reset
– PDI reset
– Software reset
• Asynchronous operation
– No running system clock in the device is required for reset
• Reset status register for reading the reset source from the application code
12.2 Overview
The reset system issues a microcontroller reset and sets the device to its initial state. This is for situations where
operation should not start or continue, such as when the microcontroller operates below its power supply rating. If a reset
source goes active, the device enters and is kept in reset until all reset sources have released their reset. The I/O pins
are immediately tri-stated. The program counter is set to the reset vector location, and all I/O registers are set to their
initial values. The SRAM content is kept. However, if the device accesses the SRAM when a reset occurs, the content of
the accessed location can not be guaranteed.
After reset is released from all reset sources, the default oscillator is started and calibrated before the device starts
running from the reset vector address. By default, this is the lowest program memory address, 0, but it is possible to
move the reset vector to the lowest address in the boot section.
The reset functionality is asynchronous, and so no running system clock is required to reset the device. The software
reset feature makes it possible to issue a controlled system reset from the user software.
The reset status register has individual status flags for each reset source. It is cleared at power-on reset, and shows
which sources have issued a reset since the last power-on.
12.3 Reset Sequence
A reset request from any reset source will immediately reset the device and keep it in reset as long as the request is
active. When all reset requests are released, the device will go through three stages before the device starts running
again:
Reset counter delay
Oscillator startup
Oscillator calibration
If another reset requests occurs during this process, the reset sequence will start over again.
12.4 Reset Sources
12.4.1 Power-on Reset
A power-on reset (POR) is generated by an on-chip detection circuit. The POR is activated when the VCC rises and
reaches the POR threshold voltage (VPOT), and this will start the reset sequence.
The POR is also activated to power down the device properly when the VCC falls and drops below the VPOT level.
The VPOT level is higher for falling VCCthan for rising VCC. Consult the datasheet for POR characteristics data.
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12.4.2 Brownout Detection
The on-chip brownout detection (BOD) circuit monitors the VCC level during operation by comparing it to a fixed,
programmable level that is selected by the BODLEVEL fuses. If disabled, BOD is forced on at the lowest level during chip
erase and when the PDI is enabled.
12.4.3 External Reset
The external reset circuit is connected to the external RESET pin. The external reset will trigger when the RESET pin is
driven below the RESET pin threshold voltage, VRST, for longer than the minimum pulse period, tEXT. The reset will be
held as long as the pin is kept low. The RESET pin includes an internal pull-up resistor.
12.4.4 Watchdog Reset
The watchdog timer (WDT) is a system function for monitoring correct program operation. If the WDT is not reset from
the software within a programmable timout period, a watchdog reset will be given. The watchdog reset is active for one to
two clock cycles of the 2MHz internal oscillator. For more details see “WDT – Watchdog Timer” on page 25.
12.4.5 Software Reset
The software reset makes it possible to issue a system reset from software by writing to the software reset bit in the reset
control register.The reset will be issued within two CPU clock cycles after writing the bit. It is not possible to execute any
instruction from when a software reset is requested until it is issued.
12.4.6 Program and Debug Interface Reset
The program and debug interface reset contains a separate reset source that is used to reset the device during external
programming and debugging. This reset source is accessible only from external debuggers and programmers.
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13. WDT – Watchdog Timer
13.1 Features
• Issues a device reset if the timer is not reset before its timeout period
• Asynchronous operation from dedicated oscillator
• 1kHz output of the 32kHz ultra low power oscillator
• 11 selectable timeout periods, from 8ms to 8s
• Two operation modes:
– Normal mode
– Window mode
• Configuration lock to prevent unwanted changes
13.2 Overview
The watchdog timer (WDT) is a system function for monitoring correct program operation. It makes it possible to recover
from error situations such as runaway or deadlocked code. The WDT is a timer, configured to a predefined timeout
period, and is constantly running when enabled. If the WDT is not reset within the timeout period, it will issue a
microcontroller reset. The WDT is reset by executing the WDR (watchdog timer reset) instruction from the application
code.
The window mode makes it possible to define a time slot or window inside the total timeout period during which WDT
must be reset. If the WDT is reset outside this window, either too early or too late, a system reset will be issued.
Compared to the normal mode, this can also catch situations where a code error causes constant WDR execution.
The WDT will run in active mode and all sleep modes, if enabled. It is asynchronous, runs from a CPU-independent clock
source, and will continue to operate to issue a system reset even if the main clocks fail.
The configuration change protection mechanism ensures that the WDT settings cannot be changed by accident. For
increased safety, a fuse for locking the WDT settings is also available.
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14. Interrupts and Programmable Multilevel Interrupt Controller
14.1 Features
• Short and predictable interrupt response time
• Separate interrupt configuration and vector address for each interrupt
• Programmable multilevel interrupt controller
– Interrupt prioritizing according to level and vector address
– Three selectable interrupt levels for all interrupts: low, medium and high
– Selectable, round-robin priority scheme within low-level interrupts
– Non-maskable interrupts for critical functions
• Interrupt vectors optionally placed in the application section or the boot loader section
14.2 Overview
Interrupts signal a change of state in peripherals, and this can be used to alter program execution. Peripherals can have
one or more interrupts, and all are individually enabled and configured. When an interrupt is enabled and configured, it
will generate an interrupt request when the interrupt condition is present. The programmable multilevel interrupt
controller (PMIC) controls the handling and prioritizing of interrupt requests. When an interrupt request is acknowledged
by the PMIC, the program counter is set to point to the interrupt vector, and the interrupt handler can be executed.
All peripherals can select between three different priority levels for their interrupts: low, medium, and high. Interrupts are
prioritized according to their level and their interrupt vector address. Medium-level interrupts will interrupt low-level
interrupt handlers. High-level interrupts will interrupt both medium- and low-level interrupt handlers. Within each level, the
interrupt priority is decided from the interrupt vector address, where the lowest interrupt vector address has the highest
interrupt priority. Low-level interrupts have an optional round-robin scheduling scheme to ensure that all interrupts are
serviced within a certain amount of time.
Non-maskable interrupts (NMI) are also supported, and can be used for system critical functions.
14.3 Interrupt vectors
The interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for specific interrupts in
each peripheral. The base addresses for the XMEGA B1 devices are shown in Table 14-1. Offset addresses for each
interrupt available in the peripheral are described for each peripheral in the XMEGA B manual. For peripherals or
modules that have only one interrupt, the interrupt vector is shown in Table 14-1. The program address is the word
address.
Table 14-1. Reset and Interrupt Vectors.
Program Address
(Base Address)
0x000
Source
Interrupt Description
RESET
0x002
OSCF_INT_vect
PORTC_INT_base
PORTR_INT_base
DMA_INT_base
RTC_INT_base
TWIC_INT_base
TCC0_INT_base
Crystal Oscillator Failure Interrupt vector (NMI)
Port C Interrupt base
0x004
0x008
Port R Interrupt base
0x00C
DMA Controller Interrupt base
0x014
Real Time Counter Interrupt base
Two-Wire Interface on Port C Interrupt base
Timer/Counter 0 on port C Interrupt base
0x018
0x01C
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Program Address
(Base Address)
Source
Interrupt Description
0x028
0x030
0x032
0x03E
0x046
0x048
0x04A
0x04E
0x052
0x058
0x060
0x064
0x068
0x06C
0x074
0x08A
0x096
0x09A
0x0A0
TCC1_INT_base
SPIC_INT_vect
USARTC0_INT_base
USB_INT_base
LCD_INT_base
AES_INT_vect
Timer/Counter 1 on port C Interrupt base
SPI on port C Interrupt vector
USART 0 on port C Interrupt base
USB on port D Interrupt base
LCD Interrupt base
AES Interrupt vector
NVM_INT_base
PORTB_INT_base
ACB_INT_base
ADCB_INT_base
PORTD_INT_base
PORTG_INT_base
PORTM_INT_base
PORTE_INT_base
TCE0_INT_base
USARTE0_INT_base
PORTA_INT_base
ACA_INT_base
ADCA_INT_base
Non-Volatile Memory Interrupt base
Port B Interrupt base
Analog Comparator on Port B Interrupt base
Analog to Digital Converter on Port B Interrupt base
Port D Interrupt base
Port G Interrupt base
Port M Interrupt base
Port E Interrupt base
Timer/Counter 0 on port E Interrupt base
USART 0 on port E Interrupt base
Port A Interrupt base
Analog Comparator on Port A Interrupt base
Analog to Digital Converter on Port A Interrupt base
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15. I/O Ports
15.1 Features
• 53 General purpose input and output pins with individual configuration
• Output driver with configurable driver and pull settings:
– Totem-pole
– Wired-AND
– Wired-OR
– Bus-keeper
– Inverted I/O
• Input with synchronous and/or asynchronous sensing with interrupts and events
– Sense both edges
– Sense rising edges
– Sense falling edges
– Sense low level
• Optional pull-up and pull-down resistor on input and Wired-OR/AND configurations
• Optional slew rate control
• Asynchronous pin change sensing that can wake the device from all sleep modes
• Two port interrupts with pin masking per I/O port
• Efficient and safe access to port pins
– Hardware read-modify-write through dedicated toggle/clear/set registers
– Configuration of multiple pins in a single operation
– Mapping of port registers into bit-accessible I/O memory space
• Peripheral clocks output on port pin
• Real-time counter clock output to port pin
• Event channels can be output on port pin
• Remapping of digital peripheral pin functions
– Selectable USART, SPI, and timer/counter input/output pin locations
15.2 Overview
One port consists of up to eight port pins: pin 0 to 7. Each port pin can be configured as input or output with configurable
driver and pull settings. They also implement synchronous and asynchronous input sensing with interrupts and events for
selectable pin change conditions. Asynchronous pin-change sensing means that a pin change can wake the device from
all sleep modes, included the modes where no clocks are running.
All functions are individual and configurable per pin, but several pins can be configured in a single operation. The pins
have hardware read-modify-write (RMW) functionality for safe and correct change of drive value and/or pull resistor
configuration. The direction of one port pin can be changed without unintentionally changing the direction of any other
pin.
The port pin configuration also controls input and output selection of other device functions. It is possible to have both the
peripheral clock and the real-time clock output to a port pin, and available for external use. The same applies to events
from the event system that can be used to synchronize and control external functions. Other digital peripherals, such as
USART, SPI, and timer/counters, can be remapped to selectable pin locations in order to optimize pin-out versus
application needs.
The notation of the ports are PORTA, PORTB, PORTC, PORTD, PORTE, PORTG, PORTM and PORTR.
15.3 Output Driver
All port pins (Pn) have programmable output configuration. The port pins also have configurable slew rate limitation to
reduce electromagnetic emission.
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15.3.1 Push-pull
Figure 15-1. I/O configuration - Totem-pole
DIRn
OUTn
INn
Pn
15.3.2 Pull-down
Figure 15-2. I/O configuration - Totem-pole with pull-down (on input)
DIRn
OUTn
INn
Pn
15.3.3 Pull-up
Figure 15-3. I/O configuration - Totem-pole with pull-up (on input)
DIRn
OUTn
INn
Pn
15.3.4 Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as a pull-up if the last level
was ‘1’, and pull-down if the last level was ‘0’.
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Figure 15-4. I/O configuration - Totem-pole with bus-keeper
DIRn
OUTn
INn
Pn
15.3.5 Others
Figure 15-5. Output configuration - Wired-OR with optional pull-down
OUTn
Pn
INn
Figure 15-6. I/O configuration - Wired-AND with optional pull-up
INn
Pn
OUTn
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15.4 Input sensing
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports, and the configuration is
shown in Figure 15-7 on page 31.
Figure 15-7. Input sensing system overview
Asynchronous sensing
EDGE
DETECT
Interrupt
Control
IREQ
Event
Synchronous sensing
Pn
Synchronizer
INn
EDGE
DETECT
Q
Q
D
D
INVERTEDI/O
R
R
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
15.5 Alternate Port Functions
Most port pins have alternate pin functions in addition to being a general purpose I/O pin. When an alternate function is
enabled, it might override the normal port pin function or pin value. This happens when other peripherals that require pins
are enabled or configured to use pins. If and how a peripheral will override and use pins is described in the section for
that peripheral. “Pinout and Pin Functions” on page 52 shows which modules on peripherals that enable alternate
functions on a pin, and which alternate functions that are available on a pin.
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16. T/C – 16-bit Timer/Counter Type 0 and 1
16.1 Features
• Three 16-bit timer/counters
– Two timer/counters of type 0
– One timer/counters of type 1
• 32-bit Timer/Counter support by cascading two timer/counters
• Up to four compare or capture (CC) channels
– Four CC channels for timer/counters of type 0
– Two CC channels for timer/counters of type 1
• Double buffered timer period setting
• Double buffered capture or compare channels
• Waveform generation:
– Frequency generation
– Single-slope pulse width modulation
– Dual-slope pulse width modulation
• Input capture:
– Input capture with noise cancelling
– Frequency capture
– Pulse width capture
– 32-bit input capture
• Timer overflow and error interrupts/events
• One compare match or input capture interrupt/event per CC channel
• Can be used with event system for:
– Quadrature decoding
– Count and direction control
– Capture
• Can be used with DMA and to trigger DMA transactions
• High-resolution extension
– Increases frequency and waveform resolution by 4x (2-bit) or 8x (3-bit)
• Advanced waveform extension:
– Low- and high-side output with programmable dead-time insertion (DTI)
• Event controlled fault protection for safe disabling of drivers
16.2 Overview
Atmel AVR XMEGA devices have a set of three flexible 16-bit Timer/Counters (TC). Their capabilities include accurate
program execution timing, frequency and waveform generation, and input capture with time and frequency measurement
of digital signals. Two timer/counters can be cascaded to create a 32-bit timer/counter with optional 32-bit capture.
A timer/counter consists of a base counter and a set of compare or capture (CC) channels. The base counter can be
used to count clock cycles or events. It has direction control and period setting that can be used for timing. The CC
channels can be used together with the base counter to do compare match control, frequency generation, and pulse
width waveform modulation, as well as various input capture operations. A timer/counter can be configured for either
capture or compare functions, but cannot perform both at the same time.
A timer/counter can be clocked and timed from the peripheral clock with optional prescaling or from the event system.
The event system can also be used for direction control and capture trigger or to synchronize operations.
There are two differences between timer/counter type 0 and type 1. Timer/counter 0 has four CC channels, and
timer/counter 1 has two CC channels. All information related to CC channels 3 and 4 is valid only for timer/counter 0.
Only Timer/Counter 0 has the split mode feature that split it into 2 8-bit Timer/Counters with four compare channels each.
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Some timer/counters have extensions to enable more specialized waveform and frequency generation. The advanced
waveform extension (AWeX) is intended for motor control and other power control applications. It enables low- and high-
side output with dead-time insertion, as well as fault protection for disabling and shutting down external drivers. It can
also generate a synchronized bit pattern across the port pins.
The Advanced Waveform Extension can be enabled to provide extra and more advanced features for the Timer/Counter.
This are only available for Timer/Counter 0. See “TC2 –16-bit Timer/Counter Type 2” on page 34 for more details.
The high-resolution (hi-res) extension can be used to increase the waveform output resolution by four or eight times by
using an internal clock source running up to four times faster than the peripheral clock. See “Hi-Res – High Resolution
Extension” on page 36 for more details.
Figure 16-1. Overview of a Timer/Counter and closely related peripherals
Timer/Counter
Base Counter
Prescaler
clkPER
Timer Period
Counter
Control Logic
Event
System
clkPER4
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
AWeX
Pattern
Generation
Fault
Dead-Time
Insertion
Capture
Comparator
Control
Protection
Waveform
Buffer
Generation
PORTC has one Timer/Counter 0 and one Timer/Counter1. PORTE has one Timer/Counter 0. Notation of these are
TCC0 (Time/Counter C0), TCC1, and TCE0, respectively.
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17. TC2 –16-bit Timer/Counter Type 2
17.1 Features
• A system of two eight-bit timer/counters
– Low-byte timer/counter
– High-byte timer/counter
• Eight compare channels
– Four compare channels for the low-byte timer/counter
– Four compare channels for the high-byte timer/counter
• Waveform generation
– Single slope pulse width modulation
• Timer underflow interrupts/events
• One compare match interrupt/event per compare channel for the low-byte timer/counter
• Can be used with the event system for count control
• Can be used to trigger DMA transactions
• High-resolution extension increases frequency and waveform resolution by 4x or 8x
17.2 Overview
A timer/counter 2 is realized when a timer/counter 0 is set in split mode. It is a system of two eight-bit timer/counters,
each with four compare channels. This results in eight configurable pulse width modulation (PWM) channels with
individually controlled duty cycles, and is intended for applications that require a high number of PWM channels.
The two eight-bit timer/counters in this system are referred to as the low-byte timer/counter and high-byte timer/counter,
respectively. The difference between them is that only the low-byte timer/counter can be used to generate compare
match interrupts, events and DMA triggers.
The two eight-bit timer/counters have a shared clock source and separate period and compare settings. They can be
clocked and timed from the peripheral clock, with optional prescaling, or from the event system. The counters are always
counting down.
The timer/counter 2 is set back to timer/counter 0 by setting it in normal mode; hence, one timer/counter can exist only as
either type 0 or type 2.
PORTC and PORTE each has one Timer/Counter 2. Notation of these are TCC2 (Time/Counter C2) and TCE2
respectively.
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18. AWeX – Advanced Waveform Extension
18.1 Features
• Waveform output with complementary output from each compare channel
• Four dead-time insertion (DTI) units
– 8-bit resolution
– Separate high and low side dead-time setting
– Double buffered dead time
– Optionally halts timer during dead-time insertion
• Pattern generation unit creating synchronised bit pattern across the port pins
– Double buffered pattern generation
– Optional distribution of one compare channel output across the port pins
• Event controlled fault protection for instant and predictable fault triggering
18.2 Overview
The advanced waveform extension (AWeX) provides extra functions to the timer/counter in waveform generation (WG)
modes. It is primarily intended for use with different types of motor control and other power control applications. It
enables low- and high side output with dead-time insertion and fault protection for disabling and shutting down external
drivers. It can also generate a synchronized bit pattern across the port pins.
Each of the waveform generator outputs from the timer/counter 0 are split into a complimentary pair of outputs when any
AWeX features are enabled. These output pairs go through a dead-time insertion (DTI) unit that generates the non-
inverted low side (LS) and inverted high side (HS) of the WG output with dead-time insertion between LS and HS
switching. The DTI output will override the normal port value according to the port override setting.
The pattern generation unit can be used to generate a synchronized bit pattern on the port it is connected to. In addition,
the WG output from compare channel A can be distributed to and override all the port pins. When the pattern generator
unit is enabled, the DTI unit is bypassed.
The fault protection unit is connected to the event system, enabling any event to trigger a fault condition that will disable
the AWeX output. The event system ensures predictable and instant fault reaction, and gives flexibility in the selection of
fault triggers.
The AWEX is available for TCC0. The notation of this is AWEXC.
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19. Hi-Res – High Resolution Extension
19.1 Features
• Increases waveform generator resolution up to 8x (3 bits)
• Supports frequency, single-slope PWM, and dual-slope PWM generation
• Supports the AWeX when this is used for the same timer/counter
19.2 Overview
The high-resolution (hi-res) extension can be used to increase the resolution of the waveform generation output
from a timer/counter by four or eight. It can be used for a timer/counter doing frequency, single-slope PWM, or
dual-slope PWM generation. It can also be used with the AWeX if this is used for the same timer/counter.
The hi-res extension uses the peripheral 4x clock (ClkPER4). The system clock prescalers must be configured so the
peripheral 4x clock frequency is four times higher than the peripheral and CPU clock frequency when the hi-res extension
is enabled.
Atmel AVR XMEGA B1 devices have one Hi-Res Extension that can be enabled for the timer/counters pair on PORTC.
The notation of this is HIRESC.
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20. RTC – 16-bit Real-Time Counter
20.1 Features
• 16-bit resolution
• Selectable clock source
– 32.768kHz external crystal
– External clock
– 32.768kHz internal oscillator
– 32kHz internal ULP oscillator
• Programmable 10-bit clock prescaling
• One compare register
• One period register
• Clear counter on period overflow
• Optional interrupt/event on overflow and compare match
20.2 Overview
The 16-bit real-time counter (RTC) is a counter that typically runs continuously, including in low-power sleep modes, to
keep track of time. It can wake up the device from sleep modes and/or interrupt the device at regular intervals.
The reference clock is typically the 1.024kHz output from a high-accuracy crystal of 32.768kHz, and this is the
configuration most optimized for low power consumption. The faster 32.768kHz output can be selected if the RTC needs
a resolution higher than 1ms. The RTC can also be clocked from an external clock signal, the 32.768kHz internal
oscillator or the 32kHz internal ULP oscillator.
The RTC includes a 10-bit programmable prescaler that can scale down the reference clock before it reaches the
counter. A wide range of resolutions and time-out periods can be configured. With a 32.768kHz clock source, the
maximum resolution is 30.5µs, and time-out periods can range up to 2000 seconds. With a resolution of 1s, the
maximum timeout period is more than18 hours (65536 seconds). The RTC can give a compare interrupt and/or event
when the counter equals the compare register value, and an overflow interrupt and/or event when it equals the period
register value.
Figure 20-1. Real-time Counter overview
External Clock
TOSC1
32.768kHz Crystal Osc
TOSC2
32.768kHz Int. Osc
32kHz int ULP (DIV32)
PER
RTCSRC
TOP/
clkRTC
10-bit
=
=
Overflow
CNT
prescaler
”match”/
Compare
COMP
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21. USB – Universal Serial Bus Interface
21.1 Features
• One USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface
• Integrated on-chip USB transceiver, no external components needed
• 16 endpoint addresses with full endpoint flexibility for up to 31 endpoints
– One input endpoint per endpoint address
– One output endpoint per endpoint address
• Endpoint address transfer type selectable to
– Control transfers
– Interrupt transfers
– Bulk transfers
– Isochronous transfers
• Configurable data payload size per endpoint, up to 1023 bytes
• Endpoint configuration and data buffers located in internal SRAM
– Configurable location for endpoint configuration data
– Configurable location for each endpoint's data buffer
• Built-in direct memory access (DMA) to internal SRAM for:
– Endpoint configurations
– Reading and writing endpoint data
• Ping-pong operation for higher throughput and double buffered operation
– Input and output endpoint data buffers used in a single direction
– CPU/DMA controller can update data buffer during transfer
• Multipacket transfer for reduced interrupt load and software intervention
– Data payload exceeding maximum packet size is transferred in one continuous transfer
– No interrupts or software interaction on packet transaction level
• Transaction complete FIFO for workflow management when using multiple endpoints
– Tracks all completed transactions in a first-come, first-served work queue
• Clock selection independent of system clock source and selection
• Minimum 1.5MHz CPU clock required for low speed USB operation
• Minimum 12MHz CPU clock required for full speed operation
• Connection to event system
• On chip debug possibilities during USB transactions
21.2 Overview
The USB module is a USB 2.0 full speed (12Mbps) and low speed (1.5Mbps) device compliant interface.
The USB supports 16 endpoint addresses. All endpoint addresses have one input and one output endpoint, for a total of
31 configurable endpoints and one control endpoint. Each endpoint address is fully configurable and can be configured
for any of the four transfer types: control, interrupt, bulk, or isochronous. The data payload size is also selectable, and it
supports data payloads up to 1023 bytes.
No dedicated memory is allocated for or included in the USB module. Internal SRAM is used to keep the configuration for
each endpoint address and the data buffer for each endpoint. The memory locations used for endpoint configurations
and data buffers are fully configurable. The amount of memory allocated is fully dynamic, according to the number of
endpoints in use and the configuration of these. The USB module has built-in direct memory access (DMA), and will
read/write data from/to the SRAM when a USB transaction takes place.
To maximize throughput, an endpoint address can be configured for ping-pong operation. When done, the input and
output endpoints are both used in the same direction. The CPU or DMA controller can then read/write one data buffer
while the USB module writes/reads the others, and vice versa. This gives double buffered communication.
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Multipacket transfer enables a data payload exceeding the maximum packet size of an endpoint to be transferred as
multiple packets without software intervention. This reduces the CPU intervention and the interrupts needed for USB
transfers.
For low-power operation, the USB module can put the microcontroller into any sleep mode when the USB bus is idle and
a suspend condition is given. Upon bus resumes, the USB module can wake up the microcontroller from any sleep
mode.
PORTD has one USB. Notation of this is USB.
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22. TWI – Two Wire Interface
22.1 Features
• One two-wire interface peripheral
• Bidirectional, two-wire communication interface
– Phillips I2C compatible
– System Management Bus (SMBus) compatible
• Bus master and slave operation supported
– Slave operation
– Single bus master operation
– Bus master in multi-master bus environment
– Multi-master arbitration
• Flexible slave address match functions
– 7-bit and general call address recognition in hardware
– 10-bit addressing supported
– Address mask register for dual address match or address range masking
– Optional software address recognition for unlimited number of addresses
• Slave can operate in all sleep modes, including power-down
• Slave address match can wake device from all sleep modes
• 100kHz and 400kHz bus frequency support
• Slew-rate limited output drivers
• Input filter for bus noise and spike suppression
• Support arbitration between start/repeated start and data bit (SMBus)
• Slave arbitration allows support for address resolve protocol (ARP) (SMBus)
22.2 Overview
The two-wire interface (TWI) is a bidirectional, two-wire communication interface. It is I2C and System Management Bus
(SMBus) compatible. The only external hardware needed to implement the bus is one pull-up resistor on each bus line.
A device connected to the bus must act as a master or a slave. The master initiates a data transaction by addressing a
slave on the bus and telling whether it wants to transmit or receive data. One bus can have many slaves and one or
several masters that can take control of the bus. An arbitration process handles priority if more than one master tries to
transmit data at the same time. Mechanisms for resolving bus contention are inherent in the protocol.
The TWI module supports master and slave functionality. The master and slave functionality are separated from each
other, and can be enabled and configured separately. The master module supports multi-master bus operation and
arbitration. It contains the baud rate generator. Both 100kHz and 400kHz bus frequency is supported. Quick command
and smart mode can be enabled to auto-trigger operations and reduce software complexity.
The slave module implements 7-bit address match and general address call recognition in hardware. 10-bit addressing is
also supported. A dedicated address mask register can act as a second address match register or as a register for
address range masking. The slave continues to operate in all sleep modes, including power-down mode. This enables
the slave to wake up the device from all sleep modes on TWI address match. It is possible to disable the address
matching to let this be handled in software instead.
The TWI module will detect START and STOP conditions, bus collisions, and bus errors. Arbitration lost, errors, collision,
and clock hold on the bus are also detected and indicated in separate status flags available in both master and slave
modes.
It is possible to disable the TWI drivers in the device, and enable a four-wire digital interface for connecting to an external
TWI bus driver. This can be used for applications where the device operates from a different VCC voltage than used by
the TWI bus.
PORTC has one TWI. Notation of this peripheral is TWIC.
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23. SPI – Serial Peripheral Interface
23.1 Features
• One SPI peripheral
• Full-duplex, three-wire synchronous data transfer
• Master or slave operation
• Lsb first or msb first data transfer
• Eight programmable bit rates
• Interrupt flag at the end of transmission
• Write collision flag to indicate data collision
• Wake up from idle sleep mode
• Double speed master mode
23.2 Overview
The Serial Peripheral Interface (SPI) is a high-speed synchronous data transfer interface using three or four pins. It
allows fast communication between an XMEGA device and peripheral devices or between several microcontrollers. The
SPI supports full-duplex communication.
A device connected to the bus must act as a master or slave.The master initiates and controls all data transactions.
PORTC has one SPI. Notation of this peripheral is SPIC.
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24. USART
24.1 Features
• Two Identical USART peripherals
• Full-duplex operation
• Asynchronous or synchronous operation
– Synchronous clock rates up to 1/2 of the device clock frequency
– Asynchronous clock rates up to 1/8 of the device clock frequency
• Supports serial frames with 5, 6, 7, 8, or 9 data bits and 1 or 2 stop bits
• Fractional baud rate generator
– Can generate desired baud rate from any system clock frequency
– No need for external oscillator with certain frequencies
• Built-in error detection and correction schemes
– Odd or even parity generation and parity check
– Data overrun and framing error detection
– Noise filtering includes false start bit detection and digital low-pass filter
• Separate interrupts for
– Transmit complete
– Transmit data register empty
– Receive complete
• Multiprocessor communication mode
– Addressing scheme to address a specific devices on a multidevice bus
– Enable unaddressed devices to automatically ignore all frames
• Master SPI mode
– Double buffered operation
– Configurable data order
– Operation up to 1/2 of the peripheral clock frequency
• IRCOM module for IrDA compliant pulse modulation/demodulation
24.2 Overview
The universal synchronous and asynchronous serial receiver and transmitter (USART) is a fast and flexible serial
communication module. The USART supports full-duplex communication and asynchronous and synchronous operation.
The USART can be configured to operate in SPI master mode and used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide range of standards. The
USART is buffered in both directions, enabling continued data transmission without any delay between frames. Separate
interrupts for receive and transmit complete enable fully interrupt driven communication. Frame error and buffer overflow
are detected in hardware and indicated with separate status flags. Even or odd parity generation and parity check can
also be enabled.
The clock generator includes a fractional baud rate generator that is able to generate a wide range of USART baud rates
from any system clock frequencies. This removes the need to use an external crystal oscillator with a specific frequency
to achieve a required baud rate. It also supports external clock input in synchronous slave operation.
When the USART is set in master SPI mode, all USART-specific logic is disabled, leaving the transmit and receive
buffers, shift registers, and baud rate generator enabled. Pin control and interrupt generation are identical in both modes.
The registers are used in both modes, but their functionality differs for some control settings.
An IRCOM module can be enabled for one USART to support IrDA 1.4 physical compliant pulse modulation and
demodulation for baud rates up to 115.2kbps.
PORTC and PORTE each has one USART. Notation of these peripherals are USARTC0 and USARTE0 respectively.
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25. IRCOM – IR Communication Module
25.1 Features
• Pulse modulation/demodulation for infrared communication
• IrDA compatible for baud rates up to 115.2kbps
• Selectable pulse modulation scheme
– 3/16 of the baud rate period
– Fixed pulse period, 8-bit programmable
– Pulse modulation disabled
• Built-in filtering
• Can be connected to and used by any USART
25.2 Overview
XMEGA devices contain an infrared communication module (IRCOM) that is IrDA compatible for baud rates up to
115.2kbps. It can be connected to any USART to enable infrared pulse encoding/decoding for that USART.
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26. AES and DES Crypto Engine
26.1 Features
• Data Encryption Standard (DES) CPU instruction
• Advanced Encryption Standard (AES) crypto module
• DES Instruction
– Encryption and decryption
– DES supported
– Encryption/decryption in 16 CPU clock cycles per 8-byte block
• AES crypto module
– Encryption and decryption
– Supports 128-bit keys
– Supports XOR data load mode to the state memory
– Encryption/decryption in 375 clock cycles per 16-byte block
26.2 Overview
The Advanced Encryption Standard (AES) and Data Encryption Standard (DES) are two commonly used standards for
cryptography. These are supported through an AES peripheral module and a DES CPU instruction, and the
communication interfaces and the CPU can use these for fast, encrypted communication and secure data storage.
DES is supported by an instruction in the AVR CPU. The 8-byte key and 8-byte data blocks must be loaded into the
register file, and then the DES instruction must be executed 16 times to encrypt/decrypt the data block.
The AES crypto module encrypts and decrypts 128-bit data blocks with the use of a 128-bit key. The key and data must
be loaded into the key and state memory in the module before encryption/decryption is started. It takes 375 peripheral
clock cycles before the encryption/decryption is done. The encrypted/encrypted data can then be read out, and an
optional interrupt can be generated. The AES crypto module also has DMA support with transfer triggers when
encryption/decryption is done and optional auto-start of encryption/decryption when the state memory is fully loaded.
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27. CRC – Cyclic Redundancy Check Generator
27.1 Features
• Cyclic redundancy check (CRC) generation and checking for
– Communication data
– Program or data in flash memory
– Data in SRAM and I/O memory space
• Integrated with flash memory, DMA controller and CPU
– Continuous CRC on data going through a DMA channel
– Automatic CRC of the complete or a selectable range of the flash memory
– CPU can load data to the CRC generator through the I/O interface
• CRC polynomial software selectable to
– CRC-16 (CRC-CCITT)
– CRC-32 (IEEE 802.3)
• Zero remainder detection
27.2 Overview
A cyclic redundancy check (CRC) is an error detection technique test algorithm used to find accidental errors in data, and
it is commonly used to determine the correctness of a data transmission, and data present in the data and program
memories. A CRC takes a data stream or a block of data as input and generates a 16- or 32-bit output that can be
appended to the data and used as a checksum. When the same data are later received or read, the device or application
repeats the calculation. If the new CRC result does not match the one calculated earlier, the block contains a data error.
The application will then detect this and may take a corrective action, such as requesting the data to be sent again or
simply not using the incorrect data.
Typically, an n-bit CRC applied to a data block of arbitrary length will detect any single error burst not longer than n bits
(any single alteration that spans no more than n bits of the data), and will detect the fraction 1-2-n of all longer error
bursts. The CRC module in XMEGA devices supports two commonly used CRC polynomials; CRC-16 (CRC-CCITT) and
CRC-32 (IEEE 802.3).
CRC-16:
Polynomial:
Hex value:
x16+x12+x5+1
0x1021
CRC-32:
Polynomial:
Hex value:
x32+x26+x23+x22+x16+x12+x11+x10+x8+x7+x5+x4+x2+x+1
0x04C11DB7
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28. LCD - Liquid Crystal Display Controller
28.1 Features
• Display capacity up to 40 segment and up to 4 common terminals
• Supports up to 16 GPIO's
• Shadow display memory gives full freedom in segment update
• ASCII character mapping
• Swap capability option on segment and/or common terminal buses
• Supports from static up to 1/4 duty
• Supports static and 1/3 bias
• LCD driver active in power save mode for low power operation
• Software selectable low power waveform
• Flexible selection of frame frequency
• Programmable blink mode and frequency on two segment terminals
• Uses Only 32 kHz RTC clock source
• On-chip LCD power supply
• Software contrast adjustment control
• Equal source and sink capability to Increase glass life time
• Extended interrupt mode for display update or wake-up from sleep mode
28.2 Overview
The LCD controller is intended for monochrome passive liquid crystal display (LCD) with up to 4 Common terminals and
up to 40 Segments terminals. If the application does not need all the LCD segments available on the XMEGA, up to 16 of
the unused LCD pins can be used as general purpose I/O pins.
The LCD controller can be clocked by an internal or an external asynchronous 32kHz clock source. This 32kHz oscillator
source selection is the same as for the real time counter (RTC).
Dedicated Low Power Waveform, Contrast Control, Extended Interrupt Mode, Selectable Frame Frequency and Blink
functionality are supported to offload the CPU, reduce interrupts and reduce power consumption.
To reduce hardware design complexity, the LCD includes integrated LCD buffers, an integrated power supply voltage
and an innovative SWAP mode. Using SWAP mode, the hardware designers have more flexibility during board layout as
they can rearrange the pin sequence on Segment and/or Common Terminal Buses.
Figure 28-1. LCD overview
Character
Mapping
Timing
Control & Swap
SEG[39:0]
COM[3:0]
Shadow
Display
Memory
Analog
Switch
Array
Display
Memory
VLCD
BIAS1
BIAS2
LCD Power
Supply
CAPH
CAPL
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29. ADC – 12-bit Analog to Digital Converter
29.1 Features
• Two Analog to Digital Converters (ADCs)
• 12-bit resolution
• Up to 300 thousand samples per second
– Down to 2.3µs conversion time with 8-bit resolution
– Down to 3.35µs conversion time with 12-bit resolution
• Differential and single-ended input
– Up to 16 single-ended inputs
– 16x4 differential inputs without gain
– 16x4 differential input with gain
• Built-in differential gain stage
– 1/2x, 1x, 2x, 4x, 8x, 16x, 32x, and 64x gain options
• Single, continuous and scan conversion options
• Three internal inputs
– Internal temperature sensor
– VCC voltage divided by 10
– 1.1V bandgap voltage
• Internal and external reference options
• Compare function for accurate monitoring of user defined thresholds
• Optional event triggered conversion for accurate timing
• Optional DMA transfer of conversion results
• Optional interrupt/event on compare result
29.2 Overview
The ADC converts analog signals to digital values. The ADC has 12-bit resolution and is capable of converting up to 300
thousand samples per second (KSPS). The input selection is flexible, and both single-ended and differential
measurements can be done. For differential measurements, an optional gain stage is available to increase the dynamic
range. In addition, several internal signal inputs are available. The ADC can provide both signed and unsigned results.
The ADC measurements can either be started by application software or an incoming event from another peripheral in
the device. The ADC measurements can be started with predictable timing, and without software intervention. It is
possible to use DMA to move ADC results directly to memory or peripherals when conversions are done.
Both internal and external reference voltages can be used. An integrated temperature sensor is available for use with the
ADC. The output from the VCC/10 and the bandgap voltage can also be measured by the ADC.
The ADC has a compare function for accurate monitoring of user defined thresholds with minimum software intervention
required.
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Figure 29-1. ADC overview
Compare
Register
ADC0
•
•
•
VINP
<
>
ADC15
Threshold
(Int Req)
Internal
signals
CH0 Result
ADC
ADC0
•
•
•
VINN
ADC7
Internal 1.00V
Internal VCC/1.6V
Internal VCC/2
AREFA
Reference
Voltage
AREFB
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (propagation delay) from
3.35µs for 12-bit to 2.3µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This eases calculation when
the result is represented as a signed integer (signed 16-bit number).
PORTA and PORTB each has one ADC. Notation of these peripherals are ADCA and ADCB, respectively.
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30. AC – Analog Comparator
30.1 Features
• Four Analog Comparators (AC)
• Selectable hysteresis
– No
– Small
– Large
• Analog comparator output available on pin
• Flexible input selection
– All pins on the port
– Bandgap reference voltage
– A 64-level programmable voltage scaler of the internal VCC voltage
• Interrupt and event generation on:
– Rising edge
– Falling edge
– Toggle
• Window function interrupt and event generation on:
– Signal above window
– Signal inside window
– Signal below window
• Constant current source with configurable output pin selection
30.2 Overview
The analog comparator (AC) compares the voltage levels on two inputs and gives a digital output based on this
comparison. The analog comparator may be configured to generate interrupt requests and/or events upon several
different combinations of input change.
One important property of the analog comparator’s dynamic behavior is the hysteresis. This parameter may be adjusted
in order to achieve the optimal operation for each application.
The input selection includes analog port pins, several internal signals, and a 64-level programmable voltage scaler. The
analog comparator output state can also be output on a pin for use by external devices.
A constant current source can be enabled and output on a selectable pin. This can be used to replace, for example,
external resistors used to charge capacitors in capacitive touch sensing applications.
The analog comparators are always grouped in pairs on each port. These are called analog comparator 0 (AC0) and
analog comparator 1 (AC1). They have identical behavior, but separate control registers. Used as pair, they can be set in
window mode to compare a signal to a voltage range instead of a voltage level.
PORTA and PORTB each has one AC pair. Notations are ACA and ACB, respectively.
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Figure 30-1. Analog comparator overview
Pin Input
+
AC0OUT
AC0
Pin Input
-
Hysteresis
Enable
Interrupt
Interrupts
Events
Sensititivity
Control
&
Interrupt
Mode
Voltage
Scaler
ACnMUXCTRL
ACnCTRL
WINCTRL
Window
Function
Enable
Bandgap
Hysteresis
+
-
Pin Input
Pin Input
AC1OUT
AC1
The window function is realized by connecting the external inputs of the two analog comparators in a pair as shown in
Figure 30-2..
Figure 30-2. Analog comparator window function
+
AC0
Upper limit of window
-
Interrupts
Interrupt
Input signal
sensitivity
Events
control
+
AC1
Lower limit of window
-
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31. Programming and Debugging
31.1 Features
• Programming
– External programming through PDI or JTAG interfaces
Minimal protocol overhead for fast operation
Built-in error detection and handling for reliable operation
– Boot loader support for programming through any communication interface
• Debugging
– Nonintrusive, real-time, on-chip debug system
– No software or hardware resources required from device except pin connection
– Program flow control
Go, Stop, Reset, Step Into, Step Over, Step Out, Run-to-Cursor
– Unlimited number of user program breakpoints
– Unlimited number of user data breakpoints, break on:
Data location read, write, or both read and write
Data location content equal or not equal to a value
Data location content is greater or smaller than a value
Data location content is within or outside a range
– No limitation on device clock frequency
• Program and Debug Interface (PDI)
– Two-pin interface for external programming and debugging
– Uses the Reset pin and a dedicated pin
– No I/O pins required during programming or debugging
• JTAG interface
– Four-pin, IEEE Std. 1149.1 compliant interface for programming and debugging
– Boundary scan capabilities according to IEEE Std. 1149.1 (JTAG)
31.2 Overview
The Program and Debug Interface (PDI) is an Atmel proprietary interface for external programming and on-chip
debugging of a device.
The PDI supports fast programming of nonvolatile memory (NVM) spaces; flash, EEPOM, fuses, lock bits, and the user
signature row.
Debug is supported through an on-chip debug system that offers nonintrusive, real-time debug. It does not require any
software or hardware resources except for the device pin connection. Using the Atmel tool chain, it offers complete
program flow control and support for an unlimited number of program and complex data breakpoints. Application debug
can be done from a C or other high-level language source code level, as well as from an assembler and disassembler
level.
Programming and debugging can be done through two physical interfaces. The primary one is the PDI physical layer,
which is available on all devices. This is a two-pin interface that uses the Reset pin for the clock input (PDI_CLK) and one
other dedicated pin for data input and output (PDI_DATA). A JTAG interface is also available on most devices, and this
can be used for programming and debugging through the four-pin JTAG interface. The JTAG interface is IEEE Std.
1149.1 compliant, and supports boundary scan. Any external programmer or on-chip debugger/emulator can be directly
connected to either of these interfaces. Unless otherwise stated, all references to the PDI assume access through the
PDI physical layer.
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32. Pinout and Pin Functions
The device pinout is shown in “Pinout/Block Diagram” on page 3. In addition to general purpose I/O functionality, each
pin can have several alternate functions. This will depend on which peripheral is enabled and connected to the actual pin.
Only one of the pin functions can be used at time.
32.1 Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function.
32.1.1 Operation/Power Supply
VCC
Digital supply voltage
Analog supply voltage
Ground
AVCC
GND
AGND
Analog Ground
32.1.2 Port Interrupt functions
SYNC
Port pin with full synchronous and limited asynchronous interrupt function
ASYNC
Port pin with full synchronous and full asynchronous interrupt function
32.1.3 Analog functions
ACn
Analog Comparator input pin n
Analog Comparator n Output
Analog to Digital Converter input pin n
Analog Reference input pin
ACnOUT
ADCn
AREF
32.1.4 LCD functions
SEGn
COMn
VLCD
BIAS2
BIAS1
CAPH
CAPL
LCD Segment Drive Output n
LCD Common Drive Output n
LCD Voltage Multiplier Output
LCD Intermediate Voltage 2 Output (VLCD * 2/3)
LCD Intermediate Voltage 1 Output (VLCD * 1/3)
LCD High End Of Flying Capacitor
LCD Low End Of Flying Capacitor
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32.1.5 Timer/Counter and AWEX functions
OCnxLS
OCnxHS
Output Compare Channel x Low Side for Timer/Counter n
Output Compare Channel x High Side for Timer/Counter n
32.1.6 Communication functions
SCL
Serial Clock for TWI
SDA
Serial Data for TWI
SCLIN
SCLOUT
SDAIN
SDAOUT
XCKn
RXDn
TXDn
SS
Serial Clock In for TWI when external driver interface is enabled
Serial Clock Out for TWI when external driver interface is enabled
Serial Data In for TWI when external driver interface is enabled
Serial Data Out for TWI when external driver interface is enabled
Transfer Clock for USART n
Receiver Data for USART n
Transmitter Data for USART n
Slave Select for SPI
MOSI
MISO
SCK
Master Out Slave In for SPI
Master In Slave Out for SPI
Serial Clock for SPI
D-
Data- for USB
D+
Data+ for USB
32.1.7 Oscillators, Clock and Event
TOSCn
XTALn
Timer Oscillator pin n
Input/Output for Oscillator pin n
Peripheral Clock Output
CLKOUT
EVOUT
RTCOUT
Event Channel 0 Output
RTC Clock Source Output
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32.1.8 Debug/System functions
RESET
PDI_CLK
PDI_DATA
TCK
Reset pin
Program and Debug Interface Clock pin
Program and Debug Interface Data pin
JTAG Test Clock
TDI
JTAG Test Data In
TDO
JTAG Test Data Out
TMS
JTAG Test Mode Select
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32.2 Alternate Pin Functions
The tables below show the primary/default function for each pin on a port in the first column, the pin number in the
second column, and then all alternate pin functions in the remaining columns. The head row shows what peripheral that
enable and use the alternate pin functions.
For better flexibility, some alternate functions also have selectable pin locations for their functions, this is noted under the
the first table where this apply.
Table 32-1. Port A - Alternate functions
ADCA
ADCB
PORT A
PIN #
INTERRUPT
ADCA
NEG
ADCA
ACA
POS
ACA
NEG
ACA
OUT
REFA
POS/GAIN
POS
POS/GAIN
POS
GAINNEG
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
82
83
84
85
86
87
88
89
SYNC
SYNC
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC0
ADC1
ADC2
ADC3
AC0
AC1
AC2
AC3
AC4
AC5
AC6
AC0
AC1
AREF
SYNC/ASYNC
SYNC
ADC10
ADC11
ADC12
ADC13
ADC14
ADC15
AC3
AC5
AC7
SYNC
ADC4
ADC5
ADC6
ADC7
SYNC
SYNC
AC1OUT
AC0OUT
SYNC
Table 32-2. Port B - Alternate functions
ADCA
ADCB
PORT B
PIN #
INTERRUPT
ADCB
ADCB
ACB
POS
ACB
NEG
ACB
OUT
REFB
JTAG
POS/GAIN
POS
POS/GAIN
POS
NEG
GAINNEG
AGND
AVDD
PB0
90
91
92
93
SYNC
SYNC
ADC8
ADC9
ADC0
ADC1
ADC0
ADC1
AC0
AC1
AC0
AC1
AREF
PB1
SYNC/ASYN
C
PB2
94
ADC10
ADC2
ADC2
ADC3
AC2
PB3
PB4
PB5
PB6
PB7
95
96
97
98
99
SYNC
SYNC
SYNC
SYNC
SYNC
ADC11
ADC12
ADC13
ADC14
ADC15
ADC3
ADC4
ADC5
ADC6
ADC7
AC3
AC4
AC5
AC6
AC3
AC5
AC7
ADC4
ADC5
ADC6
ADC7
TMS
TDI
AC1OUT
AC0OUT
TCK
TDO
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Table 32-3. Port C - Alternate functions.
PIN
CLOCKOUT
EVENTOUT
(4)
(5)
PORT C
GND
VCC
PC0
#
100
1
INTERRUPT
TCC0(1)
AWEXC
TCC1
USARTC0(2)
SPIC(3)
TWIC
EXTCLK
2
SYNC
SYNC
OC0A
OC0B
OC0C
OC0D
OC0ALS
OC0AHS
OC0BLS
OC0BHS
OC0CLS
OC0CHS
OC0DLS
OC0DHS
SDA
SCL
EXTCLKC0
EXTCLKC1
EXTCLKC2
EXTCLKC3
EXTCLKC4
EXTCLKC5
EXTCLKC6
EXTCLKC7
PC1
3
XCK0
RXD0
TXD0
PC2
4
SYNC/ASYNC
SYNC
PC3
5
PC4
6
SYNC
OC1A
OC1B
SS
PC5
7
SYNC
MOSI
MISO
SCK
PC6
8
SYNC
RTCOUT
clkPER
PC7
9
SYNC
EVOUT
Notes:
1. Pin mapping of all TC0 can optionally be moved to high nibble of port.
2. Pin mapping of all USART0 can optionally be moved to high nibble of port.
3. Pins MOSI and SCK for all SPI can optionally be swapped.
4. CLKOUT can optionally be moved between port C and E and between pin 4 and 7.
5. EVOUT can optionally be moved between port C and E and between pin 4 and 7.
Table 32-4. Port D - Alternate functions.
PORT D
GND
VCC
PIN #
10
INTERRUPT
USBD
11
PD0
12
SYNC
SYNC
D-
PD1
13
D+
PD2
14
SYNC/ASYNC
Table 32-5. Program and Debug functions.
PROG
RESET
PDI
PIN #
15
INTERRUPT
PROG
PDI_DATA
16
PDI_CLOCK
GND
17
VCC
18
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Table 32-6. Port E - Alternate functions.
PORT E
PE0
PIN #
19
INTERRUPT
SYNC
TCE0(1)
OC0A
OC0B
OC0C
OC0D
USARTE0(2)
CLOCKOUT(4)
EVENTOUT(5)
Alternate TOSC
PE1
20
SYNC
XCK0
RXD0
TXD0
PE2
21
SYNC/ASYNC
SYNC
PE3
22
PE4
23
SYNC
PE5
24
SYNC
PE6
25
SYNC
TOSC2
TOSC1
PE7
26
SYNC
clkPER
EVOUT
Table 32-7. LCD
LCD(1)(2)
GND
PIN #
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
INTERRUPT(1)
GPIO(1)
BLINK(1)
VCC
SEG39
SEG38
SEG37
SEG36
SEG35
SEG34
SEG33
SEG32
SEG31
SEG30
SEG29
SEG28
SEG27
SEG26
SEG25
SEG24
SEG23
SEG22
SEG21
SEG20
SEG19
SYNC
SYNC
PG0
PG1
PG2
PG3
PG4
PG5
PG6
PG7
PM0
PM1
PM2
PM3
PM4
PM5
PM6
PM7
SYNC/ASYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC
SYNC/ASYNC
SYNC
SYNC
SYNC
SYNC
SYNC
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LCD(1)(2)
SEG18
SEG17
SEG16
SEG15
SEG14
SEG13
SEG12
SEG11
SEG10
SEG9
PIN #
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
INTERRUPT(1)
GPIO(1)
BLINK(1)
SEG8
SEG7
SEG6
SEG5
SEG4
SEG3
SEG2
SEG1
BLINK
BLINK
SEG0
GND
VCC
BIAS1
BIAS2
VLCD
CAPL
CAPH
COM0
COM1
COM2
COM3
Notes:
1. Pin mapping of all Segment terminals (SEGn) can be optionnaly swapped. Interrupt, GPIO and Blink functions will be automatically swapped.
2. Pin mapping of all Common terminals (COMn) can be optionnaly swapped.
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Table 32-8. Port R- Alternate functions.
PORT R
PRO
PIN #
80
INTERRUPT
SYNC
XTAL
XTAL2
XTAL1
TOSC
TOSC2
TOSC1
PR1
82
SYNC
33. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in XMEGA B1. For complete register
description and summary for each peripheral module, refer to the XMEGA B Manual.
Table 33-1. Peripheral module address map.
Base address
0x0000
0x0010
0x0014
0x0018
0x001C
0x0030
0x0040
0x0048
0x0050
0x0060
0x0068
0x0070
0x0078
0x0080
0x0090
0x00A0
0x00B0
0x00C0
0x00D0
0x0100
0x0180
0x01C0
0x0200
0x0240
0x0380
0x0390
0x0400
0x0480
0x04C0
0x0600
0x0620
Name
GPIO
Description
General Purpose IO Registers
Virtual Port 0
VPORT0
VPORT1
VPORT2
VPORT3
CPU
Virtual Port 1
Virtual Port 2
Virtual Port 3
CPU
CLK
Clock Control
SLEEP
OSC
Sleep Controller
Oscillator Control
DFLLRC32M
DFLLRC2M
PR
DFLL for the 32MHz Internal Oscillator
DFLL for the 2MHz Internal Oscillator
Power Reduction
RST
Reset Controller
WDT
Watch-Dog Timer
MCU
MCU Control
PMIC
Programmable Multilevel Interrupt Controller
Port Configuration
PORTCFG
AES
AES Module
CRC
CRC Module
DMA
DMA Controller
EVSYS
NVM
Event System
Non Volatile Memory (NVM) Controller
Analog to Digital Converter on port A
Analog to Digital Converter on port B
Analog Comparator pair on port A
Analog Comparator pair on port B
Real Time Counter
Two Wire Interface on port C
USB Device
ADCA
ADCB
ACA
ACB
RTC
TWIC
USB
PORTA
PORTB
Port A
Port B
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Base address
0x0640
0x0660
0x0680
0x06C0
0x0760
0x07E0
0x0800
0x0840
0x0880
0x0890
0x08A0
0x08C0
0x08F8
0x0A00
0x0AA0
0x0D00
Name
PORTC
PORTD
PORTE
PORTG
PORTM
PORTR
TCC0
Description
Port C
Port D
Port E
Port G
Port M
Port R
Timer/Counter 0 on port C
Timer/Counter 1 on port C
Advanced Waveform Extension on port C
High Resolution Extension on port C
USART 0 on port C
Serial Peripheral Interface on port C
Infrared Communication Module
Timer/Counter 0 on port E
USART 0 on port E
Liquid Crystal Display
TCC1
AWEXC
HIRESC
USARTC0
SPIC
IRCOM
TCE0
USARTE0
LCD
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34. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
Arithmetic and Logic Instructions
ADD
ADC
ADIW
SUB
Rd, Rr
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add without Carry
Rd
Rd
Rd
Rd
Rd
Rd
Rd
Rd + Rr
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,C,N,V,S
Z,C,N,V,S,H
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
None
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
1/2
Add with Carry
Rd + Rr + C
Rd + 1:Rd + K
Rd - Rr
Add Immediate to Word
Subtract without Carry
Subtract Immediate
Subtract with Carry
Subtract Immediate with Carry
Subtract Immediate from Word
Logical AND
SUBI
SBC
Rd - K
Rd - Rr - C
Rd - K - C
Rd + 1:Rd - K
Rd Rr
SBCI
SBIW
AND
ANDI
OR
Rd + 1:Rd
Rd
Logical AND with Immediate
Logical OR
Rd
Rd K
Rd
Rd v Rr
ORI
Logical OR with Immediate
Exclusive OR
Rd
Rd v K
EOR
COM
NEG
SBR
Rd
Rd Rr
One’s Complement
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd
$FF - Rd
Rd
Rd
$00 - Rd
Rd,K
Rd,K
Rd
Rd
Rd v K
CBR
INC
Rd
Rd ($FFh - K)
Rd + 1
Rd
DEC
TST
Rd
Decrement
Rd
Rd - 1
Rd
Test for Zero or Minus
Clear Register
Rd
Rd Rd
CLR
Rd
Rd
Rd Rd
SER
Rd
Set Register
Rd
$FF
MUL
MULS
MULSU
FMUL
FMULS
FMULSU
DES
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
K
Multiply Unsigned
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
Rd x Rr (UU)
Rd x Rr (SS)
Rd x Rr (SU)
Rd x Rr<<1 (UU)
Rd x Rr<<1 (SS)
Rd x Rr<<1 (SU)
Z,C
Multiply Signed
Z,C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Data Encryption
Z,C
Z,C
Z,C
Z,C
if (H = 0) then R15:R0
else if (H = 1) then R15:R0
Encrypt(R15:R0, K)
Decrypt(R15:R0, K)
Branch instructions
RJMP
IJMP
k
Relative Jump
PC
PC + k + 1
None
None
2
2
Indirect Jump to (Z)
PC(15:0)
PC(21:16)
Z,
0
EIJMP
Extended Indirect Jump to (Z)
PC(15:0)
PC(21:16)
Z,
EIND
None
2
JMP
k
k
Jump
PC
PC
k
None
None
3
RCALL
Relative Call Subroutine
PC + k + 1
2 / 3 (1)
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8330C–AVR–07/2012
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ICALL
Indirect Call to (Z)
PC(15:0)
PC(21:16)
Z,
0
None
2 / 3 (1)
EICALL
Extended Indirect Call to (Z)
PC(15:0)
PC(21:16)
Z,
EIND
None
3 (1)
CALL
RET
k
call Subroutine
PC
PC
k
None
None
I
3 / 4 (1)
4 / 5 (1)
4 / 5 (1)
1 / 2 / 3
1
Subroutine Return
STACK
STACK
PC + 2 or 3
RETI
Interrupt Return
PC
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC
None
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Rd,Rr
Rd - Rr
CPC
Rd,Rr
Compare with Carry
Rd - Rr - C
1
CPI
Rd,K
Compare with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd - K
1
SBRC
SBRS
SBIC
SBIS
Rr, b
if (Rr(b) = 0) PC
if (Rr(b) = 1) PC
if (I/O(A,b) = 0) PC
If (I/O(A,b) =1) PC
if (SREG(s) = 1) then PC
if (SREG(s) = 0) then PC
if (Z = 1) then PC
if (Z = 0) then PC
if (C = 1) then PC
if (C = 0) then PC
if (C = 0) then PC
if (C = 1) then PC
if (N = 1) then PC
if (N = 0) then PC
if (N V= 0) then PC
if (N V= 1) then PC
if (H = 1) then PC
if (H = 0) then PC
if (T = 1) then PC
if (T = 0) then PC
if (V = 1) then PC
if (V = 0) then PC
if (I = 1) then PC
if (I = 0) then PC
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
1 / 2 / 3
1 / 2 / 3
2 / 3 / 4
2 / 3 / 4
1 / 2
Rr, b
A, b
A, b
s, k
s, k
k
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
1 / 2
1 / 2
k
Branch if Not Equal
1 / 2
k
Branch if Carry Set
1 / 2
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
1 / 2
k
1 / 2
k
1 / 2
k
Branch if Minus
1 / 2
k
Branch if Plus
1 / 2
k
Branch if Greater or Equal, Signed
Branch if Less Than, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
Data transfer instructions
MOV
MOVW
LDI
Rd, Rr
Rd, Rr
Rd, K
Copy Register
Rd
Rd+1:Rd
Rd
Rr
None
None
None
1
1
1
Copy Register Pair
Load Immediate
Rr+1:Rr
K
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8330C–AVR–07/2012
Mnemonics
Operands
Rd, k
Description
Operation
Flags
None
None
None
#Clocks
2 (1)(2)
LDS
LD
Load Direct from data space
Load Indirect
Rd
Rd
(k)
Rd, X
(X)
1 (1)(2)
LD
Rd, X+
Load Indirect and Post-Increment
Rd
X
(X)
X + 1
1 (1)(2)
LD
Rd, -X
Load Indirect and Pre-Decrement
X X - 1,
Rd (X)
X - 1
(X)
None
2 (1)(2)
LD
LD
Rd, Y
Load Indirect
Rd (Y)
(Y)
None
None
1 (1)(2)
1 (1)(2)
Rd, Y+
Load Indirect and Post-Increment
Rd
Y
(Y)
Y + 1
LD
Rd, -Y
Load Indirect and Pre-Decrement
Y
Rd
Y - 1
(Y)
None
2 (1)(2)
LDD
LD
Rd, Y+q
Rd, Z
Load Indirect with Displacement
Load Indirect
Rd
Rd
(Y + q)
(Z)
None
None
None
2 (1)(2)
1 (1)(2)
1 (1)(2)
LD
Rd, Z+
Load Indirect and Post-Increment
Rd
Z
(Z),
Z+1
LD
Rd, -Z
Load Indirect and Pre-Decrement
Z
Rd
Z - 1,
(Z)
None
2 (1)(2)
LDD
STS
ST
Rd, Z+q
k, Rr
Load Indirect with Displacement
Store Direct to Data Space
Store Indirect
Rd
(k)
(X)
(Z + q)
Rd
None
None
None
None
2 (1)(2)
2 (1)
X, Rr
Rr
1 (1)
ST
X+, Rr
Store Indirect and Post-Increment
(X)
X
Rr,
X + 1
1 (1)
ST
-X, Rr
Store Indirect and Pre-Decrement
X
(X)
X - 1,
Rr
None
2 (1)
ST
ST
Y, Rr
Store Indirect
(Y)
Rr
None
None
1 (1)
1 (1)
Y+, Rr
Store Indirect and Post-Increment
(Y)
Y
Rr,
Y + 1
ST
-Y, Rr
Store Indirect and Pre-Decrement
Y
(Y)
Y - 1,
Rr
None
2 (1)
STD
ST
Y+q, Rr
Z, Rr
Store Indirect with Displacement
Store Indirect
(Y + q)
(Z)
Rr
Rr
None
None
None
2 (1)
1 (1)
1 (1)
ST
Z+, Rr
Store Indirect and Post-Increment
(Z)
Z
Rr
Z + 1
ST
-Z, Rr
Store Indirect and Pre-Decrement
Store Indirect with Displacement
Load Program Memory
Z
(Z + q)
R0
Z - 1
Rr
None
None
None
None
None
2 (1)
2 (1)
3
STD
LPM
LPM
LPM
Z+q,Rr
(Z)
Rd, Z
Load Program Memory
Rd
(Z)
3
Rd, Z+
Load Program Memory and Post-Increment
Rd
Z
(Z),
Z + 1
3
ELPM
ELPM
ELPM
Extended Load Program Memory
Extended Load Program Memory
R0
Rd
(RAMPZ:Z)
(RAMPZ:Z)
None
None
None
3
3
3
Rd, Z
Rd, Z+
Extended Load Program Memory and Post-
Increment
Rd
Z
(RAMPZ:Z),
Z + 1
SPM
SPM
Store Program Memory
(RAMPZ:Z)
R1:R0
None
None
-
-
Z+
Store Program Memory and Post-Increment
by 2
(RAMPZ:Z)
Z
R1:R0,
Z + 2
XMEGA B1 [DATASHEET]
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8330C–AVR–07/2012
Mnemonics
IN
Operands
Rd, A
A, Rr
Rr
Description
Operation
Flags
None
None
None
None
None
#Clocks
In From I/O Location
Out To I/O Location
Push Register on Stack
Pop Register from Stack
Exchange RAM location
Rd
I/O(A)
STACK
Rd
I/O(A)
Rr
1
1
OUT
PUSH
POP
Rr
1 (1)
2 (1)
2
Rd
STACK
XCH
Z, Rd
Temp
Rd
(Z)
Rd,
(Z),
Temp
LAS
LAC
LAT
Z, Rd
Z, Rd
Z, Rd
Load and Set RAM location
Load and Clear RAM location
Load and Toggle RAM location
Temp
Rd
(Z)
Rd,
(Z),
Temp v (Z)
None
None
None
2
2
2
Temp
Rd
(Z)
Rd,
(Z),
($FFh – Rd) (Z)
Temp
Rd
(Z)
Rd,
(Z),
Temp (Z)
Bit and bit-test instructions
LSL
Rd
Rd
Rd
Rd
Logical Shift Left
Rd(n+1)
Rd(0)
C
Rd(n),
0,
Rd(7)
Z,C,N,V,H
Z,C,N,V
1
1
1
1
LSR
ROL
ROR
Logical Shift Right
Rd(n)
Rd(7)
C
Rd(n+1),
0,
Rd(0)
Rotate Left Through Carry
Rotate Right Through Carry
Rd(0)
Rd(n+1)
C
C,
Rd(n),
Rd(7)
Z,C,N,V,H
Z,C,N,V
Rd(7)
Rd(n)
C
C,
Rd(n+1),
Rd(0)
ASR
SWAP
BSET
BCLR
SBI
Rd
Arithmetic Shift Right
Swap Nibbles
Rd(n)
Rd(n+1), n=0..6
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rd
Rd(3..0)
Rd(7..4)
None
s
Flag Set
SREG(s)
1
SREG(s)
s
Flag Clear
SREG(s)
0
SREG(s)
A, b
A, b
Rr, b
Rd, b
Set Bit in I/O Register
Clear Bit in I/O Register
Bit Store from Register to T
Bit load from T to Register
Set Carry
I/O(A, b)
1
None
CBI
I/O(A, b)
0
None
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
T
Rr(b)
T
1
T
Rd(b)
None
C
C
N
N
Z
Z
I
C
C
N
N
Z
Z
I
Clear Carry
0
Set Negative Flag
Clear Negative Flag
Set Zero Flag
1
0
1
Clear Zero Flag
0
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
1
CLI
I
0
I
SES
CLS
S
S
1
S
S
0
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Mnemonics
SEV
Operands
Description
Operation
Flags
#Clocks
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
V
V
T
1
0
1
0
1
0
V
V
T
T
H
H
1
1
1
1
1
1
CLV
SET
CLT
Clear T in SREG
T
SEH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H
H
CLH
MCU control instructions
BREAK
NOP
Break
(See specific descr. for BREAK)
None
None
None
None
1
1
1
1
No Operation
Sleep
SLEEP
WDR
(see specific descr. for Sleep)
(see specific descr. for WDR)
Watchdog Reset
Notes:
1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid for accesses via the external RAM interface.
2. One extra cycle must be added when accessing Internal SRAM.
XMEGA B1 [DATASHEET]
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35. Packaging information
35.1 100A
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0°~7°
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
NOTE
SYMBOL
A
–
–
A1
A2
D
0.05
0.95
15.75
13.90
15.75
13.90
0.17
0.09
0.45
0.15
1.00
16.00
14.00
16.00
14.00
–
1.05
16.25
D1
E
14.10 Note 2
16.25
Notes:
E1
B
14.10 Note 2
0.27
1. This package conforms to JEDEC reference MS-026, Variation AED.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
C
–
0.20
3. Lead coplanarity is 0.08 mm maximum.
L
–
0.75
e
0.50 TYP
2010-10-20
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
100A, 100-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.5 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
100A
D
R
XMEGA B1 [DATASHEET]
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36. Electrical Characteristics
All typical values are measured at T = 25C unless other temperature condition is given. All minimum and maximum
values are valid across operating temperature and voltage unless other conditions are given.
36.1 Absolute Maximum Ratings
Stresses beyond those listed in Table 36-1 on page 67 under may cause permanent damage to the device. This is a
stress rating only and functional operation of the device at these or other conditions beyond those indicated in the
operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Table 36-1. Absolute maximum ratings.
Symbol
VCC
Parameter
Condition
Min.
Typ.
Max.
4
Units
Power supply voltage
Current into a Vcc pin
Current out of a Gnd pin
-0.3
V
IVCC
200
200
mA
IGND
Pin voltage with respect to
Gnd and VCC
VPIN
-0.5
Vcc+0.5
V
IPIN
TA
Tj
I/O pin sink/source current
Storage temperature
-25
-65
25
mA
150
150
°C
Junction temperature
36.2 General Operating Ratings
The device must operate within the ratings listed in Table 36-2 on page 67 in order for all other electrical characteristics
and typical characteristics of the device to be guaranteed and valid.
Table 36-2. General operating conditions.
Symbol
VCC
AVCC
TA
Parameter
Condition
Min.
1.60
1.60
-40
Typ.
Max.
3.6
Units
Power supply voltage
Power supply voltage
Temperature range
Junction temperature
V
3.6
85
°C
Tj
-40
105
Table 36-3. Operating voltage and frequency.
Symbol
Parameter
Condition
VCC = 1.6V
VCC = 1.8V
VCC = 2.7V
VCC = 3.6V
Min
0
Typ.
Max.
12
Units
0
12
ClkCPU
CPU clock frequency
MHz
0
32
0
32
XMEGA B1 [DATASHEET]
67
8330C–AVR–07/2012
The maximum System clock frequency of the Atmel® AVR® XMEGA B1 devices is depending on VCC. As shown in Figure
36-1 on page 68 the Frequency vs. VCC curve is linear between 1.8V < VCC < 2.7V.
Figure 36-1. Maximum Frequency vs. Vcc
MHz
32
Safe Operating Area
12
V
1.6
1.8
2.7
3.6
XMEGA B1 [DATASHEET]
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36.3 DC Characteristics
Table 36-4. Current Consumption for active and sleep modes.
Symbol Parameter
Condition
Min
Typ
150
320
350
700
650
1.0
10
Max
Units
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
32kHz, Ext. Clk
µA
1MHz, Ext. Clk
Active Power
consumption(1)
800
1.6
15
2MHz, Ext. Clk
32MHz, Ext. Clk
32kHz, Ext. Clk
VCC = 3.0V
mA
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
4.0
8.0
80
1MHz, Ext. Clk
2MHz, Ext. Clk
µA
Idle Power
150
160
300
4.7
0.1
2.1
1.2
1.3
3.1
1.2
1.3
0.8
0.9
1.3
1.6
consumption(1)
250
600
7
ICC
VCC = 3.0V
32MHz, Ext. Clk
mA
T = 25°C
1.0
5
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
T = 85°C
Power-down
power
consumption
WDT and Sampled BOD enabled, T = 25°C
WDT and Sampled BOD enabled, T = 25°C
WDT and Sampled BOD enabled, T=85°C
2.5
3
7
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
VCC = 3.0V
µA
RTC on ULP clock, WDT and sampled BOD
enabled, T = 25°C
Power-save
power
RTC on 1.024kHz low power 32.768kHz
TOSC, T = 25°C
consumption(2)
RTC from low power 32.768kHz TOSC,
T = 25°C
XMEGA B1 [DATASHEET]
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Symbol Parameter
Condition
Min
Typ
4.6
5.2
3.9
Max
Units
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
RTC on ULP clock, WDT, sampled BOD and
LCD enabled, and all pixels ON, T = 25°C
Power-save
RTC on 1.024kHz low power 32.768kHz
TOSC, LCD enabled and all pixels ON
T = 25°C
ICC
power
consumption(2)
VCC = 3.0V
4.3
µA
VCC = 1.8V
VCC = 3.0V
4.0
4.5
RTC from low power 32.768kHz TOSC, LCD
enabled and all pixels ON, T = 25°C
Reset power
consumption
Current through RESET pin substracted
VCC = 3.0V
420
Notes:
1. All Power Reduction Registers set.
2. Maximum limits are based on characterization and not tested in production.
XMEGA B1 [DATASHEET]
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Table 36-5. Current Consumption for modules and peripherals.
Symbol Parameter
Condition(1)
Min
Typ
Max
Units
ULP oscillator
1.0
32.768kHz int.
oscillator
26
80
112
255
444
316
1
2MHz int.
oscillator
DFLL enabled with 32.768kHz int. osc. as reference
32MHz int.
oscillator
DFLL enabled with 32.768kHz int. osc. as reference
Multiplication factor = 20x
PLL
Watchdog Timer
Continuous mode
126
1.3
3.0
3.0
3.0
3.3
3.4
3.4
3.8
3.9
3.9
3.7
4.3
BOD
Sampled mode, include ULP oscillator
All pixels OFF
Contrast min
Contrast typ
100 pixels ON
All pixels ON
All pixels OFF
100 pixels ON
All pixels ON
All pixels OFF
100 pixels ON
All pixels ON
All pixels OFF
All pixels ON
µA
No pixel load
LCD(2)
ICC
Contrast max
Contrast typ
22pF pixel load
Internal 1.0V
reference
100
100
Temperature
sensor
1.3
1.1
1.0
0.9
CURRLIMIT = LOW
16ksps
VREF = Ext ref
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
ADC
mA
75ksps
VREF = Ext ref
1.7
3.1
300ksps
VREF = Ext ref
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Symbol Parameter
Condition(1)
Min
Typ
440
115
9
Max
Units
µA
AC
DMA
615Kbps between I/O registers and SRAM
Rx and Tx enabled, 9600 BAUD
ICC
USART
Flash memory and EEPROM programming
4.4
mA
Notes:
1. .All parameters measured as the difference in current consumption between module enabled and disabled. All data at VCC = 3.0V, ClkSYS = 1MHz External
clock without prescaling, T = 25°C unless other conditiond are given.
2. LCD configuration: internal voltage generation, 32Hz low power frame rate, 1/3 bias, clocked by low power 32.768kHz TOSC.
36.4 Wake-up time from sleep modes
Table 36-6. Device wake-up time from sleep modes with various system clock sources.
Symbol Parameter
Condition
External 2MHz clock
Min
Typ
2
Max
Units
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
External 2MHz clock
120
2
Wake-up time from Idle,
Standby, and Extend Standby
0.2
4.5
320
9
twakeup
µs
32.768kHz internal oscillator
2MHz internal oscillator
32MHz internal oscillator
Wake-up time from Power-save
and Power-down mode
5
Note:
1. The wake-up time is the time from the wake-up request is given until the peripheral clock is available on pin, see Figure 36-2 on page 72. All peripherals and
modules start execution from the first clock cycle, expect the CPU that is halted for four clock cycles before program execution starts.
Figure 36-2. Wake-up time definition.
Wakeup time
Wakeup request
Clock output
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8330C–AVR–07/2012
36.5 I/O Pin Characteristics
The I/O pins complies with the JEDEC LVTTL and LVCSMOS specification and the high- and low level input and output
voltage limits reflect or exceed this specification.
Table 36-7. I/O Pin Characteristics.
Symbol Parameter
Condition
Min
Typ
Max
Units
(1)
I
/
OH
I/O pin source/sink current
-20
20
mA
(2)
I
OL
VCC = 3.0 - 3.6V
0.6*VCC
0.6*VCC
0.6*VCC
-0.3
VCC+0.3
VCC+0.3
VCC+0.3
0.4*VCC
0.4*VCC
0.4*VCC
0.76
VIH
High Level Input Voltage
VCC = 2.3 - 2.7V
VCC = 1.6 - 2.3V
VCC = 3.0 - 3.6V
VCC = 2.3 - 2.7V
VCC = 1.6 - 2.3V
VCC = 3.3V
VIL
Low Level Input Voltage
Output Low Voltage GPIO
Output High Voltage GPIO
-0.3
-0.3
V
IOL = 15mA
IOL = 10mA
IOL = 5mA
IOH = -8mA
IOH = -6mA
IOH = -2mA
0.4
0.26
0.17
2.8
2.6
1.6
<0.01
25
VOL
VCC = 3.0V
0.64
VCC = 1.8V
0.46
VCC = 3.3V
2.6
2.1
1.4
VOH
VCC = 3.0V
VCC = 1.8V
IIN
Input Leakage Current I/O pin
Pull/Buss keeper Resistor
Reset pin Pull-up Resistor
1
µA
RP
k
RRST
25
4
(3)tr
Rise time
No load
ns
slew rate limitation
7
Notes:
1. The sum of all IOH for PORTA and PORTB must not exceed 100mA.
The sum of all IOH for PORTC, PORTD, PORTE and PDI must for each port not exceed 200mA
TThe sum of all IOH for PORTG and PORTM must not exceed 100mA.
The sum of all IOH for PORTR must not exceed 100mA.
2. The sum of all IOL for PORTA and PORTB must not exceed 100mA.
The sum of all IOL for PORTC, PORTD, PORTE must for each port not exceed 200mA.
The sum of all IOL for PORTG and PORTM must not exceed 100mA.
The sum of all IOL PORTR must not exceed 100mA.
3. From design simulations
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36.6 Liquid Crystal Display Characteristics
Table 36-8. Liquid crystal display characteristics.
Symbol
SEG
Parameter
Condition
Min
0
Typ
Max
40
Units
Segment terminal pins
Common terminal pins
LCD frame frequency
Flying capacitor
COM
0
4
fFrame
F(clkLCD)=32.768kHz
31.25
512
Hz
nF
CFlying
100
Contrast Contrast adjustment
VLCD
-0.5
0
3
0.5
CFlying = 0.1µF
0.1µF on VLCD, BIAS2 and
BIAS1 pins
V
BIAS2
BIAS1
RCOM
RSEG
LCD regulated voltages
2*VLCD/3
VLCD/3
0.5
Common output impedance
Segment output impedance
COM0 to COM3(1)
SEG0 to SEG39(1)
0.25
2
1
8
k
4
Notes:
1. Applies to Static and 1/3 bias
36.7 ADC characteristics
Table 36-9. Power supply, reference and input range.
Symbol
AVCC
Parameter
Condition
Min.
VCC- 0.3
1
Typ.
Max.
Units
Analog supply voltage
Reference voltage
Input resistance
VCC+ 0.3
AVCC- 0.6
4.5
V
VREF
Rin
Cin
RAREF
Switched
k
pF
Input capacitance
Reference input resistance
Switched
5
(leakage only)
>10
7
M
pF
CAREF
Vin
Reference input capacitance Static load
Input range
0
VREF
Vin
Conversion range
Conversion range
Differential mode, Vinp - Vinn
-0.95*VREF
-0.05*VREF
0.95*VREF
0.95*VREF
V
Vin
Single ended unsigned mode, Vinp
Table 36-10. Clock and timing.
Symbol
ClkADC
fClkADC
Parameter
Condition
Min.
Typ.
Max.
Units
kHz
Maximum is 1/4 of Peripheral clock
frequency
100
1800
ADC Clock frequency
Sample rate
Measuring internal signals
125
16
300
ksps
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Symbol
Parameter
Condition
Current limitation (CURRLIMIT) off
CURRLIMIT = LOW
Min.
Typ.
Max.
300
250
150
50
Units
ksps
µs
16
fADC
Sample rate
CURRLIMIT = MEDIUM
CURRLIMIT = HIGH
Sampling Time
1/2 ClkADC cycle
0.25
6
5
(RES+2)/2+(GAIN !=0)
RES (Resolution) = 8 or 12
ClkADC
cycles
Conversion time (latency)
10
Start-up time
ADC clock cycles
12
7
24
7
ClkADC
cycles
ADC settling time
After changing reference or input mode
Table 36-11. Accuracy characteristics.
Symbol
RES
Parameter
Resolution
Resolution
Resolution
Condition(2)
Min.
Typ.
12
11
12
1
Max.
12
Units
Differential
8
7
8
RES
12-bit resolution
Single ended signed
Single ended unsigned
16kSPS, VREF = 3V
16kSPS, VREF = 1V
300kSPS, VREF = 3V
300kSPS, VREF = 1V
16kSPS, VREF = 3.0V
16kSPS, VREF = 1.0V
16kSPS, VREF = 3V
16kSPS, VREF = 1V
300kSPS, VREF = 3V
300kSPS, VREF = 1V
16kSPS, VREF = 3.0V
16kSPS, VREF = 1.0V
11
Bits
RES
12
2
Differential mode
1
INL(1)
Integral non-linearity
2
1
1.5
3
Single ended
unsigned mode
2
lsb
1
2
Differential mode
1
DNL(1)
Differential non-linearity
2
1
1.5
3
Single ended
unsigned mode
2
8
mV
Offset Error
Differential mode
Temperature drift
0.01
mV/K
mV/V
Operating voltage drift
0.25
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Symbol
Parameter
Condition(2)
External reference
Min.
Typ.
-5
Max.
Units
AVCC/1.6
AVCC/2.0
-5
mV
-6
Gain Error
Differential mode
Bandgap
±10
0.02
2
Temperature drift
Operating voltage drift
External reference
AVCC/1.6
mV/K
mV/V
-8
-8
mV
AVCC/2.0
-8
Single ended
unsigned mode
Gain Error
Bandgap
±10
0.03
2
Temperature drift
Operating voltage drift
mV/K
mV/V
Notes:
1. Maximum numbers are based on characterisation and not tested in production, and valid for 10% to 90% input voltage range.
2. Unless otherwise noted all linearity, offset and gain error numbers are valid under the condition that external VREF is used.
Table 36-12. Gain stage characteristics.
Symbol
Rin
Csample
Parameter
Condition
Switched in normal mode
Min.
Typ.
4.0
Max.
Units
k
Input resistance
Input capacitance
Signal range
Switched in normal mode
Gain stage output
4.4
pF
0
AVCC- 0.3
1800
V
ClkADC
cycles
Propagation delay
Clock rate
ADC conversion rate
1
Same as ADC
100
kHz
0.5x gain, normal mode
1x gain, normal mode
8x gain, normal mode
64x gain, normal mode
0.5x gain, normal mode
1x gain, normal mode
8x gain, normal mode
64x gain, normal mode
-1
-1
Gain error
%
-1
10
10
10
Offset error,
mV
input referred
-20
-150
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36.8 Analog Comparator Characteristics
Table 36-13. Analog comparator characteristics.
Symbol Parameter
Condition
Min.
Typ.
10
Max.
Units
mV
nA
Voff
Ilk
Input offset voltage
Input leakage current
Input voltage range
AC startup time
<10
50
0.1
AVCC- 0.1
V
50
0
µs
Vhys1
Vhys2
Vhys3
Hysteresis, none
Hysteresis, small
Hysteresis, large
VCC = 1.6V - 3.6V
VCC = 1.6V - 3.6V
VCC = 1.6V - 3.6V
12
28
22
21
mV
ns
VCC = 3.0V, T= 85°C
30
40
tdelay
Propagation delay
VCC = 1.6V - 3.6V
64-Level Voltage Scaler Integral non-
linearity (INL)
0.3
5
0.5
lsb
%
Current source accuracy after calibration
Current source calibration range
Current source calibration range
Single mode
Double mode
4
8
6
µA
12
36.9 Bandgap and Internal 1.0V Reference Characteristics
Table 36-14. Bandgap and internal 1.0V reference characteristics.
Symbol Parameter
Condition
As reference for ADC
Min
Typ
Max
Units
1 ClkPER + 2.5µs
Startup time
µs
As input voltage to ADC and AC
1.5
1.1
1
Bandgap voltage
V
INT1V
Internal 1.00V reference for ADC
T= 85°C, After calibration
Calibrated at T= 85°C
0.99
1.01
Variation over voltage and temperature
2.25
%
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36.10 Brownout Detection Characteristics
Table 36-15. Brownout Detection Characteristics(1)
.
Symbol Parameter
BOD level 0 falling Vcc
BOD level 1 falling Vcc
BOD level 2 falling Vcc
BOD level 3 falling Vcc
BOD level 4 falling Vcc
BOD level 5 falling Vcc
BOD level 6 falling Vcc
BOD level 7 falling Vcc
Condition
T = 85C, calibrated
Min
Typ
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
0.4
1000
1.6
Max
Units
1.5
1.72
V
Continuous mode
Sampled mode
tBOD
Detection time
Hysteresis
µs
%
VHYST
Note:
1. BOD is calibrated at 85°C within BOD level 0 values, and BOD level 0 is the default level.
36.11 External Reset Characteristics
Table 36-16. External reset characteristics.
Symbol Parameter
Condition
Min
Typ
Max
Units
tEXT
Minimum reset pulse width
90
1000
ns
VCC = 2.7 - 3.6V
VCC = 1.6 - 2.7V
0.50*VCC
0.40*VCC
VRST
Reset threshold voltage
V
36.12 Power-on Reset Characteristics
Table 36-17. Power-on reset characteristics.
Symbol Parameter
Condition
Min
0.4
0.8
Typ
1.0
1.3
1.3
Max
Units
VCC falls faster than 1V/ms
VCC falls at 1V/ms or slower
(1)
VPOT-
POR threshold voltage falling VCC
POR threshold voltage rising VCC
V
VPOT+
1.59
Note:
1. Both VPOT- values are only valid when BOD is disabled. When BOD is enabled the µBOD is enabled, and VPOT- =VPOT+
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36.13 Flash and EEPROM Memory Characteristics
Table 36-18. Endurance and data retention.
Symbol Parameter
Condition
Min
10K
10K
100
25
Typ
Max
Units
25°C
85°C
25°C
55°C
25°C
85°C
25°C
55°C
Write/Erase cycles
Cycle
Flash
Data retention
Year
Cycle
Year
100K
100K
100
25
Write/Erase cycles
Data retention
EEPROM
Table 36-19. Programming time.
Symbol Parameter
Condition
Min
Typ(1)
Max
Units
128KB Flash, EEPROM(2)
64KB Flash, EEPROM(2)
Page Erase
75
55
4
Chip Erase
Flash
Page Write
4
ms
Page Write Automatic Page Erase and Write
Page Erase
8
4
EEPROM
Page Write
4
Page Write Automatic Page Erase and Write
8
Notes:
1. Programming is timed from the 2MHz internal oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
36.14 Clock and Oscillator Characteristics
36.14.1 Calibrated 32.768kHz Internal Oscillator characteristics
Table 36-20. Calibrated 32.768kHz internal oscillator characteristics.
Symbol Parameter
Condition
Min
Typ
Max
Units
Frequency
32.768
kHz
Factory calibrated accuracy
User calibration accuracy
T = 85C, VCC = 3.0V
-0.5
-0.5
0.5
0.5
%
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36.14.2 Calibrated 2MHz RC Internal Oscillator characteristics
Table 36-21. Calibrated 2MHz internal oscillator characteristics.
Symbol Parameter
Frequency range
Condition
Min
Typ
Max
Units
DFLL can tune to this frequency over
voltage and temperature
1.8
2.2
MHz
Factory calibrated frequency
Factory calibration accuracy
User calibration accuracy
DFLL calibration stepsize
2.0
T = 85C, VCC= 3.0V
-1.5
-0.2
1.5
0.2
%
0.22
36.14.3 Calibrated and tunable 32MHz Internal Oscillator characteristics
Table 36-22. Calibrated 32MHz internal oscillator characteristics.
Symbol Parameter
Frequency range
Condition
Min
Typ
Max
Units
DFLL can tune to this frequency over
voltage and temperature
30
35
MHz
Factory calibrated frequency
Factory calibration accuracy
User calibration accuracy
DFLL calibration step size
32
T = 85C, VCC= 3.0V
-1.5
-0.2
1.5
0.2
%
0.23
36.14.4 32kHz Internal ULP Oscillator characteristics
Table 36-23. 32kHz internal ULP oscillator characteristics.
Symbol Parameter
Condition
Min
Typ
Max
Units
kHz
%
Factory calibrated frequency
32
Factory calibration accuracy
T = 85C, VCC= 3.0V
-12
12
36.14.5 Phase Locked Loop (PLL) characteristics
Table 36-24. Calibrated 32MHz internal oscillator characteristics.
Symbol Parameter Condition
Min
0.4
20
Typ
Max
64
Units
fIN
Input Frequency
Output frequency must be within fOUT
VCC= 1.60V
32
MHz
fOUT
Output frequency(1)
VCC= 2.70V
20
128
100
50
Start-up time
re-lock time
23
20
µs
Note:
1. The maximum output frequency vs. supply voltage is linear between 1.8V and 2.7V, and can never be higher than 4 times the maximum CPU frequency.
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36.14.6 External Clock Characteristics
Figure 36-3. External Clock Drive Waveform
tCH
tCH
tCR
tCF
VIH1
VIL1
tCL
tCK
Table 36-25. External clock used as system clock without prescaling.
Symbol Parameter
Condition
Min
0
Typ
Max
12
Units
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
1/tCK
Clock frequency(1)
Clock period
MHz
0
32
83.3
31.5
30.0
12.5
30.0
12.5
tCK
tCH
Clock high time
tCL
Clock low time
ns
10
3
tCR
Rise time (for maximum frequency)
10
3
tCF
Fall time (for maximum frequency)
tCK
Change in period from one clock cycle to the next
10
%
Note:
1. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions.
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Table 36-26. External clock with prescaler(1) for system clock
Symbol Parameter
Condition
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
VCC = 1.6 - 1.8V
VCC = 2.7 - 3.6V
Min
0
Typ
Max
90
Units
1/tCK
Clock Frequency(2)
Clock Period
MHz
0
142
11
7
tCK
4.5
2.4
4.5
2.4
tCH
Clock High Time
Clock Low Time
ns
tCL
tCR
tCF
Rise Time (for maximum frequency)
1.5
1.5
10
Fall Time (for maximum frequency)
tCK
Change in period from one clock cycle to the next
%
Notes:
1. System Clock Prescalers must be set so that maximum CPU clock frequency for device is not exceeded.
2. The maximum frequency vs. supply voltage is linear between 1.8V and 2.7V, and the same applies for all other parameters with supply voltage conditions
36.14.7 External 16MHz crystal oscillator and XOSC characteristics
Table 36-27. External 16MHz crystal oscillator and XOSC characteristics.
Symbol Parameter
Condition
Min.
Typ.
0
Max.
Units
XOSCPWR=0, FRQRANGE=0
XOSCPWR=0, FRQRANGE=1, 2, or 3
XOSCPWR=1
Cycle to cycle jitter
0
0
ns
XOSCPWR=0, FRQRANGE=0
XOSCPWR=0, FRQRANGE=1, 2, or 3
XOSCPWR=1
0
Long term jitter
Frequency error
0
0
XOSCPWR=0, FRQRANGE=0
XOSCPWR=0, FRQRANGE=1
XOSCPWR=0, FRQRANGE=2 or 3
XOSCPWR=1
0.03
0.03
0.03
0.03
50
50
50
50
%
XOSCPWR=0, FRQRANGE=0
XOSCPWR=0, FRQRANGE=1
XOSCPWR=0, FRQRANGE=2 or 3
XOSCPWR=1
Duty cycle
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Symbol Parameter
Condition
Min.
Typ.
44k
Max.
Units
0.4MHz resonator, CL=100pF
1MHz crystal, CL=20pF
2MHz crystal, CL=20pF
2MHz crystal
XOSCPWR=0,
FRQRANGE=0
67k
67k
82k
XOSCPWR=0,
FRQRANGE=1,
CL=20pF
8MHz crystal
1500
1500
2700
2700
1000
3600
1300
590
9MHz crystal
8MHz crystal
XOSCPWR=0,
FRQRANGE=2,
CL=20pF
9MHz crystal
12MHz crystal
9MHz crystal
XOSCPWR=0,
FRQRANGE=3,
CL=20pF
12MHz crystal
16MHz crystal
9MHz crystal
Negative impedance (1)
RQ
390
XOSCPWR=1,
FRQRANGE=0,
CL=20pF
12MHz crystal
16MHz crystal
9MHz crystal
50
10
1500
650
XOSCPWR=1,
FRQRANGE=1,
CL=20pF
12MHz crystal
16MHz crystal
12MHz crystal
270
XOSCPWR=1,
FRQRANGE=2,
CL=20pF
1000
16MHz crystal
12MHz crystal
16MHz crystal
440
1300
590
XOSCPWR=1,
FRQRANGE=3,
CL=20pF
XOSCPWR=0,
FRQRANGE=0
0.4MHz resonator, CL=100pF
2MHz crystal, CL=20pF
8MHz crystal, CL=20pF
12MHz crystal, CL=20pF
16MHz crystal, CL=20pF
1.0
2.6
0.8
1.0
1.4
XOSCPWR=0,
FRQRANGE=1
XOSCPWR=0,
FRQRANGE=2
Start-up time
ms
XOSCPWR=0,
FRQRANGE=3
XOSCPWR=1,
FRQRANGE=3
CXTAL1
CXTAL2
CLOAD
Parasitic capacitance
Parasitic capacitance
Parasitic capacitance load
5.9
8.3
3.5
pF
Note:
1. Numbers for negative impedance are not tested but guaranteed from design and characterization.
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36.14.8 External 32.768kHz crystal oscillator and TOSC characteristics
Table 36-28. External 32.768kHz crystal oscillator and TOSC characteristics.
Symbol Parameter
Condition
Crystal load capacitance 6.5pF
Crystal load capacitance 9.0pF
Crystal load capacitance 12.0pF
Normal mode
Min
Typ
Max
60
Units
Recommended crystal equivalent
series resistance (ESR)
ESR/R1
35
k
28
3.5
3.5
CIN_TOSC Input capacitance between TOSC pins
pF
%
Low power mode
capacitance load matched to
crystal specification
Recommended Safety factor
Long term Jitter (SIT)
3
0
Note:
1. See Figure 36-4 on page 84 for definition
Figure 36-4. TOSC input capacitance
CL1
CL2
Device internal
External
TOSC1
TOSC2
32.768kHz crystal
The input capacitance between the TOSC pins is CL1 + CL2 in series as seen from the crystal when oscillating without
external capacitors.
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36.15 SPI characteristics
Figure 36-5. SPI interface requirements in master mode
SS
tMOS
tSCKR
tSCKF
SCK
(CPOL = 0)
tSCKW
SCK
(CPOL = 1)
tSCKW
tMIS
tMIH
MSB
tSCK
MISO
(Data Input)
LSB
tMOH
tMOH
MOSI
(Data Output)
MSB
LSB
Figure 36-6. SPI timing requirements in slave mode
SS
tSSS
tSCKR
tSCKF
tSSH
SCK
(CPOL = 0)
tSSCKW
SCK
(CPOL = 1)
tSSCKW
tSIS
tSIH
MSB
tSSCK
LSB
MOSI
(Data Input)
tSOSSS
tSOS
tSOSSH
MISO
(Data Output)
MSB
LSB
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Table 36-29. SPI Timing characteristics and requirements.
Symbol Parameter Condition
Min
Typ
Max
Units
(See Table 21-4 in
XMEGA B Manual)
tSCK
SCK Period
Master
tSCKW
tSCKR
tSCKF
tMIS
SCK high/low width
SCK Rise time
Master
Master
Master
Master
Master
Master
Master
0.5*SCK
2.7
SCK Fall time
2.7
MISO setup to SCK
MISO hold after SCK
MOSI setup SCK
MOSI hold after SCK
11
tMIH
0
0.5*SCK
1
tMOS
tMOH
tSSCK
tSSCKW
tSSCKR
tSSCKF
tSIS
Slave SCK Period
SCK high/low width
SCK Rise time
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
Slave
4*t ClkPER
2*t ClkPER
ns
1600
1600
SCK Fall time
MOSI setup to SCK
MOSI hold after SCK
SS setup to SCK
3
t ClkPER
21
tSIH
tSSS
tSSH
SS hold after SCK
MISO setup SCK
20
tSOS
8
13
11
8
tSOH
MISO hold after SCK
MISO setup after SS low
MISO hold after SS high
tSOSS
tSOSH
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36.16 Two-Wire Interface Characteristics
Table 2-1 describes the requirements for devices connected to the Two Wire Serial Bus. The XMEGA Two-Wire Interface
meets or exceeds these requirements under the noted conditions. Timing symbols refer to Figure 36-7.
Figure 36-7. Two-Wire Interface Bus Timing
tof
tHIGH
tLOW
tr
SCL
SDA
tHD;DAT
tSU;STA
tSU;STO
tSU;DAT
tHD;STA
tBUF
Table 36-30. Two wire serial bus characteristics.
Symbol Parameter
Condition
Min
Typ
Max
VCC+0.5
0.3*VCC
0
Units
VIH
VIL
Input High Voltage
0.7*VCC
-0.5
Input Low Voltage
V
(1)
Vhys
Hysteresis of Schmitt Trigger Inputs
Output Low Voltage
0.05VCC
VOL
3mA, sink current
0
20+0.1Cb
20+0.1Cb
0
0.4
(1)(2)
(1)(2)
tr
tof
Rise Time for both SDA and SCL
Output Fall Time from VIHmin to VILmax
Spikes Suppressed by Input Filter
Input Current for each I/O Pin
Capacitance for each I/O Pin
SCL Clock Frequency
300
250
50
10pF < Cb < 400pF(2)
0.1VCC < VI < 0.9VCC
ns
tSP
II
-10
10
µA
pF
CI
10
fSCL
fPER(3)>max(10fSCL, 250kHz)
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
0
400
kHz
VCC – 0.4V
---------------------------
3mA
100ns
300ns
--------------
--------------
RP
Value of Pull-up resistor
Cb
Cb
4.0
0.6
4.7
1.3
4.0
0.6
4.7
0.6
tHD;STA
Hold Time (repeated) START condition
Low Period of SCL Clock
tLOW
µs
tHIGH
High Period of SCL Clock
tSU;STA
Set-up time for a repeated START condition
XMEGA B1 [DATASHEET]
87
8330C–AVR–07/2012
Symbol Parameter
Condition
fSCL 100kHz
Min
0
Typ
Max
3.5
Units
tHD;DAT
tSU;DAT
tSU;STO
tBUF
Data hold time
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
fSCL 100kHz
fSCL > 100kHz
0
0.9
250
100
4.0
0.6
4.7
1.3
Data setup time
µs
Setup time for STOP condition
Bus free time between a STOP and START
condition
Notes:
1. Required only for fSCL > 100kHz
2. Cb = Capacitance of one bus line in pF
3.
fPER = Peripheral clock frequency
XMEGA B1 [DATASHEET]
88
8330C–AVR–07/2012
37. Typical Characteristics
37.1 Current consumption
37.1.1 Active mode supply current
Figure 37-1. Active supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
1000
900
800
700
600
500
400
300
200
100
3.6V
3.0V
2.7V
2.2V
1.8V
1.6V
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
Figure 37-2. Active supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
14
12
10
8
3.6V
3.0V
2.7V
6
2.2V
4
1.8V
2
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
XMEGA B1 [DATASHEET]
89
8330C–AVR–07/2012
Figure 37-3. Active mode supply current vs. VCC
.
fSYS = 2MHz internal oscillator.
2100
1900
1700
1500
1300
1100
900
-40°C
25°C
85°C
700
500
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 37-4. Active mode supply current vs. VCC
.
fSYS = 32MHz internal oscillator.
14000
13250
12500
11750
11000
10250
9500
-40 °C
25 °C
85 °C
8750
8000
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
Vcc [V]
XMEGA B1 [DATASHEET]
90
8330C–AVR–07/2012
37.1.2 Idle mode supply current
Figure 37-5. Idle mode supply current vs. frequency.
fSYS = 0 - 1MHz external clock, T = 25°C.
180
160
140
120
100
80
3.6V
3.0V
2.7V
2.2V
1.8V
1.6V
60
40
20
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
Figure 37-6. Idle mode supply current vs. frequency.
fSYS = 1 - 32MHz external clock, T = 25°C.
6
5
4
3
2
3.6V
3.0V
2.7V
2.2V
1
1.8V
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
XMEGA B1 [DATASHEET]
91
8330C–AVR–07/2012
Figure 37-7. Idle mode supply current vs. VCC
.
fSYS = 32.768kHz internal oscillator.
34.5
33.75
33
-40°C
85°C
32.25
31.5
30.75
30
25°C
29.25
28.5
27.75
27
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-8. Idle mode supply current vs. VCC
.
fSYS = 2MHz internal oscillator.
450
425
400
375
350
325
300
275
250
225
200
175
150
-40°C
25°C
85°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA B1 [DATASHEET]
92
8330C–AVR–07/2012
Figure 37-9. Idle mode current vs. VCC
.
fSYS = 32MHz internal oscillator.
5800
-40 °C
25 °C
85 °C
5300
4800
4300
3800
3300
2800
2300
1800
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
37.1.3 Power-down mode supply current
Figure 37-10.Power-down mode supply current vs. Temperature.
All functions disabled.
2.5
2.25
2
3.0 V
2.7 V
2.2 V
1.8 V
1.75
1.5
1.25
1
0.75
0.5
0.25
0
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
XMEGA B1 [DATASHEET]
93
8330C–AVR–07/2012
Figure 37-11.Power-down mode supply current vs. Temperature.
Watchdog and sampled BOD enabled.
3.5
3.25
3
3.0 V
2.7 V
2.2 V
1.8 V
2.75
2.5
2.25
2
1.75
1.5
1.25
1
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [°C]
37.2 I/O Pin Characteristics
37.2.1 Pull-up
Figure 37-12.I/O pin pull-up resistor current vs. input voltage.
VCC = 1.8V.
80
70
60
50
40
30
20
10
0
85°C
25°C
-40°C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VPIN [V]
XMEGA B1 [DATASHEET]
94
8330C–AVR–07/2012
Figure 37-13.I/O pin pull-up resistor current vs. input voltage.
VCC = 3.0V.
140
120
100
80
60
40
85°C
25°C
20
-40°C
0
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
VPIN [V]
Figure 37-14.I/O pin pull-up resistor current vs. pin voltage.
VCC = 3.3V.
160
140
120
100
80
60
40
85°C
25°C
-40°C
20
0
0
0.35
0.7
1.05
1.4
1.75
2.1
2.45
2.8
3.15
3.5
VPIN [V]
XMEGA B1 [DATASHEET]
95
8330C–AVR–07/2012
37.2.2 Output Voltage vs. Sink/Source Current
Figure 37-15.I/O pin output voltage vs. source current.
VCC = 1.8V.
1.3
1.2
1.1
1
-40°C
25°C
85°C
0.9
0.8
0.7
0.6
-6
-5.4
-4.8
-4.2
-3.6
-3
-2.4
-1.8
-1.2
-0.6
0
IPIN [mA]
Figure 37-16.I/O pin output voltage vs. source current.
VCC = 3.0V.
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
-40°C
25°C
85°C
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
IPIN [mA]
XMEGA B1 [DATASHEET]
96
8330C–AVR–07/2012
Figure 37-17.I/O pin output voltage vs. source current.
VCC = 3.3V.
2.5
2.25
2
85°C
25°C
-40°C
1.75
1.5
1.25
1
-20
-18
-16
-14
-12
-10
-8
-6
-4
-2
0
IPIN [mA]
Figure 37-18.I/O pin output voltage vs. sink current.
VCC = 1.8V.
1.8
1.6
1.4
1.2
1
85°C
0.8
0.6
0.4
0.2
0
25°C
-40°C
0
2
4
6
8
10
12
14
16
18
20
IPIN [mA]
XMEGA B1 [DATASHEET]
97
8330C–AVR–07/2012
Figure 37-19.I/O pin output voltage vs. sink current.
VCC = 3.0V.
0.6
0.54
0.48
0.42
0.36
0.3
85°C
25°C
-40°C
0.24
0.18
0.12
0.06
0
0
2
4
6
8
10
12
14
16
18
20
IPIN [mA]
Figure 37-20.I/O pin output voltage vs. sink current.
VCC = 3.3V.
0.4
0.35
0.3
85°C
25°C
-40°C
0.25
0.2
0.15
0.1
0.05
0
0
2
4
6
8
10
12
14
16
18
20
IPIN [mA]
XMEGA B1 [DATASHEET]
98
8330C–AVR–07/2012
37.2.3 Thresholds and Hysteresis
Figure 37-21.I/O pin input threshold voltage vs. VCC
.
VIH I/O pin read as “1”.
1.8
1.6
1.4
1.2
1
-40°C
25°C
85°C
0.8
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-22.I/O pin input threshold voltage vs. VCC
.
VIL I/O pin read as “0”.
1.7
1.5
1.3
1.1
0.9
0.7
0.5
-40°C
25°C
85°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA B1 [DATASHEET]
99
8330C–AVR–07/2012
Figure 37-23.I/O pin input hysteresis vs. VCC
.
350
300
250
200
150
100
-40°C
25°C
85°C
1.6
1.8
2.0
2.2
2.4
2.6
2.8
3.0
3.2
3.4
3.6
VCC [V]
37.3 ADC Characteristics
Figure 37-24.ADC INL vs. VREF
.
Differential signed mode, VCC = 3.6V, external reference.
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
-40ºC
85ºC
25ºC
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
XMEGA B1 [DATASHEET]
100
8330C–AVR–07/2012
Figure 37-25.ADC INL vs. VREF
.
SE Unsigned mode, VCC = 3.6V, external reference.
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
1.3
1.1
0.9
0.7
0.5
85ºC
25ºC
-40ºC
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
Figure 37-26.ADC DNL vs. VREF
.
Differential signed mode, VCC = 3.6V, external reference.
2.1
2
1.9
1.8
1.7
1.6
1.5
1.4
1.3
1.2
1.1
1
-40ºC
85ºC
25ºC
0.9
0.8
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
XMEGA B1 [DATASHEET]
101
8330C–AVR–07/2012
Figure 37-27.ADC DNL vs. VREF
.
SE Unsigned mode, VCC = 3.6V, external reference.
3.0
2.8
2.6
2.4
2.2
2.0
1.8
1.6
1.4
1.2
1.0
-40ºC
25ºC
85ºC
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
Figure 37-28.ADC Offset vs. VCC
.
SE Unsigned mode, VREF = 1.0V, external reference.
14
85ºC
12
10
8
25ºC
-40ºC
6
4
2
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA B1 [DATASHEET]
102
8330C–AVR–07/2012
Figure 37-29.ADC Offset vs. VREF
.
SE Unsigned mode, VCC = 3.6V, external reference.
19
18
17
16
15
14
13
12
11
10
9
85ºC
25ºC
-40ºC
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
Figure 37-30.ADC Offset vs. VREF
.
Differential signed mode, VCC = 3.6V, external reference.
10.0
9.0
8.0
7.0
6.0
5.0
4.0
3.0
2.0
85ºC
25ºC
-40ºC
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREFV]
XMEGA B1 [DATASHEET]
103
8330C–AVR–07/2012
Figure 37-31.ADC Offset vs. VCC
.
Differential signed mode, VREF = 1.0V, external reference.
-3
-3.5
-4
-4.5
-5
-5.5
-6
85ºC
25ºC
-6.5
-7
-7.5
-40ºC
-8
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-32.ADC Gain Error vs. VREF
.
Differential signed mode, external reference.
-1.0
-3.0
-5.0
-7.0
-9.0
-40ºC
25ºC
85ºC
-11.0
-13.0
-15.0
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
XMEGA B1 [DATASHEET]
104
8330C–AVR–07/2012
Figure 37-33.ADC Gain Error vs. VREF
.
SE Unsigned mode, external reference.
0.0
-1.0
-2.0
-3.0
-4.0
-5.0
-6.0
-7.0
-8.0
-9.0
-10.0
-40ºC
25ºC
85ºC
1
1.2
1.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
VREF [V]
Figure 37-34.ADC Gain Error vs. VCC
.
Differential signed mode, external reference.
-3.0
-3.5
-4.0
-4.5
-5.0
-5.5
-6.0
-6.5
-7.0
-7.5
25ºC
-40ºC
85ºC
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA B1 [DATASHEET]
105
8330C–AVR–07/2012
Figure 37-35.ADC Gain Error vs. VCC
.
SE Unsigned mode, external reference.
0
-1
-2
-3
-4
-5
-6
-7
-8
-40ºC
25ºC
85ºC
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-36.ADC Gain Error vs. Temperature.
Differential signed mode, external reference.
-5.0
-6.0
1.0V Vref
-7.0
1.5V Vref
2.0V Vref
-8.0
-9.0
-10.0
-11.0
-12.0
2.5V Vref
3.0V Vref
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [ºC]
XMEGA B1 [DATASHEET]
106
8330C–AVR–07/2012
Figure 37-37.ADC Gain Error vs. Temperature.
SE Unsigned mode, VCC = 3.6V, external reference.
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
-3.0
-4.0
-5.0
-6.0
-7.0
-8.0
-9.0
1.0V Vref
1.5V Vref
2.0V Vref
2.5V Vref
3.0V Vref
Temperature [ºC]
37.4 Analog Comparator Characteristics
Figure 37-38.Analog comparator hysteresis vs. VCC
.
High-speed mode, small hysteresis.
16
15
14
13
12
11
10
9
85ºC
25ºC
-40ºC
8
7
6
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
[V]
CC
XMEGA B1 [DATASHEET]
107
8330C–AVR–07/2012
Figure 37-39.Analog comparator hysteresis vs. VCC
.
High-speed mode, large hysteresis.
32
30
28
26
24
22
20
18
16
85°C
25°C
-40°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
[V]
CC
Figure 37-40.Analog comparator propagation delay vs. VCC
.
High speed mode.
34
32
30
28
26
24
22
20
18
16
85°C
25°C
40°C
-
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
Vcc [V]
XMEGA B1 [DATASHEET]
108
8330C–AVR–07/2012
Figure 37-41.Analog comparator current consumption vs. VCC
.
High-speed mode.
290
270
250
230
210
190
170
150
85°C
25°C
-40°C
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCM [V]
Figure 37-42.Analog comparator voltage scaler vs. SCALEFAC.
T = 25C.
4
3.5
3
3.6V
3.3V
3.0V
2.7V
2.5
2
1.8V
1.6V
1.5
1
0.5
0
0
7
14
21
28
35
42
49
56
63
SCALEFAC
XMEGA B1 [DATASHEET]
109
8330C–AVR–07/2012
Figure 37-43.Analog comparator offset voltage vs. Common mode voltage.
High-speed mode.
20
18
16
14
12
10
8
-40°C
25°C
85°C
6
4
2
0
0.5
0.7
0.9
1.1
1.3
1.5
1.7
1.9
2.1
2.3
2.5
2.7
2.9
3.1
3.3
3.5
V
[V]
CC
Figure 37-44.Analog comparator current source vs. Calibration.
VCC = 3.0V, double mode.
12
11.5
11
10.5
10
9.5
9
-40°C
25°C
85°C
8.5
8
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
CURRCALIBA[3..0]
XMEGA B1 [DATASHEET]
110
8330C–AVR–07/2012
37.5 Internal 1.0V reference Characteristics
Figure 37-45.ADC/DAC Internal 1.0V reference vs. temperature.
1.012
1.01
1.008
1.006
1.004
1.002
1
1.8V
2.7V
3.0V
0.998
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [°C]
37.6 BOD Characteristics
Figure 37-46.BOD current consumption vs. VCC
.
Continuous mode, BOD level = 1.6V.
150
140
130
120
110
100
90
85°C
25°C
-40°C
80
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA B1 [DATASHEET]
111
8330C–AVR–07/2012
Figure 37-47.BOD current consumption vs. VCC
.
Sampled mode, BOD level = 1.6V.
5
4.5
4
85°C
3.5
3
2.5
2
1.5
1
25°C
-40°C
0.5
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-48.BOD thresholds vs. temperature.
BOD level = 1.6V.
1.626
1.624
1.622
1.62
1.618
1.616
1.614
1.612
1.61
Rising Vcc
Falling Vcc
1.608
1.606
1.604
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [°C]
XMEGA B1 [DATASHEET]
112
8330C–AVR–07/2012
Figure 37-49.BOD thresholds vs. temperature.
BOD level = 2.2V.
2.35
2.345
2.34
Rising Vcc
2.335
2.33
2.325
2.32
2.315
2.31
Falling Vcc
2.305
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
Figure 37-50.BOD thresholds vs. temperature.
BOD level = 3.0V.
3.07
3.06
3.05
3.04
3.03
3.02
3.01
3
Rising Vcc
Falling Vcc
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [°C]
XMEGA B1 [DATASHEET]
113
8330C–AVR–07/2012
37.7 External Reset Characteristics
Figure 37-51.Minimum Reset pin pulse width vs. VCC
.
140
130
120
110
100
90
85°C
25°C
-40°C
80
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-52.Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 1.8V.
70
60
50
40
30
20
10
0
85°C
25°C
-40°C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
VRESET [V]
XMEGA B1 [DATASHEET]
114
8330C–AVR–07/2012
Figure 37-53.Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.0V.
140
120
100
80
60
40
85°C
20
25°C
-40°C
0
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
VRESET [V]
Figure 37-54.Reset pin pull-up resistor current vs. reset pin voltage.
VCC = 3.3V.
140
120
100
80
60
40
85°C
25°C
-40°C
20
0
0
0.3
0.6
0.9
1.2
1.5
1.8
2.1
2.4
2.7
3
3.3
VRESET [V]
XMEGA B1 [DATASHEET]
115
8330C–AVR–07/2012
Figure 37-55.Reset pin input threshold voltage vs. VCC.
VIH - Reset pin read as “1”.
1.8
1.6
1.4
1.2
1
-40°C
25°C
85°C
0.8
0.6
0.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
Figure 37-56.Reset pin input threshold voltage vs. VCC.
VIL - Reset pin read as “0”.
1.8
1.6
1.4
1.2
1
-40 °C
25 °C
85 °C
0.8
0.6
0.4
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA B1 [DATASHEET]
116
8330C–AVR–07/2012
37.8 Oscillator Characteristics
37.8.1 32.768kHz Internal Oscillator
Figure 37-57.32.768kHz internal oscillator frequency vs. temperature.
32.83
32.82
32.81
32.8
1.8V
1.6V
2.2V
3.6V
2.7V
3.0V
32.79
32.78
32.77
32.76
32.75
32.74
32.73
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [°C]
Figure 37-58.32.768kHz ULP internal oscillator frequency vs. temperature.
36000
35500
35000
34500
34000
33500
33000
32500
32000
31500
31000
3.6V
3.0V
2.7V
1.8V
1.6V
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [°C]
XMEGA B1 [DATASHEET]
117
8330C–AVR–07/2012
Figure 37-59.32.768kHz internal oscillator calibration step size.
T = -40C to 85C, VCC = 3V.
0.01
0.005
0.000
-0.005
-0.01
85°C
25°C
-40°C
-0.015
-0.02
-0.025
-0.03
-0.035
-0.04
-0.045
0
32
64
96
128
160
192
224
256
RC32KCAL[7..0]
Figure 37-60.32.768kHz internal oscillator frequency vs. calibration value.
VCC = 3.0V, T = 25°C.
55
50
45
40
35
30
25
20
3.0 V
0
16
32
48
64
80
96
112 128 144 160 176 192 208 224 240 256
RC32KCAL[7..0]
XMEGA B1 [DATASHEET]
118
8330C–AVR–07/2012
37.8.2 2MHz Internal Oscillator
Figure 37-61.2MHz internal oscillator frequency vs. temperature.
DFLL disabled.
2.16
2.14
2.12
2.1
2.08
2.06
2.04
2.02
2.00
1.98
1.96
3.6 V
3.0 V
2.7 V
2.2 V
1.8 V
1.6 V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
Figure 37-62.2MHz internal oscillator frequency vs. temperature.
DFLL enabled.
2.006
2.005
2.004
2.003
2.002
2.001
2.000
1.999
1.6 V
2.2 V
1.8 V
2.7 V
3.0 V
3.6 V
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [°C]
XMEGA B1 [DATASHEET]
119
8330C–AVR–07/2012
Figure 37-63.2MHz internal oscillator CALA calibration step size.
VCC = 3V.
-0.14
-0.15
-0.16
-0.17
-0.18
-0.19
-0.2
85 °C
25 °C
-40 °C
-0.21
-0.22
-0.23
-0.24
-0.25
-0.26
-0.27
0
10
20
30
40
50
60
70
80
90
100
110
120
130
DFLLRC2MCALA
Figure 37-64.2MHz internal oscillator CALB calibration step size.
VCC = 3V, DFLL enabled.
-0.155
-0.165
-0.175
-0.185
-0.195
-0.205
-0.215
-0.225
-0.235
-0.245
-0.255
85°C
25°C
-40°C
0
7
14
21
28
35
42
49
56
63
DFLLRC2MCALB
XMEGA B1 [DATASHEET]
120
8330C–AVR–07/2012
37.8.3 32MHz Internal Oscillator
Figure 37-65.32MHz internal oscillator frequency vs. temperature.
DFLL disabled.
35.5
35
34.5
34
33.5
33
3.6V
3.0V
2.7V
2.2V
1.8V
1.6V
32.5
32
31.5
31
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
Figure 37-66.32MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
32.08
32.06
32.04
32.02
32
1.8V
3.3V
2.2V
1.6V
2.7V
3.0V
31.98
31.96
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
XMEGA B1 [DATASHEET]
121
8330C–AVR–07/2012
Figure 37-67.32MHz internal oscillator CALA calibration step size.
VCC = 3.0V.
-0.1
-0.12
-0.14
-0.16
-0.18
-0.2
25°C
85°C
-40°C
-0.22
-0.24
-0.26
-0.28
-0.3
0
10
20
30
40
50
60
70
80
90
100
110
120
130
DFLLRC32MCALA
Figure 37-68.32MHz internal oscillator CALB calibration step size.
VCC = 3.0V, CALA = mid value.
0.60
0.50
0.40
0.30
0.20
0.10
0.00
-0.10
-0.20
-0.30
-0.40
-40°C
25°C
85°C
0
8
16
24
32
40
48
56
64
DFLLRC32MCALB
XMEGA B1 [DATASHEET]
122
8330C–AVR–07/2012
Figure 37-69.32MHz internal oscillator frequency vs. CALA calibration value.
VCC = 3.0V.
56
54
52
50
48
46
44
42
40
38
36
-40°C
25°C
85°C
0
8
16
24
32
40
48
56
64
72
80
88
96
104 112 120 128
DFLLRC32MCALA
Figure 37-70.32MHz internal oscillator frequency vs. CALB calibration value.
VCC = 3.0V, DFLL enabled.
70
65
60
55
50
45
40
35
30
25
20
-40°C
25°C
85°C
0
7
14
21
28
35
42
49
56
63
DFLLRC32MCALB
XMEGA B1 [DATASHEET]
123
8330C–AVR–07/2012
37.8.4 32MHz internal oscillator calibrated to 48MHz
Figure 37-71.48MHz internal oscillator frequency vs. temperature.
DFLL disabled.
53
52
51
50
49
48
47
46
3.6V
3.0V
2.7V
2.2V
1.8V
1.6V
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
Figure 37-72.48MHz internal oscillator frequency vs. temperature.
DFLL enabled, from the 32.768kHz internal oscillator.
48.12
48.1
1.8V
2.2V
3.6V
3.0V
1.6V
2.7V
48.08
48.06
48.04
48.02
48
47.98
47.96
47.94
47.92
-45
-35
-25
-15
-5
5
15
25
35
45
55
65
75
85
Temperature [°C]
XMEGA B1 [DATASHEET]
124
8330C–AVR–07/2012
Figure 37-73. 32MHz internal oscillator CALA calibration step size.
Using 48MHz calibration value from signature row, VCC = 3.0V.
0.80
0.60
0.40
0.20
0.00
-0.20
-0.40
-0.60
-40°C
85°C
25°C
0
8
16
24
32
40
48
56
64
72
80
88
96
104 112 120 128
CALA
Figure 37-74. 48MHz internal oscillator frequency vs. CALA calibration value.
VCC = 3.0V.
60
58
56
54
52
50
48
46
44
42
40
-40°C
25°C
85°C
0
8
16
24
32
40
48
56
64
72
80
88
96
104 112 120 128
CALA
XMEGA B1 [DATASHEET]
125
8330C–AVR–07/2012
37.9 PDI characteristics
Figure 37-75.Maximum PDI frequency vs. VCC
.
20.5
20.0
19.5
19.0
18.5
18.0
17.5
17.0
25°C
-40°C
85°C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
XMEGA B1 [DATASHEET]
126
8330C–AVR–07/2012
37.10 LCD Characteristics
Figure 37-76.ICC vs. Frame Rate
32Hz Low P ower Frame Rate from 32.768KHz TOSC, w/ and w/o pixel load, VCC = 1.8V, T = 25°C
11
10
9
22pF All Pixels ON
8
22pF All Pixels OFF
7
6
5
0pF All Pixels ON
0pF All Pixels OFF
4
3
32
64
96
128
160
192
224
256
Frame Rate[Hz]
Figure 37-77.ICC vs. Frame Rate
32Hz Low P ower Frame Rate from 32.768KHz TOSC, w/ and w/o pixel load, VCC = 3.0V, T = 25°C
13
12
11
10
9
22pF All Pixels ON
22pF 100 Pixels ON
8
7
22pF All Pixels OFF
6
0pF All Pixels ON
0pF 100 Pixels ON
5
4
0pF All Pixels OFF
3
32
64
96
128
160
192
224
256
Frame Rate[Hz]
XMEGA B1 [DATASHEET]
127
8330C–AVR–07/2012
Figure 37-78.ICC vs. Frame Rate
0pF load
15
13
11
9
85°C
25°C
-40°C
7
5
3
32
64
96
128
160
192
224
256
Frame Rate[Hz]
Figure 37-79.ICC vs. Contrast
32Hz Low Power Frame Rate from 32.768KHz TOSC, w/o pixel load, VCC = 1.8V
7.5
7
6.5
6
85°C
5.5
5
25°C
4.5
4
-40°C
3.5
3
-32
-23
-14
-5
4
13
22
31
Contrast
XMEGA B1 [DATASHEET]
128
8330C–AVR–07/2012
Figure 37-80.ICC vs. Contrast
32Hz Low Power Frame Rate from 32.768KHz TOSC, w/o pixel load, VCC = 3.0V
7.5
7
85°C
6.5
6
5.5
5
25°C
4.5
4
-40°C
3.5
3
-32
-23
-14
-5
4
13
22
31
Contrast
Figure 37-81.Psave LCD LP 32Hz vs. Temperature
3.2
3
2.8
2.6
2.4
2.2
2
3.6V
3.0V
2.2V
1.8V
1.6V
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [°C]
XMEGA B1 [DATASHEET]
129
8330C–AVR–07/2012
Figure 37-82.Psave LCD LP 32Hz vs. Temperature
RTC, WDT, BOD sampled
3.6
3.4
3.2
3.0
2.8
2.6
2.4
2.2
2.0
3.6V
3.0V
2.2V
1.8V
1.6V
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [°C]
Figure 37-83.Psave vs. Temperature
RTC, WDT, BOD sampled.
0.3
0.275
0.25
3.6V
0.225
0.2
3.0V
2.2V
0.175
1.8V
1.6V
0.15
-40
-30
-20
-10
0
10
20
30
40
50
60
70
80
Temperature [°C]
XMEGA B1 [DATASHEET]
130
8330C–AVR–07/2012
38. Errata
38.1 ATxmega64B1, ATxmega128B1
38.1.1 Rev. C
• Device revision number
• AWeX fault protection restore is not done correct in Pattern Generation Mode
1. Device revision number is unchanged between rev. B and rev. C
2. AWeX fault protection restore is not done correctly in Pattern Generation Mode
When a fault is detected the OUTOVEN register is cleared, and when fault condition is cleared, OUTOVEN is
restored according to the corresponding enabled DTI channels. For Common Waveform Channel Mode (CWCM),
this has no effect as the OUTOVEN is correct after restoring from fault. For Pattern Generation Mode (PGM),
OUTOVEN should instead have been restored according to the DTILSBUF register.
Problem fix/Workaround
For CWCM no workaround is required.
For PGM in latched mode, disable the DTI channels before returning from the fault condition. Then, set correct
OUTOVEN value and enable the DTI channels, before the direction (DIR) register is written to enable the correct
outputs again.
For PGM in cycle-by-cycle mode there is no workaround.
38.1.2 Rev. B
Not sampled.
38.1.3 Rev. A
• Power down consumption
• ADC conversion error when x0.5 gain is used
1. Power Down consumption
After reset, when system enters in power down or when ADC is disabled, extra power consumption is drawn.
Problem fix/Workaround
Set ADC to a configuration different from differential mode.
2. ADC conversion error when x0.5 gain is used
When the gain is set to x0.5, the conversion result is similar to the gain setting x1.
Problem fix/Workaround
There is no workaround.
XMEGA B1 [DATASHEET]
131
8330C–AVR–07/2012
39. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The referring revision in this
section are referring to the document revision.
39.1 8386C –07/2012
1.
2.
3.
Updated the Table 32-4 on page 56. PDI_CLOCK is on pin 16 and PDI_DATA on pin 15.
Updated the datasheet using the Atmel new template.
Updated “Errata” , “Rev. C” on page 131: “JTAG revision” replaced by “Device revision number”.
39.2 8386B –02/2012
1.
Updated the Table 7-2 on page 14. The page size (words) for ATxmega128B1 changed from 256
to 128.
2.
3.
4.
Updated all “Electrical Characteristics” on page 67.
Updated all “Typical Characteristics” on page 89.
Updated “Errata” on page 131.
39.3 8386A – 10/2011
1.
Initial revision.
XMEGA B1 [DATASHEET]
132
8330C–AVR–07/2012
Table Of Contents
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2. Pinout/Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
3. Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
3.1
Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
4. Resources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4.1
Recommended reading. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
5. Capacitive touch sensing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
6. AVR CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
6.1
6.2
6.3
6.4
6.5
6.6
6.7
6.8
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
ALU - Arithmetic Logic Unit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Program Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Stack and Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Register File . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
7. Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Flash Program Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Fuses and Lock bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Data Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
I/O Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Data Memory and Bus Arbitration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Memory Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.10 Device ID and Revision. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7.11 JTAG Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.12 I/O Memory Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7.13 Flash and EEPROM Page Size . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
8. DMAC – Direct Memory Access Controller . . . . . . . . . . . . . . . . . . . 15
8.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
8.2
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
9. Event System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
9.2
Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
10. System Clock and Clock options . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
10.3 Clock Sources. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
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11. Power Management and Sleep Modes . . . . . . . . . . . . . . . . . . . . . . 21
11.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
11.3 Sleep Modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
12. System Control and Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.3 Reset Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
12.4 Reset Sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
13. WDT – Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
13.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
14. Interrupts and Programmable Multilevel Interrupt Controller . . . . . . 26
14.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
14.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
14.3 Interrupt vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
15. I/O Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
15.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
15.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
15.3 Output Driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
15.4 Input sensing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
15.5 Alternate Port Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
16. T/C – 16-bit Timer/Counter Type 0 and 1 . . . . . . . . . . . . . . . . . . . . 32
16.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
16.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
17. TC2 –16-bit Timer/Counter Type 2 . . . . . . . . . . . . . . . . . . . . . . . . . 34
17.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
17.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
18. AWeX – Advanced Waveform Extension . . . . . . . . . . . . . . . . . . . . . 35
18.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
18.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
19. Hi-Res – High Resolution Extension . . . . . . . . . . . . . . . . . . . . . . . . 36
19.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
19.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
20. RTC – 16-bit Real-Time Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
20.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
20.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
21. USB – Universal Serial Bus Interface . . . . . . . . . . . . . . . . . . . . . . . 38
21.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
21.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
22. TWI – Two Wire Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
22.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
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22.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
23. SPI – Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
23.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
23.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
24. USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
24.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
24.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
25. IRCOM – IR Communication Module . . . . . . . . . . . . . . . . . . . . . . . . 43
25.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
25.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
26. AES and DES Crypto Engine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
26.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
26.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
27. CRC – Cyclic Redundancy Check Generator . . . . . . . . . . . . . . . . . 45
27.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
27.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
28. LCD - Liquid Crystal Display Controller . . . . . . . . . . . . . . . . . . . . . . 46
28.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
28.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
29. ADC – 12-bit Analog to Digital Converter . . . . . . . . . . . . . . . . . . . . 47
29.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
29.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
30. AC – Analog Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
30.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
30.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
31. Programming and Debugging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
31.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
31.2 Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51
32. Pinout and Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
32.1 Alternate Pin Function Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
32.2 Alternate Pin Functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55
33. Peripheral Module Address Map . . . . . . . . . . . . . . . . . . . . . . . . . . . 59
34. Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61
35. Packaging information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
35.1 100A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
36. Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
36.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
36.2 General Operating Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
36.3 DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
36.4 Wake-up time from sleep modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
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36.5 I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
36.6 Liquid Crystal Display Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
36.7 ADC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
36.8 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
36.9 Bandgap and Internal 1.0V Reference Characteristics. . . . . . . . . . . . . . . . . . 77
36.10 Brownout Detection Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
36.11 External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
36.12 Power-on Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78
36.13 Flash and EEPROM Memory Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . 79
36.14 Clock and Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
36.15 SPI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
36.16 Two-Wire Interface Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
37. Typical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
37.1 Current consumption. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
37.2 I/O Pin Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
37.3 ADC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
37.4 Analog Comparator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
37.5 Internal 1.0V reference Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
37.6 BOD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
37.7 External Reset Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
37.8 Oscillator Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
37.9 PDI characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
37.10 LCD Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
38. Errata . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
38.1 ATxmega64B1, ATxmega128B1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
39. Datasheet Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
39.1 8386C –07/2012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
39.2 8386B –02/2012 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
39.3 8386A – 10/2011. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
Table Of Contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i
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Atmel Corporation
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