ATXMEGA64D3-MH-SL383 [ATMEL]
Microcontroller;型号: | ATXMEGA64D3-MH-SL383 |
厂家: | ATMEL |
描述: | Microcontroller 微控制器 |
文件: | 总96页 (文件大小:3301K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
Features
• High-performance, Low-power 8/16-bit AVR XMEGA Microcontroller
• Non-volatile Program and Data Memories
– 64K - 256K Bytes of In-System Self-Programmable Flash
– 4K - 8K Bytes Boot Code Section with Independent Lock Bits
– 2K - 4K Bytes EEPROM
– 4K - 16K Bytes Internal SRAM
• Peripheral Features
– Four-channel Event System
– Five 16-bit Timer/Counters
8/16-bit
XMEGA D3
Microcontroller
Four Timer/Counters with 4 Output Compare or Input Capture channels
One Timer/Counters with 2 Output Compare or Input Capture channels
High Resolution Extensions on two Timer/Counters
Advanced Waveform Extension on one Timer/Counter
– Three USARTs
IrDA Extension on 1 USART
– Two Two-Wire Interfaces with dual address match(I2C and SMBus compatible)
– Two SPI (Serial Peripheral Interfaces)
ATxmega256D3
ATxmega192D3
ATxmega128D3
ATxmega64D3
– 16-bit Real Time Counter with Separate Oscillator
– One Sixteen-channel, 12-bit, 200ksps Analog to Digital Converter
– Two Analog Comparators with Window compare function
– External Interrupts on all General Purpose I/O pins
– Programmable Watchdog Timer with Separate On-chip Ultra Low Power Oscillator
• Special Microcontroller Features
– Power-on Reset and Programmable Brown-out Detection
– Internal and External Clock Options with PLL
– Programmable Multi-level Interrupt Controller
– Sleep Modes: Idle, Power-down, Standby, Power-save, Extended Standby
– Advanced Programming, Test and Debugging Interface
PDI (Program and Debug Interface) for programming, test and debugging
• I/O and Packages
Preliminary
– 50 Programmable I/O Lines
– 64-lead TQFP
– 64-pad QFN
• Operating Voltage
– 1.6 – 3.6V
• Speed performance
– 0 – 12 MHz @ 1.6 – 3.6V
– 0 – 32 MHz @ 2.7 – 3.6V
Typical Applications
• Industrial control
• Factory automation
• Building control
• Board control
• Climate control
• ZigBee
• Hand-held battery applications
• Power tools
• HVAC
• Metering
• Medical Applications
• Motor control
• Networking
• Optical
• White Goods
8134D–AVR–12/09
XMEGA D3
1. Ordering Information
Ordering Code
Flash (B)
256K + 8K
192K + 8K
128K + 8K
64K + 4K
256K + 8K
192K + 8K
128K + 8K
64K + 4K
E2 (B)
4K
SRAM (B)
16K
16K
8K
Speed (MHz) Power Supply Package(1)(2)(3)
Temp
ATxmega256D3-AU
ATxmega192D3-AU
ATxmega128D3-AU
ATxmega64D3-AU
ATxmega256D3-MH
ATxmega192D3-MH
ATxmega128D3-MH
ATxmega64D3-MH
32
32
32
32
32
32
32
32
1.6 - 3.6V
1.6 - 3.6V
1.6 - 3.6V
1.6 - 3.6V
1.6 - 3.6V
1.6 - 3.6V
1.6 - 3.6V
1.6 - 3.6V
4K
64A
2K
2K
4K
-40° - 85°C
4K
16K
16K
8K
4K
64M2
2K
2K
4K
Notes:
1.
2.
3.
This device can also be supplied in wafer form. Please contact your local Atmel sales office for detailed ordering information.
Pb-free packaging, complies to the European Directive for Restriction of Hazardous Substances (RoHS directive). Also Halide free and fully Green.
For packaging information, see ”Packaging information” on page 85.
Package Type
64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness, 0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm, 7.65 mm Exposed Pad, Quad Flat No-Lead Package (QFN)
64A
64M2
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XMEGA D3
2. Pinout/ Block Diagram
Figure 2-1.
Block diagram and pinout
INDEX CORNER
PA3
PA4
PA5
PA6
PA7
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
GND
VCC
PC0
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PF2
PF1
PF0
VCC
GND
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
VCC
GND
PD7
Port R
2
DATA BU S
3
ADC A
AC A0
AC A1
4
OSC/CLK
Control
BOD
TEMP
VREF
POR
OCD
5
RTC
6
Power
Control
FLASH
7
8
RAM
Reset
Control
CPU
9
E2PROM
10
11
12
13
14
15
16
Interrupt Controller
Event System ctrl
DATA BUS
Watchdog
EVENT ROUTING NETWORK
Port C
Port D
Port E
Port F
Note:
1. For full details on pinout and alternate pin functions refer to ”Pinout and Pin Functions” on page 46.
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XMEGA D3
3. Overview
The XMEGA D3 is a family of low power, high performance and peripheral rich CMOS 8/16-bit
microcontrollers based on the AVR® enhanced RISC architecture. By execug powerful instruc-
tions in a single clock cycle, the XMEGA D3 achieves throughputs approaching 1 Million
Instructions Per Second (MIPS) per MHz allowing the system designer to optimize power con-
sumption versus processing speed.
The AVR CPU combines a rich instruction set with 32 general purpose working registers. All the
32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction, executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs many times faster than conven-
tional single-accumulator or CISC based microcontrollers.
The XMEGA D3 devices provide the following features: In-System Programmable Flash with
Read-While-Write capabilities, Internal EEPROM and SRAM, four-channel Event System, Pro-
grammable Multi-level Interrupt Controller, 50 general purpose I/O lines, 16-bit Real Time
Counter (RTC), five flexible 16-bit Timer/Counters with compare modes and PWM, three
USARTs, two Two-Wire Interface (TWIs), two Serial Peripheral Interfaces (SPIs), one 16-chan-
nel 12-bit ADC with optional differential input with programmable gain, two analog comparators
with window mode, programmable Watchdog Timer with separate Internal Oscillator, accurate
internal oscillators with PLL and prescaler and programmable Brown-Out Detection.
The Program and Debug Interface (PDI), a fast 2-pin interface for programming and debugging,
is available.
The XMEGA D3 devices have five software selectable power saving modes. The Idle mode
stops the CPU while allowing the SRAM, Event System, Interrupt Controller and all peripherals
to continue functioning. The Power-down mode saves the SRAM and register contents but stops
the oscillators, disabling all other functions until the next TWI or pin-change interrupt, or Reset.
In Power-save mode, the asynchronous Real Time Counter continues to run, allowing the appli-
cation to maintain a timer base while the rest of the device is sleeping. In Standby mode, the
Crystal/Resonator Oscillator is kept running while the rest of the device is sleeping. This allows
very fast start-up from external crystal combined with low power consumption. In Extended
Standby mode, both the main Oscillator and the Asynchronous Timer continue to run. To further
reduce power consumption, the peripheral clock for each individual peripheral can optionally be
stopped in Active mode and Idle sleep mode.
The device is manufactured using Atmel's high-density nonvolatile memory technology. The pro-
gram Flash memory can be reprogrammed in-system through the PDI. A Bootloader running in
the device can use any interface to download the application program to the Flash memory. The
Bootloader software in the Boot Flash section will continue to run while the Application Flash
section is updated, providing true Read-While-Write operation. By combining an 8/16-bit RISC
CPU with In-System Self-Programmable Flash, the Atmel XMEGA D3 is a powerful microcon-
troller family that provides a highly flexible and cost effective solution for many embedded
applications.
The XMEGA D3 devices are supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debugger/simulators, programmers,
and evaluation kits.
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XMEGA D3
3.1
Block Diagram
Figure 3-1. XMEGA D3 Block Diagram
PR[0..1]
XTAL1
XTAL2
Oscillator
Circuits/
Clock
Watchdog
Oscillator
Generation
Real Time
Counter
Watchdog
Timer
DATA BUS
VCC
GND
Power
Supervision
POR/BOD &
RESET
Event System
Controller
Oscillator
Control
PA[0..7]
PORT A (8)
SRAM
Sleep
Controller
ACA
ADCA
RESET/
PDI_CLK
BUS
Controller
Prog/Debug
Controller
PDI
AREFA
VCC/10
Int. Refs.
Tempref
AREFB
PDI_DATA
OCD
CPU
Interrupt
Controller
CRC
PB[0..7]
PORT B (8)
NVM Controller
USARTF0
TCF0
PF[0..7]
Flash
EEPROM
IRCOM
DATA BUS
EVENT ROUTING NETWORK
To Clock
Generator
PORT C (8)
PORT D (8)
PORT E (8)
TOSC1
TOSC2
PC[0..7]
PD[0..7]
PE[0..7]
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XMEGA D3
4. Resources
A comprehensive set of development tools, application notes and datasheets are available for
download on http://www.atmel.com/avr.
4.1
Recommended reading
• XMEGA D Manual
• XMEGA Application Notes
This device data sheet only contains part specific information and a short description of each
peripheral and module. The XMEGA D Manual describes the modules and peripherals in depth.
The XMEGA application notes contain example code and show applied use of the modules and
peripherals.
The XMEGA Manual and Application Notes are available from http://www.atmel.com/avr.
5. Disclaimer
For devices that are not available yet, typical values contained in this datasheet are based on
simulations and characterization of other AVR XMEGA microcontrollers manufactured on the
same process technology. Min. and Max values will be available after the device is
characterized.
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XMEGA D3
6. AVR CPU
6.1
Features
• 8/16-bit high performance AVR RISC Architecture
– 138 instructions
– Hardware multiplier
• 32x8-bit registers directly connected to the ALU
• Stack in RAM
• Stack Pointer accessible in I/O memory space
• Direct addressing of up to 16M bytes of program and data memory
• True 16/24-bit access to 16/24-bit I/O registers
• Support for 8-, 16- and 32-bit Arithmetic
• Configuration Change Protection of system critical features
6.2
Overview
The XMEGA D3 uses the 8/16-bit AVR CPU. The main function of the AVR CPU is to ensure
correct program execution. The CPU must therefore be able to access memories, perform calcu-
lations and control peripherals. Interrupt handling is described in a separate section. Figure 6-1
on page 7 shows the CPU block diagram.
Figure 6-1. CPU block diagram
DATA BUS
Flash
Program
Program
Counter
Memory
32 x 8 General
Purpose
Registers
Instruction
Register
OCD
STATUS/
CONTROL
Instruction
Decode
Multiplier/
DES
ALU
DATA BUS
Peripheral
Module 1
Peripheral
Module 2
SRAM
EEPROM
PMIC
The AVR uses a Harvard architecture - with separate memories and buses for program and
data. Instructions in the program memory are executed with a single level pipeline. While one
instruction is being executed, the next instruction is pre-fetched from the program memory.
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8134D–AVR–12/09
XMEGA D3
This concept enables instructions to be executed in every clock cycle. The program memory is
In-System Re-programmable Flash memory.
6.3
6.4
Register File
The fast-access Register File contains 32 x 8-bit general purpose working registers with a single
clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation. In a typ-
ical ALU operation, two operands are output from the Register File, the operation is executed,
and the result is stored back in the Register File - in one clock cycle.
Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing - enabling efficient address calculations. One of these address pointers can
also be used as an address pointer for look up tables in Flash program memory.
ALU - Arithmetic Logic Unit
The high performance Arithmetic Logic Unit (ALU) supports arithmetic and logic operations
between registers or between a constant and a register. Single register operations can also be
executed. Within a single clock cycle, arithmetic operations between general purpose registers
or between a register and an immediate are executed. After an arithmetic or logic operation, the
Status Register is updated to reflect information about the result of the operation.
The ALU operations are divided into three main categories – arithmetic, logical, and bit-func-
tions. Both 8- and 16-bit arithmetic is supported, and the instruction set allows for easy
implementation of 32-bit arithmetic. The ALU also provides a powerful multiplier supporting both
signed and unsigned multiplication and fractional format.
6.5
Program Flow
When the device is powered on, the CPU starts to execute instructions from the lowest address
in the Flash Program Memory ‘0’. The Program Counter (PC) addresses the next instruction to
be fetched. After a reset, the PC is set to location ‘0’.
Program flow is provided by conditional and unconditional jump and call instructions, capable of
addressing the whole address space directly. Most AVR instructions use a 16-bit word format,
while a limited number uses a 32-bit format.
During interrupts and subroutine calls, the return address PC is stored on the Stack. The Stack
is effectively allocated in the general data SRAM, and consequently the Stack size is only limited
by the total SRAM size and the usage of the SRAM. After reset the Stack Pointer (SP) points to
the highest address in the internal SRAM. The SP is read/write accessible in the I/O memory
space, enabling easy implementation of multiple stacks or stack areas. The data SRAM can
easily be accessed through the five different addressing modes supported in the AVR CPU.
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XMEGA D3
7. Memories
7.1
Features
• Flash Program Memory
– One linear address space
– In-System Programmable
– Self-Programming and Bootloader support
– Application Section for application code
– Application Table Section for application code or data storage
– Boot Section for application code or bootloader code
– Separate lock bits and protection for all sections
• Data Memory
– One linear address space
– Single cycle access from CPU
– SRAM
– EEPROM
Byte and page accessible
Optional memory mapping for direct load and store
– I/O Memory
Configuration and Status registers for all peripherals and modules
16 bit-accessible General Purpose Register for global variables or flags
• Production Signature Row Memory for factory programmed data
Device ID for each microcontroller device type
Serial number for each device
Oscillator calibration bytes
ADC and temperature sensor calibration data
• User Signature Row
One flash page in size
Can be read and written from software
Content is kept after chip erase
7.2
Overview
The AVR architecture has two main memory spaces, the Program Memory and the Data Mem-
ory. In addition, the XMEGA D3 features an EEPROM Memory for non-volatile data storage. All
three memory spaces are linear and require no paging. The available memory size configura-
tions are shown in ”Ordering Information” on page 2. In addition each device has a Flash
memory signature row for calibration data, device identification, serial number etc.
Non-volatile memory spaces can be locked for further write or read/write operations. This pre-
vents unrestricted access to the application software.
7.3
In-System Programmable Flash Program Memory
The XMEGA D3 devices contains On-chip In-System Programmable Flash memory for program
storage, see Figure 7-1 on page 10. Since all AVR instructions are 16- or 32-bits wide, each
Flash address location is 16 bits.
The Program Flash memory space is divided into Application and Boot sections. Both sections
have dedicated Lock Bits for setting restrictions on write or read/write operations. The Store Pro-
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8134D–AVR–12/09
XMEGA D3
gram Memory (SPM) instruction must reside in the Boot Section when used to write to the Flash
memory.
A third section inside the Application section is referred to as the Application Table section which
has separate Lock bits for storage of write or read/write protection. The Application Table sec-
tion can be used for storing non-volatile data or application software.
Figure 7-1. Flash Program Memory (Hexadecimal address)
Word Address
0
Application Section
(256K/192K/128K/64K)
...
1EFFF
1F000
1FFFF
20000
20FFF
/
/
/
/
/
16FFF
17000
17FFF
18000
18FFF
/
/
/
/
/
EFFF
F000
/
/
/
/
/
77FF
7800
7FFF
8000
87FF
Application Table Section
(8K/8K/8K/4K)
FFFF
10000
10FFF
Boot Section
(8K/8K/8K/4K)
The Application Table Section and Boot Section can also be used for general application
software.
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XMEGA D3
7.4
Data Memory
The Data Memory consist of the I/O Memory, EEPROM and SRAM memories, all within one lin-
ear address space, see Figure 7-2 on page 11. To simplify development, the memory map for all
devices in the family is identical and with empty, reserved memory space for smaller devices.
Figure 7-2. Data Memory Map (Hexadecimal address)
Byte Address
ATxmega192D3
Byte Address
ATxmega128D3
Byte Address
ATxmega64D3
0
0
0
I/O Registers
(4KB)
I/O Registers
(4KB)
I/O Registers
(4KB)
FFF
FFF
1000
17FF
FFF
1000
17FF
1000
EEPROM
(2K)
EEPROM
(2K)
EEPROM
(4K)
RESERVED
RESERVED
1FFF
2000
5FFF
2000
3FFF
2000
2FFF
Internal SRAM
(16K)
Internal SRAM
(8K)
Internal SRAM
(4K)
Byte Address
ATxmega256D3
0
FFF
I/O Registers
(4KB)
1000
EEPROM
(4K)
1FFF
2000
5FFF
Internal SRAM
(16K)
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XMEGA D3
7.4.1
I/O Memory
All peripherals and modules are addressable through I/O memory locations in the data memory
space. All I/O memory locations can be accessed by the Load (LD/LDS/LDD) and Store
(ST/STS/STD) instructions, transferring data between the 32 general purpose registers in the
CPU and the I/O Memory.
The IN and OUT instructions can address I/O memory locations in the range 0x00 - 0x3F
directly.
I/O registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and
CBI instructions. The value of single bits can be checked by using the SBIS and SBIC instruc-
tions on these registers.
The I/O memory address for all peripherals and modules in XMEGA D3 is shown in the ”Periph-
eral Module Address Map” on page 51.
7.4.2
7.4.3
SRAM Data Memory
The XMEGA D3 devices have internal SRAM memory for data storage.
EEPROM Data Memory
The XMEGA D3 devices have internal EEPROM memory for non-volatile data storage. It is
addressable either in a separate data space or it can be memory mapped into the normal data
memory space. The EEPROM memory supports both byte and page access.
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XMEGA D3
7.5
Production Signature Row
The Production Signature Row is a separate memory section for factory programmed data. It
contains calibration data for functions such as oscillators and analog modules.
The production signature row also contains a device ID that identify each microcontroller device
type, and a serial number that is unique for each manufactured device. The device ID for the
available XMEGA D3 devices is shown in Table 7-1 on page 13. The serial number consist of
the production LOT number, wafer number, and wafer coordinates for the device.
The production signature row can not be written or erased, but it can be read from both applica-
tion software and external programming.
Table 7-1.
Device ID bytes for XMEGA D3 devices.
Device
Device ID bytes
Byte 2
Byte 1
96
Byte 0
1E
ATxmega64D3
ATxmega128D3
ATxmega192D3
ATxmega256D3
4A
48
49
44
97
1E
97
1E
98
1E
7.6
User Signature Row
The User Signature Row is a separate memory section that is fully accessible (read and write)
from application software and external programming. The user signature row is one flash page
in size, and is meant for static user parameter storage, such as calibration data, custom serial
numbers or identification numbers, random number seeds etc. This section is not erased by
Chip Erase commands that erase the Flash, and requires a dedicated erase command. This
ensures parameter storage during multiple program/erase session and on-chip debug sessions.
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XMEGA D3
7.7
Flash and EEPROM Page Size
The Flash Program Memory and EEPROM data memory is organized in pages. The pages are
word accessible for the Flash and byte accessible for the EEPROM.
Table 7-2 on page 14 shows the Flash Program Memory organization. Flash write and erase
operations are performed on one page at the time, while reading the Flash is done one byte at
the time. For Flash access the Z-pointer (Z[m:n]) is used for addressing. The most significant
bits in the address (FPAGE) gives the page number and the least significant address bits
(FWORD) gives the word in the page.
Table 7-2.
Number of words and Pages in the Flash.
Devices
Flash
Page Size
(words)
128
FWORD
FPAGE
Application
Boot
No of Pages
Size (Bytes)
64K + 4K
Size
No of Pages
Size
4K
ATxmega64D3
ATxmega128D3
ATxmega192D3
ATxmega256D3
Z[7:1]
Z[8:1]
Z[8:1]
Z[8:1]
Z[16:8]
Z[17:9]
Z[18:9]
Z[18:9]
64K
256
256
384
512
16
16
16
16
128K + 8K
192K + 8K
256K + 8K
256
128K
192K
256K
8K
256
8K
256
8K
Table 7-3 on page 14 shows EEPROM memory organization for the XMEGA D3 devices.
EEEPROM write and erase operations can be performed one page or one byte at the time, while
reading the EEPROM is done one byte at the time. For EEPROM access the NVM Address
Register (ADDR[m:n] is used for addressing. The most significant bits in the address (E2PAGE)
gives the page number and the least significant address bits (E2BYTE) gives the byte in the
page.
Table 7-3.
Number of bytes and Pages in the EEPROM.
Devices
EEPROM
Page Size
E2BYTE
E2PAGE
No of Pages
Size (Bytes)
(Bytes)
32
ATxmega64D3
ATxmega128D3
ATxmega192D3
ATxmega256D3
2K
2K
2K
4K
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
ADDR[4:0]
ADDR[10:5]
ADDR[10:5]
ADDR[10:5]
ADDR[11:5]
64
64
32
32
64
32
128
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XMEGA D3
8. Event System
8.1
Features
• Inter-peripheral communication and signalling with minimum latency
• CPU independent operation
• 4 Event Channels allows for up to 4 signals to be routed at the same time
• Events can be generated by
– Timer/Counters (TCxn)
– Real Time Counter (RTC)
– Analog to Digital Converters (ADC)
– Analog Comparators (AC)
– Ports (PORTx)
– System Clock (ClkSYS
)
– Software (CPU)
• Events can be used by
– Timer/Counters (TCxn)
– Analog to Digital Converters (ADC)
– Ports (PORTx)
– IR Communication Module (IRCOM)
• The same event can be used by multiple peripherals for synchronized timing
• Advanced Features
– Manual Event Generation from software (CPU)
– Quadrature Decoding
– Digital Filtering
• Functions in Active and Idle mode
8.2
Overview
The Event System is a set of features for inter-peripheral communication. It enables the possibil-
ity for a change of state in one peripheral to automatically trigger actions in one or more
peripherals. What changes in a peripheral that will trigger actions in other peripherals are config-
urable by software. It is a simple, but powerful system as it allows for autonomous control of
peripherals without any use of interrupts or CPU resources.
The indication of a change in a peripheral is referred to as an event, and is usually the same as
the interrupt conditions for that peripheral. Events are passed between peripherals using a dedi-
cated routing network called the Event Routing Network. Figure 8-1 on page 16 shows a basic
block diagram of the Event System with the Event Routing Network and the peripherals to which
it is connected. This highly flexible system can be used for simple routing of signals, pin func-
tions or for sequencing of events.
The maximum latency is two CPU clock cycles from when an event is generated in one periph-
eral, until the actions are triggered in one or more other peripherals.
The Event System is functional in both Active and Idle modes.
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XMEGA D3
Figure 8-1. Event system block diagram.
ClkSYS
CPU
PORTx
RTC
ACx
Event Routing
Network
ADCx
IRCOM
T/Cxn
The Event Routing Network can directly connect together ADCs, Analog Comparators (AC),
I/O ports (PORTx), the Real-time Counter (RTC), Timer/Counters (T/C) and the IR Communica-
tion Module (IRCOM). Events can also be generated from software (CPU).
All events from all peripherals are always routed into the Event Routing Network. This consist of
four multiplexers where each can be configured in software to select which event to be routed
into that event channel. All four event channels are connected to the peripherals that can use
events, and each of these peripherals can be configured to use events from one or more event
channels to automatically trigger a software selectable action.
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XMEGA D3
9. System Clock and Clock options
9.1
Features
• Fast start-up time
• Safe run-time clock switching
• Internal Oscillators:
– 32 MHz run-time calibrated RC oscillator
– 2 MHz run-time calibrated RC oscillator
– 32.768 kHz calibrated RC oscillator
– 32 kHz Ultra Low Power (ULP) oscillator
• External clock options
– 0.4 - 16 MHz Crystal Oscillator
– 32.768 kHz Crystal Oscillator
– External clock
• PLL with internal and external clock options with 2 to 31x multiplication
• Clock Prescalers with 2 to 2048x division
• Fast peripheral clock running at 2 and 4 times the CPU clock speed
• Automatic Run-Time Calibration of internal oscillators
• Crystal Oscillator failure detection
9.2
Overview
XMEGA D3 has an advanced clock system, supporting a large number of clock sources. It incor-
porates both integrated oscillators, external crystal oscillators and resonators. A high frequency
Phase Locked Loop (PLL) and clock prescalers can be controlled from software to generate a
wide range of clock frequencies from the clock source input.
It is possible to switch between clock sources from software during run-time. After reset the
device will always start up running from the 2 Mhz internal oscillator.
A calibration feature is available, and can be used for automatic run-time calibration of the inter-
nal 2 MHz and 32 MHz oscillators. This reduce frequency drift over voltage and temperature.
A Crystal Oscillator Failure Monitor can be enabled to issue a Non-Maskable Interrupt and
switch to internal oscillator if the external oscillator fails. Figure 9-1 on page 18 shows the princi-
pal clock system in XMEGA D3.
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XMEGA D3
Figure 9-1. Clock system overview
clkULP
clkRTC
WDT/BOD
RTC
32 kHz ULP
Internal Oscillator
32.768 kHz
Calibrated Internal
Oscillator
PERIPHERALS
ADC
2 MHz
Run-Time Calibrated
Internal Oscillator
PORTS
...
CLOCK CONTROL
UNIT
32 MHz
Run-time Calibrated
Internal Oscillator
clkPER
with PLL and
Prescaler
INTERRUPT
EVSYS
32.768 KHz
Crystal Oscillator
RAM
0.4 - 16 MHz
Crystal Oscillator
CPU
NVM MEMORY
FLASH
clkCPU
External
Clock Input
EEPROM
Each clock source is briefly described in the following sub-sections.
9.3
Clock Options
9.3.1
32 kHz Ultra Low Power Internal Oscillator
The 32 kHz Ultra Low Power (ULP) Internal Oscillator is a very low power consumption clock
source. It is used for the Watchdog Timer, Brown-Out Detection and as an asynchronous clock
source for the Real Time Counter. This oscillator cannot be used as the system clock source,
and it cannot be directly controlled from software.
9.3.2
32.768 kHz Calibrated Internal Oscillator
The 32.768 kHz Calibrated Internal Oscillator is a high accuracy clock source that can be used
as the system clock source or as an asynchronous clock source for the Real Time Counter. It is
calibrated during production to provide a default frequency which is close to its nominal
frequency.
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9.3.3
9.3.4
9.3.5
32.768 kHz Crystal Oscillator
The 32.768 kHz Crystal Oscillator is a low power driver for an external watch crystal. It can be
used as system clock source or as asynchronous clock source for the Real Time Counter.
0.4 - 16 MHz Crystal Oscillator
The 0.4 - 16 MHz Crystal Oscillator is a driver intended for driving both external resonators and
crystals ranging from 400 kHz to 16 MHz.
2 MHz Run-time Calibrated Internal Oscillator
The 2 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during production to provide a default frequency which is close to its nominal frequency. The
oscillator can use the 32.768 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator
as a source for calibrating the frequency run-time to compensate for temperature and voltage
drift hereby optimizing the accuracy of the oscillator.
9.3.6
32 MHz Run-time Calibrated Internal Oscillator
The 32 MHz Run-time Calibrated Internal Oscillator is a high frequency oscillator. It is calibrated
during production to provide a default frequency which is close to its nominal frequency. The
oscillator can use the 32.768 kHz Calibrated Internal Oscillator or the 32 kHz Crystal Oscillator
as a source for calibrating the frequency run-time to compensate for temperature and voltage
drift hereby optimizing the accuracy of the oscillator.
9.3.7
9.3.8
External Clock input
The external clock input gives the possibility to connect a clock from an external source.
PLL with Multiplication factor 2 - 31x
The PLL provides the possibility of multiplying a frequency by any number from 2 to 31. In com-
bination with the prescalers, this gives a wide range of output frequencies from all clock sources.
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10. Power Management and Sleep Modes
10.1 Features
• 5 sleep modes
– Idle
– Power-down
– Power-save
– Standby
– Extended standby
• Power Reduction registers to disable clocks to unused peripherals
10.2 Overview
The XMEGA D3 provides various sleep modes tailored to reduce power consumption to a mini-
mum. All sleep modes are available and can be entered from Active mode. In Active mode the
CPU is executing application code. The application code decides when and what sleep mode to
enter. Interrupts from enabled peripherals and all enabled reset sources can restore the micro-
controller from sleep to Active mode.
In addition, Power Reduction registers provide a method to stop the clock to individual peripher-
als from software. When this is done, the current state of the peripheral is frozen and there is no
power consumption from that peripheral. This reduces the power consumption in Active mode
and Idle sleep mode.
10.3 Sleep Modes
10.3.1
Idle Mode
In Idle mode the CPU and Non-Volatile Memory are stopped, but all peripherals including the
Interrupt Controller and Event System are kept running. Interrupt requests from all enabled inter-
rupts will wake the device.
10.3.2
Power-down Mode
In Power-down mode all system clock sources, and the asynchronous Real Time Counter (RTC)
clock source, are stopped. This allows operation of asynchronous modules only. The only inter-
rupts that can wake up the MCU are the Two Wire Interface address match interrupts, and
asynchronous port interrupts, e.g pin change.
10.3.3
10.3.4
Power-save Mode
Power-save mode is identical to Power-down, with one exception: If the RTC is enabled, it will
keep running during sleep and the device can also wake up from RTC interrupts.
Standby Mode
Standby mode is identical to Power-down with the exception that all enabled system clock
sources are kept running, while the CPU, Peripheral and RTC clocks are stopped. This reduces
the wake-up time when external crystals or resonators are used.
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10.3.5
Extended Standby Mode
Extended Standby mode is identical to Power-save mode with the exception that all enabled
system clock sources are kept running while the CPU and Peripheral clocks are stopped. This
reduces the wake-up time when external crystals or resonators are used.
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11. System Control and Reset
11.1 Features
• Multiple reset sources for safe operation and device reset
– Power-On Reset
– External Reset
– Watchdog Reset
The Watchdog Timer runs from separate, dedicated oscillator
– Brown-Out Reset
Accurate, programmable Brown-Out levels
– PDI reset
– Software reset
• Asynchronous reset
– No running clock in the device is required for reset
• Reset status register
11.2 Resetting the AVR
During reset, all I/O registers are set to their initial values. The SRAM content is not reset. Appli-
cation execution starts from the Reset Vector. The instruction placed at the Reset Vector should
be an Absolute Jump (JMP) instruction to the reset handling routine. By default the Reset Vector
address is the lowest Flash program memory address, ‘0’, but it is possible to move the Reset
Vector to the first address in the Boot Section.
The I/O ports of the AVR are immediately tri-stated when a reset source goes active.
The reset functionality is asynchronous, so no running clock is required to reset the device.
After the device is reset, the reset source can be determined by the application by reading the
Reset Status Register.
11.3 Reset Sources
11.3.1
11.3.2
11.3.3
Power-On Reset
The MCU is reset when the supply voltage VCC is below the Power-on Reset threshold voltage.
External Reset
The MCU is reset when a low level is present on the RESET pin.
Watchdog Reset
The MCU is reset when the Watchdog Timer period expires and the Watchdog Reset is enabled.
The Watchdog Timer runs from a dedicated oscillator independent of the System Clock. For
more details see ”WDT - Watchdog Timer” on page 23.
11.3.4
11.3.5
Brown-Out Reset
The MCU is reset when the supply voltage VCC is below the Brown-Out Reset threshold voltage
and the Brown-out Detector is enabled. The Brown-out threshold voltage is programmable.
PDI reset
The MCU can be reset through the Program and Debug Interface (PDI).
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11.3.6
Software reset
The MCU can be reset by the CPU writing to a special I/O register through a timed sequence.
12. WDT - Watchdog Timer
12.1 Features
• 11 selectable timeout periods, from 8 ms to 8s.
• Two operation modes
– Standard mode
– Window mode
• Runs from the 1 kHz output of the 32 kHz Ultra Low Power oscillator
• Configuration lock to prevent unwanted changes
12.2 Overview
The XMEGA D3 has a Watchdog Timer (WDT). The WDT will run continuously when turned on
and if the Watchdog Timer is not reset within a software configurable time-out period, the micro-
controller will be reset. The Watchdog Reset (WDR) instruction must be run by software to reset
the WDT, and prevent microcontroller reset.
The WDT has a Window mode. In this mode the WDR instruction must be run within a specified
period called a window. Application software can set the minimum and maximum limits for this
window. If the WDR instruction is not executed inside the window limits, the microcontroller will
be reset.
A protection mechanism using a timed write sequence is implemented in order to prevent
unwanted enabling, disabling or change of WDT settings.
For maximum safety, the WDT also has an Always-on mode. This mode is enabled by program-
ming a fuse. In Always-on mode, application software can not disable the WDT.
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13. PMIC - Programmable Multi-level Interrupt Controller
13.1 Features
• Separate interrupt vector for each interrupt
• Short, predictable interrupt response time
• Programmable Multi-level Interrupt Controller
– 3 programmable interrupt levels
– Selectable priority scheme within low level interrupts (round-robin or fixed)
– Non-Maskable Interrupts (NMI)
• Interrupt vectors can be moved to the start of the Boot Section
13.2 Overview
XMEGA D3 has a Programmable Multi-level Interrupt Controller (PMIC). All peripherals can
define three different priority levels for interrupts; high, medium or low. Medium level interrupts
may interrupt low level interrupt service routines. High level interrupts may interrupt both low-
and medium level interrupt service routines. Low level interrupts have an optional round robin
scheme to make sure all interrupts are serviced within a certain amount of time.
The built in oscillator failure detection mechanism can issue a Non-Maskable Interrupt (NMI).
13.3 Interrupt vectors
When an interrupt is serviced, the program counter will jump to the interrupt vector address. The
interrupt vector is the sum of the peripheral’s base interrupt address and the offset address for
specific interrupts in each peripheral. The base addresses for the XMEGA D3 devices are
shown in Table 13-1. Offset addresses for each interrupt available in the peripheral are
described for each peripheral in the XMEGA A manual. For peripherals or modules that have
only one interrupt, the interrupt vector is shown in Table 13-1. The program address is the word
address.
Table 13-1. Reset and Interrupt Vectors
Program Address
(Base Address)
Source
Interrupt Description
0x000
0x002
0x004
0x008
0x014
0x018
0x01C
0x028
0x030
0x032
0x040
0x044
0x056
RESET
OSCF_INT_vect
PORTC_INT_base
PORTR_INT_base
RTC_INT_base
TWIC_INT_base
TCC0_INT_base
TCC1_INT_base
SPIC_INT_vect
USARTC0_INT_base
NVM_INT_base
PORTB_INT_base
PORTE_INT_base
Crystal Oscillator Failure Interrupt vector (NMI)
Port C Interrupt base
Port R Interrupt base
Real Time Counter Interrupt base
Two-Wire Interface on Port C Interrupt base
Timer/Counter 0 on port C Interrupt base
Timer/Counter 1 on port C Interrupt base
SPI on port C Interrupt vector
USART 0 on port C Interrupt base
Non-Volatile Memory Interrupt base
Port B Interrupt base
Port E INT base
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Table 13-1. Reset and Interrupt Vectors (Continued)
Program Address
(Base Address)
Source
Interrupt Description
0x05A
TWIE_INT_base
TCE0_INT_base
USARTE0_INT_base
PORTD_INT_base
PORTA_INT_base
ACA_INT_base
Two-Wire Interface on Port E Interrupt base
Timer/Counter 0 on port E Interrupt base
USART 0 on port E Interrupt base
Port D Interrupt base
0x05E
0x074
0x080
0x084
Port A Interrupt base
0x088
Analog Comparator on Port A Interrupt base
0x08E
ADCA_INT_base
TCD0_INT_base
SPID_INT_vector
USARTD0_INT_base
PORTF_INT_base
TCF0_INT_base
Analog to Digital Converter on Port A Interrupt base
Timer/Counter 0 on port D Interrupt base
SPI D Interrupt vector
0x09A
0x0AE
0x0B0
USART 0 on port D Interrupt base
Port F Interrupt base
0x0D0
0x0D8
Timer/Counter 0 on port F Interrupt base
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14. I/O Ports
14.1 Features
• Selectable input and output configuration for each pin individually
• Flexible pin configuration through dedicated Pin Configuration Register
• Synchronous and/or asynchronous input sensing with port interrupts and events
– Sense both edges
– Sense rising edges
– Sense falling edges
– Sense low level
• Asynchronous wake-up from all input sensing configurations
• Two port interrupts with flexible pin masking
• Highly configurable output driver and pull settings:
–
–
–
–
–
–
Totem-pole
Pull-up/-down
Wired-AND
Wired-OR
Bus-keeper
Inverted I/O
• Optional Slew rate control
• Configuration of multiple pins in a single operation
• Read-Modify-Write (RMW) support
• Toggle/clear/set registers for Output and Direction registers
• Clock output on port pin
• Event Channel 7 output on port pin
• Mapping of port registers (virtual ports) into bit accessible I/O memory space
14.2 Overview
The XMEGA D3 devices have flexible General Purpose I/O Ports. A port consists of up to 8 pins,
ranging from pin 0 to pin 7. The ports implement several functions, including synchronous/asyn-
chronous input sensing, pin change interrupts and configurable output settings. All functions are
individual per pin, but several pins may be configured in a single operation.
14.3 I/O configuration
All port pins (Pn) have programmable output configuration. In addition, all port pins have an
inverted I/O function. For an input, this means inverting the signal between the port pin and the
pin register. For an output, this means inverting the output signal between the port register and
the port pin. The inverted I/O function can be used also when the pin is used for alternate
functions.
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XMEGA D3
14.3.1
Push-pull
Figure 14-1. I/O configuration - Totem-pole
DIRn
OUTn
INn
Pn
14.3.2
Pull-down
Figure 14-2. I/O configuration - Totem-pole with pull-down (on input)
DIRn
OUTn
INn
Pn
14.3.3
Pull-up
Figure 14-3. I/O configuration - Totem-pole with pull-up (on input)
DIRn
OUTn
INn
Pn
14.3.4
Bus-keeper
The bus-keeper’s weak output produces the same logical level as the last output level. It acts as
a pull-up if the last level was ‘1’, and pull-down if the last level was ‘0’.
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XMEGA D3
Figure 14-4. I/O configuration - Totem-pole with bus-keeper
DIRn
OUTn
INn
Pn
14.3.5
Others
Figure 14-5. Output configuration - Wired-OR with optional pull-down
OUTn
Pn
INn
Figure 14-6. I/O configuration - Wired-AND with optional pull-up
INn
Pn
OUTn
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14.4 Input sensing
• Sense both edges
• Sense rising edges
• Sense falling edges
• Sense low level
Input sensing is synchronous or asynchronous depending on the enabled clock for the ports,
and the configuration is shown in Figure 14-7 on page 29.
Figure 14-7. Input sensing system overview
Asynchronous sensing
EDGE
DETECT
Interrupt
Control
IREQ
Event
Synchronous sensing
Pn
Synchronizer
INn
EDGE
DETECT
Q
Q
D
D
INVERTEDI/O
R
R
When a pin is configured with inverted I/O, the pin value is inverted before the input sensing.
14.5 Port Interrupt
Each port has two interrupts with separate priority and interrupt vector. All pins on the port can
be individually selected as source for each of the interrupts. The interrupts are then triggered
according to the input sense configuration for each pin configured as source for the interrupt.
14.6 Alternate Port Functions
In addition to the input/output functions on all port pins, most pins have alternate functions. This
means that other modules or peripherals connected to the port can use the port pins for their
functions, such as communication or pulse-width modulation. ”Pinout and Pin Functions” on
page 46 shows which modules on peripherals that enable alternate functions on a pin, and
which alternate functions that is available on a pin.
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15. T/C - 16-bits Timer/Counter with PWM
15.1 Features
• Five 16-bit Timer/Counters
– Four Timer/Counters of type 0
– One Timer/Counters of type 1
• Four Compare or Capture (CC) Channels in Timer/Counter 0
• Two Compare or Capture (CC) Channels in Timer/Counter 1
• Double Buffered Timer Period Setting
• Double Buffered Compare or Capture Channels
• Waveform Generation:
– Single Slope Pulse Width Modulation
– Dual Slope Pulse Width Modulation
– Frequency Generation
• Input Capture:
– Input Capture with Noise Cancelling
– Frequency capture
– Pulse width capture
– 32-bit input capture
• Event Counter with Direction Control
• Timer Overflow and Timer Error Interrupts and Events
• One Compare Match or Capture Interrupt and Event per CC Channel
• Hi-Resolution Extension (Hi-Res)
• Advanced Waveform Extension (AWEX)
15.2 Overview
XMEGA D3 has five Timer/Counters, four Timer/Counter 0 and one Timer/Counter 1. The differ-
ence between them is that Timer/Counter 0 has four Compare/Capture channels, while
Timer/Counter 1 has two Compare/Capture channels.
The Timer/Counters (T/C) are 16-bit and can count any clock, event or external input in the
microcontroller. A programmable prescaler is available to get a useful T/C resolution. Updates of
Timer and Compare registers are double buffered to ensure glitch free operation. Single slope
PWM, dual slope PWM and frequency generation waveforms can be generated using the Com-
pare Channels.
Through the Event System, any input pin or event in the microcontroller can be used to trigger
input capture, hence no dedicated pins are required for this. The input capture has a noise can-
celler to avoid incorrect capture of the T/C, and can be used to do frequency and pulse width
measurements.
A wide range of interrupt or event sources are available, including T/C Overflow, Compare
match and Capture for each Compare/Capture channel in the T/C.
PORTC has one Timer/Counter 0 and one Timer/Counter1. PORTD, PORTE and PORTF each
have one Timer/Counter 0. Notation of these are TCC0 (Time/Counter C0), TCC1, TCD0, TCE0,
and TCF0, respectively.
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Figure 15-1. Overview of a Timer/Counter and closely related peripherals
Timer/Counter
Base Counter
Prescaler
clkPER
Timer Period
Counter
Control Logic
Event
System
clkPER4
Compare/Capture Channel D
Compare/Capture Channel C
Compare/Capture Channel B
Compare/Capture Channel A
AWeX
Pattern
Generation
Fault
DTI
Dead-Time
Insertion
Capture
Comparator
Control
Protection
Waveform
Buffer
Generation
The Hi-Resolution Extension can be enabled to increase the waveform generation resolution by
2 bits (4x). This is available for all Timer/Counters. See ”Hi-Res - High Resolution Extension” on
page 33 for more details.
The Advanced Waveform Extension can be enabled to provide extra and more advanced fea-
tures for the Timer/Counter. This are only available for Timer/Counter 0. See ”AWEX - Advanced
Waveform Extension” on page 32 for more details.
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16. AWEX - Advanced Waveform Extension
16.1 Features
• Output with complementary output from each Capture channel
• Four Dead Time Insertion (DTI) Units, one for each Capture channel
• 8-bit DTI Resolution
• Separate High and Low Side Dead-Time Setting
• Double Buffered Dead-Time
• Event Controlled Fault Protection
• Single Channel Multiple Output Operation (for BLDC motor control)
• Double Buffered Pattern Generation
16.2 Overview
The Advanced Waveform Extension (AWEX) provides extra features to the Timer/Counter in
Waveform Generation (WG) modes. The AWEX enables easy and safe implementation of for
example, advanced motor control (AC, BLDC, SR, and Stepper) and power control applications.
Any WG output from a Timer/Counter 0 is split into a complimentary pair of outputs when any
AWEX feature is enabled. These output pairs go through a Dead-Time Insertion (DTI) unit that
enables generation of the non-inverted Low Side (LS) and inverted High Side (HS) of the WG
output with dead time insertion between LS and HS switching. The DTI output will override the
normal port value according to the port override setting. Optionally the final output can be
inverted by using the invert I/O setting for the port pin.
The Pattern Generation unit can be used to generate a synchronized bit pattern on the port it is
connected to. In addition, the waveform generator output from Compare Channel A can be dis-
tributed to, and override all port pins. When the Pattern Generator unit is enabled, the DTI unit is
bypassed.
The Fault Protection unit is connected to the Event System. This enables any event to trigger a
fault condition that will disable the AWEX output. Several event channels can be used to trigger
fault on several different conditions.
The AWEX is available for TCC0. The notation of this is AWEXC.
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17. Hi-Res - High Resolution Extension
17.1 Features
• Increases Waveform Generator resolution by 2-bits (4x)
• Supports Frequency, single- and dual-slope PWM operation
• Supports the AWEX when this is enabled and used for the same Timer/Counter
17.2 Overview
The Hi-Resolution (Hi-Res) Extension is able to increase the resolution of the waveform genera-
tion output by a factor of 4. When enabled for a Timer/Counter, the Fast Peripheral clock running
at four times the CPU clock speed will be as input to the Timer/Counter.
The High Resolution Extension can also be used when an AWEX is enabled and used with a
Timer/Counter.
XMEGA D3 devices have one Hi-Res Extension that can be enabled for each Timer/Counters
on PORTC. The notation of this is HIRESC.
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18. RTC - Real-Time Counter
18.1 Features
• 16-bit Timer
• Flexible Tick resolution ranging from 1 Hz to 32.768 kHz
• One Compare register
• One Period register
• Clear timer on Overflow or Compare Match
• Overflow or Compare Match event and interrupt generation
18.2 Overview
The XMEGA D3 includes a 16-bit Real-time Counter (RTC). The RTC can be clocked from an
accurate 32.768 kHz Crystal Oscillator, the 32.768 kHz Calibrated Internal Oscillator, or from the
32 kHz Ultra Low Power Internal Oscillator. The RTC includes both a Period and a Compare
register. For details, see Figure 18-1.
A wide range of Resolution and Time-out periods can be configured using the RTC. With a max-
imum resolution of 30.5 µs, time-out periods range up to 2000 seconds. With a resolution of 1
second, the maximum time-out period is over 18 hours (65536 seconds).
Figure 18-1. Real-time Counter overview
Period
Overflow
32.768 kHz
=
=
10-bit
prescaler
Counter
1.024 kHz
Compare Match
Compare
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19. TWI - Two Wire Interface
19.1 Features
• Two Identical TWI peripherals
• Simple yet Powerful and Flexible Communication Interface
• Both Master and Slave Operation Supported
• Device can Operate as Transmitter or Receiver
• 7-bit Address Space Allows up to 128 Different Slave Addresses
• Multi-master Arbitration Support
• Up to 400 kHz Data Transfer Speed
• Slew-rate Limited Output Drivers
• Noise Suppression Circuitry Rejects Spikes on Bus Lines
• Fully Programmable Slave Address with General Call Support
• Address Recognition Causes Wake-up when in Sleep Mode
• I2C and System Management Bus (SMBus) compatible
19.2 Overview
The Two-Wire Interface (TWI) is a bi-directional wired-AND bus with only two lines, the clock
(SCL) line and the data (SDA) line. The protocol makes it possible to interconnect up to 128 indi-
vidually addressable devices. Since it is a multi-master bus, one or more devices capable of
taking control of the bus can be connected.
The only external hardware needed to implement the bus is a single pull-up resistor for each of
the TWI bus lines. Mechanisms for resolving bus contention are inherent in the TWI protocol.
PORTC and PORTE each has one TWI. Notation of these peripherals are TWIC and TWIE,
respectively.
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20. SPI - Serial Peripheral Interface
20.1 Features
• Two Identical SPI peripherals
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
20.2 Overview
The Serial Peripheral Interface (SPI) allows high-speed full-duplex, synchronous data transfer
between different devices. Devices can communicate using a master-slave scheme, and data is
transferred both to and from the devices simultaneously.
PORTC and PORTD each has one SPI. Notation of these peripherals are SPIC and SPID,
respectively.
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21. USART
21.1 Features
• Three Identical USART peripherals
• Full Duplex Operation (Independent Serial Receive and Transmit Registers)
• Asynchronous or Synchronous Operation
• Master or Slave Clocked Synchronous Operation
• High-resolution Arithmetic Baud Rate Generator
• Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
• Odd or Even Parity Generation and Parity Check Supported by Hardware
• Data OverRun Detection
• Framing Error Detection
• Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
• Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
• Multi-processor Communication Mode
• Double Speed Asynchronous Communication Mode
• Master SPI mode for SPI communication
• IrDA support through the IRCOM module
21.2 Overview
The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication module. The USART supports full duplex communication,
and both asynchronous and clocked synchronous operation. The USART can also be set in
Master SPI mode to be used for SPI communication.
Communication is frame based, and the frame format can be customized to support a wide
range of standards. The USART is buffered in both direction, enabling continued data transmis-
sion without any delay between frames. There are separate interrupt vectors for receive and
transmit complete, enabling fully interrupt driven communication. Frame error and buffer over-
flow are detected in hardware and indicated with separate status flags. Even or odd parity
generation and parity check can also be enabled.
One USART can use the IRCOM module to support IrDA 1.4 physical compliant pulse modula-
tion and demodulation for baud rates up to 115.2 kbps.
PORTC, PORTD, and PORTE each has one USART. Notation of these peripherals are
USARTC0, USARTD0 and USARTE0, respectively.
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22. IRCOM - IR Communication Module
22.1 Features
• Pulse modulation/demodulation for infrared communication
• Compatible to IrDA 1.4 physical for baud rates up to 115.2 kbps
• Selectable pulse modulation scheme
– 3/16 of baud rate period
– Fixed pulse period, 8-bit programmable
– Pulse modulation disabled
• Built in filtering
• Can be connected to and used by one USART at the time
22.2 Overview
XMEGA contains an Infrared Communication Module (IRCOM) for IrDA communication with
baud rates up to 115.2 kbps. This supports three modulation schemes: 3/16 of baud rate period,
fixed programmable pulse time based on the Peripheral Clock speed, or pulse modulation dis-
abled. There is one IRCOM available which can be connected to any USART to enable infrared
pulse coding/decoding for that USART.
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23. ADC - 12-bit Analog to Digital Converter
23.1 Features
• One ADC with 12-bit resolution
• 200 ksps sample rate
• Signed and Unsigned conversions
• 16 single ended inputs
• 8x4 differential inputs
• 3 internal inputs:
–
–
–
Integrated Temperature Sensor
VCC voltage divided by 10
Bandgap voltage
• Software selectable gain of 2, 4, 8, 16, 32 or 64
• Software selectable resolution of 8- or 12-bit.
• Internal or External Reference selection
• Event triggered conversion for accurate timing
• Interrupt/Event on compare result
23.2 Overview
XMEGA D3 devices have one Analog to Digital Converters (ADC), see Figure 23-1 on page 40.
The ADC converts analog voltages to digital values. The ADC has 12-bit resolution and is capa-
ble of converting up to 200 thousand samples per second. The input selection is flexible, and
both single-ended and differential measurements can be performed. The ADC can provide both
signed and unsigned results, and an optional gain stage is available to increase the dynamic
range of the ADC.
It is a Successive Approximation Result (SAR) ADC. A SAR ADC measures one bit of the con-
version result at a time.
ADC measurements can be started by application software or an incoming event from another
peripheral in the device.
Both internal and external analog reference voltages can be used. An accurate internal 1.0V
reference is available.
An integrated temperature sensor is available and the output from this can be measured with the
ADC. The output from the VCC/10 and the Bandgap voltage can also be measured by the ADC.
39
8134D–AVR–12/09
XMEGA D3
Figure 23-1. ADC overview
Channel A MUX selection
Channel B MUX selection
Channel C MUX selection
Channel D MUX selection
Configuration
Reference selection
Channel A
Register
Channel B
Register
ADC
Channel C
Register
Channel D
Register
Event
Trigger
1-64 X
Each ADC has four MUX selection registers with a corresponding result register. This means
that four channels can be sampled within 1.5 µs without any intervention by the application other
than starting the conversion. The results will be available in the result registers.
The ADC may be configured for 8- or 12-bit result, reducing the minimum conversion time (prop-
agation delay) from 3.5 µs for 12-bit to 2.5 µs for 8-bit result.
ADC conversion results are provided left- or right adjusted with optional ‘1’ or ‘0’ padding. This
eases calculation when the result is represented as a signed integer (signed 16-bit number).
PORTA has one ADC. Notation of this peripheral is ADCA.
40
8134D–AVR–12/09
XMEGA D3
24. AC - Analog Comparator
24.1 Features
• Two Analog Comparators
• Selectable hysteresis
– No, Small or Large
• Analog Comparator output available on pin
• Flexible Input Selection
– All pins on the port
– Bandgap reference voltage.
– Voltage scaler that can perform a 64-level scaling of the internal VCC voltage.
• Interrupt and event generation on
– Rising edge
– Falling edge
– Toggle
• Window function interrupt and event generation on
– Signal above window
– Signal inside window
– Signal below window
24.2 Overview
XMEGA D3 features two Analog Comparators (AC). An Analog Comparator compares two volt-
ages, and the output indicates which input is largest. The Analog Comparator may be configured
to give interrupt requests and/or events upon several different combinations of input change.
Hysteresis can be adjusted in order to find the optimal operation for each application.
A wide range of input selection is available, both external pins and several internal signals can
be used.
The Analog Comparators are always grouped in pairs (AC0 and AC1) on each analog port. They
have identical behavior but separate control registers.
Optionally, the state of the comparator is directly available on a pin.
PORTA and has one AC pair. Notations of this peripheral is ACA.
41
8134D–AVR–12/09
XMEGA D3
Figure 24-1. Analog comparator overview
Pin inputs
Internal inputs
+
-
Pin 0 output
Interrupts
AC0
Pin inputs
Internal inputs
VCC scaled
Interrupt
sensitivity
control
Events
Pin inputs
Internal inputs
+
-
AC1
Pin inputs
Internal inputs
VCC scaled
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8134D–AVR–12/09
XMEGA D3
24.3 Input Selection
The Analog comparators have a very flexible input selection and the two comparators grouped
in a pair may be used to realize a window function. One pair of analog comparators is shown in
Figure 24-1 on page 42.
• Input selection from pin
– Pin 0, 1, 2, 3, 4, 5, 6 selectable to positive input of analog comparator
– Pin 0, 1, 3, 5, 7 selectable to negative input of analog comparator
• Internal signals available on positive analog comparator inputs
• Internal signals available on negative analog comparator inputs
– 64-level scaler of the VCC, available on negative analog comparator input
– Bandgap voltage reference
24.4 Window Function
The window function is realized by connecting the external inputs of the two analog comparators
in a pair as shown in Figure 24-2.
Figure 24-2. Analog comparator window function
+
AC0
Upper limit of window
-
Interrupts
Events
Interrupt
sensitivity
control
Input signal
+
AC1
Lower limit of window
-
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XMEGA D3
25. OCD - On-chip Debug
25.1 Features
• Complete Program Flow Control
– Go, Stop, Reset, Step into, Step over, Step out, Run-to-Cursor
• Debugging on C and high-level language source code level
• Debugging on Assembler and disassembler level
• 1 dedicated program address or source level breakpoint for AVR Studio / debugger
• 4 Hardware Breakpoints
• Unlimited Number of User Program Breakpoints
• Unlimited Number of User Data Breakpoints, with break on:
– Data location read, write or both read and write
– Data location content equal or not equal to a value
– Data location content is greater or less than a value
– Data location content is within or outside a range
– Bits of a data location are equal or not equal to a value
• Non-Intrusive Operation
– No hardware or software resources in the device are used
• High Speed Operation
– No limitation on debug/programming clock frequency versus system clock frequency
25.2 Overview
The XMEGA D3 has a powerful On-Chip Debug (OCD) system that - in combination with Atmel’s
development tools - provides all the necessary functions to debug an application. It has support
for program and data breakpoints, and can debug an application from C and high level language
source code level, as well as assembler and disassembler level. It has full Non-Intrusive Opera-
tion and no hardware or software resources in the device are used. The ODC system is
accessed through an external debugging tool which connects to the PDI interface. Refer to ”PDI
- Program and Debug Interface” on page 45.
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8134D–AVR–12/09
XMEGA D3
26. PDI - Program and Debug Interface
26.1 Features
• PDI - Program and Debug Interface (Atmel proprietary 2-pin interface)
• Access to the OCD system
• Programming of Flash, EEPROM, Fuses and Lock Bits
26.2 Overview
The programming and debug facilities are accessed through the PDI interface. The PDI physical
interface uses one dedicated pin together with the Reset pin, and no general purpose pins are
used.
The PDI is an Atmel proprietary protocol for communication between the microcontroller and
Atmel’s or third party development tools.
45
8134D–AVR–12/09
XMEGA D3
27. Pinout and Pin Functions
The pinout of XMEGA D3 is shown in ”” on page 2. In addition to general I/O functionality, each
pin may have several function. This will depend on which peripheral is enabled and connected to
the actual pin. Only one of the alternate pin functions can be used at time.
27.1 Alternate Pin Function Description
The tables below show the notation for all pin functions available and describe its function.
27.1.1
Operation/Power Supply
VCC
Digital supply voltage
Analog supply voltage
Ground
AVCC
GND
27.1.2
27.1.3
Port Interrupt functions
SYNC
Port pin with full synchronous and limited asynchronous interrupt function
Port pin with full synchronous and full asynchronous interrupt function
ASYNC
Analog functions
ACn
Analog Comparator input pin n
Analog Comparator 0 Output
Analog to Digital Converter input pin n
Analog Reference input pin
AC0OUT
ADCn
AREF
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8134D–AVR–12/09
XMEGA D3
27.1.4
27.1.5
Timer/Counter and AWEX functions
OCnx
OCxn
Output Compare Channel x for Timer/Counter n
Inverted Output Compare Channel x for Timer/Counter n
Communication functions
SCL
Serial Clock for TWI
SDA
Serial Data for TWI
SCLIN
SCLOUT
SDAIN
SDAOUT
XCKn
RXDn
TXDn
SS
Serial Clock In for TWI when external driver interface is enabled
Serial Clock Out for TWI when external driver interface is enabled
Serial Data In for TWI when external driver interface is enabled
Serial Data Out for TWI when external driver interface is enabled
Transfer Clock for USART n
Receiver Data for USART n
Transmitter Data for USART n
Slave Select for SPI
MOSI
MISO
SCK
Master Out Slave In for SPI
Master In Slave Out for SPI
Serial Clock for SPI
27.1.6
27.1.7
Oscillators, Clock and Event
TOSCn
XTALn
Timer Oscillator pin n
Input/Output for inverting Oscillator pin n
Peripheral Clock Output
CLKOUT
EVOUT
Event Channel 0 Output
Debug/System functions
RESET
Reset pin
PDI_CLK
PDI_DATA
Program and Debug Interface Clock pin
Program and Debug Interface Data pin
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8134D–AVR–12/09
XMEGA D3
27.2 Alternate Pin Functions
The tables below show the main and alternate pin functions for all pins on each port. They also
show which peripheral that makes use of or enables the alternate pin function.
Table 27-1. Port A - Alternate functions
ADAA
GAINPOS
ADCA
GAINNEG
PORT A
GND
AVCC
PA0
PIN #
60
61
62
63
64
1
INTERRUPT
ADCA POS
ADCA NEG
ACA POS
ACA NEG
ACA OUT
REFA
SYNC
SYNC
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
ADC0
ADC1
ADC2
ADC3
ADC0
ADC1
ADC2
ADC3
ADC4
ADC5
ADC6
ADC7
AC0
AC1
AC2
AC3
AC4
AC5
AC6
AC0
AC1
AREFA
PA1
PA2
SYNC/ASYNC
SYNC
PA3
AC3
AC5
AC7
PA4
2
SYNC
ADC4
ADC5
ADC6
ADC7
PA5
3
SYNC
PA6
4
SYNC
PA7
5
SYNC
AC0 OUT
Table 27-2. Port B - Alternate functions
PORT B
PIN #
INTERRUPT
ADCA POS
REFB
PB0
6
SYNC
ADC8
AREFB
PB1
6
SYNC
ADC9
PB2
8
SYNC/ASYNC
SYNC
ADC10
ADC11
ADC12
ADC13
ADC14
ADC15
PB3
9
PB4
10
11
12
13
14
15
SYNC
PB5
SYNC
PB6
SYNC
PB7
SYNC
GND
VCC
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8134D–AVR–12/09
XMEGA D3
Table 27-3. Port C - Alternate functions
PORT C
PIN #
INTERRUPT
TCC0
OC0A
OC0B
OC0C
OC0D
AWEXC
OC0A
OC0A
OC0B
OC0B
OC0C
OC0C
OC0D
OC0D
TCC1
USARTC0
SPIC
TWIC
SDA
SCL
CLOCKOUT
EVENTOUT
PC0
16
SYNC
PC1
17
SYNC
XCK0
RXD0
TXD0
PC2
18
SYNC/ASYNC
SYNC
PC3
19
PC4
20
SYNC
OC1A
OC1B
SS
PC5
21
SYNC
MOSI
MISO
SCK
PC6
22
SYNC
PC7
23
SYNC
CLKOUT
EVOUT
GND
VCC
24
25
Table 27-4. Port D - Alternate functions
PORT D
PIN #
INTERRUPT
TCD0
OC0A
OC0B
OC0C
OC0D
USARTD0
SPID
CLOCKOUT
EVENTOUT
PD0
26
SYNC
PD1
27
SYNC
XCK0
RXD0
TXD0
PD2
28
SYNC/ASYNC
SYNC
PD3
29
PD4
30
SYNC
SS
PD5
31
SYNC
MOSI
MISO
SCK
PD6
32
SYNC
PD7
33
SYNC
CLKOUT
EVOUT
GND
VCC
34
35
Table 27-5. Port E - Alternate functions
PORT E
PIN #
INTERRUPT
TCE0
OC0A
OC0B
OC0C
OC0D
USARTE0
CLOCKOUT
EVENTOUT
TOSC
TWIE
SDA
SCL
PE0
36
SYNC
PE1
37
SYNC
XCK0
RXD0
TXD0
PE2
38
SYNC/ASYNC
SYNC
PE3
39
PE4
40
SYNC
PE5
41
SYNC
PE6
42
SYNC
TOSC1
TOSC1
PE7
43
SYNC
CLKOUT
EVOUT
GND
VCC
44
45
49
8134D–AVR–12/09
XMEGA D3
Table 27-6. Port F - Alternate functions
PORT F
PIN #
INTERRUPT
TCF0
OC0A
OC0B
OC0C
OC0D
PF0
46
SYNC
PF1
47
SYNC
PF2
48
SYNC/ASYNC
SYNC
PF3
49
PF4
50
SYNC
PF5
51
SYNC
PF6
54
SYNC
PF7
55
SYNC
GND
VCC
52
53
Table 27-7. Port R - Alternate functions
PORT R
PDI
PIN #
56
INTERRUPT
PDI
XTAL
PDI_DATA
PDI_CLOCK
RESET
PRO
57
58
SYNC
SYNC
XTAL2
XTAL1
PR1
59
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8134D–AVR–12/09
XMEGA D3
28. Peripheral Module Address Map
The address maps show the base address for each peripheral and module in XMEGA D3. For
complete register description and summary for each peripheral module, refer to the XMEGA A
Manual.
Table 28-1. Peripheral Module Address Map
Base Address
Name
Description
0x0000
0x0010
0x0014
0x0018
0x001C
0x0030
0x0040
0x0048
0x0050
0x0060
0x0068
0x0070
0x0078
0x0080
0x0090
0x00A0
0x00B0
0x0180
0x01C0
0x0200
0x0380
0x0400
0x0480
0x04A0
0x0600
0x0620
0x0640
0x0660
0x0680
0x06A0
0x07E0
0x0800
0x0840
0x0880
0x0890
0x08A0
0x08C0
0x08F8
0x0900
0x09A0
0x09C0
0x0A00
0x0A80
0x0AA0
0x0AC0
0x0B00
GPIO
General Purpose IO Registers
Virtual Port 0
Virtual Port 1
Virtual Port 2
Virtual Port 2
CPU
Clock Control
Sleep Controller
Oscillator Control
DFLL for the 32 MHz Internal RC Oscillator
DFLL for the 2 MHz RC Oscillator
Power Reduction
Reset Controller
Watch-Dog Timer
MCU Control
Programmable MUltilevel Interrupt Controller
Port Configuration
VPORT0
VPORT1
VPORT2
VPORT3
CPU
CLK
SLEEP
OSC
DFLLRC32M
DFLLRC2M
PR
RST
WDT
MCU
PMIC
PORTCFG
EVSYS
NVM
ADCA
ACA
RTC
TWIC
Event System
Non Volatile Memory (NVM) Controller
Analog to Digital Converter on port A
Analog Comparator pair on port A
Real Time Counter
Two Wire Interface on port C
Two Wire Interface on port E
Port A
Port B
Port C
Port D
Port E
TWIE
PORTA
PORTB
PORTC
PORTD
PORTE
PORTF
PORTR
TCC0
Port F
Port R
Timer/Counter 0 on port C
Timer/Counter 1 on port C
Advanced Waveform Extension on port C
High Resolution Extension on port C
USART 0 on port C
Serial Peripheral Interface on port C
Infrared Communication Module
Timer/Counter 0 on port D
USART 0 on port D
Serial Peripheral Interface on port D
Timer/Counter 0 on port E
Advanced Waveform Extensionon port E
USART 0 on port E
Serial Peripheral Interface on port E
Timer/Counter 0 on port F
TCC1
AWEXC
HIRESC
USARTC0
SPIC
IRCOM
TCD0
USARTD0
SPID
TCE0
AWEXE
USARTE0
SPIE
TCF0
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XMEGA D3
29. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
Arithmetic and Logic Instructions
ADD
Rd, Rr
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Add without Carry
Rd
Rd
Rd
Rd
Rd
Rd
Rd
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
Rd + Rr
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,C,N,V,S
Z,C,N,V,S,H
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
Z,N,V,S
None
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
2
2
ADC
Add with Carry
Rd + Rr + C
Rd + 1:Rd + K
Rd - Rr
ADIW
SUB
Add Immediate to Word
Subtract without Carry
Subtract Immediate
Subtract with Carry
Subtract Immediate with Carry
Subtract Immediate from Word
Logical AND
SUBI
SBC
Rd - K
Rd - Rr - C
Rd - K - C
Rd + 1:Rd - K
Rd • Rr
SBCI
SBIW
AND
Rd + 1:Rd
Rd
ANDI
OR
Logical AND with Immediate
Logical OR
Rd
Rd • K
Rd
Rd v Rr
ORI
Logical OR with Immediate
Exclusive OR
Rd
Rd v K
EOR
COM
NEG
SBR
Rd
Rd ⊕ Rr
One’s Complement
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Rd
$FF - Rd
Rd
Rd
$00 - Rd
Rd,K
Rd,K
Rd
Rd
Rd v K
CBR
Rd
Rd • ($FFh - K)
Rd + 1
INC
Rd
DEC
Rd
Decrement
Rd
Rd - 1
TST
Rd
Test for Zero or Minus
Clear Register
Rd
Rd • Rd
CLR
Rd
Rd
Rd ⊕ Rd
SER
Rd
Set Register
Rd
$FF
MUL
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Rd,Rr
Multiply Unsigned
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
R1:R0
Rd x Rr (UU)
Rd x Rr (SS)
Rd x Rr (SU)
Rd x Rr<<1 (UU)
Rd x Rr<<1 (SS)
Rd x Rr<<1 (SU)
Z,C
MULS
MULSU
FMUL
FMULS
FMULSU
Multiply Signed
Z,C
Multiply Signed with Unsigned
Fractional Multiply Unsigned
Fractional Multiply Signed
Fractional Multiply Signed with Unsigned
Z,C
Z,C
Z,C
Z,C
Branch Instructions
RJMP
IJMP
k
Relative Jump
PC
←
PC + k + 1
None
None
2
2
Indirect Jump to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
0
EIJMP
Extended Indirect Jump to (Z)
PC(15:0)
PC(21:16)
←
←
Z,
EIND
None
2
JMP
k
k
Jump
PC
PC
←
←
k
None
None
None
3
RCALL
ICALL
Relative Call Subroutine
Indirect Call to (Z)
PC + k + 1
2 / 3(1)
2 / 3(1)
PC(15:0)
PC(21:16)
←
←
Z,
0
EICALL
CALL
Extended Indirect Call to (Z)
call Subroutine
PC(15:0)
PC(21:16)
←
←
Z,
EIND
None
None
3(1)
k
PC
←
k
3 / 4(1)
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8134D–AVR–12/09
XMEGA D3
Mnemonics
RET
Operands
Description
Operation
Flags
None
I
#Clocks
4 / 5(1)
4 / 5(1)
1 / 2 / 3
1
Subroutine Return
PC
PC
←
←
←
STACK
RETI
Interrupt Return
STACK
CPSE
CP
Rd,Rr
Compare, Skip if Equal
Compare
if (Rd = Rr) PC
PC + 2 or 3
None
Z,C,N,V,S,H
Z,C,N,V,S,H
Z,C,N,V,S,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
Rd,Rr
Rd - Rr
CPC
Rd,Rr
Compare with Carry
Rd - Rr - C
1
CPI
Rd,K
Compare with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
Rd - K
1
SBRC
SBRS
SBIC
Rr, b
if (Rr(b) = 0) PC
if (Rr(b) = 1) PC
if (I/O(A,b) = 0) PC
If (I/O(A,b) =1) PC
if (SREG(s) = 1) then PC
if (SREG(s) = 0) then PC
if (Z = 1) then PC
if (Z = 0) then PC
if (C = 1) then PC
if (C = 0) then PC
if (C = 0) then PC
if (C = 1) then PC
if (N = 1) then PC
if (N = 0) then PC
if (N ⊕ V= 0) then PC
if (N ⊕ V= 1) then PC
if (H = 1) then PC
if (H = 0) then PC
if (T = 1) then PC
if (T = 0) then PC
if (V = 1) then PC
if (V = 0) then PC
if (I = 1) then PC
if (I = 0) then PC
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + 2 or 3
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
PC + k + 1
1 / 2 / 3
1 / 2 / 3
2 / 3 / 4
2 / 3 / 4
1 / 2
Rr, b
A, b
A, b
s, k
s, k
k
SBIS
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
1 / 2
1 / 2
k
Branch if Not Equal
1 / 2
k
Branch if Carry Set
1 / 2
k
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
1 / 2
k
1 / 2
k
1 / 2
k
Branch if Minus
1 / 2
k
Branch if Plus
1 / 2
k
Branch if Greater or Equal, Signed
Branch if Less Than, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
k
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
1 / 2
k
1 / 2
k
1 / 2
k
1 / 2
BRID
k
1 / 2
Data Transfer Instructions
MOV
MOVW
LDI
Rd, Rr
Rd, Rr
Rd, K
Rd, k
Copy Register
Rd
Rd+1:Rd
Rd
←
←
←
←
←
Rr
None
None
None
None
None
None
1
Copy Register Pair
Load Immediate
Rr+1:Rr
1
K
1
LDS
LD
Load Direct from data space
Load Indirect
Rd
(k)
(X)
2(1)(2)
1(1)(2)
1(1)(2)
Rd, X
Rd, X+
Rd
LD
Load Indirect and Post-Increment
Rd
X
←
←
(X)
X + 1
LD
Rd, -X
Load Indirect and Pre-Decrement
X ← X - 1,
Rd ← (X)
←
←
X - 1
(X)
None
2(1)(2)
LD
LD
Rd, Y
Load Indirect
Rd ← (Y)
←
(Y)
None
None
1(1)(2)
1(1)(2)
Rd, Y+
Load Indirect and Post-Increment
Rd
Y
←
←
(Y)
Y + 1
53
8134D–AVR–12/09
XMEGA D3
Mnemonics
Operands
Description
Operation
Flags
#Clocks
LD
Rd, -Y
Load Indirect and Pre-Decrement
Y
Rd
←
←
Y - 1
(Y)
None
2(1)(2)
LDD
LD
Rd, Y+q
Rd, Z
Load Indirect with Displacement
Load Indirect
Rd
Rd
←
←
(Y + q)
(Z)
None
None
None
2(1)(2)
1(1)(2)
1(1)(2)
LD
Rd, Z+
Load Indirect and Post-Increment
Rd
Z
←
←
(Z),
Z+1
LD
Rd, -Z
Load Indirect and Pre-Decrement
Z
Rd
←
←
Z - 1,
(Z)
None
2(1)(2)
LDD
STS
ST
Rd, Z+q
k, Rr
Load Indirect with Displacement
Store Direct to Data Space
Store Indirect
Rd
(k)
(X)
←
←
←
(Z + q)
Rd
None
None
None
None
2(1)(2)
2(1)
X, Rr
Rr
1(1)
ST
X+, Rr
Store Indirect and Post-Increment
(X)
X
←
←
Rr,
X + 1
1(1)
ST
-X, Rr
Store Indirect and Pre-Decrement
X
(X)
←
←
X - 1,
Rr
None
2(1)
ST
ST
Y, Rr
Store Indirect
(Y)
←
Rr
None
None
1(1)
1(1)
Y+, Rr
Store Indirect and Post-Increment
(Y)
Y
←
←
Rr,
Y + 1
ST
-Y, Rr
Store Indirect and Pre-Decrement
Y
(Y)
←
←
Y - 1,
Rr
None
2(1)
STD
ST
Y+q, Rr
Z, Rr
Store Indirect with Displacement
Store Indirect
(Y + q)
(Z)
←
←
Rr
Rr
None
None
None
2(1)
1(1)
1(1)
ST
Z+, Rr
Store Indirect and Post-Increment
(Z)
Z
←
←
Rr
Z + 1
ST
-Z, Rr
Store Indirect and Pre-Decrement
Store Indirect with Displacement
Load Program Memory
Z
(Z + q)
R0
←
←
←
←
Z - 1
Rr
None
None
None
None
None
2(1)
2(1)
3
STD
LPM
LPM
LPM
Z+q,Rr
(Z)
Rd, Z
Load Program Memory
Rd
(Z)
3
Rd, Z+
Load Program Memory and Post-Increment
Rd
Z
←
←
(Z),
Z + 1
3
ELPM
ELPM
ELPM
Extended Load Program Memory
Extended Load Program Memory
R0
Rd
←
←
(RAMPZ:Z)
(RAMPZ:Z)
None
None
None
3
3
3
Rd, Z
Rd, Z+
Extended Load Program Memory and Post-
Increment
Rd
Z
←
←
(RAMPZ:Z),
Z + 1
SPM
SPM
Store Program Memory
(RAMPZ:Z)
←
R1:R0
None
None
-
-
Z+
Store Program Memory and Post-Increment
by 2
(RAMPZ:Z)
Z
←
←
R1:R0,
Z + 2
IN
Rd, A
A, Rr
Rr
In From I/O Location
Out To I/O Location
Rd
I/O(A)
STACK
Rd
←
←
←
←
I/O(A)
Rr
None
None
None
None
1
OUT
PUSH
POP
1
Push Register on Stack
Pop Register from Stack
Rr
1(1)
2(1)
Rd
STACK
Bit and Bit-test Instructions
LSL
LSR
Rd
Rd
Logical Shift Left
Logical Shift Right
Rd(n+1)
Rd(0)
C
←
←
←
Rd(n),
0,
Rd(7)
Z,C,N,V,H
Z,C,N,V
1
1
Rd(n)
Rd(7)
C
←
←
←
Rd(n+1),
0,
Rd(0)
54
8134D–AVR–12/09
XMEGA D3
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ROL
Rd
Rotate Left Through Carry
Rd(0)
Rd(n+1)
C
←
←
←
C,
Rd(n),
Rd(7)
Z,C,N,V,H
1
ROR
Rd
Rotate Right Through Carry
Rd(7)
Rd(n)
C
←
←
←
C,
Z,C,N,V
1
Rd(n+1),
Rd(0)
ASR
SWAP
BSET
BCLR
SBI
Rd
Arithmetic Shift Right
Swap Nibbles
Rd(n)
←
↔
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
←
Rd(n+1), n=0..6
Z,C,N,V
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Rd
Rd(3..0)
Rd(7..4)
None
s
Flag Set
SREG(s)
1
SREG(s)
s
Flag Clear
SREG(s)
0
SREG(s)
A, b
A, b
Rr, b
Rd, b
Set Bit in I/O Register
Clear Bit in I/O Register
Bit Store from Register to T
Bit load from T to Register
Set Carry
I/O(A, b)
1
None
CBI
I/O(A, b)
0
None
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
T
Rr(b)
T
1
T
Rd(b)
C
C
N
N
Z
None
C
C
N
N
Z
Clear Carry
0
Set Negative Flag
1
Clear Negative Flag
Set Zero Flag
0
1
Clear Zero Flag
Z
0
Z
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Two’s Complement Overflow
Clear Two’s Complement Overflow
Set T in SREG
I
1
I
CLI
I
0
I
SES
CLS
SEV
CLV
SET
CLT
S
1
S
S
V
V
T
S
0
V
1
V
0
T
1
Clear T in SREG
T
0
T
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
H
H
1
H
H
0
MCU Control Instructions
BREAK
NOP
Break
(See specific descr. for BREAK)
None
None
None
None
1
1
1
1
No Operation
Sleep
SLEEP
WDR
(see specific descr. for Sleep)
Watchdog Reset
(see specific descr. for WDR)
Notes: 1. Cycle times for Data memory accesses assume internal memory accesses, and are not valid
for accesses via the external RAM interface.
2. One extra cycle must be added when accessing Internal SRAM.
55
8134D–AVR–12/09
XMEGA D3
30. Electrical Characteristics
30.1 Absolute Maximum Ratings*
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability.
Operating Temperature.................................. -55°C to +125°C
Storage Temperature..................................... -65°C to +150°C
Voltage on any Pin with respect to Ground. -0.5V to VCC+0.5V
Maximum Operating Voltage ............................................ 3.6V
DC Current per I/O Pin ............................................... 20.0 mA
DC Current VCC and GND Pins................................ 200.0 mA
30.2 DC Characteristics
Table 30-1. Current Consumption
Symbol Parameter
Condition
32 kHz, Ext. Clk
Min
Typ
25
Max
Units
µA
V
CC = 1.8V
VCC = 3.0V
71
VCC = 1.8V
VCC = 3.0V
VCC = 1.8V
317
697
613
1340
15.7
3.6
1 MHz, Ext. Clk
Active
800
1800
18
2 MHz, Ext. Clk
32 MHz, Ext. Clk
32 kHz, Ext. Clk
VCC = 3.0V
V
CC = 3.0V
CC = 1.8V
mA
µA
Power Supply Current(1)
V
VCC = 3.0V
CC = 1.8V
VCC = 3.0V
6.9
V
112
215
224
430
6.9
1 MHz, Ext. Clk
Idle
V
CC = 1.8V
CC = 3.0V
350
650
8
ICC
2 MHz, Ext. Clk
32 MHz, Ext. Clk
V
VCC = 3.0V
VCC = 3.0V
VCC = 3.0V
mA
All Functions Disabled
0.1
All Functions Disabled, T = 85°C
1.75
1
5
Power-down mode
Power-save mode
V
CC = 1.8V
VCC = 3.0V
CC = 3.0V
VCC = 1.8V
CC = 3.0V
ULP, WDT, Sampled BOD
1
ULP, WDT, Sampled BOD, T=85°C
V
2.7
10
µA
0.55
0.65
1.16
RTC 1 kHz from Low Power 32 kHz
TOSC
V
RTC from Low Power 32 kHz TOSC
without Reset pull-up resistor current
VCC = 3.0V
VCC = 3.0V
Reset Current
Consumption
1300
56
8134D–AVR–12/09
XMEGA D3
Table 30-1. Current Consumption
Symbol Parameter
Module current consumption(2)
RC32M
Condition
Min
Typ
Max
Units
460
594
101
134
27
RC32M w/DFLL
Internal 32.768 kHz oscillator as DFLL source
Internal 32.768 kHz oscillator as DFLL source
Multiplication factor = 10x
RC2M
RC2M w/DFLL
RC32K
PLL
202
1
Watchdog normal mode
BOD Continuous mode
128
1
ICC
µA
BOD Sampled mode
Internal 1.00 V ref
80
Temperature reference
74
RTC with int. 32 kHz RC as
source
No prescaling
No prescaling
27
RTC with ULP as source
1
AC
103
5.4
20
USART
Rx and Tx enabled, 9600 BAUD
Prescaler DIV1
Timer/Counter
Notes: 1. All Power Reduction Registers set. T = 25°C if not specified.
2. All parameters measured as the difference in current consumption between module enabled and disabled.
All data at VCC = 3.0V, ClkSYS = 1 MHz External clock with no prescaling, T = 25°C.
57
8134D–AVR–12/09
XMEGA D3
30.3 Operating Voltage and Frequency
Table 30-2. Operating voltage and voltage and frequency
Symbol
Parameter
Condition
CC = 1.6V
CC = 1.8V
Min
0
Typ
Max
12
Units
V
V
0
12
System clock
frequency
ClkSYS
MHz
VCC = 2.7V
CC = 3.6V
0
32
V
0
32
The maximum System clock frequency of the XMEGA D3 devices is depending on VCC. As
shown in Figure 30-1 on page 58 the Frequency vs. VCC curve is linear between
1.8V < VCC < 2.7V.
Figure 30-1. Maximum Frequency vs. Vcc
MHz
32
Safe Operating Area
12
V
1.6
1.8
2.7
3.6
58
8134D–AVR–12/09
XMEGA D3
30.4 Flash and EEPROM Memory Characteristics
Table 30-3. Endurance and Data Retention
Symbol Parameter
Condition
Min
10K
10K
100
25
Typ
Max
Units
25°C
85°C
25°C
55°C
25°C
85°C
25°C
55°C
Write/Erase cycles
Cycle
Flash
Data retention
Year
Cycle
Year
80K
30K
100
25
Write/Erase cycles
Data retention
EEPROM
Table 30-4. Programming time
Symbol Parameter
Chip Erase
Condition
Min
Typ(1)
40
6
Max
Units
Flash, EEPROM(2) and SRAM Erase
Page Erase
Flash
Page Write
6
Page WriteAutomatic Page Erase and Write
Page Erase
12
6
ms
EEPROM
Page Write
6
Page WriteAutomatic Page Erase and Write
12
Notes: 1. Programming is timed from the internal 2 MHz oscillator.
2. EEPROM is not erased if the EESAVE fuse is programmed.
59
8134D–AVR–12/09
XMEGA D3
30.5 ADC Characteristics
Table 30-5. ADC Characteristics
Symbol
RES
Parameter
Condition
Programmable: 8/12
80 ksps
Min
Typ
12
Max
Units
Bits
Resolution
8
12
INL
Integral Non-Linearity
Differential Non-Linearity
Gain Error
2
LSB
LSB
mV
DNL
80 ksps
< 1
< 10
< 2
Offset Error
mV
ADCclk
ADC Clock frequency
Conversion rate
Max is 1/4 of Peripheral Clock
1400
200
kHz
ksps
Conversion time
(RES+2)/2+GAIN
ADCclk
cycles
5
7
10
(propagation delay)
RES = 8 or 12, GAIN = 0, 1, 2 or 3
Sampling Time
1/2 ADCclk cycle
0.36
0
uS
V
Conversion range
VREF
VREF
Reference voltage
1.0
Vcc-0.6V
V
Input bandwidth
kHz
V
INT1V
INTVCC
SCALEDVCC
RAREF
Internal 1.00V reference
Internal VCC/1.6
1.00
VCC/1.6
VCC/10
> 10
V
Scaled internal VCC/10 input
Reference input resistance
Start-up time
V
MΩ
µs
ksps
Temp. sensor, VCC/10, Bandgap
Internal input sampling speed
100
Table 30-6. ADC Gain Stage Characteristics
Symbol
Parameter
Gain error
Offset error
Condition
Min
Typ
< 1
< 1
0.12
0.06
Max
Units
1 to 64 gain
%
VREF = Int. 1V
VREF = Ext. 2V
mV
Vrms
Noise level at input
Clock rate
64x gain
Same as ADC
200
kHz
60
8134D–AVR–12/09
XMEGA D3
30.6 Analog Comparator Characteristics
Table 30-7. Analog Comparator Characteristics
Symbol Parameter
Condition
Min
Typ
< 10
< 1000
0
Max
Units
mV
Voff
Ilk
Input Offset Voltage
VCC = 1.6 - 3.6V
VCC = 1.6 - 3.6V
VCC = 1.6 - 3.6V
VCC = 1.6 - 3.6V
VCC = 1.6 - 3.6V
VCC = 1.6 - 3.6V
Input Leakage Current
Hysteresis, No
pA
Vhys1
Vhys2
Vhys3
tdelay
mV
Hysteresis, Small
Hysteresis, Large
Propagation delay
20
mV
ns
40
175
30.7 Bandgap Characteristics
Table 30-8. Bandgap Voltage Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
As reference for ADC
As input to AC or ADC
1 Clk_PER + 2.5µs
Bandgap Startup Time
Bandgap voltage
µs
1.5
1.1
T= 85°C, After calibration
0.99
1
1
1.01
V
ADC ref
Variation over voltage and temperature
VCC = 1.6 - 3.6V, TA = -40°C to 85°C
5
%
30.8 Brownout Detection Characteristics
Table 30-9. Brownout Detection Characteristics(1)
Symbol Parameter
Condition
Min
Typ
1.62
1.9
Max
Units
BOD level 0 falling Vcc
BOD level 1 falling Vcc
BOD level 2 falling Vcc
2.17
2.43
2.68
2.96
3.22
3.49
1
BOD level 3 falling Vcc
V
BOD level 4 falling Vcc
BOD level 5 falling Vcc
BOD level 6 falling Vcc
BOD level 7 falling Vcc
Hysteresis
BOD level 0-5
%
Note:
1. BOD is calibrated to BOD level 0 at 85°C, and BOD level 0 is the default level.
61
8134D–AVR–12/09
XMEGA D3
30.9 PAD Characteristics
Table 30-10. PAD Characteristics
Symbol Parameter
Condition
CC = 2.4 - 3.6V
Min
0.7*VCC
0.8*VCC
-0.5
Typ
Max
VCC+0.5
VCC+0.5
0.3*VCC
0.2*VCC
0.76
Units
V
V
V
VIH
VIL
Input High Voltage
Input Low Voltage
CC = 1.6 - 2.4V
CC = 2.4 - 3.6V
VCC = 1.6 - 2.4V
OH = 8 mA, VCC = 3.3V
-0.5
I
0.4
0.3
V
VOL
Output Low Voltage GPIO
Output High Voltage GPIO
IOH = 5 mA, VCC = 3.0V
IOH = 3 mA, VCC = 1.8V
0.64
0.2
0.46
I
OH = -4 mA, VCC = 3.3V
2.6
2.1
1.4
3.0
VOH
IOH = -3 mA, VCC = 3.0V
IOH = -1 mA, VCC = 1.8V
2.7
1.6
IIL
IIH
Input Leakage Current I/O pin
Input Leakage Current I/O pin
I/O pin Pull/Buss keeper Resistor
Reset pin Pull-up Resistor
Input hysteresis
<0.001
<0.001
20
1
1
µA
RP
kΩ
RRST
20
0.5
V
30.10 POR Characteristics
Table 30-11. Power-on Reset Characteristics
Symbol Parameter
Condition
Min
Typ
1
Max
Units
VPOT-
POR threshold voltage falling Vcc
POR threshold voltage rising Vcc
V
VPOT+
1.45
30.11 Reset Characteristics
Table 30-12. Reset Characteristics
Symbol Parameter
Condition
Min
Typ
90
Max
Units
Minimum reset pulse width
ns
V
CC = 2.7 - 3.6V
0.45*VCC
0.42*VCC
Reset threshold voltage
V
VCC = 1.6 - 2.7V
62
8134D–AVR–12/09
XMEGA D3
30.12 Oscillator Characteristics
Table 30-13. Internal 32.768 kHz Oscillator Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
T = 85°C, VCC = 3V,
After production calibration
Accuracy
-0.5
0.5
%
Table 30-14. Internal 2 MHz Oscillator Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
T = 85°C, VCC = 3V,
After production calibration
Accuracy
-1.5
1.5
%
DFLL Calibration step size
T = 25°C, VCC = 3V
0.15
Table 30-15. Internal 32 MHz Oscillator Characteristics
Symbol Parameter
Condition
Min
Typ
Max
Units
T = 85°C, VCC = 3V,
After production calibration
Accuracy
-1.5
1.5
%
DFLL Calibration stepsize
T = 25°C, VCC = 3V
0.2
Table 30-16. Internal 32 kHz, ULP Oscillator Characteristics
Symbol Parameter Condition
Output frequency 32 kHz ULP OSC T = 85°C, VCC = 3.0V
Min
Typ
Max
Units
26
kHz
63
8134D–AVR–12/09
XMEGA D3
31. Typical Characteristics
31.1 Active Supply Current
Figure 31-1. Active Supply Current vs. Frequency
fSYS = 0 - 1.0 MHz External clock, T = 25°C
900
800
700
600
500
400
300
200
100
0
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
Figure 31-2. Active Supply Current vs. Frequency
fSYS = 1 - 32 MHz External clock, T = 25°C
20
18
16
14
12
10
8
3.3 V
3.0 V
2.7 V
2.2 V
6
4
1.8 V
2
0
0
4
8
12
16
20
24
28
32
Frequency [MHz]
64
8134D–AVR–12/09
XMEGA D3
Figure 31-3. Active Supply Current vs. Vcc
fSYS = 1.0 MHz External Clock
1000
900
800
700
600
500
400
300
200
100
0
85 °C
25 °C
-40 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 31-4. Active Supply Current vs. VCC
fSYS = 32.768 kHz internal RC
140
120
100
80
-40 °C
25 °C
85 °C
60
40
20
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
65
8134D–AVR–12/09
XMEGA D3
Figure 31-5. Active Supply Current vs. Vcc
fSYS = 2.0 MHz internal RC
2000
1800
1600
1400
1200
1000
800
-40 °C
25 °C
85 °C
600
400
200
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 31-6. Active Supply Current vs. Vcc
fSYS = 32 MHz internal RC prescaled to 8 MHz
8
7
6
5
4
3
2
1
0
-40 °C
25 °C
85 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
66
8134D–AVR–12/09
XMEGA D3
Figure 31-7. Active Supply Current vs. Vcc
fSYS = 32 MHz internal RC
25
20
15
10
5
-40 °C
25 °C
85 °C
0
2.7
2.8
2.9
3
3.1
3.2
CC [V]
3.3
3.4
3.5
3.6
V
31.2 Idle Supply Current
Figure 31-8. Idle Supply Current vs. Frequency
fSYS = 0 - 1.0 MHz, T = 25°C
250
200
150
100
50
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
0
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency [MHz]
67
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XMEGA D3
Figure 31-9. Idle Supply Current vs. Frequency
fSYS = 1 - 32 MHz, T = 25°C
8
7
6
5
4
3
2
1
0
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
0
4
8
12
16
Frequency [MHz]
20
24
28
32
Figure 31-10. Idle Supply Current vs. Vcc
fSYS = 1.0 MHz External Clock
300
250
200
150
100
50
85 °C
25 °C
-40 °C
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
68
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Figure 31-11. Idle Supply Current vs. Vcc
fSYS = 32.768 kHz internal RC
40
35
30
25
20
15
10
5
85 °C
-40 °C
25 °C
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 31-12. Idle Supply Current vs. Vcc
fSYS = 2.0 MHz internal RC
700
600
500
400
300
200
100
0
-40 °C
25 °C
85 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
69
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XMEGA D3
Figure 31-13. Idle Supply Current vs. Vcc
fSYS = 32 MHz internal RC prescaled to 8 MHz
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
-40 °C
25 °C
85 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 31-14. Idle Supply Current vs. Vcc
fSYS = 32 MHz internal RC
10
8
-40 °C
25 °C
85 °C
6
4
2
0
2.7
2.8
2.9
3
3.1
3.2
3.3
3.4
3.5
3.6
VCC [V]
70
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31.3 Power-down Supply Current
Figure 31-15. Power-down Supply Current vs. Temperature
2
1.8
1.6
1.4
1.2
1
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
0.8
0.6
0.4
0.2
0
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
Figure 31-16. Power-down Supply Current vs. Temperature
With WDT and sampled BOD enabled.
3
2.5
2
3.3 V
3.0 V
2.7 V
2.2 V
1.8 V
1.5
1
0.5
0
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
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31.4 Power-save Supply Current
Figure 31-17. Power-save Supply Current vs. Temperature
With WDT, sampled BOD and RTC from ULP enabled
3
2.5
2
3.3 V
3.0 V
2.7 V
1.8 V
2.2 V
1.5
1
0.5
0
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
31.5 Pin Pull-up
Figure 31-18. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 1.8V
100
80
60
40
20
0
-40 °C
25 °C
85 °C
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
V
RESET [V]
72
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Figure 31-19. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.0V
160
140
120
100
80
60
40
-40 °C
25 °C
85 °C
20
0
0
0.5
1
1.5
2
2.5
3
V
RESET [V]
Figure 31-20. Reset Pull-up Resistor Current vs. Reset Pin Voltage
VCC = 3.3V
180
160
140
120
100
80
60
40
-40 °C
25 °C
85 °C
20
0
0
0.5
1
1.5
2
2.5
3
VRESET [V]
73
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31.6 Pin Output Voltage vs. Sink/Source Current
Figure 31-21. I/O Pin Output Voltage vs. Source Current
Vcc = 1.8V
2
1.8
1.6
1.4
1.2
1
-40 °C
25 °C
85 °C
0.8
0.6
0.4
0.2
0
-6
-5
-4
-3
-2
-1
0
I
PIN [mA]
Figure 31-22. I/O Pin Output Voltage vs. Source Current
Vcc = 3.0V
3.5
3
-40 °C
25 °C
85 °C
2.5
2
1.5
1
0.5
0
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
IPIN [mA]
74
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XMEGA D3
Figure 31-23. I/O Pin Output Voltage vs. Source Current
Vcc = 3.3V
3.5
3
-40 °C
25 °C
85 °C
2.5
2
1.5
1
0.5
0
-10
-9
-8
-7
-6
-5
-4
-3
-2
-1
0
IPIN [mA]
Figure 31-24. I/O Pin Output Voltage vs. Sink Current
Vcc = 1.8V
85°C 25°C
1.8
1.6
1.4
1.2
1
-40 °C
0.8
0.6
0.4
0.2
0
0
1
2
3
4
5
6
7
8
9
10
IPIN [mA]
75
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XMEGA D3
Figure 31-25. I/O Pin Output Voltage vs. Sink Current
Vcc = 3.0V
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
85 °C
25 °C
-40 °C
0
1
2
3
4
5
6
7
8
9
10
IPIN [mA]
Figure 31-26. I/O Pin Output Voltage vs. Sink Current
Vcc = 3.3V
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
85 °C
25 °C
-40 °C
0
1
2
3
4
5
6
7
8
9
10
IPIN [mA]
76
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31.7 Pin Thresholds and Hysteresis
Figure 31-27. I/O Pin Input Threshold Voltage vs. VCC
VIH - I/O Pin Read as “1”
2.5
2
-40 °C
25 °C
85 °C
1.5
1
0.5
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 31-28. I/O Pin Input Threshold Voltage vs. VCC
VIL - I/O Pin Read as “0”
1.8
1.6
1.4
1.2
1
85 °C
25 °C
-40 °C
0.8
0.6
0.4
0.2
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
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XMEGA D3
Figure 31-29. I/O Pin Input Hysteresis vs. VCC
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
85 °C
25 °C
-40 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 31-30. Reset Input Threshold Voltage vs. VCC
VIH - I/O Pin Read as “1”
1.8
1.6
1.4
1.2
1
-40 °C
25 °C
85 °C
0.8
0.6
0.4
0.2
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
78
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XMEGA D3
Figure 31-31. Reset Input Threshold Voltage vs. VCC
VIL - I/O Pin Read as “0”
1.8
1.6
1.4
1.2
1
-40 °C
25 °C
85 °C
0.8
0.6
0.4
0.2
0
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
31.8 Bod Thresholds
Figure 31-32. BOD Thresholds vs. Temperature
BOD Level = 1.6V
1.67
1.66
Rising Vcc
Falling Vcc
1.65
1.64
1.63
1.62
1.61
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
79
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XMEGA D3
Figure 31-33. BOD Thresholds vs. Temperature
BOD Level = 2.9V
3.06
3.04
Rising Vcc
3.02
3
2.98
2.96
2.94
2.92
2.9
Falling Vcc
-40 -30 -20 -10
0
10
20
30
40
50
60
70
80
90
Temperature [°C]
31.9 Internal Oscillator Speed
31.9.1
Internal 32.768 kHz Oscillator
Figure 31-34. Internal 32.768 kHz Oscillator Calibration Step Size
T = -40 to 85°C, VCC = 3V
0.80 %
0.65 %
0.50 %
0.35 %
0.20 %
0.05 %
0
32
64
96
128
160
192
224
256
RC32KCAL[7..0]
80
8134D–AVR–12/09
XMEGA D3
31.9.2
Internal 2 MHz Oscillator
Figure 31-35. Internal 2 MHz Oscillator CALA Calibration Step Size
T = -40 to 85°C, VCC = 3V
0.50 %
0.40 %
0.30 %
0.20 %
0.10 %
0.00 %
-0.10 %
-0.20 %
-0.30 %
0
16
32
48
64
80
96
112
128
DFLLRC2MCALA
Figure 31-36. Internal 2 MHz Oscillator CALB Calibration Step Size
T = -40 to 85°C, VCC = 3V
3.00 %
2.50 %
2.00 %
1.50 %
1.00 %
0.50 %
0.00 %
0
8
16
24
32
40
48
56
64
DFLLRC2MCALB
81
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XMEGA D3
31.9.3
Internal 32 MHZ Oscillator
Figure 31-37. Internal 32 MHz Oscillator CALA Calibration Step Size
T = -40 to 85°C, VCC = 3V
0.60 %
0.50 %
0.40 %
0.30 %
0.20 %
0.10 %
0.00 %
-0.10 %
-0.20 %
0
16
32
48
64
80
96
112
128
DFLLRC32MCALA
Figure 31-38. Internal 32 MHz Oscillator CALB Calibration Step Size
T = -40 to 85°C, VCC = 3V
3.00 %
2.50 %
2.00 %
1.50 %
1.00 %
0.50 %
0.00 %
0
8
16
24
32
40
48
56
64
DFLLRC32MCALB
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XMEGA D3
31.10 Module current consumption
Figure 31-39. AC current consumption vs. Vcc
Low-power Mode
120
100
80
60
40
20
0
85 °C
25 °C
-40 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
V
CC [V]
Figure 31-40. Power-up current consumption vs. Vcc
700
-40 °C
25 °C
85 °C
600
500
400
300
200
100
0
0.4
0.6
0.8
1
1.2
1.4
1.6
VCC [V]
83
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XMEGA D3
31.11 Reset Pulsewidth
Figure 31-41. Minimum Reset Pulse Width vs. Vcc
120
100
80
60
40
20
0
85 °C
25 °C
-40 °C
1.6
1.8
2
2.2
2.4
2.6
2.8
3
3.2
3.4
3.6
VCC [V]
84
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XMEGA D3
32. Packaging information
32.1 64A
PIN 1
B
PIN 1 IDENTIFIER
E1
E
e
D1
D
C
0°~7°
A2
A
A1
L
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
–
MAX
1.20
NOM
–
NOTE
SYMBOL
A
A1
A2
D
0.05
0.95
15.75
13.90
15.75
13.90
0.30
0.09
0.45
–
0.15
1.00
16.00
14.00
16.00
14.00
–
1.05
16.25
D1
E
14.10 Note 2
16.25
Notes:
E1
B
14.10 Note 2
0.45
1.This package conforms to JEDEC reference MS-026, Variation AEB.
2. Dimensions D1 and E1 do not include mold protrusion. Allowable
protrusion is 0.25 mm per side. Dimensions D1 and E1 are maximum
plastic body size dimensions including mold mismatch.
C
–
0.20
3. Lead coplanarity is 0.10 mm maximum.
L
–
0.75
e
0.80 TYP
10/5/2001
TITLE
DRAWING NO. REV.
2325 Orchard Parkway
San Jose, CA 95131
64A, 64-lead, 14 x 14 mm Body Size, 1.0 mm Body Thickness,
0.8 mm Lead Pitch, Thin Profile Plastic Quad Flat Package (TQFP)
64A
B
R
85
8134D–AVR–12/09
XMEGA D3
32.2 64M2
D
Marked Pin# 1 ID
E
SEATING PLANE
C
A1
TOP VIEW
A
K
0.08
C
L
Pin #1 Corner
SIDE VIEW
D2
Pin #1
Triangle
Option A
1
2
3
COMMON DIMENSIONS
(Unit of Measure = mm)
MIN
0.80
–
MAX
1.00
0.05
0.30
9.10
7.80
9.10
NOM
0.90
0.02
0.25
9.00
7.65
9.00
NOTE
SYMBOL
E2
Option B
Option C
A
Pin #1
Chamfer
(C 0.30)
A1
b
0.18
8.90
7.50
8.90
D
D2
E
K
Pin #1
Notch
(0.20 R)
e
b
E2
e
7.50
7.65
0.50 BSC
0.40
7.80
BOTTOM VIEW
L
0.35
0.20
0.45
0.40
K
0.27
1. JEDEC Standard MO-220, (SAW Singulation) Fig. 1, VMMD.
2. Dimension and tolerance conform to ASMEY14.5M-1994.
Note:
5/25/06
DRAWING NO. REV.
64M2
TITLE
2325 Orchard Parkway
San Jose, CA 95131
64M2, 64-pad, 9 x 9 x 1.0 mm Body, Lead Pitch 0.50 mm,
7.65 mm Exposed Pad, Micro Lead Frame Package (MLF)
D
R
86
8134D–AVR–12/09
XMEGA D3
33. Errata
33.1 ATxmega256D3, ATxmega192D3, ATxmega128D3, ATxmega64D3
33.1.1
rev. B
• Bandgap voltage input for the ACs cannot be changed when used for both ACs simultaneously
• Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
• ADC gain stage cannot be used for single conversions
• ADC gain stage output range is limited to 2.4V
• ADC propagation delay not correct when 8x-6x gain is used
• ADC has increased INL error for some operating conditions
• BOD will be enabled after any reset
• Writing EEPROM or Flash while reading any of them will not work
• VCC voltage scaler for AC is non-linear
• Maximum operating frequency below 1.76V is 8 MHz
• TWIE is not available
1. Bandgap voltage input for the ACs cannot be changed when used for both ACs
simultaneously
If the bandgap voltage is selected as input for one Analog Comparator (AC) and then
selected/deselected as input for the another AC, the first comparator will be affected for up
to 1 us and could potentially give a wrong comparison result.
Problem fix/Workaround
If the Bandgap is required for both ACs simultaneously, configure the input selection for both
ACs before enabling any of them.
2. Bandgap measurement with the ADC is non-functional when VCC is below 2.7V
The ADC cannot be used to do bandgap measurements when VCC is below 2.7V.
Problem fix/Workaround
If internal voltages must be measured when VCC is below 2.7V, measure the internal 1.00V
reference instead of the bandgap.
3. ADC gain stage cannot be used for single conversion
The ADC gain stage will not output correct result for single conversions that is triggered and
started from software or the event system.
Problem fix/Workaround
When the gain stage is used, the ADC must be set in free running mode for correct results.
4. ADC gain stage output range is limited to 2.4 V
The amplified output of the ADC gain stage will never go above 2.4 V, hence the differential
input will only give correct output when below 2.4 V/gain. For the available gain settings, this
gives a differential input range of:
87
8134D–AVR–12/09
XMEGA D3
–
–
–
–
–
–
–
1x gain:
2x gain:
4x gain:
8x gain:
16x gain:
32x gain:
64x gain:
2.4
1.2
0.6
V
V
V
300 mV
150 mV
75 mV
38 mV
Problem fix/Workaround
Keep the amplified voltage output from the ADC gain stage below 2.4 V in order to get a cor-
rect result, or keep ADC voltage reference below 2.4 V.
5. ADC has increased INL error for some operating conditions
Some ADC configurations or operating condition will result in increased INL error.
In differential mode INL is increased to:
– 6 LSB for sample rates above 130 kSPS, and up to 8 LSB for 200 kSPS sample rate.
– 6 LSB for reference voltage below 1.1V when VCC is above 3.0V.
– 20 LSB for ambient temperature below 0 degree C and reference voltage below 1.3V.
In single ended mode, the INL is increased up to a factor of 3 for the conditions above.
Problem fix/Workaround
None, avoid using the ADC in the above configurations in order to prevent increased INL
error.
6. ADC propagation delay not correct when 8x-64x gain is used
The propagation delay will increase by only one ADC clock cycle for the 8x and 16x gain set-
ting, and 32x and 64x gain settings.
Problem fix/Workaround
None.
7. BOD will be enabled after any reset
If any reset source goes active, the BOD will be enabled and keep the device in reset if the
VCC voltage is below the programmed BOD level. During Power-On Reset, reset will not be
released until VCC is above the programmed BOD level even if the BOD is disabled.
Problem fix/Workaround
Do not set the BOD level higher than VCC even if the BOD is not used.
8. Writing EEPROM or Flash while reading any of them will not work
The EEPROM and Flash cannot be written while reading EEPROM or Flash, or while exe-
cuting code in Active mode.
Problem fix/Workaround
Enter IDLE sleep mode within 2.5 uS (Five 2 MHz clock cycles and 80 32 MHz clock cycles)
after starting an EEPROM or flash write operation. Wake-up source must either be
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8134D–AVR–12/09
XMEGA D3
EEPROM ready or NVM ready interrupt. Alternatively set up a Timer/Counter to give an
overflow interrupt 7 mS after the erase or write operation has started, or 13 mS after atomic
erase-and-write operation has started, and then enter IDLE sleep mode.
9. VCC voltage scaler for AC is non-linear
The 6-bit VCC voltage scaler in the Analog Comparators is non-linear. Problem
fix/Workaround
Use external voltage input for the analog comparator if accurate voltage levels are needed.
10. Maximum operating frequency below 1.76V is 8 MHz
To ensure correct operation, the maximum operating frequency below 1.76V VCC is 8 MHz.
Problem fix/Workaround
None, avoid running the device outside this frequency and voltage limitation.
11. TWIE is not available
The TWI module on PORTE, TWIE is not available.
Problem fix/Workaround
Use the identical TWI module on PORTC, TWIC instead.
33.1.2
All rev. A
Not sampled.
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34. Datasheet Revision History
Please note that the referring page numbers in this section are referred to this document. The
referring revisions in this section are referring to the document revision.
34.1 8134D – 11/09
1.
2.
3.
4.
Added Table 30-3 on page 59, Endurance and Data Retention.
Updated Table 30-10 on page 62, Input hysteresis is in V and not in mV.
Added ”Errata” on page 87.
Editing updates.
34.2 8134C – 10/09
1.
2.
3.
4.
5.
6.
7.
8.
Updated ”Features” on page 1 with Two Two-Wire Interfaces.
Updated ”Block diagram and pinout” on page 3.
Updated ”Overview” on page 4.
Updated ”XMEGA D3 Block Diagram” on page 5.
Updated Table 13-1 on page 24.
Updated ”Overview” on page 35.
Updated Table 27-5 on page 49.
Updated ”Peripheral Module Address Map” on page 51.
34.3 8134B – 08/09
34.4 8134A – 03/09
1.
2.
Added ”Electrical Characteristics” on page 56.
Added ”Typical Characteristics” on page 64.
1.
Initial revision.
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8134D–AVR–12/09
XMEGA D3
Table of Contents
Features..................................................................................................... 1
Typical Applications ................................................................................ 1
Ordering Information ............................................................................... 2
Pinout/ Block Diagram ............................................................................. 3
1
2
3
Overview ................................................................................................... 4
3.1Block Diagram ...........................................................................................................5
4
Resources ................................................................................................. 6
4.1Recommended reading .............................................................................................6
5
6
Disclaimer ................................................................................................. 6
AVR CPU ................................................................................................... 7
6.1Features ....................................................................................................................7
6.2Overview ...................................................................................................................7
6.3Register File ..............................................................................................................8
6.4ALU - Arithmetic Logic Unit .......................................................................................8
6.5Program Flow ............................................................................................................8
7
Memories .................................................................................................. 9
7.1Features ....................................................................................................................9
7.2Overview ...................................................................................................................9
7.3In-System Programmable Flash Program Memory ...................................................9
7.4Data Memory ...........................................................................................................11
7.5Production Signature Row .......................................................................................13
7.6User Signature Row ................................................................................................13
7.7Flash and EEPROM Page Size ...............................................................................14
8
9
Event System ......................................................................................... 15
8.1Features ..................................................................................................................15
8.2Overview .................................................................................................................15
System Clock and Clock options ......................................................... 17
9.1Features ..................................................................................................................17
9.2Overview .................................................................................................................17
9.3Clock Options ..........................................................................................................18
10 Power Management and Sleep Modes ................................................. 20
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8134D–AVR–12/09
XMEGA D3
10.1Features ................................................................................................................20
10.2Overview ...............................................................................................................20
10.3Sleep Modes .........................................................................................................20
11 System Control and Reset .................................................................... 22
11.1Features ................................................................................................................22
11.2Resetting the AVR .................................................................................................22
11.3Reset Sources .......................................................................................................22
12 WDT - Watchdog Timer ......................................................................... 23
12.1Features ................................................................................................................23
12.2Overview ...............................................................................................................23
13 PMIC - Programmable Multi-level Interrupt Controller ....................... 24
13.1Features ................................................................................................................24
13.2Overview ...............................................................................................................24
13.3Interrupt vectors ....................................................................................................24
14 I/O Ports .................................................................................................. 26
14.1Features ................................................................................................................26
14.2Overview ...............................................................................................................26
14.3I/O configuration ....................................................................................................26
14.4Input sensing .........................................................................................................29
14.5Port Interrupt .........................................................................................................29
14.6Alternate Port Functions ........................................................................................29
15 T/C - 16-bits Timer/Counter with PWM ................................................. 30
15.1Features ................................................................................................................30
15.2Overview ...............................................................................................................30
16 AWEX - Advanced Waveform Extension ............................................. 32
16.1Features ................................................................................................................32
16.2Overview ...............................................................................................................32
17 Hi-Res - High Resolution Extension ..................................................... 33
17.1Features ................................................................................................................33
17.2Overview ...............................................................................................................33
18 RTC - Real-Time Counter ...................................................................... 34
18.1Features ................................................................................................................34
18.2Overview ...............................................................................................................34
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XMEGA D3
19 TWI - Two Wire Interface ....................................................................... 35
19.1Features ................................................................................................................35
19.2Overview ...............................................................................................................35
20 SPI - Serial Peripheral Interface ............................................................ 36
20.1Features ................................................................................................................36
20.2Overview ...............................................................................................................36
21 USART ..................................................................................................... 37
21.1Features ................................................................................................................37
21.2Overview ...............................................................................................................37
22 IRCOM - IR Communication Module .................................................... 38
22.1Features ................................................................................................................38
22.2Overview ...............................................................................................................38
23 ADC - 12-bit Analog to Digital Converter ............................................. 39
23.1Features ................................................................................................................39
23.2Overview ...............................................................................................................39
24 AC - Analog Comparator ....................................................................... 41
24.1Features ................................................................................................................41
24.2Overview ...............................................................................................................41
24.3Input Selection .......................................................................................................43
24.4Window Function ...................................................................................................43
25 OCD - On-chip Debug ............................................................................ 44
25.1Features ................................................................................................................44
25.2Overview ...............................................................................................................44
26 PDI - Program and Debug Interface ..................................................... 45
26.1Features ................................................................................................................45
26.2Overview ...............................................................................................................45
27 Pinout and Pin Functions ...................................................................... 46
27.1Alternate Pin Function Description ........................................................................46
27.2Alternate Pin Functions .........................................................................................48
28 Peripheral Module Address Map .......................................................... 51
29 Instruction Set Summary ...................................................................... 52
30 Electrical Characteristics ...................................................................... 56
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30.1Absolute Maximum Ratings* .................................................................................56
30.2DC Characteristics ................................................................................................56
30.3Operating Voltage and Frequency ........................................................................58
30.4Flash and EEPROM Memory Characteristics .......................................................59
30.5ADC Characteristics ..............................................................................................60
30.6Analog Comparator Characteristics .......................................................................61
30.7Bandgap Characteristics .......................................................................................61
30.8Brownout Detection Characteristics ......................................................................61
30.9PAD Characteristics ..............................................................................................62
30.10POR Characteristics ............................................................................................62
30.11Reset Characteristics ..........................................................................................62
30.12Oscillator Characteristics .....................................................................................63
31 Typical Characteristics .......................................................................... 64
31.1Active Supply Current ............................................................................................64
31.2Idle Supply Current ................................................................................................67
31.3Power-down Supply Current .................................................................................71
31.4Power-save Supply Current ..................................................................................72
31.5Pin Pull-up .............................................................................................................72
31.6Pin Output Voltage vs. Sink/Source Current .........................................................74
31.7Pin Thresholds and Hysteresis ..............................................................................77
31.8Bod Thresholds .....................................................................................................79
31.9Internal Oscillator Speed .......................................................................................80
31.10Module current consumption ...............................................................................83
31.11Reset Pulsewidth .................................................................................................84
32 Packaging information .......................................................................... 85
32.164A ........................................................................................................................85
32.264M2 .....................................................................................................................86
33 Errata ....................................................................................................... 87
33.1ATxmega256D3, ATxmega192D3, ATxmega128D3, ATxmega64D3 ...................87
34 Datasheet Revision History .................................................................. 90
34.18134D – 11/09 .......................................................................................................90
34.28134C – 10/09 .......................................................................................................90
34.38134B – 08/09 .......................................................................................................90
34.48134A – 03/09 .......................................................................................................90
iv
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Table of Contents....................................................................................... i
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8134D–AVR–12/09
相关型号:
ATXMEGA64D3-MHR
RISC Microcontroller, 16-Bit, FLASH, AVR RISC CPU, 32MHz, CMOS, 9 X 9 MM, 1 MM HEIGHT, 0.50 MM PITCH, GREEN, MO-220VMMD, MLF-64
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