E1466D-S8Y [ATMEL]
Stepping Motor Clock, CMOS, PDSO8, LEAD FREE, SO-8;
| 型号： | E1466D-S8Y |
| 厂家： | 
ATMEL |
| 描述： | Stepping Motor Clock, CMOS, PDSO8, LEAD FREE, SO-8 ATM 电池 异步传输模式 模拟时钟 光电二极管 商用集成电路 振荡器 |
| 文件： | 总11页 (文件大小：212K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• 32-kHz Crystal Oscillator
• 1.1V to 2.2V Operating-voltage Range
• Integrated Capacitors for Digital Trimming
• Suitable for up to 12.5 pF Quartz
• Output Pulse Formers
• Mask Options for Motor Period and Pulse Width
• Low Resistance Output for Bipolar Stepping Motor
• Motor Fast-test Function
32-kHz Clock
CMOS IC with
Digital
1. Description
The e1466D is an integrated circuit in CMOS Silicon Gate Technology for analog
clocks. It consists of a 32-kHz oscillator, frequency divider, output pulse formers and
push-pull motor drivers. Integrated capacitors are mask-selectable to accommodate
the external quartz crystal. Additional capacitance can be selected through pad bond-
ing for trimming the oscillator frequency.
Trimming
e1466D
4731D–CLOCK–09/07
2. Pin Configuration
Figure 2-1. Pad Layout
C3 C2 C1
10 11 12
C4
9
VDD(1)
1
2
OSCIN
8
OSCOUT(1)
e1466D
7
6
VSS
TEST(2)
MOT1(2)
3
MOT2
MOT1
5
4
(1) The pads VDD and OSCOUT are interchangeable per mask option
(2) The pads TEST and MOT1 are interchangeable per mask option
Figure 2-2. Pinning DIP8
VDD
VSS
1
2
3
4
8
7
6
5
OSCIN
OSCOUT
NC
MOT1
NC
MOT2
Figure 2-3. Pinning SO8
VSS
TEST
MOT1
MOT2
1
2
3
4
8
7
6
5
VDD
C3
OSCIN
OSCOUT
Table 2-1.
Pin Description
Name
Description
Positive supply voltage
Negative supply voltage
Oscillator input
VDD
VSS
OSCIN
OSCOUT
MOT1/2
C1, C2, C3, C4
TEST
Oscillator output
Motor drive outputs
Oscillator trimming inputs
TEST input/output
Not connected
NC
2
e1466D
4731D–CLOCK–09/07
e1466D
3. Functional Description
3.1
Oscillator
An oscillator inverter with feedback resistor is provided to generate the 32768 Hz clock
frequency. Values for the fixed capacitors at OSCIN and OSCOUT are mask-selectable (see
note 3 of “Operating Characteristics”). Four capacitor pads, C1 to C4, enable the users to add
integrated trimming capacitors to OSCIN, providing 15 tuning steps.
3.2
Trimming Capacitors
A frequency variation of typically 4 ppm for each tuning step is obtained by bonding the capacitor
pads to OSCIN. As none of these pads are bonded, the IC is in an untrimmed state. Figure 6-1
on page 6 shows the trimming curve characteristic.
Note:
For applications which utilize this integrated trimming feature, Atmel will determine optimum val-
ues for the integrated capacitors COSCIN and COSCOUT.
Capacitor pads C1 to C4: 0 = open, 1 = connected to OSCIN
Combination C1 + C4 is redundant and therefore eliminated from the list
Table 3-1.
Frequency Trimming Table
Capacitor Pads
C4
C3
C2
C1
Trimming Step
0
0
0
0
0
0
0
1
0
0
1
0
0
1
0
0
0
1
2
3
1
0
0
0
0
0
1
1
0
1
0
1
0
1
1
0
4
5
6
7
1
1
0
0
1
1
1
0
1
0
0
1
8
9
10
1
1
1
1
0
1
1
1
1
0
1
1
1
1
0
1
11
12
13
14
3
4731D–CLOCK–09/07
3.3
Motor Drive Output
The e1466D contains two push-pull output buffers for driving bipolar stepping motors. During a
motor pulse, the N-channel device of one buffer and the P-channel device of the other buffer will
be activated. Both N-channel transistors are on and conducting between output pulses. The out-
puts are protected against inductive voltage spikes with diodes to both supply pins. The motor
output period and pulse width are mask-programmable, as listed below:
Available motor periods (TM): 125, 250, 500 ms and 2, 16s
Available max. pulse widths (tM): 15, 6, 23.4, 31.25, 46.9 ms and 1s
Available motor periods for motor test (TMT): 250, 500 ms and 1s
Note:
The following constraints for combination of motor period and pulse widths have to be considered:
TM > 4 × tM, TMT > 4 × tM or alternatively TM = 2 × tM, TMT = 2 × tM
3.4
Test Functions
For test purposes, the TEST pad is open. With a high resistance probe (R ≥ 10 MΩ, C ≥ 20 pF),
a test frequency fTEST of 128 Hz can be measured at the TEST pad. Connecting TEST (for at
least 32 ms) to VDD changes the motor period from the selected value to TMT (mask-selectable)
while the pulse width remains unaffected. This feature can be used for testing the mechanical
parts of the clock.
4. Absolute Maximum Ratings
Absolute maximum ratings define parameter limits which, if exceeded, may permanently change or damage the device.
All inputs and outputs on Atmel’s circuits are protected against electrostatic discharges. However, precautions to minimize the build-up of
electrostatic charges during handling are recommended.
The circuit is protected against supply voltage reversal for typically 5 minutes.
Parameters
Symbol
VSS
Value
Unit
V
Supply voltage
–0.3 to 5 V
Input voltage range, all inputs
Output short-circuit duration
Power dissipation (DIL package)
Operating ambient temperature range
Storage temperature range
VIN
(VSS – 0.3V) ≤ VIN ≤ (VDD + 0.3V)
V
indefinite
125
Ptot
Tamb
Tstg
Tsld
mW
°C
–20 to +70
–40 to +125
260
°C
Lead temperature during soldering at 2 mm distance, 10s
°C
4
e1466D
4731D–CLOCK–09/07
e1466D
5. Operating Characteristics
VSS = 0V, VDD = 1.5V, Tamb = +25°C, unless otherwise specified.
All voltage levels are measured with reference to VSS. Test crystal as specified below.
Parameters
Test Conditions
Symbol
VDD
Min.
1.1
Typ.
Max.
Unit
V
Operating voltage
1.5
2.2
+70
5
Operating temperature
Operating current
Tamb
–20
°C
(2)
R1 = ∞
IDD
2
mA
Motor Drive Output
Motor output current
Motor period
VDD = 1.2V, R1 = 200Ω
IM
TM
TMT
tM
±4.3
1.2
mA
See option list
See option list
See option list
Motor period during motor test
Motor pulse width
Oscillator
Startup voltage
Within 2s
VSTART
∆f/f
2.2
V
Frequency stability
Integrated input capacitance
Integrated output capacitance
∆VDD = 100 mV, VDD = 1.1 to 2.2V
(3)
1
ppm
COSCIN
COSCOUT
See option list
See option list
C1
C2
C3
C4
3
4
5
6
pF
pF
pF
pF
(4)
Integrated capacitance for bond option
TEST Input
Input current
TEST = VDD peak current
TEST = VSS peak current
ITINH
ITINL
tTIN
0.6
3
10
µA
µA
ms
Input current
–0.6
23.4
–3
–10
31.2
Input debounce delay
Notes: 1. Typical parameters represent the statistical mean values
2. See test circuit
3. Values can be selected in 1 pF steps. A total capacitance (COSCIN + COSCOUT) of 38 pF is available
4. These values are valid for 10 pF quartz applications. For CL = 12.5 pF these values change to 4.5, 6, 7.5, 9 pF
Figure 5-1. Functional Test
VDD
C4 C3 C2 C1
OSCIN
VSS
OSCOUT
e1466D
TEST
MOT2
R1
MOT1
MOT1
5
4731D–CLOCK–09/07
6. Test Crystal Specification
Oscillation frequency
Series resistance
Static capacitance
fOSC = 32768 Hz
RS = 30 kΩ
C0 = 1.5 pF
Dynamic capacitance C1 = 3.0 fF
Load capacitance
CL optionally 10 or 12.5 pF
Figure 6-1. Motor Output Signal During Normal Operation and During Motor Test
Detail a
VDD
VSS
TEST
MOT1
VDD
VSS
tM
MOT2
VDD
VSS
TM
TMT
Detail a:
1/fTEST
Figure 6-2. Typical Trimming Curve Characteristic for TM of 2s
2.00006
2.00005
2.00004
2.00003
2.00002
2.00001
2.00000
1.99999
1.99998
1.99997
1.99996
1.99995
1.99994
1.99993
1.99992
1.99991
COX = 1.05
COX = 1.00
COX = 0.95
0
1
2
3
4
5
6
7
8
9
10 11 12 13 14
Trimming Step
COX means frequency deviation due to production process variations.
Trimming inputs C1 ... C4 are binary weighted, i.e.,
C1 ... C4 = 0 corresponds to trimming step 0
C1 ... C4 = 1 corresponds to trimming step 15
LSB = C1
6
e1466D
4731D–CLOCK–09/07
e1466D
7. Ordering Information
Table 7-1.
Option
Option List e1466Dx
Load
Capacitance
Motor
Integrated Capacitance
(1)
(1)
Cycle Pulse
Test
COSCIN
COSCOUT
C1
C2
C3
C4
(TM)
s
(tM)
ms
(TMT
ms
)
x
pF
pF
pF
pF
pF
pF
pF
500/
250
HO
2
1000
9
20
3
4
5
6
10
Note:
1. On-chip stray capacitance included
Option
Pad Designation
x
Pad 1
Pad 2
Pad 3
Pad 4
Pad 5
Pad 6
Pad 7
Pad 8
Pad 9
C4
Pad 10 Pad 11 Pad 12
C3 C2 C1
HO
OSCIN OSCOUT MOT2
MOT1
MOT1
TEST
VSS
VDD
Table 7-2.
Package List
Extended Type Number
e1466x-P8Y
Package
DIP8
Remarks
Tube, Pb-free
Tube, Pb-free
e1466x-S8Y
SO8
e1466x-S8G3Y
SO8
Taped and reeled, Pb-free
7
4731D–CLOCK–09/07
8. Package Information
Package: DIP8
Dimensions in mm
9.8 max.
9.6±0.1
7.62±0.15
0.3 B
A
1.2±0.3
0.53±0.05
6.3±0.1
0.4 A
2.54 nom.
B
8.75±0.8
3 x 2.54 = 7.62 nom.
1.54
0.65
5
8
1
technical drawings
according to DIN
specifications
4
Drawing-No.: 6.543-5040.01-4
Issue: 1; 16.01.02
8
e1466D
4731D–CLOCK–09/07
e1466D
Package: SO 8
Dimensions in mm
5±0.2
4.9±0.1
3.7±0.1
3.8±0.1
6±0.2
0.4
1.27
3.81
8
5
technical drawings
according to DIN
specifications
1
4
Drawing-No.: 6.541-5031.01-4
Issue: 1; 15.08.06
9
4731D–CLOCK–09/07
9. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
• Put datasheet in a new template
4731D-CLOCK-09/07
• Pb-free logo on page 1 deleted
• Section 7 “Ordering Information” on page 7 changed
• First page: Pb-free logo added
• Figure 1-2 on page 2 heading changed in “Pinning DIP8”
• Page 7: Table 7-1: FO rows added
4731C-CLOCK-08/05
4731B-CLOCK-01/05
• Page 7: Table 7-2: Package List added
• Page 8+9: Package drawings added
• Put datasheet in a new template
• Figure 1-1 “Pad Layout” on page 2 changed
• Figure 1-2 “Pinning DP8” on page 2 added
• Figure 1-3 “Pinning SO8” on page 2 added
• Table 6-1 “Option List e1466Dx” on page 7 changed
10
e1466D
4731D–CLOCK–09/07
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4731D–CLOCK–09/07
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