MG2044(256MQFP) [ATMEL]
Field Programmable Gate Array, CMOS, PQFP256;
| 型号： | MG2044(256MQFP) |
| 厂家： | 
ATMEL |
| 描述： | Field Programmable Gate Array, CMOS, PQFP256 栅 可编程逻辑 |
| 文件： | 总13页 (文件大小：215K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Full Range of Matrices with up to 480K Gates
• 0.5 µm Drawn CMOS, 3 Metal Layers, Sea of Gates
• RAM and DPRAM Compilers
• Library Optimized for Synthesis, Floor Plan and Automatic Test Generation (ATG)
• 3 and 5 Volts Operation; Single or Dual Supply Mode
• High Speed Performances
– 420 ps Max NAND2 Propagation Delay at 4.5V, 670 ps at 2.7 and FO = 5
– Min 650 MHz Toggle Frequency at 4.5V and 340 MHz at 2.7V
• Programmable PLL Available on Request
• High System Frequency Skew Control through Clock Tree Synthesis Software
• Low Power Consumption:
350K Used Gates
0.5 µm CMOS
Sea of Gates
– 1.96 µW/Gate/MHz at 5V
– 0.6 µW/Gate/MHz at 3V
• Integrated Power On Reset
• Matrices With a Max of 484 Fully Programmable Pads
• Standard 3, 6, 12 and 24 mA I/Os
• Versatile I/O Cell: Input, Output, I/O, Supply, Oscillator
• CMOS/TTL/PCI Interface
MG2
• ESD (2 KV) and Latch-up Protected I/O
• High Noise and EMC Immunity:
– I/O with Slew Rate Control
– Internal Decoupling
– Signal Filtering between Periphery and Core
– Application Dependent Supply Routing and Several Independent Supply Sources
• Wide Range of Hermetic and Plastic Packages
• Delivery in Die Form with 94.6 µm Pad Pitch
• Advanced CAD Support: Floor Plan, Proprietary Delay Models, Timing Driven Layout,
Power Management
• Cadence®, Mentor™, Vital and Synopsys® Reference Platforms
• EDIF and VHDL Reference Formats
• Available In Commercial, Industrial and Military Quality Grades (for Space Application
see MG2RT and MG2RTP Specifications)
• QML Q with SMD 5962-00B02
Description
The MG2 series is a 0.5 micron, array based, CMOS product family. Several arrays up
to 480K gates cover most system integration needs. The MG2 is manufactured using
a 0.5 micron drawn, 3 metal layers CMOS process, called SCMOS 3/2.
The base cell architecture of the MG2 series provides high routability of logic with
extremely dense compiled memories: RAM and DPRAM. ROM can be generated
using synthesis tools.
Accurate control of clock distribution can be achieved by PLL hardware and CTS
(Clock Tree Synthesis) software. New noise prevention techniques are applied in the
array and in the periphery: three or more independent supplies, internal decoupling,
customization dependent supply routing, noise filtering, skew controlled I/Os, low
swing differential I/Os, all contribute to improve the noise immunity and reduce the
emission level.
The MG2 is supported by an advanced software environment based on industry stan-
dards linking proprietary and commercial tools. Verilog, Modelsim, Design Compiler
are the reference front-end tools. Floor planning associated with timing driven layout
provides a short back-end cycle.
The MG2 library allows straight forward migration from MG1 Sea of Gates. A netlist
based on this library can be simulated as either MG2, or MG2RT or MG2RTP.
4137O–AERO–06/05
Table 1. List of Available MG2 Matrices
Typical Usable
Type
Total Gates
44616
Gates
Total Pads
173
Maximum Programmable I/Os
MG2044 (1)
MG2091 (1)
MG2194
31200
150
214
310
362
422
484
91464
64000
237
193800
264375
361680
481143
135600
185000
253100
336800
333
MG2265 (1)
MG2360
385
445
MG2480
507
Note:
1. Not available for new designs.
Libraries
The MG2 cell library has been designed to take full advantage of the features offered by both
logic and test synthesis tools.
Design testability is assured by the full support of SCAN, JTAG (IEEE 1149) and BIST
methodologies.
More complex macro functions are available in VHDL, for example: I2C, UART,
Timer, etc.
Block Generators
Block generators are used to create a customer-specific simulation model and metallisation pat-
tern for regular functions like RAM and DPRAM. The basic cell architecture allows one bit per
cell for RAM and DPRAM. The main characteristics of these generators are summarized below.
Table 2. Block Generator Capability
Typical Characteristics (16k bits) at 5V
Maximum
Function
RAM
Size (bits)
Bits/Word
Access Time (ns)
Used Cells
32k
1-36
8
20 k
DPRAM
32k
1-36
8.6
23 k
2
MG2
4137O–AERO–06/05
MG2
I/O Buffer Interfacing
I/O Flexibility
All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A level
translator is located close to each buffer.
Inputs
Input buffers with CMOS or TTL thresholds are non-inverting and feature versions with and with-
out hysteresis. The CMOS and TTL input buffers may incorporate pull-up or pull down
terminators. For special purposes, a buffer allowing direct input to the matrix core is available.
Outputs
Several kinds of CMOS and TTL output drivers are offered: fast buffers with 3, 6, 12 and 24 mA
drive at 5V, low noise buffers with 12 mA drive at 5V.
Clock Generation and PLL
Clock Generation
Atmel offers 6 different types of oscillators: 4 high frequency crystal oscillators and 2 RC oscilla-
tors. For all devices, the mark-space ratio is better than 40/60 and the start-up time less than 10
ms.
Frequency (MHz)
Typical Consumption (mA)
Oscillators
Xtal 7M
Max 5V
Max 3V
7
5V
1.2
2.5
7
3V
0.4
0.8
2
12
28
Xtal 20M
Xtal 50M
Xtal 100M
RC 10M
RC 32M
17
70
40
130
10
75
16
2
5
10
1
32
32
3
1.5
PLL
Contact factory.
3
4137O–AERO–06/05
Power Supply
and Noise
The speed and density of the SCMOS3/2 technology causes large switching current spikes, for
example, when:
•
•
16 high current output buffers switch simultaneously,
or 10% of the 480,000 gates are switching within a window of 1 ns.
Protection
Sharp edges and high currents cause some parasitic elements in the packaging to become sig-
nificant. In this frequency range, the package inductance and series resistance should be taken
into account. It is known that an inductor slows down the settling time of the current and causes
voltage drops on the power supply lines. These drops can affect the behavior of the circuit itself
or disturb the external application (ground bounce).
In order to improve the noise immunity of the MG core matrix, several mechanisms have been
implemented inside the MG arrays. Two kinds of protection have been added: one to limit the I/O
buffer switching noise and the other to protect the I/O buffers against the switching noise coming
from the matrix.
I/O Buffers
Switching
Protection
Three features are implemented to limit the noise generated by the switching current:
•
•
•
The power supplies of the input and output buffers are separated.
The rise and fall times of the output buffers can be controlled by an internal regulator.
A design rule concerning the number of buffers connected on the same power supply line
has been imposed.
Matrix Switching
This noise disturbance is caused by a large number of gates switching simultaneously. To allow
this without impacting the functionality of the circuit, three new features have been added:
Current Protection
•
•
Decoupling capacitors are integrated directly on the silicon to reduce the power supply drop.
A power supply network has been implemented in the matrix. This solution reduces the
number of parasitic elements such as inductance and resistance and constitutes an artificial
VDD and Ground plane. One mesh of the network supplies approximately 150 cells.
•
A low pass filter has been added between the matrix and the input to the output buffer. This
limits the transmission of the noise coming from the ground or the VDD supply of the matrix
to the external world via the output buffers.
4
MG2
4137O–AERO–06/05
MG2
Packaging
Atmel offers a wide range of packaging options which are listed below:
Table 3. Packaging Options
Pins
Min./Max
Lead Spacing
(mils)
Package Type (1)
132
160
25,6
25,6
CQPF
196
256
352
25
20
20
MQFP
Notes: 1. Contact Atmel Local Design Centers to check the availability of the matrix/package
combination.
2. Contact factory.
5
4137O–AERO–06/05
Design Flows and Tools
Design Flows and A generic design flow for an MG2 array is illustrated below.
Modes
A top down design methodology is proposed which starts with high level system description and
is refined in successive design steps. At each step, structural verification is performed which
includes the following tasks:
•
•
•
•
Gate level logic simulation and comparison with high level simulation results.
Design and test rules check.
Power consumption analysis.
Timing analysis (only after floor plan).
The main design stages are:
•
•
•
•
•
•
•
System specification, preferably in VHDL form.
Functional description at RTL level.
Logic synthesis.
Floor planning and bonding diagram generation.
Test/Scan insertion, ATG and/or fault simulation.
Physical cell placement, JTAG insertion and clock tree synthesis.
Routing.
To meet the various requirements of designers, several interface levels between the customer
and Atmel are possible.
For each of the possible design modes a review meeting is required for data transfer from the
user to Atmel. In all cases the final routing and verifications are performed by Atmel.
The design acceptance is formalized by a design review which authorizes Atmel to proceed with
sample manufacturing.
6
MG2
4137O–AERO–06/05
MG2
Figure 1. MG2 Design Flow
System
Specifications
RTL
Simulation
Logic
Synthesis
Floor Plan
Bonding Diagram
Gate Level Simulation
Scan Insertion
ATG and Fault Simulation
Placement
JTAG Insertion
Clock Tree Synthesis
Routing & Extract
Back Annotated
Simulation
Sign-off
Samples
Manufacturing
and Test
7
4137O–AERO–06/05
Design Tools and
Design Kits (DK)
The basic content of a design kit is described in the table below.
The interface formats to and from Atmel rely on IEEE or industry standard:
•
•
•
•
•
VHDL for functional descriptions
VHDL or EDIF for netlists
Tabular, log or .VCD for simulation results
SDF (VITAL format) and SPF for back annotation
LEF and DEF for physical floor plan information
The design kits supported for several commercial tools is outlined below.
Design Kit Support
•
•
•
•
Cadence/Verilog (RTL and gate), Logic Design Planner
Mentor/Modelsim (RTL and gate), Velocity, BSD Archictect, Flex Test
Synopsys/Design Compiler, Prime Time
Vital
Table 4. Design Kit Description
Atmel
Software
Name
Third
Party
Tools
Design Tool or Library
Design manual and libraries
Synthesis library
(1)
(1)
(1)
Gate level simulation library
Design rules analyzer
STAR
Power consumption analyzer
Floor plan library
COMET
(1)
(1)
Timing analyzer library
Package and bonding software
Scan path and JTAG insertion
ATG and fault simulation library
PIM
(1)
(1)
Note:
1. Refer to ‘Design kits cross reference tables’ ATD-TS-WF-R0181
8
MG2
4137O–AERO–06/05
MG2
Electrical Characteristics
Absolute Maximum Ratings
*NOTE:
Stresses above those listed may cause perma-
Ambient temperature under bias (TA)
nent damage to the device. Exposure to absolute
maximum rating conditions for extended periods
may affect device reliability.
Military .......................................................... -55°C to +125°C
Junction temperature....................................... TJ < TA + 20°C
Storage temperature...................................... -65°C to +150°C
TLL/CMOS:
Supply voltage VDD..............................................-0.5V to +7V
I/O voltage ............................................... -0.5V to VDD + 0.5V
9
4137O–AERO–06/05
DC Characteristics
Table 5. DC Characteristics - Specified at VDD = +5V ± 10%
Symbol
Parameter
Min.
Typ
Max
Unit
Conditions
Input LOW voltage(3)
CMOS input
TTL input
VIL
0
0
–
1.5
0.8
V
–
Input HIGH voltage(3)
CMOS input
TTL input
3.5
2.2
VDD
VDD
VIH
–
–
V
VOL
VOH
Output LOW voltage
Output HIGH voltage
–
–
0.4
–
V
V
IOL = 24,12, 6, 3 mA(1)
3.9
IOH = -24,-12, -6, -3 mA(1)
Schmitt trigger positive threshold
CMOS input
TTL input
3.6
1.8
V
VT+
–
–
–
Schmitt trigger negative threshold
CMOS input
TTL input
1.2
1.0
V
VT-
–
–
–
–
CMOS hysteresis 25°C/5V
TTL hysteresis 25°C/5V
1.9
0.6
Delta V
–
V
Input low leakage
No pull up/down
Pull up
-5
-120
-5
+5
µA
µA
µA
IIL
–
-55
-69
Pull down
+5
Input High leakage
No pull up/down
Pull up
-5
-5
79
+5
+5
330
µA
µA
µA
IIH
–
–
125
–
Pull down
IOZ
IOS
3-State Output Leakage current
±5
µA
90
BOUT3
BOUT6
BOUT12
BOUT24
180
270
540
Output Short circuit current (2)
–
mA
ICCSB
ICCOP
Leakage current per cell
Operating current per cell
–
–
1.0
10.0
0.58
nA
–
–
0.39
µA/MHz
Notes: 1. According buffer: Bout24,Bout12, Bout6, Bout3.
2. Supplied as a design limit but not guarantedd or tested. No more than one outout may be shorted at a time for a maximum
duration of 10 seconds.
3. Without Schmitt trigger.
10
MG2
4137O–AERO–06/05
MG2
Table 6. DC Characteristics
Specified at VDD = +3V ± 0.3V
Symbol
Parameter
Min.
Typ
Max
Unit
Conditions
Input LOW voltage(3)
LVCMOS input
LVTTL input
VIL
–
0.3VDD
0.8
–
–
0
0
V
Input HIGH voltage(3)
LVCMOS input
LVTTL input
VDD
VDD
VIH
0.7VDD
2.0
–
V
Output LOW voltage
LVTTL
VOL
VOH
–
–
IOL = 12,6, 3, 1.5 mA(1)
IOH = -10,-4, -2, -1 mA(1)
0.4
V
V
Output HIGH voltage
LVTTL
2.4
–
Schmitt trigger positive threshold
LVCMOS input
LVTTL input
VT+
–
–
2.2
1.2
–
V
V
Schmitt trigger negative threshold
LVCMOS input
LVTTL input
VT-
–
–
–
–
0.9
0.8
LVCMOS hysteresis 25°C/3V
LVTTL hysteresis 25°C/3V
0.8
0.2
Delta V
–
V
Input leakage
No pull up/down
Pull up
-1
+1
-60
+1
uA
uA
uA
IIL
–
-20
24
-1
Pull down
Input leakage
No pull up/down
Pull up
-1
-1
32
+1
+1
150
µA
µA
µA
IIH
–
–
42
–
Pull down
IOZ
IOS
3-State Output Leakage current
+1
µA
50
BOUT3
BOUT6
BOUT12
BOUT24
100
155
310
Output Short circuit current (2)
–
–
mA
ICCSB
ICCOP
Leakage current per cell
Operating current per cell
–
–
0.6
0.2
5
nA
–
–
0.25
µA/MHz
Notes: 1. According buffer: Bout12, Bout6, Bout3
2. Supplied as a design limit but not guarantedd or tested. No more than one outout may be shorted at a time for a maximum
duration of 10 seconds.
3. Without Schmitt trigger.
11
4137O–AERO–06/05
AC Characteristics Table 7. AC Characteristics
TJ = 25°C, Process Typical (all values in ns)
VDD
Buffer
Description
Load
Transition
Tplh
5V
3V
3.18
2.35
4.67
3.33
BOUT12
Output buffer with 12 mA drive
60pf
Tphl
Table 8. AC Characteristics
TJ = 25°C, Process Typical (all values in ns)
VDD
Cell
Description
Load
Transition
Tplh
Tphl
Tplh
Tphl
Tplh
Tphl
Tplh
Tphl
Tplh
Tphl
Ts
5V
3V
0.75
0.7
1.12
0.98
1.29
1.03
0.85
0.49
0.89
0.67
1.30
1.08
1.06
0.00
BINCMOS
CMOS input buffer
15 fan
0.88
0.65
0.54
0.39
0.57
0.49
0.86
0.73
0.44
0.00
BINTTL
INV
TTL input buffer
Inverter
16 fan
12 fan
12 fan
NAND2
2 - input NAND
FDFF
D flip-flop, Clk to Q
8 fan
Th
12
MG2
4137O–AERO–06/05
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