PC8260VTPU200A1 [ATMEL]
RISC Microprocessor, 32-Bit, 200MHz, CMOS, PBGA480, 37.50 X 37.50 MM, TBGA-480;
| 型号： | PC8260VTPU200A1 |
| 厂家： | 
ATMEL |
| 描述： | RISC Microprocessor, 32-Bit, 200MHz, CMOS, PBGA480, 37.50 X 37.50 MM, TBGA-480 ATM 异步传输模式 外围集成电路 |
| 文件： | 总53页 (文件大小：565K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• PC603e™ Microprocessor (Embedded PowerPC™ Core) at 100 - 200 MHz
– 140 MIPS at 100 MHz (Dhrystone 2.1)
– 280 MIPS at 200 MHz (Dhrystone 2.1)
– High-performance, Superscalar Microprocessor
– Disable CPU Mode
– Improved Low-power Core
– 16-Kbyte Data and 16-Kbyte Instruction Cache, Four-way Set Associative
– Memory Management Unit
– No Floating Point Unit
– Common On-chip Processor (COP)
• System Integration Unit (SIU)
PowerPC-based
Communications
Processors
– Memory Controller, Including Two Dedicated SDRAM Machines
– PCI up to 66 MHz (Available in Subsequent Versions)
– Hardware Bus Monitor and Software Watchdog Timer
– IEEE 1149.1 JTAG Test Access Port
• High-performance Communications Processor Module (CPM) with Operating
Frequency up to 166 MHz
– PowerPC and CPM May Run at Different Frequencies
– Supports Serial Bit Rates up to 710 Mbps at 133 MHz
– Parallel I/O Registers
– On-board 24 KBytes of Dual-port RAM
– Two Multi-channel Controllers (MCCs) Each Supporting 128 Full-duplex, 64-Kbps,
HDLC Lines
PC8260
PowerQUICC II™
– Virtual DMA Functionality
• Two Bus Architectures: One 64-bit PowerPC and One 32-bit Local Bus (or PCI on
PC8265)
• Two UTOPIA Level-2 Master/Slave Ports, Both with Multi-PHY Support. One Can
Support 8/16 bit Data
• Three MIL Interfaces
• Eight TDM Interfaces (T1/E1), Two TDM Ports Can Be Glueless to T3/E3
• Power Consumption: 2.5W at 133 MHz
Description
The PC8260 PowerQUICC II™ is a versatile communications processor that inte-
grates on one chip, a high-performance PowerPC (PC603e) RISC microprocessor, a
highly flexible system integration unit, and many communications peripheral control-
lers that can be used in a variety of applications, particularly in communications and
networking systems.
The core is an embedded variant of the PC603e microprocessor, specifically referred
to later in this document as the EC603e, with 16 Kbytes of instruction cache and 16
Kbytes of data cache and no floating-point unit (FPU). The system interface unit (SIU)
consists of a flexible memory controller that interfaces to almost any user-defined
memory system, a 60x-to-PCI bus bridge (available in future revisions) and many
other peripherals, making this device a complete system on a chip.
The communications processor module (CPM) includes all the peripherals found in
the PC860, with the addition of three high-performance communication channels that
support new emerging protocols (for example, 155-Mbps ATM and Fast Ethernet).
Equipped with dedicated hardware, the PC8260 can handle up to 256 full-duplex,
time-division, multiplexed logical channels.
Rev. 2131A–08/01
Screening
Quality
Packaging
This product is manufactured in full compliance with:
•
•
•
•
Upscreening based upon Atmel standards.
Full military temperature range (TJ = -55°C, TJ = +125°C)
Industrial temperature range (TJ = -40°C, TJ = +110°C)
Core power supply:
2.5V 5ꢀ (L-Spec for 200 MHz)
2.50V to 2.75V (R-Spec for 250 MHz) (tbc)
I/O power supply: 3.0V to 3.6V
•
•
480-ball Tape Ball Grid Array package (TBGA 37.5 mm x 37.5 mm)
2
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
PC8260
Architecture
General Overview
The PC8260 has two external buses to accommodate bandwidth requirements from the high-
speed system core and the very fast communications channels. The device is composed of
the following three major functional blocks:
•
•
•
A 64-bit PowerPC core derived from the EC603e with MMUs and caches.
A system interface unit (SIU).
A communications processor module (CPM). Both the system core and the CPM have an
internal PLL, which allows independent optimization of the frequencies at which they run.
The system core and CPM are both connected to the 60x bus.
Figure 1. PC8260 Block Diagram
16-Kbyte
Instruction Cache
60x Bus
IMMU
EC603e
PowerPC
Core
60x-to-PCI Bus Bridge
16-Kbyte
Data Cache
(PC8265 only)
PCI/
Local
Bus
60x-to-Local Bus Bridge
DMMU
Memory Controller
Bus Interface Unit
24-Kbyte Dual-
Port RAM
Timers
Interrupt
Controller
Serial DMAs
Parallel I/O
Clock Counter
32-Bit RISC Communications
Processor (CP) and
Program ROM
4 Virtual
IDMAs
Baud Rate
Generator
System Functions
I2C
MCC MCC FCC FCC FCC SCC SCC SCC SCC SMC SMC
Time Slot Assigner
SPI
Serial Interface
2 UTOPIA
3 Mlls
Non-Multiplexed I/O
8 TDMs
3
2131A–08/01
EC603e Core
The EC603e core is derived from the PowerPC603e microprocessor without the floating-point
unit and with power management modifications.The core is a high-performance low-power
implementation of the PowerPC family of reduced instruction set computer (RISC) micropro-
cessors. The EC603e core implements the 32-bit portion of the PowerPC architecture, which
provides 32-bit effective addresses, integer data types of 8, 16 and 32 bits. The EC603e
cache provides snooping to ensure data coherency with other masters. This helps ensure
coherency between the CPM and system core.
The core includes 16 Kbytes of instruction cache and 16 Kbytes of data cache. It has a 64-bit
split-transaction external data bus which is connected directly to the external PC8260 pins.
The EC603e core has an internal common on-chip (COP) debug processor. This processor
allows access to internal scan chains for debugging purposes. It is also used as a serial con-
nection to the core for emulator support.
The EC603e core performance for the SPEC 95 benchmark for integer operations ranges
between 4.4 and 5.1 at 200 MHz. In Dhrystone 2.1 MIPS, the EC603e is 280 MIPS at 200
MHz (compared to 86 MIPS of the PC860 at 66 MHz).
The EC603e core can be disabled. In this mode, the PC8260 functions as a slave peripheral to
an external core or to another PC8260 device with its core enabled.
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PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
System Interface
Unit (SIU)
The SIU consists of the following:
•
A 60x-compatible parallel system bus configurable to 64-bit data width. The PC8260
supports 64-, 32-, 16-, and 8-bit port sizes.The PC8260 internal arbiter arbitrates between
internal components that can access the bus (system core, PCI bridge, CPM, and one
external master). This arbiter can be disabled, and an external arbiter can be used if
necessary.
•
A local (32-bit data, 32-bit internal and 18-bit external address) bus. This bus is used to
enhance the operation of the very high-speed communication controllers. Without
requiring extensive manipulation by the core, the bus can be used to store connection
tables for ATM or buffer descriptors (BDs) for the communication channels or raw data that
is transmitted between channels. The local bus is synchronous to the 60x bus and runs at
the same frequency.
•
The local bus can be configured as a 32-bit data and up to 66 MHz PCI (version 2.1) bus.
In PCI mode the bus can be programmed as a host or as an agent. The PCI bus can be
configured to run synchronously or asynchronously to the 60x bus. The PC8260 has an
internal PCI bridge with an efficient 60x-to-PCI DMA for memory block transfers.
•
•
Applications that require both the local bus and PCI bus need to connect an external PCI
bridge.
A memory controller supporting 12 memory banks that can be allocated for either the
system or the local bus. The memory controller is an enhanced version of the PC8260
memory controller. It supports three user-programmable machines. Besides supporting all
PC8260 features, the memory controller also supports SDRAM with page mode and
address data pipeline
•
•
Supports JTAG controller IEEE 1149.1 test access port (TAP).
A bus monitor that prevents 60x bus lock-ups, a real-time clock, a periodic interrupt timer,
and other system functions useful in embedded applications.
•
Glueless interface to L2 cache and 4-/16-K-entry CAM.
5
2131A–08/01
Communication
Processor Module
(CPM)
The CPM contains features that allow the PC8260 to excel in a variety of applications targeted
mainly for networking and telecommunication markets.
The CPM is a superset of the PC8260 PowerQUICC CPM, with enhancements on the CP per-
formance and additional hardware and microcode routines that support high bit rate protocols
like ATM (up to 155 Mbps full-duplex) and Fast Ethernet (100 Mbps full-duplex).
The following list summarizes the major features of the CPM:
•
The communications processor (CP) is an embedded 32-bit RISC controller residing on a
separate bus (CPM local bus) from the 60x bus (used by the system core). With this
separate bus, the CP does not affect the performance of the PowerPC core. The
CP handles the lower layer tasks and DMA control activities, leaving the PowerPC core
free to handle higher layer activities. The CP has an instruction set optimized for
communications, but can also be used for general-purpose applications, relieving the sys-
tem core of small often repeated tasks.
•
•
Two serial DMAs (SDMAs) that can do simultaneous transfers, optimized for burst
transfers to the 60x bus and to the local bus.
Three full-duplex, serial fast communications controllers (FCCs) supporting ATM (155
Mbps) protocol through UTOPIA2 interface (there are two UTOPIA interfaces on the
PC8260), IEEE 802.3 and Fast Ethernet protocols, HDLC up to E3 rates (45 Mbps) and
totally transparent operation. Each FCC can be configured to transmit fully transparent
and receive HDLC, or vice-versa.
•
Two multichannel controllers (MCCs) that can handle an aggregate of 256 x 64 Kbps
HDLC or transparent channels, multiplexed on up to eight TDM interfaces. The MCC also
supports super-channels of rates higher than 64 Kbps and subchanneling of the 64-Kbps
channels.
•
•
Four full-duplex serial communications controllers (SCCs) supporting
IEEE802.3/Ethernet, high-level synchronous data link control, HDLC, local talk, UART,
synchronous UART, BISYNC and transparent.
Two full-duplex serial management controllers (SMC) supporting GCI, UART, and
transparent operations.
•
•
Serial peripheral interface (SPI) and I2C bus controllers.
Time-slot assigner (TSA) that supports multiplexing of data from any of the four SCCs,
three FCCs, and two SMCs.
Software
Compatibility
Issues
As much as possible, the PC8260 CPM features were made similar to those of the previous
devices (PC860). The code ports easily from previous devices to the PC8260, except for new
protocols supported by the PC8260.
Although many registers are new, most registers retain the old status and event bits, so an
understanding of the programming models of the 68360, PC860, or PC850 is helpful. Note
that the PC8260 initialization code requires changes from the PC8260 initialization code.
6
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Differences
The following PC860 features are not included in the PC8260:
Between PC860
and PC8260
•
•
•
•
•
•
•
•
•
•
•
•
•
•
On-chip crystal oscillators (must use external oscillator)
4 MHz oscillator (input clock must be at the bus speed)
Low power (standby) modes
Battery-backup real-time clock (must use external battery-backup clock)
BDM (COP offers most of the same functionality)
True little endian mode (except the PCI bus)
PCMCIA interface
Infrared (IR) port
QMC protocol in SCC (256 HDLC channels are supported by the MCCs)
Multiply and accumulate (MAC) block in the CPM
Centronics port (PIP)
Asynchronous HDLC protocol (optional RAM microcode)
Pulse-width modulated outputs
SCC Ethernet controller option to sample 1 byte from the parallel port when a receive
frame is complete.
•
Parallel CAM interface for SCC (Ethernet)
Serial Protocol
Table
Table 1 summarizes available protocols for each serial port.
Table 1. PC8260 Serial Protocols
Port
Protocol
ATM (Utopia)
100BaseT
10BaseT
HDLC
FCC
SCC
MCC
SMC
x
x
x
x
x
x
x
x
x
x
x
x
HDLC_BUS
Transparent
UART
x
x
x
DPLL
Multichannel
x
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2131A–08/01
Pin Assignment
Table 2 shows the pinout of the PC8260.
Table 2. Pinout
Pin Name
BR
Ball
W5
F4
E2
E3
G1
H5
H2
H1
J5
BG
ABB/IRQ2
TS
A0
A1
A2
A3
A4
A5
J4
A6
J3
A7
J2
A8
J1
A9
K4
K3
K2
K1
L5
A10
A11
A12
A13
A14
A15
A16
A17
A18
A19
A20
A21
A22
A23
A24
A25
A26
A27
A28
A29
A30
L4
L3
L2
L1
M5
N5
N4
N3
N2
N1
P4
P3
P2
P1
R1
R3
R5
8
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Table 2. Pinout (Continued)
Pin Name
A31
Ball
R4
TTO
TT1
F1
G4
G3
G2
F2
TT2
TT3
TT4
TBST
TSIZ0
TSIZ1
TSIZ2
TSIZ3
AACK
ARTRY
DBG
DBB/IRQ3
D0
D3
C1
E4
D2
F5
F3
E1
V1
V2
B20
A18
A16
A13
E12
D9
D1
D2
D3
D4
D5
D6
A6
D7
B5
D8
A20
E17
B15
B13
A11
E9
D9
D10
D11
D12
D13
D14
D15
D16
D17
D18
D19
D20
B7
B4
D19
D17
D15
C13
B11
9
2131A–08/01
Table 2. Pinout (Continued)
Pin Name
D21
D22
D23
D24
D25
D26
D27
D28
D29
D30
D31
D32
D33
D34
D35
D36
D37
D38
D39
D40
D41
D42
D43
D44
D45
D46
D47
D48
D49
D50
D51
D52
D53
D54
D55
D56
Ball
A8
A5
C5
C19
C17
C15
D13
C11
B8
A4
E6
E18
B17
A15
A12
D11
C8
E7
A3
D18
A187
A14
B12
A10
D8
B6
C4
C18
E16
B14
C12
B10
A7
C6
D5
B18
10
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Table 2. Pinout (Continued)
Pin Name
Ball
B16
E14
D12
C10
E8
D57
D58
D59
D60
D61
D62
D6
D63
C2
DPO/RSRV/EXT_BR2
B22
A22
E21
D21
C21
B21
A21
E20
V3
IRQ1/DP1/EXT_BG2
IRQ2/DP2/TLBISYNC/EXT DBG2
IRQ3/DP3/CKSTP_OUT/EXT BR3
IRQ4/DP4/CORE_SRESET/EXT BG3
IRQ5/DP5/TBEN/EXT_DBG3
IRQ6/DP6/CSEO
IRQ7/DP7/CSE1
PSDVAL
TA
C22
V5
TEA
GBL/IRQ1
W1
U2
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
U3
L2_HIT/IRQ4
Y4
CPU_BG/BADDR31/IRQ5
U4
CPU_DBG
CPU_BR
CS0
R2
Y3
F25
C29
E27
E28
F26
F27
F28
G25
D29
E29
F29
CS1
CS2
CS3
CS4
CS5
CS6
CS7
CS8
CS9
CS10/BCTL1
11
2131A–08/01
Table 2. Pinout (Continued)
Pin Name
Ball
G28
T5
CS11/APO
BADDR27
BADDR28
U1
ALE
T2
BCTL0
A27
C25
E24
D24
C24
B26
A26
B25
A25
E23
B24
A24
B23
A23
D22
H28
H27
H26
G29
D27
C28
E26
D25
C26
B27
D28
N27
T29
R27
R26
R29
R28
PWE0/PSDQM0/PBS0
PWE1/PSDDQM1/PBS1
PWE2/PSDDQM2/PBS2
PWE3/PSDDQM3/PBS3
PWE4/PSDDQM4/PBS4
PWE5PSDDQM5/PBS5
PWE6/PSDDQM6/PBS6
PWE7/PSDDQM7/PBS7
PSDA10/PGL0
PSDWE/PGPL1
POE/OSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE0/LSDDQM0/LBS0
LWE1/LSDDQM1/LBS1
LWE2/LSDDQM2/LBS2
LWE3/LSDDQM3/LBS3
LSDA10/LGPL0
LSDWE/LGPL1
LOE/LSDRAS/LGPL2
LSDCAS/LGPL3
LGTA/LUPMWAIT/LGPL4/LPBS
LGPL5
LWR
L A14
L A15/SMI
L A16
L A17/CKSTP_OUT
L A18
L A19
12
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Table 2. Pinout (Continued)
Pin Name
L A20
Ball
W20
P28
N26
AA27
P29
AA26
N25
AA25
AB29
AB28
P25
AB27
H29
J29
L A21
L A22
L A23
L A24
L A25
L A26
L A27
L A28/CORE_SRESET
L A29
L A30
L A31
LCL D0
LCL D1
LCL D2
J28
LCL D3
J27
LCL D4
J26
LCL D5
J25
LCL D6
K25
L29
LCL D7
LCL D8
L27
LCL D9
L26
LCL D10
LCL D11
LCL D12
LCL D13
LCL D14
LCL D15
LCL D16
LCL D17
LCL D18
LCL D19
LCL D20
LCL D21
LCL D22
LCL D23
L25
M29
M28
M27
M26
N29
T25
U27
U26
U25
V29
V28
V27
V26
13
2131A–08/01
Table 2. Pinout (Continued)
Pin Name
Ball
W27
W26
W25
Y29
LCL_D24
LCL_D25
LCL_D26
LCL_D27
LCL_D28
Y28
LCL_D29
Y25
LCL_D30
AA29
AA28
L28
LCL_D31
LCL_DP0
LCL_DP1
N28
T28
LCL_DP2
LCL_DP3
W28
W28
D1
IRQ0/NMI_OUT
IRQ7INT_OUT/APE
TRST
AH3
AG5
AJ3
TCK
TMS
TDI
AE6
AF5
AB4
AG6
AH5
AF6
AA3
AJ4
TDO
TRIS
PORESET
HRESET
SRESET
QREQ
RSTCONF
MODCK1/AP1/TC0/BNKSEL0
MODCK2/AP2/TC1/BNKSEL1
MODCK3/AP3/TC2/BNKSEL2
XFC
W2
W3
W4
AB2
AH4
AC29
AC25
AE28
AG29
AG28
AG26
CLKIN
PA0/RESTART1/DREQ/FCC2_UTM_TXADDRS
PA1/REJECT1/FCC2_UTM_TXADDR1/DONE3
PA2/CLK20/FCC2_UTM_TXADDR0/DACK3
PA3/CLK19/FCC2_UTM_RXADDR0/DACK4/L1RXD1A2
PA4/REJECT2/FCC2/RXADDR1/DONE4
PA5/RESTART2/DREQ4/FCC2_UTM RXADDR2
14
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Table 2. Pinout (Continued)
Pin Name
Ball
PA6/L1RSYNCA1
AE24
AH25
AF23
AE24
AH25
AF23
AH23
PA7/SMSYN2/L1TSYNCA1/L1GNTA1
PA8/SMRSXD2/L1RXD0A1/L1RXDA1
PA6/L1RSYNCA1
PA7/SMSYN2/L1TSYNCA1/L1GNTA1
PA8/SMRXD2/L1RXD0A1/L1RXDA1
PA9/SMTXD2/L1TXD0A1
PA10/FCC1_UT8_RXD0/FCC1_UT16_RXD8/MSNUM5
PA11/FCC1_UT8_RXD1/FCC1_UT16_RXD9/MSNUM4
PA12/FCC1_UT8_RXD2/FCC1_UT16_RXD10/MSNUM3
PA13/FCC1_UT8_RXD3/FCC1_UT16_RXD11/MSNUM2
PA14/FCC1_UT8_RXD4/FCC1_UT16_RXD12/FCC1_RXD3
PA15/FCC1_UT8_RXD5/FCC1_UT16_RXD13/FCC1_RXD2
PA16/FCC1_UT8_RXD6/FCC1_UT16_RXD14/FCC1_RXD1
PA17/FCC1_UT8_RXD7/FCC1_UT16_RXD15/FCC1_RXD0/FCC1_RXD
PA18/FCC1_UT8_TXD7/FCC1_UT16_TXD15/FCC1_TXD0/FCC1_TXD
PA19/FCC1_UT8_TXD6/FCC1_UT16_TXD14/FCC1_TXD1
PA20/FCC1_UT8_TXD5/FCC1_UT16_TXD13/FCC1_TXD2
PA21/FCC1_UT8_TXD4/FCC1_UT16_TXD12/FCC1_TXD3
PA22/FCC1_UT8_TXD3/FCC1_UT16_TXD11
AE22
AH22
AJ21
AH20
AG19
AF18
AF17
AE16
AJ16
AG15
AJ13
AE13
AF12
AG11
AH9
PA23/FCC1_UT8_TXD2/FCC1_UT16_TXD10
PA24/FCC1_UT8_TXD1/FCC1_UT16_TXD9/MSNUM1
PA25/FCC1_UT8_TXD0/FCC1_UT16_TXD8/MSNUM0
PA26/FCC1_UTM_RXCLAV/FCC1_UTS_RXCLAV/FCC1_MII_RX_ER
PA27/FCC1_UT_RXSOC/FCC1_MII_RX DV
AJ8
AH7
AF7
PA28/FCC1_UTM_RXENB/FCC1_UTS_RXENB/FCC1_MII_TX_EN
PA29/FCC1_UT_TXSOC/FCC1_MII_TX_ER
AD5
AF1
PA30/FCC1_UTM_TXCLAV/FCC1_UTS_TXCLAV/FCC1_MII_CRS/FCC1_RTS
PA31/FCC1_UTM_TXENB/FCC1_UTS_TXENB/FCC1_MII_COL
PB4/FCC3_TXD3/FCC2_UT8_RXD0/L1RSYNCA2/FCC3_RTS
PB5/FCC3_TXD2/FCC2_UT8_RXD1/L1TSYNCA2/L1GNTA2
PB6/FCC3_TXD1/FCC2_UT8_RXD2/L1RXDA2/L1RXD0A2
PB7/FCC3_TXD0/FCC3_TXD/FCC2_UT8_RXD3/L1TXDA2/L1TXD0A2
PB8/FCC2_UT8_TXD3/FCC3_RXD0/FCC3 RXD/TXD3/L1RSYNCD1
PB9/FCC2_UT8_TXD2/FCC3_RXD1/L1TXD2A2/L1TSYNCD1/L1GNTD1
PB10/FCC2_UT8_TXD1/FCC3_RXD2/L1RXDD1
AD3
AB5
AD28
AD26
AD25
AE26
AH27
AG24
AH24
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2131A–08/01
Table 2. Pinout (Continued)
Pin Name
Ball
AJ24
AG22
AH21
AG20
AF19
AJ18
AJ17
AE14
AF13
AG12
AH11
PB11/FCC3_RXD3/FCC2_UT8_TXD0/L1TXDD1
PB12/FCC3_MII_CRS/L1CLKOB1/L1RSYNCC1/TXD2
PB13/FCC3_MII_COL/L1RQB1/L1TSYNCC1/L1GNTC1/L1TXD1A2
PB14/FCC3_MIL_TX_EN/RXD3/L1RXDC1
PB15/FCC3_MIL_TX_ER/RXD2/L1TXDC1
PB14/FCC3_MIL_RX_ER/L1CLKOA1/CLK18
PB17FCC3_MIL_RX_DV/L1RQA1/CLK17
PB18/FCC2_UT8_RXD4/FCC2_RXD3/L1CLKOD2/L1RXD2A2
PB19/FCC2_UT8_RXD5/FCC2_RXD2/L1RQD2/L1RXD3A2
PB20/FCC2_UT8_RXD6/FCC2 RXD1/L1RSYNCD2/L1TXD1A1
PB21/FCC2_UT8_RXD7/FCC2_RXD0/FCC2_RXD/
L1TSYNCD2/L1GNTD2/L1TXD2A1
PB22/FCC2_UT8_TXD7/FCC2_TXD0/FCC2_L1RXD1A1/L1RXDD2
PB23/FCC2_UT8_TXD6/FCC2_TXD1/L1RXD2A1/L1RXDD2
PB24/FCC2_UT8_TXD5/FCC2_TXD2/L1RXD3A1/L1RSYNCC2
PB25/FCC2_UT8_TXD4/FCC2_TXD3/L1TSYNCC2/L1GNTC2/L1TXD3A1
PB26/FCC2_MII_CRS/FCC2_UT8_TXD1/L1RXDC2
AH16
AE15
AJ9
AE9
AJ7
PB27/FCC2_MII_COL/FCC2_UT8_TXD0/L1TXDC2
AH6
AE3
AE2
PB28/FCC2_MII RX_ER/FCC2_RTS/L1TSYNCB2/L1GNTB2/TXD1
PB29/FCC2_UTM_RXCLAV/FCC2_UTS_RXCLAV/
L1RSYNCB2/FCC2_MII_TX_EN
PB30/FCC2_MII_RX_DV/FCC2_UT_TXSOC/1RXDB2
PB31/FCC2_MII_TX_ER/FCC2_UT_RXSOC/L1TXDB2
PC0/DREQ1/BRGO7/SMSYN2/L1CLKOA2
AC5
AC4
AB26
AD29
AE29
AE27
AF27
AF24
AJ26
PC1/DREQ2/BRGO6/L1RQA2
PC2/FCC3_CD/FCC2_UT8_TXD3/DONE2
PC3/FCC3_CTS/FCC2_UT8_TXD2/DACk2/CTS4
PC4/FCC2_UTM_RXENB/FCC2_UTS_RXENB/SI2_L1ST4/FCC2_CD
PC5/FCC2_UTM_TXCLAV/FCC2_UTS_TXCLAV/SI2_L1ST3/FCC2_CTS
PC6/FCC1_CD/L1CLKOC1/FCC1_UTM_RXADDR2/FCC1_UTS RXADDR2/
FCC1_UTM_RXCLAV1
PC7/FCC1_CTS/L1RQC1/
AJ25
FCC1_UTM_TXADDR2/FCC1_UTS_TXADDR2/FCC1_UTM_TSCLAV1
PC8/CD4/RENA4/FCC1_UT16_TXD0/SI2_L1ST2/CTS3
AF22
AE21
AE20
AE19
PC9/CTS4/CLSN4/FCC1_UT16_TXD1/SI2_L1ST1/L1TSYNCA2/L1GNTA2
PC10/CD3/RENA3/FCC1_UT16_TXD2/SI1_L1ST4/FCC2_UT8_RXD3
PC11/CTS3/CLSN3/L1CLKOD1/L1TXD3A2/FCC2_UT8_RXD2
16
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Table 2. Pinout (Continued)
Pin Name
Ball
PC12/CD2/RENA2/SI1_L1ST3/FCC1_UTM_RXADDR1/FCC1_UTS_RXADDR1
PC13/CTS2/SLSN2/L1RQD1/FCC1_UTM_TXADDR1/FCC1_UTS_TXADDR1
PC14/CD1/RENA1/FCC1_UTM_RXADDR0/FCC1_UTS_RXADDR0
PC15/CTS1/CLSN1/SMTXD2/FCC1_UTM_TXADDR0/FCC1_UTS_TXADDR0
PC16/CLK16/TIN3
AE18
AH18
AH17
AG16
AF15
AJ15
AH14
AG13
AH12
AJ11
AG10
AE10
AF9
PC17/CLK15/TIN4/BRGO8
PC18/CLK14/TGATE2
PC19/CLK13/BRGO7
PC20/CLK12/TGATE1
PC21/CLK11/BTGO6
PC22/CLK10/DONE1
PC23/CLK9/BRGO5/DACK1
PC24/FCC2_UT8_TXD3/CLK8/TOUT4
PC25/FCC2_UT8_TXD2/CLK7/BRGO4
PC26/CLK6/TOUT3/TMCLK
AE8
AJ6
PC27/FCC3_TXD/FCC3_TXD0/CLK5/BRGO3
PC28/CLK4/TIN1/TOUT2/CTS2/CLSN2
PC29/CLK3/TIN2/BRGO2/CTS1/CLSN1
PC30/FCC2_UT8_TXD3/CLK2/TOUT1
PC31/CLK1/BRGO1
AG2
AF3
AF2
AE1
AD1
PD4/BRGO8/L1TSYNCD1/L1GNTD1/FCC3_RTS/SMRXD2
PD5/FCC1_UT16_TXD3/DONE1
AC28
AD27
AF29
AF28
AG25
AH26
AJ27
AJ23
AG23
AJ22
AE20
AJ20
AG18
AG17
AF16
PD6/FCC1_UT16_TXD4/DACK1
PD7/SMSYN1/FCC1_UTM_TXADDR3/FCC1_UTS_TXADDR3/FCC1_TXCLAV2
PD8/SMRXD1/FCC2_UT_TXPRTY/BRGO5
PD9/SMTXD1/FCC2_UT_RXPRTY/BRGO3
PD10/L1CLKOB2/FCC2_UT8_RXD1/L1RSYNCB1/BRGO4
PD11/L1RQB2/FCC2_UT8_RXD0/L1TSYNCB1/L1GNTB1
PD12/SI1_L1ST2/L1RXDB1
PD13/SI1_L1ST1/L1RTDB1
PD14/FCC1_UT16_RXD0/L1CLKOC2/L2CSCL
PD15/FCC1_UT16_RXD1/L1RQC2/I2CSDA
PD16/FCC1_UT_TXPRTY/L1TSYNCC1/L1GNTC1/SPIMISO
PD17/FCC1_UT_RXPRTY/BRGO2/SPIMOSI
PD18/FCC1_UTM_RXADDR4/FCC1_UTS_RXADDR4/FCC1_UTM_RXCLAV3/
SPICLK
17
2131A–08/01
Table 2. Pinout (Continued)
Pin Name
Ball
PD19/FCC1_UTM_RXADDR4/FCC1_UTS_RXADDR4/FCC1_UTM
TXCLAV3/SPISEL/BRGO1
AH15
PD20/RTS4/TENA4/FCC1_UT16_RXD2/L1RSYNCA2
PD21/TXD4/FCC1_UT16_RXD3/L1RXD0A2/L1RXDA2
PD22/RXD4/FCC1_UT16_TXD5/L1TXD0A2/L1TXDA2
PD23/RTS3/TENA3/FCC1_UT16_RXD4/L1RSYNCD1
PD24/TXD3/FCC1_UT16_RXD5/L1RXDD1
AJ14
AH13
AJ12
AE12
AF10
AG9
AH8
PD25/RXD3/FCC1_UT16_TXD6/L1TXDD1
PD26/RTS2/TENA2/FCC1_UT16_RXD6/L1RSYNCC1
PD27/TXD2/FCC1_UT16_RXD7/L1RXDC1
AG7
AE4
PD28/RXD2/FCC1_UT16_TXD7/L1TXDC1
PD29/RTS1/TENA1/FCC1_UTM_RXADDR3/FCC1_UTS_RXADDR3/
FCC1 UTM RXCLAV2
AG1
PD30/FCC2_UTM_TXENB/FCC2_UTS_TXENB/TXD1
AD4
AD2
AB3
B9
PD31/RXD1
VCCSYN
VCCSYN1
GNDSYN
AB1
AA1
AG4
AE11
UF
THERMAL0 (thermal ball)
THERMAL1 (thermal ball)
SPARE1
SPARE4
SPARE5
AF25
V4
SPARE6
18
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Table 2. Pinout (Continued)
Pin Name
Ball
I/O Power
AG21,AG14,
AG8, AJ1, AJ2,
AH1, AH2,AG3,
AF4, AE5,
AC27, Y27,
T27, P27, K26,
G27, AE25,
AF26, AG27,
AH28, AH29,
AJ28, AJ29,
C7,C14,C16,C2
0,C23, E10,
A28, A29, B28,
B29, C27, D26,
E25, H3, M4,
T3, AA4, A1,
A2, B1, B2, C3,
D4, E5
Core Power
U28, U29, K28,
K29, A9, A19,
B19, M1, M2,
Y1, Y2, AC1,
AC2, AH19,
AJ19, AH10,
AJ10, AJ5
Ground
U28, U29, K28,
K29, A9, A19,
B19, M1, M2,
Y1, Y2, AC1,
AC2, AH19,
AJ19, AH10,
AJ10, AJ5
Note:
Symbol Legend:
Overline: Signals with overlines, such as TA, are active low
UTM:
UTS:
2UT8:
UT16:
MII:
Indicates that a signal is part of the UTOPIA master interface
Indicates that a signal is part of the UTOPIA slave interface
Indicates that a signal is part of the 8-bit UTOPIA interface
Indicates that a signal is part of the 16-bit UTOPIA interface
Indicates that a signal is part of the media independent interface
19
2131A–08/01
Figure 2. PowerQUICC II External Signals
VCCSYN/GNDSYN/VCCSYN1/VDDH/VDD/VSS
P AR / L_A14
100
1
1
1
1
1
1
1
1
32
5
4
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
64
1
1
1
1
1
1
1
1
1
1
1
1
1
10
1
1
2
1
1
8
1
1
1
1
1
1
1
1
1
1
1
A[0:31]
TT[0:4]
TSIZ[0:3]
TBST
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
CPU_BR
BR
BG
ABB/IRQ2
TS
AACK
ARTRY
DBG
DBB/IRQ3
D[0:63]
NC/DP0/RSRV/EXT_BR2
IRQ1/DP1/EXT_BG2
IRQ2/DP2/TLBISYNC/EXT_DBG2
IRQ3/DP3/CKSTP_OUT/EXT_BR3
IRQ4/DP4/CORE_SRESET /EXT_BG
IRQ5/DP5/TBEN/EXT_DBG3
IRQ6/DP6/CSE0
IRQ7/DP7/CSE1
PS_DVAL
SMI/FRAME/ L_A15
TRDY / L_A16
CKSTOP_OUT/IRDY/ L_A17
STOP/ L_A18
DEVSEL / L_A19
IDSEL/ L_A20
L
O
C
A
L
PERR / L_A21
SERR/ L_A22
REQ0/ L_A23
REQ1 / L_A24
GNT0 / L_A25
GNT1 / L_A26
1
1
1
1
1
1
1
1
1
6
0
x
B
U
S
CLK / L_A27
CORE_SRESET/RST/ L_A28
B
U
S
INTA/ L_A29
LOCK/ L_A30
L_A31
AD[0:31]/LCL_D[0:31]
1
32
4
C/BE[0:3]
/LCL_DP[0:3]
WE [0:3]
[0:3]/L
LBS[0:3]/LSDDQM
4
LGPL0/LSDA10
LGPL1/LSDWE
LGPL2/LSDRAS/LOE
LGPL3/LSDCAS
1
1
1
1
1
M
E
M
C
LPBS/LGPL4/LUPWAIT/LGTA
LGPL5
TA
TEA
1
1
LWR
PA[0:31]
PB[4:31]
PC[0:31]
PD[4:31]
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
CS[0:9]
CS[10]/BCTL1/DBG_DIS
CS[11]/AP[0]
BADDR[27:28]
ALE
BCTL0
PWE[0:7]/PSDDQM[0:7]/PBS[0:7]
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
TMS
TDI
TCK
TRST
TDO
32
28
32
28
1
1
1
1
1
P
I
O
PORESET
RSTCONF
HRESET
SRESET
QREQ
M
E
M
C
R
S
T
XFC
1
CLKIN
TRIS
1
1
1
1
1
2
4
C
L
BNKSEL[0]/TC[0]/AP[1]/MODCK1
BNKSEL[1]/TC[1]/AP[2]/MODCK2
BNKSEL[2]/TC[2]/AP[3]/MODCK3
TERM[0:1]
J
K
T
A
G
NC
20
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Signal Descriptions
The PowerQUICC II system bus signals consist of all the lines that interface with the external bus. Many of these lines per-
form different functions, depending on how the user assigns them. Each signal’s pin number can be found in Table 3.
Table 3. External Signals
Pin
Signal Name
Type
Description
BR
60x Bus Request
I/O
This is an output when an external arbiter is used and an input when an
internal arbiter is used. As an output, the PowerQUICC II asserts this pin
to request ownership of the 60x bus. As an input, an external master
should assert this pin to request 60x bus ownership from the internal
arbiter.
BG
60x BusGrant
I/O
I/O
This is an output when an internal arbiter is used and an input when an
internal arbiter is used. As an output, the PowerQUICC II asserts this pin
to grant 60x bus ownership to an external bus master. As an input, an
external arbiter should assert this pin to grant 60x bus ownership to the
PowerQUICC II.
ABB
60x Address Bus Busy
As an output the PowerQUICC II asserts this pin for the duration of the
address bus tenure. Following an AACK, which terminates the address
bus tenure, the PowerQUICC II negates ABB for a fraction of a bus cycle
and than stops driving this pin. As an input, the PowerQUICC II will not
assume 60x bus ownership, as long as it senses this pin is asserted by
an external 60x bus master.
IRQ2
Interrupt Request 2
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
TS
T-S 60x Bus Transfer Start
I/O
Assertion of this pin signals the beginning of a new address bus tenure.
The PowerQUICC II asserts this signal when one of its internal 60x bus
masters (core, dma, PCI bridge) begins an address tenure. When the
PowerQUICC II senses this pin being asserted by an external 60x bus
master, it will respond to the address bus tenure as required (snoop if
enabled, access internal PowerQUICC II resources and memory
controller support).
A[0:31]
60x Address Bus
I/O
When the PowerQUICC II is in the external master bus mode, these pins
function as the 60x address bus. The PowerQUICC II drives the address
of its internal 60x bus masters and will respond to addresses generated
by external 60x bus masters. When the PowerQUICC II is in the internal
master bus mode, these pins are used as address lines connected to
memory devices and controlled by the PowerQUICC II’s memory
controller.
TT[0:4]
TBST
60x Bus Transfer Type
60x Bus Transfer Burst
60x Transfer Size
I/O
I/O
I/O
I/O
I/O
The 60x bus master drives these pins during the address tenure to
specify the type of the transaction.
The 60x bus master asserts this pin to indicate that the current
transaction is a burst transaction (transfers 4 double words).
TSIZ[0:3]
AACK
The 60x bus master drives these pins with a value indicating the amount
of bytes transferred in the current transaction.
60x Address Acknowledge
60x Address Retry
A 60x bus slave asserts this signal to indicate that it has identified the
address tenure. Assertion of this signal terminates the address tenure.
ARTRY
Assertion of this signal indicates that the bus transaction should be
retried by the 60x bus master. The PowerQUICC II asserts this signal to
enforce data coherency with its internal cache and to prevent deadlock
situations.
21
2131A–08/01
Table 3. External Signals (Continued)
Pin
Signal Name
Type
Description
DBG
60x Data Bus Grant
I/O
This is an output when an internal arbiter is used and an input when an
external arbiter is used. As an output, the PowerQUICC II asserts this
pin to grant 60x data bus ownership to an external bus master. As an
input, the external arbiter should assert this pin to grant 60x data bus
ownership to the PowerQUICC II.
DBB
60x Data Bus Busy
I/O
As an output the PowerQUICC II asserts this pin for the duration of the
data bus tenure. Following a TA, which terminates the data bus tenure,
the PowerQUICC II negates DBB for a fraction of a bus cycle and then
stops driving this pin. As an input, the PowerQUICC II will not assume
60x data bus ownership, as long as it senses this pin is asserted by an
external 60x bus master.
IRQ3
Interrupt Request 3
60x Data Bus
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
D[0:63]
I/O
I/O
In write transactions, the 60x bus master drives the valid data on this
bus. In read transactions, the 60x slave drives the valid data on this bus.
DP[0]
60x Data Parity 0
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 0 pin should provide odd
parity (odd number of 1’s) on the group of signals that include data parity
0 and D[0:7].
RSRV
EXT BR2
Reservation
O
The value driven on this output pin represents the state of the coherency
bit in the reservation address register that is used by the Iwarx and
stwcx. instructions.
External Bus Request 2
Interrupt Request 1
60x Data Parity 1
I
I
An external master should assert this pin to request 60xbus ownership
from the internal arbiter.
IRQ1
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
DP[1]
EXT BG2
I/O
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 1 pin should provide odd
parity (odd number of 1’s) on the group of signals that includes data
parity 1 and D[8:15].
External Bus Grant 2
Interrupt Request 2
60x Data Parity 2
O
I
The PowerQUICC II asserts this pin to grant 60x bus ownership to an
external bus master.
IRQ2
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
DP[2]
TLBISYNC
EXT DBG2
I/O
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 2 pin should provide odd
parity (odd number of 1’s) on the group of signals that includes data
parity 2 and S[16:23].
TLB Sync:
I
This input pin can be used to synchronize 60x core instruction execution
to hardware indications. Asserting this pin will force the core to stop
instruction execution following a tlbsinc instruction execution. The core
resumes instruction execution once this pin is negated.
External Data Bus Grant 2
O
The PowerQUICC II asserts this pin to grant 60x data bus ownership to
an external bus master.
22
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Table 3. External Signals (Continued)
Pin
Signal Name
Type
Description
IRQ3
Interrupt Request 3
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
DP[3]
CKSTP OUT
EXT BR3
60x Data Parity 3
I/O
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 3 pin should provide odd
parity (odd number of 1’s) on the group of signals that includes data
parity 3 and D[24:31].
Checkstop Output
O
I
Assertion of this pin indicates that the core is in its checkstop mode.
External Bus Request 3
An external master should assert this pin to request 60x bus ownership
from the internal arbiter.
IRQ4
Interrupt Request 4
60x Data Parity 4
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
DP[4]
CORE SRESET
EXT BG3
I/O
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 4 pin should provide odd
parity (odd number of 1’s) on the group of signals that includes data
parity 4 and D[32:39].
Core system reset
I
Asserting this pin will force the core to branch to its reset vector.
External Bus Grant 3
O
The PowerQUICC II asserts this pin to grant 60x data bus ownership to
an external bus master.
IRQ5
Interrupt Request 5
60x Data Parity 5
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
DP[5]
TBEN
I/O
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 5 pin should provide odd
parity (odd number of 1’s) on the group of signals that includes data
parity 5 and D[40:47].
EXT DBG3
Time Base Enable
I
This is a count enable input to the Time Base counter in the core.
External Bus Grant3
O
The PowerQUICC II asserts this pin to grant 60x data bus ownership to
an external bus master.
IRQ6
Interrupt Request 6
60x Data Parity 6
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
DP[6]
CSE[0]
I/O
The 60x agent that drives the data bus, also drives the data parity
signals. The value driven on the data parity 6 pin should provide odd
parity (odd number of 1’s) on the group of signals that include data parity
6 and D[48:55].
Cache Set Entry 0
O
The cache set entry outputs from the core, represent the cache
replacement set element for the current core transaction reloading into,
or writing out of, the cache.
IRQ7
Interrupt Request 7
60x Data Parity 7
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
DP[7]
CSE[1]
I/O
The 60x master or slave that drives the data bus, also drives the data
parity signals. The value driven on the data parity 7pin should provide
odd parity (odd number of 1’s) on the group of signals that include data
parity 7 and D[56:63].
Cache Set Entry 1
O
The cache set entry outputs from the core, represent the cache
replacement set element for the current core transaction reloading into,
or writing out of, the cache.
23
2131A–08/01
Table 3. External Signals (Continued)
Pin
Signal Name
Type
Description
PSDVAL
60x Data Valid
I/O
Assertion of the PSDVAL pin indicates that a data beat is valid on the
data bus. The difference between the TA pin and thePSDVAL pin is that
the TA pin is asserted to indicate 60x data transfer terminations, while
thePSDVAL signal is asserted with each data beat movement. Thus,
always when TA is asserted, PSDVAL will be asserted, but, when
PSDVAL is asserted, TA is not necessarily asserted. For example, when
a double-double word (2x64 bits) transfer is initiated by the SDMA to a
memory device that has 32 bits port size, PSDVAL will be asserted 3
times without TA and, finally, both pins will be asserted to terminate the
transfer.
TA
Transfer Acknowledge
I/O
Assertion of theTA pin indicates that a 60x data beat is valid on the data
bus. For 60x single beat transfers, assertion of this pin indicates the
termination of the transfer. For 60x burst transfers, this pin will be
asserted four times to indicate the transfer of four data beats, with the
last assertion indicating the termination of the burst transfer.
TEA
Transfer Error Acknowledge
Global
I/O
I/O
Assertion of this pin indicates a bus error. 60x masters within the
PowerQUICC II monitor the state of this pin. PowerQUICC II’s internal
bus monitor may assert this pin if it has identified a 60x transfer that is
hung.
GBL
When a 60x master within the chip initiates a bus transaction it drives
this pin. When an external 60x master initiates a bus transaction, it
should drive this pin. Assertion of this pin indicates that the transfer is
global and it should be snooped by caches in the system. The
PowerQUICC II data cache monitors the state of this pin.
IRQ1
Interrupt Request 1
Cache Inhibit
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
CI
O
This pin is an output pin. It is used for L2 cache control. For each
BADDR29 PowerQUICC II 60x transaction initiated in the core, the state
of this pin indicates if this transaction should be cached or not. Assertion
of the CI pin indicates that the transaction should not be cached.
BADDR29
IRQ2
Burst Address 29
O
There are five burst address output pins. These pins are outputs of the
60x memory controller. These pins are used in external master
configuration and are connected directly to memory devices controlled
by PowerQUICC II memory controller.
Interrupt Request 2
Write Through
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
WT
O
Output used for L2 cache control. For each core initiated PowerQUICC II
60x transaction, the state of this pin indicates if the transaction should be
cached using write-through or copy-back mode. Assertion of WT
indicates that the transaction should be cached using the write-through
mode.
BADDR30
IRQ3
Burst Address 30
O
I
There are five burst address output pins. These pins are outputs of the
60x memory controller. These pins are used in external master
configuration and are connected directly to memory devices controlled
by PowerQUICC II’s memory controller.
Interrupt Request 3
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
24
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Table 3. External Signals (Continued)
Pin
Signal Name
Type
Description
L2 HIT
IRQ4
L2 Cache Hit
I
This pin is used for L2 cache control. Assertion of this pin indicates that
the 60x transaction will be handled by the L2 cache. In this case, the
memory controller will not start an access to the memory it controls.
Interrupt Request 4
CPU BusGrant
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
CPU BG
BADDR31
IRQ5
O
The value of the60x core bus grant is driven on this pin for the BADDR31
use of an external L2 cache. The driven bus grant is non qualified. that
is, in the IRQ5 case of external arbiter, the user should qualify this signal
with the bus grant input to the PowerQUICC II before connecting it to the
L2 Cache.
Burst address 31
O
There are five burst address outputs of the 60x memory controller used
in the external master configuration and are connected directly to the
memory devices controlled by PowerQUICC II’s memory controller.
Interrupt Request 5
CPU Bus Data Bus Grant
CPU Bus Request
Chip Select
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
CPU DBG
CPU BR
CS[0:9]
O
O
O
O
O
The value of the 60x core data bus grant is driven on this pin for the use
of an external L2 cache.
The value of the 60x core bus request is driven on this pin for the use of
an external L2 cache.
These are output pins that enable specific memory devices or
peripherals connected to PowerQUICC II buses.
CS[10]
Chip Select
This is an output pin that enables specific memory devices or
peripherals connected to PowerQUICC II buses.
BCTL1
DBG DIS
Buffer Control 1
Output signal whose function is to control buffers on the 60x data bus.
This pin will usually be used with BCTL0. The exact function of this pin is
defined by the value of SIUMCR[BCTLC]. See 6.5.1.8 SIU Module
Configuration Register for details.
Data Bus Grant Disable
O
This is an output when the PowerQUICC II is in external arbiter mode
and an input when the PowerQUICC II is in internal arbiter mode. When
this pin is asserted, the 60x bus arbiter should negate all of its DBG
outputs to prevent data bus contention.
CS[11]
AP[0]
Chip Select
O
Output that enables specific memory devices or peripherals connected
to PowerQUICC II buses.
Address Parity 0
I/O
The 60x master that drives the address bus, also drives the address
parity signals. The value driven on address parity 0 pin should provide
odd parity (odd number of 1’s) on the group of signals that includes
address parity 0 and A[0: 7].
BADDR[27:28]
Burst Address 27:28
O
O
There are five burst address output pins. These pins are outputs of the
60x memory controller. Used in external master configuration and
connected directly to the memory devices controlled by PowerQUICC II’s
memory controller.
ALE
Address Latch Enable
Buffer Control 0
This output pin controls the external address latch that should be used in
external master 60x bus configuration.
BCTLO
An Output whose function is to control buffers on the 60x data bus. This
pin will usually be used with BCTL1 that is MUXed on CS10. The exact
function of this pin is defined by the value of SIUMCR[BCTLC]. See
6.5.1.8 SIU Module Configuration Register for details.
25
2131A–08/01
Table 3. External Signals (Continued)
Pin
Signal Name
Type
Description
PWE[0:7]
60x Bus Write Enable
O
Outputs of the 60x bus GPCM, these pins select byte lanes for
PSDDQM[0-7] write operations.
PSDDQM[0:7]
PBS[0:7]
60x Bus SDRAM DQM
O
O
The DQM pins are outputs of the SDRAM control machine. These pins
select specific byte lanes of SRAM devices.
60x Bus UPM Byte Select
The byte select pins are outputs of the UPM in the memory controller.
They are used to select specific byte lanes during memory operations.
The timing of these pins is programmed in the UPM. The actual driven
value depends on the address and size of the transaction and the port
size of the accessed device.
PSDA10
PGPLO
60x Bus SDRAM A10
O
An output from the 60x bus SDRAM controller, this pin is part of the
address when a row address is driven and is part of the command when
a column address is driven.
60x Bus UPM General
Purpose Line 0
O
O
O
O
O
O
O
O
I
This is one of six general purpose output lines from UPM. The values
and timing of this pin are programmed in the UPM;
PSDWE
PGPL1
60x Bus SDRAM Write
Enable
An output from the 60x bus SDRAM controller. This pin should be
connected to SRAM’s WE input.
60x Bus UPM General
Purpose Line 1
This is one of six general purpose output lines from UPM. The values
and timing of this pin are programmed in the UPM.
POE
60x Bus Output Enable
The output enable pin is an output of the 60x bus GPCM. This pin
controls the output buffer of memory devices during read operations.
PSDRAS
PGPL2
60x Bus SDRAM RAS
Output from the 60x bus SDRAM controller. This pin should be
connected to SDRAM’s RAS input.
60xBus UPM General
Purpose Line 2.
This is one of six general purpose output lines from the UPM. The values
and timing of this pin are programmed in the UPM.
PSDCAS
PGPL3
60x bus SDRAM CAS
Output from the 60x bus SDRAM controller. This pin should be
connected to SDRAM’s CAS input.
60x Bus UPM General
Purpose line 3
This is one of six general purpose output lines from the UPM. The values
and timing of this pin are programmed in the UPM.
PGTA
60x GPCM TA
This input pin is used for transaction termination during GPCM
operation. This pin requires external pull up resistor for proper operation.
PUPMWAIT
PGPL4
PPBS
60x Bus UPM Wait
I
This is an input to the UPM. An external device may hold this pin low to
force the UPM to wait until the device is ready for the continuation of the
operation.
60x Bus UPM General
Purpose Line 4
O
O
O
O
This is one of six general purpose output lines from UPM. The values
and timing of this pin are programmed in the UPM.
60 x Bus Parity Byte Select
In systems in which data parity is stored in a separate chip, this output is
used as the byte select for that chip.
PSDAMUX
PGPL5
60x SDRAM Address
Multiplexer
This output pin controls the 60x SDRAM address multiplexer when the
PowerQUICC II is in external master mode.
60x Bus General Purpose
Line 5
This is one of six general purpose output lines from UPM. The values
and timing of this pin are programmed in the UPM.
26
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Table 3. External Signals (Continued)
Pin
Signal Name
Type
Description
LWE[0:3]
Local Bus Write Enable
O
The write enable pins are outputs of the Local bus GPCM. These pins
select specific byte lanes for write operations.
LSDDQM[0:3]
LBS[0:3]
Local Bus SDRAM DQM
Local Bus UPM byte select
O
O
The DQM pins are outputs of the SDRAM control machine. These pins
select specific byte lanes of SDRAM devices.
The byte select pins are outputs of the UPM in the memory controller.
They are used to select specific byte lanes during memory operations.
The timing of these pins is programmed in the UPM. The actual driven
value depends on the address and size of the transaction and the port
size of the accessed device.
LSDA10
LGPL0
Local Bus SDRAM A10
O
Output from the 60x bus SDRAM controller. This pin is part of the
address when a row address is driven and is part of the command when
a column address is driven.
Local Bus UPM General
Purpose Line 0
O
O
O
O
O
O
O
O
I
This is one of six general purpose output lines from the UPM. The values
and timing of this pin are programmed in the UPM.
LSDWE
LGPL1
Local Bus SDRAM Write
Enable
Output from the local bus SDRAM controller. This pin should be
connected to SDRAM’s WE input.
Local Bus UPM General
Purpose Line 1
This is one of six general purpose output lines from the UPM. The values
and timing of this pin are programmed in the UPM.
LOE
Local Bus Output Enable
The output enable pin is an output of the Local bus GPCM. This pin
controls the output buffer of memory devices during read operations.
LSDRAS
LGPL2
Local Bus SDRAM RAS
Output from the Local bus SDRAM controller. This pin should be
connected to the SDRAM RAS input.
Local bus UPM General
Purpose Line 2
This is one of six general purpose output lines from UPM. The values
and timing of this pin are programmed in the UPM.
LSDCAS
LGPL3
Local Bus SDRAM CAS
Output from the Local bus SDRAM controller. This pin should be
connected to SDRAM’s CAS input.
Local Bus UPM General
Purpose Line 3
This is one of six general purpose output lines from the UPM. The values
and timing of this pin are programmed in the UPM.
LGTA
Local Bus GPCM TA
This input pin is used for transaction termination during GPCM
operation. This pin requires an external pull up resistor for proper
operation.
LUPWAIT
LGPL4
LPBS
Local Bus UPM Wait
I
This is an input to the UPM. An external device may hold this pin low to
force the UPM to wait until the device is ready for the continuation of the
operation.
Local Bus UPM General
Purpose Line 4
O
O
O
O
This is one of six general purpose output lines from UPM. The values
and timing of this pin is programmed in the UPM.
Local Bus Parity Byte
Select
In systems in which the data parity is stored in a separate chip, this
output is used as the byte select for that chip.
LGPL5
LWR
Local Bus UPM General
Purpose Line 5
This is one of six general purpose output lines from the UPM. The values
and timing of this pin are programmed in the UPM.
Local Write
The local write pin is an output from the local bus memory controller. It is
used to distinguish between read and write transactions.
27
2131A–08/01
Table 3. External Signals (Continued)
Pin
Signal Name
Type
Description
L_A14
Local Bus Address 14
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI_PAR
PCI Parity
I/O
Assertion of this pin indicates that odd parity is driven across AD[31:0]
and C/BE3-C/BE0 during address and data phases. Negation of this pin
indicates that even parity is driven across the AD31-AD0 and C/BE3-
C/BE0 signals during address and data phases.
L_A15
FRAME
SMI
Local Bus Address 15
PCI Frame i
O
In the local address bus, bit 14 FRAME is most significant and bit 31 is
least significant.
I/O
This pin is driven by the PowerQUICC II when its interface is the initiator
of a PCI transfer. This pin is asserted to indicate that a PCI transfer is on
going.
System Management
Interrupt
I
System management interrupt input to the core.
L-A16
Local Bus Address 16
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI_TRDY
PCI Target Ready
I/O
This pin is driven by the PowerQUICC II when its PCI interface is the
target of a PCI transfer. Assertion of this pin indicates that the PCI target
is ready to send or accept a data beat.
L_A17
Local Bus Address 17
PCI Initiator Ready
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI_IRDY
CKSTP_OUT
I/O
This pin is driven by the PowerQUICC II when its PCI interface is the
initiator of a PC] transfer. Assertion of this pin indicates that the PCI
initiator is ready to send or accept a data beat.
Checkstop Output
O
O
Assertion of CKSTP_OUT indicates the core is in checkstop mode.
L_A18
Local Bus Address 18
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI_STOP
PCI Stop
I/O
This pin is driven by the PowerQUICC II when its PCI interface is the
target of a PCI transfer. Assertion of this pin indicates that the PCI target
is requesting to stop the PCI transfer.
L_A19
Local Bus Address 19
PCI Device Select
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI_DEVESEL
I/O
This pin is driven by the PowerQUICC II when its PCI interface is the
target of a PCI transfer. Assertion of this pin indicates that a PCI target
has recognized a new PCI transfer with an address that belongs to the
PCI target.
L_A20
Local Bus Address 20
PCI ID select
O
I
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI_IDSEL
Used to select PowerQUICC II’s PCI interface during a PCI configuration
cycle.
L_A21
Local Bus Address 21
PCI Parity Error
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI_PERR
I/O
Assertion of this pin indicates that a parity error was detected during a
PCI transfer.
28
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Table 3. External Signals (Continued)
Pin
Signal Name
Type
Description
L_A22
Local Bus Address 22
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI_SERR
PCI System Error
I/O
O
Assertion of this pin indicates that a PCI system error was detected
during a PCI transfer.
L_A23
Local Bus Address 23
PCI Arbiter Request 0
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI_REQ0
I/O
When PowerQUICC II’s internal PCI arbiter is used, this is an input pin.
In this mode assertion of this pin indicates that an external PCI agent is
requesting the PCI bus. When an external PCI arbiter is used, this is an
output pin. In this mode assertion of this pin indicates that PowerQUICC
II’s PCI interface is requesting the PCI bus.
L_A24
Local Bus Address 24
PCI Arbiter Request 1
Local Bus Address 25
PCI Arbiter Grant 0
O
I
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI_REQ1
When PowerQUICC II’s internal PCI arbiter is used, assertion of this pin
indicates that an external PCI agent is requesting the PCI bus.
L_A25
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI_GNT0
I/O
When PowerQUICC II’s internal PCI arbiter is used, this is an output pin.
In this mode, assertion of this pin indicates that an external PCI agent
that requested the PCI bus with the REQ0 pin is granted the bus. When
an external PCI arbiter is used, this is an input pin. In this mode,
assertion of this pin indicates that PowerQUICC II’s PCI interface is
granted the PCI bus.
L_A26
Local Bus Address 26
PCI Arbiter Grant 1
O
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI_GNT1
When PowerQUICC II’s internal PCI arbiter is used, assertion of this pin
indicates that the external PCI agent that requested the PCI bus with the
REQ1 pin is granted the bus.
L_A27
Local Bus Address 27
Clock Output pin
O
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
CLKOUT
In a PCI system where PC8260’s PCI interface is configured to operate
from an external PCI clock, the 60x bus clock is driven on CLKOUT. In a
PCI system where the PC8260’s PCI interface is configured to generate
the PCI clock, the PCI clock is driven on CLKOUT. The PCI clock
frequency range is 25-66MHz.
L_A28
Local Bus Address 28
PCI Reset
O
In the local address bus bit 14 is most significant and bit 31 is least
significant.
PCI_RST
CORE_SRESET
I/O
When the PC8260 is the host in the PCI system, PCI_RST is an output.
When the PC8260is not the host of the PCI system, PCI_RST is an
input.
Core System Reset
I
This an input to the core. When this input pin is asserted the core
branches to its reset vector.
29
2131A–08/01
Table 3. External Signals (Continued)
Pin
Signal Name
Type
Description
L_A29
Local Bus Address 29
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
PCI_INTA
PCI INTA
I/O
When the PowerQUICC II is the host in the PCI system, this pin is an
input for delivering PCI interrupts to the host. When the PowerQUICC II
is not the host of the PCI system, this pin is an output used by the
PowerQUICC II to signal an interrupt to the PCI host.
L_A30
Local Bus Address 30
Local Bus Address 31
O
O
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
L_A31
In the local address bus, bit 14 is most significant and bit 31 is least
significant.
DLLSYNC
DLL Synchronization
Local Bus Data
I
DLLSYNC is used to eliminate skew for the clock driven on CLKOUT.
LCL_D[0:31]
PCI_AD[0:31]
I/O
In the local data bus, bit 0 is most significant and bit 31 is least
significant.
PCI Address Data
I/O
I/O
PCI bus address data input/output pins. In the PCI address data bus, bit
31 is most significant and bit 0 is least significant.
LCL_DP[0:3]
Local Bus Data Parity
In local bus write operations the PowerQUICC II drives these pins. In
local bus read operations the accessed device drives these pins.
PCI_C/BE[0:3]
LCL_DP(0) is driven with a value that gives odd parity with LCL_D(0:7).
LCL-DP(1) is driven with a value that gives odd parity with LCL_D(8:15).
LCL_DP(2) is driven with a value that gives odd parity with
LCL_D(16:23).
LCL_DP(3) is driven with a value that gives odd parity with
LCL_D(24:31)
PCP Command/Byte
Enable
I/O
I
The PowerQUICC II drives these pins when it is the initiator of a PCI
transfer.
IRQ0
Interrupt request 0
This input is one of the eight external lines that can request (by means of
the NMI-OUT internal interrupt controller) a service routine from the
core.
NMI_OUT
Non Maskable Interrupt
Output
O
This is an output driven from PowerQUICC II’s internal interrupt
controller. Assertion of this output indicates that an unmasked interrupt
is pending in PowerQUICC II’s internal interrupt controller.
IRQ7
Interrupt Request 7
Interrupt Output
I
This input is one of the eight external lines that can request (by means of
the internal interrupt controller) a service routine from the core.
INT_OUT
APE
O
This is an output driven from PowerQUICC II’s internal interrupt
controller. Assertion of this output indicates that an unmasked interrupt
is pending in PowerQUICC II’s internal interrupt controller.
Address Parity Error
O
This output pin will be asserted when the PowerQUICC II’s detects
wrong parity driven on its address parity pins by an external master
TRST
TCK
Test Reset (JTAG)
Test Clock (JTAG)
I
I
This is the reset input to PowerQUICC II’s JTAG/COP controller.
This pin provides the clock input for PowerQUICC II’s JTAG/COP
controller.
TMS
TDI
Test Mode Select (JTAG)
Test Data In (JTAG)
I
I
This pin controls the state of PowerQUICC II’s JTAG/COP controller.
This pin is the data input to PowerQUICC II’s JTAG/COP controller.
This pin is the data output from PowerQUICC II’s JTAG/COP controller.
TDO
Test Data Out (JTAG)
O
30
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Table 3. External Signals (Continued)
Pin
Signal Name
Type
Description
TRIS
Three State
I
Asserting TRIS forces all other PowerQUICC II’s pins to high impedance
state.
PORESET
HRESET
SRESET
QREQ
Power-on Reset
Hard Reset
I
When asserted, this input line causes the PowerQUICC II to enter
power-on reset state.
I/O
I/O
O
This open drain line, when asserted, causes the PowerQUICC II to enter
hard reset state.
Soft Reset
This open drain line, when asserted, causes the PowerQUICC II to enter
soft reset state.
Quiescent Request
This pin indicates that PowerQUICC II’s internal core is about to enter its
low power mode. In the PowerQUICC II, this pin will be typically used for
debug purposes.
RSTCONF
Reset Configuration
I
This input lien is sampled by the PowerQUICC II during the assertion of
the HRESET signal. If the line is asserted, the configuration mode is
sampled in the form of the hard reset configuration word driven on the
data bus. When this line is negated, the default configuration mode is
adopted by the PowerQUICC II. Notice that the initial base address of
internal registers is determined in this sequence.
MODCK1
AP[1]
Clock Mode Input
Address Parity 1
I
Defines the operating mode of internal clock circuits.
I/O
The 60x master that drives the address bus, also drives the address
parity signals. The value driven on the address parity 1 pin should
provide odd parity (odd number of 1’s) on the group of signals that
includes address parity 1 and [A8:15].
TC[0]
BNKSEL[0]
Transfer Code 0
Bank Select 0
O
O
The transfer code output pins supply information that can be useful for
debug purposes for each of the PowerQUICC II initiated bus
transactions.
The bank select outputs are used for selecting SDRAM bank when the
PowerQUICC II is in 60x compatible bus mode.
MODCK2
AP[2]
Clock Mode Input
Address Parity 2
I
Defines the operating mode of internal clock circuits.
I/O
The 60x master that drives the address bus, also drives the address
parity signals. The value driven on the address parity 2 pin should
provide odd parity (odd number of 1’s) on the group of signals that
includes address parity 2 and [A16:23].
TC[1]
BNKSEL[1]
Transfer Code 1
Bank Select 1
O
O
The transfer code output pins supply information that can be useful for
debug purposes for each of the PowerQUICC II initiated bus
transactions.
The bank select outputs are used for selecting SDRAM bank when the
PowerQUICC II is in 60x compatible bus mode.
31
2131A–08/01
Table 3. External Signals (Continued)
Pin
Signal Name
Type
I
Description
MODCK3
AP[3]
Clock Mode Input
Address Parity 3
Defines the operating mode of internal clock circuits.
I/O
The 60x master that drives the address bus, also drives the address
parity signals. The value driven on the address parity 3 pin should
provide odd parity (odd number of 1’s) on the group of signals that
includes address parity 3and [A24:314].
TC[2]
BNKSEL[2]
Transfer Code 2
Bank Select 2
O
O
The transfer code output pins supply information that can be useful for
debug purposes for each of the PowerQUICC II initiated bus
transactions.
The bank select outputs are used for selecting SDRAM bank when the
PowerQUICC II is in 60x compatible bus mode.
XFC
External Filter Capacitance
Clock In
I
Input connection for an external capacitor filter for PLL circuity.
Primary clock input to PowerQUICC II’s PLL.
General Purpose I/O Port
CLKIN
I
PA[0:31]
PB[4:31]
PC[0:31]
PD[4:31]
Port A Bits 0:31
Port B Bits 4:31
Port C Bits 0:31
Port D Bits 4:31
I/O
I/O
I/O
I/O
General Purpose I/O Port
General Purpose I/O Port
General Purpose I/O Port
VDD
Power Supply
Power Supply
Power Supply
Special Ground
Power Supply
Power supply of the internal logic
Power supply of the I/O buffers
Power supply of the PLL circuity
Special ground of the PLL circuity
Power supply of the core’s PLL circuity
VDDH
VCCSYN
GNDSYN
VCCSYN1
32
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Applicable
Documents
1. MIL-STD-883: Test methods and procedures for electronics.
2. SQ32S0100.0: Quality levels for supplied components.
Requirements
General
The microcircuits are in accordance with the applicable documents and as specified herein.
The terminal connections are shown in Table 2 on page 8.
Terminal Connections
Absolute Maximum
Ratings
Table 4. Maximum Ratings
Symbol
VDD
Rating
Value
-0.3/2.75
-0.3/2.75
-0.3/3.6
Unit
V
Core Supply Voltage
PLL Supply Voltage
I/O Supply Voltage
Input Voltage
VCCSYN
VDDH
VIN
V
V
(GND-0.3)/3.6
-65/+150
V
TSTG
Storage Temperature Range
°C
Note:
Absolute maximum ratings are stress ratings only. Functional operation (see Table on page 34)
at the maximums is not guaranteed. Stress beyond those listed may affect device reliability or
cause permanent damage.
Warning
VIN must not exceed VDDH by more than 2.5V at any time, including during power-on reset.
VDDH must not exceed VDD/VCCSYN by more than 1.6V at any time, including during power-on
reset. VDD/VCCSYN must not exceed VDDH by more than 0.4V at any time, including during
power-on reset. It is recommended to use a bootstrap diode between the power rails, as
shown in Figure 3.
Figure 3. Bootstrap Diodes for Power-up Sequencing
3.3V (VDDH)
I/O Power
MUR420
MUR420
Core/Pll
Power
2.5V(VDD/VCCSYN)
Select the bootstrap diodes so that a nominal VDD/VCCSYN is sourced from the VDDH power sup-
ply until the VDD/VCCSYN power supply becomes active. In Figure 3, two MUR420 Schottky
barrier diodes are connected in a series; each has a forward voltage (VF) of 0.6V at high cur-
rents, and so provides a 1.2V drop, maintaining 2.1V on the 2.5V power line. Once the
core/PLL power supply stabilizes at 2.5V, the bootstrap diode(s) will be reverse biased with
negligible leakage current.
The forward voltage should be effective at the current levels needed by the processor, approx-
imately 2-3 amps. That is, do not use diodes with only a nominal VF which drops too low at
high current.
33
2131A–08/01
Recommended
Operating Conditions
Table 5. Recommended Operational Voltage Conditions
Symbol
VDD
Rating
2.5V Device
2.4 / 2.7
Unit
V
Core Supply Voltage
PLL Supply Voltage
I/O Supply Voltage
Input Voltage
VCCSYN
VDDH
VIN
2.4 / 2.7
V
3.15 / 3.465
GND -0.3 / 3.6
-55 / + 125
V
V
TJ
Junction Temperature
°C
Note:
The recommended and tested operating conditions. Proper device operation outside of these
conditions is not guaranteed.
This device contains circuitry to protect against damage due to high static voltage or electrical
fields. However, it is advised that normal precautions be taken to avoid application of any volt-
ages higher than maximum-rated voltages to this high-impedance circuit. Operational
reliability is enhanced if unused inputs are tied to an appropriate logic voltage level (either
GND or VCC).
Table 6. Thermal Characteristics
Symbol
ΘJA
Characteristics
Value
13.5(1)
11.0(1)
10.8(3)
8.5(3)
Unit
°C/W
°C/W
°C/W
°C/W
Air Flow
NC(2)
1 m/s
NC
Thermal Resistance for TBGA
ΘJA
ΘJA
ΘJA
1 m/s
Notes: 1. Assumes a single layer board with no thermal bias
2. Natural convection
3. Assumes a four layer board
34
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Power Considerations
The average chip-junction temperature, TJ, in °C can be obtained from the following:
TJ = TA + (PD • ΘJA
where
TA = ambient temperature °C
)
(1)
QJA = package thermal resistance, junction to ambient, °C/W
PD = PINT + PI/O
PINT =IDD x VDD Watts–chip internal power
PI/O = power dissipation on input and output pins–user determined
PI ⁄ O < 0.3 • PINT
Can be neglected for most applications. If PI/O is neglected, an approximate relationship
between PD and TJ is the following:
PD = K / (TJ + 273 °C)
(2)
Solving equations (1) and (2) for K gives:
2
K = PD • (TA + 273°C) + Θ • PD
(3)
Where K is a constant pertaining to the particular part. K can be determined from equation (3)
by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ
can be obtained by solving equations (1) and (2) iteratively for any value of TA.
Layout Practices
Each VCC pin on the PC8260 should be provided with a low-impedance path to the board’s
power supply. Each ground pin should likewise be provided with a low-impedance path to
ground. The power supply pins drive distinct groups of logic on chip. The VCC power supply
should be bypassed to ground using at least four 0.1 µF by-pass capacitors located as close
as possible to the four sides of the package. The capacitor leads and associated printed circuit
traces connecting to chip VCC and ground should be kept to less than half an inch per capaci-
tor lead. A four-layer board is recommended, employing two inner layers as VCC and GND
planes.
All output pins on the PC8260 have fast rise and fall times. Printed circuit (PC) trace intercon-
nection length should be minimized in order to minimize undershoot and reflections caused by
these fast output switching times. This recommendation particularly applies to the address and
data busses. Maximum PC trace lengths of six inches are recommended. Capacitance calcu-
lations should consider all device loads as well as parasitic capacitances due to the PC traces.
Attention to proper PCB layout and bypassing becomes especially critical in systems with
higher capacitive loads because these loads create higher transient currents in the VCC and
GND circuits. Pull up all unused inputs or signals that will be inputs during reset. Special care
should be taken to minimize the noise levels on the PLL supply pins.
35
2131A–08/01
Electrical
Characteristics
DC Electrical
Specification
This section describes the DC electrical characteristics for the PC8260. The measurements in
Table 7 assume the following system conditions:
TC = -55°C to +125°C
VDD = 2.0 5ꢀ VDC
VDDH = 3.3 5ꢀ VDC
GND = 0 VDC
The leakage current is measured for nominal VDDH and VDD, or both. VDDH and VDD must vary
in the same direction (for example, both VDDH and VDD vary by either +5ꢀ or -5ꢀ).
Table 7. DC Electrical Characteristics
Symbol
VIH
Characteristic
Min
2.0
Max
3.465
0.8
Unit
V
Input High Voltage, All Inputs Except CLKIN
Input Low Voltage
VIL
GND
2.4
V
VIHC
VILC
IIN
CLKIN Input High Voltage
3.465
0.4
V
CLKIN Input Low Voltage
GND
V
Input Leakage Current, VIN= VDDH
Hi-Z (off state) Leakage Current, VIN = VDDH
Signal Low Input Current, VIL= 0.8V
Signal High Input Current, VIH = 2.0V
10
µA
µA
µA
µA
V
IOZ
10
IL
TBD
TBD
2.4
TBD
TBD
IH
VOH
Output High Voltage, IOH = -2 mA
Except XFC, and Open Drain Pins
36
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Table 7. DC Electrical Characteristics (Continued)
Symbol
Characteristic
Min
Max
Unit
VOL
IOL = 7.0 mA
0.4
V
BR
BG
ABB/IRQ2
TS
A[0:31]
TT[0:4]
TBST
TSIZE[0:3]
AACK
ARTRY
DBG
DBB/IRQ3
D[0:63]
DP(0)/RSRV
DP(1)/IRQ1
DP(2)/TLBISYNC/IRQ2
DP(3)/IRQ3
DP(4)/IRQ4
DP(5)/TBEN/IRQ5
DP(6)/CSE(0)/IRQ6
DP(7)/CSE(1)/IRQ7
PSDVAL
TA
TEA
GBL/IRQ1
CI/BADDR29/IRQ2
WT/BADDR30/IRQ3
L2_HIT/IRQ4
CPU_BG/BADDR31/IRQ5
CPU_DBG
CPU_BR
IRQ0/NMI_OUT
IRQ7/INT_OUT/APE
PORESET
SRESET
RSTCONF
QREQ
37
2131A–08/01
Table 7. DC Electrical Characteristics (Continued)
Symbol
Characteristic
Min
Max
Unit
VOL
IOL = 5.3 mA
0.4
V
CS[0:9]
CS(10)/BCTL1
CS(11)/AP(0)
BADDR[27–28]
ALE
BCTL0
PWE(0:7)/PSDDQM(0:7)/PBS(0:7)
PSDA10/PGPL0
PSDWE/PGPL1
POE/PSDRAS/PGPL2
PSDCAS/PGPL3
PGTA/PUPMWAIT/PGPL4/PPBS
PSDAMUX/PGPL5
LWE[0–3]LSDDQM(0:3)/LBS([0–3]
LSDA10/LGPL0
LSDWE/LGPL1
LOE/LSDRAS/LGPL2
LSDCAS/LGPL3
LGTA/LUPMWAIT/LGPL4/LPBS
LGPL5
LWR
MODCK1/AP(1)/TC(0)/BNKSEL(0)
MODCK2/AP(2)/TC(1)/BNKSEL(1)
MODCK3/AP(3)/TC(2)/BNKSEL(2)
I
OL = 3.2 mA
L_A14
L_A15/SMI
L_A16
L_A17/CKSTP_OUT
L_A18
L_A19
L_A20
L_A21
L_A22
L_A23
L_A24
L_A25
L_A26
L_A27
L_A28/CORE_SRESET
38
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Table 7. DC Electrical Characteristics (Continued)
Symbol
Characteristic
Min
Max
Unit
VOL
L_A29
0.4
V
L_A30
L_A31
LCL_D(0:31)
LCL_DP(0:3)
PA[0:31]
PB[4:31]
PC[0:31]
PD[4:31]
TDO
39
2131A–08/01
AC Electrical
Specifications
Included in this section are illustrations and tables of clock diagrams, signals, and CPM out-
puts and inputs. Note that AC timings are based on a 50 pF load. Typical output buffer
impedances are shown in Table 8.
Table 8. Output Buffer Impedances
Output Buffers
60x bus
Typical Impedance (Ω)
40
40
40
46
25
Local bus
Memory Controller
Parallel I/O
PCI
Note:
These are typical values at 65°C. The impedance may vary by
temperature.
25ꢀ with process and
Although the specifications generally refer to the rising edge of the clock, the following AC tim-
ing diagrams also apply when the falling edge is the active edge.
Figure 4. FCC External Clock Diagram
Serial CLKin
sp17b
sp16b
FCC Input Signals
sp36b/sp37b
FCC Output Signals
Figure 5. FCC Internal Clock Diagram
sp17a
BRG_OUT
sp16a
FCC Input Signals
sp36a/sp37a
FCC Output Signals
40
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Figure 6. SCC/SMCSPI/I2C External Clock
Serial CLKin
sp19b
sp18
SCC/SMCSPI/I2C Input Signals
SCC/SMCSPI/I2C Output Signals
sp38b/sp39b
Figure 7. SCC/SMC/SPI/I2C Internal Clock Diagram
BRG_OUT
sp18a
sp19a
SCC/SMC/SPI/I2C Input Signals
SCC/SMC/SPI/I2C Output Signals
sp38a/sp39a
Figure 8. PIO, Timer and DMA Signal Diagram
CLKin
sp23
sp22
PIO/TIMER/DMA Input Signals
sp42/sp43
PIO/TIMER/DMA Output Signals
PIO Output Signals
sp42
41
2131A–08/01
Figure 9. TDM Signal Diagram
Serial CLKin
sp21
sp20
TDM Input Signals
TDM Output Signals
sp40/sp41
Table 9. AC Characteristics for CPM Outputs
Spec_num
sp36a/sp37a
sp36b/sp37b
sp40/sp41
Characteristics
Max Delay (ns)
Min Delay (ns)
FCC Outputs – Internal clock (NMSI)
FCC Outputs – External clock (NMSI)
TDM Outputs
6
0
2
5
0
18
35
20
sp38a/sp39a
SCC/SMC/SPI/I2C Outputs –
Internal Clock (NMSI)
sp38b/sp39b
sp42/sp43
EX_SCC/SMC/SPI/I2C Outputs –
External Clock (NMSI)
30
14
0
1
PIO/TIMER/DMA Outputs
Note:
Output specifications are measured from the 1.4V level of the rising edge of CLKIN to the TTL
level (0.8 or 2.0V) of the signal. Timing is measured at the pin.
Table 10. AC Characteristics for CPM Inputs
Spec_num
sp16a/sp17a
sp16b/sp17b
sp20/sp21
Characteristics
Setup (ns)
Hold (ns)
FCC Inputs – Internal clock (NMSI)
FCC Inputs – External clock (NMSI)
TDM Inputs
10
5
0
3
20
20
20
0
sp18a/sp19a
ISCC/SMC/SPI/I2C Inputs –
Internal Clock (NMSI)
sp18b/sp19b
sp22/sp23
SCC/SMC/SPI/I2C Inputs –
External Clock (NMSI)
5
5
3
PIO/TIMER/DMA Outputs
10
Note:
Input specifications are measured from the TTL level (0.8 or 2.0V) of the signal to the 1.4 level of
the rising edge of CLKIN. Timing is measured at the pin.
42
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Figure 10. Interaction of Bus Signals
CLKin
sp11
sp12
sp15
sp10
sp10
sp10
AACK/ARTRY/TA/TEA/DBG/BG/BR Input Signals
Data Bus Name Input Signal
All Other Input Signals
PSDVAL/TEA/TA Output Signals
sp31/sp30
sp32/sp30
ADD/ADD_atr/BADDR/CI/GBL/WT Output Signals
sp33a/sp30
DATA Bus Output Signals
sp35/sp30
All Other Output Signals
Figure 11. ECC Mode Diagram
sp10
sp13
sp10
DATA Bus, ECC, and PARITY Mode Input Signals
sp10
sp14
DP Mode Input Signal
DP Mode Output Signal
sp33b/sp30
43
2131A–08/01
Figure 12. MEMC Mode Diagram
CLKin
V_CLK
sp34/sp30
Memory Controller Signals
Table 11. Tick Spacing for Memory Controller Signals
Tick Spacing (T1 Occurs at the Rising Edge of CLKin)
PLL Clock Radio
1:2, 1:3, 1:4, 1:5, 1:6
1:2.5
T2
T3
T4
1/4 CLKin
3/10 CLKin
4/14 CLKin
1/2 CLKin
1/2 CLKin
1/2 CLKin
3/4 CLKin
8/10 CLKin
11/14 CLKin
1:3.5
Note:
Generally, all PC8260 bus and system output signals are driven from the rising edge of the input
clock (CLKin). Memory controller signals, however, trigger on four points within a CLKin cycle.
Each cycle is divided by four internal ticks: T1, T2, T3, and T4. T1 always occurs at the rising
edge of CLKin (and T3 at the falling edge), but the spacing of T2 and T4 depends on the PLL
clock ratio selected, as shown in Table 11.
Figure 13. Internal Tick Spacing for Memory Controller Signals
CLKin
for 1:2, 1:3, 1:4, 1:5, 1:6
T1
T2
T3
T4
CLKin
CLKin
for 1:2.5
for 1:3.5
T1
T1
T2
T3
T3
T4
T2
T4
Note:
The UPM machine and GPCM machine outputs change on the internal tick determined by the
memory controller programming. The AC specifications are relative to the internal tick. Note that
SDRAM machine outputs change only on the CLKin’s rising edge.
44
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Table 12. AC Characteristics for SIU Inputs
Spec_num
sp11/sp10
sp12/sp10
sp13sp10
sp14/sp10
sp15/sp10
Characteristics
Setup (ns)
Hold (ns)
AACK/ARTRY/TA/TEA/DBG/BG/BR
Data Bus in Normal mode
Data Bus in ECC and PARITY Modes
DP pins
6
5
8
8
5
1
1
1
1
1
All Other Pins
Notes: 1. Input specifications are measured from TTL level (0.8 or 2.0V) of the signal to the 1.4 level of
the rising edge of CLKIN.
2. Timings are measured at the pins.
Table 13. AC Characteristics for SIU Outputs
Spec_num
sp31/sp30
sp32/sp30
sp33a/sp30
sp33b/sp30
sp34/sp10
sp35/sp10
Characteristics
PSDVAL/TEA/TA
ADD/ADD_atr./BADDR/CIGBL/WT
Data Bus
Max Delay (ns)
Min Delay (ns)
10
8
1
1
1
1
1
1
8
DP
12
6
Memc Signals/ALE
All Other Signals
7
Notes: 1. Output specifications are measured from the 1.4V level of the rising edge of CLKIN to the
TTL level (0.8 or 2.0V) of the signal.
2. Timings are measured at the pin.
Activating data pipelining (setting BRx[DR] in the memory controller) improves the AC timing.
When data pipelining is activated, sp12 can be used for data bus setup even when ECC or
PARITY are used. Also, sp33a can be used as the AC specification for DP signals.
45
2131A–08/01
Clock Configuration Modes
To configure the main PLL multiplication factor and the core, CPM, and 60x bus frequencies, the MODCK[1:3] pins are
sampled while HRESET is asserted. Table 14 shows the eight basic configuration modes. Another 49 modes are available
by using the configuration pin (RSTCONF) and driving four pins on the data bus.
Table 14. Clock Default Modes
Input Clock
Frequency
(MH)z
CPM
Frequency
(MHz)
Core
Frequency
(MHz)
CPM Multiplication
Factor
Core Multiplication
Factor
MODCK[1–3]
000
001
010
011
100
101
110
111
33
33
33
33
66
66
66
66
3
3
100
100
133
133
133
133
166
166
4
5
133
166
133
166
166
200
166
200
4
4
4
5
2
2.5
3
2
2.5
2.5
2.5
3
Table 15. Clock Configuration Modes
Input Clock
Frequency
(MHz)
CPM
Frequency
(MHz)
Core
Frequency
(MHz)
MODCK_H–
MODCK[1–3]
CPM Multiplication
Factor
Core Multiplication Factor
0001_000
0001_001
0001_010
0001_011
0001_100
33
33
33
33
33
2
2
2
2
2
66
66
66
66
66
4
5
6
7
8
133
166
200
233
266
0001_101
0001_110
0001_111
0010_000
0010_001
33
33
33
33
33
3
3
3
3
3
100
100
100
100
100
4
5
6
7
8
133
166
200
233
266
0010_010
0010_011
0010_100
0010_101
0010_110
33
33
33
33
33
4
4
4
4
4
133
133
133
133
133
4
5
6
7
8
133
166
200
233
266
46
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Table 15. Clock Configuration Modes (Continued)
Input Clock
Frequency
(MHz)
CPM
Frequency
(MHz)
Core
Frequency
MODCK_H–
MODCK[1–3]
CPM Multiplication
Factor
Core Multiplication Factor
(MHz)
0010_111
0011_000
0011_001
0011_010
0011_011
33
33
33
33
33
5
5
5
5
5
166
166
166
166
166
4
5
6
7
8
133
166
200
233
266
0011_100
0011_101
0011_110
0011_111
0100_000
33
33
33
33
33
6
6
6
6
6
200
200
200
200
200
4
5
6
7
8
133
166
200
233
266 MHz
0100_001
0100_010
0100_011
0100_100
0100_101
0100_110
Reserved
0100_111
0101_000
0101_001
0101_010
0101_011
0101_100
Reserved
0101_101
0101_110
0101_111
0110_000
0110_001
0110_010
66
66
66
66
66
66
2
2
2
2
2
2
133
133
133
133
133
133
2
2.5
3
133
166
200
233
266
300
3.5
4
4.5
0110_011
0110_100
66
66
2.5
2.5
166
166
2
133
166
2.5
47
2131A–08/01
Table 15. Clock Configuration Modes (Continued)
Input Clock
Frequency
(MHz)
CPM
Frequency
(MHz)
Core
Frequency
(MHz)
MODCK_H–
MODCK[1–3]
CPM Multiplication
Factor
Core Multiplication Factor
0110_101
0110_110
0110_111
0111_000
66
66
66
66
2.5
2.5
2.5
2.5
166
166
166
166
3
200
233
266
300
3.5
4
4.5
0111_001
0111_010
0110_101
0110_110
0110_111
0111_000
66
66
66
66
66
66
3
200
200
166
166
166
166
2
2.5
3
133
166
200
233
266
300
3
2.5
2.5
2.5
2.5
3.5
4
4.5
0111_001
0111_010
0111_011
0111_100
0111_101
0111_110
66
66
66
66
66
66
3
3
3
3
3
3
200
200
200
200
200
200
2
2.5
3
133
166
200
233
266
300
3.5
4
4.5
0111_111
1000_000
1000_001
1000_010
1000_011
1000_100
66
66
66
66
66
66
3.5
3.5
3.5
3.5
3.5
3.5
233
233
233
233
233
233
2
2.5
3
133
166
200
233
266
300
3.5
4
4.5
Notes: 1. This table describes all possible clock configurations when using the hard reset configuration sequence. Note that clock con-
figuration changes only after POR is asserted.
2. Because of speed dependencies, not all of the possible configurations in this table may be applicable.
3. The 66 MHz configurations are required for input clock frequencies higher than 50 MHz. 33 MHz configurations are required
for input clock frequencies below 50 MHz.
4. The user should choose the input clock frequency, and the multiplication factor of the CPM so that the frequency of the CPM
will be between 50 MHz and 166 MHz for a 2V part, and between 66 MHz and 233 MHz for a 2.5V part.
48
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Status
Table 16. Datasheet Status
Datasheet Status
Validity
Objective Specification
Target Specification
This datasheet contains target and goal specification for
discussion with customer and application validation.
Valid before design phase
This datasheet contains target or goal specifications for
product development.
Valid during the design phase
Preliminary Specification ∝ Site
This datasheet contains preliminary data. Additional data
may be published later. This could include simulation
results.
Valid before the characterization
phase
Preliminary Specification β Site
This datasheet also contains characterization results.
Valid before the industrialization
phase.
Product Specification
This datasheet contains final product specifications.
Valid for production purposes
Limiting Values
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134).
Stress above one or more of the limiting values may cause permanent damage to the device.
These are stress ratings only and operation of the device at these or at any other conditions
above those given in the Characteristics sections of the specification is not implied. Exposure
to limiting values for extended periods may affect device reliability.
Application
Information
Where application information is given, it is advisory and does not form part of the
specification.
Life Support
Applications
These products are not designed for use in life support appliances, devices, or systems where
malfunction of these products can reasonably be expected to result in personal injury. ATMEL-
Grenoble customers using or selling these products for use in such applications do so at their
own risk and agree to fully indemnify Atmel-Grenoble for any damages resulting from such
improper use or sale.
49
2131A–08/01
Package Dimensions TBGA480
F
B
CORNER
E
± ±T±±
0.150
MAX
37.5 BSC
37.5 BSC
T
MIN
A1
A
INDEX
B
C
D
G
H
K
L
1.45 1.65
0.65 0.85
1.27 BSC
A
0.85 0.95
35.56 BSC
0.50 0.70
4X
0.2
Top View
28 26 24 22 20 18 16 14 12 10 8
29 27 25 23 21 19 17 15 13 11 9
6
4
2
7
5
3
1
A
C
E
G
J
B
D
F
H
K
M
P
T
L
N
R
U
W
K
V
Y
AA
AB
AC
AD
AE
AF
AG
AH
AJ
Bottom View
C
480X ϕ D
G
H
K
L
All measurements are in mm.
Notes:
1. Dimensions and tolerancing per asme Y14.5M-1994.
2. Dimensions in millimeters.
3. Dimension b is measured at the maximum solder ball diameter. Parallel to primary datum A.
4. Primary datum A and the seating plane are defined by the spherical crowns of the solder balls.
50
PC8260 PowerQUICC II
2131A–08/01
PC8260 PowerQUICC II
Ordering Information
Revision A1
PC (X)
8260
M
TP
200 (A1 )
U
Revision Level
Prefix(1)
Prototype
Type
Temperature Range: Tj
M:
V:
-55, +125 ˚C
-40, +110 ˚C
Max. Internal Processor Speed(2)
200/200 MHz
150/150 MHz
Package
TP: TBGA
Screening Level(2)
U: Upscreening
(1) Atmel-Grenoble
(2)
For availability of the different versions, contact your sales office.
51
2131A–08/01
Revision B1 and Above
B1
PC (X)
8260
M
TP
IFB
U
Revision Level
Prefix(1)
Prototype
Type
Core Voltage
= 2.5 V + 0.2, -0.1 Volt
V = 1.8 V 0.1 Volt
Temperature Range: Tj
M:
V:
-55, +125 °C
-40, +110 °C
CPU/CPM/Bus Speed (MHz)
A = 50, B = 66, C= 75
D = 83, E = 100, F = 133
G = 150, H = 166, I = 200
J = 233, K = 266, L = 300
M = 333
Package:
TP: TBGA
Screening Level(2)
U: Upscreening
(1) Atmel-Grenoble
(2)
For availability of the different versions, contact your sales office.
52
PC8260 PowerQUICC II
2131A–08/01
Atmel Headquarters
Atmel Product Operations
Corporate Headquarters
2325 Orchard Parkway
San Jose, CA 95131
TEL (408) 441-0311
FAX (408) 487-2600
Atmel Colorado Springs
1150 E. Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
TEL (719) 576-3300
FAX (719) 540-1759
Europe
Atmel Grenoble
Atmel SarL
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2131A–08/01/0M
相关型号：
PC8265AMTPUMHBC
RISC Microprocessor, 32-Bit, 200MHz, CMOS, PBGA480, 37.50 X 37.50 MM, 1.27 MM PITCH, TBGA-480
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