SAM-D21_14 [ATMEL]
SMART ARM-Based Microcontroller;
| 型号： | SAM-D21_14 |
| 厂家： | 
ATMEL |
| 描述： | SMART ARM-Based Microcontroller 微控制器 |
| 文件： | 总23页 (文件大小：631K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Atmel SAM D21E / SAM D21G / SAM D21J
SMART ARM-Based Microcontroller
DATASHEET SUMMARY
Description
The Atmel® | SMART™ SAM D21 is a series of low-power microcontrollers using the 32-bit
ARM® Cortex®-M0+ processor, and ranging from 32- to 64-pins with up to 256KB Flash and
32KB of SRAM. The SAM D21 devices operate at a maximum frequency of 48MHz and reach
2.14 Coremark/MHz. They are designed for simple and intuitive migration with identical
peripheral modules, hex compatible code, identical linear address map and pin compatible
migration paths between all devices in the product series. All devices include intelligent and
flexible peripherals, Atmel Event System for inter-peripheral signaling, and support for capacitive
touch button, slider and wheel user interfaces.
The Atmel SAM D21 devices provide the following features: In-system programmable Flash,
twelve-channel direct memory access (DMA) controller, 12 channel Event System,
programmable interrupt controller, up to 52 programmable I/O pins, 32-bit real-time clock and
calendar, up to five 16-bit Timer/Counters (TC) and three 24-bit Timer/Counters for Control
(TCC), where each TC can be configured to perform frequency and waveform generation,
accurate program execution timing or input capture with time and frequency measurement of
digital signals. The TCs can operate in 8- or 16-bit mode, selected TCs can be cascaded to form
a 32-bit TC, and three timer/counters have extended functions optimized for motor, lighting and
other control applications. The series provide one full-speed USB 2.0 embedded host and device
interface; up to six Serial Communication Modules (SERCOM) that each can be configured to act
as an USART, UART, SPI, I2C up to 3.4MHz, SMBus, PMBus, and LIN slave; two-channel I2S
interface; up to twenty-channel 350ksps 12-bit ADC with programmable gain and optional
oversampling and decimation supporting up to 16-bit resolution, one 10-bit 350ksps DAC, two
analog comparators with window mode, Peripheral Touch Controller supporting up to 256
buttons, sliders, wheels and proximity sensing; programmable Watchdog Timer, brown-out
detector and power-on reset and two-pin Serial Wire Debug (SWD) program and debug interface.
All devices have accurate and low-power external and internal oscillators. All oscillators can be
used as a source for the system clock. Different clock domains can be independently configured
to run at different frequencies, enabling power saving by running each peripheral at its optimal
clock frequency, and thus maintaining a high CPU frequency while reducing power consumption.
The SAM D21 devices have two software-selectable sleep modes, idle and standby. In idle mode
the CPU is stopped while all other functions can be kept running. In standby all clocks and
functions are stopped expect those selected to continue running. The device supports
SleepWalking. This feature allows the peripheral to wake up from sleep based on predefined
conditions, and thus allows the CPU to wake up only when needed, e.g. when a threshold is
crossed or a result is ready. The Event System supports synchronous and asynchronous events,
allowing peripherals to receive, react to and send events even in standby mode.
The Flash program memory can be reprogrammed in-system through the SWD interface. The
same interface can be used for non-intrusive on-chip debug of application code. A boot loader
running in the device can use any communication interface to download and upgrade the
application program in the Flash memory.
The Atmel SAM D21 devices are supported with a full suite of program and system development
tools, including C compilers, macro assemblers, program debugger/simulators, programmers and
evaluation kits.
Atmel-42181DS–SAM-D21_Summary–09/2014
SMART
Features
z
Processor
ARM Cortex-M0+ CPU running at up to 48MHz
z
z
z
Single-cycle hardware multiplier
Micro Trace Buffer (MTB)
z
z
Memories
z
z
32/64/128/256KB in-system self-programmable Flash
4/8/16/32KB SRAM Memory
System
z
Power-on reset (POR) and brown-out detection (BOD)
z
Internal and external clock options with 48MHz Digital Frequency Locked Loop (DFLL48M) and 48MHz to 96MHz Fractional
Digital Phase Locked Loop (FDPLL96M)
External Interrupt Controller (EIC)
16 external interrupts
One non-maskable interrupt
Two-pin Serial Wire Debug (SWD) programming, test and debugging interface
z
z
z
z
z
z
Low Power
z
z
Idle and standby sleep modes
SleepWalking peripherals
Peripherals
z
z
z
12-channel Direct Memory Access Controller (DMAC)
12-channel Event System
Up to five 16-bit Timer/Counters (TC), configurable as either:
z
z
z
One 16-bit TC with compare/capture channels
One 8-bit TC with compare/capture channels
One 32-bit TC with compare/capture channels, by using two TCs
z
Three 24-bit Timer/Counters for Control (TCC), with extended functions:
z
z
z
z
Up to four compare channels with optional complementary output
Generation of synchronized pulse width modulation (PWM) pattern across port pins
Deterministic fault protection, fast decay and configurable dead-time between complementary output
Dithering that increase resolution with up to 5 bit and reduce quantization error
z
z
z
z
32-bit Real Time Counter (RTC) with clock/calendar function
Watchdog Timer (WDT)
CRC-32 generator
One full-speed (12Mbps) Universal Serial Bus (USB) 2.0 interface
z
z
Embedded host and device function
Eight endpoints
z
Up to six Serial Communication Interfaces (SERCOM), each configurable to operate as either:
z
z
z
z
USART with full-duplex and single-wire half-duplex configuration
I2C up to 3.4MHz
SPI
LIN slave
z
z
One two-channel Inter-IC Sound (I2S) interface
One 12-bit, 350ksps Analog-to-Digital Converter (ADC) with up to 20 channels
z
z
z
z
Differential and single-ended input
1/2x to 16x programmable gain stage
Automatic offset and gain error compensation
Oversampling and decimation in hardware to support 13-, 14-, 15- or 16-bit resolution
z
z
z
10-bit, 350ksps Digital-to-Analog Converter (DAC)
Two Analog Comparators (AC) with window compare function
Peripheral Touch Controller (PTC)
z
256-Channel capacitive touch and proximity sensing
z
I/O
z
Up to 52 programmable I/O pins
z
z
Drop in compatible with SAM D20
Packages
z
z
z
64-pin TQFP, QFN
48-pin TQFP, QFN
32-pin TQFP, QFN
z
Operating Voltage
1.62V – 3.63V
z
Atmel | SMART SAM D21 [DATASHEET SUMMARY]
2
Atmel-42181DS–SAM-D21_Summary–09/2014
1.
Configuration Summary
SAM D21J
SAM D21G
SAM D21E
Pins
64
48
32
General Purpose I/O-pins (GPIOs)
52
256/128/64/32KB
32/16/8/4KB
5
38
256/128/64/32KB
32/16/8/4KB
3
26
256/128/64/32KB
32/16/8/4KB
3
Flash
SRAM
Timer Counter (TC) instances
Waveform output channels per TC
instance
2
3
2
3
2
3
Timer Counter for Control (TCC)
instances
Waveform output channels per TCC
DMA channels
8/4/2
12
8/4/2
12
6/4/2
12
USB interface
1
1
1
Serial Communication Interface
(SERCOM) instances
6
1
6
1
4
1
Inter-IC Sound (I2S) interface
Analog-to-Digital Converter (ADC)
channels
20
2
14
2
10
2
Analog Comparators (AC)
Digital-to-Analog Converter (DAC)
channels
1
1
1
Real-Time Counter (RTC)
RTC alarms
Yes
1
Yes
1
Yes
1
1 32-bit value or
2 16-bit values
1 32-bit value or
2 16-bit values
1 32-bit value or
2 16-bit values
RTC compare values
External Interrupt lines
16
16
16
Peripheral Touch Controller (PTC) X
and Y lines
16x16
12x10
48MHz
10x6
Maximum CPU frequency
QFN
TQFP
QFN
TQFP
QFN
TQFP
Packages
32.768kHz crystal oscillator (XOSC32K)
0.4-32MHz crystal oscillator (XOSC)
32.768kHz internal oscillator (OSC32K)
Oscillators
32kHz ultra-low-power internal oscillator (OSCULP32K)
8MHz high-accuracy internal oscillator (OSC8M)
48MHz Digital Frequency Locked Loop (DFLL48M)
96MHz Fractional Digital Phased Locked Loop (FDPLL96M)
Atmel | SMART SAM D21 [DATASHEET SUMMARY]
3
Atmel-42181DS–SAM-D21_Summary–09/2014
SAM D21J
12
SAM D21G
SAM D21E
Event System channels
SW Debug Interface
12
12
Yes
Yes
Yes
Yes
Yes
Watchdog Timer (WDT)
Yes
Atmel | SMART SAM D21 [DATASHEET SUMMARY]
4
Atmel-42181DS–SAM-D21_Summary–09/2014
2.
Ordering Information
SAMD 21 E 15 A
-
M U T
Product Family
Package Carrier
SAMD = General Purpose Microcontroller
No character = Tray (Default)
T = Tape and Reel
Product Series
21 = Cortex M0 + CPU, Basic Feature Set
+ DMA + USB
Package Grade
O
U = 40 - 85 C Matte Sn Plating
Pin Count
E = 32 Pins
G = 48 Pins
J = 64 Pins
Package Type
Flash Memory Density
A = TQFP
M = QFN
18 = 256KB
17 = 128KB
16 = 64KB
15 = 32KB
Device Variant
A = Default Variant
2.1
SAM D21E
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
TQFP32
TQFP32
QFN32
QFN32
TQFP32
TQFP32
QFN32
QFN32
TQFP32
TQFP32
QFN32
QFN32
Carrier Type
Tray
ATSAMD21E15A-AU
ATSAMD21E15A-AUT
ATSAMD21E15A-MU
ATSAMD21E15A-MUT
ATSAMD21E16A-AU
ATSAMD21E16A-AUT
ATSAMD21E16A-MU
ATSAMD21E16A-MUT
ATSAMD21E17A-AU
ATSAMD21E17A-AUT
ATSAMD21E17A-MU
ATSAMD21E17A-MUT
Tape & Reel
Tray
32K
4K
Tape & Reel
Tray
Tape & Reel
Tray
64K
8K
Tape & Reel
Tray
Tape & Reel
Tray
128K
16K
Tape & Reel
Atmel | SMART SAM D21 [DATASHEET SUMMARY]
5
Atmel-42181DS–SAM-D21_Summary–09/2014
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
TQFP32
TQFP32
QFN32
Carrier Type
Tray
ATSAMD21E18A-AU
ATSAMD21E18A-AUT
ATSAMD21E18A-MU
ATSAMD21E18A-MUT
Tape & Reel
Tray
256K
32K
QFN32
Tape & Reel
2.2
SAM D21G
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
TQFP48
TQFP48
QFN48
QFN48
TQFP48
TQFP48
QFN48
QFN48
TQFP48
TQFP48
QFN48
QFN48
TQFP48
TQFP48
QFN48
QFN48
Carrier Type
Tray
ATSAMD21G15A-AU
ATSAMD21G15A-AUT
ATSAMD21G15A-MU
ATSAMD21G15A-MUT
ATSAMD21G16A-AU
ATSAMD21G16A-AUT
ATSAMD21G16A-MU
ATSAMD21G16A-MUT
ATSAMD21G17A-AU
ATSAMD21G17A-AUT
ATSAMD21G17A-MU
ATSAMD21G17A-MUT
ATSAMD21G18A-AU
ATSAMD21G18A-AUT
ATSAMD21G18A-MU
ATSAMD21G18A-MUT
Tape & Reel
Tray
32K
4K
Tape & Reel
Tray
Tape & Reel
Tray
64K
128K
256K
8K
Tape & Reel
Tray
Tape & Reel
Tray
16K
32K
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
2.3
SAM D21J
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
TQFP64
TQFP64
QFN64
Carrier Type
Tray
ATSAMD21J15A-AU
ATSAMD21J15A-AUT
ATSAMD21J15A-MU
ATSAMD21J15A-MUT
Tape & Reel
Tray
32K
4K
QFN64
Tape & Reel
Atmel | SMART SAM D21 [DATASHEET SUMMARY]
6
Atmel-42181DS–SAM-D21_Summary–09/2014
Ordering Code
FLASH (bytes)
SRAM (bytes)
Package
TQFP64
TQFP64
QFN64
QFN64
TQFP64
TQFP64
QFN64
QFN64
TQFP64
TQFP64
QFN64
QFN64
Carrier Type
Tray
ATSAMD21J16A-AU
ATSAMD21J16A-AUT
ATSAMD21J16A-MU
ATSAMD21J16A-MUT
ATSAMD21J17A-AU
ATSAMD21J17A-AUT
ATSAMD21J17A-MU
ATSAMD21J17A-MUT
ATSAMD21J18A-AU
ATSAMD21J18A-AUT
ATSAMD21J18A-MU
ATSAMD21J18A-MUT
Tape & Reel
Tray
64K
8K
Tape & Reel
Tray
Tape & Reel
Tray
128K
256K
16K
32K
Tape & Reel
Tray
Tape & Reel
Tray
Tape & Reel
Atmel | SMART SAM D21 [DATASHEET SUMMARY]
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Atmel-42181DS–SAM-D21_Summary–09/2014
3.
Block Diagram
IOBUS
256/128/64/32KB
NVM
32/16/8/4KB
RAM
CORTEX-M0+
PROCESSOR
Fmax 48 MHz
SWCLK
SWDIO
SERIAL
WIRE
NVM
CONTROLLER
Cache
SRAM
CONTROLLER
DEVICE
SERVICE
UNIT
M
S
S
S
M
M
DMA
HIGH SPEED
BUS MATRIX
PERIPHERAL
ACCESS CONTROLLER
DP
USB FS
S
S
S
DM
DEVICE
MINI-HOST
SOF 1KHZ
AHB-APB
BRIDGE B
AHB-APB
BRIDGE A
AHB-APB
BRIDGE C
PERIPHERAL
ACCESS CONTROLLER
PERIPHERAL
ACCESS CONTROLLER
DMA
SYSTEM CONTROLLER
PAD0
PAD1
PAD2
PAD3
6 x SERCOM
VREF
OSCULP32K
OSC32K
BOD33
XOSC32K
XOSC
DMA
XIN32
XOUT32
WO0
WO1
OSC8M
5 x TIMER / COUNTER
DFLL48M
FDPLL96M
XIN
XOUT
WO0
WO1
DMA
3x TIMER / COUNTER
FOR CONTROL
(2)
POWER MANAGER
CLOCK
WOn
DMA
AIN[19..0]
VREFA
CONTROLLER
20-CHANNEL
12-bit ADC 350KSPS
RESET
CONTROLLER
SLEEP
CONTROLLER
VREFB
RESETN
CMP[1..0]
AIN[3..0]
GENERIC CLOCK
CONTROLLER
2 ANALOG
COMPARATORS
GCLK_IO[7..0]
REAL TIME
COUNTER
DMA
VOUT
10-bit DAC
WATCHDOG
TIMER
VREFA
EXTINT[15..0]
NMI
EXTERNAL INTERRUPT
CONTROLLER
X[15..0]
Y[15..0]
PERIPHERAL
TOUCH
CONTROLLER
DMA
MCK[1..0]
SCK[1..0]
SD[1..0]
FS[1..0]
INTER-IC
SOUND
CONTROLLER
1. Some products have different number of SERCOM instances, Timer/Counter instances, PTC signals and ADC
signals.
2. The three TCC instances have different configurations, including the number of Waveform Output (WO) lines.
Atmel | SMART SAM D21 [DATASHEET SUMMARY]
8
Atmel-42181DS–SAM-D21_Summary–09/2014
4.
Pinout
4.1
SAM D21J
VDDIO
GND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PA00
PA01
1
2
PA25
PA24
PA23
PA22
PA21
PA20
PB17
PB16
PA19
PA18
PA17
PA16
VDDIO
GND
3
PA02
4
PA03
5
PB04
6
PB05
7
GNDANA
VDDANA
PB06
8
9
10
11
12
13
14
15
16
PB07
PB08
PB09
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
Atmel | SMART SAM D21 [DATASHEET SUMMARY]
9
Atmel-42181DS–SAM-D21_Summary–09/2014
4.2
SAM D21G
36
35
34
33
32
31
30
29
28
27
26
25
VDDIO
GND
PA00
1
2
PA01
PA02
PA25
PA24
PA23
PA22
PA21
PA20
PA19
PA18
PA17
PA16
3
PA03
4
5
GNDANA
VDDANA
PB08
6
7
8
PB09
9
PA04
10
11
12
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
Atmel | SMART SAM D21 [DATASHEET SUMMARY]
10
Atmel-42181DS–SAM-D21_Summary–09/2014
4.3
SAM D21E
24
23
22
21
20
19
18
17
PA25
PA24
PA23
PA22
PA19
PA18
PA17
PA16
PA00
1
2
3
4
5
6
7
8
PA01
PA02
PA03
PA04
PA05
PA06
PA07
DIGITAL PIN
ANALOG PIN
OSCILLATOR
GROUND
INPUT SUPPLY
REGULATED OUTPUT SUPPLY
Atmel | SMART SAM D21 [DATASHEET SUMMARY]
11
Atmel-42181DS–SAM-D21_Summary–09/2014
5.
Product Mapping
Figure 5-1. Atmel | SMART SAM D21 Product Mapping
Global Memory Space
Code
0x00000000
0x00000000
0x20000000
0x20008000
0x40000000
0x43000000
0x60000000
Internal Flash
0x00400000
0x1FFFFFFF
Code
SRAM
Reserved
AHB-APB Bridge C
0x42000000
SRAM
PAC2
EVSYS
SERCOM0
SERCOM1
SERCOM2
SERCOM3
SERCOM4
SERCOM5
TCC0
0x20000000
0x20007FFF
Internal SRAM
0x42000400
0x42000800
0x42000C00
0x42001000
0x42001400
0x42001800
0x42001C00
0x42002000
0x42002400
0x42002800
0x42002C00
0x42003000
0x42003400
0x42003800
0x42003C00
0x42004000
0x42004400
0x42004800
0x42004C00
0x42005000
Undefined
Peripherals
AHB-APB
0x40000000
0x41000000
AHB-APB
Bridge A
AHB-APB
Bridge B
0x42000000
0x42FFFFFF
Reserved
AHB-APB
Bridge C
Undefined
Reserved
System
System
0xE0000000
0xE000E000
0xE000F000
0xE00FF000
Reserved
0x60000200
0xE0000000
SCS
TCC1
Reserved
ROMTable
Reserved
TCC2
0xFFFFFFFF
TC3
0xE0100000
0xFFFFFFFF
TC4
AHB-APB Bridge A
TC5
AHB-APB Bridge B
0x41000000
0x40000000
PAC1
PAC0
PM
TC6
0x41002000
0x41004000
0x41004400
0x41004800
0x41005000
0x41006000
0x40000400
0x40000800
0x40000C00
0x40001000
0x40001400
0x40001800
DSU
TC7
NVMCTRL
PORT
SYSCTRL
GCLK
WDT
ADC
AC
DMAC
USB
DAC
RTC
PTC
MTB
EIC
I2S
0x40001C00
0x40FFFFFF
0x41007000
0x41FFFFFF
0x42005400
0x42FFFFFF
Reserved
Reserved
Reserved
This figure represents the full configuration of the Atmel® SAM D21 with maximum flash and SRAM capabilities and a full
set of peripherals. Refer to the “Configuration Summary” on page 3 for details.
Atmel | SMART SAM D21 [DATASHEET SUMMARY]
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Atmel-42181DS–SAM-D21_Summary–09/2014
6.
Processor And Architecture
6.1
Cortex M0+ Processor
The Atmel | SMART SAM D21 implements the ARM® Cortex™-M0+ processor, which is based on the ARMv6
Architecture and Thumb®-2 ISA. The Cortex M0+ is 100% instruction set compatible with its predecessor, the Cortex-M0
processor, and upward compatible to Cortex-M3 and M4 processors.
For more information refer to www.arm.com.
6.1.1 Cortex M0+ Configuration
Atmel | SMART SAM D21
configuration
Features
Configuration option
External interrupts 0-32
Little-endian or big-endian
Present or absent
0, 1, 2
Interrupts
32
Data endianness
Little-endian
Present
2
SysTick timer
Number of watchpoint comparators
Number of breakpoint comparators
Halting debug support
Multiplier
0, 1, 2, 3, 4
4
Present or absent
Fast or small
Present
Fast (single cycle)
Present
Not supported
Present
Absent(1)
Not present
Absent
Single-cycle I/O port
Wake-up interrupt controller
Vector Table Offset Register
Unprivileged/Privileged support
Memory Protection Unit
Reset all registers
Present or absent
Supported or not supported
Present or absent
Present or absent
Not present or 8-region
Present or absent
16-bit only or mostly 32-bit
Instruction fetch width
32-bit
Note: 1. All software run in privileged mode only
The ARM Cortex-M0+ core has two bus interfaces:
z
Single 32-bit AMBA®-3 AHB-Lite™ system interface that provides connections to peripherals and all system
memory, including flash and RAM
z
Single 32-bit I/O port bus interfacing to the PORT with one-cycle loads and stores
Atmel | SMART SAM D21 [DATASHEET SUMMARY]
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Atmel-42181DS–SAM-D21_Summary–09/2014
7.
Packaging Information
7.1
Thermal Considerations
7.1.1 Thermal Resistance Data
Table 7-1 summarizes the thermal resistance data depending on the package.
Table 7-1. Thermal Resistance Data
Package Type
32-pin TQFP
48-pin TQFP
64-pin TQFP
32-pin QFN
48-pin QFN
64-pin QFN
θJA
θJC
68 °C/W
78.8 °C/W
66.7 °C/W
37.2 °C/W
33 °C/W
33.5 °C/W
25.8 °C/W
12.3 °C/W
11.9 °C/W
3.1 °C/W
11.4 °C/W
11.2 °C/W
7.1.2 Junction Temperature
The average chip-junction temperature, TJ, in °C can be obtained from the following:
where:
z
z
z
z
z
θ
θ
θ
JA = package thermal resistance, Junction-to-ambient (°C/W), provided in Table 7-1.
JC = package thermal resistance, Junction-to-case thermal resistance (°C/W), provided in Table 7-1.
HEATSINK = cooling device thermal resistance (°C/W), provided in the device datasheet.
PD = device power consumption (W).
TA = ambient temperature (°C).
From the first equation, the user can derive the estimated lifetime of the chip and decide if a cooling device is necessary
or not. If a cooling device is to be fitted on the chip, the second equation should be used to compute the resulting average
chip-junction temperature TJ in °C.
Atmel | SMART SAM D21 [DATASHEET SUMMARY]
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Atmel-42181DS–SAM-D21_Summary–09/2014
7.2
Package Drawings
7.2.1 64-pin TQFP
Table 7-2. Device and Package Maximum Weight
300
mg
Table 7-3. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 7-4. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MS-026
E3
Atmel | SMART SAM D21 [DATASHEET SUMMARY]
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Atmel-42181DS–SAM-D21_Summary–09/2014
7.2.2 64-pin QFN
Table 7-5. Device and Package Maximum Weight
200
mg
Table 7-6. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 7-7. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MO-220
E3
Atmel | SMART SAM D21 [DATASHEET SUMMARY]
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Atmel-42181DS–SAM-D21_Summary–09/2014
7.2.3 48-pin TQFP
Table 7-8. Device and Package Maximum Weight
140
mg
Table 7-9. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 7-10. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MS-026
E3
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7.2.4 48-pin QFN
Table 7-11. Device and Package Maximum Weight
140
mg
Table 7-12. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 7-13. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MO-220
E3
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Atmel-42181DS–SAM-D21_Summary–09/2014
7.2.5 32-pin TQFP
Table 7-14. Device and Package Maximum Weight
100
mg
Table 7-15. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 7-16. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MS-026
E3
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Atmel-42181DS–SAM-D21_Summary–09/2014
7.2.6 32-pin QFN
Table 7-17. Device and Package Maximum Weight
90
mg
Table 7-18. Package Characteristics
Moisture Sensitivity Level
MSL3
Table 7-19. Package Reference
JEDEC Drawing Reference
JESD97 Classification
MO-220
E3
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Atmel-42181DS–SAM-D21_Summary–09/2014
7.3
Soldering Profile
The following table gives the recommended soldering profile from J-STD-20.
Profile Feature
Green Package
3°C/s max
150-200°C
60-150s
Average Ramp-up Rate (217°C to peak)
Preheat Temperature 175°C +/-25°C
Time Maintained Above 217°C
Time within 5°C of Actual Peak Temperature
Peak Temperature Range
30s
260°C
Ramp-down Rate
6°C/s max
8 minutes max
Time 25°C to Peak Temperature
A maximum of three reflow passes is allowed per component.
___REV___264506
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Table of Contents
Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2
1. Configuration Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
2. Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
2.1
2.2
2.3
SAM D21E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
SAM D21G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
SAM D21J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3. Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
4. Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
4.1
4.2
4.3
SAM D21J . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
SAM D21G. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
SAM D21E . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
5. Product Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
6. Processor And Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
6.1
Cortex M0+ Processor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
7. Packaging Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
7.1
7.2
7.3
Thermal Considerations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Package Drawings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Soldering Profile. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22
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