T4260 [ATMEL]
AM/FM Front End IC; AM / FM前端IC
| 型号： | T4260 |
| 厂家： | 
ATMEL |
| 描述： | AM/FM Front End IC |
| 文件： | 总31页 (文件大小：300K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• AM/FM Tuner Front End with Integrated PLL
• AM Up-conversion System (AM-IF: 10.7 MHz)
• FM Down-conversion System (FM-IF: 10.7 MHz)
• IF Frequencies up to 25 MHz
• Fine-tuning Steps: AM = 1 kHz and FM = 50 kHz/25 kHz/12.5 kHz
• Fast Fractional PLL (Lock Time < 1 ms) Inclusive Spurious Compensation
• Fast RF-AGC, Programmable in 1-dB Steps
• Fast IF-AGC, Programmable in 2-dB Steps
• Fast Frequency Change by 2 Programmable N-divider
• Two DACs for Automatic Tuner Alignment
• High S/N Ratio
AM/FM
Front End IC
• 3-wire Bus (Enable, Clock and Data; 3 V and 5 V Microcontrollers-compatible)
Description
T4260
The T4260 is an advanced AM/FM receiver with integrated fast PLL as a single-chip
solution based on Atmel’s high-performance BICMOS II technology. The low-imped-
ance driver at the IF output is designed for the A/D of a digital IF. The fast tuning
concept realized in this part is based on patents held by Atmel and allows lock times
less than 1 ms for a jump over the FM band with a step width of 12.5 kHz. The AM
up-conversion and the FM down-conversion allows an economic filter concept. An
automatic tuner alignment is provided by built-in DACs for gain and offset compensa-
tion. The frequency range of the IC covers the FM broadcasting band as well as the
AM band. The low current consumption helps the designers to achieve economic
power consumption concepts and helps to keep the power dissipation in the tuner low.
Pin Description
Figure 1. Pinning SSO44
Rev. 4528G–AUDR–12/03
Pin Description
Pin
Symbol
DAC1
Function
1
DAC1 output
2
DAC2
DAC2 output
3
FMAGCO
MXFMIA
MXFMIB
GNDRF
MXAMIB
MXAMIA
AMAGCO
IFAGCA2
SW2/AGC
RFAGCA2
SW1
FM AGC current
FM mixer input A
FM mixer input B
RF ground
4
5
6
7
AM mixer input B
AM mixer input A
AM AGC current
AM IF-AGC filter 2
Switch 2 / AM AGC voltage
RF AM-AGC filter 2
Switching output 1
VCO reference voltage
PLL supply voltage
FM loop filter
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
VRVCO
VSPLL
FMLF
AMLF
AM loop filter
VTUNE
OSCGND
OSCE
Tuning voltage
Oscillator ground
Oscillator emitter
Oscillator base
OSCB
OSCBUF
EN
Oscillator buffer output/input
3-wire bus Enable
3-wire bus Clock
3-wire bus Data
CLK
DATA
VRPLL
PLL reference voltage
PLL reference frequency
PLL ground
REFFREQ
GNDPLL
IFOUTB
IFOUTA
IFAGCFM
IFAGCA1
RFAGCFM
IFREF
IF output B
IF output A
FM IF-AGC filter
AM IF-AGC filter 1
RF FM-AGC filter
IF amplifier reference input
IF amplifier AM input
IF amplifier FM input
Tuner reference voltage
Tuner ground
IFINAM
IFINFM
VRT
GNDT
MXAMOB
MXAMOA
VST
AM mixer output B
AM mixer output A
Tuner supply voltage
RF AM-AGC filter 1
FM mixer output A
FM mixer output B
RFAGCA1
MXFMOA
MXFMOB
2
T4260
4528G–AUDR–12/03
T4260
Figure 2. Block Diagram
IFAGCFM
IFAGCA2
IFAGCA1
MXFMOB
MXFMOA
MXAMOA
40
IFINAM
IFREF ININFM
IFOUTA
IFOUTB
MXAMOB
29
10
30 31
32
44
36
43
39
34
35
41
37
38
14
VST
VRT
RF/IF
SUPPLY
GNDT
VRVCO
4
5
6
MXFMIA
MXFMIB
AGC
15
26
28
VSPLL
VRPLL
GNDPLL
GNDRF
PLL
SUPPLY
7
8
MXAMIB
MXAMIA
42
33
12
DIV
RFAGCA1
RFAGCFM
23
24
25
EN
BUS
CLK
DATA
RFAGCA2
11
13
SW2/AGC
SW1
FM
AM
AMAGCO
FMAGCO
9
3
SW-AMLF
2
1
DAC2
DAC1
N DIV
R DIV
PD
VCO
21
19
27
22
OSCBUF
20
16
FMLF AMLF
18
17
OSCE
OSCGND
VTUNE
REFFREQ
OSCB
Functional
Description
The T4260 implements an AM up-conversion reception path from the RF input signal to
the IF output signal. A VCO and an LO prescaler for AM are integrated to generate the
LO frequency to the AM mixer. The FM reception path generates the same LO
frequency from the RF input signal by a down-conversion to the IF output. The IF A/D
output is designed for digital signal processing. The IF can be chosen in the range of
10 MHz to 25 MHz. Automatic gain control (AGC) circuits are implemented to control the
preamplifier stages in the AM and FM reception paths.
For improved performance, the PLL has an integrated special 2-bit shift fractional logic
with spurious suppression that enables fast frequency changes in AM and FM mode by
a low step frequency (fPDF). In addition, two programmable DACs (Digital to Analog
Converter) support the alignment via a microcontroller.
For a double-tuner concept, external voltage can be applied at the input of the DACs,
the internal PLL can switched off and the OSC buffer (output) can also be used as input.
Several register bits (Bit 0 to Bit 145) are used to control the circuit’s operation and to
adapt certain circuit parameters to the specific application. The control bits are orga-
nized in four 8-bit, four 16-bit and three 24-bit registers that can be programmed by the
3-wire bus protocol. The bus protocol and the bit-to-register mapping is described in the
section “3-wire Bus Description” on page 9. The meaning of the control bits is mentioned
in the following sections.
3
4528G–AUDR–12/03
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All voltages are referred to GND
Parameters
Symbol
VST, VSPLL
Ptot
Value
10
Unit
V
Analog supply voltage
Pins 15 and 41
Maximum power consumption
Ambient temperature range
Storage temperature range
Junction temperature
1.0
W
Tamb
-40 to +85
-40 to +150
150
°C
°C
°C
Tstg
Tj
Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient, soldered to PCB
RthJA
52
K/W
Operating Range
Parameters
Symbol
VST, VSPLL
Tamb
Min.
8
Typ.
Max.
10
Unit
Supply voltage range(1)
Ambient temperature
Oscillator frequency
Pins 15 and 41
8.5
V
-40
60
85
°C
Pin 21
Rfi
175
MHz
Note:
1. VST and VSPLL must have the same voltage.
Electrical Characteristics
Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25° C
No.
1
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Power Supply
15,
41
1.1
Supply voltage
VS
IS
8
8.5
85
10
V
C
A
AM and FM mode,
VS = 10 V
15,
41
1.2
2
Supply current
70
110
mA
PLL Divider
Programmable
R-divider
2.1
14-bit register
3
3
16383
A
A
B
Programmable (VCO)
N-divider
(1 kHz step frequency)
2- × 18-bit register
switchable via Bit 5
2.2
262143
Reference oscillator
input voltage
2.3
2.4
f = 0.1 MHz to 3 MHz
27
100
mVrms
FM
AM
120
120
150
2850
10000
10000
kHz
kHz
Reference frequency
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Minimum and maximum limits are characterized for entire temperature range (-40°C to +85° C) but are tested at +25°C
4
T4260
4528G–AUDR–12/03
T4260
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25° C
No.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Settling time in FM
mode (switching from
87.5 MHz to 108 MHz
or vice versa)
fPD = 50 kHz
2.5
1
ms
B
I
PD = 2 mA
3
AMLF/FMLF
16,
17
3.1
Output current 1
FMLF, AMLF = 1.8 V
FMLF, AMLF = 1.8 V
FMLF, AMLF = 1.8 V
FMLF, AMLF = 1.8 V
FMLF, AMLF = 1.8 V
40
80
50
60
120
1250
2450
10
µA
µA
µA
µA
nA
A(1)
A(1)
A(1)
A(1)
A(1)
16,
17
3.2
3.3
3.4
Output current 2
Output current 3
Output current 4
100
16,
17
850
1650
1000
2000
16,
17
16,
17
3.5
4
Leakage current
VTUNE
Saturation voltage
LOW
4.1
VSATH = (VA-VPDOFM
VSATH = (VA-VPDOFM
)
)
18
18
VSATL
VSATH
100
200
400
500
mV
mV
C
C
Saturation voltage
HIGH
4.2
5
DAC1, DAC2
5.1
5.2
5.3
5.4
5.5
5.6
6
Output current
1, 2
1, 2
1, 2
1, 2
1, 2
1, 2
IDAC1,2
1
mA
V
D
Output voltage
VDAC1,2
0.3
0.9
VS-0.6
1.1
A
Maximum offset range
Minimum offset range
Maximum gain range
Minimum gain range
Oscillator
Offset = 0, gain = 58
Offset = 127, gain = 58
Gain = 255, offset = 64
Gain = 0, offset = 64
0.98
-0.98
2.09
0.67
V
A(1)
A(1)
A(1)
A(1)
-0.9
2.06
0.63
-1.1
V
2.13
0.73
–
–
6.1
Frequency range
21
21
22
60
60
170
140
MHz
MHz
B
A
Fractional frequency
range
6.2
Fractional mode
6.3
7
Buffer output
Oscillator Input
Input voltage
FM Mixer
150
mVrms
mVrms
C
A
7.1
8
21
VOSC
150
75
8.1
8.2
8.3
8.4
8.5
Frequency range
Input IP3
163
MHz
dBµV
kΩ
B
C
D
D
C
133
3.5
Input impedance
Input capacitance
Noise figure
4
pF
F
14
dB
Conversion
transconductance
8.6
2.6
3.1
3.6
ms
D(1)
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40°C to +85° C) but are tested at +25°C
5
4528G–AUDR–12/03
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25° C
No.
9
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
AM Mixer (Symmetrical Input)
Frequency range
Input IP3
9.1
9.2
9.3
9.4
0.075
26
MHz
dBµV
kΩ
B
C
D
C
133
2.5
10
Input impedance
Noise figure
F
dB
Conversion
transconductance
9.5
2.6
3.1
3.6
mS
D(1)
10
Isolation
10.1 Isolation AM-FM
10.2 IF suppression
40
40
dB
dB
C
C
11
RF-AGC
FM
AM
75
0.075
163
26
MHz
MHz
11.1 Frequency range
11.2 Output current
A
B
FM
AM
5
5
mA
mA
FM rising
FM falling
AM symmetrical
2
50
40
ms
ms
ms
Output current time
constant
11.3
C
88 dBµV
89 dBµV
90 dBµV
91 dBµV
92 dBµV
93 dBµV
94 dBµV
95 dBµV
96 dBµV
97 dBµV
98 dBµV
99 dBµV
100 dBµV
101 dBµV
102 dBµV
103 dBµV
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
42
87
88
88
89
90
91
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
89
90
92
90
91
93
91
92
94
92
93
95
93
94
96
RF-AGC AM threshold
11.4 (programmable with
Bit 12 - Bit 15)
94
95
97
95
96
98
96
97
99
97
98
100
101
102
103
104
107
98
99
99
100
101
102
103
100
101
102
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Minimum and maximum limits are characterized for entire temperature range (-40°C to +85° C) but are tested at +25°C
6
T4260
4528G–AUDR–12/03
T4260
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25° C
No.
Parameters
Test Conditions
91 dBµV
Pin
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
33
Symbol
Min.
90
Typ.
91
Max.
93
Unit
Type*
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
92 dBµV
91
92
95
93 dBµV
92
93
96
94 dBµV
93
94
96
95 dBµV
94
95
98
96 dBµV
95
96
99
97 dBµV
96
97
102
101
102
104
104
105
106
107
108
109
RF-AGC FM threshold
98 dBµV
97
98
11.5 (programmable with
Bit 12 - Bit 15)
99 dBµV
98
99
100 dBµV
101 dBµV
102 dBµV
103 dBµV
104 dBµV
105 dBµV
106 dBµV
99
100
101
102
103
104
105
106
100
101
102
103
104
105
12
IF Amplifier
12.1 Frequency range
12.2 Output voltage
10
25
MHz
A
B
117
55
dBµV
f1 = 10.7 MHz
f2 = 10.75 MHz
RL = 2 × 300 Ω
Distortion
12.3
dB
A
(2-tone IM3)
Gain (programmable in
2-dB steps)
Minimum gain
Maximum gain
12
42
dB
dB
12.4
A
D
FM
AM
36,
35
330
2500
Ω
Ω
12.5 Input impedance
13
IF-AGC
109 dBµV
111 dBµV
113 dBµV
115 dBµV
117 dBµV
118 dBµV
119 dBµV
121 dBµV
29/30
29/30
29/30
29/30
29/30
29/30
29/30
29/30
108
110
111
113
116
117
118
120
109
111
113
115
117
118
119
121
40
112
114
115
117
121
122
123
126
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dBµV
dB
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
A(1)
B
IF-AGC
AM/FM threshold
(programmable with
Bit 0 - Bit 2)
13.1
13.2 AGC dynamic range
AGC time constant
13.3 (external capacity
≤100 nF)
FM rising
FM falling
AM symmetrical
16
4
200
µs
ms
ms
D
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note: 1. Minimum and maximum limits are characterized for entire temperature range (-40°C to +85° C) but are tested at +25°C
7
4528G–AUDR–12/03
Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VST/VSPLL = +8.5 V, Tamb = +25° C
No.
14
Parameters
IF Gain
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
12 dB
14 dB
16 dB
18 dB
20 dB
22 dB
24 dB
26 dB
28 dB
30 dB
32 dB
34 dB
36 dB
38 dB
40 dB
42 dB
9
12
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
14
16
18
20
22
24
26
28
30
32
34
36
38
40
42
44
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
dB
A(1)
A(1)
A(1)
C(1)
A(1)
C(1)
C(1)
C(1)
A(1)
C(1)
C(1)
C(1)
C(1)
C(1)
C(1)
A(1)
12
14
17
17
19
21
23
25
27
29
31
33
35
37
39
IF gain
14.1 (programmable with
Bit 6 - Bit 9)
15
SWO1 (Open Drain)
15.1 Output voltageLOW
13
13
13
VSWOL
IOHL
100
160
200
10
mV
µA
V
A
A
C
I = 1 mA,
Output leakage current
HIGH
VSWO1 = 8.5 V
15.2
15.3 Maximum output voltage
8.5
16
SW2/AGC (Open Drain in Switch Mode)
16.1 Output voltage LOW
11
11
11
VSWOL
IOHL
100
160
200
10
mV
µA
V
A
A
C
I = 1 mA,
V11 = 6 V
16.2 Output leakage current
HIGH
16.3 Maximum output voltage
6
17
3-wire Bus, ENABLE, DATA, CLOCK
High
Low
VBUS
VBUS
2.7
-0.3
5.3
+0.8
V
V
A
A
17.1 Input voltage
17.2 Clock frequency
17.3 Period of CLK
23-25
24
1.0
MHz
B
tH
tL
250
250
ns
ns
C
C
24
17.4 Rise time EN, DA, CLK
17.5 Fall time EN, DA, CLK
17.6 Set-up time
23-25
23-25
23-25
23
tR
tF
400
100
ns
ns
ns
ns
ns
C
C
C
C
C
tS
100
250
0
17.7 Hold time EN
tHEN
tHDA
17.8 Hold time DA
25
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Note:
1. Minimum and maximum limits are characterized for entire temperature range (-40°C to +85° C) but are tested at +25°C
8
T4260
4528G–AUDR–12/03
T4260
3-wire Bus
Description
The register settings of the T4260 are programmed by a 3-wire bus protocol. The bus
protocol consists of separate commands. A defined number of bits is transmitted
sequentially during each command.
One command is used to program all bits of one register. The different registers avail-
able (see chapter “3-wire Bus Data Transfer” on page 11) are addressed by the length
of the command (number of transmitted bits) and by two address bits that are unique to
each register of a given length. 8-bit registers are programmed by 8-bit commands, 16-
bit registers are programmed by 16-bit commands and 24-bit registers are programmed
by 24-bit commands.
Each bus command starts with a falling edge on the enable line (EN) and ends with a
rising edge on EN. EN has to be kept LOW during the bus command.
The sequence of transmitted bits during one command starts with the MSB of the first
byte and ends with the LSB of the last byte of the register addressed. To transmit one bit
(0/1), DATA has to be set to the appropriate value (LOW/HIGH) and a LOW-to-HIGH
transition has to be performed on the clock line (CLK) while DATA is valid. The DATA is
evaluated at the rising edges of CLK. The number of LOW-to-HIGH transitions on CLK
during the LOW period of EN is used to determine the length of the command.
Figure 3. 3-wire Pulse Diagram
8-bit command
EN
DATA
CLK
MSB
BYTE 1
LSB
16-bit command
EN
DATA
CLK
MSB
BYTE 1
LSB MSB
BYTE 2
LSB
24-bit command
EN
DATA
CLK
MSB
BYTE 1
LSB MSB
BYTE 2
LSB MSB
BYTE 3
LSB
e.g. R-Divider
PDFM
PDAM
20
20
X
26
23
22
21
2
2
211
29
28
13
12
27
25
24
2
1
0
23
Fract.
22
VCO-Divider
2 1
10
X
R-Divider
Addr.
9
4528G–AUDR–12/03
Figure 4. 3-wire Bus Timing Diagram
tF
tR
VHigh
VLow
Enable
tHEN
tS
tR
tF
VHigh
VLow
Data
tHDA
tS
tR
tF
VHigh
VLow
Clock
tH
tL
10
T4260
4528G–AUDR–12/03
T4260
3-wire Bus Data Transfer
Table 1. Control Registers
A24_10
MSB
BYTE 1
LSB
MSB
BYTE 2
LSB
MSB
BYTE 3
Fractio-
LSB
PDAM/
PDFM
R-Divider
R-Divider
ADDR.
Divider VCO
nal
0/1
144
27
26
25
24
23
127
22
21
20
x
x
213
212
211
135
210
29
28
1
x
0
x
1/0
23
22
21
20
131
130
129
128
126
125
124
139
138
137
136
134
133
132
145
143
142
141
140
A24_01
MSB
BYTE 1
N2-Divider
LSB
MSB
BYTE 2
N2-Divider
LSB
MSB
ADDR.
BYTE 3
LSB
x
x
x
x
N2-Divider
27
26
108
1.
25
24
23
22
21
20
215
214
213
212
211
210
29
28
0
x
1
x
01)
01)
01)
01)
217
216
109
107
106
105
104
103
102
117
116
115
114
113
112
111
110
123
122
121
120
119
118
Note:
Value has to be 0.
A24_00
MSB
BYTE 1
LSB
MSB
BYTE 2
N1-Divider
LSB
MSB
ADDR.
BYTE 3
LSB
N1-Divider
x
x
x
x
N1-Divider
27
26
86
1.
25
24
23
22
21
20
215
95
214
94
213
93
212
211
210
90
29
28
0
x
0
x
01)
01)
01)
01)
217
216
87
85
84
83
82
81
80
92
91
89
88
101
100
99
98
97
96
Note:
Value has to be 0.
A16_11
MSB
BYTE 1
LSB
MSB
ADDR.
BYTE 2
LSB
DAC2-Gain
27
26
25
24
23
22
21
20
1
x
1
x
x
x
x
x
x
x
73
72
71
70
69
68
67
66
79
78
77
76
75
74
A16_10
MSB
BYTE 1
DAC2-Offset
LSB
MSB
ADDR.
BYTE 2
LSB
SW-
AMLF
Osc.-
Low
High
c.CP
SW-
impulse
SW-
wire
Buffer
c. CP
1 =
ON/
OFF
HI/
LO
HI/
LO
ON/
OFF
ON/
OFF
x
26
25
24
23
55
22
21
20
1
x
0
x
standard
65
59
58
57
56
54
53
52
64
63
62
61
60
A16_01
MSB
BYTE 1
DAC1-Gain
LSB
MSB
ADDR.
BYTE 2
LSB
1=SW2
0=AGC
SW2
1=low
SW1
1=low
27
26
25
24
23
41
22
21
20
0
x
1
x
x
x
x
1/0
1/0
47
1/0
46
45
44
43
42
40
39
38
51
50
49
48
11
4528G–AUDR–12/03
A16_00
MSB
BYTE 1
LSB
MSB
BYTE 2
LSB
SHIFT
1/0
DAC1-Offset
ADDR.
x
0
x
x
0
x
0
x
x
26
25
24
23
22
21
20
0
x
0
x
0
01)
31
30
29
28
27
26
25
24
37
36
35
34
33
32
Note:
1.
Value has to be 0.
A8_11
MSB
BYTE 1
LSB
Delay time high
cur. CP2
Delay time
high cur. CP1
ADDR.
x
HCDEL
ON/
OFF
HI/
LO
ON/
OFF
HI/
LO
1
1
x
01)
19
1/0
18
x
23
22
21
20
Note:
1.
Value has to be 0.
A8_10
MSB
BYTE 1
LSB
AM/
FM
IF-
AGC
ADDR.
RF-AGC
1
x
0
x
1/0
17
1/0
16
23
22
21
20
15
14
13
12
A8_01
MSB
BYTE 1
LSB
ADDR.
IF-IN
VCO
HI/LO
10
IF-Gain
AM/
FM
0
x
1
x
23
9
22
8
21
7
20
6
11
A8_00
MSB
BYTE 1
LSB
PLL
ON/
OFF
PDTE/
PD
ADDR.
N2/N1
IF-AGC
0
x
0
x
1/0
5
1/0
4
01)
3
22
2
21
1
20
0
Note:
1.
Value has to be 0.
12
T4260
4528G–AUDR–12/03
T4260
Bus Control
IF-AGC
The IF-AGC controls the level of the IF signal that is passed to the external ceramic filter
and the IF input (AM Pin 35 or FM Pin 36 and Pin 34). In AM mode the time constant
can be selected by the external capacitors at Pin 32 (IFAGCA1) and Pin 10 (IFAGCA2)
and in FM mode by an external capacitor at Pin 31 (IFAGCFM). In AM mode, the double
pole (by the capacitors at Pin 32 and Pin 10) allows a better harmonic distortion by a
lower time constant.
The IF-AGC threshold can be controlled by setting Bits 0 to 2 as given in Table 2.
Table 2. IF-AGC Threshold
IF-AGC
B2
0
B1
0
B0
0
109 dBµV
111 dBµV
113 dBµV
115 dBµV
117 dBµV
118 dBµV
119 dBµV
121 dBµV
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
The IF-AGC ON/OFF can be controlled by Bit 16 as given in Table 3.
Table 3. IF-AGC
IF-AGC ON/OFF
B16
0
IF-AGC ON
IF-AGC OFF
1
PD Test
A special test mode for PD is implemented for final production test only. This mode is
activated by setting Bit 3 = 1. This mode is not intended to be used by customer
application. For normal operation Bit 3 has to be set to 0.
Table 4. PD-Test Mode
PD TE/PD
B3
0
Pin 17 = AMLF output (standard)
Pin 17 = PD Testmode
1
N1/N2
The N2/N1 Bit controls the active N-divider. Only one of the two N-Divider can be active.
The N1-Divider is activated by setting Bit 5 = 0, the N2-Divider by setting Bit 5 = 1.
Table 5. N-Divider
N2/N1
B5
0
N1-divider active
N2-divider active
1
13
4528G–AUDR–12/03
IF Amplifier
The IF gain amplifier can be used in AM and FM mode to compensate the loss of the
external ceramic bandfilters.
The IF gain can be controlled in 2-dB steps by setting Bit 6 to Bit 9 as given in Table 6.
Table 6. IF Gain
IF Gain
12 dB
14 dB
16 dB
18 dB
20 dB
...
B9
0
B8
0
B7
0
B6
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
...
1
...
1
...
1
...
0
40 dB
42 dB
1
1
1
1
The selection of the IF amplifier input can be controlled by Bit 11 as given in Table 7.
Table 7. IF-IN Operating Mode
IF-IN AM/FM
B11
0
IF-IN FM
IF-IN AM
1
REMARK:
The AM input (Pin 35) has an input impedance of 2.5 kΩfor matching with a crystal filter.
The FM input (Pin 36) has an input impedance of 330 Ω for matching with a ceramic
filter.
VCO
The VCO HI/LO function is controlled by means of Bit 10.
Table 8. VCO Operating Mode
VCO HI/LO
B10
0
VCO high current
VCO low current
1
RF-AGC
The AM and FM RF-AGC controls the current into the AM and FM pin diodes (FM Pin 3
and AM Pin 9) to limit the level at the AM or FM mixer input. If the level at the AM or FM
mixer input exceeds the selected threshold, then the current into the AM or FM pin
diodes increases. If this step is not sufficient in AM mode, the source drain voltage of
the MOSFET (Pin 11) can be decreased. In AM mode, the time constants can be
selected by the external capacitors at Pin 42 (RFAGCA1) and at Pin 12 (RFAGCAM2)
and in FM mode by an external capacitor at Pin 33 (RFAGCFM). In AM mode, the dou-
ble pole (by the capacitors at Pin 42 and Pin 12) allows a better harmonic distortion by a
lower time constant.
The RF-AGC can be controlled in 1-dB steps by setting the Bits 12 to 15. The values for
FM and AM are controlled by Bit 17.
14
T4260
4528G–AUDR–12/03
T4260
Table 9. RF-AGC
RF-AGC AM
88 dB
RF-AGC FM
91 dB
92 dB
93 dB
94 dB
95 dB
...
B15
0
B14
0
B13
0
B12
0
89 dB
0
0
0
1
90 dB
0
0
1
0
91 dB
0
0
1
1
92 dB
0
1
0
0
...
...
1
...
1
...
1
...
0
102 dB
103 dB
105 dB
106 dB
1
1
1
1
Reception Mode
There are two different operation modes, AM and FM, which are selected by means of
Bit 17 and Bit 145 according to Table 1 and Table 2. In AM mode (Bit 17 = 1), the AM
mixer, the AM RF-AGC, the AM divider (prescaler) and the IF AM amplifier (input at
Pin 35) are activated. In FM mode (Bit 17 = 0), the FM mixer, the FM RF-AGC and the
IF FM amplifier (input at Pin 36) are activated.
In AM or FM reception mode, Bit 145 has to be set to the corresponding mode. The
buffer amplifier input can be connected to Pin 16 (with the external FM loop filter) by Bit
145 = 0 and to Pin 17 (with the external AM loopfilter) by Bit 145 = 1.
The AM/FM function for the tuner part is controlled by Bit 17 as given in Table 10.
Table 10. Tuner Operating Modes
AM/FM
B17
0
FM
AM
1
PLL
The PLL can switch off by Bit 4 = 0. In this case, the N-Divider input signal is internally
connected to ground.
Table 11. PLL Mode
PLL ON/OFF
B4
0
PLL OFF
PLL ON
1
HCDEL
There are two registers, HCDEL 1 (Bits 20 and 21) and HCDEL 2 (Bits 22 and 23), to
control the delay time of the high-current charge pump and to deactivate them. Bit 18
(HCDEL) determines whether register HCDEL 1 or 2 is used.
Table 12. High-current Charge Pump Delay Time Register
HCDEL 1/2 Select Mode
HCDEL (B18)
HCDEL 1
HCDEL 2
0
1
15
4528G–AUDR–12/03
If Bits 20 and 21 (HCDEL 1) or Bits 22 and 23 (HDCEL 2) are both set to 0, then the
high-current charge pump is deactivated. Otherwise, the delay time can be selected as
described in Table 13.
Table 13. Delay Time of HCDEL Register
High-current Charge Pump
B21/B23
B20/B22
OFF
0
0
1
1
0
1
0
1
Delay time 5 ns
Delay time 10 ns
Delay time 15 ns
2-bit Shift
A divider 2-bit shift (Bit 32 = 0) allows faster frequeny changes by using a four times
higher step frequeny (e.g., fPDF = 50 kHz instead of fPDF = 12.5 kHz). If the PLL is locked
(after the frequency change), the normal step frequency (e.g., fPDF = 12.5 kHz) will be
active again.
If no 2-bit shift is used (Bit 32 = 1), the frequeny changes will be done with the normal
step frequency (12.5 kHz).
In 2-bit shift mode the N- and R-divider are shifted by two bits to the right (this corre-
sponds by a R- and N-divider division by 4). An important condition for this mode is that
the R-divider has to be a multiple of 4.
Table 14. Manual and Lock Detect Shift Mode
2-bit Shift
B32
0
Dividers 2-bit shift
No shift
1
SW1 (Pin 13)
The switching output SW1 (Pin 13) is controlled by Bit 46 as given in Table 15.
Table 15. Switching Output
SW1
High
Low
B46
0
1
REMARK:
SW1 is an open-drain output.
Figure 5. Internal Components at SW1
SW1
16
T4260
4528G–AUDR–12/03
T4260
SW2/AGC (Pin 11)
The Pin SW2/AGC works as a switching output (open drain, Pin 11) or as an AM AGC-
control pin to control the cascade stage of an external AM-preamplifier.
The SW2/AGC is controlled by Bits 47 and 48 as given in Table 16.
Table 16. Switching Output 2 / AGC Mode
SW2/AGC
AGC function
High
B48
0
B47
X
1
0
Low
1
1
REMARK:
In AGC mode, the output voltage is 6 V down to 1 V.
Figure 6. Internal Components at SW2/AGC
VS
AGC
SWO/AGC
SW2
Test Mode
A special test mode is implemented for final production test only. This mode is activated
by setting Bit 123 = 1. This mode is not intended to be used by customer application. For
normal operation Bit 123 has to be set to 0.
Table 17. Test Mode
Test Mode
B123
ON
1
0
OFF
AM Mixer
The AM mixer is used for up-conversion of the AM reception frequency to the IF
frequency. Therefore, an AM prescaler is implemented to generate the necessary LO
frequency from the VCO frequency.
The VCO divider can be controlled by the Bits 140 to 143 as given in Table 18.
(The VCO divider is only active in AM mode)
17
4528G–AUDR–12/03
Table 18. Divider Factor of the AM Prescaler
Divider AM Prescaler
B143
B142
B141
B140
Divide by 2
0
0
0
0
0
0
0
0
1
0
0
0
0
1
1
1
1
x
0
0
1
1
0
0
1
1
x
0
1
0
1
0
1
0
1
x
Divide by 3
Divide by 4
Divide by 5
Divide by 6
Divide by 7
Divide by 8
Divide by 9
Divide by 10
FM Mixer
In the FM mixer stage, the FM reception frequency is down-converted to the IF
frequency. The VCO frequency is used as LO frequency for the mixer.
PLL Loop Filter
The PLL loop filter selection for AM and FM mode can be controlled by Bit 145 as given
in Table 19.
Table 19. Loop Filter Operating Mode
PDAM/PDFM
PDFM active
PDAM active
B145
0
1
Fractional Mode
The activated fractional mode (Bit 144 = 0) in connection with the direct shift (Bit 32 = 0)
allows fast frequency changes (with the help of the 2-bit shift) with a four times higher
step frequency. After the frequency change, the normal step frequency is active again.
If the fractional mode is deactivated (Bit 144 = 1) and direct shift mode is active,
(Bit 32 = 0) the VCO frequency is set to the next lower frequency which is many times
the amount frequency of 4 times step frequency. This means that the 2 shifted bits of the
active N-Divider are not used in this mode. The shift bits are interpreted as logic 0.
The fractional mode with direct shift mode deactivated (Bit 32 = 1) allows normal fre-
quency changes with a step frequency of 12.5 kHz.
Table 20. Fractional Mode
Fractional
B144
ON
0
1
OFF
Spurious Suppression
In fractional and direct shift mode the spurious suppression is able by SW wire and SW
impulse.
Table 21. Spurious Suppression by SW Wire
SW Wire
B60
0
OFF
ON
1
18
T4260
4528G–AUDR–12/03
T4260
Table 22. Spurious Suppression by Correction Current Charge Pump
SW Impulse
B61
OFF
0
ON
1
Charge Pump
(AMLF/FMLF)
AMLF/FMLF is the current charge pump output of the PLL. The current can be con-
trolled by setting the Bits 62 and 63. The loop filter has to be designed correspondingly
to the chosen pump current and the internal reference frequency.
During the frequency change, the high-current charge pump (Bit 62) is active to enable
fast frequency changes. After the frequency change, the current will be reduced to guar-
antee a high S/N ratio. The low-current charge pump (Bit 63) is then active. The high
current charge pump can also be switched off by setting the bits of the active HCDEL
register to 0 (Bit 20 and Bit 21 [HCDEL 1] or Bit 22 and Bit 23 [HCDEL 2]).
The current of the high-current charge pump is controlled by Bit 62 as given in Table 23.
Table 23. High-current Charge Pump
High-current Charge Pump
B62
0
1 mA
2 mA
1
The current of the low-current charge pump is controlled by Bit 63 as given in Table 24.
Table 24. Low-current Charge Pump
Low Current Charge Pump
B63
0
50 µA
100 µA
1
External Voltage at AMLF The oscillator (Pin 22) can be switched on/off by Bit 65. It is possible to use the oscillator
buffer as an input or as an output. At the AMLF (Pin 17), an external tuning voltage can
be applied (Bit 65 = 0). If this is not done, the IC operates in standard mode (Bit 65 = 1).
(Oscillator)
The oscillator, oscillator buffer and the AMLF are controlled by the Bits 65 and 64 as
given in Table 25.
Table 25. Oscillator Operating Modes
Oscillator
Oscillator Buffer
AMLF (Pin 17)
INPUT f. DAC’s
AMLF (standard)
AMLF (standard)
B65
0
B64
X
OFF
INPUT
ON
OFF
1
0
ON
OUTPUT
1
1
19
4528G–AUDR–12/03
DAC1, 2 (Pins 1, 2)
For automatic tuner alignment, the DAC1 and DAC2 of the IC can be controlled by set-
ting gain and offset values. The principle of the operation is shown in Figure 7. The gain
is in the range of 0.67 × VTune to 2.09 × VTune. The offset range is +0.98 V to -0.98 V.
For alignment, DAC1 and DAC2 are connected to the varicaps of the preselection filter
and the IF filter. For alignment, offset and gain are set for having the best tuner tracking.
Figure 7. Block Diagram of DAC1, 2
VTUNE
DAC1, 2
Gain
+/-
Offset
The gain of DAC1 and DAC2 has a range of approximately 0.67 × V(VTUNE) to
2.09 × V(TUNE). This range is divided into 255 steps. One step is approximately (2.09-
0.67)/255 = 0.00557 × V(TUNE). The gain of DAC1 can be controlled by the Bits 38 to
45 (20 to 27) and the gain of DAC2 can be controlled by the Bits 66 to Bit 73 (20 to 27) as
given in Table 26.
Table 26. Gain of DAC1, 2
Gain DAC1
Approximately
Decimal
Gain
B45
B44
B43
B42
B41
B40
B39
B38
Gain DAC2
Approximately
Decimal
Gain
B73
0
B72
0
B71
0
B70
0
B69
0
B68
0
B67
0
B66
0
0.6728 × V(TUNE)
0.6783 × V(TUNE)
0.6838 × V(TUNE)
0.6894 × V(TUNE)
...
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
2
0
0
0
0
0
0
1
1
3
...
0
...
0
...
1
...
1
...
1
...
0
...
1
...
0
...
0.9959 × V(TUNE)
...
58
...
...
1
...
1
...
1
...
1
...
1
...
1
...
0
...
1
2.0821 × V(TUNE)
2.0877 × V(TUNE)
2.0932 × V(TUNE)
253
254
255
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
Offset = 64 (intermediate position)
The offset of DAC1 and DAC2 has a range of approximately +0.98 V to -0.99 V. This
range is divided into 127 steps. One step is approximately 1.97 V/127 = 15.52 mV. The
offset of DAC1 can be controlled by the Bits 24 to Bit 30 (20 to 26) and the offset gain of
DAC2 can be controlled by the Bits 52 to Bit 58 (20 to 26) as given in Table 27.
20
T4260
4528G–AUDR–12/03
T4260
Table 27. Offset of DAC1, 2
Offset DAC1
Approximately
B30 B29 B28 B26
B26
B25 B24
B53 B52
Decimal Offset
Offset DAC2
Approximately
B58 B57 B56 B55
B54
0
Decimal Offset
0.9815 V
0.9659 V
0.9512 V
0.9353 V
...
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
1
0
2
0
0
0
0
1
1
3
...
0
...
0
...
0
...
0
...
0
...
0
...
-0.0120 V
...
1
64
...
...
1
...
1
...
1
...
1
...
0
...
1
-0.9576 V
-0.9733 V
-0.9890 V
1
1
1
125
126
127
1
1
1
1
1
0
1
1
1
1
1
1
Gain = 58 (intermediate position)
21
4528G–AUDR–12/03
Permitted DAC
Conditons
The internal operation amplifier of the DACs should not operate with a too high internal
difference voltage at their inputs. This means that a voltage difference higher than 0.5 V
at the internal OP input should be avoided in operation mode. The respective output OP
in the DAC is necessary for the addition and amplification of the tuning voltage (at pin
18) with the desired voltage gain and offset value.
If the tuning voltage reaches a high value e.g. 9 V, with a gain setting of 2 times VTune
and an offset of +1 V, then the output OP of the DAC should reach the (calculated) volt-
age of 19 V. The supply voltage of e.g. 10 V, however, limits the output voltage (of the
DAC) to 10 V maximum.
Due to the (limiting) supply voltage and the internal gain resistance ratio of 6 , the miss-
ing 9 V (calculated voltage - Vs) cause a voltage of 1.5 V at the OP input. This condition
may not remain for a longer period of time.
As long as the calculated DAC output voltage value does not exceed the supply voltage
value by more than 3 V, no damages should occur during the product’s lifetime as the
input voltage of the internal OP input voltage does not exceed 0.5 V.
VTune x DAC gain factor + DAC offset < Vs + 3 V
(9 V x 2 + 1 V) < 10 V + 3 V (condition not allowed)
This means when having a gain factor of 2 and an offset value of 1 V, the tuning voltage
should not exceed 6 V.
Maximum tuning voltage < (VS + 3 V - DAC offset) / DAC gain factor
e.g.: maximum tuing voltage = (10 V + 3 V - 1 V) / 2 = 6 V
It is also possible to reduce the gain or the offset value instead of (or along with) the tun-
ing voltage.
Figure 8. Internal Components of DAC1, 2
VS
DAC1, 2
22
T4260
4528G–AUDR–12/03
T4260
Input/Output Interface Circuits
VTUNE, AMLF and
FMLF (Pins 16-18)
VTUNE is the loop amplifier output of the PLL. The bipolar output stage is a rail-to-rail
amplifier.
Figure 9. Internal Components at VTune, AMLF and FMLF
VS
VS
V5
VTUNE
AMLF/FMLF
EN, DATA, CLK
(Pins 23-25)
All functions can be controlled via a 3-wire bus consisting of Enable, Data and Clock.
The bus is designed for microcontrollers which can operate with 3-V supply voltage.
Details of the data transfer protocol can be found in the chapter “3-Wire Bus
Description”.
Figure 10. Internal Components at Enable, Data and Clock
V5
EN
DATA
CLK
23
4528G–AUDR–12/03
Figure 11. Block Diagram of the PLL Core
14 - BIT
BIT 18
BIT 32
LATCH R - DIV.
SWITCH
HCDEL 1 HCDEL 2
SHIFT 2 BIT
DELAYTIME high
cur. CP
F
ref
AM - LOOP
FILTER
R - DIVIDER
B145
AM / FM
PHASE
DETECTOR
CHARGE
PUMP
AM/FM
FILTER
FM - LOOP
FILTER
N / N+1
DIVIDER
PREAMP
VCO
B62,63
B61
SWITCH N+1, N
ACCU 2 - BIT
SHIFT 2 BIT
MUX N1 N2
B5
2-BIT (LSB)
B60, B144
LATCH N - DIV 1
LATCH N - DIV 2
18 - BIT
18 - BIT
PLL Core Block Diagram The two N-dividers are stored in two 18-bit memory register (LATCH N-DIV) and the
R-divider in a 14-bit memory register (LATCH R-DIV). One of the the two N-dividers
(N1 or N2) can be activated by Bit 5 as active N-divider (with the 18-bit multiplexer
MUX).
Description
The (divider) 2-bit shift mode can be activated with Bit 32 = 0. The N- and R-divider are
shifted two bits to the right in this shift mode. Because the two lowest R-divider bits
(Bit 124 and Bit 125) are 0 they do not have to be evaluated. In opposite to the R-divider
the lowest two N-divider bits (Bit 102 and Bit 103 or Bit 80 and Bit 81, depends on the
active N-divider) are special evaluated in the ACCU block if fractional mode is active
(Bit 144 = 0). The two lowest N- and R-divider bits are also called shift bits.
The SWITCH N+1, N block is steering the division through N or N+1 in the N-divider if
fractional and 2-bit shift mode are active. There is only a division by N if the fractional
mode is deactivated in 2-bit shift mode.
The output signals of the 18-bit N-divider and 14-bit R-divider will be compared in the
PHASEDETECTOR which one activates the sink and source currents of the charge
pumps (CP).
24
T4260
4528G–AUDR–12/03
T4260
There are also two HCDEL registers (for the high current CP delay time) but only one of
them is active. One of the HCDEL registers can be activated by Bit 18. The delay time of
the HCDEL register can be selected with Bit 20 and Bit 21 or Bit 22 and Bit 23). The
current for the high CP (HCCP) can be set by Bit 62 and the current for the low current
CP (LCCP) by Bit 63.
With Bit 145 the AM- or FM-Loopfilter (pin) can be activated. It is also possible to use
the AM-Loopfilter in FM mode (instead of the FM-Loopfilter) or the FM-Loopfilter in AM
mode.
High-speed Tuning
The fractional mode (Bit 144 = 0) in connection with the direct shift mode (Bit 32 = 0)
allows very fast frequency changes with four times the step frequency (50 kHz = 4 ×
fPDF) at low frequency steps (e.g., fPDF = 12.5 kHz). In direct shift mode, the R- and the
N-divider are shifted by 2 bits to the right (this corresponds to a R- and N-divider division
by 4 or a step frequency multiplication by 4).
Due to the 2-bit shift, a faster tuning response time of approximately 1 ms instead of 3-
4 ms for a tune over the whole FM band from 87.5 MHz to 108 MHz is possible with
fPDF = 12.5 kHz.
If the FM receiving frequency is 103.2125 MHz (with e.g. fPDF = 12.5 kHz and
fIF = 10.7 MHz), an N-divider of 9113 and an R-divider of 12 are necessary when using a
reference-frequency (fref) of 150 kHz.
fVCO = fIF + frec = 10.7 MHz + 103.2125 MHz = 113.9125 MHz
fPDF = fVCO / N = fref / R = 113.9125 MHz / 9113 = 150 kHz /12 = 12.5 kHz
An important condition for the use of the fractional mode is an R-divider with an integer
value after the division by 4 (R-dividers have to be a multiple of 4).
After a 2-bit shift (divider division by 4), the R-divider is now 3 (instead of 12) and the
N-divider is 2278.25 (instead of 9113). The new N-divider of 2278.25 is also called ¼
fractional step because the modulo value of the N-divider is 0.25 = ¼. In total, there are
4 different fractional 2-bit shift steps: full, ¼, ½ and ¾ step.
If the fractional mode is switched off (Bit 144 = 1) during direct shift mode (Bit 32 = 0),
the modulo value of the N-divider will be ignored (the new N-divider is then 2278 instead
of 2278.25). This means that the PLL locks on the next lower multiple frequency of
4 × fPDF (in our case fPDF = 12.5 kHz). The new VCO frequency (fVCO) is then 113.9 MHz
(instead of 113.9125 MHz in fractional mode).
Also the PLL has additionally a special fractional logic which allows a good spurious
suppression in the fractional and direct shift mode. Activating the wire switch (Bit 60 = 1)
and the correction charge pump (Bit 60 = 1) the spurious suppression is active.
25
4528G–AUDR–12/03
Charge Pump Current
Settings
Bit 62 (0 = 1 mA; 1 = 2 mA) allows to adjust the high current, which is active during a fre-
quency change (if the delay time of the active HCDEL register is not switched off). A
high charge pump current allows faster frequeny changes. After a frequency change,
the current reduction is reduced (in locked mode) to the low current which is set by bit 63
(0 = 50 µA; 1 = 100 µA). A lower charge pump current guarantees a higher S/N ratio.
The high current charge pump can be switched off by the active HCDEL register bits. In
this case, when HCDEL 1 is active and the bits 20 and 21 are 0 (HCDEL 1 delay time =
off) or HCDEL 2 is active and the bits 22 and 23 are 0 (HCDEL 2 delay time = off), only
the low current charge pump (current) is active in locked and in the frequency change
mode.
AM Prescaler (Divider)
Settings
The AM mixer is used for up-conversion of the AM reception frequency to the IF fre-
quency. Therefore, an AM prescaler is implemented to generate the necessary LO from
the VCO frequency. For the reception of the AM band, different prescaler (divider) set-
tings are possible.
Table 28 lists the AM prescaler (divider) settings and the reception frequencies.
f
VCO = 98.2 MHz to 124 MHz
fIF = 10.7 MHz
rec = fVCO - fIF
f
fVCO = AM prescaler x (frec + fIF)
The following formula can also be useful by AM frequencies higher than 20 MHz:
fVCO = AM prescaler x (frec - fIF)
Table 28. AM Prescaler (Divider) Settings and the Reception Frequencies
Minimum Reception
Frequency [MHz]
Maximum Reception
Divider (AM Prescaler)
no divider
Frequency [MHz]
113.3
51.3
87.5
38.4
Divide by 2
Divide by 3
22.033
13.85
8.94
30.633
20.3
Divide by 4
Divide by 5
14.1
Divide by 6
5.667
3.329
1.575
0.211
0
9.967
7.014
4.8
Divide by 7
Divide by 8
Divide by 9
3.078
1.7
Divide by 10
Note:
The AM Prescaler Divider Settings with fVCO from 98.2 MHz to 124 MHz is only an exam-
ple. The tuning range depends on the tuning diode and the inductor in the VCO circuit.
The tank of the VCO should be designed for a maximum range at pin 18 (VTUNE) of 1.5 V
to VSPLL - 1 V for a good S/N performance.
26
T4260
4528G–AUDR–12/03
T4260
The N- and R- divider can be calculated as following:
N = AM Prescaler × (frec + fIF)/fstep
N = (frec + fIF)/fstep
(AM mode)
(FM mode)
R = fref/fstep
(For all modes)
fVCO = N × fstep
fref = reference oscillator frequency (pin 27)
Example of AM settings:
If the receiving frequency is 0.84 MHz (AM) and the following conditions are:
fref = 4 MHz; fstep = 10 kHz; fIF = 10.7 MHz and an AM-Prescaler of 10 a N-Divider of
11540 and a R-Divider of 400 is necessary.
R = fref/fstep = 4 MHz/10 KHz = 400
N = AM Prescaler × (frec + fIF)/fstep = 10 × (0.84 MHz + 10.7 MHz)/10 KHz = 11540
External Voltage at AMLF By using two ICs, for example, it is possible to operate the AMLF (Pin 17) of the second
IC either with the tuning voltage (Vtune [Pin 18]), the DAC 1 voltage [Pin 1] or the DAC 2
voltage [Pin 2] from the first T4260. For voltage reduction at the AMLF [Pin 17], a volt-
age factor ratio of 100/16 (R1/R2) is required.
(Pin 17)
This means that an applied voltage from 0.5 V at Pin 17 (AMLF) corresponds to a tuning
voltage of 3.625 V. It is recommended to use R1 with 100 kΩ and R2 with 16 kΩ. The
allowed range of R1 is 10 kΩto 1 MΩ and 1.6 kΩ to 160 kΩfor R2.
Figure 12. External Voltage at AMLF (Pin 17)
T4260
Vtune or DAC
R1
R2
AMLF
T4260
The maximum input voltage at the AMLF input (Pin 17) depends on the applied supply
voltage as well as on the gain and offset settings. To avoid any damages during the
product’s lifetime, the following formulas regarding SWAMLF voltage, gain and offset
settings have to be observed (see chapter “Permitted DAC Conditons” on page 22).
VSWAMLF x ([R1 + R2] / R2) x DAC gain factor + DAC offset < VS + 3 V
(R1 + R2) / R2 = 7.25
This means when having a gain factor of 2 and an offset value of 1 V, the applied
SWAMLF voltage should be limited to a voltage lower than 0.83 V.
SWAMLF voltage < (VS + 3 V - DAC offset) / (DAC gain factor × 7.25)
e.g.: maximum SWAMLF voltage = (10 V + 3 V - 1 V) / (2 × 7.25) = 0.83 V
It is also possible to reduce the gain or offset instead (or along with) the SWAMLF
voltage.
27
4528G–AUDR–12/03
Figure 13. Test Circuit
Test Point
100n
1
2
3
4
5
6
7
8
9
DAC1
DAC2
MXFMOB 44
MXFMOA 43
10n
10n
330
FMAGCO RFAGCA1 42
MXFMIA
MXFMIB
GNDRF
VST 41
MXAMOA 40
MXAMOB 39
GNDT 38
VST
10n
3k
MXAMIB
MXAMIA
AMAGCO
VRT 37
10n
100n
330
IFINFM 36
IFINAM 35
IFREF 34
10 IFAGCA2
11 SW2/AGC
2k4
100n
RFAGCA
12
2
RFAGCFM 33
IFAGCA1 32
IFAGCFM 31
IFOUTA 30
IFOUTB 29
GNDPLL 28
REFFREQ 27
VRPLL 26
DATA 25
100k
100k
13 SW1
14 VRVCO
15 VSPLL
16 FMLF
100n
VSPLL
100
10n
100n
5k1
17 AMLF
18 VTUNE
19 OSCGND
20 OSCE
1n
10k
5k6
10n
1n
15p
22p
47p
21 OSCB
CLK 24
BUS
22 OSCBUF
EN 23
10n
10n
28
T4260
4528G–AUDR–12/03
T4260
Figure 14. Application Circuit
P2
P3
GNDT
GNDPLL
C13
IFoutA
Bu2
R2
10uF
180
C4
1u
C7
KF2
KF1
IFoutB
Bu3
R8
R5
5R6
100n
2k2
VST R1
C15
REFFREQ
Bu4
C2
P1 5R6
C1
10u
R3
300
100n
R6
300
F1
100n
C14
C9
DATA
P4
100n
F2
CLK
100n
C3
C6
P5
C5
C8
100n
C10 C11 C12
100n220n100n
EN
P6
220n
100p
47p
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23
1
2
3
4
5
6
C29
7
8
C30
9
10 11 12 13 14 15 16 17 18 19 20 21 22
DAC1
C28
C37 C39
OSCBUF
Bu5
C47 C48
P7
P11 P12 P13
FM AM VT
100n
100n
4u7
2u2 100n
C16 10n
22p 47p
DAC2
P8
C31
12p
C50
C41
OSCB
Bu4
C40
15n
P15
SW1
C17 10n
L2
100uH
100n
C42
1n
C49
6p8
1n
C23 C24
R14
68k
BC 848
T3
C32
6p8
C43
R25
R11
R24
6k2
F5
1n 6p8
C22
CD1
5k1
C25
4n7
F3
C38
L3
2m2
R16
2k7
2n2
68k
100n
R26
100
18p
CD3
BB804
C46
1n
BB804
T4
C44
R9
470
R10 47k
R12
68k
J109
100n
R27
5k6
C45
10u
C21
10n
10p
C20
27p
C19
L1
R17
47
C34
R23
5R6
T1
BFR93A
2u2
F4
C18
10n
220n
VSPLL
BB804
P10
R13
1k
R18
T2
BC848B
P16
CD2
D1 C26
470k
C27
R19
470k
R15
1k
3p9 S391D10n
AMPREIN
AMAGCO
C36
10n
P14
P9
Bu1
D2
L4
S391D
Ant
4u7
C33
R28 R22
3k9 470k
C35
10p
100n
D3
S391D
29
4528G–AUDR–12/03
Ordering Information
Extended Type Number
Package
SSO44
SSO44
Remarks
T4260IL
Tube
T4260ILQ
Taped and reeled
Package Information
9.15
8.65
Package SSO44
Dimensions in mm
18.05
17.80
7.50
7.30
2.35
0.3
0.8
0.25
0.10
0.25
10.50
10.20
16.8
44
23
technical drawings
according to DIN
specifications
1
22
30
T4260
4528G–AUDR–12/03
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Printed on recycled paper.
4528G–AUDR–12/03
相关型号：
T428P156M050AH6110
Tantalum Capacitor, Polarized, Tantalum (dry/solid), 50V, 20% +Tol, 20% -Tol, 15uF, 2824
KEMET
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