T555714-TASY_技术文档

Features

• Contactless Read/Write Data Transmission

• Radio Frequency f_RFfrom 100 kHz to 150 kHz

• e5550 Binary Compatible or T5557 Extended Mode

• Small Size, Configurable for ISO/IEC 11784/785 Compatibility

• 75 pF On-chip Resonant Capacitor (Mask Option)

• 7 × 32-bit EEPROM Data Memory Including 32-bit Password

• Separate 64-bit memory for Traceability Data

• 32-bit Configuration Register in EEPROM to Setup:

– Data Rate

Multifunctional

330-bit

Read/Write RF

Identification IC

• RF/2 to RF/128, Binary Selectable or

• Fixed e5550 Data Rates

– Modulation/Coding

• FSK, PSK, Manchester, Biphase, NRZ

– Other Options

• Password Mode

• Max Block Feature

• Answer-On-Request (AOR) Mode

• Inverse Data Output

T5557

• Direct Access Mode

• Sequence Terminator(s)

• Write Protection (Through Lock-bit per Block)

• Fast Write Method (5 Kbps versus 2 Kbps)

• OTP Functionality

• POR Delay up to 67 ms

1. Description

The T5557 is a contactless R/W IDentification IC (IDIC^®) for applications in the

125 kHz frequency range. A single coil, connected to the chip, serves as the IC’s

power supply and bi-directional communication interface. The antenna and chip

together form a transponder or tag.

The on-chip 330-bit EEPROM (10 blocks, 33 bits each) can be read and written block-

wise from a reader. Block 0 is reserved for setting the operation modes of the T5557

tag. Block 7 may contain a password to prevent unauthorized writing.

Data is transmitted from the IDIC using load modulation. This is achieved by damping

the RF field with a resistive load between the two terminals Coil 1 and Coil 2. The IC

receives and decodes 100% amplitude modulated (OOK) pulse interval encoded bit

streams from the base station or reader.

Rev. 4517I–RFID–11/05

2. System Block Diagram

Figure 2-1. RFID System Using T5557 Tag

Transponder

Power

Data

Reader

Memory

or

Base station

*

Base station

T5557

Mask option

*

3. T5557 – Building Blocks

Figure 3-1. Block Diagram

POR

Modulator

Coil 1

Mode register

Memory

(330-bit

*

EEPROM)

Controller

Test logic

Input register

HV generator

Coil 2

* Mask option

3.1

Analog Front End (AFE)

The AFE includes all circuits which are directly connected to the coil. It generates the IC’s power

supply and handles the bi-directional data communication with the reader. It consists of the fol-

lowing blocks:

• Rectifier to generate a DC supply voltage from the AC coil voltage

• Clock extractor

• Switchable load between Coil 1/Coil 2 for data transmission from tag to the reader

• Field gap detector for data transmission from the base station to the tag

• ESD protection circuitry

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3.2

Data-rate Generator

The data rate is binary programmable to operate at any data rate between RF/2 and RF/128 or

equal to any of the fixed e5550/e5551 and T5554 bitrates (RF/8, RF/16, RF/32, RF/40, RF/50,

RF/64, RF/100 and RF/128).

3.3

3.4

3.5

Write Decoder

HV Generator

DC Supply

This function decodes the write gaps and verifies the validity of the data stream according to the

Atmel e555x write method (pulse interval encoding).

This on-chip charge pump circuit generates the high voltage required for programming of the

EEPROM.

Power is externally supplied to the IDIC via the two coil connections. The IC rectifies and regu-

lates this RF source and uses it to generate its supply voltage.

3.6

3.7

3.8

Power-On Reset (POR)

This circuit delays the IDIC functionality until an acceptable voltage threshold has been reached.

Clock Extraction

The clock extraction circuit uses the external RF signal as its internal clock source.

Controller

The control-logic module executes the following functions:

• Load-mode register with configuration data from EEPROM block 0 after power-on and also

during reading

• Control memory access (read, write)

• Handle write data transmission and write error modes

• The first two bits of the reader to tag data stream are the opcode, e.g., write, direct access or

reset

• In password mode, the 32 bits received after the opcode are compared with the password

stored in memory block 7

3.9

Mode Register

The mode register stores the configuration data from the EEPROM block 0. It is continually

refreshed at the start of every block read and (re-)loaded after any POR event or reset com-

mand. On delivery the mode register is preprogrammed with the value ‘0014 8000’h which

corresponds to continuous read of block 0, Manchester coded, RF/64.

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Figure 3-2. Block 0 Configuration Mapping – e5550 Compatibility Mode

L

1

0

2

1

3

1

4

0

5

6

7

8

0

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

0

Master Key

Data

Modulation

PSK-

CF

MAX-

Note 1), 2)

Bit Rate

BLOCK

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

RF/2

RF/4

RF/8

Res.

RF/8

RF/16

RF/32

RF/40

RF/50

RF/64

RF/100

RF/128

0

Unlocked

Locked

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Direct

PSK1

PSK2

PSK3

FSK1

FSK2

FSK1a

FSK2a

Manchester

Biphase ('50)

Reserved

1) If Master Key = 6 then test mode write commands are ignored

2) If Master Key <> 6 or 9 then extended function mode is disabled

3.10 Modulator

The modulator consists of data encoders for the following basic types of modulation:

Table 3-1.

Mode

Types of e5550-compatible Modulation Modes

Direct Data Output

FSK1a⁽¹⁾

FSK2a⁽¹⁾

FSK1⁽¹⁾

FSK2⁽¹⁾

PSK1⁽²⁾

PSK2⁽²⁾

PSK3⁽²⁾

Manchester

Biphase

NRZ

FSK/8-/5

FSK/8-/10

FSK/5-/8

FSK/10-/8

“0” = rf/8;

“0” = rf/5;

“0” = rf/10;

“1” = rf/5

“1” = rf/10

“1” = rf/8

Phase change when input changes

Phase change on bit clock if input high

Phase change on rising edge of input

“0” = falling edge, “1” = rising edge

“1” creates an additional mid-bit change

“1” = damping on, “0” = damping off

Notes: 1. A common multiple of bitrate and FSK frequencies is recommended.

2. In PSK mode the selected data rate has to be an integer multiple of the PSK sub-carrier

frequency.

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3.11 Memory

The memory is a 330-bit EEPROM, which is arranged in 10 blocks of 33 bits each. All 33 bits of

a block, including the lock bit, are programmed simultaneously.

Block 0 of page 0 contains the mode/configuration data, which is not transmitted during regular-

read operations. Block 7 of page 0 may be used as a write protection password.

Bit 0 of every block is the lock bit for that block. Once locked, the block (including the lock bit

itself) is not re-programmable through the RF field again.

Blocks 1 and 2 of page 1 contain traceability data and are transmitted with the modulation

parameters defined in the configuration register after the opcode “11” is issued by the reader

(see Figure 4-6 on page 10). These tracebility data blocks are programmed and locked by

Atmel.

Figure 3-3. Memory Map

0 1

32

Block 2

Block 1

1

Traceability data

Block 7

Block 6

Block 5

Block 4

Block 3

Block 2

Block 1

Block 0

L

User data or password

User data

Configuration data

32 bits

Not transmitted

3.12 Traceability Data Structure

Blocks 1 and 2 of page 1 contain the traceability data and are programmed and locked by Atmel

during production testing. The most significant byte of block 1 is fixed to “E0”hex, the allocation

class (ACL) as defined in ISO/IEC 15963-1. The second byte is therefore defined as the manu-

facturer’s ID of Atmel (= “15”hex). The following 8 bits are used as IC reference byte (ICR bits 47

to 40). The 3 most significant bits define the IC and/or foundry version of the T5557. The lower

5 bits are by default reset (= 00) as the Atmel standard value. Other values may be assigned on

request to high volume customers as tag issuer identification.

The lower 40 bits of the data encode the traceability information of Atmel and conform to a

unique numbering system. These 40 data bits are divided in two sub-groups, a 5-digit lot ID

number, the binary wafer number (5 bit) concatenated with the sequential die number per wafer.

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Figure 3-4. T5557 Traceability Data Structure

Traceability

12

20

' 557 '

31

32

1

...

12 13 ... 18 19

wafer #

...

die on wafer #

MSN LotID

24 25 ... 32

Block 2

Block 1

LotID

ACL

...

MFC

...

ICR

16 17 ...

8

9

' 41 '

8

Example:

' E0 '

' 15 '

' 00 '

ACL

MFC

ICR

Allocation class as defined in ISO/IEC 15963-1 = E0h

Manufacturer code of Atmel Corporation as defined in ISO/IEC 7816-6 = 15h

IC reference of silicon and/or tag manufacturer

Top 3 bits define IC revision

Lower 5 bits may contain a customer ID code on request

Manufacturer serial number consists of:

5-digit lot number, e.g., “38765”

MSN

LotID

DPW

20 bits encoded as sequential die per wafer number (with top 5 bits = wafer#)

4. Operating the T5557

4.1

Initialization and POR Delay

The Power-On-Reset (POR) circuit remains active until an adequate voltage threshold has been

reached. This in turn triggers the default start-up delay sequence. During this configuration

period of about 192 field clocks, the T5557 is initialized with the configu-ration data stored in

EEPROM block 0. During initialization of the configuration block 0, all T55570x variants the load

damping is active permanently (see Figure 4-5 on page 10). The T55571x types (without damp-

ing option) achieve a longer read range based on the lower activation field strength.

If the POR-delay bit is reset, no additional delay is observed after the configuration period. Tag

modulation in regular-read mode will be observed about 3 ms after entering the RF field. If the

POR delay bit is set, the T5557 remains in a permanent damping state until 8190 internal field

clocks have elapsed.

T_INIT= (192 + 8190 × POR delay) × T_C≈ 67 ms ; T_C= 8 µs at 125 kHz

Any field gap occurring during this initialization phase will restart the complete sequence. After

this initialization time the T5557 enters regular-read mode and modulation starts automatically

using the parameters defined in the configuration register.

4.2

Tag to Reader Communication

During normal operation, the data stored within the EEPROM is cycled and the Coil 1, Coil 2 ter-

minals are load modulated. This resistive load modulation can be detected at the reader module.

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4.3

Regular-read Mode

In regular-read mode data from the memory is transmitted serially, starting with block 1, bit 1, up

to the last block (e.g., 7), bit 32. The last block which will be read is defined by the mode param-

eter field MAXBLK in EEPROM block 0. When the data block addressed by MAXBLK has been

read, data transmission restarts with block 1, bit 1.

The user may limit the cyclic datastream in regular-read mode by setting the MAXBLK between

0 and 7 (representing each of the 8 data blocks). If set to 7, blocks 1 through 7 can be read. If

set to 1, only block 1 is transmitted continously. If set to 0, the contents of the configuration block

(normally not transmitted) can be read. In the case of MAXBLK = 0 or 1, regular-read mode can

not be distinguished from block-read mode.

Figure 4-1. Examples for Different MAXBLK Settings

Block 1

Loading block 0

Block 4

Block 5

Block 1

Block 2

Block 1

MAXBLK = 5

MAXBLK = 2

MAXBLK = 0

0

Block 1

Block 2

Block 1

0

Loading block 0

Block 0

0

Loading block 0

Every time the T5557 enters regular- or block-read mode, the first bit transmitted is a logical “0”.

The data stream starts with block 1, bit 1, continues through MAXBLK, bit 32, and cycles contin-

uously if in regular-read mode.

Note:

This behavior is different from the original e555x and helps to decode PSK-modulated data.

4.4

Block-read Mode

With the direct access command, the addressed block is repetitively read only. This mode is

called block-read mode. Direct access is entered by transmitting the page access opcode (“10”

or “11”), a single “0” bit and the requested 3-bit block address when the tag is in normal mode.

In password mode (PWD bit set), the direct access to a single block needs the valid 32-bit pass-

word to be transmitted after the page access opcode whereas a “0” bit and the 3-bit block

address follow afterwards. In case the transmitted password does not match with the contents of

block 7, the T5557 tag returns to the regular-read mode.

Note:

A direct access to block 0 of page 1 will read the configuration data of block 0, page 0.

A direct access to bock 3 to 7 of page 1 reads all data bits as zero.

4.5

e5550 Sequence Terminator

The sequence terminator ST is a special damping pattern which is inserted before the first block

and may be used to synchronize the reader. This e5550-compatible sequence terminator con-

sists of 4 bit periods with underlaying data values of “1”. During the second and the fourth bit

period, modulation is switched off (Manchester encoding – switched on). Biphase modulated

data blocks need fixed leading and trailing bits in combination with the sequence terminator to

be identified reliable.

The sequence terminator may be individually enabled by setting of mode bit 29 (ST = “1”) in the

e5550-compatibility mode (X-mode = “0”).

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In the regular-read mode, the sequence terminator is inserted at the start of each MAXBLK-lim-

ited read data stream.

In block-read mode – after any block-write or direct access command – or if MAXBLK was set to

0 or 1, the sequence terminator is inserted before the transmission of the selected block.

Especially this behavior is different to former e5550-compatible ICs (T5551, T5554).

Figure 4-2. Read Data Stream with Sequence Terminator

No terminator

Block 1

Block 2

MAXBLK

Block 1

Block 2

Regular read mode

Sequence terminator

Block 1

Block 2

MAXBLK

Block 1

Block 2

ST = on

Figure 4-3. e5550-compatible Sequence Terminator Waveforms

Bit period

Last bit

Data 1

Sequence

First Bit

Modulation

off (on)

Modulation

off (on)

Waveforms per different modulation types

bit 1 or 0

V_CoilPP

Manchester

FSK

Sequence terminator not suitable for Biphase or PSK modulation

4.6

Reader to Tag Communication

Data is written to the tag by interrupting the RF field with short field gaps (on-off keying) in accor-

dance with the e5550 write method. The time between two gaps encodes the “0/1” information to

be transmitted (pulse interval encoding). The duration of the gaps is usually 50 µs to 150 µs. The

time between two gaps is nominally 24 field clocks for a “0” and 54 field clocks for a “1”. When

there is no gap for more than 64 field clocks after a previous gap, the T5557 exits the write

mode. The tag starts with the command execution if the correct number of bits were received. If

there is a failure detected the T5557 does not continue and will enter regular-read mode.

4.7

Start Gap

The initial gap is referred to as the start gap. This triggers the reader to tag communication. Dur-

ing this mode of operation, the receive damping is permanently enabled to ease gap detection.

The start gap may need to be longer than subsequent gaps in order to be detected reliably.

A start gap will be accepted at any time after the mode register has been loaded (≥ 3 ms). A sin-

gle gap will not change the previously selected page (by former opcode “10” or “11”).

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Figure 4-4. Start of Reader to Tag Communication

Read mode

Write mode

d₁

d_n

S_gap

W_gap

Table 4-1.

Parameters

Start gap

Write Data Decoding Scheme

Remark

Symbol

S_gap

W_gap

d₀

Min.

Max.

50

Unit

FC

10

8

Write gap

Normal write mode

30

“0” data

“1” data

16

48

31

Write data in normal mode

d₁

63

4.8

Write Data Protocol

The T5557 expects to receive a dual bit opcode as the first two bits of a reader command

sequence. There are three valid opcodes:

• The opcodes “10” and “11” precede all block write and direct access operations for page 0

and page 1

• The RESET opcode “00” initiates a POR cycle

• The opcode “01” precedes all test mode write operations. Any test mode access is ignored

after master key (bits 1 to 4) in block 0 has been set to “6”. Any further modifications of the

master key are prohibited by setting the lock bit of block 0 or the OTP bit.

Writing has to follow these rules:

• Standard write needs the opcode, the lock bit, 32 data bits and the 3-bit address (38 bits

total)

• Protected write (PWD bit set) requires a valid 32-bit password between opcode and data,

address bits

• For the AOR wake-up command an opcode and a valid password are necessary to select

and activate a specific tag

Note:

The data bits are read in the same order as written.

If the transmitted command sequence is invalid, the T5557 enters regular-read mode with the

previously selected page (by former opcode “10” or “11”).

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Figure 4-5. Complete Writing Sequence

Read mode

Write mode

Read mode

Block

address

T55571x

Opcode

Block data

Programming

T555701

Start gap

Lock bit

Block 0 loading

POR

Figure 4-6. T5557 Command Formats

OP

Standard write

L

1

0

1

Data

32

2

1

Addr

0

1p*

10

Protected write

Password

32

L

0

Data

32

2

Addr

0

Password

AOR (wake-up command)

Direct access (PWD = 1)

Direct access (PWD = 0)

Page 0/1 regular read

Reset command

1p*

2

Addr

0

1p*

2

Addr

0

1p*

00

* p = page selector

4.9

Password

When password mode is active (PWD = 1), the first 32 bits after the opcode are regarded as the

password. They are compared bit by bit with the contents of block 7, starting at bit 1. If the com-

parison fails, the T5557 will not program the memory, instead it will restart in regular-read mode

once the command transmission is finished.

Note:

In password mode, MAXBLK should be set to a value below 7 to prevent the password from being

transmitted by the T5557.

Each transmission of the direct access command (two opcode bits, 32 bits password, “0” bit plus

3 address bits = 38 bits) needs about 18 ms. Testing all possible combinations (about 4.3 billion)

takes about two years.

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4.10 Answer-On-Request (AOR) Mode

When the AOR bit is set, the T5557 does not start modulation in the regular-read mode after

loading configuration block 0. The tag waits for a valid AOR data stream (“wake-up command”)

from the reader before modulation is enabled. The wake-up command consists of the opcode

(“10”) followed by a valid password. The selected tag will remain active until the RF field is

turned off or a new command with a different password is transmitted which may address

another tag in the RF field.

Table 4-2.

T5557 — Modes of Operation

Behavior of Tag after Reset Command or POR

PWD

AOR

De-activate Function

Answer-On-Request (AOR) mode:

• Modulation starts after wake-up with a matching password

• Programming needs valid password

Command with non-matching password

deactivates the selected tag

1

0

--

Password mode:

• Modulation in regular-read mode starts after reset

• Programming and direct access needs valid password

1

0

Normal mode:

• Modulation in regular-read mode starts after reset

• Programming and direct access without password

Figure 4-7. Answer-On-Request (AOR) Mode

T55571x

T55570x

Modulation

V_{Coil1 - Coil2}

No modulation

because AOR = 1

Loading block 0

POR

AOR wake-up command (with valid PWD)

Figure 4-8. Coil Voltage after Programming of a Memory Block

V_{Coil 1 - Coil 2}

POR/

Read programmed

memory block

or

5.6 ms

Read block 1..MAXBLK

(Regular-read mode)

Write data to tag

Programming and

data verification

(Block-read mode)

single

gap

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Figure 4-9. Anticollision Procedure Using AOR Mode

Reader

Tag

init tags with

AOR = "1" , PWD = "1"

Field OFF => ON

POWER ON RESET

read configuration

wait for t_W> 2.5 ms

enter AOR mode

wait for OPCODE + PWD

=> "wake up command"

"Select a single tag"

send OPCODE + PWD

=> "wake up command"

Receive damping ON

NO

Password correct ?

YES

send block 1...MAXBLK

decode data

NO

all tags read ?

YES

EXIT

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4.11 Programming

When all necessary information has been received by the T5557, programming may proceed.

There is a clock delay between the end of the writing sequence and the start of programming.

Typical programming time is 5.6 ms. This cycle includes a data verification read to grant secure

and correct programming. After programming was executed successfully, the T5557 enters

block-read mode transmitting the block just programmed (see Figure 4-8 on page 11).

Note:

This timing and behavior is different from the e555x-family predecessors.

5. Error Handling

Several error conditions can be detected to ensure that only valid bits are programmed into the

EEPROM. There are two error types, which lead to two different actions.

5.1

Errors During Writing

The following detectable errors could occur during writing data into the T5557:

• Wrong number of field clocks between two gaps (i.e., not a valid “1” or “0” pulse stream)

• Password mode is activated and the password does not match the contents of block 7

• The number of bits received in the command sequence is incorrect

Valid bit counts accepted by the T5557 are:

Password write

Standard write

AOR wake up

Direct access with PWD

Direct access

70 bits

38 bits

34 bits

38 bits

6 bits

(PWD = 1)

(PWD = 0)

(PWD = 1)

(PWD = 0)

Reset command

Page 0/1 regular-read

2 bits

If any of these erroneous conditions were detected, the T5557 enters regular-read mode, start-

ing with block 1 of the page defined in the command sequence.

5.2

Errors Before/During Programming

If the command sequence was received successfully, the following error could still prevent

programming:

• The lock bit of the addressed block is set already

• In case of a locked block, programming mode will not be entered. The T5557 reverts to block-

read mode continuously transmitting the currently addressed block.

If the command sequence is validated and the addressed block is not write protected, the new

data will be programmed into the EEPROM memory. The new state of the block write protection

bit (lock bit) will be programmed at the same time accordingly.

Each programming cycle consists of 4 consecutive steps: erase block, erase verification

(data = “0” ), programming, write verification (corresponding data bits = “1”).

• If a data verification error is detected after an executed data block programming, the tag will

stop modulation (modulation defeat) until a new command is transmitted.

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Figure 5-1. T5557 Functional Diagram

Power-on Reset

* p = page selector

AOR = 1

Setup Modes

AOR Mode

AOR = 0

Regular-read Mode

Page 0 or 1

Page 0

addr = 1 .. maxblk

Block-read Mode

gap

Start

Gap

addr = current

gap

command mode

Direct access OP (1p)*

OP(1p)*

Commanddecode

OP(11..)

single gap

Modulation

Page 1

Page 0

Defeat

OP(10..)

OP(00)

OP(01)

Write

OP(1p)*

Test-mode

if master key

<> 6

Reset

to page 0

Write

fail

data = old

Number of bits

fail

ok

data = old

data = new

Password check

Lock bit check

Data verification failed

Program & Verify

6. T5557 in Extended Mode (X-mode)

In general, the block 0 setting of the master key (bits 1 to 4) to the value “6” or “9” together with

the X-mode bit will enable the extended mode functions.

• Master key = “92: Test mode access and extended mode are both enabled.

• Master key = “6”: Any test mode access will be denied but the extended mode is still enabled.

Any other master key setting will prevent the activation of the T5557 extended mode options,

even when the X-mode bit is set.

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6.1

6.2

Binary Bit-rate Generator

In extended mode the data rate is binary programmable to operate at any data rate between

RF/2 and RF/128 as given in the formula below.

Data rate = RF/(2n+2)

OTP Functionality

If the OTP bit is set to “1”, all memory blocks are write protected and behave as if all lock bits are

set to 1. If the master key is set to “6” additionally, the T5557 mode of operation is locked forever

(= OTP functionality).

If the master key is set to “9”, the test-mode access allows the re-configuration of the tag again.

Figure 6-1. Block 0 — Configuration Map in Extended Mode (X-mode)

L

1

2

0

3 4

5

0

6

0

7 8 9 10 11 12 13 14 15 16 17 18 19 2021 22 23 2425 26 27 2829 30 31 32

0

1

0

1

Master Key

Modulation

PSK-

CF

MAX-

n5 n4 n3 n2 n1 n0

Data Bit Rate

RF/(2n+2)

Direct

Note 1), 2)

BLOCK

0

1

0

1

0

1

RF/2

RF/4

RF/8

Res.

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

PSK1

PSK2

0

Unlocked

Locked

PSK3

1

FSK1

FSK2

Manchester

Biphase ('50) 1

Biphase ('57) 1

1) If Master Key = 6 and bit 15 set, then test-mode access is disabled and extended mode is active

2) If Master Key = 9 and bit 15 set, then extended mode is enabled

Table 6-1.

Mode

T5557 Types of Modulation in Extended Mode

Direct Data Output Encoding

Inverse Data Output Encoding

FSK1⁽¹⁾

FSK2⁽¹⁾

FSK/5-/8

“0” = RF/5; “1” = RF/8

“0” = RF/10; “1” = RF/8

FSK/8-/5

“0” = RF/8; “1” = RF/5

“0” = RF/8; “1” = RF/10

(= FSK1a)

(= FSK2a)

FSK/10-/8

FSK/8-/10

PSK1⁽²⁾

PSK2⁽²⁾

PSK3⁽²⁾

Phase change when input changes

Phase change on bit clock if input low

Phase change on falling edge of input

“1” = falling edge, “1” = rising edge on mid-bit

“0” creates an additional mid-bit change

“1” creates an additional mid-bit change

“0” = damping on, “1” = damping off

Phase change on bit clock if input high

Phase change on rising edge of input

“0” = falling edge, “1” = rising edge on mid-bit

“1” creates an additional mid-bit change

“0” creates an additional mid-bit change

“1” = damping on, “0” = damping off

Manchester

Biphase 1 (’50)

Biphase 2 (’57)

NRZ

Notes: 1. A common multiple of bitrate and FSK frequencies is recommended.

2. In PSK mode the selected data rate has to be an integer multiple of the PSK sub-carrier frequency.

15

4517I–RFID–11/05

6.3

Sequence Start Marker

Figure 6-2. T5557 Sequence Start Marker in Extended Mode

Sequence Start Marker

10

Block n

Block 1

01

Block n

10 Block n

01

Block n

10

Block n

01

10

Block-read mode

Block 2

MAXBLK 01 Block 1

Block 2

MAXBLK

Regular-read mode

The T5557 sequence start marker is a special damping pattern, which may be used to synchro-

nize the reader. The sequence start marker consists of two bits (“01” or “10”) which are inserted

as header before the first block to be transmitted if the bit 29 in extended mode ist set. At the

start of a new block sequence, the value of the two bits is inverted.

6.4

Inverse Data Output

The T5557 supports in its extended mode (X-mode) an inverse data output option. If inverse

data is enabled, the modulator as shown in Figure 6-3 works on inverted data (see Table 6-1 on

page 15). This function is supported for all basic types of encoding.

Figure 6-3. Data Encoder for Inverse Data Output

PSK1

PSK2

PSK3

Intern out

data

D

Direct/NRZ

Data output

Sync

R

XOR

Mux

FSK1

FSK2

Data clock

CLK

Manchester

Biphase

Inverse data output

Modulator

16

T5557

4517I–RFID–11/05

T5557

6.5

Fast Write

In the optional fast write mode the time between two gaps is nominally 12 field clocks for a “0”

and 27 field clocks for a “1”. When there is no gap for more than 32 field clocks after a previous

gap, the T5557 will exit the write mode. Please refer to Table 6-2 and Figure 4-3 on page 8.

Table 6-2.

Parameters

Start gap

Fast Write Data Decoding Schemes

Remark

–

Symbol

S_gap

Wn_gap

Wf_gap

d₀

Min.

10

8

Max.

50

Unit

FC

Normal write mode

Fast write mode

30

Write gap

8

20

“0” data

“1” data

“0” data

“1” data

16

48

8

31

Write data in normal

mode

d₁

63

d₀

15

Write data in fast

mode

d₁

24

31

17

4517I–RFID–11/05

7. Absolute Maximum Ratings

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating

only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.

Parameters

Symbol

Value

Unit

Maximum DC current into Coil 1/Coil 2

I_coil

20

mA

Maximum AC current into Coil 1/Coil 2

f = 125 kHz

I_{coil p}

P_tot

20

mA

mW

V

Power dissipation (dice)

(free-air condition, time of application: 1 s)

100

Electrostatic discharge maximum to

MIL-Standard 883 C method 3015

V_max

4000

Operating ambient temperature range

T_amb

T_stg

–40 to +85

°C

Storage temperature range (data retention reduced)

–40 to +150

8. Electrical Characteristics

T_amb= +25°C; f_coil= 125 kHz; unless otherwise specified

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

1

RF frequency range

f_RF

100

125

150

kHz

T_amb= 25°C⁽¹⁾

(see Figure 6-9 on page 23)

2.1

1.5

2

3

4

µA

V

T

Supply current

(without current consumed Read – full temperature

2.2

2.3

3.1

3.2

I_DD

Q

by the external LC tank

circuit)

range

Programming full

temperature range

25

3.6

40

POR threshold

(50 mV hysteresis)

3.2

4.0

V_clamp

Coil voltage (AC supply)

Read mode and write

command⁽²⁾

Program EEPROM⁽²⁾

V_{coil pp}

6

8

V

3.3

4

V_clamp

3

V

ms

V

Q

T

Start-up time

V_{coil pp}= 6V

t_startup

V_clamp

2.5

5

Clamp voltage

10 mA current into Coil 1/2

17

23

6.1

V_coilpp= 6V on test circuit

generator and modulation

ON⁽³⁾

V _{mod pp}

4.2

600

–6

4.8

V

T

6.2 Modulation parameters

6.3

I _{mod pp}

400

µA

T

Thermal stability

V

_mod/T_amb

mV/°C

Q

*) Type means: T: directly or indirectly tested during production; Q: guaranteed based on initial product qualification data

Notes: 1. I_DDmeasurement setup R = 100 kΩ; V_CLK= V_coil= 5V: EEPROM programmed to 00 ... 000 (erase all); chip in modulation

defeat. I_DD= (V_OUTmax– V_CLK)/R

2. Current into Coil 1/Coil 2 is limited to 10 mA. The damping circuitry has the same structure as the e5550. The damping

characteristics are defined by the internally limited supply voltage (= minimum AC coil voltage)

3. V_modmeasurement setup: R = 2.3 kΩ; V_CLK= 3V; setup with modulation enabled (see Figure 8-1 on page 25).

4. Since EEPROM performance is influenced by assembly processes, Atmel confirms the parameters for DOW (tested dice

on uncutted wafer) delivery.

5. The tolerance of the on-chip resonance capacitor C_ris ±10% at 3σ over whole production. The capacitor tolerance is

±3% at 3σ on a wafer basis.

6. The tolerance of the microcodule resonance capacitor C_ris ±5% at 3σ over whole production.

24

T5557

4517I–RFID–11/05

T5557

8. Electrical Characteristics (Continued)

T_amb= +25°C; f_coil= 125 kHz; unless otherwise specified

No. Parameters

Test Conditions

Symbol

Min.

Typ.

Max.

Unit

Type*

From last command gap to

re-enter read mode

(64 + 648 internal clocks)

Erase all / Write all⁽⁴⁾

Top = 55°C⁽⁴⁾

Top = 150°C⁽⁴⁾

7

Programming time

Endurance

T_prog

5

5.7

6

ms

T

8

n_cycle

t_retention

C_r

100000

10

Cycles

Years

hrs

Q

9.1

20

50

9.2 Data retention

96

T

Q

9.3

Top = 250°C⁽⁴⁾

Mask option⁽⁵⁾

24

hrs

10 Resonance capacitor

70

78

86

pF

T

11.1

Capacitance tolerance T_amb

Temperature coefficient

C_r

313.5

TBD

330

TBD

346.5

TBD

pF

T

Microdule capacitor

11.2

TBD

parameters

11.3

*) Type means: T: directly or indirectly tested during production; Q: guaranteed based on initial product qualification data

Notes: 1. I_DDmeasurement setup R = 100 kΩ; V_CLK= V_coil= 5V: EEPROM programmed to 00 ... 000 (erase all); chip in modulation

defeat. I_DD= (V_OUTmax– V_CLK)/R

2. Current into Coil 1/Coil 2 is limited to 10 mA. The damping circuitry has the same structure as the e5550. The damping

characteristics are defined by the internally limited supply voltage (= minimum AC coil voltage)

3. V_modmeasurement setup: R = 2.3 kΩ; V_CLK= 3V; setup with modulation enabled (see Figure 8-1 on page 25).

4. Since EEPROM performance is influenced by assembly processes, Atmel confirms the parameters for DOW (tested dice

on uncutted wafer) delivery.

5. The tolerance of the on-chip resonance capacitor C_ris ±10% at 3σ over whole production. The capacitor tolerance is

±3% at 3σ on a wafer basis.

6. The tolerance of the microcodule resonance capacitor C_ris ±5% at 3σ over whole production.

Figure 8-1. Measurement Setup for I_DDand V_mod

R

BAT68

-

Coil 1

750

V_OUTmax

+

750

Coil 2

Substrate

BAT68

25

4517I–RFID–11/05

9. Ordering Information⁽²⁾

T5557

a b M c c - x x x Package

Drawing

- DDW

- DDT

- DBW

- Dice on wafer, 6” un-sawn wafer, thickness 300 µm

- Dice in tray (waffle pack), thickness 300 µm

- Dice on solder bumped wafer, thickness 390 µm

Sn63Pb37 on 5 µm Ni/Au, height 70 µm

Figure 10-2 on page 28

Figure 10-3 on page 28

- TASY

- PAE

- SO8 package (lead-free)

Figure 10-6 on page 31

Figure 10-4 on page 29

- MOA2 mocro-module (lead-free)

Customer ID⁽¹⁾

- Atmel standard (corresponds to “0”)

- Customer “X” unique ID code⁽¹⁾

- 2 pads withput on-chip C

M01

11

Figure 10-1 on page 27

Figure 10-2 on page 28

Figure 10-4 on page 29

Figure 10-1 on page 27

14

- 4 pads with on-chip 75 pF

15

- Micro-module with 330 pF

01

- 2 pads without C, damping during initialization

Notes: 1. Unique customer ID code programming according to Figure 5 is linked to a minimum order quantity of 1 Mio parts per year.

2. For available order codes refer to Atmel Sales/Marketing.

9.1

9.2

Ordering Examples (Recommended)

T555711-DDW

Tested dice on unsawn 6” wafer, thickness 300 µm, no on-chip capacitor,

no damping during POR initialisation; especially for ISO 11784/785 and

access control applications

Available Order Codes

T555711-DDW, DDT, TASY

T555714-DDW, DBW, TASY

T555715-PAE

New order codes will be done on customer request if order quantities are upside 250k pieces.

26

T5557

4517I–RFID–11/05

T5557

10. Package Information

Figure 10-1. 2 Pad Layout for Wire Bonding

Dimensions in µm

124

994

149.5

87

125

C2

497

27

4517I–RFID–11/05

Figure 10-2. 4 Pad Flip-chip Version with 70 µm Solder Bumps

Dimensions in µm

124

994

82

97

60

157

107

100

C2

497

Figure 10-3. Solder Bump on NiAu

PbSn

70 µm

Ni

Passivation

AL bondpad

28

T5557

4517I–RFID–11/05

T5557

Figure 10-4. Wafer Map

Die: 0.894 × 0.864, Step: 0.994 × 0.934, N: 14 × 7, Frame Step: 13.916 × 15.878

> Shift-ASML = [0.3; –6.9] : 15539 dice, 87 shots (11 cols × 9 rows)

> Shift-CANON/ALARM/SEM = [0.3; –6.9] – W2 = [–13.152; 6.9] – W1 = [–6.648; 6.9]

29

4517I–RFID–11/05

10.1 Failed Die Identification

Every die on the wafer not passing Atmel test sequence is marked with inch.

The inch dot specification:

• Dot size: 200 µm

• Position: center of die

• Color: black

Figure 10-5. NOA2 Micromodule

9.5±0.03

+0.02

4.625

4.75

1.42±0.05

0.03 A B

31.83

25.565

21.815

2±0.05

Note 1

15.915

12.165

6.265

2.515

B

technical drawings

according to DIN

specifications

0

1.585

A

Dimensions in mm

X

2.375

4.8±0.05

X5:1

0.03 A

0.38-0.04

Note 3

Note:

5.15±0.03

Note 2

1. Reject hole by device testing

2. Punching cutline

0.09-0.01

R1.5±0.03

recommendation for singulation

3. Total package thickness

excludes punching burr

4. Module dimension

after galvanic seperation

R0.2 max.

R1.1±0.03 (4x)

Drawing refers to following types: Micromodule

5.06±0.03

Note 4

Drawing-No.: 6.549-5034.01-4

Issue: prel.; 25.09.02

Subcontractor: NedCard

30

T5557

4517I–RFID–11/05

T5557

Figure 10-6. Shipping Reel

41,4 to

Ø329,6

max 43,0

120˚ (3x)

2,3

R1,14

Ø13

Ø171

Ø175

16,7

2

2,2

31

4517I–RFID–11/05

Figure 10-7. SO8 Package

Package SO8

Dimensions in mm

5.2

4.8

5.00

4.85

3.7

1.4

0.25

0.2

0.4

3.8

0.10

1.27

6.15

5.85

3.81

8

5

technical drawings

according to DIN

specifications

1

4

Figure 10-8. Pinning SO8

COIL2

NC

1

2

3

4

8

7

6

5

COIL1

NC

11. Revision History

Please note that the following page numbers referred to in this section refer to the specific revision

mentioned, not to this document.

Revision No.

History

4517I-RFID-11/05

• Legal notice changed

• Put datasheet in a new template

• First page: Pb-free logo added

4517H-RFID-08/05

• Page 26: Ordering Information changed

32

T5557

4517I–RFID–11/05

Atmel Corporation

Atmel Operations

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Europe

Atmel Sarl

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

Tel: (41) 26-426-5555

Fax: (41) 26-426-5500

Fax: 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Datacom

Avenue de Rochepleine

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

Tel: (33) 2-40-18-18-18

Fax: (33) 2-40-18-19-60

BP 123

38521 Saint-Egreve Cedex, France

Tel: (33) 4-76-58-30-00

Fax: (33) 4-76-58-34-80

Asia

Room 1219

Chinachem Golden Plaza

77 Mody Road Tsimshatsui

East Kowloon

Hong Kong

Tel: (852) 2721-9778

Fax: (852) 2722-1369

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

Tel: (33) 4-42-53-60-00

Fax: (33) 4-42-53-60-01

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906, USA

Tel: 1(719) 576-3300

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

PURPOSE, OR NON-INFRINGEMENT. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT, CONSEQUENTIAL, PUNITIVE, SPECIAL OR INCIDEN-

TAL DAMAGES (INCLUDING, WITHOUT LIMITATION, DAMAGES FOR LOSS OF PROFITS, BUSINESS INTERRUPTION, OR LOSS OF INFORMATION) ARISING OUT

OF THE USE OR INABILITY TO USE THIS DOCUMENT, EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. Atmel makes no

representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications

and product descriptions at any time without notice. Atmel does not make any commitment to update the information contained herein. Unless specifically provided

otherwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’s products are not intended, authorized, or warranted for use

as components in applications intended to support or sustain life.

tered trademarks or trademarks of Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

Printed on recycled paper.

4517I–RFID–11/05


型号：	T555714-TASY
厂家：	ATMEL
描述：	Telecom Circuit, 1-Func, PDSO8, LEAD FREE, SOP-8 电信光电二极管电信集成电路
文件：	总33页 (文件大小：733K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

T555714-TASY [ATMEL]

相关型号：

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T555714M01-DDT

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T555714M01-PAE

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T555714M01-TAS

T555715-PAE

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