T5754 [ATMEL]
UHF ASK/FSK TRANSMITTER; 超高频ASK / FSK发射器
| 型号： | T5754 |
| 厂家： | 
ATMEL |
| 描述： | UHF ASK/FSK TRANSMITTER |
| 文件： | 总13页 (文件大小：214K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Integrated PLL Loop Filter
• ESD Protection (4 kV HBM/200 V MM; Except Pin 2: 4 kV HBM/100 V MM) also at
ANT1/ANT2
• High Output Power (7.5 dBm) with Low Supply Current (9.0 mA)
• Modulation Scheme ASK/ FSK
– FSK Modulation is Achieved by Connecting an Additional Capacitor Between the
XTAL Load Capacitor and the Open Drain Output of the Modulating Microcontroller
• Easy to Design-in Due to Excellent Isolation of the PLL from the PA and Power Supply
• Single Li-cell for Power Supply
• Supply Voltage 2.0 V to 4.0 V in the Temperature Range of -40°C to 85°C/125°C
• Package TSSOP8L
• Single-ended Antenna Output with High Efficient Power Amplifier
• CLK Output for Clocking the Microcontroller
UHF ASK/FSK
Transmitter
• One-chip Solution with Minimum External Circuitry
• 125°C Operation for Tire Pressure Systems
T5754
Description
The T5754 is a PLL transmitter IC which has been developed for the demands of RF
low-cost transmission systems at data rates up to 32 kBaud. The transmitting
frequency range is 429 MHz to 439 MHz. It can be used in both FSK and ASK
systems.
Figure 1. System Block Diagram
UHF ASK/FSK
Remote control transmitter
UHF ASK/FSK
Remote control receiver
1 Li cell
U3741B/
U3745B/
T5743/
T5754
Demod.
1...3
Control
XTO
Encoder
T5744
PLL
ATARx9x
IF Amp
Keys
Antenna Antenna
XTO
VCO
PLL
Power
amp.
LNA
VCO
Rev. 4511F–RKE–07/04
Pin Configuration
Figure 2. Pinning TSSOP8L
1
2
3
4
8
7
6
5
CLK
PA_ENABLE
ANT2
ENABLE
GND
T5754
VS
XTAL
ANT1
Pin Description
Pin
Symbol
Function
Configuration
VS
Clock output signal for micro con roller
The clock output frequency is set by the
crystal to fXTAL/4
100
CLK
1
CLK
100
PA_ENABLE
50k
Uref = 1.1 V
Switches on power amplifier, used for
ASK modulation
2
PA_ENABLE
20 µA
ANT1
3
4
ANT2
ANT1
Emitter of antenna output stage
Open collector antenna output
ANT2
VS
VS
1.5k
1.2k
5
XTAL
Connection for crystal
XTAL
182 µA
6
7
VS
Supply voltage
Ground
See ESD protection circuitry (see Figure 8 on page 8)
See ESD protection circuitry (see Figure 8 on page 8)
GND
ENABLE
200k
8
ENABLE
Enable input
2
T5754
4511F–RKE–07/04
T5754
Figure 3. Block Diagram
T5754
Power up/down
CLK
ENABLE
8
f
1
4
f
32
PA_ENABLE
GND
7
2
PFD
CP
ANT2
VS
6
3
LF
ANT1
XTAL
5
PA
VCO
XTO
4
PLL
General Description
This fully integrated PLL transmitter allows particularly simple, low-cost RF miniature
transmitters to be assembled. The VCO is locked to 32 fXTAL hence a 13.56 MHz crystal
is needed for a 433.92 MHz transmitter. All other PLL and VCO peripheral elements are
integrated.
The XTO is a series resonance oscillator so that only one capacitor together with a
crystal connected in series to GND are needed as external elements.
The crystal oscillator together with the PLL needs typically <1 ms until the PLL is locked
and the CLK output is stable. There is a wait time of ≥ 1 ms until the CLK is used for the
microcontroller and the PA is switched on.
The power amplifier is an open-collector output delivering a current pulse which is nearly
independent from the load impedance. The delivered output power is hence controllable
via the connected load impedance.
This output configuration enables a simple matching to any kind of antenna or to 50 Ω. A
high power efficiency of η= Pout/(IS,PA VS) of 36% for the power amplifier results when
an optimized load impedance of ZLoad = (166 + j223) Ω is used at 3 V supply voltage.
3
4511F–RKE–07/04
Functional
Description
If ENABLE = L and the PA_ENABLE = L, the circuit is in standby mode consuming only
a very small amount of current so that a lithium cell used as power supply can work for
several years.
With ENABLE = H the XTO, PLL and the CLK driver are switched on. If PA_ENABLE
remains L only the PLL and the XTO is running and the CLK signal is delivered to the
microcontroller. The VCO locks to 32 times the XTO frequency.
With ENABLE = H and PA_ENABLE = H the PLL, XTO, CLK driver and the power
amplifier are on. With PA_ENABLE the power amplifier can be switched on and off,
which is used to perform the ASK modulation.
ASK Transmission
FSK Transmission
The T5754 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥1 ms, then
the CLK signal can be taken to clock the microcontroller and the output power can be
modulated by means of Pin PA_ENABLE. After transmission PA_ENABLE is switched
to L and the microcontroller switches back to internal clocking. The T5754 is switched
back to standby mode with ENABLE = L.
The T5754 is activated by ENABLE = H. PA_ENABLE must remain L for t ≥1 ms, then
the CLK signal can be taken to clock the microcontroller and the power amplifier is
switched on with PA_ENABLE = H. The chip is then ready for FSK modulation. The
microcontroller starts to switch on and off the capacitor between the XTAL load capaci-
tor and GND with an open-drain output port, thus changing the reference frequency of
the PLL. If the switch is closed, the output frequency is lower than if the switch is open.
After transmission PA_ENABLE is switched to L and the microcontroller switches back
to internal clocking. The T5754 is switched back to standby mode with ENABLE = L.
The accuracy of the frequency deviation with XTAL pulling method is about ±25% when
the following tolerances are considered.
Figure 4. Tolerances of Frequency Modulation
~
VS
CStray2
CStray1
XTAL
CM LM
RS
C4
C0
Crystal equivalent circuit
C5
CSwitch
Using C4 = 9.2 pF ± 2%, C5 = 6.8 pF ± 5%, a switch port with CSwitch = 3 pF ± 10%, stray
capacitances on each side of the crystal of CStray1 = CStray2 = 1 pF ± 10%, a parallel
capacitance of the crystal of C0 = 3.2 pF ± 10% and a crystal with CM = 13 fF ± 10%, an
FSK deviation of ±21 kHz typical with worst case tolerances of ±16.3 kHz to ±28.8 kHz
results.
CLK Output
An output CLK signal is provided for a connected microcontroller, the delivered signal is
CMOS compatible if the load capacitance is lower than 10 pF.
Clock Pulse Take-over
The clock of the crystal oscillator can be used for clocking the microcontroller. Atmel’s
ATARx9x has the special feature of starting with an integrated RC-oscillator to switch on
the T5754 with ENABLE = H, and after 1 ms to assume the clock signal of the transmis-
sion IC, so that the message can be sent with crystal accuracy.
4
T5754
4511F–RKE–07/04
T5754
Output Matching and Power
Setting
The output power is set by the load impedance of the antenna. The maximum output
power is achieved with a load impedance of ZLoad,opt = (166 + j223) Ω. There must be a
low resistive path to VS to deliver the DC current.
The delivered current pulse of the power amplifier is 9 mA and the maximum output
power is delivered to a resistive load of 465 Ω if the 1.0 pF output capacitance of the
power amplifier is compensated by the load impedance.
An optimum load impedance of:
ZLoad = 465 Ω || j/(2 × π 1.0 pF) = (166 + j223) Ω thus results for the maximum output
power of 7.5 dBm.
The load impedance is defined as the impedance seen from the T5754’s ANT1, ANT2
into the matching network. Do not confuse this large signal load impedance with a small
signal input impedance delivered as input characteristic of RF amplifiers and measured
from the application into the IC instead of from the IC into the application for a power
amplifier.
Less output power is achieved by lowering the real parallel part of 465 Ω where the
parallel imaginary part should be kept constant.
Output power measurement can be done with the circuit of Figure 5. Note that the com-
ponent values must be changed to compensate the individual board parasitics until the
T5754 has the right load impedance ZLoad,opt = (166 + j223) Ω. Also the damping of the
cable used to measure the output power must be calibrated out.
Figure 5. Output Power Measurement
VS
C1 = 1n
L1 = 33n
Power
meter
ANT1
ANT2
Z = 50 Ω
ZLopt
C2 = 2.2p
Rin
50 Ω
~
Application Circuit
For the supply-voltage blocking capacitor C3 a value of 68 nF/X7R is recommended
(see Figure 6 on page 6 and Figure 7 on page 7). C1 and C2 are used to match the loop
antenna to the power amplifier where C1 typically is 8.2 pF/NP0 and C2 is 6 pF/NP0
(10 pF + 15 pF in series); for C2 two capacitors in series should be used to achieve a
better tolerance value and to have the possibility to realize the ZLoad,opt by using stan-
dard valued capacitors.
C1 forms together with the pins of T5754 and the PCB board wires a series resonance
loop that suppresses the 1st harmonic, hence the position of C1 on the PCB is important.
Normally the best suppression is achieved when C1 is placed as close as possible to the
Pins ANT1 and ANT2.
The loop antenna should not exceed a width of 1.5 mm, otherwise the Q-factor of the
loop antenna is too high.
L1 ([50 nH to 100 nH) can be printed on PCB. C4 should be selected that the XTO runs
on the load resonance frequency of the crystal. Normally, a value of 12 pF results for a
15 pF load-capacitance crystal.
5
4511F–RKE–07/04
Figure 6. ASK Application Circuit
VDD
S1
BPXY
BPXY
BPXY
ATARx9x
1
VS
VSS
S2
20
OSC1
7
BPXY
T5754
Power up/down
CLK
ENABLE
8
f
1
4
f
32
PA_ENABLE
GND
2
7
PFD
C3
CP
LF
C2
VS
6
ANT2
3
VS
Loop
C1
Antenna
XTAL
ANT1
XTAL
PA
VCO
XTO
4
5
C4
PLL
L1
VS
6
T5754
4511F–RKE–07/04
T5754
Figure 7. FSK Application Circuit
ATARx9x
S1
S2
VDD
BPXY
BPXY
BPXY
1
VS
VSS
20
BP42/T2O
18
OSC1
7
BPXY
T5754
Power up/down
CLK
ENABLE
8
f
1
4
f
32
PA_ENABLE
GND
7
2
PFD
C3
CP
LF
C2
VS
6
ANT2
3
VS
Loop
C1
Antenna
C5
C4
XTAL
ANT1
XTAL
5
4
PA
VCO
XTO
PLL
L1
VS
7
4511F–RKE–07/04
Figure 8. ESD Protection Circuit
VS
ANT1
ANT2
CLK
PA_ENABLE
XTAL
ENABLE
GND
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
Minimum
Maximum
Unit
V
Supply voltage
VS
5
100
Power dissipation
Junction temperature
Storage temperature
Ambient temperature
Input voltage
Ptot
mW
°C
°C
°C
V
Tj
Tstg
150
-55
-55
-0.3
125
Tamb
125
(VS + 0.3)(1)
VmaxPA_ENABLE
Note:
1. If VS + 0.3 is higher than 3.7 V, the maximum voltage will be reduced to 3.7 V.
Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient
RthJA
170
K/W
8
T5754
4511F–RKE–07/04
T5754
Electrical Characteristics
VS = 2.0 V to 4.0 V, Tamb = -40° C to 125° C unless otherwise specified.
Typical values are given at VS = 3.0 V and Tamb = 25° C. All parameters are referred to GND (pin 7).
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Power down
VENABLE < 0.25 V, -40° C to 85°C
VPA-ENABLE < 0.25 V, -40° C to +125° C
350
7
nA
µA
nA
Supply current
IS_Off
VPA-ENABLE < 0.25 V, 25°C
<10
(100% correlation tested)
Power up, PA off, VS = 3 V,
VENABLE > 1.7 V, VPA-ENABLE < 0.25 V
Supply current
Supply current
Output power
IS
3.7
9
4.8
11.6
10
mA
mA
Power up, VS = 3.0 V,
IS_Transmit
PRef
VENABLE > 1.7 V, VPA-ENABLE > 1.7 V
VS = 3.0 V, Tamb = 25°C,
f = 433.92 MHz, ZLoad = (166 + j233) Ω
5.5
7.5
dBm
T
amb = -40°C to +85°C,
Output power variation for the full
temperature range
VS = 3.0 V
VS = 2.0 V
∆PRef
∆PRef
-1.5
-4.0
dB
dB
Tamb = -40°C to +125°C,
Output power variation for the full VS = 3.0 V
∆PRef
∆PRef
-2.0
-4.5
dB
dB
temperature range
VS = 2.0 V
Out = PRef + ∆PRef
P
Achievable output-power range
Selectable by load impedance
POut_typ
0
7.5
dBm
fCLK = f0/128
Load capacitance at pin CLK = 10 pF
fO ± 1× fCLK
fO ± 4 × fCLK
Spurious emission
-55
-52
dBc
dBc
other spurious are lower
f
XTO = f0/32
fXTAL = resonant frequency of the XTAL,
CM ≤10 fF, load capacitance selected
Oscillator frequency XTO
(= phase comparator frequency)
fXTO
accordingly
Tamb = -40°C to +85°C
Tamb = -40°C to +125°C
-30
-40
fXTAL
+30
+40
ppm
ppm
PLL loop bandwidth
250
-116
-86
kHz
Referred to fPC = fXT0,
25 kHz distance to carrier
Phase noise of phase comparator
In loop phase noise PLL
Phase noise VCO
-110
-80
dBc/Hz
25 kHz distance to carrier
dBc/Hz
at 1 MHz
at 36 MHz
-94
-125
-90
-121
dBc/Hz
dBc/Hz
Frequency range of VCO
fVCO
429
439
MHz
MHz
V
Clock output frequency (CMOS
microcontroller compatible)
f0/128
V0h
V0l
VS × 0.8
Voltage swing at Pin CLK
CLoad ≤10 pF
VS × 0.2
V
Series resonance R of the crystal
Capacitive load at Pin XT0
Rs
110
7
Ω
pF
Note:
1. If VS is higher than 3.6 V, the maximum voltage will be reduced to 3.6 V.
9
4511F–RKE–07/04
Electrical Characteristics (Continued)
VS = 2.0 V to 4.0 V, Tamb = -40° C to 125° C unless otherwise specified.
Typical values are given at VS = 3.0 V and Tamb = 25° C. All parameters are referred to GND (pin 7).
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
Duty cycle of the modulation signal =
50%
FSK modulation frequency rate
0
32
kHz
Duty cycle of the modulation signal =
50%
ASK modulation frequency rate
ENABLE input
0
32
kHz
Low level input voltage
High level input voltage
Input current high
VIl
VIh
IIn
0.25
V
V
µA
1.7
20
Low level input voltage
High level input voltage
Input current high
VIl
VIh
IIn
0.25
VS
5
V
V
µA
(1)
PA_ENABLE input
1.7
Note:
1. If VS is higher than 3.6 V, the maximum voltage will be reduced to 3.6 V.
10
T5754
4511F–RKE–07/04
T5754
Ordering Information
Extended Type Number
Package
Remarks
T5754-6AQ
TSSOP8L
Taped and reeled, Marking: T574
Package Information
11
4511F–RKE–07/04
Revision History
Please note that the following page numbers referred to in this section refer to the
specific revision mentioned, not to this document.
Changes from Rev.
4511E-RKE-10/03
to Rev.
1. Abs. Max. Ratings table (page 8): row “Input voltage” added
2. Abs. Max. Ratings table (page 8): table note 1 added
3. El. Char. table (page 10): row “PA_ENABLE input“ changed
4. El. Char. table (page 10): table note 1 added
4511F-RKE-07/04
5. Ordering Information table (page 10): Remarks changed
12
T5754
4511F–RKE–07/04
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Printed on recycled paper.
4511F–RKE–07/04
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