T87C5111-ICUCV [ATMEL]
Microcontroller, 8-Bit, OTPROM, 66MHz, CMOS, PDSO24, SSOP-24;型号: | T87C5111-ICUCV |
厂家: | ATMEL |
描述: | Microcontroller, 8-Bit, OTPROM, 66MHz, CMOS, PDSO24, SSOP-24 可编程只读存储器 微控制器 光电二极管 |
文件: | 总84页 (文件大小:941K) |
中文: | 中文翻译 | 下载: | 下载PDF数据表文档文件 |
T80C5111
Low-pin-count 8-bit microcontroller with A/D converter
1. Description
The T80C5111 is a high performance ROM/OTP version the same CPU power at a divided by two oscillator
of the 80C51 8-bit microcontroller in Low Pin Count frequency. The prescaler allows to decrease CPU and
package.
peripherals clock frequency.
The T80C5111 retains all the features of the standard The fully static design of the T80C5111 allows to reduce
80C51 with 4 Kbytes ROM/OTP program memory, 256 system power consumption by bringing the clock
bytes of internal RAM, a 8-source , 4-level interrupt frequency down to any value, even DC, without loss of
system, an on-chip oscillator and two timer/counters.
data.
The T80C5111 is dedicated for analog interfacing The T80C5111 has 3 software-selectable modes of
applications. For this, it has an 10-bit, 8 channels A/D reduced activity for further reduction in power
converter and a five channels Programmable Counter consumption. In the idle mode the CPU is frozen while
Array.
the peripherals are still operating. In the quiet mode, the
A/D converter only is operating. In the power-down
mode the RAM is saved and all other functions are
inoperative. Two oscillators source, crystal and RC,
provide a versatile power management.
In addition, the T80C5111 has a Hardware Watchdog
Timer with its own low power oscillator, a versatile
serial
channel
that
facilitates
multiprocessor
communication (EUART) with an independent baud rate
generator, a SPI serial bus controller and a X2 speed The T80C5111 is proposed in low pin count packages.
improvement mechanism. The X2 feature allows to keep Port 0 and Port 2 (address / data busses) are not available .
2. Features
•
80C51 Compatible
•
Dual system clock
•
•
•
Three I/O ports
•
Crystal or ceramic oscillator with hardware set
up (32 KHz or 33/40 MHz)
Two 16-bit timer/counters
256 bytes RAM
•
•
•
Internal RC oscillator (12 MHz)
Programmable prescaler
•
•
4 Kbytes ROM/OTP program memory with 64 bytes
encryption array and 3 security levels.
Active oscillator during reset defined by hardware
set up
High-Speed Architecture
•
Timer 0 subclock mode for Real Time Clock.
•
•
•
33MHz @ 5V (66 MHz equivalent)
20MHz @ 3V (40 MHz equivalent)
•
•
Programmable counter array with High speed output,
Compare / Capture, Pulse Width Modulation and
Watchdog timer capabilities
X2 Speed Improvement capability (6 clocks/
machine cycle)
Interrupt Structure with:
•
•
•
10-bit, 8 channels A/D converter
•
•
8 Interrupt sources,
Voltage reference for A/D & external analog
4 interrupt priority levels
Hardware Watchdog Timer with integrated low
power oscillator (20µA).
•
Power Control modes:
•
•
•
Idle mode
•
•
Programmable I/O mode: standard C51, input only,
push-pull, open drain.
Power-down mode
Power-off Flag, Power fail detect, Power on Reset
Asynchronous port reset, Power On Reset, Power
fail Detect
•
•
Power supply: 2.7 to 5.5V
o
Temperature ranges: Commercial (0 to 70 C) and
Industrial (-40 to 85 C)
•
•
Full duplex Enhanced UART with baud rate generator
SPI, master/slave mode
o
Rev. B - November 10, 2000
1
Preliminary
T80C5111
•
Package: SSOP16, SO24, DIL24, (SSOP24, SO20, under evaluation)
3. Block Diagram
(3)
(3)
(3)
(3)
(1) (1)
(2) (2)
(2)
XTAL1
Xtal
Osc
ROM /OTP
4 K *8
(2)
RAM
256
x8
RC
Osc
Watch
Dog
PCA
SPI
EUART
BRG
XTAL2
C51
CORE
IB-bus
RC
Osc
CPU
Parallel I/O Ports
Timer 0
Timer 1
INT
Ctrl
Vref
generator
A/D
Converter
Port 3 Port 4
Port 1
(2) (3)
(2) (3)
(2)
(3)
(1): Alternate function of Port 1
(2): Alternate function of Port 3
(3): Alternate function of Port 4
2
Rev. B - November 10, 2000
Preliminary
T80C5111
4. alias SFR Mapping
The Special Function Registers (SFRs) of the T80C5111 belongs to the following categories:
•
•
•
•
•
•
•
•
•
C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
I/O port registers: P1, P3, P4, P1M1, P1M2, P3M1, P3M2, P4M1, P4M2
Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1
Serial I/O port registers: SADDR, SADEN, SBUF, SCON, BRL, BDRCON
Power and clock control registers: CKCON0, CKCON1, OSCCON, CKSEL, PCON, CKRL
Interrupt system registers: IE, IE1, IPL0, IPL1, IPH0, IPH1
WatchDog Timer: WDTRST, WDTPRG
SPI: SPCON, SPSTA, SPDAT
PCA: CCAP0L, CCAP1L, CCAP2L, CCAP3L, CCAP4L, CCAP0H, CCAP1H, CCAP2H, CCAP3H,
CCAP4H, CCAPM0, CCAPM1, CCAPM2, CCAPM3, CCAPM4, CL, CH, CMOD, CCON
•
ADC: ADCCON, ADCCLK, ADCDATH, ADCDATL, ADCF
Table 1. SFR Addresses and Reset Values
0/8
1/9
CH
2/A
3/B
4/C
5/D
6/E
7/F
CCAP0H
CCAP1H
CCAP2H
CCAP3H
CCAP4H
F8h
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
9Fh
97h
0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
B
ADCLK
ADCON
ADDL
ADDH
ADCF
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
0000 0000
0000 0000
0000 0000
XXXXXX00
0000 0000
0000 0000
CL
CCAP0L
CCAP1L
CCAP2L
CCAP3L
CCAP4L
CONF
0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 1111 111X
ACC
0000 0000
P1M2
P3M2
P4M2
0000 0000
0000 0000
0000 0000
CCON
00X0 0000
CMOD
CCAPM0
CCAPM1
CCAPM2
CCAPM3
CCAPM4
X000 0000
00XX X000
X000 0000
X000 0000
X000 0000
X000 0000
PSW
0000 0000
P1M1
P3M1
P4M1
0000 0000
0000 0000
0000 0000
P4
SPCON
SPSTA
SPDAT
1111 1111
0001 0100
XXXXXXXX XXXX XXXX
IPL0
0000 0000
SADEN
0000 0000
P3
IE1
IPL1
IPH1
IPH0
X000 0000
1111 1111
0000 0000
0000 0000
0000 0000
IE0
0000 0000
SADDR
0000 0000
CKCON1
XXXX XXX0
AUXR1
WDRST
WDTPRG
0000 0000
XXXXXXX0
0000 0000
SCON
SBUF
BRL
BDRCON
0000 0000
0000 0000 XXXX XXXX 0000 0000
P1
CKRL
1111 1111
1111 1111
TCON
0000 0000
TMOD
TL0
TL1
TH0
TH1
CKCON0
X000X000
8Fh
87h
0000 0000
0000 0000
0000 0000
0000 0000
0000 0000
SP
DPL
DPH
CKSEL
OSCCON
PCON
0000 0111
0000 0000
0000 0000
XXXX XXXC XXXX XXCC 00X1 0000
0/8
1/9
2/A
3/B
4/C
5/D 6/E 7/F
Notes: "C", value defined by the configuration byte, see Section “Configuration byte”, page 10
Rev. B - November 10, 2000
3
Preliminary
T80C5111
5. Pin Configuration
P4.4/MISO/AIN4
24
23
22
1
2
P4.3/INT1/AIN3
P4.2/SS/AIN2
P4.1/AIN1/T1
P4.4/MISO/AIN4
24
23
22
1
2
P4.3/INT1/AIN3
P4.2/SS/AIN2
P4.1/AIN1/T1
P4.5/MOSI/AIN5
P4.6/SPSCK/AIN6
P4.7/AIN7
P4.5/MOSI/AIN5
P4.6/SPSCK/AIN6
VREF
3
4
3
4
21 P4.0/AIN0
21 P4.0/AIN0
P3.0/RxD
20
VREF
5
6
SO24
P3.0/RxD
20
VSS
5
6
SSOP24*
P3.1/TxD
19
P3.1/TxD
VSS
19
AVSS
P1.2/ECI
18
7
8
P1.2/ECI
18
VCC
P3.6/RST/VPP
P3.5/XTAL2
P3.4/XTAL1
P1.7/CEX4
7
8
DIL24
AVCC
VCC
P1.3/CEX0
17
16
15
14
13
P1.3/CEX0
17
P1.4/CEX1
9
P1.4/CEX1
9
16
15
14
13
P3.6/RST/VPP
P3.5/XTAL2
P3.4/XTAL1
10
11
12
P1.5/CEX2
P3.2/INT0
P3.3/T0
10
11
12
P1.5/CEX2
P3.2/INT0
P3.3/T0
P1.6/CEX3
P1.6/CEX3
P4.4/MISO/AIN4
P4.5/MOSI/AIN5
20
1
2
P4.2/SS/AIN2
P4.1/AIN1/T1
P4.0/AIN0
P4.4/AIN4
16
15
14
1
2
P4.1/AIN1/T1
19
18
P4.0/AIN0
P3.0/RxD
P4.6/AIN6
VREF
P4.6/SPSCK/AIN6
VREF
3
4
3
4
27 P3.0/RxD
13 P3.1/TxD
VSS
P3.1/TxD
26
VSS
P1.3/CEX0
12
5
6
VCC
5
6
SO20*
SSOP16
P1.3/CEX0
P1.4/CEX1
VCC
15
P3.6/RST/VPP
11
P1.4/CEX1
14
P1.5/CEX2
13
P3.2/INT0
12
P3.2/INT0
10
P3.3/T0
9
P3.6/RST/VPP
P3.5/XTAL2
P3.4/XTAL1
P1.6/CEX3
7
8
7
8
P3.5/XTAL2
P3.4/XTAL1
9
P3.3/T0
10
11
* Under evaluation
TYPE
I
MNEMONIC
NAME AND FUNCTION
V
Ground: 0V reference
SS
Power Supply: This is the power supply voltage for normal, idle and power-
down operation.
V
I
CC
VREF : A/D converter positive reference input, output of the internal voltage
reference
VREF
I/O
I/O
Port 1: Port 1 is an 6-bit programmable I/O port .See Section 9, page 21 for a
description of I/O ports.
P1.2-P1.7
Alternate functions for Port 1 include:
I/O
I/O
I/O
I/O
I/O
I/O
ECI (P1.2): External Clock for the PCA
CEX0 (P1.3): Capture/Compare External I/O for PCA module 0
CEX1 (P1.4): Capture/Compare External I/O for PCA module 1
CEX2 (P1.5): Capture/Compare External I/O for PCA module 2
CEX3 (P1.6): Capture/Compare External I/O for PCA module 3
CEX4 (P1.7): Capture/Compare External I/O for PCA module 4
4
Rev. B - November 10, 2000
Preliminary
T80C5111
P3.0-P3.6
I/O
Port 3: Port 3 is an 7-bit programmable I/O port with internal pull-ups. See
Section 9, page 21 for a description of I/O ports.
Port 3 also serves the special features of the 80C51 family, as listed below.
RXD (P3.0): Serial input port
I/O
I/O
I/O
I/O
TXD (P3.1): Serial output port
INT0 (P3.2): External interrupt 0
T0 (P3.3): Timer 0 external input
XTAL1 (P3.4): Input to the inverting oscillator amplifier and input to the internal
clock generator circuits, selected by hardware set up
I/O
I/O
a
XTAL2 (P3.5): Output from the inverting oscillator amplifier, selected by
hardware set up
RST/Vpp (P3.6 is not implemented on first version): Reset/Programming
Supply Voltage:
A low on this pin for two machine cycles while the oscillator is running, resets
the device. An internal diffused resistor to V permits a power-on reset using
cc
I
only the internal ( selected by hardware set up) or an external capacitor to V
SS.
This pin also receives the 12V programming pulse which will start the EPROM
programming and the manufacturer test modes.
Port 4: Port 4 is an 8-bit programmable I/O port with internal pull-ups. See
Section 9, page 21 for a description of I/O ports.
P4.0-P4.7
I/O
Port 4 is also the input port of the Analog to digital converter
I/O
I/O
AIN0 (P4.0): A/D converter input 0
AIN1 (P4.1): A/D converter input 1
T1: Timer 1 external input
AIN2 (P4.2): A/D converter input 2
SS: Slave select input of the SPI controller
I/O
I/O
I/O
I/O
AIN3 (P4.3): A/D converter input 3
INT1: External interrupt 1
AIN4 (P4.4): A/D converter input 4
MISO: Master IN, Slave OUT of the SPI controller
AIN5 (P4.5): A/D converter input 5
MOSI: Master OUT, Slave IN of the SPI controllers
AIN6 (P4.6): A/D converter input 6
SPSCK: Clock I/O of the SPI controlle
I/O
I/O
AIN7 (P4.7): A/D converter input 7
a. Hardware set up :
+Configuration bits programmed with the code for ROM version
+Configuration bits for EPROM version
Rev. B - November 10, 2000
5
Preliminary
T80C5111
6. Clock system
6.1. Overview
The T80C5111 oscillator system provides a reliable clocking system with full mastering of speed versus CPU
power trade off. Several clocks sources are possible:
•
•
•
•
•
External clock input
High speed crystal or ceramic oscillator
Low speed crystal oscillator
Integrated high speed RC oscillator
The low speed RC oscillator of the watchdog is a backup clocking source when no clock are selected in active
or idle modes.
The selected clock source can be divided by 2-512 before clocking the CPU and the peripherals. When X2 function
is set, the CPU need 6 clock periods per cycle.
Active oscillator at reset is defined by bits in a configuration byte programmed on an OTP programmer or by
metal mask.
Clocking is controlled by several SFR registers : OSCON, CKCON0, CKCON1, CKRL.
6.2. Blocks description
The T80C5111 includes the following oscillators:
•
•
•
Crystal oscillator, with two possible gains optimized for 32 kHz or 33 MHz.
Integrated high speed RC oscillator, with typical frequency of 12 MHz
Integrated low speed, low power RC oscillator, with typical frequency of 200 kHz; this oscillator is used to
clock the hardware watchdog and as back up oscillator when the CPU receives no clock signal in active or
idle modes.
6.2.1. Crystal oscillator : OSCA
The crystal oscillator uses two external pins, XTAL1 for input and XTAL2 for output.
XT_SP in configuration byte allows to select between two possible gains optimized for 32 kHz or 33 MHz. Both
crystal and ceramic resonnators can be used.
OSCAEN in OSCCON register is an enable signal for the crystal oscillator or the external oscillator input.
When the crystal oscillator is not selected, XTAL1 can be used as a standard C51 I/O port, and X2 can be used
as a standard C51 I/O port.
6.2.2. Integrated high speed RC oscillator : OSCB
The high speed RC oscillator do not need any external component; its typical frequency is 12 MHz. Note that the
on chip oscillator has a +-25% frequency tolerance and for that reason may not be suitable for use in some applications.
OSCBEN in OSCCON register is an enable signal for the high speed RC oscillator.
6
Rev. B - November 10, 2000
Preliminary
T80C5111
6.2.3. Integrated low speed, low power RC oscillator : OSCC
The low speed, low power RC oscillator is used to clock the hardware watchdog and do not need any external
component; its typical frequency is 200 kHz.
This oscillator is also used as back up oscillator when the CPU receive no clock signal in active or idle modes.
RCLF_OFF is the configuration bit used to switch on or off the low speed RC oscillator.
Note that the on chip oscillator has a +-25% frequency tolerance and for that reason may not be suitable for use
in some applications.
6.2.4. Clock selector
CKS bit in CKS register is used to select from crystal to RC oscillator.
OSCBEN bit in OSCCON register is used to enable the RC oscillator.
OSCAEN bit in OSCCON register is used to enable the crystal oscillator or the external oscillator input.
If both oscillators are disabled, the low speed oscillator, OSCC is used as a backup source for the CPU and the
peripherals.
This feature provides a stand alone low frequency mode which can be activated when needed.
6.2.5. Clock prescaler
Before supplying the CPU and the peripherals, the main clock is divided by a factor to 2 to 512, as defined by
the CKRL register. The CPU needs from 12 to 256*12 clock periods per instruction. This allows:
•
•
To accept any cyclic ratio to be accepted on XTAL1 input.
To reduce the CPU power consumption.
The X2 bit allows to bypass the clock prescaler ; in this case, the CPU need only 6 clock periods per machine
cycle. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%
Rev. B - November 10, 2000
7
Preliminary
T80C5111
6.3. Functional Block diagram
Timer 0 clock
:128
Sub Clock
Reload
ResetB
XT_SP
1
0
WD clock
A/D clock
Ckrl
Xtal1
Xtal2
Xtal_Osc
OSCA
1
0
Mux OscOut
+
8-bit
Prescaler-Divider
CkAdc
0
1
RCLF_OFF
Filter
OSCAEN
OSCBEN
1
0
Peripherals clock
PwdOsc
CkOut
CkIdle
CKS
RC_Osc
OSCB
Cpu clock
Ck
X2
PwdRC
RCLF_Osc
OSCC
OSCBEN
OSCAEN
Pwd
Quiet
Idle
RCLF_OFF
Figure 1. Functional block diagram
6.4. Operating modes
6.4.1. Reset :
•
An hardware RESET select Xtal_Osc or RC_Osc depending on the RST_OSC configuration bit
6.4.2. Functional modes :
6.4.2.1. NORMAL MODES :
•
CPU and Peripherals clock depend on the software selection using CKCON0, CKCON1, CKSEL and CKRL
registers
•
•
CKS bit selects either Xtal_Osc or RC_Osc
CKRL register determines the frequency of the selected clock, unless X2 bit is set.
In this case the prescaler/divider is not used, so CPU core needs only 6-clock period per machine cycle.
According to the value of the peripheral X2 individual bit, each peripherals need 6 or 12 clock period per
instructions.
•
It is always possible to switch dynamicaly by software from Xtal_Osc to RC_Osc, and vice versa by changing
CKS bit, a synchronization cell allowing to avoid any spike during transition.
8
Rev. B - November 10, 2000
Preliminary
T80C5111
6.4.2.2. IDLE MODES :
•
•
IDLE modes are achieved by using any instruction that writes into PCON.0 sfr
IDLE modes A and B depend on previous software sequence, prior to writing into PCON.0 register :
•
•
•
IDLE MODE A : Xtal_Osc is running (OSCAEN = 1) and selected (CKS = 1)
IDLE MODE B : RC_Osc is running (OSCBEN = 1) and selected (CKS = 0)
The unused oscillator Xtal_Osc or RC_Osc can be stopped by software by clearing OSCAEN or OSCBEN
respectively.
•
•
•
Exit from IDLE mode is acheived by Reset, or by activation of an enabled interrupt.
In both case, PCON.0 is cleared by hardware.
Exit from IDLE modes will leave the ocillators control bits OSCAEN, OSCBEN and CKS unchanged.
6.4.2.3. POWER DOWN MODES :
•
•
POWER DOWN modes are achieved by using any instruction that writes into PCON.1 sfr
Exit from POWER DOWN mode is acheived either by an harware Reset, by an external interruption.
•
•
By RST signal : The CPU will restart in the mode defined by RST_OSC.
By INT0 or INT1 interruptions, if enabled. The ocillators control bits OSCAEN, OSCBEN and CKS will
not be changed, so the selected oscillator before entering into Power-down will be activated.
RCLF
PD
IDLE
CKS OSCBEN OSCAEN
Selected Mode
Comment
_OFF
0
X
0
0
X
0
1
1
1
0
0
0
X
X
0
1
0
X
1
NORMAL MODE A
INVALID
OSCA: XTAL clock
no active clock
0
0
RESCUE MODE
NORMAL MODE B,
INVALID
OSCC: Low speed RC clock active
OSCB: high speed RC clock
0
0
1
X
X
0
X
1
X
0
X
0
0
0
0
RESCUE MODE
OSCC: Low speed RC clock active
The CPU is off, OSCA supplies the
peripherics
0
0
1
1
1
1
0
X
1
1
X
1
X
X
0
IDLE MODE A
IDLE MODE B
The CPU is off, OSCB supplies the
peripherics
POWER DOWN MODE The CPU and peripherics are off, but
X
X
X
with WD
OSCC is still running for WD
The CPU is off, OSCA and OSCB are
1
X
X
X
X
1
TOTAL POWER DOWN stopped
OSCC is stopped
6.4.2.4. Prescaler Divider :
•
An hardware RESET selects the prescaler divider :
•
•
•
CKRL = FFh: internal clock = OscOut / 2 (Standard C51 feature)
X2 = 0,
SEL_OSC signal selects Xtal_Osc or RC_Osc, depending on the value of the RST_OSC configuration bit.
•
After Reset, any value between FFh down to 00h can be written by software into CKRL sfr in order to divide
frequency of the selected oscillator:
•
•
CKRL = 00h : minimum frequency = OscOut / 512
CKRL = FFh : maximum frequency = OscOut / 2
Rev. B - November 10, 2000
9
Preliminary
T80C5111
•
A software instruction which set X2 bit desactivates the precaler/divider, so the internal clock is either Xtal_Osc
or RC_Osc depending on SEL_OSC bit.
6.5. Timer 0 : Clock Inputs
CkIdle
:6
0
1
Timer 0
T0 pin
0
1
Control
Sub Clock
C/T
TMOD
SCLKT0
OSCCON
Gate
INT0
TR0
Figure 2. Timer 0 : Clock Inputs
The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock. This allow to perform a Real
Time Clock function.
SCLKT0 = 0 : Timer 0 uses the standard T0 pin as clock input ( Standard mode )
SCLKT0 = 1 : Timer 0 uses the special Sub Clock as clock input.
When the subclock input is selected for Timer 0 and the crystal oscillator is selected for CPU and peripherals, the
CKRL prescaler must be set to FF (division factor 2) in order to assure a proper count on Timer 0.
With a 32 kHz crystal, the timer interrupt can be set from 1/256 to 256 seconds to perform a Real Time Clock
(RTC) function. The power consumption will be very low as the CPU is in idle mode at 32 KHz most of the time.
When more CPU power is needed, the internal RC oscillator is activated and used by the CPU and the others
peripherals.
6.6. Registers
6.6.1. Configuration byte
The configuration byte is a special register. Its content is defined by the diffusion mask in the ROM version or
is rerad or written by the OTP programmer in the OTP version. This register can also be accessed as a read only
register.
CONF - Configuration byte (EFh)
7
6
5
4
3
2
1
0
LB1
LB2
LB3
RST_OSC
XT_SP
RST_EXT
OSCC_OFF
Bit
Number
7:5
Bit
Mnemonic
Description
-
Program memory lock bits
See chapter program memory for the definition of these bits..
10
Rev. B - November 10, 2000
Preliminary
T80C5111
Bit
Number
4
Bit
Mnemonic
Description
RST_OSC Selected oscillator at reset
This bit is used to define the value of some bits controlling the oscillator activity at reset:
1: The crystal oscillator is sectected and active
0: The RC oscillator is selected; it is also active if the WDRC is inactive.
3
2
1
XT_SP
Crystal oscillator speed
This bit is used to define the performance of the crystal oscillator.
1: High speed, up to 33 MHz
0: Low speed, low power, optimised for 32 kHz.
EXT_RST External Reset
This bit defines the behavior of the P3.6/RST pin
1: P3.6/RST is the reset pin
0: P3.6/RST is an input pin
OSCC_OFF Control for watchdog RC oscillator
This bit is used to switch the watchdog RC oscillator and the watchdog source
1: WDRC oscillator is off; the watchdog is clocked by the main oscillator.
0: WDRC oscillator is on and clock the watchdog
0
-
Reserved
The value read from this bit is indeterminate. Do not reset this bit.
Initial value after erasing : 1111 111X
6.6.2. Clock control register
The clock control register is used to define the clock system behavior
OSCCON - Clock Control Register (86h)
7
6
-
5
-
4
-
3
-
2
1
0
-
SCLKT0
OSCBEN
OSCAEN
Bit
Number
7
Bit
Mnemonic
Description
-
Reserved
Reserved
Reserved
Reserved
Reserved
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
6
5
4
3
2
-
-
-
-
Sub Clock Timer0
SCLKT0
OSCBEN
Cleared by software to select T0 pin
Set by software to select T0 Sub Clock
1
0
Enable RC oscillator
This bit is used to enable the high speed RC oscillator
0: The oscillator is disabled
1: The oscillator is enabled.
OSCAEN
Enable crystal oscillator
This bit is used to enable the crystal oscillator
0: The oscillator is disabled
1: The oscillator is enabled.
Reset Value = 0XXX X0 "RST_OSC" "RST_OSC" b
Not bit addressable
Rev. B - November 10, 2000
11
Preliminary
T80C5111
6.6.3. Clock selection register
The clock selectionl register is used to define the clock system behavior
CKSEL - Clock Selection Register (85h)
7
6
-
5
-
4
-
3
-
2
-
1
-
0
CKS
Bit
Number
7
Bit
Mnemonic
Description
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
6
5
4
3
2
1
0
-
-
-
-
-
-
CKS
Active oscillator selection
This bit is used to select the active oscillator
1: The crystal oscillator is selected
0: The high speed RC oscillator is selected.
Reset Value = XXXX XXX "RST_OSC" b
Not bit addressable
6.6.4. Clock prescaler register
This register is used to reload the clock prescaler of the CPU and peripheral clock.
CKRL - Clock prescaler Register (97h)
7
6
5
4
3
2
1
0
M
Bit
Number
7:0
Bit
Mnemonic
Description
CKRL
0000 0000b: Division factor equal 512
1111 1111b: Division factor equal 2
M: Division factor equal 2*(256-M)
Reset Value = 1111 1111b
Not bit addressable
6.6.5. Clock control register
This register is used to control the X2 mode of the CPU and peripheral clock.
Table 2. CKCON0 Register
12
Rev. B - November 10, 2000
Preliminary
T80C5111
CKCON0 - Clock Control Register (8Fh)
7
6
5
4
3
-
2
1
0
-
WdX2
PcaX2
SiX2
T1X2
T0X2
X2
Bit
Bit
Description
Number
Mnemonic
7
6
-
Reserved
WdX2
Watchdog clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
5
4
PcaX2
SiX2
Programmable Counter Array clock (This control bit is validated when the CPU clock X2 is set; when X2 is
low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the CPU clock X2 is set; when X2 is
low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle.
Reserved
3
2
-
T1X2
Timer1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
1
0
T0X2
X2
Timer0 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
CPU clock
Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals.
Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2" bits.
Reset Value = X000 0000b
Not bit addressable
Table 3. CKCON1 Register
CKCON1 - Clock Control Register
7
6
5
-
4
-
3
-
2
-
1
0
-
-
BRGX2
SPIX2
Bit
Bit
Description
Number
Mnemonic
7
6
5
4
3
2
1
0
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
-
-
-
-
-
-
SPIX2
SPI clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)
Clear to select 6 clock periods per peripheral clock cycle.
Set to select 12 clock periods per peripheral clock cycle
Reset Value = XXXX XX00b
Not bit addressable
Rev. B - November 10, 2000
13
Preliminary
T80C5111
7. Reset and Power Management
7.1. Introduction
The power monitoring and management can be used to supervise the Power Supply (VDD) and to start up properly
when T80C5111 is powered up.
It consists of the features listed below and explained hereafter:
•
•
•
•
•
•
Power on Reset
Power-Fail reset
Power-Off flag
Idle mode
Power-Down mode
Reduced EMI mode
All these features are controlled by several registers, the Power Control register (PCON) and the Auxiliary register
(AUXR) detailed at the end of this chapter.
AUX register not available on all versions.
7.2. Functional description
Figure 3 shows the block diagram of the possible sources of microcontroller reset.
14
Rev. B - November 10, 2000
Preliminary
T80C5111
RST pin*
Hardware WD
Reset
RST pin*
RST_EXT
CONF
PCA WD
set
POF
PCON
POR
PFD
+24 Ck
5V
EN
Fail
CPU Clock
RSTD
PCON
Figure 3. Reset sources
Notes: RST pin available only on 48 and 52 pins versions.
Notes: RST pin available only on LPC versions.
7.3. Power-On Reset
The T80C5111 has a power on reset (POR) module which reset the chip during the initial power raise. The internal
power on reset pulse duration is 24 clock periods of the CPU clock. The chip can also be reseted by the P3.6/
RST/Vpp pin provided the EXT_RST bit of the configuration byte is high.
This module set the POF bit vhen Vcc is below the memory data retention voltage.
The behavior or POR and PFD is shown on Figure 4.
7.4. Power-Fail Detector
The Power-Fail Detector (PFD) is controlled by RSTD bit in PCON register. The PFD is disabled upon reset.
(1)
When enabled, the power supply is continuously monitored and an internal reset is generated if VDD goes
below V
for at least 60 ns.
RST
2
If the power supply rises again over V
( ), the internal reset completes after 24 CPU clock periods.
RST+
If RSTD is reset, the power supply monitoring is disabled.
Rev. B - November 10, 2000
15
Preliminary
T80C5111
In Power-Down mode, the PFD is automatically disabled; this avoids extra consumption and allows VDD reduction
to V
Note:
RET.
1. The internal reset is not propagated on the RST pin.
2 See AC/DC section for the specifications of Vrst.
Caution:
When VDD is reduced to V
in Power-Down mode the VDD voltage is not accuratly monitored. In this case, RAM content may be damage if VDD
RET
goes below V
data.
and circuit behavior is unpredictable unless an external reset is applied. The POF bit can be used to verify if memory contains valid
RET
VRST+
VRST
<60ns
VRET
RSTVPP
>60ns
POR
PFD
RST
24 Ck
24 Ck
Figure 4. Power Fail Reset timing diagram
7.5. Power-Off Flag
When the power is turned off or fails, the data retention is not guaranteed. A Power-Off Flag (POF, see 7.6.1. )
allows to detect this condition. POF is set by hardware during a reset which follows a power-up or a power-fail.
This is a cold reset. A warm reset is an external or a watchdog reset without power failure, hence which preserves
the internal memory content and POF. To use POF, test and clear this bit just after reset. Then it will be set only
after a cold reset.
Notes: When power supply monitoring is disabled (RSTD= 1 or in Power-Down mode), POF information is not delivered with the same
accuracy. It is recommended to clear and not to take in account the POF value after exit from a power down mode with VDD reduction.
Notes: The POF flag is set only if Vcc is lower below the memory data retention voltage. Hence, the PFD may detect a power fail while the
POF bit is still valid.
16
Rev. B - November 10, 2000
Preliminary
T80C5111
7.6. Registers
7.6.1. PCON: Power configuration register
Table 4. PCON Register
PCON (S:87h)
Power configuration Register
7
6
5
4
3
2
1
0
SMOD1
SMOD0
RSTD
POF
GF1
GF0
PD
IDL
Bit
Bit
Description
Number
Mnemonic
Double Baud Rate bit
7
6
SMOD1
SMOD0
Set to double the Baud Rate when Timer 1 is used and mode 1, 2 or 3 is selected in SCON register.
SCON Select bit
When cleared, read/write accesses to SCON.7 are to SM0 bit and read/write accesses to SCON.6 are to SM1 bit.
When set, read/write accesses to SCON.7 are to FE bit and read/write accesses to SCON.6 are to OVR bit.
SCON is Serial Port Control register.
Reset Detector Disable bit
5
4
RSTD
POF
Clear to disable the Power-Fail detector.
Set to enable the Power-Fail detector.
Power-Off flag
Set by hardware when VDD rises above V
to indicate that the Power Supply has been set off.
RET+
Must be cleared by software.
General Purpose flag 1
One use is to indicate wether an interrupt occurred during normal operation or during Idle mode.
3
2
GF1
GF0
General Purpose flag 0
One use is to indicate wether an interrupt occurred during normal operation or during Idle mode.
Power-Down Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Power-Down mode.
If IDL and PD are both set, PD takes precedence.
1
0
PD
Idle Mode bit
Cleared by hardware when an interrupt or reset occurs.
Set to activate the Idle mode.
IDL
If IDL and PD are both set, PD takes precedence.
Reset Value= 0000 0000b
7.7. Port pins
The value of port pins in the different operating modes is shown on the figure below.
Table 5. Pin Conditions in Special Operating Modes
Mode
Program
Memory
Port 1 pins
Port 3 pins
Port 4 pins
Reset
Don’t care
Weak High
Data
Weak High
Data
Weak High
Data
Idle
Internal
Internal
Power-Down
Data
Data
Data
Rev. B - November 10, 2000
17
Preliminary
T80C5111
8. Hardware Watchdog Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The
WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default
disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST,
SFR location 0A6H. When WDT is enabled, it will increment every machine cycle ( 6 internal clock periods) and
there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). The T0
bit of the WDTPRG register is used to select the overflow after 10 or 14 bits. When WDT overflows, it will
generate an internal reset. It will also drive an output RESET HIGH pulse at the emulator RST-pin.
If the crystal oscillator is selected with whe low speed option (32kHz), the low speed RC oscillator must not be
used. In this case the WDT will also use the low speed crystal oscillator.
8.1. Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When
WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow.
The 14-bit counter overflows when it reaches 16383 (3FFFH) or 1024 (1FFFH) and this will reset the device.
When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user
must reset the WDT at least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H
to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows,
it will generate an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x T
, where T
=
OSC
OSC
1/F
. To make the best use of the WDT, it should be serviced in those sections of code that will periodically
OSC
be executed within the time required to prevent a WDT reset.
7
To have a more powerful WDT, a 2 counter has been added to extend the Time-out capability, ranking from
16ms to 2s @ F
7. (SFR0A7h).
= 12MHz and T0=0. To manage this feature, refer to WDTPRG register description, Table
OSC
Table 6. WDTRST Register
WDTRST Address (0A6h)
7
6
5
4
3
2
1
Reset value
X
X
X
X
X
X
X
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
18
Rev. B - November 10, 2000
Preliminary
T80C5111
Table 7. WDTPRG Register
WDTPRG Address (0A7h)
7
6
5
4
3
2
1
0
T4
T3
T2
T1
T0
S2
S1
S0
Bit
Mnemonic
Bit Number
Description
7
6
5
4
3
T4
T3
T2
T1
T0
Reserved
Do not try to set this bit.
WDT overflow select bit
0 : Overflow after 14 bits
1 : Overflow after 10 bits
2
1
0
S2
S1
S0
WDT Time-out select bit 2
WDT Time-out select bit 1
WDT Time-out select bit 0
S2S1S0
000
001
010
011
100
101
110
111
Selected Time-out with T0=0
14
(2 - 1) machine cycles, 16.3 ms @ 12 MHz
15
(2 - 1) machine cycles, 32.7 ms @ 12 MHz
16
(2 - 1) machine cycles, 65.5 ms @ 12 MHz
17
(2 - 1) machine cycles, 131 ms @ 12 MHz
18
(2 - 1) machine cycles, 262 ms @ 12 MHz
19
(2 - 1) machine cycles, 542 ms @ 12 MHz
20
(2 - 1) machine cycles, 1.05 s @ 12 MHz
21
(2 - 1) machine cycles, 2.09 s @ 12 MHz
S2S1 S0
000
001
010
011
100
101
110
111
Selected Time-out with T0=1
10
(2 - 1) machine cycles, 60 ms @ 200 kHz
11
(2 - 1) machine cycles, 120ms @ 200 kHz
12
(2 - 1) machine cycles, 240ms @ 200 kHz
13
(2 - 1) machine cycles, 480ms @ 200 kHz
14
(2 - 1) machine cycles, 860ms @ 200 kHz
15
(2 - 1) machine cycles, 1.7s @ 200 kHz
16
(2 - 1) machine cycles, 3.4s @ 200 kHz
17
(2 - 1) machine cycles, 6.8s @ 200 kHz
Reset value XXX0 0000
Write only register
8.1.1. WDT during Power Down and Idle
8.1.1.1. Power down and OSCC inactive
In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the
user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset
or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power
Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the T80C5111
is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from
resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reseted during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the
WDT just before entering powerdown.
Rev. B - November 10, 2000
19
Preliminary
T80C5111
8.1.1.2. Power down and OSCC active
In Power Down mode the low speed RC oscillator never stops. If the WDT is active before entering power down,
the T80C5111 will be reseted once and will start executing the program code. The software may then decide to
leave the WDT inactive.
If the high speed RC oscillator is selected at reset, this mode may be used to periodically awake the T80C5111
and check for an external event while keeping the average consumption at a very low level.
There are 2 methods of exiting Power Down mode: by a hardware or watchdog reset or via a level activated
external interrupt which is enabled prior to entering Power Down mode. When Power Down is exited with hardware
or watch dog reset, servicing the WDT should occur as it normally should whenever the T80C5111 is reset. Exiting
Power Down with an interrupt is significantly different. As the WDT and interrupt are asynchronous events, the
WDT may overflow within a few states of exiting of powerdown. To limit the probability of such an event, it is
suggested that the WDT be reseted during the interrupt service routine.
8.1.1.3. Idle mode
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the T80C5111 while in Idle
mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode.
20
Rev. B - November 10, 2000
Preliminary
T80C5111
9. Ports
The low pin count versions of the T80C5111 has 3 I/O ports, port 1, port 3, and port 4. The exact number of I/
O pins available depend upon the oscillator and reset options chosen. The number of possible I/O on each package
option is shown on Table 9.
At least 11, 15 or 19 pins of the T80C5111 may be used as I/Os when a two-pin external oscillator and an external
reset circuit are used. Three more pins may be available if fully on-chip oscillator and reset configurations are chosen.
Table 8. Number of available I/O versus pin number
16
20
24
I/O
10
1
14
1
18
1
RST input (*)
XTAL I/O
2
2
2
Maximun I/O count
12+1
16+1
20+1
Notes: (*)Not implemeted on first version
Except RST/Vpp, all port1, port3 and port4 I/O port pins on the T80C5111 may be software configured to one of
four types on a bit-by-bit basis, as shown in Table 10. These are: quasi-bidirectional (standard 80C51 port outputs),
push-pull, open drain, and input only. Two configuration registers for each port choose the output type for each
port pin.
Table 9. Port Output Configurationsettings using PxM1 and PxM2 registers
PxM1.y bit
PxM2.y bit
Port Output Mode
0
0
1
1
0
1
0
1
Quasi bidirectional
Push-Pull
Input Only (High Impedance)
Open Drain
9.1. Ports types
9.1.1. Quasi-Bidirectional Output Configuration
The default port output configuration for standard T80C5111 I/O ports is the quasi-bidirectional output that is
common on the 80C51 and most of its derivatives. This output type can be used as both an input and output
without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly
driven, allowing an external device to pull the pin low. When the pin is pulled low, it is driven strongly and able
to sink a fairly large current. These features are somewhat similar to an open drain output except that there are
three pull-up transistors in the quasi-bidirectional output that serve different purposes. One of these pull-ups, called
the "very weak" pull-up, is turned on whenever the port latch for the pin contains a logic 1. The very weak pull-
up sources a very small current that will pull the pin high if it is left floating. A second pull-up, called the "weak"
pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level.
This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If a pin that
has a logic 1 on it is pulled low by an external device, the weak pull-up turns off, and only the very weak pull-
up remains on. In order to pull the pin low under these conditions, the external device has to sink enough current
to overpower the weak pull-up and take the voltage on the port pin below its input threshold.
Rev. B - November 10, 2000
21
Preliminary
T80C5111
The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up low-to-high transitions on
a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1. When this occurs, the strong
pull-up turns on for a brief time, two CPU clocks, in order to pull the port pin high quickly. Then it turns off again.
The quasi-bidirectional port configuration is shown in Figure 5.
2 CPU
CLOCK DELAY
P
P
P
Very
Weak
Strong
Weak
Pin
Port latch
Data
N
Input
Data
Figure 5. Quasi-Bidirectional Output
9.1.2. Open Drain Output Configuration
The open drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port
driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must
have an external pull-up, typically a resistor tied to Vdd. The pull-down for this mode is the same as for the quasi-
bidirectional mode. The open drain port configuration is shown in Figure 6.
Pin
Port latch
Data
N
Input
Data
Figure 6. Open Drain Output
9.1.3. Push-Pull Output Configuration
The push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bidirectional
output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode
may be used when more source current is needed from a port output. The push-pull port configuration is shown
in Figure 7.
22
Rev. B - November 10, 2000
Preliminary
T80C5111
P
Strong
Pin
Port latch
Data
N
Input
Data
Figure 7. Push-Pull Output
9.1.4. Input only Configuration
The input only configuration is a pure input with neither pull-up nor pull-down.
The input only configuration is shown in Figure 7.
Input
Data
Pin
Figure 8. Input only
9.2. Ports description
9.2.1. Ports P1, P3 and P4
P3.7 may be used as a Schmitt trigger input if the T80C5111 has been configured for an internal reset and is not
using the external reset input function RST.
Additionally, port pins P3. and P3.5 are disabled for both input and output if one of the crystal oscillator options
is chosen. Those options are described in the Oscillator section.
Every output on the T80C5111 may potentially be used as a 20 mA sink LED drive output. However, there is a
maximum total output current for all ports which must not be exceeded. All ports pins of the T80C5111 have slew
rate controlled outputs. This is to limit noise generated by quickly switching output signals. The slew rate is factory
set to approximately 10 ns rise and fall times.
The inputs of each I/O port of the T80C5111 are TTL level Schmitt triggers with hysteresis.
Rev. B - November 10, 2000
23
Preliminary
T80C5111
9.2.2. Ports P0 and P2
High pin count version of the T80C5111 have standard address and data ports P0 and P2. These ports are standard C51
ports (Quasi-bidirectional I/O). The control lines are provided on the pins : ALE, PSEN, EA, Reset; RD and WR signals
are on the bits P1.1 and P1.0 .
9.3. Registers
Table 10. P1M1 Register
P1M1 Address (D4h)
7
6
5
4
3
2
1
0
P1M1.7
P1M1.6
P1M1.5
P1M1.4
P1M1.3
P1M1.2
P1M1.1
P1M1.0
Bit
Mnemonic
Bit Number
Description
7 : 0
P1M1.x
Port Output configuration bit
See Table 10. for configuration definition
Reset value 0000 00XX
Table 11. P1M2 Register
P1M2 Address (E2h)
7
6
5
4
3
2
1
0
P1M2.7
P1M2.6
P1M2.5
P1M2.4
P1M2.3
P1M2.2
P1M2.1
P1M2.0
Bit
Mnemonic
Bit Number
Description
7 : 0
P1M2.x
Port Output configuration bit
See Table 10. for configuration definition
Reset value 0000 00XX
Table 12. P3M1 Register
P3M1 Address (D5h)
7
6
5
4
3
2
1
0
P3M1.7
P3M1.6
P3M1.5
P3M1.4
P3M1.3
P3M1.2
P3M1.1
P3M1.0
Bit
Mnemonic
Bit Number
Description
7 : 0
P3M1.x
Port Output configuration bit
See Table 10. for configuration definition
Reset value 0000 0000
Table 13. P3M2 Register
P3M2 Address (E4h)
7
6
5
4
3
2
1
0
P3M2.7
P3M2.6
P3M2.5
P3M2.4
P3M2.3
P3M2.2
P3M2.1
P3M2.0
Bit
Number
7 : 0
Bit
Mnemonic
P3M2.x
Description
Port Output configuration bit
See Table 10. for configuration definition
Reset value 0000 0000
24
Rev. B - November 10, 2000
Preliminary
T80C5111
Table 14. P4M1 Register
P4M1 Address (D6h)
7
6
5
4
3
2
1
0
P4M1.7
P4M1.6
P4M1.5
P4M1.4
P4M1.3
P4M1.2
P4M1.1
P4M1.0
Bit
Mnemonic
Bit Number
Description
7 : 0
P4M1.x
Port Output configuration bit
See Table 10. for configuration definition
Reset value 0000 0000
Table 15. P4M2 Register
P4M2 Address (E5h)
7
6
5
4
3
2
1
0
P4M2.7
P4M2.6
P4M2.5
P4M2.4
P4M2.3
P4M2.2
P4M2.1
P4M2.0
Bit
Mnemonic
Bit Number
Description
7: 0
P4M2.x
Port Output configuration bit
See Table 10. for configuration definition
Reset value 0000 0000
Rev. B - November 10, 2000
25
Preliminary
T80C5111
10. Dual Data Pointer Register Ddptr
The additional data pointer can be used to speed up code execution and reduce code size in a number of ways.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory location.
There are two 16-bit DPTR registers that address the external memory, and a single bit called
DPS = AUXR1/bit0 (See Table 16.) that allows the program code to switch between them (Refer to Figure 9).
External Data Memory
7
0
DPS
DPTR1
DPTR0
AUXR1(A2H)
DPH(83H) DPL(82H)
Figure 9. Use of Dual Pointer
26
Rev. B - November 10, 2000
Preliminary
T80C5111
Table 16. AUXR1: Auxiliary Register 1
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
DPS
Bit
Mnemonic
Bit Number
Description
7
-
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
The value read from this bit is indeterminate. Do not set this bit.
6
5
4
3
2
1
0
-
-
-
-
-
-
DPS
Data Pointer Selection
Clear to select DPTR0.
Set to select DPTR1.
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new feature. In that case, the reset
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
Application
Software can take advantage of the additional data pointers to both increase speed and reduce code size, for
example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’
pointer and the other one as a "destination" pointer.
Rev. B - November 10, 2000
27
Preliminary
T80C5111
ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2 AUXR1 EQU 0A2H
;
0000 909000MOV DPTR,#SOURCE ; address of SOURCE
0003 05A2 INC AUXR1 ; switch data pointers
0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers
000A E0 MOVX A,@DPTR ; get a byte from SOURCE
000B A3 INC DPTR ; increment SOURCE address
000C 05A2 INC AUXR1 ; switch data pointers
000E F0 MOVX @DPTR,A ; write the byte to DEST
000F A3 INC DPTR ; increment DEST address
0010 70F6JNZ LOOP ; check for 0 terminator
0012 05A2 INC AUXR1 ; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note
that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple
routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not
its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe
that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.
28
Rev. B - November 10, 2000
Preliminary
T80C5111
11. Serial I/O Ports enhancements
The serial I/O ports in the T80C5111 are compatible with the serial I/O port in the 80C52.
They provide both synchronous and asynchronous communication modes. They operate as Universal Asynchronous
Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and
reception can occur simultaneously and at different baud rates
Serial I/O ports include the following enhancements:
•
•
Framing error detection
Automatic address recognition
11.1. Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing
bit error detection feature, set SMOD0 bit in PCON register (See Figure 10).
SM2 REN
TI
RI
SM0/FE SM1
TB8 RB8
SCON for UART (98h) (SCON_1 for UART_1 (C0h))
Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1 for UART)
SM0 to UART mode control (SMOD0 = 0 for UART)
GF1
POF
GF0
SMOD1 SMOD0
PCON for UART (87h) (SMOD bits for UART_1
are located in BDRCON_1)
-
PD
IDL
To UART framing error control
Figure 10. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop
bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit
is not found, the Framing Error bit (FE) in SCON register (See Table 17) bit is set.
Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can
clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled,
RI rises on stop bit instead of the last data bit (See Figure 11. and Figure 12.).
D0 D1 D2 D3 D4 D5 D6 D7
RXD
Start
bit
Data byte
Stop
bit
RI
SMOD0=X
FE
SMOD0=1
Figure 11. UART Timings in Mode 1
Rev. B - November 10, 2000
29
Preliminary
T80C5111
RXD
RI
D0 D1 D2 D3 D4 D5 D6 D7 D8
Start
bit
Data byte
Ninth Stop
bit bit
SMOD0=0
RI
SMOD0=1
FE
SMOD0=1
Figure 12. UART Timings in Modes 2 and 3
11.2. Automatic Address Recognition
The automatic address recognition feature is enabled for each UART when the multiprocessor communication
feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by
allowing the serial port to examine the address of each incoming command frame. Only when the serial port
recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit
takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the
device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broadcast address.
NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON
register in mode 0 has no effect).
11.2.1. Given Address
Each UART has an individual address that is specified in SADDR register; the SADEN register is a mask byte
that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the
flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:
SADDR
SADEN
Given
0101 0110b
1111 1100b
0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:
Slave B:
Slave C:
SADDR
SADEN
Given
1111 0001b
1111 1010b
1111 0X0Xb
SADDR
SADEN
Given
1111 0011b
1111 1001b
1111 0XX1b
SADDR
SADEN
Given
1111 0010b
1111 1101b
1111 00X1b
30
Rev. B - November 10, 2000
Preliminary
T80C5111
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A
only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but
not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2
clear (e.g. 1111 0001b).
11.2.2. Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as
don’t-care bits, e.g.:
SADDR
0101 0110b
SADEN
1111 1100b
Broadcast =SADDR OR SADEN
1111 111Xb
The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a
broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:
Slave B:
Slave C:
SADDR
1111 0001b
SADEN
1111 1010b
Broadcast 1111 1X11b,
SADDR
SADEN
1111 0011b
1111 1001b
Broadcast 1111 1X11B,
SADDR=
SADEN
Broadcast 1111 1111b
1111 0010b
1111 1101b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the
master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send
and address FBh.
11.2.3. Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX
XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards
compatible with the 80C51 microcontrollers that do not support automatic address recognition.
11.3. Baud Rate Selection for UART for mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON
registers.
Rev. B - November 10, 2000
31
Preliminary
T80C5111
TIMER1_BRG
0
1
/ 16
Rx Clock
INT_BRG
RBCK
TIMER1_BRG
0
/ 16
1
Tx Clock
INT_BRG
TBCK
Figure 13. Baud Rate selection
11.3.1. Baud Rate selection table for UART
Clock Source for
UART Tx
Clock Source
UART Rx
TBCK
RBCK
0
1
0
1
0
0
1
1
Timer 1
INT_BRG
Timer 1
Timer 1
Timer 1
INT_BRG
INT_BRG
INT_BRG
11.3.2. Internal Baud Rate Generator (BRG)
When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending
on the BRL reload value, the X2 bit in CKON0 register, the value of SPD bit (Speed Mode) in BDRCON register
and the value of the SMOD1 bit in PCON register (for UART). :
SMOD1
/2
0
INT_BRG
1
auto reload counter
Peripheral clock
0
1
/6
BRG
overflow
BRL
SPD
BRR
Figure 14. Internal Baud Rate Generator
32
Rev. B - November 10, 2000
Preliminary
T80C5111
•
for UART
SMOD1
X2
x 2 x FXTAL
2
Baud_Rate =
(BRL) = 256 -
(1-SPD)
2 x 2 x 6
x 16 x [256 - (BRL)]
SMOD1
X2
2
x 2 x FXTAL
(1-SPD)
2 x 2 x 6
x 16 x Baud_Rate
Example of computed value when X2=1, SMOD1=1, SPD=1
Baud Rates
FXTAL = 16.384 MHz
FXTAL = 24MHz
BRL
Error (%)
1.23
BRL
243
230
217
204
178
100
-
Error (%)
0.16
0.16
0.16
0.16
0.16
0.16
-
115200
57600
38400
28800
19200
9600
247
238
229
220
203
149
43
1.23
1.23
1.23
0.63
0.31
4800
1.23
Example of computed value when X2=0, SMOD1=0, SPD=0
Baud Rates
FOSC = 16.384 MHz
FOSC = 24MHz
BRL
Error (%)
1.23
BRL
243
230
202
152
Error (%)
0.16
4800
2400
1200
600
247
238
220
185
1.23
0.16
1.23
3.55
0.16
0.16
The baud rate generator can be used for mode 1 or 3 (refer to figures 13 ), but also for mode 0 for both UARTs,
thanks to the bit SRC located in BDRCON register (Table 19)
11.4. UARTs registers
SADEN - Slave Address Mask Register for UART (B9h)
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b
SADDR - Slave Address Register for UART (A9h)
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b
Rev. B - November 10, 2000
33
Preliminary
T80C5111
SBUF - Serial Buffer Register for UART (99h)
7
6
5
4
3
2
1
0
Reset Value = XXXX XXXXb
BRL - Baud Rate Reload Register for the internal baud rate generator, UART UART(9Ah)
7
6
5
4
3
2
1
0
Reset Value = 0000 0000b
34
Rev. B - November 10, 2000
Preliminary
T80C5111
Table 17. SCON Register
SCON - Serial Control Register for UART (98h)
7
6
5
4
3
2
1
0
FE/SM0
SM1
SM2
REN
TB8
RB8
TI
RI
Bit
Mnemonic
Bit Number
Description
7
FE
Framing Error bit (SMOD0=1) for UART
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
SMOD0 must be set to enable access to the FE bit
SM0
SM1
Serial port Mode bit 0 (SMOD0=0) for UART
Refer to SM1 for serial port mode selection.
SMOD0 must be cleared to enable access to the SM0 bit
6
5
Serial port Mode bit 1 for UART
SM0
SM1
ModeDescriptionBaud Rate
0
0
0Shift RegisterF /12 (F
/6 X2 mode)
XTAL
XTAL
0
1
1
0
18-bit UARTVariable
29-bit UARTF /64 or F
/32 (F
/32 or F
/16 X2 mode)
XTAL
XTAL
XTAL
XTAL
1
1
39-bit UARTVariable
SM2
Serial port Mode 2 bit / Multiprocessor Communication Enable bit for UART
Clear to disable multiprocessor communication feature.
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit
should be cleared in mode 0.
4
3
REN
TB8
Reception Enable bit for UART
Clear to disable serial reception.
Set to enable serial reception.
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 for UART.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
2
RB8
Receiver Bit 8 / Ninth bit received in modes 2 and 3 for UART
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1
0
TI
RI
Transmit Interrupt flag for UART
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
modes.
Receive Interrupt flag for UART
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 11. and Figure 12. in the other modes.
Reset Value = 0000 0000b
Bit addressable
Rev. B - November 10, 2000
35
Preliminary
T80C5111
Table 18. PCON Register
PCON - Power Control Register (87h)
7
6
5
4
3
2
1
0
SMOD1
SMOD0
RSTD
POF
GF1
GF0
PD
IDL
Bit
Mnemonic
Bit Number
Description
7
SMOD1
Serial port Mode bit 1 for UART
Set to select double baud rate in mode 1, 2 or 3.
6
5
SMOD0
Serial port Mode bit 0 for UART
Clear to select SM0 bit in SCON register.
Set to to select FE bit in SCON register.
RSTD
Reset Detector Disable Bit
Clear to disable PFD.
Set to enable PFD.
4
3
2
1
0
POF
GF1
GF0
PD
Power-Off Flag
Clear to recognize next reset type.
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
IDL
Idle mode bit
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 0001 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit.
36
Rev. B - November 10, 2000
Preliminary
T80C5111
Table 19. BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
7
-
6
-
5
-
4
3
2
1
0
BRR
TBCK
RBCK
SPD
SRC
Bit
Number
Bit
Mnemonic
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Baud Rate Run Control bit
7
6
5
-
-
-
4
3
2
1
0
BRR
TBCK
RBCK
SPD
Clear to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
Transmission Baud rate Generator Selection bit for UART
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
Reception Baud Rate Generator Selection bit for UART
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
Baud Rate Speed Control bit for UART
Clear to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
Baud Rate Source select bit in Mode 0 for UART
SRC
Clear to select F
/12 as the Baud Rate Generator (F
/6 in X2 mode).
OSC
OSC
Set to select the internal Baud Rate Generator for UARTs in mode 0.
Reset Value = XXX0 0000b
Rev. B - November 10, 2000
37
Preliminary
T80C5111
12. Serial Port Interface (SPI)
12.1. Introduction
The Serial Peripheral Interface module (SPI) which allows full-duplex, synchronous, serial communication between
the MCU and peripheral devices, including other MCUs.
12.2. Features
Features of the SPI module include the following:
•
•
•
•
•
•
Full-duplex, three-wire synchronous transfers
Master or Slave operation
Eight programmable Master clock rates
Serial clock with programmable polarity and phase
Master Mode fault error flag with MCU interrupt capability
Write collision flag protection
12.3. Signal Description
Figure 15 shows a typical SPI bus configuration using one Master controller and many Slave peripherals. The bus
is made of three wires connecting all the devices:
Slave 1
MISO
MOSI
SCK
SS
V
DD
Master
0
1
2
3
Slave 4
Slave 3
Slave 2
Figure 15. Typical SPI bus
The Master device selects the individual Slave devices by using four pins of a parallel port to control the four SS
pins of the Slave devices.
12.3.1. Master Output Slave Input (MOSI)
This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI line is used to
transfer data in series from the Master to the Slave. Therefore, it is an output signal from the Master, and an input
signal to a Slave. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB)last.
38
Rev. B - November 10, 2000
Preliminary
T80C5111
12.3.2. Master Input Slave Output (MISO)
This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO line is used to
transfer data in series from the Slave to the Master. Therefore, it is an output signal from the Slave, and an input
signal to the Master. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.
12.3.3. SPI Serial Clock (SCK)
This signal is used to synchronize the data movement both in and out the devices through their MOSI and MISO
lines. It is driven by the Master for eight clock cycles which allows to exchange one byte on the serial lines.
12.3.4. Slave Select (SS)
Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a
Slave. It is obvious that only one Master (SS high level) can drive the network. The Master may select each Slave
device by software through port pins (Figure 15). To prevent bus conflicts on the MISO line, only one slave should
be selected at a time by the Master for a transmission.
In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register
(SPSTA) to prevent multiple masters from driving MOSI and SCK (See Error conditions).
A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.
The SS pin could be used as a general purpose if the following conditions are met:
•
The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of configuration
can be found when only one Master is driving the network and there is no way that the SS pin will be
pulled low. Therefore, the MODF flag in the SPSTA will never be set .
1
2
•
The Device is configured as a Slave with CPHA and SSDIS control bits set . This kind of configuration
can happen when the system comprises one Master and one Slave only. Therefore, the device should always
be selected and there is no raison that the Master uses the SS pin to select the communicating Slave device.
12.3.5. Baud rate
In Master mode, the baud rate can be selected from a baud rate generator which is controled by three bits in the
SPCON register: SPR2, SPR1 and SPR0. The Master clock is chosen from one of seven clock rates resulting from
the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128, or an external clock.
Table 20 gives the different clock rates selected by SPR2:SPR1:SPR0:
Table 20. SPI Master baud rate selection
SPR2:SPR1:SPR0
Clock Rate
Baud rate divisor (BD)
000
001
010
011
100
101
110
111
F
F
/2
/4
2
CkIdle
CkIdle
4
F
/ 8
/16
/32
8
CkIdle
F
16
CkIdle
F
32
CkIdle
F
/64
64
128
CkIdleH
F
/128
CkIdle
External clock
Output of BRG
1. Clearing SSDIS control bit does not clear MODF.
2. Special care should be taken not to set SSDIS control bit when CPHA = ’0’ because in this mode, the SS is used to start the transmission.
Rev. B - November 10, 2000
39
Preliminary
T80C5111
12.4. Functional Description
Figure 16 shows a detailed structure of the SPI module.
Internal Bus
SPDAT
Shift Register
IntClk
7
6
5
4
3
2
1
0
/2
/4
/8
/16
/32
/64
/128
Clock
Divider
Receive Data Register
Pin
Control
Logic
MOSI
MISO
Clock
Logic
M
S
SCK
SS
Clock
Select
External Clk
SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0
SPCON
8-bit bus
SPI
1-bit signal
Control
SPI Interrupt Request
SPSTA
-
-
-
-
-
SPIF WCOL
MODF
Figure 16. SPI Module Block Diagram
12.4.1. Operating Modes
The Serial Peripheral Interface can be configured as one of the two modes: Master mode or Salve mode. The
configuration and initialization of the SPI module is made through one register:
•
The Serial Peripheral CONtrol register (SPCON)
Once the SPI is configured, the data exchange is made using:
•
•
•
SPCON
The Serial Peripheral STAtus register (SPSTA)
The Serial Peripheral DATa register (SPDAT)
During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially).
A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A
Slave Select line (SS) allows individual selection of a Slave SPI device; Slave devices that are not selected do not
interfere with SPI bus activities.
When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending
data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in
synchronized with the same clock (Figure 17).
40
Rev. B - November 10, 2000
Preliminary
T80C5111
MISO
MOSI
MISO
MOSI
8-bit Shift register
8-bit Shift register
SPI
Clock Generator
SCK
SS
SCK
SS
V
DD
Master MCU
Slave MCU
VSS
Figure 17. Full-Duplex Master-Slave Interconnection
12.4.1.1. Master mode
1
The SPI operates in Master mode when the Master bit, MSTR , in the SPCON register is set. Only one Master
SPI device can initiate transmissions. Software begins the transmission from a Master SPI module by writing to
the Serial Peripheral Data Register (SPDAT). If the shift register is empty, the byte is immediately transferred to
the shift register. The byte begins shifting out on MOSI pin under the control of the serial clock, SCK. Simultaneously,
another byte shifts in from the Slave on the Master’s MISO pin. The transmission ends when the Serial Peripheral
transfer data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes set, the received byte from
the Slave is transferred to the receive data register in SPDAT. Software clears SPIF by reading the Serial Peripheral
Status register (SPSTA) with the SPIF bit set, and then reading the SPDAT.
When the pin SS is pulled down during a transmission, the data is interrupted and when the transmission is
established again, the data present in the SPDAT is resent.
12.4.1.2. Slave mode
2
The SPI operates in Slave mode when the Master bit, MSTR , in the SPCON register is cleared. Before a data
transmission occurs, the Slave Select pin, SS, of the Slave device must be set to ’0’. SS must remain low until
the transmission is complete.
In a Slave SPI module, data enters the shift register under the control of the SCK from the Master SPI module.
After a byte enters the shift register, it is immediately transferred to the receive data register in SPDAT, and the
SPIF bit is set. To prevent an overflow condition, Slave software must then read the SPDAT before another byte
3
enters the shift register . A Slave SPI must complete the write to the SPDAT (shift register) at least one bus cycle
before the Master SPI starts a transmission. If the write to the data register is late, the SPI transmits the data
already in the shift register from the previous transmission.
12.4.2. Transmission Formats
Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON:
4
4
the Clock POLarity (CPOL ) and the Clock PHAse (CPHA ). CPOL defines the default SCK line level in idle
state. It has no significant effect on the transmission format. CPHA defines the edges on which the input data are
sampled and the edges on which the output data are shifted (Figure 18 and Figure 19). The clock phase and polarity
should be identical for the Master SPI device and the communicating Slave device.
1. The SPI module should be configured as a Master before it is enabled (SPEN set). Also the Master SPI should be configured before the Slave SPI.
2. The SPI module should be configured as a Slave before it is enabled (SPEN set).
3. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed.
4. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = ’0’).
Rev. B - November 10, 2000
41
Preliminary
T80C5111
1
2
3
4
5
6
7
8
SCK cycle number
SPEN (internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI (from Master)
MSB
bit6
bit6
bit5
bit5
bit4
bit4
bit3
bit3
bit2
bit2
bit1
bit1
LSB
LSB
MISO (from Slave)
MSB
SS (to Slave)
Capture point
Figure 18. Data Transmission Format (CPHA = 0)
1
2
3
4
5
6
7
8
SCK cycle number
SPEN (internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MSB
MSB
bit6
bit6
bit5
bit5
bit4
bit4
bit3
bit3
bit2
bit2
bit1
bit1
LSB
LSB
MOSI (from Master)
MISO (from Slave)
SS (to Slave)
Capture point
Figure 19. Data Transmission Format (CPHA = 1)
As shown in Figure 18, the first SCK edge is the MSB capture strobe. Therefore the Slave must begin driving its
data before the first SCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must
be toggled high and then low between each byte transmitted (Figure 20).
Byte 3
MISO/MOSI
Master SS
Byte 1
Byte 2
Slave SS
(CPHA = 0)
Slave SS
(CPHA = 1)
Figure 20. CPHA/SS timing
Figure 19 shows an SPI transmission in which CPHA is ’1’. In this case, the Master begins driving its MOSI pin
on the first SCK edge. Therefore the Slave uses the first SCK edge as a start transmission signal. The SS pin can
remain low between transmissions (Figure 20). This format may be preferable in systems having only one Master
and only one Slave driving the MISO data line.
42
Rev. B - November 10, 2000
Preliminary
T80C5111
12.4.3. Error conditions
The following flags in the SPSTA signal SPI error conditions:
12.4.3.1. Mode Fault (MODF)
MODe Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with
the actual mode of the device. MODF is set to warn that there may have a multi-master conflict for system control.
In this case, the SPI system is affected in the following ways:
•
•
•
An SPI receiver/error CPU interrupt request is generated.
The SPEN bit in SPCON is cleared. This disable the SPI.
The MSTR bit in SPCON is cleared.
When SS DISable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the SS signal becomes ’0’.
However, as stated before, for a system with one Master, if the SS pin of the Master device is pulled low, there
is no way that another Master is attempting to drive the network. In this case, to prevent the MODF flag from
being set, software can set the SSDIS bit in the SPCON register and therefore making the SS pin as a general
purpose I/O pin.
Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed by a write to
the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared.
12.4.3.2. Write Collision (WCOL)
A Write COLlision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done during a transmit
sequence.
WCOL does not cause an interruption, and the transfer continues uninterrupted.
Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an access to SPDAT.
12.4.3.3. Overrun Condition
An overrun condition occurs when the Master device tries to send several data bytes and the Slave devise has not
cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the
byte sent after the SPIF bit was last cleared. A read of the SPDAT returns this byte. All others bytes are lost.
This condition is not detected by the SPI peripheral.
12.4.4. Interrupts
Two SPI status flags can generate a CPU interrupt requests:
Flag
Request
SPIF (SP data transfer)
MODF (Mode Fault)
SPI Transmitter Interrupt request
SPI Receiver/Error Interrupt Request (if SSDIS = ’0’)
Table 21. SPI Interrupts
Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been completed. SPIF
bit generates transmitter CPU interrupt requests.
Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent with the mode
of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests.
Figure 21 gives a logical view of the above statements:
Rev. B - November 10, 2000
43
Preliminary
T80C5111
SPIF
SPI Transmitter
CPU Interrupt Request
SPI
CPU Interrupt Request
MODF
SPI Receiver/error
CPU Interrupt Request
SSDIS
Figure 21. SPI Interrupt Requests Generation
12.4.5. Registers
There are three registers in the module that provide control, status and data storage functions. These registers are
describes in the following paragraphs.
12.4.5.1. Serial Peripheral CONtrol register (SPCON)
The Serial Peripheral Control Register does the following:
•
•
•
•
•
Selects one of the Master clock rates,
Configure the SPI module as Master or Slave,
Selects serial clock polarity and phase,
Enables the SPI module,
Frees the SS pin for a general purpose
Table 22 describes this register and explains the use of each bit:
Table 22. Serial Peripheral Control Register
7
6
5
4
3
2
1
0
SPR2
SPEN
SSDIS
MSTR
CPOL
CPHA
SPR1
SPR0
Bit
Number
R/W
Mode
Bit Mnemonic
Description
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate
7
SPR2
RW
Serial Peripheral Enable
6
5
SPEN
RW
RW
Clear to disable the SPI interface
Set to enable the SPI interface
SS Disable
Clear to enable SS# in both Master and Slave modes
Set to disable SS# in both Master and Slave modes. In Slave mode, this bit has no effect if
CPHA = ’0’
SSDIS
Serial Peripheral Master
4
3
2
MSTR
CPOL
CPHA
RW
RW
RW
Clear to configure the SPI as a Slave
Set to configure the SPI as a Master
Clock Polarity
Clear to have the SCK set to ’0’ in idle state
Set to have the SCK set to ’1’ in idle low
Clock Phase
Clear to have the data sampled when the SPSCK leaves the idle state (see CPOL)
Set to have the data sampled when the SPSCK returns to idle state (see CPOL)
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Rev. B - November 10, 2000
Preliminary
T80C5111
Bit
Number
R/W
Mode
Bit Mnemonic
Description
Serial Peripheral Rate (SPR2:SPR1:SPR0)
000 : F
001 : F
010 : F
011 : F
/2
/4
/8
/16
CLK PERIPH
CLK PERIPH
CLK PERIPH
CLK PERIPH
1
0
SPR1
RW
RW
100 : F
101 : F
110 : F
/32
/64
/128
CLK PERIPH
CLK PERIPH
CLK PERIPH
SPR0
111 : External clock, output of BRG
Reset Value= 00010100b
12.4.5.2. Serial Peripheral STAtus register (SPSTA)
The Serial Peripheral Status Register contains flags to signal the following conditions:
•
•
•
Data transfer complete
Write collision
Inconsistent logic level on SS pin (mode fault error)
Table 23 describes the SPSTA register and explains the use of every bit in the register:
7
6
5
4
3
2
1
0
SPIF
WCOL
-
MODF
-
-
-
-
Bit
Number
R/W
Mode
Bit Mnemonic
Description
Serial Peripheral data transfer flag
Clear by hardware to indicate data transfer is in progress or has been approved by a clearing
sequence.
7
SPIF
R
Set by hardware to indicate that the data transfer has been completed.
Write Collision flag
Cleared by hardware to indicate that no collision has occurred or has been approved by a
clearing sequence.
Set by hardware to indicate that a collision has been detected.
6
5
4
WCOL
-
R
RW
R
Reserved
The value read from this bit is indeterminate. Do not set this bit
Mode Fault
Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been
approved by a clearing sequence.
MODF
Set by hardware to indicate that the SS pin is at inappropriate logic level
Reserved
3
2
1
0
-
-
-
-
RW
RW
RW
RW
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reset Value= 00X0XXXXb
Table 23. Serial Peripheral Status and Control register
Rev. B - November 10, 2000
45
Preliminary
T80C5111
12.4.5.3. Serial Peripheral DATa register (SPDAT)
The Serial Peripheral Data Register (Table 24) is a read/write buffer for the receive data register. A write to SPDAT
places data directly into the shift register. No transmit buffer is available in this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content of the shift register.
Table 24. Serial Peripheral Data Register
7
6
5
4
3
2
1
0
R7
R6
R5
R4
R3
R2
R1
R0
Reset Value= XXXX XXXXb
R7:R0 : Receive data bits
SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-going exchange.
However, special care should be taken when writing to them while a transmission is on-going:
•
•
•
•
•
Do not change SPR2, SPR1 and SPR0
Do not change CPHA and CPOL
Do not change MSTR
Clearing SPEN would immediately disable the peripheral
Writing to the SPDAT will cause an overflow
46
Rev. B - November 10, 2000
Preliminary
T80C5111
13. Programmable Counter Array PCA
The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its
advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/
counter which serves as the time base for an array of five compare/ capture modules. Its clock input can be
programmed to count any one of the following signals:
•
•
•
•
Oscillator frequency ÷ 12 (÷ 6 in X2 mode)
Oscillator frequency ÷ 4 (÷ 2 in X2 mode)
Timer 0 overflow
External input on ECI (P1.2)
Each compare/capture modules can be programmed in any one of the following modes:
•
•
•
•
rising and/or falling edge capture,
software timer,
high-speed output, or
pulse width modulator.
Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog Timer", page 56).
When the compare/capture modules are programmed in the capture mode, software timer, or high speed output
mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer
overflow share one interrupt vector.
The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below.
If the port is not used for the PCA, it can still be used for standard I/O.
PCA component
External I/O Pin
16-bit Counter
P1.2 / ECI
16-bit Module 0
16-bit Module 1
16-bit Module 2
16-bit Module 3
16-bit Module 4
P1.3 / CEX0
P1.4 / CEX1
P1.5 / CEX2
P1.6 / CEX3
P1.7 / CEX4
The PCA timer is a common time base for all five modules (See Figure 22). The timer count source is determined
from the CPS1 and CPS0 bits in the CMOD SFR (See Table 25) and can be programmed to run at:
•
•
•
•
1/12 the oscillator frequency. (Or 1/6 in X2 Mode)
1/4 the oscillator frequency. (Or 1/2 in X2 Mode)
The Timer 0 overflow.
The input on the ECI pin (P1.2).
Rev. B - November 10, 2000
47
Preliminary
T80C5111
To PCA
modules
Fosc /12
Fosc / 4
T0 OVF
P1.2
overflow
It
CH
CL
16 bit up/down counter
CMOD
0xD9
CIDL WDTE
CPS1 CPS0 ECF
Idle
CCON
0xD8
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
Figure 22. PCA Timer/Counter
Table 25. CMOD: PCA Counter Mode Register
CMOD
Address 0D9H
CIDL WDTE
-
-
-
CPS1 CPS0
ECF
Reset value
0
0
X
X
X
0
0
0
Symbol
Function
Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during
idle Mode. CIDL = 1 programs it to be gated off during idle.
CIDL
Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4.
WDTE = 1 enables it.
WDTE
a
-
Not implemented, reserved for future use.
CPS1
CPS0
PCA Count Pulse Select bit 1.
PCA Count Pulse Select bit 0.
b
CPS1 CPS0 Selected PCA input.
0
0
1
1
0
1
0
1
Internal clock f /12 ( Or f /6 in X2 Mode).
osc osc
Internal clock f /4 ( Or f /2 in X2 Mode).
osc
osc
Timer 0 Overflow
External clock at ECI/P1.2 pin (max rate = f / 8)
osc
PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an
interrupt. ECF = 0 disables that function of CF.
ECF
a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its
active value will be 1. The value read from a reserved bit is indeterminate.
b.
f
= oscillator frequency
osc
48
Rev. B - November 10, 2000
Preliminary
T80C5111
The CMOD SFR includes three additional bits associated with the PCA (See Figure 22 and Table 25).
•
•
•
The CIDL bit which allows the PCA to stop during idle mode.
The WDTE bit which enables or disables the watchdog function on module 4.
The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set
when the PCA timer overflows.
The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module
(Refer to Table 26).
•
•
Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit.
Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the
ECF bit in the CMOD register is set. The CF bit can only be cleared by software.
•
Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by
hardware when either a match or a capture occurs. These flags also can only be cleared by software.
Table 26. CCON: PCA Counter Control Register
CCON
Address 0D8H
CF
0
CR
0
-
CCF4
0
CCF3
0
CCF2
0
CCF1
0
CCF0
0
Reset value
X
Symbol
Function
PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags
an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but
can only be cleared by software.
CF
PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared
by software to turn the PCA counter off.
CR
-
a
Not implemented, reserved for future use.
PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF4
PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
CCF3
CCF2
CCF1
CCF0
PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be
cleared by software.
a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its
active value will be 1. The value read from a reserved bit is indeterminate.
The watchdog timer function is implemented in module 4 (See Figure 25).
The PCA interrupt system is shown in Figure 23
Rev. B - November 10, 2000
49
Preliminary
T80C5111
CCON
0xD8
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
PCA Timer/Counter
Module 0
Module 1
Module 2
Module 3
To Interrupt
priority decoder
Module 4
CMOD.0
IE.6
EC
IE.7
EA
CCAPMn.0
ECCFn
ECF
Figure 23. PCA Interrupt System
PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform:
•
•
•
•
•
•
16-bit Capture, positive-edge triggered,
16-bit Capture, negative-edge triggered,
16-bit Capture, both positive and negative-edge triggered,
16-bit Software Timer,
16-bit High Speed Output,
8-bit Pulse Width Modulator.
In addition, module 4 can be used as a Watchdog Timer.
Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module
0, CCAPM1 for module 1, etc. (See Table 27). The registers contain the bits that control the mode that each
module will operate in.
•
The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the
CCON SFR to generate an interrupt when a match or compare occurs in the associated module.
•
•
PWM (CCAPMn.1) enables the pulse width modulation mode.
The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there
is a match between the PCA counter and the module's capture/compare register.
•
•
The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there
is a match between the PCA counter and the module's capture/compare register.
The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will
be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both
bits are set both edges will be enabled and a capture will occur for either transition.
•
The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.
Table 28 shows the CCAPMn settings for the various PCA functions.
50
Rev. B - November 10, 2000
Preliminary
T80C5111
Table 27. CCAPMn: PCA Modules Compare/Capture Control Registers
CCAPM0=0DAH
CCAPM1=0DBH
CCAPM2=0DCH
CCAPM3=0DDH
CCAPM4=0DEH
CCAPMn Address
n = 0 - 4
-
ECOMn CAPPn CAPNn MATn
TOGn PWMm ECCFn
Reset value
X
0
0
0
0
0
0
0
Symbol
Function
a
-
Not implemented, reserved for future use.
ECOMn
CAPPn
CAPNn
Enable Comparator. ECOMn = 1 enables the comparator function.
Capture Positive, CAPPn = 1 enables positive edge capture.
Capture Negative, CAPNn = 1 enables negative edge capture.
Match. When MATn = 1, a match of the PCA counter with this module's compare/capture
register causes the CCFn bit in CCON to be set, flagging an interrupt.
MATn
TOGn
PWMn
ECCFn
Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture
register causes the CEXn pin to toggle.
Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width
modulated output.
Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate
an interrupt.
a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family
products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its
active value will be 1. The value read from a reserved bit is indeterminate.
Table 28. PCA Module Modes (CCAPMn Registers)
ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn
Module Function
No Operation
0
0
1
0
0
0
0
0
0
0
0
0
16-bit capture by
trigger on CEXn
a positive-edge
X
X
16-bit capture by a negative trigger on
CEXn
X
X
1
0
1
0
1
1
0
0
0
1
0
0
0
0
0
0
X
X
X
16-bit capture by a transition on CEXn
16-bit Software Timer / Compare
mode.
1
1
1
0
0
0
0
0
0
1
0
1
1
0
0
1
0
X
0
16-bit High Speed Output
8-bit PWM
X
X
Watchdog Timer (module 4 only)
There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and
these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module
is used in the PWM mode these registers are used to control the duty cycle of the output (See Table 29 & Table 30)
Rev. B - November 10, 2000
51
Preliminary
T80C5111
Table 29. CCAPnH: PCA Modules Capture/Compare Registers High
CCAP0H=0FAH
CCAP1H=0FBH
CCAP2H=0FCH
CCAP3H=0FDH
CCAP4H=0FEH
CCAPnH Address
n = 0 - 4
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset value
Table 30. CCAPnL: PCA Modules Capture/Compare Registers Low
CCAP0L=0EAH
CCAP1L=0EBH
CCAP2L=0ECH
CCAP3L=0EDH
CCAP4L=0EEH
CCAPnL Address
n = 0 - 4
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Reset value
Reset value
Reset value
Table 31. CH: PCA Counter High
CH
Address 0F9H
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Table 32. CL: PCA Counter Low
CL
Address 0E9H
7
0
6
0
5
0
4
0
3
0
2
0
1
0
0
0
13.1. PCA Capture Mode
To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for
that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a
valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the
module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the
ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated (Refer to Figure 24).
52
Rev. B - November 10, 2000
Preliminary
T80C5111
CCON
0xD8
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
PCA IT
PCA Counter/Timer
Cex.n
CH
CL
Capture
CCAPnH
CCAPnL
CCAPMn, n= 0 to 4
0xDA to 0xDE
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Figure 24. PCA Capture Mode
13.2. 16-bit Software Timer / Compare Mode
The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules
CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs
an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both
set (See Figure 25).
Rev. B - November 10, 2000
53
Preliminary
T80C5111
CCON
0xD8
CCF4
CF
CR
CCF3 CCF2 CCF1 CCF0
Write to
CCAPnL Reset
PCA IT
Write to
CCAPnH
CCAPnH
CCAPnL
Enable
1
0
Match
16 bit comparator
RESET *
CH
CL
PCA counter/timer
CCAPMn, n = 0 to 4
0xDA to 0xDE
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
CMOD
0xD9
CIDL WDTE
CPS1 CPS0 ECF
* Only for Module 4
Figure 25. PCA Compare Mode and PCA Watchdog Timer
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted
match could happen. Writing to CCAPnH will set the ECOM bit.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur while modifying
the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first,
and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.
13.3. High Speed Output Mode
In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs
between the PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM
bits in the module's CCAPMn SFR must be set (See Figure 26).
A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.
54
Rev. B - November 10, 2000
Preliminary
T80C5111
CCON
CF
CR
CCF4 CCF3 CCF2 CCF1 CCF0
0xD8
Write to
CCAPnL
Reset
PCA IT
Write to
CCAPnH
CCAPnH
CCAPnL
0
Enable
1
Match
16 bit comparator
CEXn
CH
CL
PCA counter/timer
CCAPMn, n = 0 to 4
0xDA to 0xDE
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Figure 26. PCA High Speed Output Mode
Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted
match could happen.
Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur while modifying
the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first,
and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.
13.4. Pulse Width Modulator Mode
All of the PCA modules can be used as PWM outputs. Figure 27 shows the PWM function. The frequency of the
output depends on the source for the PCA timer. All of the modules will have the same frequency of output
because they all share the PCA timer. The duty cycle of each module is independently variable using the module's
capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn
Rev. B - November 10, 2000
55
Preliminary
T80C5111
SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from
FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The
PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode.
CCAPnH
Overflow
CCAPnL
“0”
CEXn
Enable
<
≥
8 bit comparator
“1”
CL
PCA counter/timer
CCAPMn, n= 0 to 4
0xDA to 0xDE
ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn
Figure 27. PCA PWM Mode
13.5. PCA Watchdog Timer
An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing
chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic
discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can
still be used for other modes if the watchdog is not needed. Figure 25 shows a diagram of how the watchdog
works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit
value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This
will not cause the RST pin to be driven high.
In order to hold off the reset, the user has three options:
•
•
•
1. periodically change the compare value so it will never match the PCA timer,
2. periodically change the PCA timer value so it will never match the compare values, or
3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it.
The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program
counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not
recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules;
changing the time base for other modules would not be a good idea. Thus, in most applications the first solution
is the best option.
This watchdog timer won’t generate a reset out on the reset pin.
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Rev. B - November 10, 2000
Preliminary
T80C5111
14. Analog-to-Digital Converter (ADC)
14.1. Introduction
This section describes the on-chip 10 bit analog-to-digital converter of the T80C5111. Eight ADC channels are
available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter
to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bit-
cascaded potentiometric ADC.
Three kind of conversion are available:
•
•
•
Standard conversion (7-8 bits).
Precision conversion (8-9 bits).
Accurate conversion (10 bits).
For the precision conversion, set bits PSIDLE and ADSST in ADCON register to start the conversion. The chip
is in a idle mode, the CPU doesn’t run but the peripherals are always running. This mode allows digital noise to
be lower, to ensure precise conversion.
For the accurate conversion, set bits QUIETM and ADSST in ADCON register to start the conversion. The chip
is in a pseudo-idle mode, the AD is the only peripheral running. This mode allows digital noise to be as low as
possible, to ensure high precision conversion.
For these modes it is necessary to work with end of conversion interrupt, which is the only way to wake up the chip.
If another interrupt occurs during the precision conversion, it will be treated only after this conversion is ended.
14.2. Features
•
•
•
•
•
•
•
•
•
•
•
8 channels with multiplexed inputs
10-bit cascaded potentiometric ADC
Conversion time 40 micro-seconds
Zero Error (offset) +/- 2 LSB max
External Positive Reference Voltage Range 2.4 to Vcc
Internal Positive Reference Voltage 2.4 Volt. If Vref is used as output, the load must be higher than 18 kOhm.
ADCIN Range 0 to Vcc
Integral non-linearity typical 1 LSB, max. 2 LSB
Differential non-linearity typical 0.5 LSB, max. 1 LSB
Conversion Complete Flag or Conversion Complete Interrupt
Selected ADC Clock
14.3. ADC I/O Functions
AINx are general I/O that are shared with the ADC channels. The channel select bit in ADCF register define
which ADC channel pin will be used as ADCIN. The remaining ADC channels pins can be used as general purpose
I/O or as the alternate function that is available. Writes to the port register which aren’t selected by the ADCF
will not have any effect.
Rev. B - November 10, 2000
57
Preliminary
T80C5111
ADCON.5
ADCON.3
ADEN
ADSST
ADCON.4
ADC
Interrupt
Request
ADEOC
CONTROL
CONV_CK
EADC
IE1.1
AIN0/P4.0
AIN1/P4.1
AIN2/P4.2
AIN3/P4.3
AIN4/P4.4
AIN5/P4.5
AIN6/P4.6
AIN7/P4.7
000
001
010
011
100
101
110
111
8
2
ADCIN
ADDH
ADDL
+
-
SAR
AVSS
Sample and Hold
10
R/2R DAC
ADCLK.7
VAGND
ADCON.5
SELREF
ADEN
SCH2
SCH1
SCH0
2.4V
ADCON.2 ADCON.1 ADCON.0
Vref
VADREF
Figure 28. ADC Description
Figure 29 shows the timing diagram of a complete conversion. For simplicity, the figure depicts the waveforms in
idealized form and do not provide precise timing information. For ADC characteristics and timing parameters refer
to the Section “AC Characteristics” of the T80C5111 datasheet.
CONV_CK
ADEN
T
SETUP
ADSST
ADEOC
T
CONV
Figure 29. Timing Diagram
NOTE:
Tsetup = 4 us
14.4. ADC Converter Operation
A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).
The busy flag ADSST(ADCON.3) remains set as long as an A/D conversion is running. After completion of the
A/D conversion, it is cleared by hardware. When a conversion is running, this flag can be read only, a write has
no effect.
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Rev. B - November 10, 2000
Preliminary
T80C5111
The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is available in ADDH and
ADDL, it is cleared by software. If the bit EADC (IE1.1) is set, an interrupt occur when flag ADEOC is set (see
Figure 31). Clear this flag for re-arming the interrupt.
The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection.
Before starting normal power reduction modes the ADC conversion has to be completed.
Table 33. Selected Analog input
SCH2
SCH1
SCH0
Selected Analog input
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
14.5. Voltage Conversion
When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If the input voltage
equals VAGND, the ADC converts it to 000h. Input voltage between VAREF and VAGND are a straight-line
linear conversion. All other voltages will result in 3FFh if greater than VAREF and 000h if less than VAGND.
Note that ADCIN should not exceed VAREF absolute maximum range.
14.6. Clock Selection
The maximum clock frequency for ADC (CONV_CK for Conversion Clock) is defined in the AC characteristics
section. A prescaler is featured (ADCCLK) to generate the CONV_CK clock from the oscillator frequency.
CONV_CK
CKADC
Prescaler ADCLK
/ 2
A/D
Converter
Figure 30. A/D Converter clock
Rev. B - November 10, 2000
59
Preliminary
T80C5111
14.7. ADC Standby Mode
When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register.
In this mode the power dissipation is about 1uW.
14.8. Voltage referencee
The voltage reference can be either internal or external.
As input, the Vref pin is used to enter the voltage reference for the A/D conversion.
When the voltage reference is active, the Vref pin is an output. This voltage can be used for the A/D and for any
other application requiring a voltage independant from the power supply. Voltage typical value is 2.4 volt and the
load must greater than 18 kOms.
14.9. IT ADC management
An interrupt end-of-conversion will occurs when the bit ADEOC is actived and the bit EADC is set. For re-arming
the interrupt the bit ADEOC must be cleared by software.
ADCI
ADEOC
ADCON.2
EADC
IE1.1
Figure 31. ADC interrupt structure
14.10. Registers
Table 34. ADCON Register
ADCON (S:F3h)
ADC Control Register
7
6
5
4
3
2
1
0
QUIETM
PSIDLE
ADEN
ADEOC
ADSST
SCH2
SCH1
SCH0
Bit Number Bit Mnemonic
Description
Pseudo Idle mode (best precision)
Set to put in quiet mode during conversion.
7
6
QUIETM
PSIDLE
Cleared by hardware after completion of the conversion.
Pseudo Idle mode (good precision)
Set to put in idle mode during conversion.
Cleared by hardware after completion of the conversion.
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Rev. B - November 10, 2000
Preliminary
T80C5111
Bit Number Bit Mnemonic
Description
Enable/Standby Mode
5
4
ADEN
Set to enable ADC.
Clear for Standby mode (power dissipation 1 uW).
End Of Conversion
ADEOC
Set by hardware when ADC result is ready to be read. This flag can generate an interrupt.
Must be cleared by software.
Start and Status
3
ADSST
SCH2:0
Set to start an A/D conversion.
Cleared by hardware after completion of the conversion.
Selection of channel to convert
2-0
see Table 33.
Reset Value=X000 0000b
Table 35. ADCLK Register
ADCLK (S:F2h)
ADC Clock Prescaler
7
6
5
4
3
2
1
0
SELREF
PRS 6
PRS 5
PRS 4
PRS 3
PRS 2
PRS 1
PRS 0
Bit Number Bit Mnemonic
Description
Selection and activation of the internal 2.4V voltage reference
Set to enable the internal voltage reference.
7
SELREF
Clear to disable the internal voltage reference.
Clock Prescaler
f
= f
/ (2 * PRS)
CkADC
CONV_CK
6-0
PRS6:0
if PRS=0, f
= f
/ 256
CONV_CK
CkADC
Reset Value: 0000 0000b
Table 36. ADDH Register
ADDH (S:F5h Read Only)
ADC Data High byte register
7
6
5
4
3
2
1
0
ADAT 9
ADAT 8
ADAT 7
ADAT 6
ADAT 5
ADAT 4
ADAT 3
ADAT 2
Bit Number Bit Mnemonic
Description
ADC result
7-0
ADAT9:2
bits 9-2
Read only register
Reset Value: 00h
Rev. B - November 10, 2000
61
Preliminary
T80C5111
Table 37. ADDL Register
ADDL (S:F4h Read Only)
ADC Data Low byte register
7
-
6
-
5
-
4
-
3
-
2
-
1
0
ADAT 1
ADAT 0
Bit Number Bit Mnemonic
Description
Reserved
7-6
1-0
-
The value read from these bits are indeterminate. Do not set these bits.
ADC result
ADAT1:0
bits 1-0
Read only register
Reset Value: xxxx xx00b
Table 38. ADCF Register
ADCF (S:F6h)
ADC Input Select Register
7
6
5
4
3
2
1
0
SEL7
SEL6
SEL5
SEL4
SEL3
SEL2
SEL1
SEL0
Bit Number Bit Mnemonic
Description
Select Input 7-0
7-0
SEL7-0
Set to select bit 7-0 as possible input for A/D
Cleared to leave this bit free for other function
Reset Value=0000 0000b
62
Rev. B - November 10, 2000
Preliminary
T80C5111
15. Interrupt System
The T80C5111 has a total of 8 interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts
(timers 0, 1), serial port interrupt, PCA, SPI and A/D. These interrupts are shown in Figure 32..
High priority
IPH, IP
interrupt
3
INT0
IE0
IE1
0
3
0
3
0
3
0
TF0
INT1
TF1
Interrupt
polling
sequence
CF
3
PCA
0
CCFx
3
RI
TI
0
3
0
NC
3
SPI
0
3
ADC
0
Global
disable
Individual
enable
Low priority
interrupt
Figure 32. Interrupt Control System
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt
Enable register (See Table 41.). This register also contains a global disable bit, which must be cleared to disable
all interrupts at once.
Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a
bit in the Interrupt Priority register (See Table 43.) and in the Interrupt Priority High register (See Table 45.).
Table 39. shows the bit values and priority levels associated with each combination.
Rev. B - November 10, 2000
63
Preliminary
T80C5111
Table 39. Priority bit level values
IP.x
IPH.x
Interrupt Level Priority
0
0
1
1
0
1
0
1
0 (Lowest)
1
2
3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt.
A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level
is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 40. Address vectors
Interrupt Address
Interrupt Name
Priority Number
Vector
external interrupt (INT0)
Timer0 (TF0)
0003h
000Bh
0013h
001Bh
0033h
0023h
004Bh
0043h
1
2
3
4
5
6
8
9
external interrupt (INT1)
Timer1 (TF1)
PCA (CF or CCFn)
UART (RI or TI)
SPI
ADC
64
Rev. B - November 10, 2000
Preliminary
T80C5111
Table 41. IE Register
IE - Interrupt Enable Register (A8h)
7
6
5
4
3
2
1
0
EA
EC
-
ES
ET1
EX1
ET0
EX0
Bit
Mnemonic
Bit Number
Description
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
7
EA
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt
enable bit.
PCA Interrupt Enable
Clear to disable the the PCA interrupt.
Set to enable the the PCA interrupt.
Reserved
6
5
4
EC
-
The value read from this bit is indeterminate. Do not set this bit.
Serial port Enable bit
ES
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
Timer 1 overflow interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
3
2
1
0
ET1
EX1
ET0
EX0
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
Timer 0 overflow interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
Reset Value = 00X0 0000b
Bit addressable
Rev. B - November 10, 2000
65
Preliminary
T80C5111
Table 42. IE1 Register
IE1 (S:C0h)
Interrupt Enable Register
7
-
6
-
5
-
4
-
3
-
2
1
0
-
ESPI
EADC
Bit
Mnemonic
Bit Number
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
SPI Interrupt Enable bit
7
6
5
4
3
-
-
-
-
-
2
ESPI
Clear to disable the SPI interrupt.
Set to enable the SPI interrupt.
A/D Interrupt Enable bit
Clear to disable the ADC interrupt.
Set to enable the ADC interrupt.
1
0
EADC
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = XXXX X00Xb
No Bit addressable
66
Rev. B - November 10, 2000
Preliminary
T80C5111
Table 43. IPL0 Register
IPL0 - Interrupt Priority Register (B8h)
7
6
5
4
3
2
1
0
-
PPC
-
PS
PT1
PX1
PT0
PX0
Bit
Mnemonic
Bit Number
Description
Reserved
7
6
5
4
3
2
1
0
-
The value read from this bit is indeterminate. Do not set this bit.
PCA Counter Interrupt Priority bit
PPCL
-
Refer to PPCH for priority level
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Serial port Priority bit
PSL
Refer to PSH for priority level.
Timer 1 overflow interrupt Priority bit
PT1L
PX1L
PT0L
PX0L
Refer to PT1H for priority level.
External interrupt 1 Priority bit
Refer to PX1H for priority level.
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
External interrupt 0 Priority bit
Refer to PX0H for priority level.
Reset Value = X0X0 0000b
Bit addressable.
Rev. B - November 10, 2000
67
Preliminary
T80C5111
Table 44. IPL1 Register
IPL1 - Interrupt Priority Low Register 1 (S:B2h)
7
6
5
4
3
2
1
0
-
-
-
-
-
PSPI
PADC
-
Bit
Mnemonic
Bit Number
Description
7
6
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
-
5
4
3
2
1
0
-
-
-
PSPI
PADC
-
The value read from this bit is indeterminate. Do not set this bit.
SPI Interrupt Priority level less significant bit.
Refer to PSPIH for priority level.
ADC Interrupt Priority level less significant bit.
Refer to PADCH for priority level.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = XXXX X00Xb
Not Bit addressable.
68
Rev. B - November 10, 2000
Preliminary
T80C5111
Table 45. IPH0 Register
IPH0 - Interrupt Priority High Register (B7h)
7
6
5
4
3
2
1
0
-
PPCH
-
PSH
PT1H
PX1H
PT0H
PX0H
Bit
Mnemonic
Bit Number
Description
Reserved
7
-
The value read from this bit is indeterminate. Do not set this bit.
PCA Counter Interrupt Priority level most significant bit
PPCH PPC
Priority level
Lowest
0
0
1
1
0
1
0
1
6
5
4
PPCH
Highest priority
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Serial port Priority High bit
PSH PS Priority Level
0
0
Lowest
PSH
0
1
1
1
0
1
Highest
Timer 1 overflow interrupt Priority High bit
PT1H PT1
Priority Level
Lowest
0
0
1
1
0
1
0
1
3
2
1
0
PT1H
PX1H
PT0H
PX0H
Highest
External interrupt 1 Priority High bit
PX1H PX1
Priority Level
Lowest
0
0
1
1
0
1
0
1
Highest
Timer 0 overflow interrupt Priority High bit
PT0H PT0
Priority Level
0
0
1
1
0
Lowest
1
0
1
Highest
External interrupt 0 Priority High bit
PX0H PX0
Priority Level
Lowest
0
0
1
1
0
1
0
1
Highest
Reset Value = X0X0 0000b
Not bit addressable
Rev. B - November 10, 2000
69
Preliminary
T80C5111
Table 46. IPH1 Register
IPH1 - Interrupt Priority High Register 1 (B3h)
7
6
5
4
3
2
1
0
-
-
-
-
-
PSPIH
PADCH
-
Bit
Mnemonic
Bit Number
Description
7
6
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
-
-
-
-
5
4
3
The value read from this bit is indeterminate. Do not set this bit.
SPI Interrupt Priority level most significant bit
PSPIH
PSPI Priority level
0
0
1
1
0Lowest
1
0
2
PSPIH
1Highest
ADC Interrupt Priority level most significant bit
PADCH
PADC
0Lowest
Priority level
0
0
1
1
1
0
PADCH
1
0
1Highest
Reserved
-
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = XXXX X00Xb
Not bit addressable
70
Rev. B - November 10, 2000
Preliminary
T80C5111
16. ROM
16.1. ROM Structure
The T80C5111 ROM memory is divided in three different arrays:
•
•
•
the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Kbytes.
the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes.
the signature array:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes.
16.2. ROM Lock System
The program Lock system, when programmed, protects the on-chip program against software piracy.
16.2.1. Encryption Array
Within the ROM array are 64 bytes of encryption array. Every time a byte is addressed during program verify, 6
address lines are used to select a byte of the encryption array. This byte is then exclusive-NOR’ed (XNOR) with
the code byte, creating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed
state, will return the code in its original, unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying
the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a
verification routine will display the content of the encryption array. For this reason all the unused code bytes
should be programmed with random values.
16.2.2. Configuration byte
The configuration byte is a special register. Its content, described in paragraph 6.6.1. is defined by the diffusion
mask in the ROM version or written by the OTP programmer in the OTP version.
The lock bits when programmed according to Table 41. will provide different level of protection for the on-chip
code and data.
Table 47. Program Lock bits
Program Lock Bits
Protection description
Security
level
LB1
LB2
1
U
U
No program lock features enabled. Code verify will still be encrypted by the encryption array
if programmed. MOVC instruction returns non encrypted data.
2
3
P
U
P
Same as 1
U
Same as 2, also verify is disabled
This security level is available because ROM integrity will be verified thanks to another
method*.
U: unprogrammed
P: programmed
*Warning: When security bit is set, ROM contend cannot be verified. Only the CRC is verified.
16.2.3. Signature bytes
The T80C5111 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described
in Section “Signature bytes content”, page 89.
16.2.4. Verify Algorithm
Refer to Section “Verifying algorithm”, page 85
Rev. B - November 10, 2000
71
Preliminary
T80C5111
16.3. Program code mapping
As there is no external capability in LPC packages, the code size is limited to 4 Kbytes. Any access above 4K
will be mapped in the first 4K segment (0XXXh).
72
Rev. B - November 10, 2000
Preliminary
T80C5111
17. EPROM
17.1. EPROM Programming
Specific algorithm is implemented,. Pleas use qualified device programmers from third party vendors.
17.2. EPROM Erasure (Windowed Packages Only)
Erasing the EPROM erases the code array, the encryption array and the lock bits returning the parts to full
functionality.
Erasure leaves all the EPROM cells in a 1’s state (FF).
17.2.1. Erasure Characteristics
The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an integrated dose at least 15
2
2
W-sec/cm . Exposing the EPROM to an ultraviolet lamp of 12,000 µW/cm rating for 30 minutes, at a distance
of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers.
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately
4,000 Å. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources
over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause
inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque
label be placed over the window.
17.3. Signature Bytes
17.3.1. Signature bytes content
The T80C5111 has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes follow the procedure
for EPROM signature bytes reading. Table 48. shows the content of the signature byte for the T80C5111.
Table 48. Signature Bytes Content
Location
Contents
Comment
30h
31h
60h
60h
61h
58h
57h
Manufacturer Code: Atmel Wireless & Microcontrollers
Family Code: C51 X2
2Eh
AEh
EFh
Product name: T80C5111 4K ROM version
Product name: T80C5111 4K OTP version
Product revision number : T80C5111 Rev.0
Rev. B - November 10, 2000
73
Preliminary
T80C5111
18. Electrical Characteristics
(1)
18.1. Absolute Maximum Ratings
Ambiant Temperature Under Bias:
C = commercial 0°C to 70°C
I = industrial -40°C to 85°C
Storage Temperature-65°C to + 150°C
Voltage on V to V -0.5 V to + 7 V
CC
SS
Voltage on V to V -0.5 V to + 13 V
PP
SS
Voltage on Any Pin to V -0.5 V to V + 0.5 V
SS
CC
(2)
Power Dissipation1 W
NOTES
1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions may affect device reliability.
2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
18.2. Power consumption measurement
Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset,
which made sense for the designs were the CPU was running under reset. In our new devices, the CPU is no more
active during reset, so the power consumption is very low but is not really representative of what will happen in
the customer system. That’s why, while keeping measurements under Reset, we present a new way to measure the
operating Icc:
Using an internal test ROM, the following code is executed:
Label: SJMP Label (80 FE)
Ports 1, 3, 4 are disconnected, RST = Vcc, XTAL2 is not connected and XTAL1 is driven by the clock.
This is much more representative of the real operating Icc.
74
Rev. B - November 10, 2000
Preliminary
T80C5111
18.3. DC Parameters for Standard Voltage
TA = 0°C to +70°C; V = 0 V; V = 5 V ± 10%; F = 0 to 40 MHz.
SS
CC
TA = -40°C to +85°C; V = 0 V; V = 5 V ± 10%; F = 0 to 40 MHz.
SS
CC
Table 49. DC Parameters in Standard Voltage
Symbol
Parameter
Min
Typ
Max
Unit
V
Test Conditions
V
Input Low Voltage
-0.5
0.2 V - 0.1
CC
IL
V
Input High Voltage except XTAL1, RST
Input High Voltage, XTAL1, RST
0.2 V + 0.9
V
+ 0.5
+ 0.5
V
IH
CC
CC
CC
V
0.7 V
V
V
IH1
CC
(6)
V
0.3
V
V
V
I
I
I
= 100 µA
= 1.6 mA
= 3.5 mA
OL
Output Low Voltage, ports 1, 3, 4.
OL
OL
OL
0.45
1.0
(6)
V
V
V
V
- 0.3
- 0.7
- 1.5
V
V
V
I
I
I
= -10 µA
= -30 µA
= -60 µA
OH
Output High Voltage, ports 1, 3, 4.
mode pseudo bidirectionnel
CC
CC
CC
OH
OH
OH
V
= 5 V ± 10%
CC
(6)
V
R
V
V
V
- 0.3
- 0.7
- 1.5
V
V
V
I
I
I
= -100 µA
= -1.6 mA
= -3.2 mA
= 5 V ± 10%
OH2
Output High Voltage, ports 1, 3, 4.
mode Push pull
CC
CC
CC
OH
OH
OH
V
CC
(5)
RST Pullup Resistor
50
200
kΩ
RST
90
I
Logical 0 Input Current ports 1, 3 and 4
-50
TBD
±10
µA Vin = 0.45 V, port 1 & 3
IL
Vin = 0.45 V, port 4
I
Input Leakage Current
µA 0.45 V < Vin < V
µA Vin = 2.0 V
LI
CC
I
Logical 1 to 0 Transition Current, ports 1, 3, 4
Capacitance of I/O Buffer
-650
10
TL
C
pF Fc = 1 MHz
IO
TA = 25°C
(5)
(3)
I
Power Down Current
to be confirmed
50
µA
PD
20
2.0 V < V
5.5 V
CC <
I
Power Supply Current Maximum values, X1
mode:
to be con-
firmed
3+ 0.4 Freq
(MHz)
@12MHz 5.8
CC
(7)
(1)
V
= 5.5 V
under
RESET
CC
mA
mA
@16MHz 7.4
I
Power Supply Current Maximum values, X1
to be con-
firmed
3 + 0.6 Freq
(MHz)
@12MHz 10.2
CC
(7)
(8)
mode:
operating
V
V
= 5.5 V
CC
@16MHz 12.6
I
Power Supply Current Maximum values, X1
to be con-
firmed
3+0.3 Freq
(MHz)
CC
(7)
(2)
mode:
mA
idle
= 5.5 V
CC
@12MHz 3.9
@16MHz 5.1
V
Supply voltage during power down mode
High threshold of Power Fail Detect
Low threshold of Power Fail Detect
2
V
V
V
RET
V
2.54
RST+
V
2.19
RST
18.4. DC Parameters for Low Voltage
TA = 0°C to +70°C; V = 0 V; V = 2.7 V to 5.5 V; F = 0 to 30 MHz.
SS
CC
TA = -40°C to +85°C; V = 0 V; V = 2.7 V to 5.5 V; F = 0 to 30 MHz.
SS
CC
Rev. B - November 10, 2000
75
Preliminary
T80C5111
Table 50. DC Parameters for Low Voltage
Symbol
Parameter
Min
Typ
Max
Unit
V
Test Conditions
V
Input Low Voltage
-0.5
0.2 V - 0.1
CC
IL
V
Input High Voltage except XTAL1, RST
Input High Voltage, XTAL1, RST
0.2 V + 0.9
V
+ 0.5
+ 0.5
V
IH
CC
CC
CC
V
0.7 V
V
V
IH1
CC
(6)
V
0.3
V
V
V
I
I
I
=
OL
Output Low Voltage, ports 1, 3, 4
OL
OL
OL
0.45
1.0
= 0.8 mA
=
(6)
V
0.9 V
V
V
V
I
I
I
= -10 µA
= - mA
= - mA
OH
Output High Voltage, ports 1, 3, 4.
CC
OH
OH
OH
V
V
- 0.7
- 1.5
CC
CC
(6)
V
0.9V
V
V
V
I
I
I
= -100 µA
= - mA
OH2
Output High Voltage, ports 1, 3, 4.
mode Push pull
CC
OH
OH
OH
V
V
- 0.7
- 1.5
CC
CC
= - mA
I
Logical 0 Input Current ports 1, 2 and 3
-50
TBD
±10
µA Vin = 0.45 V, port 1 & 3
IL
Vin = 0.45 V, port 4
I
Input Leakage Current
µA 0.45 V < Vin < V
µA Vin = 2.0 V
kΩ
LI
CC
I
Logical 1 to 0 Transition Current, ports 1, 3, 4
RST Pullup Resistor
-650
200
10
TL
(5)
R
50
RST
90
CIO
Capacitance of I/O Buffer
pF Fc = 1 MHz
TA = 25°C
(5)
(3)
(3)
I
Power Down Current
to be confirmed
50
30
µA
PD
20
V
= 2.0 V to 5.5 V
= 2.0 V to 3.3 V
CC
CC
(5)
10
V
I
Power Supply Current Maximum values, X1
mode:
to be con- 1.5 + 0.2 Freq
CC
(7)
(1)
firmed
(MHz)
V
= 3.3 V
under
RESET
CC
CC
@12MHz 3.4
@16MHz 4.2
mA
I
Power Supply Current Maximum values, X1
to be con- 1.5 + 0.3 Freq
CC
(7)
(8)
firmed
(MHz)
mode:
V
= 3.3 V
operating
@12MHz 4.6
@16MHz 5.8
mA
mA
I
Power Supply Current Maximum values, X1
to be con- 1.5+0.15 Freq
CC
(7)
firmed
(MHz)
(2)
mode:
idle
V
= 3.3 V
CC
@12MHz 2
@16MHz 2.6
V
Supply voltage during power down mode
High threshold of Power Fail Detect
Low threshold of Power Fail Detect
2
V
V
V
RET
V
2.54
RST+
V
2.19
RST
NOTES
1.
I
under reset is measured with all output pins disconnected; XTAL1 driven with T
, T
= 5 ns (see Figure 37.), V = V + 0.5 V,
CC
CLCH CHCL IL SS
V
= V - 0.5V; XTAL2 N.C.; Vpp = RST = V . I would be slightly higher if a crystal oscillator used
CC CC CC
IH
2. Idle I is measured with all output pins disconnected; XTAL1 driven with T
, T
= 5 ns, V = V + 0.5 V, V = V - 0.5 V; XTAL2
CC
CLCH CHCL IL SS IH CC
N.C; Vpp = RST = V (see Figure 35.).
SS
3. Power Down I is measured with all output pins disconnected; Vpp = V ; XTAL2 NC.; RST = V (see Figure 36.).
CC
SS
SS
4. Not Applicable
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V.
6. If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test
OL
OL
conditions.
7. For other values, please contact your sales office.
8. Operating I is measured with all output pins disconnected; XTAL1 driven with T
, T
= 5 ns (see Figure 37.), V = V + 0.5 V,
IL SS
CC
CLCH CHCL
V
= V - 0.5V; XTAL2 N.C.; RST/Vpp= V ;. The internal ROM runs the code 80 FE (label: SJMP label). I would be slightly higher if a crystal
CC CC CC
IH
oscillator is used. Measurements are made with OTP products when possible, which is the worst case.
76
Rev. B - November 10, 2000
Preliminary
T80C5111
V
CC
I
CC
V
CC
RST
XTAL2
XTAL1
(NC)
CLOCK
V
SIGNAL
SS
All other pins are disconnected.
Figure 33. I
Test Condition, under reset
CC
V
CC
I
CC
V
CC
Reset = Vss after a high pulse
during at least 24 clock cycles
V
CC
RST
XTAL2
XTAL1
(NC)
CLOCK
All other pins are disconnected.
SIGNAL
V
SS
Figure 34. Operating I
Test Condition
CC
V
CC
I
CC
Reset = Vss after a high pulse
during at least 24 clock cycles
V
CC
V
CC
RST
(NC)
XTAL2
XTAL1
CLOCK
SIGNAL
All other pins are disconnected.
V
SS
Figure 35. I
Test Condition, Idle Mode
CC
Rev. B - November 10, 2000
77
Preliminary
T80C5111
V
CC
I
CC
V
CC
Reset = Vss after a high pulse
during at least 24 clock cycles
V
CC
RST
All other pins are disconnected.
XTAL2
XTAL1
V
SS
Figure 36. I
Test Condition, Power-Down Mode
CC
V
-0.5V
CC
0.7V
CC
0.45V
0.2V -0.1
CC
T
T
CLCH
CHCL
T
= T
= 5ns.
CHCL
CLCH
Figure 37. Clock Signal Waveform for I
Tests in Active and Idle Modes
CC
18.5. DC Parameters for A/D Converter
TA = 0°C to +70°C; V = 0 V; V = 2.7 V to 5.5 V; F = 0 to 30 MHz.
SS
CC
TA = -40°C to +85°C; V = 0 V; V = 2.7 V to 5.5 V; F = 0 to 30 MHz.
SS
CC
Table 51. DC Parameters for Low Voltage
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
Resolution
10
bit
V
AVin
Rref
Vref
Analog input voltage
Vss- 0.2
13
Vcc + 0.2
24
Resistance between Vref and Vss
Value of integrated voltage source
18
KOhm
V
2.43
2.49
Small variation with Vcc
and Temperature (1)
Lref
Cai
Load on integrated voltage source
Analog input Capacitance
Integral non linearity
10
KOhm
60
1
pF During sampling
2
1
2
1
lsb
lsb
lsb
Differential non linearity
Offset error
0.5
-2
Input source impedance
KOhm For 10 bit resolution at
maximum speed
Notes: (1) Total drift on one part over full Voltage and Temperature range is below 20 mV. .
18.6. AC Parameters
18.6.1. Explanation of the AC Symbols
Each timing symbol has 5 characters. The first character is always a “T” (stands for Time). The other characters,
depending on their positions, stand for the name of a signal or the logical status of that signal. The following is
a list of all the characters and what they stand for.
78
Rev. B - November 10, 2000
Preliminary
T80C5111
Example:T
= Time from clock rising edge to input data valid.
XHDV
TA = 0 to +70°C (commercial temperature range); V = 0 V; V = 5 V ± 10%; -V ranges.
SS
CC
TA = 0 to +70°C (commercial temperature range); V = 0 V; 2.7 V < V
5.5 V; -L range.
SS
CC <
TA = -40°C to +85°C (industrial temperature range); V = 0 V; 2.7 V < V
5.5 V; -L range.
SS
CC <
Table 52. gives the maximum applicable load capacitance for Port 1, 3 and 4. Timings will be guaranteed if these
capacitances are respected. Higher capacitance values can be used, but timings will then be degraded.
Table 52. Load Capacitance versus speed range, in pF
-V
-L
50
80
Port 1, 3 & 4
Table 54.gives the description of each AC symbols.
Table 55. gives for each range the AC parameter.
Table 56. gives the frequency derating formula of the AC parameter. To calculate each AC symbols, take the x
value corresponding to the speed grade you need (-V or -L) and replace this value in the formula. Values of the
frequency must be limited to the corresponding speed grade:
Table 53. Max frequency for derating formula regarding the speed grade
-V X1 mode
-V X2 mode
-L X1 mode
-L X2 mode
40
25
33
30
40
25
20
50
Freq (MHz)
T (ns)
Example:
E6
T
in X2 mode for a -V part at 20 MHz (T = 1/20 = 50 ns):
XHDV
x= 133 (Table 56.)
T= 50ns
T
= 5T - x = 5 x 50 - 133 = 117ns
XHDV
18.6.2. Serial Port Timing - Shift Register Mode
Table 54. Symbol Description
Symbol
Parameter
T
T
T
T
T
Serial port clock cycle time
XLXL
QVHX
XHQX
XHDX
XHDV
Output data set-up to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
Clock rising edge to input data valid
Rev. B - November 10, 2000
79
Preliminary
T80C5111
Table 55. AC Parameters for a Fix Clock
Speed
-V
-V
-L
-L
X2 mode
33 MHz
standard mode
40 MHz
X2 mode
20 MHz
standard mode
40 MHz
Units
66 MHz equiv.
40 MHz equiv.
Symbol
Min
180
100
10
Max
Min
300
200
30
Max
Min
300
200
30
Max
Min
300
200
30
Max
T
ns
ns
ns
ns
ns
XLXL
QVHX
XHQX
XHDX
XHDV
T
T
T
T
0
0
0
0
17
117
117
117
Table 56. AC Parameters for a Variable Clock: derating formula
Symbol
Type
Standard X2 Clock
Clock
-V
-L
Units
T
Min
Min
Min
Min
Max
12 T
10 T - x
2 T - x
x
6 T
5 T - x
T - x
x
ns
ns
ns
ns
ns
XLXL
QVHX
XHQX
XHDX
XHDV
T
T
T
T
50
20
0
50
20
0
10 T - x
5 T- x
133
133
18.6.3. Shift Register Timing Waveforms
INSTRUCTION
CLOCK
0
1
2
3
4
5
6
7
8
T
XLXL
T
T
QVXH
XHQX
0
1
2
3
4
5
6
7
OUTPUT DATA
T
SET TI
XHDX
VALID
T
XHDV
WRITE to SBUF
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
CLEAR RI
Figure 38. Shift Register Timing Waveforms
18.6.4. External Clock Drive Characteristics (XTAL1)
Symbol
Parameter
Min
25
5
Max
Units
ns
T
Oscillator Period
High Time
Low Time
CLCL
T
ns
CHCX
T
T
T
5
ns
CLCX
CLCH
CHCL
Rise Time
5
5
ns
Fall Time
ns
T
/T
Cyclic ratio in X2 mode
40
60
%
CHCX CLCX
80
Rev. B - November 10, 2000
Preliminary
T80C5111
18.6.5. External Clock Drive Waveforms
V
-0.5 V
CC
0.7V
CC
0.2V -0.1 V
0.45 V
T
CHCX
CC
T
T
T
CHCL
CLCH
CLCX
T
CLCL
Figure 39. External Clock Drive Waveforms
18.6.6. A/D comverter
Symbol
Parameter
Min
Typ
Max
Units
Conversion time
11
Clock periods (1 for sam-
pling, 10 for conversion)
Fconv_ck
Clock Conversion frequency
Sampling frequency
350 (1)
32
kHz
kHz
8
Notes: (1)For 10 bits resolution
18.6.7. AC Testing Input/Output Waveforms
V
-0.5 V
CC
0.2V +0.9
CC
INPUT/OUTPUT
0.2V -0.1
CC
0.45 V
Figure 40. AC Testing Input/Output Waveforms
AC inputs during testing are driven at V - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement
CC
are made at V min for a logic “1” and V max for a logic “0”.
IH
IL
18.6.8. Float Waveforms
FLOAT
V
-0.1 V
+0.1 V
OH
V
V
V
+0.1 V
-0.1 V
LOAD
LOAD
LOAD
V
OL
Figure 41. Float Waveforms
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins
to float when a 100 mV change from the loaded V /V level occurs. I /I
≥ ± 20mA.
OH OL
OL OH
Rev. B - November 10, 2000
81
Preliminary
T80C5111
18.6.9. Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two.
STATE1
P1P2
STATE2
P1P2
STATE3
P1P2
STATE4
P1P2
STATE4
P1P2
STATE5
P1P2
STATE6
P1P2
STATE5
P1P2
INTERNAL
CLOCK
XTAL2
PORT OPERATION
OLD DATA
NEW DATA
P1, P3, P4 PINS SAMPLED
RXD SAMPLED
P1, P3, P4 PINS SAMPLED
MOV DEST PORT (P1, P3, P4)
(INCLUDES INT0, INT1, TO, T1)
RXD SAMPLED
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
Figure 42. Clock Waveforms
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (T =25°C fully loaded)
A
RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays
are incorporated in the AC specifications.
82
Rev. B - November 10, 2000
Preliminary
T80C5111
19. Ordering Information
-3Z
T
87C5111
R
C
V
Packages:
TD : SO24
TG : SO20
3Z: DIL24
CZ: CDIL24 window*
IB: SSOP16
Conditioning
S: Stick
R:Tape & Reel
U: Stick and Dry Pack
F:Tape & Reel and
Dry Pack
V:VCC: 5V +/- 10%
L: VCC: 2.7-5.5 V
Part Number
83C5111 zzz (4k ROM, zzz is the customer code)
Temperature Range
C:Commercial 0 to 70oC
I:Industrial -40 to 85oC
E: Engineering samples
87C5111(4kOTP, zzz isthecustomercodeif factoryprogrammed)
(*) Check with Atmel Wireless & Microcontrollers Sales Office for availability
Table 57. Maximum Clock Frequency
Code
-V
-L
Unit
Standard Mode, oscillator frequency
Standard Mode, internal frequency
40
40
40
40
MHz
X2 Mode, oscillator frequency
X2 Mode, internal equivalent frequency
33
66
20
40
MHz
Notes: -L parts supplied vith 5V +-10% have same speed and timing as -V parts
Rev. B - November 10, 2000
83
Preliminary
T80C5111
Table 58. Possible order entries
Exten-
sion
Type
T83C5111
Mask ROM
T87C5111
OTP
-3ZSCL DIL24, Stick, Comm. 2.7-5.5V, 40 MHz
-3ZSCV DIL24, Stick, Comm. 5V, 66MHz
-3ZSIL
DIL24, Stick, Ind. 2.7-5.5V, 40 MHz
X
X
X
X
X
X
-TDSCL SO24, Stick, Comm. 2.7-5.5V, 40 MHz
-TDSCV SO24, Stick, Comm. 5V, 66MHz
-TDSIL SO24, Stick, Ind. 2.7-5.5V, 40 MHz
-TDRCL SO24, Tape & Reel, Comm. 2.7-5.5V, 40 MHz
-TDRCV SO24, Tape & Reel, Comm. 5V, 66MHz
-TDRIL SO24, Tape & Reel, Ind. 2.7-5.5V, 40 MHz
-TGSCL SO20, Stick, Comm. 2.7-5.5V, 40 MHz
-TGSCV SO20, Stick, Comm. 5V, 66MHz
-TGSIL SO20, Stick, Ind. 2.7-5.5V, 40 MHz
-TGRCL SO20, Tape & Reel, Comm. 2.7-5.5V, 40 MHz
-TGRCV SO20, Tape & Reel, Comm. 5V, 66MHz
-TGRIL SO20, Tape & Reel, Ind. 2.7-5.5V, 40 MHz
-IBUCL SSOP16, Stick & Dry Pack, Comm. 2.7-5.5V, 40 MHz
-IBUCV SSOP16, Stick & Dry Pack, Comm. 5V, 66MHz
-IBUIL
SSOP16, Stick & Dry Pack, Ind. 2.7-5.5V, 40 MHz
X
X
X
X
-IBFCL SSOP16, Tape & Reel & Dry Pack, Comm. 2.7-5.5V, 40 MHz
-IBFCV SSOP16, Tape & Reel & Dry Pack, Comm. 5V, 66MHz
-IBFIL
SSOP16, Tape & Reel & Dry Pack, Ind. 2.7-5.5V, 40 MHz
-ICUCL SSOP24, Stick & Dry Pack, Comm. 2.7-5.5V, 40 MHz
-ICUCV SSOP24, Stick & Dry Pack, Comm. 5V, 66MHz
-ICUIL
SSOP24, Stick & Dry Pack, Ind. 2.7-5.5V, 40 MHz
-ICFCL SSOP24, Tape & Reel & Dry Pack, Comm. 2.7-5.5V, 40 MHz
-ICFCV SSOP24, Tape & Reel & Dry Pack, Comm. 5V, 66MHz
-ICFIL
SSOP24, Tape & Reel & Dry Pack, Ind. 2.7-5.5V, 40 MHz
-TDSEL Engineering sample, SO24, Stick, 2.7-5.5V, 40MHz
X
X
-CZSEL Engineering sample, Ceramic windowed DIL24, Stick, 2.7-5.5V, 40MHz
84
Rev. B - November 10, 2000
Preliminary
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