T87C5112-S3SIV_技术文档

T80C5112

8-bit Microcontroller with A/D converter

1. Description

The T80C5112 is a high performance ROM/OTP version improvement mechanism. The X2 feature allows to keep

of the 80C51 8-bit microcontroller.

the same CPU power at a divided by two oscillator

frequency.

The T80C5112 retains all the features of the standard

80C51 with 8 Kbytes ROM/OTP program memory, 256 The fully static design of the T80C5112 allows to reduce

bytes of internal RAM, a 8-source , 4-level interrupt system power consumption by bringing the clock

system, an on-chip oscillator and two timer/counters.

frequency down to any value, even DC, without loss of

data.

The T80C5112 is dedicated for analog interfacing

applications. For this, it has an 10-bit, 8 channels A/D The T80C5112 has 3 software-selectable modes of

converter and a five channels Programmable Counter reduced activity for further reduction in power

Array.

consumption. In the idle mode the CPU is frozen while

the peripherals are still operating. In the quiet mode, the

A/D converter only is operating. In the power-down

mode the RAM is saved and all other functions are

inoperative. Two oscillators source, crystal and RC,

provide a versatile power management.

In addition, the T80C5112 has a Hardware Watchdog

Timer with its own low power oscillator, a versatile

serial

communication (EUART) with an independent baud rate

generator, a SPI serial bus controller and a X2 speed

channel

that

facilitates

multiprocessor

The T80C5112 is proposed in 48/52 pin count packages

with Port 0 and Port 2 (address / data busses).

2. Features

·

80C51 Compatible

·

Crystal or ceramic oscillator with hardware set

up (32 KHz or 33/40 MHz)

·

Five I/O ports

·

Internal RC oscillator (12 MHz)

Programmable prescaler

Two 16-bit timer/counters

256 bytes RAM

Active oscillator during reset defined by hardware

set up

·

8Kbytes ROM/OTP program memory with 64 bytes

encryption array and 3 security levels.

·

Timer 0 subclock mode for Real Time Clock.

High-Speed Architecture

·

Programmable counter array with High speed output,

Compare / Capture, Pulse Width Modulation and

Watchdog timer capabilities

·

33MHz @ 5V (66 MHz equivalent)

20MHz @ 3V (40 MHz equivalent)

X2 Speed Improvement capability (6 clocks/

machine cycle)

Interrupt Structure with:

·

8 Interrupt sources,

·

10-bit, 8 channels A/D converter

4 interrupt priority levels

Hardware Watchdog Timer with integrated low

power oscillator (20mA) and Reset-Out

·

Power Control modes:

·

Idle mode

·

Programmable I/O mode: standard C51, input only,

push-pull, open drain.

Power-down mode

Power-off Flag, Power fail detect, Power on Reset

·

Asynchronous port reset, Power On Reset

Full duplex Enhanced UART with baud rate generator

SPI, master/slave mode

·

Power supply: 2.7 to 5.5V

Temperature ranges: Commercial (0 to 70C) and

Industrial (-40 to 85 C), optionnal extented

Dual system clock

·

Package:LQFP48 (body 7*7*1.4mm), PLCC52

Rev. B - November 10, 2000

1

Preliminary

T80C5112

3. Block Diagram

(3)

(1) (1)

(2) (2)

(2)

XTAL1

Xtal

Osc

ROM /OTP

8 K *8

(2)

RAM

256

x8

RC

Osc

Watch

Dog

PCA

SPI

EUART

BRG

XTAL2

C51

CORE

IB-bus

RC

Osc

CPU

RST

EA

Timer 0

Timer 1

INT

Ctrl

Parallel I/O Ports

Vref

generator

A/D

Converter

ALE

PSEN

Port 3 Port 4

Port 2

Port 1

Port 0

(3)

(2) (3)

(2)

(1): Alternate function of Port 1

(2): Alternate function of Port 3

(3): Alternate function of Port 4

2

Rev. B - November 10, 2000

Preliminary

T80C5112

4. alias SFR Mapping

The Special Function Registers (SFRs) of the T80C5112 belongs to the following categories:

·

C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR, AUXR1

I/O port registers: P0, P1, P2, P3, P4, P1M1, P1M2, P3M1, P3M2, P4M1, P4M2

Timer registers: TCON, TH0, TH1, TMOD, TL0, TL1

Serial I/O port registers: SADDR, SADEN, SBUF, SCON, BRL, BDRCON

Power and clock control registers: CKCON0, CKCON1, OSCCON, CKSEL, PCON, CKRL

Interrupt system registers: IE, IE1, IPL0, IPL1, IPH0, IPH1

WatchDog Timer: WDTRST, WDTPRG

SPI: SPCON, SPSTA, SPDAT

PCA: CCAP0L, CCAP1L, CCAP2L, CCAP3L, CCAP4L, CCAP0H, CCAP1H, CCAP2H, CCAP3H,

CCAP4H, CCAPM0, CCAPM1, CCAPM2, CCAPM3, CCAPM4, CL, CH, CMOD, CCON

·

ADC: ADCCON, ADCCLK, ADCDATH, ADCDATL, ADCF

Table 1. SFR Addresses and Reset Values

0/8

1/9

CH

2/A

3/B

4/C

5/D

6/E

7/F

CCAP0H

CCAP1H

CCAP2H

CCAP3H

CCAP4H

F8h

F0h

E8h

E0h

D8h

D0h

C8h

C0h

B8h

B0h

A8h

A0h

98h

90h

88h

80h

FFh

F7h

EFh

E7h

DFh

D7h

CFh

C7h

BFh

B7h

AFh

A7h

9Fh

97h

0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

B

ADCLK

ADCON

ADDL

ADDH

ADCF

0000 0000

XXXXXX00

0000 0000

CL

CCAP0L

CCAP1L

CCAP2L

CCAP3L

CCAP4L

CONF

0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX 1111 111X

ACC

0000 0000

P1M2

P3M2

P4M2

0000 0000

CCON

00X0 0000

CMOD

CCAPM0

CCAPM1

CCAPM2

CCAPM3

CCAPM4

X000 0000

00XX X000

X000 0000

PSW

0000 0000

P1M1

P3M1

P4M1

0000 0000

P4

SPCON

SPSTA

SPDAT

1111 1111

0001 0100

XXXXXXXX XXXX XXXX

IPL0

0000 0000

SADEN

0000 0000

P3

IE1

IPL1

IPH1

IPH0

X000 0000

1111 1111

0000 0000

IE0

0000 0000

SADDR

0000 0000

CKCON1

XXXX XXX0

P2

AUXR1

WDRST

WDTPRG

0000 0000

1111 1111

XXXXXXX0

0000 0000

SCON

SBUF

BRL

BDRCON

0000 0000

0000 0000 XXXX XXXX 0000 0000

P1

CKRL

1111 1111

TCON

0000 0000

TMOD

TL0

TL1

TH0

TH1

AUXR

CKCON0

X000X000

8Fh

87h

0000 0000

XXXXXXX0

P0

SP

DPL

DPH

CKSEL

OSCCON

PCON

1111 1111

0000 0111

0000 0000

XXXX XXXC XXXX XXCC 00X1 0000

0/8

1/9

2/A

3/B

4/C

5/D 6/E 7/F

Notes: "C", value defined by the configuration byte, see Section ÒConfiguration byteÓ, page 11

Rev. B - November 10, 2000

3

Preliminary

T80C5112

5. Pin Configuration

37

38

48 47 46 45 44 43 42 41 40 39

P3.0/RxD

P3.1/TxD

P0.0

36

35

VREF

1

2

VSS + AVSS

P2.7

34

3

4

P0.1

33

32

31

30

P2.6

P0.2

P2.5

5

6

LQFP48

7*7*1.4 mm

P0.3

P2.4

P0.4

P2.3

7

8

P0.5

29

28

27

26

V2.2

P0.6

VCC + AVCC

P2.1

9

P0.7

10

11

P1.2/ECI

P2.0

P3.7

P1.3/CEX0

25

12

13 14 15 16 17 18 19 20 21 22 23 24

48 47

50 49

6 5 4 3 2

1 52 51

7

NIC

46

45

8

9

VSS

P3.0/RxD

P3.1/TxD

P0.0

AVSS

P2.7

44

10

43

42

41

40

11

12

13

14

P2.6

P0.1

P2.5

P0.2

PLCC52

P2.4

P0.3

P0.4

P2.3

39

38

37

36

15

16

17

P2.2

P0.5

AVCC + VCC

P0.6

P2.1

P0.7

P2.0 18

P1.2/ECI

35

34

19

20

P3.7

VPP

P1.3/CEX0

21 22 23 24 25 26 27 28 29 30 31

32 33

*NIC: No Internal Connection

4

Rev. B - November 10, 2000

Preliminary

T80C5112

NUMBER

TYPE

MNEMONIC

NAME AND FUNCTION

LQFP PLCC

48

52

V

X

I

Ground: 0V reference.

SS

Power Supply: This is the power supply voltage for normal, idle and power-

down operation.

X

CC

AV

Analog Ground: 0V reference.

SS

Analog Power Supply: This is the power supply voltage for normal and idle

operation of the A/D

CC

VREF

VPP

X

VREF : A/D converter positive reference input.

Vpp : Programming Supply Voltage:

This pin also receives the 12V programming pulse which will start the EPROM

programming and the manufacturer test modes.

I

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins

that have 1s written to them are pulled high by the internal pull-ups and can be

used as inputs.

P1.0-P1.7

X

Alternate functions for Port 1 include:

I/O

WR (P1.0): External data memory write strobe

RD (P1.1): External data memory readstrobe

ECI (P1.2): External Clock for the PCA

CEX0 (P1.3): Capture/Compare External I/O for PCA module 0

CEX1 (P1.4): Capture/Compare External I/O for PCA module 1

CEX2 (P1.5): Capture/Compare External I/O for PCA module 2

CEX3 (P1.6): Capture/Compare External I/O for PCA module 3

CEX4 (P1.7): Capture/Compare External I/O for PCA module 4

P3.0-P3.7

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins

that have 1s written to them are pulled high by the internal pull-ups and can be

used as inputs.

X

P3.4 and P3.5 are valid I/O pins only when the T80C5112 is using the internal

RC oscillator, OSCB.

P3.6 is an input only pin

Port 3 also serves the special features of the 80C51 family, as listed below.

I/O

RXD (P3.0): Serial input port

TXD (P3.1): Serial output port

INT0 (P3.2): External interrupt 0

T0 (P3.3): Timer 0 external input

XTAL1 (P3.4): Input to the inverting oscillator amplifier and input to the internal

clock generator circuits, selected by hardware set up

I/O

a

XTAL2 (P3.5): Output from the inverting oscillator amplifier, selected by

hardware set up

Port 4: Port 4 is an 8-bit bidirectional I/O port. Each bit can be set as pure

CMOS input or as push-pull output.

Port 4 is also the input port of the Analog to digital converter and used for

oscillator and reset.

P4.0-P4.7

X

I/O

AIN0 (P4.0): A/D converter input 0

AIN1 (P4.1): A/D converter input 1

T1: Timer 1 external input

AIN2 (P4.2): A/D converter input 2

SS: Slave select input of the SPI controller

I/O

Rev. B - November 10, 2000

5

Preliminary

T80C5112

AIN3 (P4.3): A/D converter input 3

INT1: External interrupt 1

I/O

AIN4 (P4.4): A/D converter input 4

MISO: Master IN, Slave OUT of the SPI controller

AIN5 (P4.5): A/D converter input 5

MOSI: Master OUT, Slave IN of the SPI controller

AIN6 (P4.6): A/D converter input 6

SPSCK: Clock I/O of the SPI controlle

I/O

AIN7 (P4.7): A/D converter input 7

P0.0-P0.7

P2.0-P2.7

X

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s

written to them ßoat and can be used as high impedance inputs. Port 0 is also

the multiplexed low-order address and data bus during access to external program

and data memory. In this application, it uses strong internal pull-up when emitting

1s.

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2

pins that have 1s written to them are pulled high by the internal pull-ups and

can be used as inputs. As inputs, Port 2 pins that are externally pulled low will

source current because of the internal pull-ups. Port 2 emits the high-order address

byte during fetches from external program memory and during accesses to external

data memory that use 16-bit addresses (MOVX @DPTR).In this application, it

uses strong internal pull-ups emitting 1s. During accesses to external data memory

that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.

RST

ALE

X

I

RST: A high on this pin for two machine cycles while the oscillator is running,

resets the device. An internal diffused resistor to V permits a power-on reset

SS

using only an external capacitor to V

If the hardware watchdog reaches its

CC.

time-out, the reset pin becomes an output during the time the internal reset is

activated.

O

Address Latch Enable: Output pulse for latching the low byte of the address

during an access to external memory. In normal operation, ALE is emitted at a

constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used

for external timing or clocking. Note that one ALE pulse is skipped during each

access to external data memory. ALE can be disabled by setting SFRÕs AUXR.0

bit. With this bit set, ALE will be inactive during internal fetches.

PSEN

EA

X

O

I

Program Store ENable: The read strobe to external program memory. When

executing code from the external program memory, PSEN is activated twice each

machine cycle, except that two PSEN activations are skipped during each access

to external data memory. PSEN is not activated during fetches from internal

program memory.

External Access Enable: EA must be externally held low to enable the device

to fetch code from external program memory locations 0000H and 1FFFH . If

EA is held high, the device executes from internal program memory unless the

program counter contains an address greater than 1FFFH. EA must be held low

for ROMless devices. If security level 1 is programmed, EA will be internally

latched on Reset.

XTAL1 : Input to the inverting oscillator amplifier and input to the internal

clock generator circuits, selected by hardware set up

XTAL1

XTAL2

X

I

b

XTAL2 : Output from the inverting oscillator amplifier, selected by hardware

set up

O

a. Hardware set up :

+Configuration bits programmed with the code for ROM version

+Configuration bits for EPROM version

b. Hardware set up :

+Configuration bits programmed with the code for ROM version

+Configuration bits for EPROM version

6

Rev. B - November 10, 2000

Preliminary

T80C5112

6. Clock system

6.1. Overview

The T80C5112 oscillator system provides a reliable clocking system with full mastering of speed versus CPU

power trade off. Several clocks sources are possible:

·

External clock input

High speed crystal or ceramic oscillator

Low speed crystal oscillator

Integrated high speed RC oscillator

The low speed RC oscillator of the watchdog is a backup clocking source when no clock are selected in active

or idle modes.

The selected clock source can be divided by 2-512 before clocking the CPU and the peripherals. When X2 function

is set, the CPU need 6 clock periods per cycle.

Active oscillator at reset is defined by bits in a configuration byte programmed on an OTP programmer or by

metal mask.

Clocking is controlled by several SFR registers : OSCON, CKCON0, CKCON1, CKRL.

6.2. Blocks description

The T80C5112 includes the following oscillators:

·

Crystal oscillator, with two possible gains optimized for 32 kHz or 33 MHz.

Integrated high speed RC oscillator, with typical frequency of 12 MHz

Integrated low speed, low power RC oscillator, with typical frequency of 200 kHz; this oscillator is used to

clock the hardware watchdog and as back up oscillator when the CPU receives no clock signal in active or

idle modes.

6.2.1. Crystal oscillator : OSCA

The crystal oscillator uses two external pins, XTAL1 for input and XTAL2 for output.

XT_SP in configuration byte allows to select between two possible gains optimized for 32 kHz or 33 MHz. Both

crystal and ceramic resonnators can be used.

OSCAEN in OSCCON register is an enable signal for the crystal oscillator or the external oscillator input.

When the crystal oscillator is not selected, XTAL1 can be used as a standard C51 I/O port, and X2 can be used

as a standard C51 I/O port.

6.2.2. Integrated high speed RC oscillator : OSCB

The high speed RC oscillator do not need any external component; its typical frequency is 12 MHz. Note that the

on chip oscillator has a +-25% frequency tolerance and for that reason may not be suitable for use in some applications.

OSCBEN in OSCCON register is an enable signal for the high speed RC oscillator.

Rev. B - November 10, 2000

7

Preliminary

T80C5112

6.2.3. Integrated low speed, low power RC oscillator : OSCC

The low speed, low power RC oscillator is used to clock the hardware watchdog and do not need any external

component; its typical frequency is 200 kHz.

This oscillator is also used as back up oscillator when the CPU receive no clock signal in active or idle modes.

RCLF_OFF is the configuration bit used to switch on or off the low speed RC oscillator.

Note that the on chip oscillator has a +-25% frequency tolerance and for that reason may not be suitable for use

in some applications.

6.2.4. Clock selector

CKS bit in CKS register is used to select from crystal to RC oscillator.

OSCBEN bit in OSCCON register is used to enable the RC oscillator.

OSCAEN bit in OSCCON register is used to enable the crystal oscillator or the external oscillator input.

If both oscillators are disabled, the low speed oscillator, OSCC is used as a backup source for the CPU and the

peripherals.

This feature provides a stand alone low frequency mode which can be activated when needed.

6.2.5. Clock prescaler

Before supplying the CPU and the peripherals, the main clock is divided by a factor to 2 to 512, as defined by

the CKRL register. The CPU needs from 12 to 256*12 clock periods per instruction. This allows:

·

To accept any cyclic ratio to be accepted on XTAL1 input.

To reduce the CPU power consumption.

The X2 bit allows to bypass the clock prescaler ; in this case, the CPU need only 6 clock periods per machine

cycle. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to 60%

8

Rev. B - November 10, 2000

Preliminary

T80C5112

6.3. Functional Block diagram

Timer 0 clock

:128

Sub Clock

Reload

ResetB

XT_SP

1

0

WD clock

Ckrl

Xtal1

Xtal2

A/D clock

CkAdc

Xtal_Osc

OSCA

1

0

Mux OscOut

+

8-bit

Prescaler-Divider

0

1

RCLF_OFF

Filter

OSCAEN

OSCBEN

1

0

Peripherals clock

PwdOsc

CkOut

CkIdle

CKS

RC_Osc

OSCB

Cpu clock

Ck

X2

PwdRC

RCLF_Osc

OSCC

OSCBEN

OSCAEN

Pwd

Quiet

Idle

RCLF_OFF

Figure 1. Functional block diagram

6.4. Operating modes

6.4.1. Reset :

·

An hardware RESET select Xtal_Osc or RC_Osc depending on the RST_OSC configuration bit

6.4.2. Functional modes :

6.4.2.1. NORMAL MODES :

·

CPU and Peripherals clock depend on the software selection using CKCON0, CKCON1, CKSEL and CKRL

registers

·

CKS bit selects either Xtal_Osc or RC_Osc

CKRL register determines the frequency of the selected clock, unless X2 bit is set.

In this case the prescaler/divider is not used, so CPU core needs only 6-clock period per machine cycle.

According to the value of the peripheral X2 individual bit, each peripherals need 6 or 12 clock period per

instructions.

·

It is always possible to switch dynamicaly by software from Xtal_Osc to RC_Osc, and vice versa by changing

CKS bit, a synchronization cell allowing to avoid any spike during transition.

Rev. B - November 10, 2000

9

Preliminary

T80C5112

6.4.2.2. IDLE MODES :

·

IDLE modes are achieved by using any instruction that writes into PCON.0 sfr

IDLE modes A and B depend on previous software sequence, prior to writing into PCON.0 register :

·

IDLE MODE A : Xtal_Osc is running (OSCAEN = 1) and selected (CKS = 1)

IDLE MODE B : RC_Osc is running (OSCBEN = 1) and selected (CKS = 0)

The unused oscillator Xtal_Osc or RC_Osc can be stopped by software by clearing OSCAEN or OSCBEN

respectively.

·

Exit from IDLE mode is acheived by Reset, or by activation of an enabled interrupt.

In both case, PCON.0 is cleared by hardware.

Exit from IDLE modes will leave the ocillators control bits OSCAEN, OSCBEN and CKS unchanged.

6.4.2.3. POWER DOWN MODES :

·

POWER DOWN modes are achieved by using any instruction that writes into PCON.1 sfr

Exit from POWER DOWN mode is acheived either by an harware Reset, by an external interruption.

·

By RST signal : The CPU will restart in the mode defined by RST_OSC.

By INT0 or INT1 interruptions, if enabled. The ocillators control bits OSCAEN, OSCBEN and CKS will

not be changed, so the selected oscillator before entering into Power-down will be activated.

RCLF

PD

IDLE

CKS OSCBEN OSCAEN

Selected Mode

Comment

_OFF

0

X

0

X

0

1

0

X

0

1

0

X

1

NORMAL MODE A

INVALID

OSCA: XTAL clock

no active clock

0

RESCUE MODE

NORMAL MODE B,

INVALID

OSCC: Low speed RC clock active

OSCB: high speed RC clock

0

1

X

0

X

1

X

0

X

0

RESCUE MODE

OSCC: Low speed RC clock active

The CPU is off, OSCA supplies the

peripherics

0

1

0

X

1

X

1

X

0

IDLE MODE A

IDLE MODE B

The CPU is off, OSCB supplies the

peripherics

POWER DOWN MODE The CPU and peripherics are off, but

X

with WD

OSCC is still running for WD

The CPU is off, OSCA and OSCB are

1

X

1

TOTAL POWER DOWN stopped

OSCC is stopped

6.4.2.4. Prescaler Divider :

·

An hardware RESET selects the prescaler divider :

·

CKRL = FFh: internal clock = OscOut / 2 (Standard C51 feature)

X2 = 0,

SEL_OSC signal selects Xtal_Osc or RC_Osc, depending on the value of the RST_OSC configuration bit.

·

After Reset, any value between FFh down to 00h can be written by software into CKRL sfr in order to divide

frequency of the selected oscillator:

·

CKRL = 00h : minimum frequency = OscOut / 512

CKRL = FFh : maximum frequency = OscOut / 2

10

Rev. B - November 10, 2000

Preliminary

T80C5112

·

A software instruction which set X2 bit desactivates the precaler/divider, so the internal clock is either Xtal_Osc

or RC_Osc depending on SEL_OSC bit.

6.5. Timer 0 : Clock Inputs

CkIdle

:6

0

1

Timer 0

T0 pin

0

1

Control

Sub Clock

C/T

TMOD

SCLKT0

OSCCON

Gate

INT0

TR0

Figure 2. Timer 0 : Clock Inputs

The SCLKT0 bit in OSCCON register allows to select Timer 0 Subsidiary clock. This allow to perform a Real

Time Clock function.

SCLKT0 = 0 : Timer 0 uses the standard T0 pin as clock input ( Standard mode )

SCLKT0 = 1 : Timer 0 uses the special Sub Clock as clock input.

When the subclock input is selected for Timer 0 and the crystal oscillator is selected for CPU and peripherals, the

CKRL prescaler must be set to FF (division factor 2) in order to assure a proper count on Timer 0.

With a 32 kHz crystal, the timer interrupt can be set from 1/256 to 256 seconds to perform a Real Time Clock

(RTC) function. The power consumption will be very low as the CPU is in idle mode at 32 KHz most of the time.

When more CPU power is needed, the internal RC oscillator is activated and used by the CPU and the others

peripherals.

6.6. Registers

6.6.1. Configuration byte

The configuration byte is a special register. Its content is defined by the diffusion mask in the ROM version or

is rerad or written by the OTP programmer in the OTP version. This register can also be accessed as a read only

register.

CONF - Conﬁguration byte (EFh)

7

6

5

4

3

2

1

0

LB1

LB2

LB3

RST_OSC

XT_SP

RST_EXT

OSCC_OFF

Bit

Number

7:5

Bit

Mnemonic

Description

-

Program memory lock bits

See chapter program memory for the deÞnition of these bits..

Rev. B - November 10, 2000

11

Preliminary

T80C5112

Bit

Number

4

Bit

Description

Mnemonic

RST_OSC Selected oscillator at reset

This bit is used to deÞne the value of some bits controlling the oscillator activity at reset:

1: The crystal oscillator is sectected and active

0: The RC oscillator is selected; it is also active if the WDRC is inactive.

3

2

1

XT_SP

Crystal oscillator speed

This bit is used to deÞne the performance of the crystal oscillator.

1: High speed, up to 33 MHz

0: Low speed, low power, optimised for 32 kHz.

EXT_RST External Reset

This bit deÞnes the behavior of the P3.6/RST pin

1: P3.6/RST is the reset pin

0: P3.6/RST is an input pin

OSCC_OFF Control for watchdog RC oscillator

This bit is used to switch the watchdog RC oscillator and the watchdog source

1: WDRC oscillator is off; the watchdog is clocked by the main oscillator.

0: WDRC oscillator is on and clock the watchdog

0

-

Reserved

The value read from this bit is indeterminate. Do not reset this bit.

Initial value after erasing : 1111 111X

6.6.2. Clock control register

The clock control register is used to define the clock system behavior

OSCCON - Clock Control Register (86h)

7

6

-

5

-

4

-

3

-

2

1

0

-

SCLKT0

OSCBEN

OSCAEN

Bit

Number

7

Bit

Mnemonic

Description

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6

5

4

3

2

-

Sub Clock Timer0

SCLKT0

OSCBEN

Cleared by software to select T0 pin

Set by software to select T0 Sub Clock

1

0

Enable RC oscillator

This bit is used to enable the high speed RC oscillator

0: The oscillator is disabled

1: The oscillator is enabled.

OSCAEN

Enable crystal oscillator

This bit is used to enable the crystal oscillator

0: The oscillator is disabled

1: The oscillator is enabled.

Reset Value = 0XXX X0 "RST_OSC" "RST_OSC" b

Not bit addressable

12

Rev. B - November 10, 2000

Preliminary

T80C5112

6.6.3. Clock selection register

The clock selectionl register is used to define the clock system behavior

CKSEL - Clock Selection Register (85h)

7

6

-

5

-

4

-

3

-

2

-

1

-

0

CKS

Bit

Number

7

Bit

Mnemonic

Description

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6

5

4

3

2

1

0

-

CKS

Active oscillator selection

This bit is used to select the active oscillator

1: The crystal oscillator is selected

0: The high speed RC oscillator is selected.

Reset Value = XXXX XXX "RST_OSC" b

Not bit addressable

6.6.4. Clock prescaler register

This register is used to reload the clock prescaler of the CPU and peripheral clock.

CKRL - Clock prescaler Register (97h)

7

6

5

4

3

2

1

0

M

Bit

Number

7:0

Bit

Mnemonic

Description

CKRL

0000 0000b: Division factor equal 512

1111 1111b: Division factor equal 2

M: Division factor equal 2*(256-M)

Reset Value = 1111 1111b

Not bit addressable

6.6.5. Clock control register

This register is used to control the X2 mode of the CPU and peripheral clock.

Table 2. CKCON0 Register

Rev. B - November 10, 2000

13

Preliminary

T80C5112

CKCON0 - Clock Control Register (8Fh)

7

-

6

5

4

3

-

2

1

0

WdX2

PcaX2

SiX2

T1X2

T0X2

X2

Bit

Description

Number

Mnemonic

7

6

-

Reserved

WdX2

Watchdog clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

5

4

PcaX2

SiX2

Programmable Counter Array clock (This control bit is validated when the CPU clock X2 is set; when X2 is

low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the CPU clock X2 is set; when X2 is

low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Reserved

3

2

-

T1X2

Timer1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle

1

0

T0X2

X2

Timer0 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle

CPU clock

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals.

Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2" bits.

Reset Value = X000 0000b

Not bit addressable

Table 3. CKCON1 Register

CKCON1 - Clock Control Register

7

6

5

-

4

-

3

-

2

-

1

0

-

BRGX2

SPIX2

Bit

Description

Number

Mnemonic

7

6

5

4

3

2

1

0

-

Reserved

-

SPIX2

SPI clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle

Reset Value = XXXX XX00b

Not bit addressable

14

Rev. B - November 10, 2000

Preliminary

T80C5112

7. Reset and Power Management

7.1. Introduction

The power monitoring and management can be used to supervise the Power Supply (VDD) and to start up properly

when T80C5112 is powered up.

It consists of the features listed below and explained hereafter:

·

Power on Reset

Power-Fail reset

Power-Off flag

Idle mode

Power-Down mode

Reduced EMI mode

All these features are controlled by several registers, the Power Control register (PCON) and the Auxiliary register

(AUXR) detailed at the end of this chapter.

AUX register not available on all versions.

7.2. Functional description

Figure 3 shows the block diagram of the possible sources of microcontroller reset.

Rev. B - November 10, 2000

15

Preliminary

T80C5112

RST pin*

Hardware WD

Reset

RST pin*

RST_EXT

CONF

PCA WD

set

POF

PCON

POR

PFD

+24 Ck

5V

EN

Fail

CPU Clock

RSTD

PCON

Figure 3. Reset sources

Notes: RST pin available only on 48 and 52 pins versions.

Notes: RST pin available only on LPC versions.

7.3. Power-On Reset

The T80C5112 has a power on reset (POR) module which reset the chip during the initial power raise. The internal

power on reset pulse duration is 24 clock periods of the CPU clock. The chip can also be reseted by the P3.6/

RST/Vpp pin provided the EXT_RST bit of the configuration byte is high.

This module set the POF bit vhen Vcc is below the memory data retention voltage.

The behavior or POR and PFD is shown on Figure 4.

7.4. Power-Fail Detector

The Power-Fail Detector (PFD) is controlled by RSTD bit in PCON register. The PFD is disabled upon reset.

(1)

When enabled, the power supply is continuously monitored and an internal reset is generated if VDD goes

below V

for at least 60 ns.

RST

2

If the power supply rises again over V

( ), the internal reset completes after 24 CPU clock periods.

RST+

If RSTD is reset, the power supply monitoring is disabled.

16

Rev. B - November 10, 2000

Preliminary

T80C5112

In Power-Down mode, the PFD is automatically disabled; this avoids extra consumption and allows VDD reduction

to V

Note:

RET.

1. The internal reset is not propagated on the RST pin.

2 See AC/DC section for the speciﬁcations of Vrst.

Caution:

When VDD is reduced to V

in Power-Down mode the VDD voltage is not accuratly monitored. In this case, RAM content may be damage if VDD

RET

goes below V

data.

and circuit behavior is unpredictable unless an external reset is applied. The POF bit can be used to verify if memory contains valid

RET

V_RST+

V_RST

<60ns

V_RET

RSTVPP

>60ns

POR

PFD

RST

24 Ck

Figure 4. Power Fail Reset timing diagram

7.5. Power-Off Flag

When the power is turned off or fails, the data retention is not guaranteed. A Power-Off Flag (POF, see 7.6.1. )

allows to detect this condition. POF is set by hardware during a reset which follows a power-up or a power-fail.

This is a cold reset. A warm reset is an external or a watchdog reset without power failure, hence which preserves

the internal memory content and POF. To use POF, test and clear this bit just after reset. Then it will be set only

after a cold reset.

Notes: When power supply monitoring is disabled (RSTD= 1 or in Power-Down mode), POF information is not delivered with the same

accuracy. It is recommended to clear and not to take in account the POF value after exit from a power down mode with VDD reduction.

Notes: The POF flag is set only if Vcc is lower below the memory data retention voltage. Hence, the PFD may detect a power fail while the

POF bit is still valid.

Rev. B - November 10, 2000

17

Preliminary

T80C5112

7.6. Registers

7.6.1. PCON: Power configuration register

Table 4. PCON Register

PCON (S:87h)

Power conÞguration Register

7

6

5

4

3

2

1

0

SMOD1

SMOD0

RSTD

POF

GF1

GF0

PD

IDL

Bit

Description

Number

Mnemonic

Double Baud Rate bit

7

6

SMOD1

SMOD0

Set to double the Baud Rate when Timer 1 is used and mode 1, 2 or 3 is selected in SCON register.

SCON Select bit

When cleared, read/write accesses to SCON.7 are to SM0 bit and read/write accesses to SCON.6 are to SM1 bit.

When set, read/write accesses to SCON.7 are to FE bit and read/write accesses to SCON.6 are to OVR bit.

SCON is Serial Port Control register.

Reset Detector Disable bit

5

4

RSTD

POF

Clear to disable the Power-Fail detector.

Set to enable the Power-Fail detector.

Power-Off flag

Set by hardware when VDD rises above V

to indicate that the Power Supply has been set off.

RET+

Must be cleared by software.

General Purpose flag 1

One use is to indicate wether an interrupt occurred during normal operation or during Idle mode.

3

2

GF1

GF0

General Purpose flag 0

One use is to indicate wether an interrupt occurred during normal operation or during Idle mode.

Power-Down Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Power-Down mode.

If IDL and PD are both set, PD takes precedence.

1

0

PD

Idle Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Idle mode.

IDL

If IDL and PD are both set, PD takes precedence.

Reset Value= 0000 0000b

7.7. Port pins

The value of port pins in the different operating modes is shown on the figure below.

Table 5. Pin Conditions in Special Operating Modes

Mode

Program

Memory

Port 1 pins

Port 3 pins

Port 4 pins

Reset

DonÕt care

Internal

Weak High

Data

Weak High

Data

Weak High

Data

Idle

Power-Down

Internal

Data

18

Rev. B - November 10, 2000

Preliminary

T80C5112

7.8. Reduced EMI mode

The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data

memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE

signal can be disabled by setting AO bit.

The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but

remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is

weakly pulled high.

Table 6. AUXR Register

AUXR - Auxiliary Register (8Eh)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

AO

Bit

Mnemonic

Bit Number

Description

7

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6

5

4

3

2

1

0

-

AO

ALE Output bit

Clear to restore ALE operation during internal fetches.

Set to disable ALE operation during internal fetches.

Reset Value = XXXX XXX0b

Not bit addressable

Rev. B - November 10, 2000

19

Preliminary

T80C5112

8. Hardware Watchdog Timer

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The

WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default

disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST,

SFR location 0A6H. When WDT is enabled, it will increment every machine cycle ( 6 internal clock periods) and

there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). The T0

bit of the WDTPRG register is used to select the overflow after 10 or 14 bits. When WDT overflows, it will

generate an internal reset. It will also drive an output RESET HIGH pulse at the emulator RST-pin.

If the crystal oscillator is selected with whe low speed option (32kHz), the low speed RC oscillator must not be

used. In this case the WDT will also use the low speed crystal oscillator.

8.1. Using the WDT

To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When

WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow.

The 14-bit counter overflows when it reaches 16383 (3FFFH) or 1024 (1FFFH) and this will reset the device.

When WDT is enabled, it will increment every machine cycle while the oscillator is running. This means the user

must reset the WDT at least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H

to WDTRST. WDTRST is a write only register. The WDT counter cannot be read or written. When WDT overflows,

it will generate an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x T

, where T

=

OSC

1/F

. To make the best use of the WDT, it should be serviced in those sections of code that will periodically

OSC

be executed within the time required to prevent a WDT reset.

7

To have a more powerful WDT, a 2 counter has been added to extend the Time-out capability, ranking from

16ms to 2s @ F

8. (SFR0A7h).

= 12MHz and T0=0. To manage this feature, refer to WDTPRG register description, Table

OSC

Table 7. WDTRST Register

WDTRST Address (0A6h)

7

6

5

4

3

2

1

Reset value

X

Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.

20

Rev. B - November 10, 2000

Preliminary

T80C5112

Table 8. WDTPRG Register

WDTPRG Address (0A7h)

7

6

5

4

3

2

1

0

T4

T3

T2

T1

T0

S2

S1

S0

Bit

Mnemonic

Bit Number

Description

7

6

5

4

3

T4

T3

T2

T1

T0

Reserved

Do not try to set this bit.

WDT overßow select bit

0 : Overßow after 14 bits

1 : Overßow after 10 bits

2

1

0

S2

S1

S0

WDT Time-out select bit 2

WDT Time-out select bit 1

WDT Time-out select bit 0

S2S1S0

000

001

010

011

100

101

110

111

Selected Time-out with T0=0

14

(2 - 1) machine cycles, 16.3 ms @ 12 MHz

15

(2 - 1) machine cycles, 32.7 ms @ 12 MHz

16

(2 - 1) machine cycles, 65.5 ms @ 12 MHz

17

(2 - 1) machine cycles, 131 ms @ 12 MHz

18

(2 - 1) machine cycles, 262 ms @ 12 MHz

19

(2 - 1) machine cycles, 542 ms @ 12 MHz

20

(2 - 1) machine cycles, 1.05 s @ 12 MHz

21

(2 - 1) machine cycles, 2.09 s @ 12 MHz

S2S1 S0

000

001

010

011

100

101

110

111

Selected Time-out with T0=1

10

(2 - 1) machine cycles, 60 ms @ 200 kHz

11

(2 - 1) machine cycles, 120ms @ 200 kHz

12

(2 - 1) machine cycles, 240ms @ 200 kHz

13

(2 - 1) machine cycles, 480ms @ 200 kHz

14

(2 - 1) machine cycles, 860ms @ 200 kHz

15

(2 - 1) machine cycles, 1.7s @ 200 kHz

16

(2 - 1) machine cycles, 3.4s @ 200 kHz

17

(2 - 1) machine cycles, 6.8s @ 200 kHz

Reset value XXX0 0000

Write only register

8.1.1. WDT during Power Down and Idle

8.1.1.1. Power down and OSCC inactive

In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the

user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset

or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power

Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the T80C5112

is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for

the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from

resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.

It is suggested that the WDT be reseted during the interrupt service routine.

To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the

WDT just before entering powerdown.

Rev. B - November 10, 2000

21

Preliminary

T80C5112

8.1.1.2. Power down and OSCC active

In Power Down mode the low speed RC oscillator never stops. If the WDT is active before entering power down,

the T80C5112 will be reseted once and will start executing the program code. The software may then decide to

leave the WDT inactive.

If the high speed RC oscillator is selected at reset, this mode may be used to periodically awake the T80C5112

and check for an external event while keeping the average consumption at a very low level.

There are 2 methods of exiting Power Down mode: by a hardware or watchdog reset or via a level activated

external interrupt which is enabled prior to entering Power Down mode. When Power Down is exited with hardware

or watch dog reset, servicing the WDT should occur as it normally should whenever the T80C5112 is reset. Exiting

Power Down with an interrupt is significantly different. As the WDT and interrupt are asynchronous events, the

WDT may overflow within a few states of exiting of powerdown. To limit the probability of such an event, it is

suggested that the WDT be reseted during the interrupt service routine.

8.1.1.3. Idle mode

In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the T80C5112 while in Idle

mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter Idle mode.

22

Rev. B - November 10, 2000

Preliminary

T80C5112

9. Ports

The T80C5112 has 5 I/O ports, from port 0 to port 4.. The number of possible I/O on each package option is

shown on Table 9.

At least 39 pins of the T80C5112 may be used as I/Os when a two-pin external oscillator.

Table 9. Number of available I/O versus pin number

48

52

Supply pins

I/O

2

39

1

3

39

1

Inputs

Maximun I/O count

40

All port1, port3 and port4 I/O port pins on the T80C5112 may be software configured to one of four types on a

bit-by-bit basis, as shown in Table 10. These are: quasi-bidirectional (standard 80C51 port outputs), push-pull,

open drain, and input only. Two configuration registers for each port choose the output type for each port pin.

Table 10. Port Output Configuration settings using PxM1 and PxM2 registers

PxM1.y bit

PxM2.y bit

Port Output Mode

0

1

0

1

0

1

Quasi bidirectional

Push-Pull

Input Only (High Impedance)

Open Drain

9.1. Ports types

9.1.1. Quasi-Bidirectional Output Configuration

The default port output configuration for standard T80C5112 I/O ports is the quasi-bidirectional output that is

common on the 80C51 and most of its derivatives. This output type can be used as both an input and output

without the need to reconfigure the port. This is possible because when the port outputs a logic high, it is weakly

driven, allowing an external device to pull the pin low. When the pin is pulled low, it is driven strongly and able

to sink a fairly large current. These features are somewhat similar to an open drain output except that there are

three pull-up transistors in the quasi-bidirectional output that serve different purposes. One of these pull-ups, called

the "very weak" pull-up, is turned on whenever the port latch for the pin contains a logic 1. The very weak pull-

up sources a very small current that will pull the pin high if it is left floating. A second pull-up, called the "weak"

pull-up, is turned on when the port latch for the pin contains a logic 1 and the pin itself is also at a logic 1 level.

This pull-up provides the primary source current for a quasi-bidirectional pin that is outputting a 1. If a pin that

has a logic 1 on it is pulled low by an external device, the weak pull-up turns off, and only the very weak pull-

up remains on. In order to pull the pin low under these conditions, the external device has to sink enough current

to overpower the weak pull-up and take the voltage on the port pin below its input threshold.

The third pull-up is referred to as the "strong" pull-up. This pull-up is used to speed up low-to-high transitions on

a quasi-bidirectional port pin when the port latch changes from a logic 0 to a logic 1. When this occurs, the strong

pull-up turns on for a brief time, two CPU clocks, in order to pull the port pin high quickly. Then it turns off again.

The quasi-bidirectional port configuration is shown in Figure 5.

Rev. B - November 10, 2000

23

Preliminary

T80C5112

2 CPU

CLOCK DELAY

P

Very

Weak

Strong

Weak

Port latch

Data

N

Input

Data

Figure 5. Quasi-Bidirectional Output

9.1.2. Open Drain Output Configuration

The open drain output configuration turns off all pull-ups and only drives the pull-down transistor of the port

driver when the port latch contains a logic 0. To be used as a logic output, a port configured in this manner must

have an external pull-up, typically a resistor tied to Vdd. The pull-down for this mode is the same as for the quasi-

bidirectional mode. The open drain port configuration is shown in Figure 6.

Port latch

Data

N

Input

Data

Figure 6. Open Drain Output

9.1.3. Push-Pull Output Configuration

The push-pull output configuration has the same pull-down structure as both the open drain and the quasi-bidirectional

output modes, but provides a continuous strong pull-up when the port latch contains a logic 1. The push-pull mode

may be used when more source current is needed from a port output. The push-pull port configuration is shown

in Figure 7.

24

Rev. B - November 10, 2000

Preliminary

T80C5112

P

Strong

Port latch

Data

N

Input

Data

Figure 7. Push-Pull Output

9.1.4. Input only Configuration

The input only configuration is a pure input with neither pull-up nor pull-down.

The input only configuration is shown in Figure 7.

Input

Data

Figure 8. Input only

9.2. Ports description

9.2.1. Ports P1, P3 and P4

Every output on the T80C5112 may potentially be used as a 20 mA sink LED drive output. However, there is a

maximum total output current for all ports which must not be exceeded. All ports pins of the T80C5112 have slew

rate controlled outputs. This is to limit noise generated by quickly switching output signals. The slew rate is factory

set to approximately 10 ns rise and fall times.

The inputs of each I/O port of the T80C5112 are TTL level Schmitt triggers with hysteresis.

9.2.2. Ports P0 and P2

High pin count version of the T80C5112 have standard address and data ports P0 and P2. These ports are standard C51

ports (Quasi-bidirectional I/O). The control lines are provided on the pins : ALE, PSEN, EA, Reset; RD and WR signals

are on the bits P1.1 and P1.0 .

Rev. B - November 10, 2000

25

Preliminary

T80C5112

9.3. Registers

Table 11. P1M1 Register

P1M1 Address (D4h)

7

6

5

4

3

2

1

0

P1M1.7

P1M1.6

P1M1.5

P1M1.4

P1M1.3

P1M1.2

P1M1.1

P1M1.0

Bit

Number

7 : 0

Bit

Mnemonic

P1M1.x

Description

Port Output conﬁguration bit

See Table 10. for conÞguration deÞnition

Reset value 0000 00XX

Table 12. P1M2 Register

P1M2 Address (E2h)

7

6

5

4

3

2

1

0

P1M2.7

P1M2.6

P1M2.5

P1M2.4

P1M2.3

P1M2.2

P1M2.1

P1M2.0

Bit

Number

7 : 0

Bit

Mnemonic

P1M2.x

Description

Port Output conﬁguration bit

See Table 10. for conÞguration deÞnition

Reset value 0000 00XX

Table 13. P3M1 Register

P3M1 Address (D5h)

7

6

5

4

3

2

1

0

P3M1.7

P3M1.6

P3M1.5

P3M1.4

P3M1.3

P3M1.2

P3M1.1

P3M1.0

Bit

Number

7 : 0

Bit

Mnemonic

P3M1.x

Description

Port Output conﬁguration bit

See Table 10. for conÞguration deÞnition

Reset value 0000 0000

Table 14. P3M2 Register

P3M2 Address (E4h)

7

6

5

4

3

2

1

0

P3M2.7

P3M2.6

P3M2.5

P3M2.4

P3M2.3

P3M2.2

P3M2.1

P3M2.0

Bit

Number

7 : 0

Bit

Mnemonic

P3M2.x

Description

Port Output conﬁguration bit

See Table 10. for conÞguration deÞnition

Reset value 0000 0000

Table 15. P4M1 Register

P4M1 Address (D6h)

7

6

5

4

3

2

1

0

P4M1.7

P4M1.6

P4M1.5

P4M1.4

P4M1.3

P4M1.2

P4M1.1

P4M1.0

26

Rev. B - November 10, 2000

Preliminary

T80C5112

Bit

Number

7 : 0

Bit

Mnemonic

P4M1.x

Description

Port Output conﬁguration bit

See Table 10. for conÞguration deÞnition

Reset value 0000 0000

Table 16. P4M2 Register

P4M2 Address (E5h)

7

6

5

4

3

2

1

0

P4M2.7

P4M2.6

P4M2.5

P4M2.4

P4M2.3

P4M2.2

P4M2.1

P4M2.0

Bit

Number

7: 0

Bit

Mnemonic

P4M2.x

Description

Port Output conﬁguration bit

See Table 10. for conÞguration deÞnition

Reset value 0000 0000

Rev. B - November 10, 2000

27

Preliminary

T80C5112

10. Dual Data Pointer Register Ddptr

The additional data pointer can be used to speed up code execution and reduce code size in a number of ways.

The dual DPTR structure is a way by which the chip will specify the address of an external data memory location.

There are two 16-bit DPTR registers that address the external memory, and a single bit called

DPS = AUXR1/bit0 (See Table 17.) that allows the program code to switch between them (Refer to Figure 9).

External Data Memory

7

0

DPS

DPTR1

DPTR0

AUXR1(A2H)

DPH(83H) DPL(82H)

Figure 9. Use of Dual Pointer

28

Rev. B - November 10, 2000

Preliminary

T80C5112

Table 17. AUXR1: Auxiliary Register 1

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

DPS

Bit

Mnemonic

Bit Number

Description

7

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

6

5

4

3

2

1

0

-

DPS

Data Pointer Selection

Clear to select DPTR0.

Set to select DPTR1.

User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new feature. In that case, the reset

value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.

Application

Software can take advantage of the additional data pointers to both increase speed and reduce code size, for

example, block operations (copy, compare, search ...) are well served by using one data pointer as a ÕsourceÕ

pointer and the other one as a "destination" pointer.

Rev. B - November 10, 2000

29

Preliminary

T80C5112

ASSEMBLY LANGUAGE

; Block move using dual data pointers

; Destroys DPTR0, DPTR1, A and PSW

; note: DPS exits opposite of entry state

; unless an extra INC AUXR1 is added

;

00A2 AUXR1 EQU 0A2H

;

0000 909000MOV DPTR,#SOURCE ; address of SOURCE

0003 05A2 INC AUXR1 ; switch data pointers

0005 90A000 MOV DPTR,#DEST ; address of DEST

0008 LOOP:

0008 05A2 INC AUXR1 ; switch data pointers

000A E0 MOVX A,@DPTR ; get a byte from SOURCE

000B A3 INC DPTR ; increment SOURCE address

000C 05A2 INC AUXR1 ; switch data pointers

000E F0 MOVX @DPTR,A ; write the byte to DEST

000F A3 INC DPTR ; increment DEST address

0010 70F6JNZ LOOP ; check for 0 terminator

0012 05A2 INC AUXR1 ; (optional) restore DPS

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note

that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple

routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not

its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe

that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.

30

Rev. B - November 10, 2000

Preliminary

T80C5112

11. Serial I/O Ports enhancements

The serial I/O ports in the T80C5112 are compatible with the serial I/O port in the 80C52.

They provide both synchronous and asynchronous communication modes. They operate as Universal Asynchronous

Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and

reception can occur simultaneously and at different baud rates

Serial I/O ports include the following enhancements:

·

Framing error detection

Automatic address recognition

11.1. Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing

bit error detection feature, set SMOD0 bit in PCON register (See Figure 10).

SM2 REN

TI

RI

SM0/FE SM1

TB8 RB8

SCON for UART (98h) (SCON_1 for UART_1 (C0h))

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1 for UART)

SM0 to UART mode control (SMOD0 = 0 for UART)

GF1

POF

GF0

SMOD1 SMOD0

PCON for UART (87h) (SMOD bits for UART_1

are located in BDRCON_1)

-

PD

IDL

To UART framing error control

Figure 10. Framing Error Block Diagram

When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop

bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit

is not found, the Framing Error bit (FE) in SCON register (See Table 18) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can

clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled,

RI rises on stop bit instead of the last data bit (See Figure 11. and Figure 12.).

D0 D1 D2 D3 D4 D5 D6 D7

RXD

Start

bit

Data byte

Stop

bit

RI

SMOD0=X

FE

SMOD0=1

Figure 11. UART Timings in Mode 1

Rev. B - November 10, 2000

31

Preliminary

T80C5112

RXD

RI

D0 D1 D2 D3 D4 D5 D6 D7 D8

Start

bit

Data byte

Ninth Stop

bit bit

SMOD0=0

RI

SMOD0=1

FE

SMOD0=1

Figure 12. UART Timings in Modes 2 and 3

11.2. Automatic Address Recognition

The automatic address recognition feature is enabled for each UART when the multiprocessor communication

feature is enabled (SM2 bit in SCON register is set).

Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by

allowing the serial port to examine the address of each incoming command frame. Only when the serial port

recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that

the CPU is not interrupted by command frames addressed to other devices.

If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit

takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the

deviceÕs address and is terminated by a valid stop bit.

To support automatic address recognition, a device is identified by a given address and a broadcast address.

NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON

register in mode 0 has no effect).

11.2.1. Given Address

Each UART has an individual address that is specified in SADDR register; the SADEN register is a mask byte

that contains donÕt-care bits (defined by zeros) to form the deviceÕs given address. The donÕt-care bits provide the

flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask byte must be 1111 1111b.

For example:

SADDR

SADEN

Given

0101 0110b

1111 1100b

0101 01XXb

The following is an example of how to use given addresses to address different slaves:

Slave A:

Slave B:

Slave C:

SADDR

SADEN

Given

1111 0001b

1111 1010b

1111 0X0Xb

SADDR

SADEN

Given

1111 0011b

1111 1001b

1111 0XX1b

SADDR

SADEN

Given

1111 0010b

1111 1101b

1111 00X1b

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Rev. B - November 10, 2000

Preliminary

T80C5112

The SADEN byte is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a donÕt-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A

only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).

For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a donÕt care bit. To communicate with slaves B and C, but

not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2

clear (e.g. 1111 0001b).

11.2.2. Broadcast Address

A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as

donÕt-care bits, e.g.:

SADDR

0101 0110b

SADEN

1111 1100b

Broadcast =SADDR OR SADEN

1111 111Xb

The use of donÕt-care bits provides flexibility in defining the broadcast address, however in most applications, a

broadcast address is FFh. The following is an example of using broadcast addresses:

Slave A:

Slave B:

Slave C:

SADDR

1111 0001b

SADEN

1111 1010b

Broadcast 1111 1X11b,

SADDR

SADEN

1111 0011b

1111 1001b

Broadcast 1111 1X11B,

SADDR=

SADEN

Broadcast 1111 1111b

1111 0010b

1111 1101b

For slaves A and B, bit 2 is a donÕt care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the

master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send

and address FBh.

11.2.3. Reset Addresses

On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX

XXXXb (all donÕt-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards

compatible with the 80C51 microcontrollers that do not support automatic address recognition.

11.3. Baud Rate Selection for UART for mode 1 and 3

The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON

registers.

Rev. B - November 10, 2000

33

Preliminary

T80C5112

TIMER1_BRG

0

1

/ 16

Rx Clock

INT_BRG

RBCK

TIMER1_BRG

0

/ 16

1

Tx Clock

INT_BRG

TBCK

Figure 13. Baud Rate selection

11.3.1. Baud Rate selection table for UART

Clock Source for

UART Tx

Clock Source

UART Rx

TBCK

RBCK

0

1

0

1

0

1

Timer 1

INT_BRG

Timer 1

INT_BRG

11.3.2. Internal Baud Rate Generator (BRG)

When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending

on the BRL reload value, the X2 bit in CKON0 register, the value of SPD bit (Speed Mode) in BDRCON register

and the value of the SMOD1 bit in PCON register (for UART). :

SMOD1

/2

0

INT_BRG

1

auto reload counter

Peripheral clock

0

1

/6

BRG

overßow

BRL

SPD

BRR

Figure 14. Internal Baud Rate Generator

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Rev. B - November 10, 2000

Preliminary

T80C5112

·

for UART

SMOD1

X2

x 2 x FXTAL

2

Baud_Rate =

(BRL) = 256 -

(1-SPD)

2 x 2 x 6

x 16 x [256 - (BRL)]

SMOD1

X2

2

x 2 x FXTAL

(1-SPD)

2 x 2 x 6

x 16 x Baud_Rate

Example of computed value when X2=1, SMOD1=1, SPD=1

Baud Rates

F_XTAL= 16.384 MHz

F_XTAL= 24MHz

BRL

Error (%)

1.23

BRL

243

230

217

204

178

100

-

Error (%)

0.16

-

115200

57600

38400

28800

19200

9600

247

238

229

220

203

149

43

1.23

0.63

0.31

4800

1.23

Example of computed value when X2=0, SMOD1=0, SPD=0

Baud Rates

F_OSC= 16.384 MHz

F_OSC= 24MHz

BRL

Error (%)

1.23

BRL

243

230

202

152

Error (%)

0.16

4800

2400

1200

600

247

238

220

185

1.23

0.16

1.23

3.55

0.16

The baud rate generator can be used for mode 1 or 3 (refer to figures 13 ), but also for mode 0 for both UARTs,

thanks to the bit SRC located in BDRCON register (Table 20)

11.4. UARTs registers

SADEN - Slave Address Mask Register for UART (B9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

SADDR - Slave Address Register for UART (A9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Rev. B - November 10, 2000

35

Preliminary

T80C5112

SBUF - Serial Buffer Register for UART (99h)

7

6

5

4

3

2

1

0

Reset Value = XXXX XXXXb

BRL - Baud Rate Reload Register for the internal baud rate generator, UART UART(9Ah)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

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Rev. B - November 10, 2000

Preliminary

T80C5112

Table 18. SCON Register

SCON - Serial Control Register for UART (98h)

7

6

5

4

3

2

1

0

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

Bit

Mnemonic

Bit Number

Description

7

FE

Framing Error bit (SMOD0=1) for UART

Clear to reset the error state, not cleared by a valid stop bit.

Set by hardware when an invalid stop bit is detected.

SMOD0 must be set to enable access to the FE bit

SM0

SM1

Serial port Mode bit 0 (SMOD0=0) for UART

Refer to SM1 for serial port mode selection.

SMOD0 must be cleared to enable access to the SM0 bit

6

5

Serial port Mode bit 1 for UART

SM0

SM1

ModeDescriptionBaud Rate

0

0Shift RegisterF /12 (F

/6 X2 mode)

XTAL

0

1

0

18-bit UARTVariable

29-bit UARTF /64 or F

/32 (F

/32 or F

/16 X2 mode)

XTAL

1

39-bit UARTVariable

SM2

Serial port Mode 2 bit / Multiprocessor Communication Enable bit for UART

Clear to disable multiprocessor communication feature.

Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit

should be cleared in mode 0.

4

3

REN

TB8

Reception Enable bit for UART

Clear to disable serial reception.

Set to enable serial reception.

Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 for UART.

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

2

RB8

Receiver Bit 8 / Ninth bit received in modes 2 and 3 for UART

Cleared by hardware if 9th bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.

1

0

TI

RI

Transmit Interrupt ﬂag for UART

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other

modes.

Receive Interrupt ﬂag for UART

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, see Figure 11. and Figure 12. in the other modes.

Reset Value = 0000 0000b

Bit addressable

Rev. B - November 10, 2000

37

Preliminary

T80C5112

Table 19. PCON Register

PCON - Power Control Register (87h)

7

6

5

4

3

2

1

0

SMOD1

SMOD0

RSTD

POF

GF1

GF0

PD

IDL

Bit

Mnemonic

Bit Number

Description

7

SMOD1

Serial port Mode bit 1 for UART

Set to select double baud rate in mode 1, 2 or 3.

6

5

SMOD0

Serial port Mode bit 0 for UART

Clear to select SM0 bit in SCON register.

Set to to select FE bit in SCON register.

RSTD

Reset Detector Disable Bit

Clear to disable PFD.

Set to enable PFD.

4

3

2

1

0

POF

GF1

GF0

PD

Power-Off Flag

Clear to recognize next reset type.

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

Power-Down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

IDL

Idle mode bit

Clear by hardware when interrupt or reset occurs.

Set to enter idle mode.

Reset Value = 0001 0000b

Not bit addressable

Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesnÕt affect the value of this bit.

38

Rev. B - November 10, 2000

Preliminary

T80C5112

Table 20. BDRCON Register

BDRCON - Baud Rate Control Register (9Bh)

7

-

6

-

5

-

4

3

2

1

0

BRR

TBCK

RBCK

SPD

SRC

Bit

Number

Bit

Mnemonic

Description

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Baud Rate Run Control bit

7

6

5

-

4

3

2

1

0

BRR

TBCK

RBCK

SPD

Clear to stop the internal Baud Rate Generator.

Set to start the internal Baud Rate Generator.

Transmission Baud rate Generator Selection bit for UART

Clear to select Timer 1 or Timer 2 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

Reception Baud Rate Generator Selection bit for UART

Clear to select Timer 1 or Timer 2 for the Baud Rate Generator.

Set to select internal Baud Rate Generator.

Baud Rate Speed Control bit for UART

Clear to select the SLOW Baud Rate Generator.

Set to select the FAST Baud Rate Generator.

Baud Rate Source select bit in Mode 0 for UART

SRC

Clear to select F

/12 as the Baud Rate Generator (F

/6 in X2 mode).

OSC

Set to select the internal Baud Rate Generator for UARTs in mode 0.

Reset Value = XXX0 0000b

Rev. B - November 10, 2000

39

Preliminary

T80C5112

12. Serial Port Interface (SPI)

12.1. Introduction

The Serial Peripheral Interface module (SPI) which allows full-duplex, synchronous, serial communication between

the MCU and peripheral devices, including other MCUs.

12.2. Features

Features of the SPI module include the following:

·

Full-duplex, three-wire synchronous transfers

Master or Slave operation

Eight programmable Master clock rates

Serial clock with programmable polarity and phase

Master Mode fault error flag with MCU interrupt capability

Write collision flag protection

12.3. Signal Description

Figure 15 shows a typical SPI bus configuration using one Master controller and many Slave peripherals. The bus

is made of three wires connecting all the devices:

Slave 1

MISO

MOSI

SCK

SS

V

DD

Master

0

1

2

3

Slave 4

Slave 3

Slave 2

Figure 15. Typical SPI bus

The Master device selects the individual Slave devices by using four pins of a parallel port to control the four SS

pins of the Slave devices.

12.3.1. Master Output Slave Input (MOSI)

This 1-bit signal is directly connected between the Master Device and a Slave Device. The MOSI line is used to

transfer data in series from the Master to the Slave. Therefore, it is an output signal from the Master, and an input

signal to a Slave. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB)last.

40

Rev. B - November 10, 2000

Preliminary

T80C5112

12.3.2. Master Input Slave Output (MISO)

This 1-bit signal is directly connected between the Slave Device and a Master Device. The MISO line is used to

transfer data in series from the Slave to the Master. Therefore, it is an output signal from the Slave, and an input

signal to the Master. A byte (8-bit word) is transmitted most significant bit (MSB) first, least significant bit (LSB) last.

12.3.3. SPI Serial Clock (SCK)

This signal is used to synchronize the data movement both in and out the devices through their MOSI and MISO

lines. It is driven by the Master for eight clock cycles which allows to exchange one byte on the serial lines.

12.3.4. Slave Select (SS)

Each Slave peripheral is selected by one Slave Select pin (SS). This signal must stay low for any message for a

Slave. It is obvious that only one Master (SS high level) can drive the network. The Master may select each Slave

device by software through port pins (Figure 15). To prevent bus conflicts on the MISO line, only one slave should

be selected at a time by the Master for a transmission.

In a Master configuration, the SS line can be used in conjunction with the MODF flag in the SPI Status register

(SPSTA) to prevent multiple masters from driving MOSI and SCK (See Error conditions).

A high level on the SS pin puts the MISO line of a Slave SPI in a high-impedance state.

The SS pin could be used as a general purpose if the following conditions are met:

·

The device is configured as a Master and the SSDIS control bit in SPCON is set. This kind of configuration

can be found when only one Master is driving the network and there is no way that the SS pin will be

pulled low. Therefore, the MODF flag in the SPSTA will never be set .

1

2

·

The Device is configured as a Slave with CPHA and SSDIS control bits set . This kind of configuration

can happen when the system comprises one Master and one Slave only. Therefore, the device should always

be selected and there is no raison that the Master uses the SS pin to select the communicating Slave device.

12.3.5. Baud rate

In Master mode, the baud rate can be selected from a baud rate generator which is controled by three bits in the

SPCON register: SPR2, SPR1 and SPR0. The Master clock is chosen from one of seven clock rates resulting from

the division of the internal clock by 2, 4, 8, 16, 32, 64 or 128, or an external clock.

Table 21 gives the different clock rates selected by SPR2:SPR1:SPR0:

Table 21. SPI Master baud rate selection

SPR2:SPR1:SPR0

Clock Rate

Baud rate divisor (BD)

000

001

010

011

100

101

110

111

F

/2

/4

2

CkIdle

4

F

/ 8

/16

/32

8

CkIdle

F

16

CkIdle

F

32

CkIdle

F

/64

64

128

CkIdleH

F

/128

CkIdle

External clock

Output of BRG

1. Clearing SSDIS control bit does not clear MODF.

2. Special care should be taken not to set SSDIS control bit when CPHA = Õ0Õ because in this mode, thSeS is used to start the transmission.

Rev. B - November 10, 2000

41

Preliminary

T80C5112

12.4. Functional Description

Figure 16 shows a detailed structure of the SPI module.

Internal Bus

SPDAT

Shift Register

IntClk

7

6

5

4

3

2

1

0

/2

/4

/8

/16

/32

/64

/128

Clock

Divider

Receive Data Register

Control

Logic

MOSI

MISO

Clock

Logic

M

S

SCK

SS

Clock

Select

External Clk

SPR2 SPEN SSDIS MSTR CPOL CPHA SPR1 SPR0

SPCON

8-bit bus

SPI

1-bit signal

Control

SPI Interrupt Request

SPSTA

-

SPIF WCOL

MODF

Figure 16. SPI Module Block Diagram

12.4.1. Operating Modes

The Serial Peripheral Interface can be configured as one of the two modes: Master mode or Salve mode. The

configuration and initialization of the SPI module is made through one register:

·

The Serial Peripheral CONtrol register (SPCON)

Once the SPI is configured, the data exchange is made using:

·

SPCON

The Serial Peripheral STAtus register (SPSTA)

The Serial Peripheral DATa register (SPDAT)

During an SPI transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially).

A serial clock line (SCK) synchronizes shifting and sampling on the two serial data lines (MOSI and MISO). A

Slave Select line (SS) allows individual selection of a Slave SPI device; Slave devices that are not selected do not

interfere with SPI bus activities.

When the Master device transmits data to the Slave device via the MOSI line, the Slave device responds by sending

data to the Master device via the MISO line. This implies full-duplex transmission with both data out and data in

synchronized with the same clock (Figure 17).

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Rev. B - November 10, 2000

Preliminary

T80C5112

MISO

MOSI

MISO

MOSI

8-bit Shift register

SPI

Clock Generator

SCK

SS

SCK

SS

V

DD

Master MCU

Slave MCU

V_SS

Figure 17. Full-Duplex Master-Slave Interconnection

12.4.1.1. Master mode

1

The SPI operates in Master mode when the Master bit, MSTR , in the SPCON register is set. Only one Master

SPI device can initiate transmissions. Software begins the transmission from a Master SPI module by writing to

the Serial Peripheral Data Register (SPDAT). If the shift register is empty, the byte is immediately transferred to

the shift register. The byte begins shifting out on MOSI pin under the control of the serial clock, SCK. Simultaneously,

another byte shifts in from the Slave on the MasterÕs MISO pin. The transmission ends when the Serial Peripheral

transfer data flag, SPIF, in SPSTA becomes set. At the same time that SPIF becomes set, the received byte from

the Slave is transferred to the receive data register in SPDAT. Software clears SPIF by reading the Serial Peripheral

Status register (SPSTA) with the SPIF bit set, and then reading the SPDAT.

When the pin SS is pulled down during a transmission, the data is interrupted and when the transmission is

established again, the data present in the SPDAT is resent.

12.4.1.2. Slave mode

2

The SPI operates in Slave mode when the Master bit, MSTR , in the SPCON register is cleared. Before a data

transmission occurs, the Slave Select pin, SS, of the Slave device must be set to Õ0ÕS. S must remain low until

the transmission is complete.

In a Slave SPI module, data enters the shift register under the control of the SCK from the Master SPI module.

After a byte enters the shift register, it is immediately transferred to the receive data register in SPDAT, and the

SPIF bit is set. To prevent an overflow condition, Slave software must then read the SPDAT before another byte

3

enters the shift register . A Slave SPI must complete the write to the SPDAT (shift register) at least one bus cycle

before the Master SPI starts a transmission. If the write to the data register is late, the SPI transmits the data

already in the shift register from the previous transmission.

12.4.2. Transmission Formats

Software can select any of four combinations of serial clock (SCK) phase and polarity using two bits in the SPCON:

4

the Clock POLarity (CPOL ) and the Clock PHAse (CPHA ). CPOL defines the default SCK line level in idle

state. It has no significant effect on the transmission format. CPHA defines the edges on which the input data are

sampled and the edges on which the output data are shifted (Figure 18 and Figure 19). The clock phase and polarity

should be identical for the Master SPI device and the communicating Slave device.

1. The SPI module should be configured as a Master before it is enabled (SPEN set). Also the Master SPI should be configured before the Slave SPI.

2. The SPI module should be configured as a Slave before it is enabled (SPEN set).

3. The maximum frequency of the SCK for an SPI configured as a Slave is the bus clock speed.

4. Before writing to the CPOL and CPHA bits, the SPI should be disabled (SPEN = Õ0Õ).

Rev. B - November 10, 2000

43

Preliminary

T80C5112

1

2

3

4

5

6

7

8

SCK cycle number

SPEN (internal)

SCK (CPOL = 0)

SCK (CPOL = 1)

MOSI (from Master)

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

MISO (from Slave)

MSB

SS (to Slave)

Capture point

Figure 18. Data Transmission Format (CPHA = 0)

1

2

3

4

5

6

7

8

SCK cycle number

SPEN (internal)

SCK (CPOL = 0)

SCK (CPOL = 1)

MSB

bit6

bit5

bit4

bit3

bit2

bit1

LSB

MOSI (from Master)

MISO (from Slave)

SS (to Slave)

Capture point

Figure 19. Data Transmission Format (CPHA = 1)

As shown in Figure 18, the first SCK edge is the MSB capture strobe. Therefore the Slave must begin driving its

data before the first SCK edge, and a falling edge on the SS pin is used to start the transmission. The SS pin must

be toggled high and then low between each byte transmitted (Figure 20).

Byte 3

MISO/MOSI

Master SS

Byte 1

Byte 2

Slave SS

(CPHA = 0)

Slave SS

(CPHA = 1)

Figure 20. CPHA/SS timing

Figure 19 shows an SPI transmission in which CPHA is Õ1Õ. In this case, the Master begins driving its MOSI pin

on the first SCK edge. Therefore the Slave uses the first SCK edge as a start transmission signal. The SS pin can

remain low between transmissions (Figure 20). This format may be preferable in systems having only one Master

and only one Slave driving the MISO data line.

44

Rev. B - November 10, 2000

Preliminary

T80C5112

12.4.3. Error conditions

The following flags in the SPSTA signal SPI error conditions:

12.4.3.1. Mode Fault (MODF)

MODe Fault error in Master mode SPI indicates that the level on the Slave Select (SS) pin is inconsistent with

the actual mode of the device. MODF is set to warn that there may have a multi-master conflict for system control.

In this case, the SPI system is affected in the following ways:

·

An SPI receiver/error CPU interrupt request is generated.

The SPEN bit in SPCON is cleared. This disable the SPI.

The MSTR bit in SPCON is cleared.

When SS DISable (SSDIS) bit in the SPCON register is cleared, the MODF flag is set when the SS signal becomes Õ0Õ.

However, as stated before, for a system with one Master, if the SS pin of the Master device is pulled low, there

is no way that another Master is attempting to drive the network. In this case, to prevent the MODF flag from

being set, software can set the SSDIS bit in the SPCON register and therefore making the SS pin as a general

purpose I/O pin.

Clearing the MODF bit is accomplished by a read of SPSTA register with MODF bit set, followed by a write to

the SPCON register. SPEN Control bit may be restored to its original set state after the MODF bit has been cleared.

12.4.3.2. Write Collision (WCOL)

A Write COLlision (WCOL) flag in the SPSTA is set when a write to the SPDAT register is done during a transmit

sequence.

WCOL does not cause an interruption, and the transfer continues uninterrupted.

Clearing the WCOL bit is done through a software sequence of an access to SPSTA and an access to SPDAT.

12.4.3.3. Overrun Condition

An overrun condition occurs when the Master device tries to send several data bytes and the Slave devise has not

cleared the SPIF bit issuing from the previous data byte transmitted. In this case, the receiver buffer contains the

byte sent after the SPIF bit was last cleared. A read of the SPDAT returns this byte. All others bytes are lost.

This condition is not detected by the SPI peripheral.

12.4.4. Interrupts

Two SPI status flags can generate a CPU interrupt requests:

Flag

Request

SPIF (SP data transfer)

MODF (Mode Fault)

SPI Transmitter Interrupt request

SPI Receiver/Error Interrupt Request (if SSDIS = Õ0Õ)

Table 22. SPI Interrupts

Serial Peripheral data transfer flag, SPIF: This bit is set by hardware when a transfer has been completed. SPIF

bit generates transmitter CPU interrupt requests.

Mode Fault flag, MODF: This bit becomes set to indicate that the level on the SS is inconsistent with the mode

of the SPI. MODF with SSDIS reset, generates receiver/error CPU interrupt requests.

Figure 21 gives a logical view of the above statements:

Rev. B - November 10, 2000

45

Preliminary

T80C5112

SPIF

SPI Transmitter

CPU Interrupt Request

SPI

CPU Interrupt Request

MODF

SPI Receiver/error

CPU Interrupt Request

SSDIS

Figure 21. SPI Interrupt Requests Generation

12.4.5. Registers

There are three registers in the module that provide control, status and data storage functions. These registers are

describes in the following paragraphs.

12.4.5.1. Serial Peripheral CONtrol register (SPCON)

The Serial Peripheral Control Register does the following:

·

Selects one of the Master clock rates,

Configure the SPI module as Master or Slave,

Selects serial clock polarity and phase,

Enables the SPI module,

Frees the SS pin for a general purpose

Table 23 describes this register and explains the use of each bit:

Table 23. Serial Peripheral Control Register

7

6

5

4

3

2

1

0

SPR2

SPEN

SSDIS

MSTR

CPOL

CPHA

SPR1

SPR0

Bit

Number

R/W

Mode

Bit Mnemonic

Description

Serial Peripheral Rate 2

Bit with SPR1 and SPR0 define the clock rate

7

SPR2

RW

Serial Peripheral Enable

6

5

SPEN

RW

Clear to disable the SPI interface

Set to enable the SPI interface

SS Disable

Clear to enable SS# in both Master and Slave modes

Set to disable SS# in both Master and Slave modes. In Slave mode, this bit has no effect if

CPHA = Õ0Õ

SSDIS

Serial Peripheral Master

4

3

2

MSTR

CPOL

CPHA

RW

Clear to configure the SPI as a Slave

Set to configure the SPI as a Master

Clock Polarity

Clear to have the SCK set to Õ0Õ in idle state

Set to have the SCK set to Õ1Õ in idle low

Clock Phase

Clear to have the data sampled when the SPSCK leaves the idle state (see CPOL)

Set to have the data sampled when the SPSCK returns to idle state (see CPOL)

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Rev. B - November 10, 2000

Preliminary

T80C5112

Bit

Number

R/W

Mode

Bit Mnemonic

Description

Serial Peripheral Rate (SPR2:SPR1:SPR0)

000 : F

001 : F

010 : F

011 : F

/2

/4

/8

/16

CLK PERIPH

1

0

SPR1

RW

100 : F

101 : F

110 : F

/32

/64

/128

CLK PERIPH

SPR0

111 : External clock, output of BRG

Reset Value= 00010100b

12.4.5.2. Serial Peripheral STAtus register (SPSTA)

The Serial Peripheral Status Register contains flags to signal the following conditions:

·

Data transfer complete

Write collision

Inconsistent logic level on SS pin (mode fault error)

Table 24 describes the SPSTA register and explains the use of every bit in the register:

7

6

5

4

3

2

1

0

SPIF

WCOL

-

MODF

-

Bit

Number

R/W

Mode

Bit Mnemonic

Description

Serial Peripheral data transfer flag

Clear by hardware to indicate data transfer is in progress or has been approved by a clearing

sequence.

7

SPIF

R

Set by hardware to indicate that the data transfer has been completed.

Write Collision flag

Cleared by hardware to indicate that no collision has occurred or has been approved by a

clearing sequence.

Set by hardware to indicate that a collision has been detected.

6

5

4

WCOL

-

R

RW

R

Reserved

The value read from this bit is indeterminate. Do not set this bit

Mode Fault

Cleared by hardware to indicate that the SS pin is at appropriate logic level, or has been

approved by a clearing sequence.

MODF

Set by hardware to indicate that the SS pin is at inappropriate logic level

Reserved

3

2

1

0

-

RW

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reserved

The value read from this bit is indeterminate. Do not set this bit

Reset Value= 00X0XXXXb

Table 24. Serial Peripheral Status and Control register

Rev. B - November 10, 2000

47

Preliminary

T80C5112

12.4.5.3. Serial Peripheral DATa register (SPDAT)

The Serial Peripheral Data Register (Table 25) is a read/write buffer for the receive data register. A write to SPDAT

places data directly into the shift register. No transmit buffer is available in this model.

A Read of the SPDAT returns the value located in the receive buffer and not the content of the shift register.

Table 25. Serial Peripheral Data Register

7

6

5

4

3

2

1

0

R7

R6

R5

R4

R3

R2

R1

R0

Reset Value= XXXX XXXXb

R7:R0 : Receive data bits

SPCON, SPSTA and SPDAT registers may be read and written at any time while there is no on-going exchange.

However, special care should be taken when writing to them while a transmission is on-going:

·

Do not change SPR2, SPR1 and SPR0

Do not change CPHA and CPOL

Do not change MSTR

Clearing SPEN would immediately disable the peripheral

Writing to the SPDAT will cause an overflow

48

Rev. B - November 10, 2000

Preliminary

T80C5112

13. Programmable Counter Array PCA

The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its

advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/

counter which serves as the time base for an array of five compare/ capture modules. Its clock input can be

programmed to count any one of the following signals:

·

Oscillator frequency ¸ 12 (¸ 6 in X2 mode)

Oscillator frequency ¸ 4 (¸ 2 in X2 mode)

Timer 0 overflow

External input on ECI (P1.2)

Each compare/capture modules can be programmed in any one of the following modes:

·

rising and/or falling edge capture,

software timer,

high-speed output, or

pulse width modulator.

Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog Timer", page 58).

When the compare/capture modules are programmed in the capture mode, software timer, or high speed output

mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer

overflow share one interrupt vector.

The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below.

If the port is not used for the PCA, it can still be used for standard I/O.

PCA component

External I/O Pin

16-bit Counter

P1.2 / ECI

16-bit Module 0

16-bit Module 1

16-bit Module 2

16-bit Module 3

16-bit Module 4

P1.3 / CEX0

P1.4 / CEX1

P1.5 / CEX2

P1.6 / CEX3

P1.7 / CEX4

The PCA timer is a common time base for all five modules (See Figure 22). The timer count source is determined

from the CPS1 and CPS0 bits in the CMOD SFR (See Table 26) and can be programmed to run at:

·

1/12 the oscillator frequency. (Or 1/6 in X2 Mode)

1/4 the oscillator frequency. (Or 1/2 in X2 Mode)

The Timer 0 overflow.

The input on the ECI pin (P1.2).

Rev. B - November 10, 2000

49

Preliminary

T80C5112

To PCA

modules

Fosc /12

Fosc / 4

T0 OVF

P1.2

overßow

It

CH

CL

16 bit up/down counter

CMOD

0xD9

CIDL WDTE

CPS1 CPS0 ECF

Idle

CCON

0xD8

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

Figure 22. PCA Timer/Counter

Table 26. CMOD: PCA Counter Mode Register

CMOD

Address 0D9H

CIDL WDTE

-

CPS1 CPS0

ECF

Reset value

0

X

0

Symbol

Function

Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during

idle Mode. CIDL = 1 programs it to be gated off during idle.

CIDL

Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4.

WDTE = 1 enables it.

WDTE

a

-

Not implemented, reserved for future use.

CPS1

CPS0

PCA Count Pulse Select bit 1.

PCA Count Pulse Select bit 0.

b

CPS1 CPS0 Selected PCA input.

0

1

0

1

0

1

Internal clock f /12 ( Or f /6 in X2 Mode).

osc osc

Internal clock f /4 ( Or f /2 in X2 Mode).

osc

Timer 0 Overflow

External clock at ECI/P1.2 pin (max rate = f / 8)

osc

PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an

interrupt. ECF = 0 disables that function of CF.

ECF

a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family

products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its

active value will be 1. The value read from a reserved bit is indeterminate.

b.

f

= oscillator frequency

osc

50

Rev. B - November 10, 2000

Preliminary

T80C5112

The CMOD SFR includes three additional bits associated with the PCA (See Figure 22 and Table 26).

·

The CIDL bit which allows the PCA to stop during idle mode.

The WDTE bit which enables or disables the watchdog function on module 4.

The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set

when the PCA timer overflows.

The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module

(Refer to Table 27).

·

Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit.

Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the

ECF bit in the CMOD register is set. The CF bit can only be cleared by software.

·

Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by

hardware when either a match or a capture occurs. These flags also can only be cleared by software.

Table 27. CCON: PCA Counter Control Register

CCON

Address 0D8H

CF

0

CR

0

-

CCF4

0

CCF3

0

CCF2

0

CCF1

0

CCF0

0

Reset value

X

Symbol

Function

PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags

an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but

can only be cleared by software.

CF

PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared

by software to turn the PCA counter off.

CR

-

a

Not implemented, reserved for future use.

PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be

cleared by software.

CCF4

PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be

cleared by software.

CCF3

CCF2

CCF1

CCF0

PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be

cleared by software.

PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be

cleared by software.

PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be

cleared by software.

a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family

products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its

active value will be 1. The value read from a reserved bit is indeterminate.

The watchdog timer function is implemented in module 4 (See Figure 25).

The PCA interrupt system is shown in Figure 23

Rev. B - November 10, 2000

51

Preliminary

T80C5112

CCON

0xD8

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

PCA Timer/Counter

Module 0

Module 1

Module 2

Module 3

To Interrupt

priority decoder

Module 4

CMOD.0

IE.6

EC

IE.7

EA

CCAPMn.0

ECCFn

ECF

Figure 23. PCA Interrupt System

PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform:

·

16-bit Capture, positive-edge triggered,

16-bit Capture, negative-edge triggered,

16-bit Capture, both positive and negative-edge triggered,

16-bit Software Timer,

16-bit High Speed Output,

8-bit Pulse Width Modulator.

In addition, module 4 can be used as a Watchdog Timer.

Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module

0, CCAPM1 for module 1, etc. (See Table 28). The registers contain the bits that control the mode that each

module will operate in.

·

The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the

CCON SFR to generate an interrupt when a match or compare occurs in the associated module.

·

PWM (CCAPMn.1) enables the pulse width modulation mode.

The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there

is a match between the PCA counter and the module's capture/compare register.

·

The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there

is a match between the PCA counter and the module's capture/compare register.

The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will

be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both

bits are set both edges will be enabled and a capture will occur for either transition.

·

The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.

Table 29 shows the CCAPMn settings for the various PCA functions.

52

Rev. B - November 10, 2000

Preliminary

T80C5112

Table 28. CCAPMn: PCA Modules Compare/Capture Control Registers

CCAPM0=0DAH

CCAPM1=0DBH

CCAPM2=0DCH

CCAPM3=0DDH

CCAPM4=0DEH

CCAPMn Address

n = 0 - 4

-

ECOMn CAPPn CAPNn MATn

TOGn PWMm ECCFn

Reset value

X

0

Symbol

Function

a

-

Not implemented, reserved for future use.

ECOMn

CAPPn

CAPNn

Enable Comparator. ECOMn = 1 enables the comparator function.

Capture Positive, CAPPn = 1 enables positive edge capture.

Capture Negative, CAPNn = 1 enables negative edge capture.

Match. When MATn = 1, a match of the PCA counter with this module's compare/capture

register causes the CCFn bit in CCON to be set, flagging an interrupt.

MATn

TOGn

PWMn

ECCFn

Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture

register causes the CEXn pin to toggle.

Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width

modulated output.

Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate

an interrupt.

a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family

products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its

active value will be 1. The value read from a reserved bit is indeterminate.

Table 29. PCA Module Modes (CCAPMn Registers)

ECOMn CAPPn CAPNn MATn TOGn PWMm ECCFn

Module Function

No Operation

0

1

0

16-bit capture by

trigger on CEXn

a positive-edge

X

16-bit capture by a negative trigger on

CEXn

X

1

0

1

0

1

0

1

0

X

16-bit capture by a transition on CEXn

16-bit Software Timer

mode.

/ Compare

1

0

1

0

1

0

1

0

X

0

16-bit High Speed Output

8-bit PWM

X

Watchdog Timer (module 4 only)

There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and

these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module

is used in the PWM mode these registers are used to control the duty cycle of the output (See Table 30 & Table 31)

Rev. B - November 10, 2000

53

Preliminary

T80C5112

Table 30. CCAPnH: PCA Modules Capture/Compare Registers High

CCAP0H=0FAH

CCAP1H=0FBH

CCAP2H=0FCH

CCAP3H=0FDH

CCAP4H=0FEH

CCAPnH Address

n = 0 - 4

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset value

Table 31. CCAPnL: PCA Modules Capture/Compare Registers Low

CCAP0L=0EAH

CCAP1L=0EBH

CCAP2L=0ECH

CCAP3L=0EDH

CCAP4L=0EEH

CCAPnL Address

n = 0 - 4

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset value

Table 32. CH: PCA Counter High

CH

Address 0F9H

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Table 33. CL: PCA Counter Low

CL

Address 0E9H

7

0

6

0

5

0

4

0

3

0

2

0

1

0

13.1. PCA Capture Mode

To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for

that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a

valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the

module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the

ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated (Refer to Figure 24).

54

Rev. B - November 10, 2000

Preliminary

T80C5112

CCON

0xD8

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

PCA IT

PCA Counter/Timer

Cex.n

CH

CL

Capture

CCAPnH

CCAPnL

CCAPMn, n= 0 to 4

0xDA to 0xDE

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

Figure 24. PCA Capture Mode

13.2. 16-bit Software Timer / Compare Mode

The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules

CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs

an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both

set (See Figure 25).

Rev. B - November 10, 2000

55

Preliminary

T80C5112

CCON

0xD8

CCF4

CF

CR

CCF3 CCF2 CCF1 CCF0

Write to

CCAPnL Reset

PCA IT

Write to

CCAPnH

CCAPnL

Enable

1

0

Match

16 bit comparator

RESET *

CH

CL

PCA counter/timer

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

CMOD

0xD9

CIDL WDTE

CPS1 CPS0 ECF

* Only for Module 4

Figure 25. PCA Compare Mode and PCA Watchdog Timer

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted

match could happen. Writing to CCAPnH will set the ECOM bit.

Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesnÕt occur while modifying

the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first,

and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.

13.3. High Speed Output Mode

In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs

between the PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM

bits in the module's CCAPMn SFR must be set (See Figure 26).

A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.

56

Rev. B - November 10, 2000

Preliminary

T80C5112

CCON

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

0xD8

Write to

CCAPnL

Reset

PCA IT

Write to

CCAPnH

CCAPnL

0

Enable

1

Match

16 bit comparator

CEXn

CH

CL

PCA counter/timer

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

Figure 26. PCA High Speed Output Mode

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted

match could happen.

Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesnÕt occur while modifying

the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first,

and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.

13.4. Pulse Width Modulator Mode

All of the PCA modules can be used as PWM outputs. Figure 27 shows the PWM function. The frequency of the

output depends on the source for the PCA timer. All of the modules will have the same frequency of output

because they all share the PCA timer. The duty cycle of each module is independently variable using the module's

capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn

Rev. B - November 10, 2000

57

Preliminary

T80C5112

SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from

FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The

PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode.

CCAPnH

Overßow

CCAPnL

Ò0Ó

CEXn

Enable

<

³

8 bit comparator

Ò1Ó

CL

PCA counter/timer

CCAPMn, n= 0 to 4

0xDA to 0xDE

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

Figure 27. PCA PWM Mode

13.5. PCA Watchdog Timer

An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing

chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic

discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can

still be used for other modes if the watchdog is not needed. Figure 25 shows a diagram of how the watchdog

works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit

value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This

will not cause the RST pin to be driven high.

In order to hold off the reset, the user has three options:

·

1. periodically change the compare value so it will never match the PCA timer,

2. periodically change the PCA timer value so it will never match the compare values, or

3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it.

The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program

counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not

recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules;

changing the time base for other modules would not be a good idea. Thus, in most applications the first solution

is the best option.

This watchdog timer wonÕt generate a reset out on the reset pin.

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14. Analog-to-Digital Converter (ADC)

14.1. Introduction

This section describes the on-chip 10 bit analog-to-digital converter of the T80C5112. Eight ADC channels are

available for sampling of the external sources AN0 to AN7. An analog multiplexer allows the single ADC converter

to select one from the 8 ADC channels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bit-

cascaded potentiometric ADC.

Three kind of conversion are available:

·

Standard conversion (7-8 bits).

Precision conversion (8-9 bits).

Accurate conversion (10 bits).

For the precision conversion, set bits PSIDLE and ADSST in ADCON register to start the conversion. The chip

is in a idle mode, the CPU doesnÕt run but the peripherals are always running. This mode allows digital noise to

be lower, to ensure precise conversion.

For the accurate conversion, set bits QUIETM and ADSST in ADCON register to start the conversion. The chip

is in a pseudo-idle mode, the AD is the only peripheral running. This mode allows digital noise to be as low as

possible, to ensure high precision conversion.

For these modes it is necessary to work with end of conversion interrupt, which is the only way to wake up the chip.

If another interrupt occurs during the precision conversion, it will be treated only after this conversion is ended.

14.2. Features

·

8 channels with multiplexed inputs

10-bit cascaded potentiometric ADC

Conversion time 40 micro-seconds

Zero Error (offset) +/- 2 LSB max

External Positive Reference Voltage Range 2.4 to Vcc

Internal Positive Reference Voltage 2.4 Volt. If Vref is used as output, the load must be higher than 18 kOhm.

ADCIN Range 0 to Vcc

Integral non-linearity typical 1 LSB, max. 2 LSB

Differential non-linearity typical 0.5 LSB, max. 1 LSB

Conversion Complete Flag or Conversion Complete Interrupt

Selected ADC Clock

14.3. ADC I/O Functions

AINx are general I/O that are shared with the ADC channels. The channel select bit in ADCF register define

which ADC channel pin will be used as ADCIN. The remaining ADC channels pins can be used as general purpose

I/O or as the alternate function that is available. Writes to the port register which arenÕt selected by the ADCF

will not have any effect.

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59

Preliminary

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ADCON.5

ADCON.3

ADEN

ADSST

ADCON.4

ADC

Interrupt

Request

ADEOC

CONTROL

CONV_CK

EADC

IE1.1

AIN0/P4.0

AIN1/P4.1

AIN2/P4.2

AIN3/P4.3

AIN4/P4.4

AIN5/P4.5

AIN6/P4.6

AIN7/P4.7

000

001

010

011

100

101

110

111

8

2

ADCIN

ADDH

ADDL

+

-

SAR

AVSS

Sample and Hold

10

R/2R DAC

ADCLK.7

VAGND

ADCON.5

SELREF

ADEN

SCH2

SCH1

SCH0

2.4V

ADCON.2 ADCON.1 ADCON.0

Vref

VADREF

Figure 28. ADC Description

Figure 29 shows the timing diagram of a complete conversion. For simplicity, the figure depicts the waveforms in

idealized form and do not provide precise timing information. For ADC characteristics and timing parameters refer

to the Section ÒAC CharacteristicsÓ of the T80C5112 datasheet.

CONV_CK

ADEN

T

SETUP

ADSST

ADEOC

T

CONV

Figure 29. Timing Diagram

NOTE:

Tsetup = 4 us

14.4. ADC Converter Operation

A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).

The busy flag ADSST(ADCON.3) remains set as long as an A/D conversion is running. After completion of the

A/D conversion, it is cleared by hardware. When a conversion is running, this flag can be read only, a write has

no effect.

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Rev. B - November 10, 2000

Preliminary

T80C5112

The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is available in ADDH and

ADDL, it is cleared by software. If the bit EADC (IE1.1) is set, an interrupt occur when flag ADEOC is set (see

Figure 31). Clear this flag for re-arming the interrupt.

The bits SCH0 to SCH2 in ADCON register are used for the analog input channel selection.

Before starting normal power reduction modes the ADC conversion has to be completed.

Table 34. Selected Analog input

SCH2

SCH1

SCH0

Selected Analog input

0

1

0

1

0

1

0

1

0

1

0

1

0

1

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

14.5. Voltage Conversion

When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If the input voltage

equals VAGND, the ADC converts it to 000h. Input voltage between VAREF and VAGND are a straight-line

linear conversion. All other voltages will result in 3FFh if greater than VAREF and 000h if less than VAGND.

Note that ADCIN should not exceed VAREF absolute maximum range.

14.6. Clock Selection

The maximum clock frequency for ADC (CONV_CK for Conversion Clock) is defined in the AC characteristics

section. A prescaler is featured (ADCCLK) to generate the CONV_CK clock from the oscillator frequency.

CONV_CK

CKADC

Prescaler ADCLK

/ 2

A/D

Converter

Figure 30. A/D Converter clock

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14.7. ADC Standby Mode

When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN in ADCON register.

In this mode the power dissipation is about 1uW.

14.8. Voltage referencee

The voltage reference can be either internal or external.

As input, the Vref pin is used to enter the voltage reference for the A/D conversion.

When the voltage reference is active, the Vref pin is an output. This voltage can be used for the A/D and for any

other application requiring a voltage independant from the power supply. Voltage typical value is 2.4 volt and the

load must greater than 18 kOms.

14.9. IT ADC management

An interrupt end-of-conversion will occurs when the bit ADEOC is actived and the bit EADC is set. For re-arming

the interrupt the bit ADEOC must be cleared by software.

ADCI

ADEOC

ADCON.2

EADC

IE1.1

Figure 31. ADC interrupt structure

14.10. Registers

Table 35. ADCON Register

ADCON (S:F3h)

ADC Control Register

7

6

5

4

3

2

1

0

QUIETM

PSIDLE

ADEN

ADEOC

ADSST

SCH2

SCH1

SCH0

Bit Number Bit Mnemonic

Description

Pseudo Idle mode (best precision)

Set to put in quiet mode during conversion.

7

6

QUIETM

PSIDLE

Cleared by hardware after completion of the conversion.

Pseudo Idle mode (good precision)

Set to put in idle mode during conversion.

Cleared by hardware after completion of the conversion.

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Bit Number Bit Mnemonic

Description

Enable/Standby Mode

5

4

ADEN

Set to enable ADC.

Clear for Standby mode (power dissipation 1 uW).

End Of Conversion

ADEOC

Set by hardware when ADC result is ready to be read. This flag can generate an interrupt.

Must be cleared by software.

Start and Status

3

ADSST

SCH2:0

Set to start an A/D conversion.

Cleared by hardware after completion of the conversion.

Selection of channel to convert

2-0

see Table 34.

Reset Value=X000 0000b

Table 36. ADCLK Register

ADCLK (S:F2h)

ADC Clock Prescaler

7

6

5

4

3

2

1

0

SELREF

PRS 6

PRS 5

PRS 4

PRS 3

PRS 2

PRS 1

PRS 0

Bit Number Bit Mnemonic

Description

Selection and activation of the internal 2.4V voltage reference

Set to enable the internal voltage reference.

7

SELREF

Clear to disable the internal voltage reference.

Clock Prescaler

f

= f

/ (2 * PRS)

CkADC

CONV_CK

6-0

PRS6:0

if PRS=0, f

= f

/ 256

CONV_CK

CkADC

Reset Value: 0000 0000b

Table 37. ADDH Register

ADDH (S:F5h Read Only)

ADC Data High byte register

7

6

5

4

3

2

1

0

ADAT 9

ADAT 8

ADAT 7

ADAT 6

ADAT 5

ADAT 4

ADAT 3

ADAT 2

Bit Number Bit Mnemonic

Description

ADC result

7-0

ADAT9:2

bits 9-2

Read only register

Reset Value: 00h

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Preliminary

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Table 38. ADDL Register

ADDL (S:F4h Read Only)

ADC Data Low byte register

7

-

6

-

5

-

4

-

3

-

2

-

1

0

ADAT 1

ADAT 0

Bit Number Bit Mnemonic

Description

Reserved

7-6

1-0

-

The value read from these bits are indeterminate. Do not set these bits.

ADC result

ADAT1:0

bits 1-0

Read only register

Reset Value: xxxx xx00b

Table 39. ADCF Register

ADCF (S:F6h)

ADC Input Select Register

7

6

5

4

3

2

1

0

SEL7

SEL6

SEL5

SEL4

SEL3

SEL2

SEL1

SEL0

Bit Number Bit Mnemonic

Description

Select Input 7-0

7-0

SEL7-0

Set to select bit 7-0 as possible input for A/D

Cleared to leave this bit free for other function

Reset Value=0000 0000b

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Rev. B - November 10, 2000

Preliminary

T80C5112

15. Interrupt System

The T80C5112 has a total of 8 interrupt vectors: two external interrupts (INT0 and INT1), two timer interrupts

(timers 0, 1), serial port interrupt, PCA, SPI and A/D. These interrupts are shown in Figure 32..

High priority

IPH, IP

interrupt

3

INT0

IE0

IE1

0

3

0

3

0

3

0

TF0

INT1

TF1

Interrupt

polling

sequence

CF

3

PCA

0

CCFx

3

RI

TI

0

3

0

NC

3

SPI

0

3

ADC

0

Global

disable

Individual

enable

Low priority

interrupt

Figure 32. Interrupt Control System

Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt

Enable register (See Table 42.). This register also contains a global disable bit, which must be cleared to disable

all interrupts at once.

Each interrupt source can also be individually programmed to one of four priority levels by setting or clearing a

bit in the Interrupt Priority register (See Table 44.) and in the Interrupt Priority High register (See Table 46.).

Table 40. shows the bit values and priority levels associated with each combination.

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65

Preliminary

T80C5112

Table 40. Priority bit level values

IP.x

IPH.x

Interrupt Level Priority

0

1

0

1

0

1

0 (Lowest)

1

2

3 (Highest)

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt.

A high-priority interrupt canÕt be interrupted by any other interrupt source.

If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level

is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence

determines which request is serviced. Thus within each priority level there is a second priority structure determined

by the polling sequence.

Table 41. Address vectors

Interrupt Address

Interrupt Name

Priority Number

Vector

external interrupt (INT0)

Timer0 (TF0)

0003h

000Bh

0013h

001Bh

0033h

0023h

004Bh

0043h

1

2

3

4

5

6

8

9

external interrupt (INT1)

Timer1 (TF1)

PCA (CF or CCFn)

UART (RI or TI)

SPI

ADC

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Rev. B - November 10, 2000

Preliminary

T80C5112

Table 42. IE Register

IE - Interrupt Enable Register (A8h)

7

6

5

4

3

2

1

0

EA

EC

-

ES

ET1

EX1

ET0

EX0

Bit

Mnemonic

Bit Number

Description

Enable All interrupt bit

Clear to disable all interrupts.

Set to enable all interrupts.

7

EA

If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its interrupt

enable bit.

PCA Interrupt Enable

Clear to disable the the PCA interrupt.

Set to enable the the PCA interrupt.

Reserved

6

5

4

EC

-

The value read from this bit is indeterminate. Do not set this bit.

Serial port Enable bit

ES

Clear to disable serial port interrupt.

Set to enable serial port interrupt.

Timer 1 overflow interrupt Enable bit

Clear to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

3

2

1

0

ET1

EX1

ET0

EX0

External interrupt 1 Enable bit

Clear to disable external interrupt 1.

Set to enable external interrupt 1.

Timer 0 overflow interrupt Enable bit

Clear to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

External interrupt 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

Reset Value = 00X0 0000b

Bit addressable

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67

Preliminary

T80C5112

Table 43. IE1 Register

IE1 (S:C0h)

Interrupt Enable Register

7

-

6

-

5

-

4

-

3

-

2

1

0

-

ESPI

EADC

Bit

Mnemonic

Bit Number

Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

SPI Interrupt Enable bit

7

6

5

4

3

-

2

ESPI

Clear to disable the SPI interrupt.

Set to enable the SPI interrupt.

A/D Interrupt Enable bit

Clear to disable the ADC interrupt.

Set to enable the ADC interrupt.

1

0

EADC

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reset Value = XXXX X00Xb

No Bit addressable

68

Rev. B - November 10, 2000

Preliminary

T80C5112

Table 44. IPL0 Register

IPL0 - Interrupt Priority Register (B8h)

7

6

5

4

3

2

1

0

-

PPC

-

PS

PT1

PX1

PT0

PX0

Bit

Mnemonic

Bit Number

Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

PCA Counter Interrupt Priority bit

PPCL

-

Refer to PPCH for priority level

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Serial port Priority bit

PSL

Refer to PSH for priority level.

Timer 1 overflow interrupt Priority bit

PT1L

PX1L

PT0L

PX0L

Refer to PT1H for priority level.

External interrupt 1 Priority bit

Refer to PX1H for priority level.

Timer 0 overflow interrupt Priority bit

Refer to PT0H for priority level.

External interrupt 0 Priority bit

Refer to PX0H for priority level.

Reset Value = X0X0 0000b

Bit addressable.

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69

Preliminary

T80C5112

Table 45. IPL1 Register

IPL1 - Interrupt Priority Low Register 1 (S:B2h)

7

6

5

4

3

2

1

0

-

PSPI

PADC

-

Bit

Mnemonic

Bit Number

Description

7

6

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

5

4

3

2

1

0

-

PSPI

PADC

-

The value read from this bit is indeterminate. Do not set this bit.

SPI Interrupt Priority level less significant bit.

Refer to PSPIH for priority level.

ADC Interrupt Priority level less significant bit.

Refer to PADCH for priority level.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reset Value = XXXX X00Xb

Not Bit addressable.

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Preliminary

T80C5112

Table 46. IPH0 Register

IPH0 - Interrupt Priority High Register (B7h)

7

6

5

4

3

2

1

0

-

PPCH

-

PSH

PT1H

PX1H

PT0H

PX0H

Bit

Mnemonic

Bit Number

Description

Reserved

7

-

The value read from this bit is indeterminate. Do not set this bit.

PCA Counter Interrupt Priority level most significant bit

PPCH PPC

Priority level

Lowest

0

1

0

1

0

1

6

5

4

PPCH

Highest priority

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Serial port Priority High bit

PSH PS Priority Level

0

Lowest

PSH

0

1

0

1

Highest

Timer 1 overflow interrupt Priority High bit

PT1H PT1

Priority Level

Lowest

0

1

0

1

0

1

3

2

1

0

PT1H

PX1H

PT0H

PX0H

Highest

External interrupt 1 Priority High bit

PX1H PX1

Priority Level

Lowest

0

1

0

1

0

1

Highest

Timer 0 overflow interrupt Priority High bit

PT0H PT0

Priority Level

0

1

0

Lowest

1

0

1

Highest

External interrupt 0 Priority High bit

PX0H PX0

Priority Level

Lowest

0

1

0

1

0

1

Highest

Reset Value = X0X0 0000b

Not bit addressable

Rev. B - November 10, 2000

71

Preliminary

T80C5112

Table 47. IPH1 Register

IPH1 - Interrupt Priority High Register 1 (B3h)

7

6

5

4

3

2

1

0

-

PSPIH

PADCH

-

Bit

Mnemonic

Bit Number

Description

7

6

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

5

4

3

The value read from this bit is indeterminate. Do not set this bit.

SPI Interrupt Priority level most significant bit

PSPIH

PSPI Priority level

0

1

0Lowest

1

0

2

PSPIH

1Highest

ADC Interrupt Priority level most significant bit

PADCH

PADC

0Lowest

Priority level

0

1

0

PADCH

1

0

1Highest

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reset Value = XXXX X00Xb

Not bit addressable

72

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Preliminary

T80C5112

16. ROM

16.1. ROM Structure

The T80C5112 ROM memory is divided in three different arrays:

·

the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8Kbytes.

the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes.

the signature array:. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes.

16.2. ROM Lock System

The program Lock system, when programmed, protects the on-chip program against software piracy.

16.2.1. Encryption Array

Within the ROM array are 64 bytes of encryption array. Every time a byte is addressed during program verify, 6

address lines are used to select a byte of the encryption array. This byte is then exclusive-NORÕed (XNOR) with

the code byte, creating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed

state, will return the code in its original, unmodified form.

When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying

the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a

verification routine will display the content of the encryption array. For this reason all the unused code bytes

should be programmed with random values.

16.2.2. Program Lock Bits

The lock bits when programmed according to Table 41. will provide different level of protection for the on-chip

code and data.

Table 48. Program Lock bits

Program Lock Bits

Protection description

Securi-

LB1

LB2

ty level

No program lock features enabled. Code verify will still be encrypted by the encryption

array if programmed. MOVC instruction executed from external program memory returns

non encrypted data.

1

U

P

U

P

MOVC instruction executed from external program memory are disabled from fetching

code bytes from internal memory, EA is sampled and latched on reset.

2

3

Same as 2, also verify is disabled

This security level is available because ROM integrity will be veriÞed thanks to another

method.

U

U: unprogrammed

P: programmed

16.2.3. Signature bytes

The T80C5112 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described

in Section ÒSignature bytesÓ, page 75.

16.2.4. Verify Algorithm

Refer to Section ÒVerify algorithmÓ, page 76.

Rev. B - November 10, 2000

73

Preliminary

T80C5112

17. EPROM

17.1. EPROM Structure

The T80C5112 EPROM is divided into two different arrays:

·

the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Kbytes.

the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes.

In addition a third non programmable array is implemented:

the signature array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes.

·

17.2. EPROM Lock System

The program Lock system, when programmed, protects the on-chip program against software piracy.

17.2.1. Encryption Array

Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FFÕs). Every time

a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This

byte is then exclusive-NORÕed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with

the encryption array in the unprogrammed state, will return the code in its original, unmodified form.

When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying

the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a

verification routine will display the content of the encryption array. For this reason all the unused code bytes

should be programmed with random values.

17.2.2. Program Lock Bits

The three lock bits, when programmed according to Table 49., will provide different level of protection for the

on-chip code and data.

Table 49. Program Lock bits

Program Lock Bits

Protection description

Security

LB1

LB2

LB3

level

No program lock features enabled. Code verify will still be encrypted by the encryption

array if programmed. MOVC instruction executed from external program memory

returns non encrypted data.

1

U

MOVC instruction executed from external program memory are disabled from fetching

code bytes from internal memory, EA is sampled and latched on reset , and further

programming of the EPROM is disabled..

2

P

U

Same as 2, also verify is disabled

3

4

U

P

U

P

This security level is available because ROM integrity will be veriÞed thanks to another

method..

U

Same as 3, also external execution is disabled.

U: unprogrammed,

P: programmed

WARNING: Security level 2 and higher should only be programmed after EPROM verification.

74

Rev. B - November 10, 2000

Preliminary

T80C5112

17.2.3. Signature bytes

The T80C5112 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described

in Section 17.5.1.

17.3. EPROM Programming

17.3.1. Set-up modes

In order to program and verify the EPROM or to read the signature bytes, the T80C5112 is placed in specific set-

up modes (See Figure 33.).

Control and program signals must be held at the levels indicated in Table 50.

17.3.2. Definition of terms

Address Lines:

P1.0-P1.7, P2.0-P2.5, P3.4, P3.5 respectively for A0-A15 (P2.5 (A13) for RB, P3.4 (A14) for

RC, P3.5 (A15) for RD)

Data Lines:

P0.0-P0.7 for D0-D7

Control Signals: RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7.

Program Signals: ALE/PROG, RST/VPP.

Table 50. EPROM Set-Up Modes

ALE/

PROG

RST/

VPP

Mode

RST

PSEN

P2.6

P2.7

P3.3

P3.6

P3.7

Program Code data

1

0

12.75V

0

1

Verify Code data

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Program Encryption Array

Address 0-3Fh

12.75V

1

Read Signature Bytes

Program Lock bit 1

Program Lock bit 2

Program Lock bit 3

1

12.75V

1

0

Rev. B - November 10, 2000

75

Preliminary

T80C5112

+5V

RST/VPP

VCC

PROGRAM

SIGNALS*

ALE/PROG

P0.0-P0.7

D0-D7

EA

+5V

RST

PSEN

P2.6

P2.7

P3.3

P3.6

P3.7

P1.0-P1.7

A0-A7

CONTROL

SIGNALS*

A8-A15

P2.0-P2.5

P3.4-P3.5

4 to 6 MHz

XTAL1

VSS

GND

* See Table 49. for proper value on these inputs

Figure 33. Set-Up Modes Configuration

17.3.3. Programming Algorithm

The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses

applied during byte programming from 25 to 1.

To program the T80C5112 the following sequence must be exercised:

·

Step 1: Activate the combination of control signals.

Step 2: Input the valid address on the address lines.

Step 3: Input the appropriate data on the data lines.

Step 4: Raise RST/VPP from VCC to VPP (typical 12.75V).

Step 5: Pulse ALE/PROG once.

Step 6: Lower RST/VPP from VPP to VCC

Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is

reached (See Figure 34).

17.3.4. Verify algorithm

Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify

of the programmed array will ensure reliable programming of the T80C5112.

P 2.7 is used to enable data output.

To verify the T80C5112 code the following sequence must be exercised:

·

Step 1: Activate the combination of program and control signals.

Step 2: Input the valid address on the address lines.

Step 3: Read data on the data lines.

Repeat step 2 through 3 changing the address for the entire array verification (See Figure 34).

The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the

code array is well encrypted.

76

Rev. B - November 10, 2000

Preliminary

T80C5112

Programming Cycle

Read/Verify Cycle

Data Out

A0-A12

D0-D7

Data In

100ms

ALE/PROG

RST/VPP

12.75V

5V

0V

Control

signals

Figure 34. Programming and Verification Signal’s Waveform

17.4. EPROM Erasure (Windowed Packages Only)

Erasing the EPROM erases the code array, the encryption array and the lock bits returning the parts to full

functionality.

Erasure leaves all the EPROM cells in a 1Õs state (FF).

17.4.1. Erasure Characteristics

The recommended erasure procedure is exposure to ultraviolet light (at 2537 ) to an integrated dose at least 15

2

W-sec/cm . Exposing the EPROM to an ultraviolet lamp of 12,000 mW/cm rating for 30 minutes, at a distance

of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers.

Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately

4,000 . Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources

over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause

inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque

label be placed over the window.

17.5. Signature Bytes

17.5.1. Signature bytes content

The T80C5112 has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes follow the procedure

for EPROM verify but activate the control lines provided in xxxx for Read Signature Bytes. Table 51. shows the

content of the signature byte for the T80C5112.

Table 51. Signature Bytes Content

Location

30h

Contents

58h

Comment

Manufacturer Code: Atmel Wireless & Microcontrollers

Family Code: C51 X2

31h

57h

60h

2Dh

Product name: T80C5112 8K ROM version

Product name: T80C5112 8K OTP version

Product revision number : T80C5112 Rev.0

60h

ADh

EFh

61h

Rev. B - November 10, 2000

77

Preliminary

T80C5112

18. Electrical Characteristics

(1)

18.1. Absolute Maximum Ratings

Ambiant Temperature Under Bias:

C = commercial 0°C to 70°C

I = industrial -40°C to 85°C

Storage Temperature -65°C to + 150°C

Voltage on V to V -0.5 V to + 7 V

CC

SS

Voltage on V to V -0.5 V to + 13 V

PP

SS

Voltage on Any Pin to V -0.5 V to V + 0.5 V

SS

CC

(2)

Power Dissipation1 W

NOTES

1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not

implied. Exposure to absolute maximum rating conditions may affect device reliability.

2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.

18.2. Power consumption measurement

Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset,

which made sense for the designs were the CPU was running under reset. In our new devices, the CPU is no more

active during reset, so the power consumption is very low but is not really representative of what will happen in

the customer system. ThatÕs why, while keeping measurements under Reset, we present a new way to measure the

operating Icc:

Using an internal test ROM, the following code is executed:

Label: SJMP Label (80 FE)

Ports 1, 3, 4 are disconnected, RST = Vcc, XTAL2 is not connected and XTAL1 is driven by the clock.

This is much more representative of the real operating Icc.

78

Rev. B - November 10, 2000

Preliminary

T80C5112

18.3. DC Parameters for Standard Voltage

TA = 0°C to +70°C; V = 0 V; V = 5 V ± 10%; F = 0 to 40 MHz.

SS

CC

TA = -40°C to +85°C; V = 0 V; V = 5 V ± 10%; F = 0 to 40 MHz.

SS

CC

Table 52. DC Parameters in Standard Voltage

Symbol

Parameter

Min

Typ

Max

Unit

V

Test Conditions

V

Input Low Voltage

-0.5

0.2 V - 0.1

CC

IL

V

Input High Voltage except XTAL1, RST

Input High Voltage, XTAL1, RST

Output Low Voltage, ports 1, 2, 3, 4.

0.2 V + 0.9

V

+ 0.5

V

IH

CC

V

0.7 V

V

IH1

CC

V

0.3

V

I

= 100 mA

= 1.6 mA

= 3.5 mA

OL

0.45

1.0

(6)

V

0.3

0.45

1.0

V

I

= 200 mA

= 3.2 mA

=7.0 mA

OL1

Output Low Voltage, port 0, ALE, PSEN

OL

(6)

V

- 0.3

- 0.7

- 1.5

V

I

= -10 mA

= -30 mA

= -60 mA

OH

Output High Voltage, ports 1, 2, 3, 4.

CC

OH

V

= 5 V ± 10%

CC

(6)

V

R

V

- 0.3

- 0.7

- 1.5

V

I

= -100 mA

= -1.6 mA

= -3.2 mA

= 5 V ± 10%

OH2

OH1

RST

Output High Voltage, ports 1, 3, 4.

mode Push pull

CC

OH

V

CC

(6)

V

- 0.3

- 0.7

- 1.5

V

I

= -200 mA

= -3.2 mA

= -7.0 mA

= 5 V ± 10%

Output High Voltage, ports 0, ALE, PSEN

CC

OH

V

CC

(5)

RST Pulldown Resistor

50

200

-50

kW

90

I

Logical 0 Input Current ports 1, 2, 3 and 4

Input Leakage Current

mA Vin = 0.45 V,

mA 0.45 V < Vin < V

mA Vin = 2.0 V

IL

LI

I

±10

-650

CC

I

Logical 1 to 0 Transition Current, ports 1, 2, 3, 4

TL

C

Capacitance of I/O Buffer

10

50

pF Fc = 1 MHz

IO

TA = 25°C

(5)

(3)

I

Power Down Current

to be conÞrmed

mA

PD

20

2.0 V < V

5.5 V

CC <

I

Power Supply Current Maximum values, X1

mode:

to be con-

Þrmed

3+ 0.4 Freq

(MHz)

@12MHz 5.8

CC

(7)

(1)

V

= 5.5 V

under

RESET

CC

mA

@16MHz 7.4

I

Power Supply Current Maximum values, X1

to be con-

Þrmed

3 + 0.6 Freq

(MHz)

@12MHz 10.2

CC

(7)

(8)

mode:

operating

V

= 5.5 V

CC

@16MHz 12.6

I

Power Supply Current Maximum values, X1

to be con-

Þrmed

3+0.3 Freq

(MHz)

CC

(7)

(2)

mode:

mA

idle

= 5.5 V

CC

@12MHz 3.9

@16MHz 5.1

V

Supply voltage during power down mode

High threshold of Power Fail Detect

Low threshold of Power Fail Detect

2

V

RET

V

2.54

RST+

V

2.19

RST

Rev. B - November 10, 2000

79

Preliminary

T80C5112

18.4. DC Parameters for Low Voltage

TA = 0°C to +70°C; V = 0 V; V = 2.7 V to 5.5 V; F = 0 to 30 MHz.

SS

CC

TA = -40°C to +85°C; V = 0 V; V = 2.7 V to 5.5 V; F = 0 to 30 MHz.

SS

CC

Table 53. DC Parameters for Low Voltage

Symbol

Parameter

Min

Typ

Max

Unit

V

Test Conditions

V

Input Low Voltage

-0.5

0.2 V - 0.1

CC

IL

V

Input High Voltage except XTAL1, RST

Input High Voltage, XTAL1, RST

Output Low Voltage, ports 1, 2, 3, 4.

0.2 V + 0.9

V

+ 0.5

V

IH

CC

V

0.7 V

V

IH1

CC

V

0.3

V

I

=

OL

0.45

1.0

= 0.8 mA

=

(6)

V

0.3

0.45

1.0

V

I

= 100 mA

= 1.6 mA

= 3.2 mA

OL1

Output Low Voltage, port 0, ALE, PSEN

OL

(6)

V

0.9 V

V

I

= -10 mA

OH

Output High Voltage, ports 1, 2, 3, 4.

CC

OH

=

V

- 0.7

- 1.5

CC

(6)

V

0.9V

V

I

= -100 mA

= - mA

=

OH2

OH1

Output High Voltage, ports 1, 3, 4.

mode Push pull

CC

OH

V

- 0.7

- 1.5

- 0.3

- 0.7

- 1.5

CC

(6)

V

I

= -100 mA

= -1.6 mA

= -3.2 mA

= 3V ± 10%

Output High Voltage, ports 0, ALE, PSEN

CC

OH

V

CC

I

Logical 0 Input Current ports 1, 2,3 and 4

Input Leakage Current

-50

±10

-650

200

10

mA Vin = 0.45 V

mA 0.45 V < Vin < V

mA Vin = 2.0 V

kW

IL

I

LI

CC

I

Logical 1 to 0 Transition Current, ports 1, 2, 3, 4

RST Pulldown Resistor

TL

RST

(5)

R

50

90

CIO

Capacitance of I/O Buffer

pF Fc = 1 MHz

TA = 25°C

(5)

(3)

I

Power Down Current

to be conÞrmed

50

30

mA

PD

20

V

= 2.0 V to 5.5 V

= 2.0 V to 3.3 V

CC

(5)

10

V

I

Power Supply Current Maximum values, X1

mode:

to be con- 1.5 + 0.2 Freq

CC

(7)

(1)

Þrmed

(MHz)

V

= 3.3 V

under

CC

@12MHz 3.4

mA

RESET

@16MHz 4.2

I

Power Supply Current Maximum values, X1

to be con- 1.5 + 0.3 Freq

CC

(7)

(8)

Þrmed

(MHz)

mode:

V

= 3.3 V

operating

@12MHz 4.6

@16MHz 5.8

mA

I

Power Supply Current Maximum values, X1

to be con- 1.5+0.15 Freq

CC

(7)

Þrmed

(MHz)

(2)

mode:

idle

V

= 3.3 V

CC

@12MHz 2

@16MHz 2.6

V

Supply voltage during power down mode

High threshold of Power Fail Detect

2

V

RET

V

2.54

RST+

V

Low threshold of Power Fail Detect

2.19

V

RST

NOTES

1.

I

under reset is measured with all output pins disconnected; XTAL1 driven with T

, T

= 5 ns (see Figure 39.), V = V + 0.5 V,

CC

CLCH CHCL IL SS

V

= V - 0.5V; XTAL2 N.C.; Vpp = RST = V . I would be slightly higher if a crystal oscillator used.

CC CC CC

IH

2. Idle I is measured with all output pins disconnected; XTAL1 driven with T

, T

= 5 ns, V = V + 0.5 V, V = V - 0.5 V; XTAL2

CC

CLCH CHCL IL SS IH CC

N.C; Vpp = RST = V (see Figure 37.).

SS

80

Rev. B - November 10, 2000

Preliminary

T80C5112

3. Power Down I is measured with all output pins disconnected; Vpp = V ; XTAL2 NC.; RST = V (see Figure 38.).

CC

SS

4. Not Applicable

5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V.

6. If I exceeds the test condition, V may exceed the related speciﬁcation. Pins are not guaranteed to sink current greater than the listed test

OL

conditions.

7. For other values, please contact your sales ofﬁce.

8. Operating I is measured with all output pins disconnected; XTAL1 driven with T

, T

= 5 ns (see Figure 39.), V = V + 0.5 V,

IL SS

CC

CLCH CHCL

V

= V - 0.5V; XTAL2 N.C.; RST/Vpp= V ;. The internal ROM runs the code 80 FE (label: SJMP label). I would be slightly higher if a crystal

CC CC CC

IH

oscillator is used. Measurements are made with OTP products when possible, which is the worst case.

V

CC

I

CC

V

CC

RST

XTAL

XTAL1

(NC)

CLOCK

SIGNAL

V

SS

All other pins are disconnected.

Figure 35. I

Test Condition, under reset

CC

V

CC

I

CC

V

CC

Reset = Vss after a high pulse

during at least 24 clock cycles

V

CC

RST

XTAL

XTAL1

(NC)

CLOCK

All other pins are disconnected.

V

SIGNAL

SS

Figure 36. Operating I

Test Condition

CC

Rev. B - November 10, 2000

81

Preliminary

T80C5112

V

CC

I

CC

Reset = Vss after a high pulse

during at least 24 clock cycles

V

CC

V

CC

RST

XTAL

(NC)

CLOCK

SIGNAL

XTAL1

All other pins are disconnected.

V

SS

Figure 37. I

Test Condition, Idle Mode

CC

V

CC

I

CC

V

CC

Reset = Vss after a high pulse

during at least 24 clock cycles

V

CC

RST

XTAL

XTAL1

V

All other pins are disconnected.

SS

Figure 38. I

Test Condition, Power-Down Mode

CC

V

-

CC

0.7V

CC

0.2V -0.1

0.45

CC

T

CLCH

CHCL

T

= T

=

CLCH

CHCL

Figure 39. Clock Signal Waveform for I

Tests in Active and Idle Modes

CC

18.5. DC Parameters for A/D Converter

TA = 0°C to +70°C; V = 0 V; V = 2.7 V to 5.5 V; F = 0 to 30 MHz.

SS

CC

TA = -40°C to +85°C; V = 0 V; V = 2.7 V to 5.5 V; F = 0 to 30 MHz.

SS

CC

Table 54. DC Parameters for Low Voltage

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

Resolution

10

bit

82

Rev. B - November 10, 2000

Preliminary

T80C5112

Symbol

AVin

Parameter

Min

Vss- 0.2

13

Typ

Max

Vcc + 0.2

24

Unit

Test Conditions

Analog input voltage

V

Rref

Resistance between Vref and Vss

Value of integrated voltage source

18

KOhm

V

Vref

2.43

2.49

Small variation with Vcc

and Temperature (1)

Lref

Cai

Load on integrated voltage source

Analog input Capacitance

Integral non linearity

10

KOhm

60

1

pF During sampling

2

1

2

1

lsb

Differential non linearity

Offset error

0.5

-2

Input source impedance

KOhm For 10 bit resolution at

maximum speed

(1) Total drift on one part over full Voltage and Temperature range is below 20 mV

18.6. AC Parameters

18.6.1. Explanation of the AC Symbols

Each timing symbol has 5 characters. The first character is always a ÒTÓ (stands for time). The other characters,

depending on their positions, stand for the name of a signal or the logical status of that signal. The following is

a list of all the characters and what they stand for.

Example:T

= Time for Address Valid to ALE Low.

AVLL

T

= Time for ALE Low to PSEN Low.

LLPL

TA = 0 to +70°C (commercial temperature range); V = 0 V; V = 5 V ± 10%; -V ranges.

SS

CC

TA = -40°C to +85°C (industrial temperature range); V = 0 V; V = 5 V ± 10%; -V ranges.

SS

CC

TA = 0 to +70°C (commercial temperature range); V = 0 V; 2.7 V < V

5.5 V; -L range.

SS

CC <

TA = -40°C to +85°C (industrial temperature range); V = 0 V; 2.7 V < V

5.5 V; -L range.

SS

CC <

Table 55. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE and PSEN signals.

Timings will be guaranteed if these capacitances are respected. Higher capacitance values can be used, but timings

will then be degraded.

Table 55. Load Capacitance versus speed range, in pF

-V

50

30

-L

100

80

Port 0

Port 1, 2, 3

ALE / PSEN

100

Table 57., Table 60. and Table 61. give the description of each AC symbols.

Table 57., Table 59. and Table 62. give for each range the AC parameter.

Table 58., Table 60. and Table 63. give the frequency derating formula of the AC parameter. To calculate each

AC symbols, take the x value corresponding to the speed grade you need (-V or -L) and replace this value in the

formula. Values of the frequency must be limited to the corresponding speed grade:

Rev. B - November 10, 2000

83

Preliminary

T80C5112

Table 56. Max frequency for derating formula regarding the speed grade

-V X1 mode

-V X2 mode

-L X1 mode

-L X2 mode

Freq (MHz)

T (ns)

40

25

30

20

50

33.3

Example:

E6

T

in X2 mode for a -V part at 20 MHz (T = 1/20 = 50 ns):

LLIV

x= 25 (Table 58.)

T= 50ns

T

= 2T - x = 2 x 50 - 25 = 75ns

LLIV

84

Rev. B - November 10, 2000

Preliminary

T80C5112

18.6.2. External Program Memory Characteristics

Symbol

Parameter

T

Oscillator clock period

ALE pulse width

T

LHLL

T

Address Valid to ALE

AVLL

T

Address Hold After ALE

ALE to Valid Instruction In

ALE to PSEN

LLAX

T

LLIV

LLPL

PLPH

T

PSEN Pulse Width

T

PSEN to Valid Instruction In

Input Instruction Hold After PSEN

Input Instruction FloatAfter PSEN

PSEN to Address Valid

PLIV

PXIX

T

PXIZ

T

PXAV

T

Address to Valid Instruction In

PSEN Low to Address Float

AVIV

T

PLAZ

Table 57. AC Parameters for Fix Clock

Speed

-V

-L

X2 mode

30 MHz

standard mode

40 MHz

X2 mode

20 MHz

standard mode

30 MHz

Units

60 MHz equiv.

40 MHz equiv.

Symbol

Min

33

Max

Min

25

Max

Min

50

Max

Min

33

Max

T

ns

T

25

42

35

52

LHLL

T

4

12

5

13

ns

AVLL

T

LLAX

T

45

25

78

50

65

30

98

55

LLIV

LLPL

PLPH

T

9

17

60

10

50

18

75

35

T

PLIV

PXIX

T

0

T

12

53

10

20

95

10

80

10

18

122

10

PXIZ

T

AVIV

PLAZ

T

Rev. B - November 10, 2000

85

Preliminary

T80C5112

Table 58. AC Parameters for a Variable Clock: derating formula

Symbol

Type

Standard X2 Clock

Clock

-V

-L

Units

T

Min

Max

Min

Max

Min

Max

2 T - x

T - x

4 T - x

T - x

3 T - x

x

T - x

0.5 T - x

2 T - x

0.5 T - x

1.5 T - x

x

8

15

20

35

15

25

45

0

ns

LHLL

T

13

22

8

AVLL

T

LLAX

T

LLIV

LLPL

PLPH

T

15

25

0

T

PLIV

PXIX

T

T - x

5 T - x

x

0.5 T - x

2.5 T - x

x

5

15

45

10

PXIZ

T

30

10

AVIV

PLAZ

T

18.6.3. External Program Memory Read Cycle

12 T

CLCL

T

LLIV

LHLL

ALE

PSEN

T

LLPL

T

PLPH

T

PXAV

T

LLAX

T

PXIZ

PLIV

AVLL

T

TPLAZ

PXIX

PORT 0

PORT 2

INSTR IN

A0-A7

INSTR IN

A0-A7

INSTR IN

T

AVIV

ADDRESS

OR SFR-P2

ADDRESS A8-A15

Figure 40. External Program Memory Read Cycle

86

Rev. B - November 10, 2000

Preliminary

T80C5112

18.6.4. External Data Memory Characteristics

Symbol

Parameter

T

RD Pulse Width

RLRH

T

WR Pulse Width

WLWH

T

RD to Valid Data In

RLDV

RHDX

Data Hold After RD

Data Float After RD

ALE to Valid Data In

Address to Valid Data In

ALE to WR or RD

T

RHDZ

T

LLDV

T

AVDV

T

LLWL

T

Address to WR or RD

Data Valid to WR Transition

Data set-up to WR High

Data Hold After WR

RD Low to Address Float

RD or WR High to ALE high

AVWL

QVWX

QVWH

WHQX

T

RLAZ

T

WHLH

Rev. B - November 10, 2000

87

Preliminary

T80C5112

Table 59. AC Parameters for a Fix Clock

Speed

-V

-L

X2 mode

30 MHz

standard mode

40 MHz

X2 mode

20 MHz

standard mode

30 MHz

Units

60 MHz equiv.

40 MHz equiv.

Symbol

Min

85

Max

Min

135

Max

Min

125

Max

Min

175

Max

T

ns

RLRH

T

85

135

125

175

WLWH

T

60

102

95

137

RLDV

RHDX

T

0

T

18

98

35

165

175

95

25

42

RHDZ

T

155

160

105

222

235

130

LLDV

T

100

70

AVDV

T

30

47

7

55

80

45

70

5

70

103

13

LLWL

T

AVWL

QVWX

QVWH

WHQX

T

15

107

9

165

17

155

10

213

18

T

0

RLAZ

T

7

27

15

35

5

45

13

53

WHLH

88

Rev. B - November 10, 2000

Preliminary

T80C5112

Table 60. AC Parameters for a Variable Clock: derating formula

Symbol

Type

Standard X2 Clock

Clock

-V

-L

Units

T

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

6 T - x

5 T - x

x

3 T - x

2.5 T - x

x

15

23

0

25

30

0

ns

RLRH

T

WLWH

T

RLDV

RHDX

T

2 T - x

8 T - x

9 T - x

3 T - x

3 T + x

4 T - x

T - x

15

35

50

20

10

8

25

45

65

30

20

15

0

RHDZ

T

4T -x

LLDV

T

4.5 T - x

1.5 T - x

1.5 T + x

2 T - x

0.5 T - x

3.5 T - x

0.5 T - x

x

AVDV

T

LLWL

T

AVWL

QVWX

QVWH

WHQX

T

7 T - x

T - x

T

x

0

RLAZ

WHLH

T

T - x

0.5 T - x

0.5 T + x

10

20

T + x

18.6.5. External Data Memory Write Cycle

T

WHLH

ALE

PSEN

WR

T

LLWL

WLWH

T

QVWX

T

QVWH

WHQX

LLAX

PORT 0

PORT 2

A0-A7

DATA OUT

T

AVWL

ADDRESS

OR SFR-P2

ADDRESS A8-A15 OR SFR P2

Figure 41. External Data Memory Write Cycle

Rev. B - November 10, 2000

89

Preliminary

T80C5112

18.6.6. External Data Memory Read Cycle

T

WHLH

T

ALE

LLDV

PSEN

T

RLRH

LLWL

T

RLDV

RD

T

RHDZ

T

AVDV

T

LLAX

RHDX

PORT 0

PORT 2

A0-A7

DATA IN

T

RLAZ

T

AVWL

ADDRESS

OR SFR-P2

ADDRESS A8-A15 OR SFR P2

Figure 42. External Data Memory Read Cycle

18.6.7. Serial Port Timing - Shift Register Mode

Table 61. Symbol Description

Symbol

Parameter

T

Serial port clock cycle time

XLXL

QVHX

XHQX

Output data set-up to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

T_XHDX

T

Clock rising edge to input data valid

XHDV

Table 62. AC Parameters for a Fix Clock

Speed

-V

-L

Units

X2 mode

30 MHz

standard mode

40 MHz

X2 mode

20 MHz

standard mode

30 MHz

60 MHz equiv.

40 MHz equiv.

Symbol

Min

200

117

13

Max

Min

300

200

30

Max

Min

300

200

30

Max

Min

400

283

47

Max

T

ns

XLXL

QVHX

XHQX

XHDX

XHDV

T

0

34

117

200

90

Rev. B - November 10, 2000

Preliminary

T80C5112

Table 63. AC Parameters for a Variable Clock: derating formula

Symbol

Type

Standard X2 Clock

Clock

-V

-L

Units

T

Min

Max

12 T

10 T - x

2 T - x

x

6 T

5 T - x

T - x

x

ns

XLXL

QVHX

XHQX

XHDX

XHDV

T

50

20

0

50

20

0

10 T - x

5 T- x

133

18.6.8. Shift Register Timing Waveforms

0

1

2

3

4

5

6

7

8

INSTRUCTION

ALE

T

XLXL

CLOCK

T

XHQX

T

QVXH

0

1

2

3

4

5

6

7

OUTPUT DATA

T

SET TI

XHDX

T

XHDV

WRITE to SBUF

INPUT DATA

VALID

SET RI

CLEAR RI

Figure 43. Shift Register Timing Waveforms

Rev. B - November 10, 2000

91

Preliminary

T80C5112

18.6.9. EPROM Programming and Verification Characteristics

TA = 21°C to 27°C; V = 0V; V = 5V ± 10% while programming. V = operating range while verifying

SS

CC

Symbol

Parameter

Min

Max

13

Units

V

Programming Supply Voltage

Programming Supply Current

Oscillator Frquency

12.5

PP

I

75

mA

PP

1/T

4

6

MHz

CLCL

T

Address Setup to PROG Low

Adress Hold after PROG

Data Setup to PROG Low

Data Hold after PROG

48 T

CLCL

AVGL

GHAX

T

48 T_CLCL

T

DVGL

GHDX

T

(Enable) High to V

48 T

CLCL

EHSH

SHGL

PP

T

V_PPSetup to PROG Low

V_PPHold after PROG

PROG Width

10

ms

10

90

GHSL

110

GLGH

T

Address to Valid Data

ENABLE Low to Data Valid

Data Float after ENABLE

48 T_CLCL

AVQV

T

ELQV

EHQZ

T

0

18.6.10. EPROM Programming and Verification Waveforms

PROGRAMMING

VERIFICATION

ADDRESS

P1.0-P1.7

ADDRESS

P2.0-P2.5

P3.4-P3.5*

T

AVQV

DATA OUT

P0

DATA IN

T

GHDX

DVGL

AVGL

T

GHAX

ALE/PROG

T

SHGL

GHSL

T

GLGH

V

EA/V

PP

V

CC

T

EHSH

EHQZ

ELQV

CONTROL

SIGNALS

(ENABLE)

* 8KB: up to P2.4, 16KB: up to P2.5, 32KB: up to P3.4, 64KB: up to P3.5

Figure 44. EPROM Programming and Verification Waveforms

92

Rev. B - November 10, 2000

Preliminary

T80C5112

18.6.11. External Clock Drive Characteristics (XTAL1)

Symbol

Parameter

Min

25

5

Max

Units

ns

T

Oscillator Period

High Time

Low Time

CLCL

T

ns

CHCX

T

5

ns

CLCX

CLCH

CHCL

Rise Time

5

ns

Fall Time

ns

T

/T

Cyclic ratio in X2 mode

40

60

%

CHCX CLCX

18.6.12. External Clock Drive Waveforms

V

-0.5 V

CC

0.7V

CC

0.2V -0.1 V

0.45 V

CC

T

CHCX

T

CHCL

CLCH

CLCX

T

CLCL

Figure 45. External Clock Drive Waveforms

18.6.13. A/D comverter

Symbol

Parameter

Min

Typ

Max

Units

Conversion time

11

Clock periods (1 for sam-

pling, 10 for conversion)

Fconv_ck

Clock Conversion frequency

Sampling frequency

350 (1)

32

kHz

8

Notes: (1)For 10 bits resolution

18.6.14. AC Testing Input/Output Waveforms

V

-0.5 V

CC

0.2V +0.9

CC

INPUT/OUTPUT

0.2V -0.1

CC

0.45 V

Figure 46. AC Testing Input/Output Waveforms

AC inputs during testing are driven at V - 0.5 for a logic Ò1Ó and 0.45V for a logic Ò0Ó. Timing measurement

CC

are made at V min for a logic Ò1Ó and V max for a logic Ò0Ó.

IH

IL

Rev. B - November 10, 2000

93

Preliminary

T80C5112

18.6.15. Float Waveforms

FLOAT

V

-0.1 V

+0.1 V

OH

V

+0.1 V

-0.1 V

LOAD

V

OL

Figure 47. Float Waveforms

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage occurs and begins

to float when a 100 mV change from the loaded V /V level occurs. I /I

³± 20mA.

OH OL

OL OH

94

Rev. B - November 10, 2000

Preliminary

T80C5112

18.6.16. Clock Waveforms

Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two.

STATE1

P1 P2

STATE2

STATE3

STATE4

P1 P2 P1

STATE4

P1 P2

STATE5

P1 P2

STATE6

P1 P2

STATE5

INTERNAL

CLOCK

P1

P2 P1 P2

P2

XTAL2

ALE

THESE SIGNALS ARE NOT ACTIVATED DURING THE

EXECUTION OF A MOVX INSTRUCTION

EXTERNAL PROGRAM MEMORY FETCH

PSEN

PCL OUT

DATA

P0

DATA

SAMPLED

DATA

SAMPLED

FLOAT

INDICATES ADDRESS TRANSITIONS

P2 (EXT)

READ CYCLE

RD

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

P0

P2

DPL OR Rt OUT

FLOAT

INDICATES DPH OR P2 SFR TO PCH TRANSITION

WRITE CYCLE

WR

PCL OUT (EVEN IF PROGRAM

MEMORY IS INTERNAL)

P0

DPL OR Rt OUT

DATA OUT

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

INDICATES DPH OR P2 SFR TO PCH TRANSITION

P2

PORT OPERATION

OLD DATA

P0 PINS SAMPLED

NEW DATA

P0 PINS SAMPLED

MOV DEST P0

P1, P2, P3 PINS SAMPLED

RXD SAMPLED

P1, P2, P3 PINS SAMPLED

MOV DEST PORT (P1, P2, P3)

(INCLUDES INT0, INT1, TO, T1)

RXD SAMPLED

SERIAL PORT SHIFT CLOCK

TXD (MODE 0)

Figure 48. Clock Waveforms

This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,

however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin

loading. Propagation also varies from output to output and component. Typically though (T =25°C fully loaded)

A

RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays

are incorporated in the AC specifications.

Rev. B - November 10, 2000

95

Preliminary

T80C5112

19. Ordering Information

-RK

T

87C5112

R

C

V

Packages:

RK: LQFP48

S3: PLCC52

Conditioning

S: Stick

R:Tape & Reel

U: Stick and Dry Pack

F:Tape & Reel and

Dry Pack

V:VCC: 5V +/- 10%

L:VCC: 2.7 to 5.5 V

Part Number

Temperature Range

C:Commercial 0 to 70^oC

I:Industrial -40 to 85^oC

E: Engineering samples

83C5112 zzz (8k ROM, zzz is the customer code)

87C5112 zzz (8k OTP, is the customer code if factory programmed)

80C5112 (ROMless part)

Table 64. Maximum Clock Frequency

-V

-L

Unit

Code

Standard Mode, oscillator frequency

Standard Mode, internal frequency

40

MHz

X2 Mode, oscillator frequency

X2 Mode, internal equivalent frequency

33

66

20

40

MHz

Notes: -L parts supplied vith 5V +-10% have same speed as -V parts

96

Rev. B - November 10, 2000

Preliminary

T80C5112

Table 65. Possible order entries

Exten-

sion

Type

T83C5112

Mask ROM

T87C5112

OTP

T80C5112

ROMless

-S3SCL PLCC52, Stick, Comm. 2.7-5.5V, 40 MHz

-S3SCV PLCC52, Stick, Comm. 5V, 66MHz

-S3SIL

PLCC52, Stick, Ind. 2.7-5.5V, 40 MHz

X

-S3RCL PLCC52, Tape & Reel, Comm. 2.7-5.5V, 40 MHz

-S3RCV PLCC52, Tape & Reel, Comm. 5V, 66MHz

-S3RIL PLCC52, Tape & Reel, Ind. 2.7-5.5V, 40 MHz

-RKUCL LQFP48, Stick & Dry Pack, Comm. 2.7-5.5V, 40 MHz

-RKUCV LQFP48, Stick & Dry Pack, Comm. 5V, 66MHz

-RKUIL LQFP48, Stick & Dry Pack, Ind. 2.7-5.5V, 40 MHz

-RKFCL LQFP48, Tape & Reel & Dry Pack, Comm. 2.7-5.5V, 40 MHz

-RKFCV LQFP48, Tape & Reel & Dry Pack, Comm. 5V, 66MHz

-RKFIL LQFP48, Tape & Reel & Dry Pack, Ind. 2.7-5.5V, 40 MHz

-RKSEL Engineering sample, LQFP48, Stick, 2.7-5.5V, 40MHz

-TDSEL Engineering sample, PLCC52, Stick, 2.7-5.5V, 40MHz

X

Rev. B - November 10, 2000

97

Preliminary


型号：	T87C5112-S3SIV
厂家：	ATMEL
描述：	8-bit Microcontroller with A/D converter 8位微控制器与A / D转换器转换器微控制器
文件：	总97页 (文件大小：764K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

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