T89C5115-TISIM_技术文档

Features

• 80C51 Core Architecture

• 256 Bytes of On-chip RAM

• 256 Bytes of On-chip ERAM

– 16-KB of On-chip Flash Memory

– Data Retention: 10 Years at 85°C

– Read/Write Cycle: 10K

• 2K Bytes of On-chip Flash for Bootloader

• 2K Bytes of On-chip EEPROM

– Read/Write Cycle: 100k

• 14-sources 4-level Interrupts

• Three 16-bit Timers/Counters

• Full Duplex UART Compatible 80C51

• Maximum Crystal Frequency 40 MHz

– In X2 Mode, 20 MHz (CPU core, 40 MHz)

• Three or Four Ports: 16 or 20 Digital I/O Lines

• Two-channel 16-bit PCA with:

– PWM (8-bit)

Low Pin Count

8-bit MCU with

A/D Converter

and 16-Kbytes of

Flash Memory

– High-speed Output

– Timer and Edge Capture

• Double Data Pointer

• 21-bit WatchDog Timer (7 Programmable Bits)

• A 10-bit Resolution Analog to Digital Converter (ADC) with 8 Multiplexed Inputs

• Power Saving Modes:

T89C5115

– Idle Mode

– Power-down Mode

• Power Supply: 5V ± 10% (or 3V⁽¹⁾± 10%)

• Temperature Range: Industrial (-40° to +85°C)

• Packages: SOIC28, PLCC28, VQFP32

Note:

1. Ask for availability

Description

The T89C5115 is a high performance Flash version of the 80C51 single chip 8-bit

microcontrollers. It contains a 16-KB Flash memory block for program and data.

The 16-KB Flash memory can be programmed either in parallel mode or in serial

mode with the ISP capability or with software. The programming voltage is internally

generated from the standard VCC pin.

The T89C5115 retains all features of the 80C52 with 256 bytes of internal RAM, a 7-

source 4-level interrupt controller and three timer/counters. In addition, the T89C5115

has a 10-bit A/D converter, a 2-KB Boot Flash memory, 2-KB EEPROM for data, a

Programmable Counter Array, an ERAM of 256 bytes, a Hardware WatchDog Timer

and a more versatile serial channel that facilitates multiprocessor communication

(EUART). The fully static design of the T89C5115 reduces system power consumption

by bringing the clock frequency down to any value, even DC, without loss of data.

The T89C5115 has two software-selectable modes of reduced activity and an 8 bit

clock prescaler for further reduction in power consumption. In the idle mode the CPU

is frozen while the peripherals and the interrupt system are still operating. In the

power-down mode the RAM is saved and all other functions are inoperative.

The added features of the T89C5115 make it more powerful for applications that need

A/D conversion, pulse width modulation, high speed I/O and counting capabilities

such as industrial control, consumer goods, alarms, motor control, etc. While remain-

ing fully compatible with the 80C52 it offers a superset of this standard microcontroller.

Rev. 4128A–8051–04/02

1

In X2 mode a maximum external clock rate of 20 MHz reaches a 300 ns cycle time.

Block Diagram

EEPROM

2kx8

RAM

256x8

Flash Boot

16kx8 loader

2kx8

ERAM

256x8

PCA

UART

Timer2

XTAL1

XTAL2

C51

CORE

IB-bus

CPU

Timer 0

Timer 1

Parallel I/O Ports & Ext. Bus

INT

Ctrl

Watch

Dog

10-bit

ADC

Port 1

Port 3

Port 4

Port 2

Notes: 1. 8 analog Inputs/8 Digital I/O

2. 2-Bit I/O Port

2

T89C5115

4128A–8051–04/02

T89C5115

Pin Configuration

VAREF

28

27

26

1

2

3

4

5

P1.0/AN0/T2

P1.1/AN1/T2EX

VAGND

VAVCC

P4.1

P1.2/AN2/ECI

25 P1.3/AN3/CEX0

P1.4/AN4/CEX1

24

23

22

21

20

19

18

17

P4.0

P1.5/AN5

6

7

8

P2.1

P1.6/AN6

P1.7/AN7

P2.0

P3.7

P3.6

P3.5/T1

P3.4/T0 10

P3.3/INT1

P3.2/INT0

SO28

9

RESE

T

VSS

VCC

11

12

13

14

XTAL1

XTAL2

P3.1/TxD

P3.0/RxD

16

15

P1.3/AN3/CEX0

25

24

23

22

21

20

19

P4.0

P2.1

5

6

7

8

9

P1.4/AN4/CEX1

P1.5/AN5

P1.6/AN6

P1.7/AN7

P2.0

P3.7

P3.6

P3.5/T1

P3.4/T0

P3.3/INT1

PLCC-28

10

11

RESET

P1.3/AN3/CEX0

P1.4/AN4/CEX1

P1.5/AN5/CEX2

P1.6/AN6/CEX3

P1.7/AN7/CEX4

P2.0

P4.0

P2.1

1

24

23

2

P3.7

P3.6

P3.5/T1

P3.4/T0

22

21

20

19

18

3

4

QFP-32

5

6

7

8

NC

RESET

P3.3/INT1

17

3

4128A–8051–04/02

Table 1. Pin Description

Pin Name

Type Description

VSS

GND Circuit ground

VCC

Supply Voltage

VAREF

VAVCC

VAGND

P1.0:7

Reference Voltage for ADC

Supply Voltage for ADC

Reference Ground for ADC

I/O

Port 1:

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 1 pins can be used for

digital input/output or as analog inputs for the Analog Digital Converter (ADC). Port 1

pins that have 1’s written to them are pulled high by the internal pull-up transistors

and can be used as inputs in this state. As inputs, Port 1 pins that are being pulled

low externally will be the source of current (I_IL, see section "Electrical Characteristic")

because of the internal pull-ups. Port 1 pins are assigned to be used as analog

inputs via the ADCCF register (in this case the internal pull-ups are disconnected).

As a secondary digital function, port 1 contains the Timer 2 external trigger and clock

input; the PCA external clock input and the PCA module I/O.

P1.0/AN0/T2

Analog input channel 0,

External clock input for Timer/counter2.

P1.1/AN1/T2EX

Analog input channel 1,

Trigger input for Timer/counter2.

P1.2/AN2/ECI

Analog input channel 2,

PCA external clock input.

P1.3/AN3/CEX0

Analog input channel 3,

PCA module 0 Entry of input/PWM output.

P1.4/AN4/CEX1

Analog input channel 4,

PCA module 1 Entry of input/PWM output.

P1.5/AN5

Analog input channel 5,

P1.6/AN6

Analog input channel 6,

P1.7/AN7

Analog input channel 7,

It can drive CMOS inputs without external pull-ups.

Port 2:

Is an 2-bit bi-directional I/O port with internal pull-ups. Port 2 pins that have 1’s

written to them are pulled high by the internal pull-ups and can be used as inputs in

this state. As inputs, Port 2 pins that are being pulled low externally will be a source

of current (IIL, on the datasheet) because of the internal pull-ups.

In the T89C51CC02 Port 2 can sink or source 5 mA. It can drive CMOS inputs

without external pull-ups.

P2.0:7

I/O

4

T89C5115

4128A–8051–04/02

T89C5115

Table 1. Pin Description (Continued)

Pin Name

Type Description

P3.0:7

I/O

Port 3:

Is an 8-bit bi-directional I/O port with internal pull-ups. Port 3 pins that have 1’s

written to them are pulled high by the internal pull-up transistors and can be used as

inputs in this state. As inputs, Port 3 pins that are being pulled low externally will be a

source of current (I_IL, see section "Electrical Characteristic") because of the internal

pull-ups.

The output latch corresponding to a secondary function must be programmed to one

for that function to operate (except for TxD ). The secondary functions are assigned

to the pins of port 3 as follows:

P3.0/RxD:

Receiver data input (asynchronous) or data input/output (synchronous) of the serial

interface

P3.1/TxD:

Transmitter data output (asynchronous) or clock output (synchronous) of the serial

interface

P3.2/INT0:

External interrupt 0 input/timer 0 gate control input

P3.3/INT1:

External interrupt 1 input/timer 1 gate control input

P3.4/T0:

Timer 0 counter input

P3.5/T1:

Timer 1 counter input

It can drive CMOS inputs without external pull-ups.

Port 4:

Is an 2-bit bi-directional I/O port with internal pull-ups. Port 4 pins that have 1’s

written to them are pulled high by the internal pull-ups and can be used as inputs in

this state. As inputs, Port 4 pins that are being pulled low externally will be a source

of current (IIL, on the datasheet) because of the internal pull-up transistor.

It can drive CMOS inputs without external pull-ups.

P4.0:1

I/O

Reset:

A high level on this pin during two machine cycles while the oscillator is running

resets the device. An internal pull-down resistor to VSS permits power-on reset

using only an external capacitor to VCC.

RESET

XTAL1:

Input of the inverting oscillator amplifier and input of the internal clock generator

circuits. To drive the device from an external clock source, XTAL1 should be driven,

while XTAL2 is left unconnected. To operate above a frequency of 16 MHz, a duty

cycle of 50% should be maintained.

XTAL1

XTAL2

I

XTAL2:

O

Output from the inverting oscillator amplifier.

5

4128A–8051–04/02

I/O Configurations

Port Structure

Each Port SFR operates via type-D latches, as illustrated in Figure 1 for Ports 3 and 4. A

CPU "write to latch" signal initiates transfer of internal bus data into the type-D latch. A

CPU "read latch" signal transfers the latched Q output onto the internal bus. Similarly, a

"read pin" signal transfers the logical level of the Port pin. Some Port data instructions

activate the "read latch" signal while others activate the "read pin" signal. Latch instruc-

tions are referred to as Read-Modify-Write instructions. Each I/O line may be

independently programmed as input or output.

Figure 1 shows the structure of Ports, which have internal pull-ups. An external source

can pull the pin low. Each Port pin can be configured either for general-purpose I/O or

for its alternate input output function.

To use a pin for general-purpose output, set or clear the corresponding bit in the Px reg-

ister (x = 1 to 4). To use a pin for general-purpose input, set the bit in the Px register.

This turns off the output FET drive.

To configure a pin for its alternate function, set the bit in the Px register. When the latch

is set, the "alternate output function" signal controls the output level (see Figure 1). The

operation of Ports is discussed further in "quasi-Bidirectional Port Operation" paragraph.

Figure 1. Ports Structure

VCC

ALTERNATE

INTERNAL

PULL-UP (1)

OUTPUT

FUNCTION

READ

LATCH

P1.x

P2.x

P3.x

P4.x

INTERNAL

BUS

D

Q

LATCH

CL

WRITE

TO

LATCH

READ

ALTERNATE

INPUT

FUNCTION

Note:

The internal pull-up can be disabled on P1 when analog function is selected.

6

T89C5115

4128A–8051–04/02

T89C5115

Read-Modify-Write

Instructions

Some instructions read the latch data rather than the pin data. The latch based instruc-

tions read the data, modify the data and then rewrite the latch. These are called "Read-

Modify-Write" instructions. Below is a complete list of these special instructions (see

Table ). When the destination operand is a Port or a Port bit, these instructions read the

latch rather than the pin:

Table 2. Read-Modify-Write Instructions

Instruction

Description

Example

ANL

logical AND

ANL P1, A

ORL P2, A

XRL P3, A

JBC P1.1, LABEL

CPL P3.0

ORL

logical OR

XRL

logical EX-OR

JBC

jump if bit = 1 and clear bit

complement bit

CPL

INC

increment

INC P2

DEC

decrement

DEC P2

DJNZ

decrement and jump if not zero

move carry bit to bit y of Port x

clear bit y of Port x

set bit y of Port x

DJNZ P3, LABEL

MOV P1.5, C

CLR P2.4

MOV Px.y, C

CLR Px.y

SET Px.y

SET P3.3

It is not obvious the last three instructions in this list are Read-Modify-Write instructions.

These instructions read the port (all 8 bits), modify the specifically addressed bit and

write the new byte back to the latch. These Read-Modify-Write instructions are directed

to the latch rather than the pin in order to avoid possible misinterpretation of voltage

(and therefore, logic) levels at the pin. For example, a Port bit used to drive the base of

an external bipolar transistor can not rise above the transistor’s base-emitter junction

voltage (a value lower than VIL). With a logic one written to the bit, attempts by the CPU

to read the Port at the pin are misinterpreted as logic zero. A read of the latch rather

than the pins returns the correct logic-one value.

Quasi-bidirectional Port

Operation

Port 1, Port 3 and Port 4 have fixed internal pull-ups and are referred to as "quasi-bidi-

rectional" Ports. When configured as an input, the pin impedance appears as logic one

and sources current in response to an external logic zero condition. Resets write logic

one to all Port latches. If logical zero is subsequently written to a Port latch, it can be

returned to input conditions by a logical one written to the latch.

Note:

Port latch values change near the end of Read-Modify-Write insruction cycles. Output

buffers (and therefore the pin state) update early in the instruction after Read-Modify-

Write instruction cycle.

Logical zero-to-one transitions in Port 1, Port 3 and Port 4 use an additional pull-up (p1)

to aid this logic transition see Figure 2. This increases switch speed. This extra pull-up

sources 100 times normal internal circuit current during 2 oscillator clock periods. The

internal pull-ups are field-effect transistors rather than linear resistors. Pull-ups consist

of three p-channel FET (pFET) devices. A pFET is on when the gate senses logical zero

and off when the gate senses logical one. pFET #1 is turned on for two oscillator periods

immediately after a zero-to-one transition in the Port latch. A logical one at the Port pin

turns on pFET #3 (a weak pull-up) through the inverter. This inverter and pFET pair form

a latch to drive logical one. pFET #2 is a very weak pull-up switched on whenever the

7

4128A–8051–04/02

associated nFET is switched off. This is traditional CMOS switch convention. Current

strengths are 1/10 that of pFET #3

Figure 2. Internal Pull-Up Configurations

VCC

p2

VCC

p3

2 Osc. PERIODS

p1(1)

P1.x

P2.x

P3.x

P4.x

OUTPUT DATA

n

INPUT DATA

READ PIN

8

T89C5115

4128A–8051–04/02

T89C5115

SFR Mapping

The Special Function Registers (SFRs) of the T89C5115 fall into the following

categories:

Table 3. C51 Core SFRs

Mnemonic Add Name

7

6

5

4

3

2

1

0

ACC

B

E0h Accumulator

F0h B Register

–

CY

–

AC

–

F0

–

RS1

–

RS0

–

OV

–

F1

–

P

–

PSW

SP

D0h Program Status Word

81h Stack Pointer

Data Pointer Low

byte

DPL

DPH

82h

–

LSB of DPTR

Data Pointer High

byte

83h

MSB of DPTR

Table 4. I/O Port SFRs

Mnemonic Add Name

7

–

6

–

5

–

4

–

3

–

2

–

1

–

0

–

P1

P2

P3

P4

90h Port 1

A0h Port 2 (x2)

B0h Port 3

C0h Port 4 (x2)

Table 5. Timers SFRs

Mnemonic Add Name

7

6

5

4

3

2

1

0

Timer/Counter 0 High

byte

TH0

TL0

8Ch

8Ah

8Dh

8Bh

CDh

CCh

88h

89h

–

Timer/Counter 0 Low

byte

–

Timer/Counter 1 High

byte

TH1

TL1

–

Timer/Counter 1 Low

byte

–

Timer/Counter 2 High

byte

TH2

TL2

–

Timer/Counter 2 Low

byte

–

Timer/Counter 0 and

1 control

TCON

TMOD

TF1

GATE1

TR1

C/T1#

TF0

M11

TR0

M01

IE1

GATE0

IT1

C/T0#

IE0

M10

IT0

M00

Timer/Counter 0 and

1 Modes

9

4128A–8051–04/02

Table 5. Timers SFRs (Continued)

Mnemonic Add Name

7

6

5

4

3

2

1

0

Timer/Counter 2

control

T2CON

T2MOD

C8h

C9h

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

Timer/Counter 2

Mode

–

T2OE

–

DCEN

–

Timer/Counter 2

CBh Reload/Capture High

byte

RCAP2H

RCAP2L

Timer/Counter 2

CAh Reload/Capture Low

byte

–

WatchDog Timer

Reset

WDTRST

WDTPRG

A6h

–

WatchDog Timer

Program

A7h

S2

S1

S0

Table 6. Serial I/O Port SFRs

Mnemonic Add Name

7

6

SM1

–

5

SM2

–

4

REN

–

3

TB8

–

2

RB8

–

1

0

SCON

SBUF

98h Serial Control

FE/SM0

TI

–

RI

–

99h Serial Data Buffer

B9h Slave Address Mask

A9h Slave Address

–

SADEN

SADDR

–

Table 7. PCA SFRs

Mnemo

-nic

Add Name

7

6

5

4

3

2

1

CCF1

CPS0

–

0

CCF0

ECF

–

CCON

CMOD

CL

D8h PCA Timer/Counter Control

D9h PCA Timer/Counter Mode

E9h PCA Timer/Counter Low byte

F9h PCA Timer/Counter High byte

CF

CIDL

CR

–

CCF4

CCF3

CCF2

CPS1

WDTE

–

CH

–

CCAPM0 DAh PCA Timer/Counter Mode 0

CCAPM1 DBh PCA Timer/Counter Mode 1

ECOM0

ECOM1

CAPP0

CAPP1

CAPN0

CAPN1

MAT0

MAT1

TOG0

TOG1

PWM0

PWM1

ECCF0

ECCF1

CCAP0H FAh PCA Compare Capture Module 0 H CCAP0H7 CCAP0H6 CCAP0H5 CCAP0H4 CCAP0H3 CCAP0H2 CCAP0H1 CCAP0H0

CCAP1H FBh PCA Compare Capture Module 1 H CCAP1H7 CCAP1H6 CCAP1H5 CCAP1H4 CCAP1H3 CCAP1H2 CCAP1H1 CCAP1H0

CCAP0L EAh PCA Compare Capture Module 0 L CCAP0L7 CCAP0L6 CCAP0L5 CCAP0L4 CCAP0L3 CCAP0L2 CCAP0L1 CCAP0L0

CCAP1L EBh PCA Compare Capture Module 1 L CCAP1L7 CCAP1L6 CCAP1L5 CCAP1L4 CCAP1L3 CCAP1L2 CCAP1L1 CCAP1L0

10

T89C5115

4128A–8051–04/02

T89C5115

Table 8. Interrupt SFRs

Mnemonic Add Name

7

6

5

4

3

2

1

0

Interrupt Enable

Control 0

IEN0

IEN1

IPL0

IPH0

IPL1

IPH1

A8h

E8h

B8h

B7h

F8h

F7h

EA

EC

ET2

ES

ET1

EX1

ET0

EX0

Interrupt Enable

Control 1

–

PPC

PPCH

–

PT2

PT2H

–

PS

PSH

–

PT1

PT1H

–

PX1

PX1H

–

EADC

PT0

–

PX0

PX0H

–

Interrupt Priority

Control Low 0

Interrupt Priority

Control High 0

PT0H

Interrupt Priority

Control Low 1

PADCL

PADCH

Interrupt Priority

Control High1

–

Table 9. ADC SFRs

Mnemonic Add Name

7

6

PSIDLE

CH6

–

5

ADEN

CH5

–

4

3

2

1

0

ADCON

ADCF

F3h ADC Control

–

CH7

–

ADEOC

CH4

ADSST

CH3

SCH2

CH2

PRS2

ADAT4

–

SCH1

CH1

SCH0

CH0

F6h ADC Configuration

F2h ADC Clock

ADCLK

ADDH

ADDL

PRS4

ADAT6

–

PRS3

ADAT5

–

PRS1

ADAT3

ADAT1

PRS0

ADAT2

ADAT0

F5h ADC Data High byte

F4h ADC Data Low byte

ADAT9

–

ADAT8

–

ADAT7

–

Table 10. Other SFRs

Mnemonic Add Name

7

SMOD1

–

6

5

4

3

2

GF0

0

1

PD

0

PCON

87h Power Control

SMOD0

–

POF

–

GF1

GF3

T2X2

FPS

–

IDL

AUXR1

CKCON

FCON

A2h Auxiliary Register 1

8Fh Clock Control

ENBOOT

PCAX2

FPL1

–

DPS

–

WDX2

FPL2

EEPL2

SIX2

FPL0

EEPL0

T1X2

FMOD1

–

T0X2

FMOD0

EEE

X2

D1h Flash Control

FPL3

EEPL3

FBUSY

EEBUSY

EECON

D2h EEPROM Contol

EEPL1

11

4128A–8051–04/02

Table 11. SFR Mapping

0/8⁽¹⁾

1/9

CH

2/A

3/B

4/C

5/D

6/E

7/F

IPL1

CCAP0H

CCAP1H

F8h

FFh

F7h

EFh

E7h

xxxx x000

0000 0000

B

ADCLK

xxx0 0000

ADCON

x000 0000

ADDL

0000 0000

ADDH

0000 0000

ADCF

0000 0000

IPH1

xxxx x000

F0h

E8h

E0h

D8h

D0h

C8h

C0h

B8h

B0h

A8h

A0h

98h

90h

88h

80h

0000 0000

IEN1

xxxx x000

CL

0000 0000

CCAP0L

0000 0000

CCAP1L

0000 0000

ACC

0000 0000

CCON

0000 0000

CMOD

00xx x000

CCAPM0

x000 0000

CCAPM1

x000 0000

DF

h

PSW

0000 0000

FCON

0000 0000

EECON

xxxx xx00

D7h

T2CON

0000 0000

T2MOD

xxxx xx00

RCAP2L

0000 0000

RCAP2H

0000 0000

TL2

0000 0000

TH2

0000 0000

CF

h

P4

xxxx xx11

C7h

BFh

B7h

AFh

A7h

9Fh

97h

8Fh

87h

IPL0

x000 0000

SADEN

0000 0000

P3

1111 1111

IPH0

x000 0000

IEN0

0000 0000

SADDR

0000 0000

P2

1111 1111

AUXR1

xxxx 00x0

WDTRST

1111 1111

WDTPRG

xxxx x000

SCON

0000 0000

SBUF

0000 0000

P1

1111 1111

TCON

0000 0000

TMOD

0000 0000

TL0

0000 0000

TL1

0000 0000

TH0

0000 0000

TH1

0000 0000

CKCON

0000 0000

P0

1111 1111

SP

0000 0111

DPL

0000 0000

DPH

0000 0000

PCON

00x1 0000

0/8⁽¹⁾

1/9

2/A

3/B

4/C

5/D

6/E

7/F

Reserved

Note:

1. These registers are bit-addressable.

Sixteen addresses in the SFR space are both byte-addressable and bit-addressable. The bit-addressable SFR’s are those

whose address ends in 0 and 8. The bit addresses, in this area, are 0x80 through to 0xFF.

12

T89C5115

4128A–8051–04/02

T89C5115

Clock

The T89C5115 core needs only 6 clock periods per machine cycle. This feature, called

‘X2’, provides the following advantages:

•

Divides frequency crystals by 2 (cheaper crystals) while keeping the same CPU

power.

Saves power consumption while keeping the same CPU power (oscillator power

saving).

Saves power consumption by dividing dynamic operating frequency by 2 in

operating and idle modes.

Increases CPU power by 2 while keeping the same crystal frequency.

In order to keep the original C51 compatibility, a divider-by-2 is inserted between the

XTAL1 signal and the main clock input of the core (phase generator). This divider may

be disabled by the software.

An extra feature is available to start after Reset in the X2 mode. This feature can be

enabled by a bit X2B in the Hardware Security Byte. This bit is described in the section

"In-System Programming".

Description

The X2 bit in the CKCON register (see Table 12) allows switching from 12 clock cycles

per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated

(STD mode).

Setting this bit activates the X2 feature (X2 mode) for the CPU Clock only (see Figure

3.).

The Timers 0, 1 and 2, Uart, PCA or WatchDog switch in X2 mode only if the corre-

sponding bit is cleared in the CKCON register.

The clock for the whole circuit and peripheral is first divided by two before being used by

the CPU core and peripherals. This allows any cyclic ratio to be accepted on the XTAL1

input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic

ratio between 40 to 60%. Figure 3. shows the clock generation block diagram. The X2

bit is validated on the XTAL1÷2 rising edge to avoid glitches when switching from the X2

to the STD mode. Figure 4 shows the mode switching waveforms.

13

4128A–8051–04/02

Figure 3. Clock CPU Generation Diagram

X2B

Hardware byte

PCON.0

On RESET

IDL

X2

CKCON.0

CPU Core

Clock

0

1

XTAL1

XTAL2

÷ 2

CPU

CLOCK

PD

PCON.1

CPU Core Clock Symbol

and ADC

1

0

÷ 2

FT0 Clock

FT1 Clock

1

0

÷ 2

1

0

÷ 2

FT2 Clock

1

0

÷ 2

FUart Clock

1

0

÷ 2

FPca Clock

FWd Clock

1

÷ 2

0

PERIPH

CLOCK

X2

CKCON.0

Peripheral Clock Symbol

WDX2 PCAX2

SIX2

T2X2

T1X2

T0X2

CKCON.6 CKCON.5 CKCON.4 CKCON.3 CKCON.2 CKCON.1

14

T89C5115

4128A–8051–04/02

T89C5115

Figure 4. Mode Switching Waveforms

XTAL1

XTAL2

X2 bit

CPU

clock

STD

X2

STD

Mode

Note:

In order to prevent any incorrect operation while operating in the X2 mode, users must be aware that all peripherals using the

clock frequency as a time reference (UART, timers...) will have their time reference divided by two. For example a free running

timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. A UART with a 4800 baud rate will have

a 9600 baud rate.

15

4128A–8051–04/02

Register

Table 12. CKCON Register

CKCON (S:8Fh)

Clock Control Register

7

–

6

5

4

3

2

1

0

WDX2

PCAX2

SIX2

T2X2

T1X2

T0X2

X2

Bit

Number

Mnemonic Description

Reserved

7

6

-

The value read from this bit is indeterminate. Do not set this bit.

WatchDog clock⁽¹⁾

WDX2

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Programmable Counter Array clock⁽¹⁾

5

4

3

2

1

PCAX2

SIX2

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Enhanced UART clock (MODE 0 and 2)⁽¹⁾

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer2 clock⁽¹⁾

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

T2X2

T1X2

T0X2

Timer1 clock⁽¹⁾

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer0 clock⁽¹⁾

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

CPU clock

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all

the peripherals.

0

X2

Set to select 6 clock periods per machine cycle (X2 mode) and to enable the

individual peripherals "X2"bits.

Notes: 1. This control bit is validated when the CPU clock bit X2 is set; when X2 is low, this bit

has no effect.

Reset Value = x000 0000b

16

T89C5115

4128A–8051–04/02

T89C5115

Power Management

Introduction

Two power reduction modes are implemented in the T89C5115: the Idle mode and the

Power-down mode. These modes are detailed in the following sections. In addition to

these power reduction modes, the clocks of the core and peripherals can be dynamically

divided by 2 using the X2 mode detailed in Section “Clock”.

Reset

A reset is required after applying power at turn-on. To achieve a valid reset, the reset

signal must be maintained for at least 2 machine cycles (24 oscillator clock periods)

while the oscillator is running and stabilized and VCC established within the specified

operating ranges. A device reset initializes the T89C5115 and vectors the CPU to

address 0000h. RST input has a pull-down resistor allowing power-on reset by simply

connecting an external capacitor to V_DDas shown in Figure 5. Resistor value and input

characteristics are discussed in the Section “DC Characteristics” of the T89C5115

datasheet. The status of the Port pins during reset is detailed in Table 13.

Figure 5. Reset Circuitry and Power-On Reset

VDD

To CPU core

and peripherals

RST

+

RST

VSS

a. RST input circuitry

b. Power-on Reset

Table 13. Pin Conditions in Special Operating Modes

Mode

Port 1

High

Port 2

High

Port 3

High

Port 4

High

Reset

Idle

Data

Power-down

Reset Recommendation

to Prevent Flash

Corruption

A bad reset sequence will lead to bad microcontroller initialization and system registers

like SFR’s, Program Counter, etc. will not be correctly initialized. A bad initialization may

lead to unpredictable behaviour of the C51 microcontroller.

An example of this situation may occur in an instance where the bit ENBOOT in AUXR1

register is initialized from the hardware bit BLJB upon reset. Since this bit allows map-

ping of the bootloader in the code area, a reset failure can be critical.

If one wants the ENBOOT cleared inorder to unmap the boot from the code area (yet

due to a bad reset) the bit ENBOOT in SFR’s may be set. If the value of Program

Counter is accidently in the range of the boot memory addresses then a flash access

(write or erase) may corrupt the Flash on-chip memory .

It is recommended to use an external reset circuitry featuring power supply monitoring to

prevent system malfunction during periods of insufficient power supply voltage(power

supply failure, power supply switched off).

17

4128A–8051–04/02

Idle Mode

Idle mode is a power reduction mode that reduces the power consumption. In this mode,

program execution halts. Idle mode freezes the clock to the CPU at known states while

the peripherals continue to be clocked. The CPU status before entering Idle mode is

preserved, i.e., the program counter and program status word register retain their data

for the duration of Idle mode. The contents of the SFRs and RAM are also retained. The

status of the Port pins during Idle mode is detailed in Table 13.

Entering Idle Mode

Exiting Idle Mode

To enter Idle mode, set the IDL bit in PCON register (see Table 14). The T89C5115

enters Idle mode upon execution of the instruction that sets IDL bit. The instruction that

sets IDL bit is the last instruction executed.

Note:

If IDL bit and PD bit are set simultaneously, the T89C5115 enters Power-down mode.

Then it does not go in Idle mode when exiting Power-down mode.

There are two ways to exit Idle mode:

1. Generate an enabled interrupt.

–

Hardware clears IDL bit in PCON register which restores the clock to the

CPU. Execution resumes with the interrupt service routine. Upon completion

of the interrupt service routine, program execution resumes with the

instruction immediately following the instruction that activated Idle mode.

The general-purpose flags (GF1 and GF0 in PCON register) may be used to

indicate whether an interrupt occurred during normal operation or during Idle

mode. When Idle mode is exited by an interrupt, the interrupt service routine

may examine GF1 and GF0.

2. Generate a reset.

A logic high on the RST pin clears IDL bit in PCON register directly and

–

asynchronously. This restores the clock to the CPU. Program execution

momentarily resumes with the instruction immediately following the

instruction that activated the Idle mode and may continue for a number of

clock cycles before the internal reset algorithm takes control. Reset

initializes the T89C5115 and vectors the CPU to address C:0000h.

Note:

During the time that execution resumes, the internal RAM cannot be accessed; however,

it is possible for the Port pins to be accessed. To avoid unexpected outputs at the Port

pins, the instruction immediately following the instruction that activated Idle mode should

not write to a Port pin or to the external RAM.

Power-down Mode

The Power-down mode places the T89C5115 in a very low power state. Power-down

mode stops the oscillator, freezes all clock at known states. The CPU status prior to

entering Power-down mode is preserved, i.e., the program counter, program status

word register retain their data for the duration of Power-down mode. In addition, the

SFRs and RAM contents are preserved. The status of the Port pins during Power-down

mode is detailed in Table 13.

Note:

VDD may be reduced to as low as V_RETduring Power-down mode to further reduce

power dissipation. Take care, however, that VDD is not reduced until Power-down mode

is invoked.

Entering Power-down Mode

To enter Power-down mode, set PD bit in PCON register. The T89C5115 enters the

Power-down mode upon execution of the instruction that sets PD bit. The instruction

that sets PD bit is the last instruction executed.

18

T89C5115

4128A–8051–04/02

T89C5115

Exiting Power-down Mode

Note:

If VDD was reduced during the Power-down mode, do not exit Power-down mode until

VDD is restored to the normal operating level.

There are two ways to exit the Power-down mode:

1. Generate an enabled external interrupt.

–

The T89C5115 provides capability to exit from Power-down using INT0#,

INT1#.

Hardware clears PD bit in PCON register which starts the oscillator and

restores the clocks to the CPU and peripherals. Using INTx# input, execution

resumes when the input is released (see Figure 6). Execution resumes with

the interrupt service routine. Upon completion of the interrupt service

routine, program execution resumes with the instruction immediately

following the instruction that activated Power-down mode.

Notes: 1. The external interrupt used to exit Power-down mode must be configured as level

sensitive (INT0# and INT1#) and must be assigned the highest priority. In addition,

the duration of the interrupt must be long enough to allow the oscillator to stabilize.

The execution will only resume when the interrupt is deasserted.

2. Exit from power-down by external interrupt does not affect the SFRs nor the internal

RAM content.

Figure 6. Power-down Exit Waveform Using INT1:0#

INT1:0#

OSC

Active phase

Power-down phase

Oscillator restart phase

Active phase

2. Generate a reset.

–

A logic high on the RST pin clears PD bit in PCON register directly and

asynchronously. This starts the oscillator and restores the clock to the CPU

and peripherals. Program execution momentarily resumes with the

instruction immediately following the instruction that activated Power-down

mode and may continue for a number of clock cycles before the internal

reset algorithm takes control. Reset initializes the T89C5115 and vectors the

CPU to address 0000h.

Notes: 1. During the time that execution resumes, the internal RAM cannot be accessed; how-

ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at

the Port pins, the instruction immediately following the instruction that activated the

Power-down mode should not write to a Port pin or to the external RAM.

2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal

RAM content.

19

4128A–8051–04/02

Registers

PCON (S:87h)

Table 14. PCON Register

Power Configuration Register

7

–

6

–

5

–

4

–

3

2

1

0

GF1

GF0

PD

IDL

Bit

Number

Mnemonic Description

Reserved

7-4

3

–

The value read from these bits is indeterminate. Do not set these bits.

General-purpose flag 1

One use is to indicate whether an interrupt occurred during normal operation or

during Idle mode.

GF1

General-purpose flag 0

2

1

GF0

PD

One use is to indicate whether an interrupt occurred during normal operation or

during Idle mode.

Power-down Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Power-down mode.

If IDL and PD are both set, PD takes precedence.

Idle Mode bit

Cleared by hardware when an interrupt or reset occurs.

Set to activate the Idle mode.

0

IDL

If IDL and PD are both set, PD takes precedence.

Reset Value = XXXX 0000b

20

T89C5115

4128A–8051–04/02

T89C5115

Data Memory

The T89C5115 provides data memory access in two different spaces:

The internal space mapped in three separate segments:

•

the lower 128 bytes RAM segment.

the upper 128 bytes RAM segment.

the expanded 256 bytes RAM segment (ERAM).

A fourth internal segment is available but dedicated to Special Function Registers,

SFRs, (addresses 80h to FFh) accessible by direct addressing mode.

Figure 7 shows the internal data memory spaces organization.

Figure 7. Internal Memory – RAM

FFh

80h

FFh

Upper

128 bytes

Internal RAM

indirect addressing

Special

Function

Registers

direct addressing

256 bytes

Internal ERAM

80h

7Fh

Lower

128 bytes

Internal RAM

direct or indirect

addressing

00h

Internal Space

Lower 128 Bytes RAM

The lower 128 bytes of RAM (see Figure 7) are accessible from address 00h to 7Fh

using direct or indirect addressing modes. The lowest 32 bytes are grouped into 4 banks

of 8 registers (R0 to R7). Two bits RS0 and RS1 in PSW register (see Figure 16) select

which bank is in use according to Table . This allows more efficient use of code space,

since register instructions are shorter than instructions that use direct addressing, and

can be used for context switching in interrupt service routines.

Table 15. Register Bank Selection

RS1

RS0

Description

0

1

0

1

0

1

Register bank 0 from 00h to 07h

Register bank 0 from 08h to 0Fh

Register bank 0 from 10h to 17h

Register bank 0 from 18h to 1Fh

The next 16 bytes above the register banks form a block of bit-addressable memory

space. The C51 instruction set includes a wide selection of single-bit instructions, and

the 128 bits in this area can be directly addressed by these instructions. The bit

addresses in this area are 00h to 7Fh.

21

4128A–8051–04/02

Figure 8. Lower 128 bytes Internal RAM Organization

7Fh

30h

2Fh

Bit-Addressable Space

(Bit Addresses 0-7Fh)

20h

18h

10h

08h

00h

1Fh

17h

0Fh

07h

4 Banks of

8 Registers

R0-R7

Upper 128 Bytes RAM

Expanded RAM

The upper 128 bytes of RAM are accessible from address 80h to FFh using only indirect

addressing mode.

The on-chip 256 bytes of expanded RAM (ERAM) are accessible from address 0000h to

00FFh using indirect addressing mode through MOVX instructions. In this address

range.

Note:

Lower 128 bytes RAM, Upper 128 bytes RAM, and expanded RAM are made of volatile

memory cells. This means that the RAM content is indeterminate after power-up and

must then be initialized properly.

22

T89C5115

4128A–8051–04/02

T89C5115

Dual Data Pointer

Description

The T89C5115 implements a second data pointer for speeding up code execution and

reducing code size in case of intensive usage of external memory accesses.

DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR

addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1

register (see Figure 17) is used to select whether DPTR is the data pointer 0 or the data

pointer 1 (see Figure 9).

Figure 9. Dual Data Pointer Implementation

0

1

DPL0

DPL1

DPL

DPTR0

DPTR1

AUXR1.0

DPTR

DPS

0

1

DPH0

DPH1

DPH

Application

Software can take advantage of the additional data pointers to both increase speed and

reduce code size, for example, block operations (copy, compare…) are well served by

using one data pointer as a “source” pointer and the other one as a “destination” pointer.

Hereafter is an example of block move implementation using the two pointers and coded

in assembler. The latest C compiler takes also advantage of this feature by providing

enhanced algorithm libraries.

The INC instruction is a short (2 bytes) and fast (6 machine cycle) way to manipulate the

DPS bit in the AUXR1 register. However, note that the INC instruction does not directly

force the DPS bit to a particular state, but simply toggles it. In simple routines, such as

the block move example, only the fact that DPS is toggled in the proper sequence mat-

ters, not its actual value. In other words, the block move routine works the same whether

DPS is '0' or '1' on entry.

; ASCII block move using dual data pointers

; Modifies DPTR0, DPTR1, A and PSW

; Ends when encountering NULL character

; Note: DPS exits opposite to the entry state unless an extra INC AUXR1 is

added

AUXR1EQU0A2h

move:movDPTR,#SOURCE ; address of SOURCE

incAUXR1 ; switch data pointers

movDPTR,#DEST ; address of DEST

mv_loop:incAUXR1; switch data pointers

movxA,@DPTR; get a byte from SOURCE

incDPTR; increment SOURCE address

incAUXR1; switch data pointers

movx@DPTR,A; write the byte to DEST

incDPTR; increment DEST address

jnzmv_loop; check for NULL terminator

end_move:

23

4128A–8051–04/02

Registers

Table 16. PSW Register

PSW (S:8Eh)

Program Status Word Register

7

6

5

4

3

2

1

0

CY

AC

F0

RS1

RS0

OV

F1

P

Bit

Number

Mnemonic Description

Carry Flag

Carry out from bit 1 of ALU operands.

7

CY

Auxiliary Carry Flag

Carry out from bit 1 of addition operands.

6

5

AC

F0

User Definable Flag 0

Register Bank Select Bits

Refer to Table for bits description.

4-3

RS1:0

Overflow Flag

Overflow set by arithmetic operations.

2

1

OV

F1

User Definable Flag 1

Parity Bit

0

P

Set when ACC contains an odd number of 1’s.

Cleared when ACC contains an even number of 1’s.

Reset Value = 0000 0000b

24

T89C5115

4128A–8051–04/02

T89C5115

Table 17. AUXR1 Register

AUXR1 (S:A2h)

Auxiliary Control Register 1

7

–

6

–

5

4

–

3

2

0

1

–

0

ENBOOT

GF3

DPS

Bit

Number

Mnemonic Description

Reserved

7-6

5

–

The value read from these bits is indeterminate. Do not set these bits.

Enable Boot Flash

ENBOOT Set this bit for map the boot flash between F800h -FFFFh

Clear this bit for disable boot flash.

Reserved

4

3

–

The value read from this bit is indeterminate. Do not set this bit.

GF3

General-purpose Flag 3.

Always Zero

2

1

0

–

This bit is stuck to logic 0 to allow INC AUXR1 instruction without affecting GF3

flag.

Reserved for Data Pointer Extension.

Data Pointer Select Bit

Set to select second dual data pointer: DPTR1.

Clear to select first dual data pointer: DPTR0.

DPS

Reset Value = xxxx 00x0b

25

4128A–8051–04/02

EEPROM Data

Memory

The 2-kbyte on-chip EEPROM memory block is located at addresses 0000h to 07FFh of

the XRAM/ERAM memory space and is selected by setting control bits in the EECON

register. A read in the EEPROM memory is done with a MOVX instruction.

A physical write in the EEPROM memory is done in two steps: write data in the column

latches and transfer of all data latches into an EEPROM memory row (programming).

The number of data written on the page may vary from 1 up to 128 bytes (the page

size). When programming, only the data written in the column latch is programmed and

a ninth bit is used to obtain this feature. This provides the capability to program the

whole memory by bytes, by page or by a number of bytes in a page. Indeed, each ninth

bit is set when the writing the corresponding byte in a row and all these ninth bits are

reset after the writing of the complete EEPROM row.

Write Data in the Column Data is written by byte to the column latches as for an external RAM memory. Out of the

11 address bits of the data pointer, the 4 MSBs are used for page selection (row) and 7

Latches

are used for byte selection. Between two EEPROM programming sessions, all the

addresses in the column latches must stay on the same page, meaning that the 4 MSB

must no be changed.

The following procedure is used to write to the column latches:

•

Save and disable interrupt.

Set bit EEE of EECON register

Load DPTR with the address to write

Store A register with the data to be written

Execute a MOVX @DPTR, A

If needed loop the three last instructions until the end of a 128 bytes page

Restore interrupt.

Note:

The last page address used when loading the column latch is the one used to select the

page programming address.

Programming

The EEPROM programming consists of the following actions:

•

writing one or more bytes of one page in the column latches. Normally, all bytes

must belong to the same page; if not, the first page address will be latched and the

others discarded.

•

launching programming by writing the control sequence (50h followed by A0h) to the

EECON register.

EEBUSY flag in EECON is then set by hardware to indicate that programming is in

progress and that the EEPROM segment is not available for reading.

The end of programming is indicated by a hardware clear of the EEBUSY flag.

Note:

The sequence 5xh and Axh must be executed without instructions between them, other-

wise the programming is aborted.

Read Data

The following procedure is used to read the data stored in the EEPROM memory:

•

Save and disable interrupt

Set bit EEE of EECON register

Load DPTR with the address to read

Execute a MOVX A, @DPTR

Restore interrupt

26

T89C5115

4128A–8051–04/02

T89C5115

Examples

;*F*************************************************************************

;* NAME: api_rd_eeprom_byte

;* DPTR contain address to read.

;* Acc contain the reading value

;* NOTE: before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_rd_eeprom_byte:

MOV

MOVX A, @DPTR

MOV EECON, #00h; unmap EEPROM

ret

EECON, #02h; map EEPROM in XRAM space

;*F*************************************************************************

;* NAME: api_ld_eeprom_cl

;* DPTR contain address to load

;* Acc contain value to load

;* NOTE: in this example we load only 1 byte, but it is possible upto

;* 128 bytes.

;* before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_ld_eeprom_cl:

MOV

EECON, #02h ; map EEPROM in XRAM space

MOVX @DPTR, A

MOVEECON, #00h; unmap EEPROM

ret

;*F*************************************************************************

;* NAME: api_wr_eeprom

;* NOTE: before execute this function, be sure the EEPROM is not BUSY

;***************************************************************************

api_wr_eeprom:

MOV

EECON, #050h

EECON, #0A0h

ret

27

4128A–8051–04/02

Registers

Table 18. EECON Register

EECON (S:0D2h)

EEPROM Control Register

7

6

5

4

3

-

2

-

1

0

EEPL3

EEPL2

EEPL1

EEPL0

EEE

EEBUSY

Bit

Bit Number Mnemonic Description

Programming Launch Command bits

Write 5Xh followed by AXh to EEPL to launch the programming.

7-4

3

EEPL3-0

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

2

The value read from this bit is indeterminate. Do not set this bit.

Enable EEPROM Space bit

Set to map the EEPROM space during MOVX instructions (Write in the column

latches).

Clear to map the XRAM space during MOVX.

1

0

EEE

Programming Busy flag

Set by hardware when programming is in progress.

Cleared by hardware when programming is done.

Can not be set or cleared by software.

EEBUSY

Reset Value = XXXX XX00b

Not bit addressable

28

T89C5115

4128A–8051–04/02

T89C5115

Program/Code

Memory

The T89C5115 implement 16-KB of on-chip program/code memory.

The Flash memory increases EPROM and ROM functionality by in-circuit electrical era-

sure and programming. Thanks to the internal charge pump, the high voltage needed for

programming or erasing Flash cells is generated on-chip using the standard VDD volt-

age. Thus, the Flash Memory can be programmed using only one voltage and allows In-

System Programming commonly known as ISP. Hardware programming mode is also

available using specific programming tool.

Figure 10. Program/Code Memory Organization

3FFFh

16-KB

internal

Flash

0000h

Flash Memory

Architecture

T89C5115 features two on-chip flash memories:

•

Flash memory FM0:

containing 16-KB of program memory (user space) organized into pages 128 bytes

•

Flash memory FM1:

2K Bytes for boot loader and Application Programming Interfaces (API).

The FM0 can be program by both parallel programming and Serial In-System Program-

ming (ISP) whereas FM1 supports only parallel programming by programmers. The ISP

mode is detailed in the "In-System Programming" section.

All Read/Write access operations on Flash Memory by user application are managed by

a set of API described in the "In-System Programming" section.

Figure 11. Flash Memory Architecture

FFFFh

2K Bytes

Flash memory

boot space

Hardware Security (1 byte)

Extra Row (128 bytes)

FM1

F800h

Column Latches (128 bytes)

FM1 mapped between FFFFh and

F800h when bit ENBOOT is set in

AUXR1 register

3FFFh

16-KB

Flash memory

user space

FM0

0000h

29

4128A–8051–04/02

FM0 Memory Architecture

The Flash memory is made up of 4 blocks (see Figure 11):

1. The memory array (user space) 16-KB.

2. The Extra Row.

3. The Hardware security bits.

4. The column latch registers.

User Space

This space is composed of a 16-KB Flash memory organized in 128 pages of 128 bytes.

It contains the user’s application code.

Extra Row (XROW)

Hardware security Byte

This row is a part of FM0 and has a size of 128 bytes. The extra row may contain infor-

mation for boot loader usage.

The Hardware Security Byte space is a part of FM0 and has a size of 1 byte.

The 4 MSB can be read/written by software, the 4 LSB can only be read by software and

written by hardware in parallel mode.

Column Latches

The column latches, also part of FM0, have a size of full page (128 bytes).

The column latches are the entrance buffers of the three previous memory locations

(user array, XROW and Hardware security byte).

Cross Flash Memory Access

Description

The FM0 memory can be program only from FM1. Programming FM0 from FM0 or from

external memory is impossible.

The FM1 memory can be program only by parallel programming.

The Table 19 show all software flash access allowed.

Table 19. Cross Flash Memory Access

FM0

(user Flash)

FM1

(boot Flash)

Action

Read

Load column latch

Write

ok

-

FM0

(user Flash)

-

Read

ok

-

FM1

(boot flash)

Load column latch

Write

-

30

T89C5115

4128A–8051–04/02

T89C5115

Overview of FM0

Operations

The CPU interfaces to the Flash memory through the FCON register and AUXR1

register.

These registers are used to:

•

Map the memory spaces in the adressable space

Launch the programming of the memory spaces

Get the status of the flash memory (busy/not busy)

Mapping of the Memory Space By default, the user space is accessed by MOVC instruction for read only. The column

latches space is made accessible by setting the FPS bit in FCON register. Writing is

possible from 0000h to 3FFFh, address bits 6 to 0 are used to select an address within a

page while bits 14 to 7 are used to select the programming address of the page.

Setting FPS bit takes precedence on the EEE bit in EECON register.

The other memory spaces (user, extra row, hardware security) are made accessible in

the code segment by programming bits FMOD0 and FMOD1 in FCON register in accor-

dance with Table 20. A MOVC instruction is then used for reading these spaces.

Table 20. FM0 Blocks Select Bits

FMOD1

FMOD0

FM0 Adressable space

User (0000h-3FFFh)

Extra Row(FF80h-FFFFh)

Hardware Security Byte (0000h)

reserved

0

1

0

1

0

1

Launching Programming

FPL3:0 bits in FCON register are used to secure the launch of programming. A specific

sequence must be written in these bits to unlock the write protection and to launch the

programming. This sequence is 5xh followed by Axh. Table 21 summarizes the memory

spaces to program according to FMOD1:0 bits.

Table 21. Programming Spaces

Write to FCON

FPL3:0

FPS

FMOD1

FMOD0

Operation

5

X

0

No action

User

Write the column latches in user

space

A

5

X

0

1

No action

Extra Row

Write the column latches in extra row

space

A

Hardware

Security

Byte

5

X

1

0

No action

A

Write the fuse bits space

5

X

1

No action

Reserved

A

Note:

The sequence 5xh and Axh must be executing without instructions between them other-

wise the programming is aborted.

31

4128A–8051–04/02

Interrupts that may occur during programming time must be disabled to avoid any spuri-

ous exit of the programming mode.

Status of the Flash Memory

The bit FBUSY in FCON register is used to indicate the status of programming.

FBUSY is set when programming is in progress.

Selecting FM1

The bit ENBOOT in AUXR1 register is used to map FM1 from F800h to FFFFh.

Loading the Column Latches

Any number of data from 1 byte to 128 bytes can be loaded in the column latches. This

provides the capability to program the whole memory by byte, by page or by any number

of bytes in a page.

When programming is launched, an automatic erase of the locations loaded in the col-

umn latches is first performed, then programming is effectively done. Thus no page or

block erase is needed and only the loaded data are programmed in the corresponding

page.

The following procedure is used to load the column latches and is summarized in

Figure 12:

•

Disable interrupt and map the column latch space by setting FPS bit.

Load the DPTR with the address to load.

Load Accumulator register with the data to load.

Execute the MOVX @DPTR, A instruction.

If needed loop the three last instructions until the page is completely loaded.

unmap the column latch and Enable Interrupt

32

T89C5115

4128A–8051–04/02

T89C5115

Figure 12. Column Latches Loading Procedure

Column Latches

Loading

Save & Disable IT

EA= 0

Column Latches Mapping

FCON = 08h (FPS=1)

Data Load

DPTR= Address

ACC= Data

Exec: MOVX @DPTR, A

Last Byte

to load?

Data memory Mapping

FCON = 00h (FPS = 0)

Restore IT

Note:

The last page address used when loading the column latch is the one used to select the

page programming address.

Programming the Flash Spaces

User

The following procedure is used to program the User space and is summarized in

Figure 13:

•

Load up to one page of data in the column latches from address 0000h to 3FFFh.

Disable the interrupts.

Launch the programming by writing the data sequence 50h followed by A0h in

FCON register (only from FM1).

The end of the programming indicated by the FBUSY flag cleared.

•

Enable the interrupts.

Extra Row

The following procedure is used to program the Extra Row space and is summarized in

Figure 13:

•

Load data in the column latches from address FF80h to FFFFh.

Disable the interrupts.

Launch the programming by writing the data sequence 52h followed by A2h in

FCON register (only from FM1).

The end of the programming indicated by the FBUSY flag cleared.

•

Enable the interrupts.

33

4128A–8051–04/02

Figure 13. Flash and Extra row Programming Procedure

Flash Spaces

Programming

Column Latches Loading

see Figure 12

Save & Disable IT

EA= 0

Launch Programming

FCON= 5xh

FCON= Axh

FBusy

Cleared?

Clear Mode

FCON = 00h

End Programming

Restore IT

Hardware Security Byte

The following procedure is used to program the Hardware Security Byte space

and is summarized in Figure 14:

•

Set FPS and map Hardware byte (FCON = 0x0C)

Save and disable the interrupts.

Load DPTR at address 0000h.

Load Accumulator register with the data to load.

Execute the MOVX @DPTR, A instruction.

Launch the programming by writing the data sequence 54h followed by A4h in

FCON register (only from FM1).

The end of the programming indicated by the FBusy flag cleared.

•

Restore the interrupts

34

T89C5115

4128A–8051–04/02

T89C5115

Figure 14. Hardware Programming Procedure

Flash Spaces

Programming

Save & Disable IT

EA= 0

Save & Disable IT

EA= 0

Launch Programming

FCON= 54h

FCON= A4h

FCON = 0Ch

Data Load

DPTR= 00h

ACC= Data

FBusy

Cleared?

Exec: MOVX @DPTR, A

Clear Mode

FCON = 00h

End Loading

Restore IT

End Programming

RestoreIT

Reading the Flash Spaces

User

The following procedure is used to read the User space:

•

Read one byte in Accumulator by executing MOVC A,@A+DPTR with

A+DPTR=read@.

Note: FCON is supposed to be reset when not needed.

Extra Row

The following procedure is used to read the Extra Row space and is summarized in

Figure 15:

•

Map the Extra Row space by writing 02h in FCON register.

Read one byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 &

DPTR= FF80h to FFFFh.

•

Clear FCON to unmap the Extra Row.

Hardware Security Byte

The following procedure is used to read the Hardware Security space and is

summarized in Figure 15:

•

Map the Hardware Security space by writing 04h in FCON register.

Read the byte in Accumulator by executing MOVC A,@A+DPTR with A= 0 &

DPTR= 0000h.

•

Clear FCON to unmap the Hardware Security Byte.

35

4128A–8051–04/02

Figure 15. Reading Procedure

Flash Spaces Reading

Flash Spaces Mapping

FCON= 00000xx0b

Data Read

DPTR= Address

ACC= 0

Exec: MOVC A, @A+DPTR

Clear Mode

FCON = 00h

Flash Protection from Parallel The three lock bits in Hardware Security Byte (see "In-System Programming" section)

Programming

are programmed according to Table 22 provide different level of protection for the on-

chip code and data located in FM0 and FM1.

The only way to write this bits are the parallel mode. They are set by default to level 3.

Table 22. Program Lock bit

Program Lock Bits

Security

level

LB0

LB1

LB2

Protection Description

No program lock features enabled. MOVC instruction executed from

external program memory returns non encrypted data.

1

2

3

U

P

U

P

U

Parallel programming of the Flash is disabled.

Same as 2, also verify through parallel programming interface is

disabled.

Program Lock bits

U: unprogrammed

P: programmed

WARNING: Security level 2 and 3 should only be programmed after Flash and Core

verification.

Preventing Flash Corruption

See paragraph in the "Power Management" section, page 17.

36

T89C5115

4128A–8051–04/02

T89C5115

Registers

FCON Register

FCON (S:D1h)

Flash Control Register

7

6

5

4

3

2

1

0

FPL3

FPL2

FPL1

FPL0

FPS

FMOD1

FMOD0

FBUSY

Bit

Number

Mnemonic Description

Programming Launch Command Bits

7-4

FPL3:0

Write 5Xh followed by AXh to launch the programming according to FMOD1:0.

(see Table 21.)

Flash Map Program Space

3

FPS

Set to map the column latch space in the data memory space.

Clear to re-map the data memory space.

Flash Mode

See Table 20 or Table 21.

2-1

FMOD1:0

Flash Busy

Set by hardware when programming is in progress.

Clear by hardware when programming is done.

Can not be changed by software.

0

FBUSY

Reset Value = 0000 0000b

37

4128A–8051–04/02

In-System

Programming (ISP)

With the implementation of the User Space (FM0) and the Boot Space (FM1) in Flash

technology the T89C5115 allows the system engineer the development of applications

with a very high level of flexibility. This flexibility is based on the possibility to alter the

customer program at any stages of a product’s life:

•

Before assembly the 1st personalization of the product by programming in the FM0

and if needed also a customized Boot loader in the FM1.

Atmel provide also a standard Boot loader by default UART

•

After assembling on the PCB in its final embedded position by serial mode via the

UART.

This In-System Programming (ISP) allows code modification over the total lifetime of the

product.

Besides the default Boot loader Atmel provide to the customer also all the needed Appli-

cation-Programming-Interfaces (API) which are needed for the ISP. The API are located

also in the Boot memory.

This allow the customer to have a full use of the 16-Kbyte user memory.

Flash Programming and There are three methods of programming the Flash memory:

Erasure

•

The Atmel bootloader located in FM1 is activated by the application. Low level API

routines (located in FM1)will be used to program FM0. The interface used for serial

downloading to FM0 is the UART. API can be called also by user’s bootloader

located in FM0 at [SBV]00h.

•

A further method exist in activating the Atmel boot loader by hardware activation.

The FM0 can be programmed also by the parallel mode using a programmer.

Figure 16. Flash Memory Mapping

FFFFh

2K Bytes IAP

bootloader

FM1

F800h

3FFFh

FM1 mapped between F800h and FFFFh

when API called

Custom

Boot Loader

[SBV]00h

16-KB

Flash memory

FM0

0000h

38

T89C5115

4128A–8051–04/02

T89C5115

Boot Process

Software Boot Process

Example

Many algorithms can be used for the software boot process. Before describing them,

The description of the different flags and bytes is given below:

Boot Loader Jump Bit (BLJB):

- This bit indicates if on RESET the user wants to jump to this application at address

@0000h on FM0 or execute the boot loader at address @F800h on FM1.

- BLJB = 0 on parts delivered with bootloader programmed.

- To read or modify this bit, the APIs are used.

Boot Vector Address (SBV):

- This byte contains the MSB of the user boot loader address in FM0.

- The default value of SBV is FFh (no user boot loader in FM0).

- To read or modify this byte, the APIs are used.

Extra Byte (EB) & Boot Status Byte (BSB):

- These bytes are reserved for customer use.

- To read or modify these bytes, the APIs are used.

Figure 17. Hardware Boot Process Algorithm

bit ENBOOT in AUXR1 register

is initialized with BLJB.

RESET

ENBOOT = 0

PC = 0000h

BLJB == 0

?

ENBOOT = 1

PC = F800h

Application

in FM0

Boot Loader

in FM1

39

4128A–8051–04/02

Application

Programming Interface

Several Application Program Interface (API) calls are available for use by an application

program to permit selective erasing and programming of Flash pages. All calls are made

by functions.

All APIs are describe in: "In-System Programing: Flash Library for T89C5115", available

on the Atmel web site at www.atmel.com.

Table 23. List of API

API Call

Description

PROGRAM DATA BYTE

PROGRAM DATA PAGE

PROGRAM EEPROM BYTE

ERASE BLOCK

Write a byte in flash memory

Write a page (128 bytes) in flash memory

Write a byte in Eeprom memory

Erase all flash memory

ERASE BOOT VECTOR (SBV)

PROGRAM BOOT VECTOR (SBV)

PROGRAM EXTRA BYTE (EB)

READ DATA BYTE

Erase the boot vector

Write the boot vector

Write the extra byte

–

READ EEPROM BYTE

READ FAMILY CODE

READ MANUFACTURER CODE

READ PRODUCT NAME

READ REVISION NUMBER

READ STATUS BIT (BSB)

READ BOOT VECTOR (SBV)

READ EXTRA BYTE (EB)

PROGRAM X2

–

Read the status bit

Read the boot vector

Read the extra byte

Write the hardware flag for X2 mode

Read the hardware flag for X2 mode

To start the bootloader from the application

READ X2

START BOOTLOADER

XROW Bytes

Table 24. XROW Mapping

Mnemonic

Description

Default value

Address

30h

–

Copy of the Manufacturer Code

Copy of the Device ID#1: Family code

58h

D7h

31h

Copy of the Device ID#2: Memories size and type BBh

Copy of the Device ID#3: Name and Revision FFh

60h

61h

40

T89C5115

4128A–8051–04/02

T89C5115

Hardware Security Byte

Table 25. Hardware Security byte

7

6

5

-

4

-

3

-

2

1

0

X2B

BLJB

LB2

LB1

LB0

Bit

Number

Mnemonic Description

X2 Bit

7

6

X2B

Set this bit to start in standard mode

Clear this bit to start in X2 mode.

Boot Loader Jump Bit

- 1: To start the user’s application on next RESET (@0000h) located in FM0,

- 0: To start the boot loader(@F800h) located in FM1.

BLJB

Reserved

5-3

2-0

-

The value read from these bits are indeterminate.

LB2:0

Lock Bits

Default value after erasing chip: FFh

Notes: 1. Only the 4 MSB bits can be accessed by software.

2. The 4 LSB bits can only be accessed by parallel mode.

41

4128A–8051–04/02

Serial I/O Port

The T89C5115 I/O serial port is compatible with the I/O serial port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as a

Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes

(Modes 1, 2 and 3). Asynchronous transmission and reception can occur simultaneously

and at different baud rates

Serial I/O port includes the following enhancements:

•

Framing error detection

Automatic address recognition

Figure 18. Serial I/O Port Block Diagram

IB Bus

Write SBUF

Read SBUF

Load SBUF

SBUF

Receiver

SBUF

Transmitter

TXD

RXD

Mode 0 Transmit

Receive

Shift register

Serial Port

Interrupt Request

RI

TI

Framing Error Detection Framing bit error detection is provided for the three asynchronous modes. To enable the

framing bit error detection feature, set SMOD0 bit in PCON register.

Figure 19. Framing Error Block Diagram

SM0/FE SM1

SM2

REN

TB8

RB8

TI

RI

Set FE bit if stop bit is 0 (framing error)

SM0 to UART mode control

SMOD1SMOD0

-

POF GF1

GF0

PD

IDL

To UART framing error control

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in

SCON register bit is set.

The software may examine the FE bit after each reception to check for data errors.

Once set, only software or a reset clears the FE bit. Subsequently received frames with

42

T89C5115

4128A–8051–04/02

T89C5115

valid stop bits cannot clear the FE bit. When the FE feature is enabled, RI rises on the

stop bit instead of the last data bit (See Figure 20 and Figure 21).

Figure 20. UART Timing in Mode 1

RXD

D0

D1

D2

D3

D4

D5

D6

D7

Start

bit

Data byte

Stop

bit

RI

SMOD0=X

FE

SMOD0=1

Figure 21. UART Timing in Modes 2 and 3

RXD

D0

D1

D2

D3

D4

D5

D6

D7

D8

Start

bit

Data byte

Ninth Stop

bit

RI

SMOD0=0

RI

SMOD0=1

FE

SMOD0=1

Automatic Address

Recognition

The automatic address recognition feature is enabled when the multiprocessor commu-

nication feature is enabled (SM2 bit in SCON register is set).

Implemented in the hardware, automatic address recognition enhances the multiproces-

sor communication feature by allowing the serial port to examine the address of each

incoming command frame. Only when the serial port recognizes its own address will the

receiver set the RI bit in the SCON register to generate an interrupt. This ensures that

the CPU is not interrupted by command frames addressed to other devices.

If necessary, you can enable the automatic address recognition feature in mode 1. In

this configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when

the received command frame address matches the device’s address and is terminated

by a valid stop bit.

To support automatic address recognition, a device is identified by a given address and

a broadcast address.

Note:

The multiprocessor communication and automatic address recognition features cannot

be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).

43

4128A–8051–04/02

Given Address

Each device has an individual address that is specified in the SADDR register; the

SADEN register is a mask byte that contains don’t-care bits (defined by zeros) to form

the device’s given address. The don’t-care bits provide the flexibility to address one or

more slaves at a time. The following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask byte must be 1111

1111b.

For example:

SADDR0101 0110b

SADEN1111 1100b

Given0101 01XXb

Here is an example of how to use given addresses to address different slaves:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 0X0Xb

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 0XX1b

Slave C:SADDR1111 0010b

SADEN1111 1101b

Given1111 00X1b

The SADEN byte is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To com-

municate with slave A only, the master must send an address where bit 0 is clear (e.g.

1111 0000b).

For slave A, bit 1 is a 0; for slaves B and C, bit 1 is a don’t care bit. To communicate with

slaves A and B, but not slave C, the master must send an address with bits 0 and 1 both

set (e.g. 1111 0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0 set,

bit 1 clear, and bit 2 clear (e.g. 1111 0001b).

Broadcast Address

A broadcast address is formed from the logical OR of the SADDR and SADEN registers

with zeros defined as don’t-care bits, e.g.:

SADDR 0101 0110b

SADEN 1111 1100b

SADDR OR SADEN1111 111Xb

The use of don’t-care bits provides flexibility in defining the broadcast address, however

in most applications, a broadcast address is FFh. The following is an example of using

broadcast addresses:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 1X11b,

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 1X11B,

Slave C:SADDR=1111 0010b

SADEN1111 1101b

Given1111 1111b

44

T89C5115

4128A–8051–04/02

T89C5115

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with

all of the slaves, the master must send an address FFh. To communicate with slaves A

and B, but not slave C, the master can send and address FBh.

Registers

Table 26. SCON Register

SCON (S:98h)

Serial Control Register

7

6

5

4

3

2

1

0

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

Bit

Number

Mnemonic Description

Framing Error bit (SMOD0 = 1)

7

–

FE

Clear to reset the error state, not cleared by a valid stop bit.

Set by hardware when an invalid stop bit is detected.

Serial port Mode bit 0 (SMOD0 = 0)

Refer to SM1 for serial port mode selection.

SM0

Serial port Mode bit 1

SM0 SM1 Mode

Baud Rate

0

1

0

1

0

1

Shift Register F_XTAL/12 (or F_XTAL/6 in mode X2)

6

SM1

8-bit UART

9-bit UART

Variable

_XTAL/64 or F_XTAL/32

Variable

F

Serial port Mode 2 bit/Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature.

Set to enable multiprocessor communication feature in mode 2 and 3.

5

4

3

2

SM2

REN

TB8

RB8

Reception Enable bit

Clear to disable serial reception.

Set to enable serial reception.

Transmitter Bit 8/Ninth bit to transmit in modes 2 and 3

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

Receiver Bit 8/Ninth bit received in modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

Transmit Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the

stop bit in the other modes.

1

0

TI

Receive Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, see Figure 20 and

Figure 21 in the other modes.

RI

Reset Value = 0000 0000b

Bit addressable

45

4128A–8051–04/02

Table 27. SADEN Register

SADEN (S:B9h)

Slave Address Mask Register

7

6

5

4

3

2

1

0

Bit

Number

Bit

Mnemonic Description

7-0

–

Mask Data for Slave Individual Address

Reset Value = 0000 0000b

Not bit addressable

Table 28. SADDR Register

SADDR (S:A9h)

Slave Address Register

7

6

5

4

3

Bit

Number

Bit

Mnemonic Description

7-0

–

Slave Individual Address

Reset Value = 0000 0000b

Not bit addressable

Table 29. SBUF Register

SBUF (S:99h)

Serial Data Buffer

7

6

5

4

3

–

Bit

Number

Bit

Mnemonic Description

7-0

–

Data sent/received by Serial I/O Port

Reset Value = 0000 0000b

Not bit addressable

46

T89C5115

4128A–8051–04/02

T89C5115

Table 30. PCON Register

PCON (S:87h)

Power Control Register

7

6

5

-

4

3

2

1

0

SMOD1

SMOD0

POF

GF1

GF0

PD

IDL

Bit

Number

Mnemonic Description

Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

7

6

5

SMOD1

Serial port Mode bit 0

SMOD0 Clear to select SM0 bit in SCON register.

Set to select FE bit in SCON register.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag

Clear to recognize next reset type.

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set

by software.

4

POF

General-purpose Flag

3

2

1

0

GF1

GF0

PD

Cleared by user for general-purpose usage.

Set by user for general-purpose usage.

General-purpose Flag

Cleared by user for general-purpose usage.

Set by user for general-purpose usage.

Power-down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle mode bit

Clear by hardware when interrupt or reset occurs.

Set to enter idle mode.

IDL

Reset Value = 00x1 0000b

Not bit addressable

47

4128A–8051–04/02

Timers/Counters

The T89C5115 implements two general-purpose, 16-bit Timers/Counters. Such are

identified as Timer 0 and Timer 1, and can be independently configured to operate in a

variety of modes as a Timer or an event Counter. When operating as a Timer, the

Timer/Counter runs for a programmed length of time, then issues an interrupt request.

When operating as a Counter, the Timer/Counter counts negative transitions on an

external pin. After a preset number of counts, the Counter issues an interrupt request.

The various operating modes of each Timer/Counter are described in the following

sections.

Timer/Counter

Operations

A basic operation is Timer registers THx and TLx (x= 0, 1) connected in cascade to form

a 16-bit Timer. Setting the run control bit (TRx) in TCON register (see Figure 31) turns

the Timer on by allowing the selected input to increment TLx. When TLx overflows it

increments THx; when THx overflows it sets the Timer overflow flag (TFx) in TCON reg-

ister. Setting the TRx does not clear the THx and TLx Timer registers. Timer registers

can be accessed to obtain the current count or to enter preset values. They can be read

at any time but TRx bit must be cleared to preset their values, otherwise the behavior of

the Timer/Counter is unpredictable.

The C/Tx# control bit selects Timer operation or Counter operation by selecting the

divided-down peripheral clock or external pin Tx as the source for the counted signal.

TRx bit must be cleared when changing the mode of operation, otherwise the behavior

of the Timer/Counter is unpredictable.

For Timer operation (C/Tx#= 0), the Timer register counts the divided-down peripheral

clock. The Timer register is incremented once every peripheral cycle (6 peripheral clock

periods). The Timer clock rate is F_PER/6, i.e. F_OSC/12 in standard mode or F_OSC/6 in X2

mode.

For Counter operation (C/Tx#= 1), the Timer register counts the negative transitions on

the Tx external input pin. The external input is sampled every peripheral cycles. When

the sample is high in one cycle and low in the next one, the Counter is incremented.

Since it takes 2 cycles (12 peripheral clock periods) to recognize a negative transition,

the maximum count rate is F_PER/12, i.e. F_OSC/24 in standard mode or F_OSC/12 in X2

mode. There are no restrictions on the duty cycle of the external input signal, but to

ensure that a given level is sampled at least once before it changes, it should be held for

at least one full peripheral cycle.

Timer 0

Timer 0 functions as either a Timer or event Counter in four modes of operation.

Figure 22 to Figure 25 show the logical configuration of each mode.

Timer 0 is controlled by the four lower bits of TMOD register (see Figure 32) and bits 0,

1, 4 and 5 of TCON register (see Figure 31). TMOD register selects the method of Timer

gating (GATE0), Timer or Counter operation (T/C0#) and mode of operation (M10 and

M00). TCON register provides Timer 0 control functions: overflow flag (TF0), run control

bit (TR0), interrupt flag (IE0) and interrupt type control bit (IT0).

For normal Timer operation (GATE0= 0), setting TR0 allows TL0 to be incremented by

the selected input. Setting GATE0 and TR0 allows external pin INT0# to control Timer

operation.

Timer 0 overflow (count rolls over from all 1s to all 0s) sets TF0 flag generating an inter-

rupt request.

It is important to stop Timer/Counter before changing mode.

48

T89C5115

4128A–8051–04/02

T89C5115

Mode 0 (13-bit Timer)

Mode 0 configures Timer 0 as an 13-bit Timer which is set up as an 8-bit Timer (TH0

register) with a modulo 32 prescaler implemented with the lower five bits of TL0 register

(see Figure 22). The upper three bits of TL0 register are indeterminate and should be

ignored. Prescaler overflow increments TH0 register.

Figure 22. Timer/Counter x (x= 0 or 1) in Mode 0

see the “Clock” section

FTx

Timer x

Interrupt

Request

÷ 6

0

1

Overflow

THx

(8 bits)

TLx

(5 bits)

CLOCK

Tx

TFx

TCON reg

C/Tx#

TMOD reg

INTx#

GATEx

TMOD reg

TRx

TCON reg

Mode 1 (16-bit Timer)

Mode 1 configures Timer 0 as a 16-bit Timer with TH0 and TL0 registers connected in

cascade (see Figure 23). The selected input increments TL0 register.

Figure 23. Timer/Counter x (x= 0 or 1) in Mode 1

see the “Clock” section

FTx

Timer x

Interrupt

Request

÷ 6

0

1

Overflow

THx

(8 bits)

TLx

(8 bits)

CLOCK

Tx

TFx

TCON reg

C/Tx#

TMOD reg

INTx#

GATEx

TMOD reg

TRx

TCON reg

49

4128A–8051–04/02

Mode 2 (8-bit Timer with Auto- Mode 2 configures Timer 0 as an 8-bit Timer (TL0 register) that automatically reloads

Reload)

from TH0 register (see Figure 24). TL0 overflow sets TF0 flag in TCON register and

reloads TL0 with the contents of TH0, which is preset by software. When the interrupt

request is serviced, hardware clears TF0. The reload leaves TH0 unchanged. The next

reload value may be changed at any time by writing it to TH0 register.

Figure 24. Timer/Counter x (x= 0 or 1) in Mode 2

see section “Clock”

FTx

CLOCK

Timer x

Interrupt

Request

÷ 6

0

1

Overflow

TLx

(8 bits)

TFx

TCON reg

Tx

C/Tx#

TMOD reg

INTx#

THx

(8 bits)

GATEx

TMOD reg

TRx

TCON reg

Mode 3 (Two 8-bit Timers)

Mode 3 configures Timer 0 such that registers TL0 and TH0 operate as separate 8-bit

Timers (see Figure 25). This mode is provided for applications requiring an additional 8-

bit Timer or Counter. TL0 uses the Timer 0 control bits C/T0# and GATE0 in TMOD reg-

ister, and TR0 and TF0 in TCON register in the normal manner. TH0 is locked into a

Timer function (counting F_PER/6) and takes over use of the Timer 1 interrupt (TF1) and

run control (TR1) bits. Thus, operation of Timer 1 is restricted when Timer 0 is in mode

3.

Figure 25. Timer/Counter 0 in Mode 3: Two 8-bit Counters

FTx

CLOCK

Timer 0

Interrupt

Request

÷ 6

0

1

Overflow

TL0

(8 bits)

TF0

TCON.5

T0

C/T0#

TMOD.2

INT0#

GATE0

TMOD.3

TR0

TCON.4

Timer 1

Interrupt

Request

Overflow

FTx

CLOCK

TH0

(8 bits)

÷ 6

TF1

TCON.7

TR1

TCON.6

see section “Clock”

50

T89C5115

4128A–8051–04/02

T89C5115

Timer 1

Timer 1 is identical to Timer 0 excepted for Mode 3 which is a hold-count mode. Follow-

ing comments help to understand the differences:

•

Timer 1 functions as either a Timer or event Counter in three modes of operation.

Figure 22 to Figure 24 show the logical configuration for modes 0, 1, and 2. Timer

1’s mode 3 is a hold-count mode.

•

Timer 1 is controlled by the four high-order bits of TMOD register (see Figure 32)

and bits 2, 3, 6 and 7 of TCON register (see Figure 31). TMOD register selects the

method of Timer gating (GATE1), Timer or Counter operation (C/T1#) and mode of

operation (M11 and M01). TCON register provides Timer 1 control functions:

overflow flag (TF1), run control bit (TR1), interrupt flag (IE1) and interrupt type

control bit (IT1).

•

Timer 1 can serve as the Baud Rate Generator for the Serial Port. Mode 2 is best

suited for this purpose.

For normal Timer operation (GATE1= 0), setting TR1 allows TL1 to be incremented

by the selected input. Setting GATE1 and TR1 allows external pin INT1# to control

Timer operation.

•

Timer 1 overflow (count rolls over from all 1s to all 0s) sets the TF1 flag generating

an interrupt request.

When Timer 0 is in mode 3, it uses Timer 1’s overflow flag (TF1) and run control bit

(TR1). For this situation, use Timer 1 only for applications that do not require an

interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in

and out of mode 3 to turn it off and on.

•

It is important to stop Timer/Counter before changing mode.

Mode 0 (13-bit Timer)

Mode 1 (16-bit Timer)

Mode 0 configures Timer 1 as a 13-bit Timer, which is set up as an 8-bit Timer (TH1 reg-

ister) with a modulo-32 prescaler implemented with the lower 5 bits of the TL1 register

(see Figure 22). The upper 3 bits of TL1 register are ignored. Prescaler overflow incre-

ments TH1 register.

Mode 1 configures Timer 1 as a 16-bit Timer with TH1 and TL1 registers connected in

cascade (see Figure 23). The selected input increments TL1 register.

Mode 2 (8-bit Timer with Auto- Mode 2 configures Timer 1 as an 8-bit Timer (TL1 register) with automatic reload from

Reload)

TH1 register on overflow (see Figure 24). TL1 overflow sets TF1 flag in TCON register

and reloads TL1 with the contents of TH1, which is preset by software. The reload

leaves TH1 unchanged.

Mode 3 (Halt)

Placing Timer 1 in mode 3 causes it to halt and hold its count. This can be used to halt

Timer 1 when TR1 run control bit is not available i.e. when Timer 0 is in mode 3.

51

4128A–8051–04/02

Interrupt

Each Timer handles one interrupt source that is the timer overflow flag TF0 or TF1. This

flag is set every time an overflow occurs. Flags are cleared when vectoring to the Timer

interrupt routine. Interrupts are enabled by setting ETx bit in IEN0 register. This assumes

interrupts are globally enabled by setting EA bit in IEN0 register.

Figure 26. Timer Interrupt System

Timer 0

Interrupt Request

TF0

TCON.5

ET0

IEN0.1

Timer 1

Interrupt Request

TF1

TCON.7

ET1

IEN0.3

52

T89C5115

4128A–8051–04/02

T89C5115

Registers

Table 31. TCON Register

TCON (S:88h)

Timer/Counter Control Register

7

6

5

4

3

2

1

0

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

Bit

Number

Mnemonic Description

Timer 1 Overflow Flag

Cleared by hardware when processor vectors to interrupt routine.

Set by hardware on Timer/Counter overflow, when Timer 1 register overflows.

7

6

5

4

3

2

1

0

TF1

TR1

TF0

TR0

IE1

Timer 1 Run Control Bit

Clear to turn off Timer/Counter 1.

Set to turn on Timer/Counter 1.

Timer 0 Overflow Flag

Cleared by hardware when processor vectors to interrupt routine.

Set by hardware on Timer/Counter overflow, when Timer 0 register overflows.

Timer 0 Run Control Bit

Clear to turn off Timer/Counter 0.

Set to turn on Timer/Counter 0.

Interrupt 1 Edge Flag

Cleared by hardware when interrupt is processed if edge-triggered (see IT1).

Set by hardware when external interrupt is detected on INT1# pin.

Interrupt 1 Type Control Bit

Clear to select low level active (level triggered) for external interrupt 1 (INT1#).

Set to select falling edge active (edge triggered) for external interrupt 1.

IT1

Interrupt 0 Edge Flag

Cleared by hardware when interrupt is processed if edge-triggered (see IT0).

Set by hardware when external interrupt is detected on INT0# pin.

IE0

Interrupt 0 Type Control Bit

Clear to select low level active (level triggered) for external interrupt 0 (INT0#).

Set to select falling edge active (edge triggered) for external interrupt 0.

IT0

Reset Value = 0000 0000b

53

4128A–8051–04/02

Table 32. TMOD Register

TMOD (S:89h)

Timer/Counter Mode Control Register

7

6

5

4

3

2

1

0

GATE1

C/T1#

M11

M01

GATE0

C/T0#

M10

M00

Bit

Number

Mnemonic Description

Timer 1 Gating Control Bit

Clear to enable Timer 1 whenever TR1 bit is set.

7

GATE1

Set to enable Timer 1 only while INT1# pin is high and TR1 bit is set.

Timer 1 Counter/Timer Select Bit

6

5

C/T1#

M11

Clear for Timer operation: Timer 1 counts the divided-down system clock.

Set for Counter operation: Timer 1 counts negative transitions on external pin T1.

Timer 1 Mode Select Bits

M11 M01 Operating mode

0

1

Mode 0: 8-bit Timer/Counter (TH1) with 5-bit prescaler (TL1).

Mode 1: 16-bit Timer/Counter.

4

M01

1

0

Mode 3: Timer 1 halted. Retains count.

Mode 2: 8-bit auto-reload Timer/Counter (TL1).⁽¹⁾

Timer 0 Gating Control Bit

3

2

GATE0

C/T0#

Clear to enable Timer 0 whenever TR0 bit is set.

Set to enable Timer/Counter 0 only while INT0# pin is high and TR0 bit is set.

Timer 0 Counter/Timer Select Bit

Clear for Timer operation: Timer 0 counts the divided-down system clock.

Set for Counter operation: Timer 0 counts negative transitions on external pin T0.

Timer 0 Mode Select Bit

M10 M00 Operating mode

1

0

M10

M00

0

1

0

1

0

Mode 0: 8-bit Timer/Counter (TH0) with 5-bit prescaler (TL0).

Mode 1: 16-bit Timer/Counter.

Mode 2: 8-bit auto-reload Timer/Counter (TL0).⁽²⁾

1

Mode 3: TL0 is an 8-bit Timer/Counter.

TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 bits.

Notes: 1. Reloaded from TH1 at overflow.

2. Reloaded from TH0 at overflow.

Reset Value = 0000 0000b

54

T89C5115

4128A–8051–04/02

T89C5115

Table 33. TH0 Register

TH0 (S:8Ch)

Timer 0 High Byte Register

7

6

5

4

3

2

1

0

Bit

Number

Mnemonic Description

7:0

High Byte of Timer 0.

Reset Value = 0000 0000b

Table 34. TL0 Register

TL0 (S:8Ah)

Timer 0 Low Byte Register

7

6

5

4

3

2

1

0

Bit

Number

Mnemonic Description

7:0

Low Byte of Timer 0.

Reset Value = 0000 0000b

Table 35. TH1 Register

TH1 (S:8Dh)

Timer 1 High Byte Register

7

6

5

4

3

2

1

0

Bit

Number

Mnemonic Description

7:0

High Byte of Timer 1.

Reset Value = 0000 0000b

55

4128A–8051–04/02

Table 36. TL1 Register

TL1 (S:8Bh)

Timer 1 Low Byte Register

7

6

5

4

3

2

1

0

Bit

Number

Mnemonic Description

7:0

Low Byte of Timer 1.

Reset Value = 0000 0000b

56

T89C5115

4128A–8051–04/02

T89C5115

Timer 2

The T89C5115 Timer 2 is compatible with Timer 2 in the 80C52.

It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2

and TL2 that are cascade- connected. It is controlled by T2CON register (See Table )

and T2MOD register (See Table 39). Timer 2 operation is similar to Timer 0 and Timer

1. C/T2 selects F_{T2 clock}/6 (timer operation) or external pin T2 (counter operation) as

timer clock. Setting TR2 allows TL2 to be incremented by the selected input.

Timer 2 includes the following enhancements:

•

Auto-reload mode (up or down counter)

Programmable clock-output

Auto-reload Mode

The auto-reload mode configures Timer 2 as a 16-bit timer or event counter with auto-

matic reload. This feature is controlled by the DCEN bit in T2MOD register (See

Table 39). Setting the DCEN bit enables Timer 2 to count up or down as shown in

Figure 27. In this mode the T2EX pin controls the counting direction.

When T2EX is high, Timer 2 counts up. Timer overflow occurs at FFFFh which sets the

TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value

in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.

When T2EX is low, Timer 2 counts down. Timer underflow occurs when the count in the

timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.

The underflow sets TF2 flag and reloads FFFFh into the timer registers.

The EXF2 bit toggles when Timer 2 overflow or underflow, depending on the direction of

the count. EXF2 does not generate an interrupt. This bit can be used to provide 17-bit

resolution.

Figure 27. Auto-reload Mode Up/Down Counter

see section “Clock”

FT2

:6

0

1

CLOCK

TR2

T2CON.2

CT/2

T2CON.1

T2

(DOWN COUNTING RELOAD VALUE)

T2EX:

FFh

(8-bit)

FFh

(8-bit)

1=UP

2=DOWN

T2CONreg

EXF2

TOGGLE

TL2

(8-bit)

TH2

(8-bit)

Timer 2

INTERRUPT

TF2

T2CONreg

RCAP2L

(8-bit)

RCAP2H

(8-bit)

(UP COUNTING RELOAD VALUE)

57

4128A–8051–04/02

Programmable Clock-

Output

In clock-out mode, Timer 2 operates as a 50%-duty-cycle, programmable clock genera-

tor (See Figure 28). The input clock increments TL2 at frequency F_OSC/2. The timer

repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H

and RCAP2L registers are loaded into TH2 and TL2. In this mode, Timer 2 overflows do

not generate interrupts. The formula gives the clock-out frequency depending on the

system oscillator frequency and the value in the RCAP2H and RCAP2L registers:

FT2clock

4 × (65536 – RCAP2H ⁄ RCAP2L)

-------------------------------------------------------------------------------------------

Clock – OutFrequency =

For a 16 MHz system clock in x1 mode, Timer 2 has a programmable frequency range

of 61 Hz (F_OSC/2¹⁶⁾to 4 MHz (F_OSC/4). The generated clock signal is brought out to T2

pin (P1.0).

Timer 2 is programmed for the clock-out mode as follows:

•

Set T2OE bit in T2MOD register.

Clear C/T2 bit in T2CON register.

Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L

registers.

•

Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the

reload value or different depending on the application.

•

To start the timer, set TR2 run control bit in T2CON register.

It is possible to use Timer 2 as a baud rate generator and a clock generator simulta-

neously. For this configuration, the baud rates and clock frequencies are not

independent since both functions use the values in the RCAP2H and RCAP2L registers.

Figure 28. Clock-out Mode

FT2

CLOCK

0

1

TR2

T2CON.2

TH2

(8-bit)

TL2

(8-bit)

CT/2

T2CON.1

OVERFLOW

RCAP2H

(8-bit)

RCAP2L

(8-bit)

1

0

T2

:2

C/T2

T2OE

T2MOD reg

T2CON reg

Timer 2

INTERRUPT

T2EX

EXF2

T2CON reg

EXEN2

T2CON reg

58

T89C5115

4128A–8051–04/02

T89C5115

Registers

Table 37. T2CON Register

T2CON (S:C8h)

Timer 2 Control Register

7

6

5

4

3

2

1

0

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

Bit

Number

Mnemonic Description

Timer 2 overflow Flag

TF2 is not set if RCLK=1 or TCLK = 1.

Must be cleared by software.

Set by hardware on Timer 2 overflow.

7

6

TF2

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if

EXEN2=1.

Set to cause the CPU to vector to Timer 2 interrupt routine when Timer 2

interrupt is enabled.

EXF2

Must be cleared by software.

Receive Clock bit

5

4

RCLK

TCLK

Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as receive clock for serial port in mode 1 or 3.

Transmit Clock bit

Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use Timer 2 overflow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable bit

Clear to ignore events on T2EX pin for Timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is

detected, if Timer 2 is not used to clock the serial port.

3

EXEN2

Timer 2 Run control bit

Clear to turn off Timer 2.

Set to turn on Timer 2.

2

1

TR2

Timer/Counter 2 select bit

Clear for timer operation (input from internal clock system: F_OSC).

Set for counter operation (input from T2 input pin).

C/T2#

Timer 2 Capture/Reload bit

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on

Timer 2 overflow.

Clear to auto-reload on Timer 2 overflows or negative transitions on T2EX pin if

EXEN2=1.

0

CP/RL2#

Set to capture on negative transitions on T2EX pin if EXEN2=1.

Reset Value = 0000 0000b

Bit addressable

59

4128A–8051–04/02

Table 38. T2MOD Register

T2MOD (S:C9h)

Timer 2 Mode Control Register

7

-

6

-

5

-

4

-

3

-

2

-

1

0

T2OE

DCEN

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 Output Enable bit

1

0

T2OE

DCEN

Clear to program P1.0/T2 as clock input or I/O port.

Set to program P1.0/T2 as clock output.

Down Counter Enable bit

Clear to disable Timer 2 as up/down counter.

Set to enable Timer 2 as up/down counter.

Reset Value = XXXX XX00b

Not bit addressable

Table 39. TH2 Register

TH2 (S:CDh)

Timer 2 High Byte Register

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

7-0

High Byte of Timer 2.

Reset Value = 0000 0000b

Not bit addressable

60

T89C5115

4128A–8051–04/02

T89C5115

Table 40. TL2 Register

TL2 (S:CCh)

Timer 2 Low Byte Register

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

7-0

Low Byte of Timer 2.

Reset Value = 0000 0000b

Not bit addressable

Table 41. RCAP2H Register

RCAP2H (S:CBh)

Timer 2 Reload/Capture High Byte Register

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

7-0

High Byte of Timer 2 Reload/Capture.

Reset Value = 0000 0000b

Not bit addressable

Table 42. RCAP2L Register

RCAP2L (S:CA^H)

Timer 2 Reload/Capture Low Byte Register

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

7-0

Low Byte of Timer 2 Reload/Capture.

Reset Value = 0000 0000b

Not bit addressable

61

4128A–8051–04/02

WatchDog Timer

T89C5115 contains a powerful programmable hardware WatchDog Timer (WDT) that

automatically resets the chip if it software fails to reset the WDT before the selected time

interval has elapsed. It permits large Time-Out ranking from 16ms to 2s

@Fosc = 12 MHz in X1 mode.

This WDT consists of a 14-bit counter plus a 7-bit programmable counter, a WatchDog

Timer reset register (WDTRST) and a WatchDog Timer programming (WDTPRG) regis-

ter. When exiting reset, the WDT is -by default- disable.

To enable the WDT, the user has to write the sequence 1EH and E1H into WDTRST

register no instruction in between. When the WatchDog Timer is enabled, it will incre-

ment every machine cycle while the oscillator is running and there is no way to disable

the WDT except through reset (either hardware reset or WDT overflow reset). When

WDT overflows, it will generate an output RESET pulse at the RST pin. The RESET

pulse duration is 96xT_OSC, where T_OSC=1/F_OSC. To make the best use of the WDT, it

should be serviced in those sections of code that will periodically be executed within the

time required to prevent a WDT reset.

Note:

When the WatchDog is enable it is impossible to change its period.

Figure 29. WatchDog Timer

CPU and Peripheral

Clock

Fwd

CLOCK

÷ 6

÷ PS

Decoder

Control

RESET

WR

WDTRST

Enable

14-bit COUNTER

7-bit COUNTER

Outputs

Fwd Clock

WDTPRG

-

0

-

1

2

RESET

62

T89C5115

4128A–8051–04/02

T89C5115

WatchDog Programming The three lower bits (S0, S1, S2) located into WDTPRG register permit to program the

WDT duration.

Table 43. Machine Cycle Count

S2

0

S1

0

S0

0

Machine Cycle Count

2¹⁴- 1

0

1

2¹⁵- 1

0

1

0

2¹⁶- 1

0

1

2¹⁷- 1

1

0

2¹⁸- 1

1

0

1

2¹⁹- 1

1

0

2²⁰- 1

1

2²¹- 1

To compute WD Time-Out, the following formula is applied:

F

wd

Svalue

------------------------------------------------------------------

FTime – Out=

14

12 × ((2 × 2

) – 1)

Note:

Svalue represents the decimal value of (S2 S1 S0)

The following table indicates the computed Time-Out value for Fosc_XTAL= 12 MHz in X1

mode

Table 44. Time-Out Computation

S2

0

S1

0

S0

0

Fosc = 12 MHz

16.38 ms

32.77 ms

65.54 ms

131.07 ms

262.14 ms

524.29 ms

1.05 sec

Fosc = 16 MHz

12.28 ms

24.57 ms

49.14 ms

98.28 ms

196.56 ms

393.12 ms

786.24 ms

1.57 s

Fosc = 20 MHz

9.82 ms

0

1

19.66 ms

39.32 ms

78.64 ms

157.28 ms

314.56 ms

629.12 ms

1.25 ms

0

1

0

1

0

1

0

1

0

1

2.10 sec

63

4128A–8051–04/02

WatchDog Timer

during Power-down

Mode and Idle

In Power-down mode the oscillator stops, which means the WDT also stops. While in

Power-down mode, the user does not need to service the WDT. There are 2 methods of

exiting Power-down mode: by a hardware reset or via a level activated external interrupt

which is enabled prior to entering Power-down mode. When Power-down is exited with

hardware reset, the WatchDog is disabled. Exiting Power-down with an interrupt is sig-

nificantly different. The interrupt shall be held low long enough for the oscillator to

stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the

WDT from resetting the device while the interrupt pin is held low, the WDT is not started

until the interrupt is pulled high. It is suggested that the WDT be reset during the inter-

rupt service for the interrupt used to exit Power-down.

To ensure that the WDT does not overflow within a few states of exiting powerdown, it is

best to reset the WDT just before entering powerdown.

In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting

T89C5115 while in Idle mode, the user should always set up a timer that will periodically

exit Idle, service the WDT, and re-enter Idle mode.

Register

Table 45. WDTPRG Register

WDTPRG (S:A7h)

WatchDog Timer Duration Programming Register

7

-

6

-

5

-

4

-

3

-

2

1

0

S2

S1

S0

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

WatchDog Timer Duration selection bit 2

Work in conjunction with bit 1 and bit 0.

S2

S1

S0

WatchDog Timer Duration selection bit 1

Work in conjunction with bit 2 and bit 0.

WatchDog Timer Duration selection bit 0

Work in conjunction with bit 1 and bit 2.

Reset Value = xxxx x000b

64

T89C5115

4128A–8051–04/02

T89C5115

Table 46. WDTRST Register

WDTRST (S:A6h Write only)

WatchDog Timer Enable Register

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

-

Bit

Number

Mnemonic Description

7

-

WatchDog Control Value

Reset Value = 1111 1111b

Note:

The WDRST register is used to reset/enable the WDT by writing 1EH then E1H in

sequence without instruction between these two sequences.

65

4128A–8051–04/02

Programmable

Counter Array (PCA)

The PCA provides more timing capabilities with less CPU intervention than the standard

timer/counters. Its advantages include reduced software overhead and improved accu-

racy. The PCA consists of a dedicated timer/counter which serves as the time base for

an array of five compare/capture modules. Its clock input can be programmed to count

any of the following signals:

•

PCA clock frequency/6 (see “clock” section)

PCA clock frequency/2

Timer 0 overflow

External input on ECI (P1.2)

Each compare/capture modules can be programmed in any one of the following modes:

•

rising and/or falling edge capture,

software timer,

high-speed output,

pulse width modulator.

When the compare/capture modules are programmed in capture mode, software timer,

or high speed output mode, an interrupt can be generated when the module executes its

function. All five modules plus the PCA timer overflow share one interrupt vector.

The PCA timer/counter and compare/capture modules share Port 1 for external I/Os.

These pins are listed below. If the port is not used for the PCA, it can still be used for

standard I/O.

PCA Component

16-bit Counter

External I/O Pin

P1.2/ECI

16-bit Module 0

16-bit Module 1

P1.3/CEX0

P1.4/CEX1

PCA Timer

The PCA timer is a common time base for all five modules (see Figure 9). The timer

count source is determined from the CPS1 and CPS0 bits in the CMOD SFR (see Table

8) and can be programmed to run at:

•

1/6 the PCA clock frequency.

1/2 the PCA clock frequency.

the Timer 0 overflow.

the input on the ECI pin (P1.2).

66

T89C5115

4128A–8051–04/02

T89C5115

Figure 30. PCA Timer/Counter

To PCA

modules

FPca/6

FPca/2

T0 OVF

P1.2

overflow

It

CH

CL

16 bit up/down counter

CMOD

0xD9

CIDL WDTE

CPS1 CPS0 ECF

Idle

CCON

0xD8

CF

CR

CCF1 CCF0

The CMOD register includes three additional bits associated with the PCA.

•

The CIDL bit which allows the PCA to stop during idle mode.

The WDTE bit which enables or disables the WatchDog function on module 4.

The ECF bit which when set causes an interrupt and the PCA overflow flag CF in

CCON register to be set when the PCA timer overflows.

The CCON register contains the run control bit for the PCA and the flags for the PCA

timer and each module.

•

The CR bit must be set to run the PCA. The PCA is shut off by clearing this bit.

The CF bit is set when the PCA counter overflows and an interrupt will be generated

if the ECF bit in CMOD register is set. The CF bit can only be cleared by software.

•

The CCF0:1 bits are the flags for the modules (CCF0 for module0...) and are set by

hardware when either a match or a capture occurs. These flags also can be cleared

by software.

67

4128A–8051–04/02

PCA Modules

Each one of the five compare/capture modules has six possible functions. It can

perform:

•

16-bit Capture, positive-edge triggered

16-bit Capture, negative-edge triggered

16-bit Capture, both positive and negative-edge triggered

16-bit Software Timer

16-bit High Speed Output

8-bit Pulse Width Modulator.

Each module in the PCA has a special function register associated with it (CCAPM0 for

module 0 ...). The CCAPM0:1 registers contain the bits that control the mode that each

module will operate in.

•

The ECCF bit enables the CCF flag in the CCON register to generate an interrupt

when a match or compare occurs in the associated module.

•

The PWM bit enables the pulse width modulation mode.

The TOG bit when set causes the CEX output associated with the module to toggle

when there is a match between the PCA counter and the module’s capture/compare

register.

•

The match bit MAT when set will cause the CCFn bit in the CCON register to be set

when there is a match between the PCA counter and the module’s capture/compare

register.

The two bits CAPN and CAPP in CCAPMn register determine the edge that a

capture input will be active on. The CAPN bit enables the negative edge, and the

CAPP bit enables the positive edge. If both bits are set both edges will be enabled.

The bit ECOM in CCAPM register when set enables the comparator function.

68

T89C5115

4128A–8051–04/02

T89C5115

PCA Interrupt

Figure 31. PCA Interrupt System

CCON

0xD8

CF

CR

CCF1 CCF0

PCA Timer/Counter

Module 0

Module 1

To Interrupt

ECF

CMOD.0

EA

IEN0.7

EC

IEN0.6

ECCFn

CCAPMn.0

PCA Capture Mode

To use one of the PCA modules in capture mode either one or both of the CCAPM bits

CAPN and CAPP for that module must be set. The external CEX input for the module

(on port 1) is sampled for a transition. When a valid transition occurs the PCA hardware

loads the value of the PCA counter registers (CH and CL) into the module’s capture reg-

isters (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the

ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated.

Figure 32. PCA Capture Mode

PCA Counter

CH

CL

(8bits) (8bits)

CEXn

n = 0, 1

CCAPnL

CCAPnH

PCA

Interrupt

Request

CCFn

-

CCON Reg

0CAPPn CAPNn000

ECCFn

0

7

CCAPMn Register (n = 0, 1)

69

4128A–8051–04/02

16-bit Software Timer

Mode

The PCA modules can be used as software timers by setting both the ECOM and MAT

bits in the modules CCAPMn register. The PCA timer will be compared to the module’s

capture registers and when a match occurs an interrupt will occur if the CCFn (CCON

SFR) and the ECCFn (CCAPMn SFR) bits for the module are both set.

Figure 33. PCA 16-bit Software Timer and High Speed Output Mode

PCA Counter

Compare/Capture Module

CCAPnH

(8 bits)

CCAPnL

(8 bits)

CH

CL

(8 bits)

Toggle

Match

16-Bit Comparator

CEXn

PCA

Interrupt

Request

Enable

CCFn

CCON reg

-

ECOMn0 0MATn TOGn0 ECCFn

0

7

CCAPMn Register

(n = 0, 1)

“0”

Reset

Write to

For software Timer mode, set ECOMn and MATn.

For high speed output mode, set ECOMn, MATn and TOGn.

“1”

CCAPnL

Write to CCAPnH

70

T89C5115

4128A–8051–04/02

T89C5115

High Speed Output Mode In this mode the CEX output (on port 1) associated with the PCA module will toggle

each time a match occurs between the PCA counter and the module’s capture registers.

To activate this mode the TOG, MAT, and ECOM bits in the module’s CCAPMn SFR

must be set.

Figure 34. PCA High Speed Output Mode

CCON

CF

CR

CCF1 CCF0

0xD8

Write to

CCAPnH Reset

PCA IT

Write to

CCAPnL

CCAPnH

CCAPnL

“0”

“1”

Enable

Match

16 bit comparator

CEXn

CH

CL

PCA counter/timer

CCAPMn, n = 0 to 1

0xDA to 0xDE

ECOMnCAPPn CAPNn MATn TOGn PWMn ECCFn

Pulse Width Modulator

Mode

All the PCA modules can be used as PWM outputs. The output frequency depends on

the source for the PCA timer. All the modules will have the same output frequency

because they all share the PCA timer. The duty cycle of each module is independently

variable using the module’s capture register CCAPLn. When the value of the PCA CL

SFR is less than the value in the module’s CCAPLn SFR the output will be low, when it

is equal to or greater than it, the output will be high. When CL overflows from FF to 00,

CCAPLn is reloaded with the value in CCAPHn. the allows the PWM to be updated with-

out glitches. The PWM and ECOM bits in the module’s CCAPMn register must be set to

enable the PWM mode.

71

4128A–8051–04/02

Figure 35. PCA PWM Mode

CCAPnH

CCAPnL

CL rolls over from FFh TO 00h loads

CCAPnH contents into CCAPnL

“0”

CL < CCAPnL

8-Bit

Comparator

CEX

CL (8 bits)

CL >= CCAPnL

“1”

ECOMn

CCAPMn.6

PWMn

CCAPMn.1

72

T89C5115

4128A–8051–04/02

T89C5115

PCA Registers

Table 47. CMOD Register

CMOD (S:D9h)

PCA Counter Mode Register

7

6

5

4

3

2

1

0

CIDL

WDTE

-

CPS1

CPS0

ECF

Bit

Number

Mnemonic Description

PCA Counter Idle Control bit

Clear to let the PCA run during Idle mode.

Set to stop the PCA when Idle mode is invoked.

7

6

CIDL

WatchDog Timer Enable

Clear to disable WatchDog Timer function on PCA Module 4,

Set to enable it.

WDTE

Reserved

5

4

3

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

EWC Count Pulse Select bits

CPS1 CPS0 Clock Source

0

1

0

1

0

1

Internal Clock, FPca/6

Internal Clock, FPca/2

Timer 0 overflow

External clock at ECI/P1.2 pin (Max. Rate = FPca/4)

2

CPS1

1

0

CPS0

ECF

Enable PCA Counter Overflow Interrupt bit

Clear to disable CF bit in CCON register to generate an interrupt.

Set to enable CF bit in CCON register to generate an interrupt.

Reset Value = 00XX X000b

73

4128A–8051–04/02

Table 48. CCON Register

CCON (S:D8h)

PCA Counter Control Register

7

6

5

-

4

-

3

-

2

-

1

0

CF

CR

CCF1

CCF0

Bit

Number

Mnemonic Description

PCA Timer/Counter Overflow flag

Set by hardware when the PCA Timer/Counter rolls over. This generates a PCA

interrupt request if the ECF bit in CMOD register is set.

Must be cleared by software.

7

CF

PCA Timer/Counter Run Control bit

Clear to turn the PCA Timer/Counter off.

Set to turn the PCA Timer/Counter on.

6

CR

-

Reserved

5-2

The value read from these bist are indeterminate. Do not set these bits.

PCA Module 1 Compare/Capture flag

Set by hardware when a match or capture occurs. This generates a PCA

interrupt request if the ECCF 1 bit in CCAPM 1 register is set.

Must be cleared by software.

1

0

CCF1

CCF0

PCA Module 0 Compare/Capture flag

Set by hardware when a match or capture occurs. This generates a PCA

interrupt request if the ECCF 0 bit in CCAPM 0 register is set.

Must be cleared by software.

Reset Value = 00xx xx00b

74

T89C5115

4128A–8051–04/02

T89C5115

Table 49. CCAPnH Registers

CCAP0H (S:FAh)

CCAP1H (S:FBh)

PCA High Byte Compare/Capture Module n Register (n=0..1)

7

6

5

4

3

2

1

0

CCAPnH 7 CCAPnH 6 CCAPnH 5 CCAPnH 4 CCAPnH 3 CCAPnH 2 CCAPnH 1 CCAPnH 0

Bit

Number

Mnemonic Description

CCAPnH

7:0

High byte of EWC-PCA comparison or capture values

7:0

Reset Value = 0000 0000b

Table 50. CCAPnL Registers

CCAP0L (S:EAh)

CCAP1L (S:EBh)

PCA Low Byte Compare/Capture Module n Register (n=0..1)

7

6

5

4

3

2

1

0

CCAPnL 7 CCAPnL 6 CCAPnL 5 CCAPnL 4 CCAPnL 3 CCAPnL 2 CCAPnL 1 CCAPnL 0

Bit

Number

Mnemonic Description

CCAPnL

7:0

Low byte of EWC-PCA comparison or capture values

Reset Value = 0000 0000b

75

4128A–8051–04/02

Table 51. CCAPMn Registers

CCAPM0 (S:DAh)

CCAPM1 (S:DBh)

PCA Compare/Capture Module n Mode registers (n=0..1)

7

-

6

5

4

3

2

1

0

ECOMn

CAPPn

CAPNn

MATn

TOGn

PWMn

ECCFn

Bit

Number

Mnemonic Description

Reserved

7

6

-

The Value read from this bit is indeterminate. Do not set this bit.

Enable Compare Mode Module x bit

Clear to disable the Compare function.

ECOMn Set to enable the Compare function.

The Compare function is used to implement the software Timer, the high-speed

output, the Pulse Width Modulator (PWM) and the WatchDog Timer (WDT).

Capture Mode (Positive) Module x bit

5

4

3

CAPPn

CAPNn

MATn

Clear to disable the Capture function triggered by a positive edge on CEXx pin.

Set to enable the Capture function triggered by a positive edge on CEXx pin

Capture Mode (Negative) Module x bit

Clear to disable the Capture function triggered by a negative edge on CEXx pin.

Set to enable the Capture function triggered by a negative edge on CEXx pin.

Match Module x bit

Set when a match of the PCA Counter with the Compare/Capture register sets

CCFx bit in CCON register, flagging an interrupt.

Toggle Module x bit

The toggle mode is configured by setting ECOMx, MATx and TOGx bits.

Set when a match of the PCA Counter with the Compare/Capture register

toggles the CEXx pin.

2

TOGn

Pulse Width Modulation Module x Mode bit

Set to configure the module x as an 8-bit Pulse Width Modulator with output

waveform on CEXx pin.

1

0

PWMn

Enable CCFx Interrupt bit

Clear to disable CCFx bit in CCON register to generate an interrupt request.

Set to enable CCFx bit in CCON register to generate an interrupt request.

ECCFn

Reset Value = X000 0000b

76

T89C5115

4128A–8051–04/02

T89C5115

Table 52. CH Register

CH (S:F9h)

PCA Counter Register High Value

7

6

5

4

3

2

1

0

CH 7

CH 6

CH 5

CH 4

CH 3

CH 2

CH 1

CH 0

Bit

Number

Mnemonic Description

7:0

CH 7:0 High byte of Timer/Counter

Reset Value = 0000 00000b

Table 53. CL Register

CL (S:E9h)

PCA counter Register Low Value

7

6

5

4

3

2

1

0

CL 7

CL 6

CL 5

CL 4

CL 3

CL 2

CL 1

CL 0

Bit

Number

Mnemonic Description

7:0

CL0 7:0 Low byte of Timer/Counter

Reset Value = 0000 00000b

77

4128A–8051–04/02

Analog-to-Digital

Converter (ADC)

This section describes the on-chip 10-bit analog-to-digital converter of the T89C5115.

Eight ADC channels are available for sampling of the external sources AN0 to AN7. An

analog multiplexer allows the single ADC converter to select one from the 8 ADC chan-

nels as ADC input voltage (ADCIN). ADCIN is converted by the 10 bit-cascaded

potentiometric ADC.

Two kind of conversion are available:

- Standard conversion (8 bits).

- Precision conversion (10 bits).

For the precision conversion, set bit PSIDLE in ADCON register and start conversion.

The device is in a pseudo-idle mode, the CPU does not run but the peripherals are

always running. This mode allows digital noise to be as low as possible, to ensure high

precision conversion.

For this mode it is necessary to work with end of conversion interrupt, which is the only

way to wake the device up.

If another interrupt occurs during the precision conversion, it will be treated only after

this conversion is ended.

Features

•

8 channels with multiplexed inputs

10-bit cascaded potentiometric ADC

Conversion time 16 micro-seconds (typ.)

Zero Error (offset) ± 2 LSB max

Positive External Reference Voltage Range (VREF) 2.4V to 3.0V (typ.)

ADCIN Range 0V to 3V

Integral non-linearity typical 1 LSB, max. 2 LSB

Differential non-linearity typical 0.5 LSB, max. 1 LSB

Conversion Complete Flag or Conversion Complete Interrupt

Selectable ADC Clock

ADC Port1 I/O Functions Port 1 pins are general I/O that are shared with the ADC channels. The channel select

bit in ADCF register define which ADC channel/port1 pin will be used as ADCIN. The

remaining ADC channels/port1 pins can be used as general-purpose I/O or as the alter-

nate function that is available.

A conversion launched on a channel which are not selected on ADCF register will not

have any effect.

78

T89C5115

4128A–8051–04/02

T89C5115

Figure 36. ADC Description

ADCON.5

ADCON.3

ADEN

ADSST

ADCON.4

ADC

Interrupt

Request

ADEOC

ADC

CLOCK

CONTROL

EADC

IEN1.1

AN0/P1.0

AN1/P1.1

AN2/P1.2

AN3/P1.3

AN4/P1.4

AN5/P1.5

AN6/P1.6

AN7/P1.7

000

001

010

011

100

101

110

111

8

2

ADCIN

ADDH

ADDL

+

-

SAR

AVSS

Sample and Hold

10

R/2R DAC

SCH2

SCH1

SCH0

VAREF VAGND

ADCON.2 ADCON.1 ADCON.0

Figure 37 shows the timing diagram of a complete conversion. For simplicity, the figure

depicts the waveforms in idealized form and do not provide precise timing information.

For ADC characteristics and timing parameters refer to the Section “AC Characteristics”

of the T89C5115 datasheet.

Figure 37. Timing Diagram

CLK

ADEN

T_SETUP

ADSST

ADEOC

T_CONV

Note:

Tsetup min = 4 us

Tconv=11 clock ADC = 1sample and hold + 10 bit conversion

The user must ensure that 4 us minimum time between setting ADEN and the start of the first conversion.

ADC Converter

Operation

A start of single A/D conversion is triggered by setting bit ADSST (ADCON.3).

After completion of the A/D conversion, the ADSST bit is cleared by hardware.

The end-of-conversion flag ADEOC (ADCON.4) is set when the value of conversion is

available in ADDH and ADDL, it must be cleared by software. If the bit EADC (IEN1.1) is

set, an interrupt occur when flag ADEOC is set (see Figure 39). Clear this flag for re-

arming the interrupt.

The bits SCH0 to SCH2 in ADCON register are used for the analog input channel

selection.

79

4128A–8051–04/02

Table 54. Selected Analog Input

SCH2

SCH1

SCH0

Selected Analog input

0

1

0

1

0

1

0

1

0

1

0

1

0

1

AN0

AN1

AN2

AN3

AN4

AN5

AN6

AN7

Voltage Conversion

When the ADCIN is equals to VAREF the ADC converts the signal to 3FFh (full scale). If

the input voltage equals VAGND, the ADC converts it to 000h. Input voltage between

VAREF and VAGND are a straight-line linear conversion. All other voltages will result in

3FFh if greater than VAREF and 000h if less than VAGND.

Note that ADCIN should not exceed VAREF absolute maximum range! (see section

“AC-DC”)

Clock Selection

The ADC clock is the same as CPU.

The maximum clock frequency for ADC is 700 KHz. A prescaler is featured (ADCCLK)

to generate the ADC clock from the oscillator frequency.

Figure 38. A/D Converter Clock

ADC Clock

CPU

CLOCK

Prescaler ADCLK

÷ 2

A/D

Converter

CPU Core Clock Symbol

ADC Standby Mode

When the ADC is not used, it is possible to set it in standby mode by clearing bit ADEN

in ADCON register. In this mode its power dissipation is about 1 uW.

80

T89C5115

4128A–8051–04/02

T89C5115

IT ADC Management

An interrupt end-of-conversion will occurs when the bit ADEOC is activated and the bit

EADC is set. For re-arming the interrupt the bit ADEOC must be cleared by software.

Figure 39. ADC interrupt structure

ADCI

ADEOC

ADCON.2

EADC

IEN1.1

Routine Examples

1. Configure P1.2 and P1.3 in ADC channels

// configure channel P1.2 and P1.3 for ADC

ADCF = 0Ch

// Enable the ADC

ADCON = 20h

2. Start a standard conversion

// The variable "channel" contains the channel to convert

// The variable "value_converted" is an unsigned int

// Clear the field SCH[2:0]

ADCON &= F8h

// Select channel

ADCON |= channel

// Start conversion in standard mode

ADCON |= 08h

// Wait flag End of conversion

while((ADCON & 01h)!= 01h)

// Clear the End of conversion flag

ADCON &= EFh

// read the value

value_converted = (ADDH << 2)+(ADDL)

3. Start a precision conversion (need interrupt ADC)

// The variable "channel" contains the channel to convert

// Enable ADC

EADC = 1

// clear the field SCH[2:0]

ADCON &= F8h

// Select the channel

ADCON |= channel

// Start conversion in precision mode

ADCON |= 48h

Note:

to enable the ADC interrupt:

EA = 1

81

4128A–8051–04/02

Registers

Table 55. ADCF Register

ADCF (S:F6h)

ADC Configuration

7

6

5

4

3

2

1

0

CH 7

CH 6

CH 5

CH 4

CH 3

CH 2

CH 1

CH 0

Bit

Number

Mnemonic Description

Channel Configuration

7-0

CH 0:7

Set to use P1.x as ADC input.

Clear to use P1.x as standart I/O port.

Reset Value = 0000 0000b

Table 56. ADCON Register

ADCON (S:F3h)

ADC Control Register

7

-

6

5

4

3

2

1

0

PSIDLE

ADEN

ADEOC

ADSST

SCH2

SCH1

SCH0

Bit

Number

Mnemonic Description

7

-

Pseudo Idle mode (best precision)

PSIDLE Set to put in idle mode during conversion

Clear to convert without idle mode.

6

Enable/Standby Mode

5

4

ADEN

Set to enable ADC

Clear for Standby mode (power dissipation 1 uW).

End Of Conversion

Set by hardware when ADC result is ready to be read. This flag can generate an

interrupt.

ADEOC

Must be cleared by software.

Start and Status

3

ADSST

SCH2:0

Set to start an A/D conversion.

Cleared by hardware after completion of the conversion

Selection of channel to convert

see Table 54

2-0

Reset Value = X000 0000b

82

T89C5115

4128A–8051–04/02

T89C5115

Table 57. ADCLK Register

ADCLK (S:F2h)

ADC Clock Prescaler

7

-

6

-

5

-

4

3

2

1

0

PRS 4

PRS 3

PRS 2

PRS 1

PRS 0

Bit

Number

Mnemonic Description

Reserved

7-5

4-0

-

The value read from these bits are indeterminate. Do not set these bits.

Clock Prescaler

PRS4:0

f_ADC= fcpu clock/ (4 (or 2 in X2 mode)* (PRS +1))

Reset Value = XXX0 0000b

Table 58. ADDH Register

ADDH (S:F5h Read Only)

ADC Data High byte register

7

6

5

4

3

2

1

0

ADAT 9

ADAT 8

ADAT 7

ADAT 6

ADAT 5

ADAT 4

ADAT 3

ADAT 2

Bit

Number

Mnemonic Description

ADC result

ADAT9:2

7-0

bits 9-2

Reset Value = 00h

Table 59. ADDL Register

ADDL (S:F4h Read Only)

ADC Data Low byte register

7

-

6

-

5

-

4

-

3

-

2

-

1

0

ADAT 1

ADAT 0

Bit

Number

Mnemonic Description

Reserved

7-2

1-0

-

The value read from these bits are indeterminate. Do not set these bits.

ADC result

bits 1-0

ADAT1:0

Reset Value = 00h

83

4128A–8051–04/02

Interrupt System

Introduction

The T89C5115 has a total of 8 interrupt vectors: two external interrupts (INT0 and

INT1), three timer interrupts (timers 0, 1 and 2), a serial port interrupt, a PCAand an

ADC. These interrupts are shown below.

Figure 40. Interrupt Control System

Highest

Priority

00

01

External

Interrupt 0

Interrupts

INT0#

10

11

EX0

IEN0.0

00

01

10

11

Timer 0

External

ET0

IEN0.1

00

01

10

11

INT1#

Interrupt 1

EX1

IEN0.2

00

01

10

11

Timer 1

ET1

IEN0.3

00

CEX0:1

PCA

01

10

11

EC

IEN0.6

00

TxD

01

10

11

UART

RxD

ES

IEN0.4

00

01

10

11

Timer 2

ET2

IEN0.5

00

01

10

11

ADC

AIN1:0

EA

IEN0.7

EADC

IEN1.1

IPH/L

Lowest Priority Interrupts

Priority Enable

Interrupt Enable

Each of the interrupt sources can be individually enabled or disabled by setting or clear-

ing a bit in the Interrupt Enable register. This register also contains a global disable bit

which must be cleared to disable all the interrupts at the same time.

Each interrupt source can also be individually programmed to one of four priority levels

by setting or clearing a bit in the Interrupt Priority registers. The Table below shows the

bit values and priority levels associated with each combination.

84

T89C5115

4128A–8051–04/02

T89C5115

Table 60. Priority Level Bit Values

IPH.x

IPL.x

Interrupt Level Priority

0

1

0

1

0

1

0 (Lowest)

1

2

3 (Highest)

A low-priority interrupt can be interrupted by a high priority interrupt but not by another

low-priority interrupt. A high-priority interrupt cannot be interrupted by any other interrupt

source.

If two interrupt requests of different priority levels are received simultaneously, the

request of the higher priority level is serviced. If interrupt requests of the same priority

level are received simultaneously, an internal polling sequence determines which

request is serviced. Thus within each priority level there is a second priority structure

determined by the polling sequence, see Table 61.

Table 61. Interrupt Priority Within Level

Interrupt Name

external interrupt (INT0)

Timer0 (TF0)

Interrupt Address Vector

Priority Number

0003h

000Bh

0013h

001Bh

0033h

0023h

002Bh

0043h

1

2

3

4

5

6

7

8

external interrupt (INT1)

Timer1 (TF1)

PCA (CF or CCFn)

UART (RI or TI)

Timer2 (TF2)

ADC (ADCI)

85

4128A–8051–04/02

Registers

Table 62. IEN0 Register

IEN0 (S:A8h)

Interrupt Enable Register

7

6

5

4

3

2

1

0

EA

EC

ET2

ES

ET1

EX1

ET0

EX0

Bit

Number

Mnemonic Description

Enable All interrupt bit

Clear to disable all interrupts.

Set to enable all interrupts.

7

EA

If EA=1, each interrupt source is individually enabled or disabled by setting or

clearing its interrupt enable bit.

PCA Interrupt Enable

6

5

4

3

2

1

0

EC

ET2

ES

Clear to disable the PCA interrupt.

Set to enable the PCA interrupt.

Timer 2 overflow interrupt Enable bit

Clear to disable Timer 2 overflow interrupt.

Set to enable Timer 2 overflow interrupt.

Serial port Enable bit

Clear to disable serial port interrupt.

Set to enable serial port interrupt.

Timer 1 overflow interrupt Enable bit

Clear to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

ET1

EX1

ET0

EX0

External interrupt 1 Enable bit

Clear to disable external interrupt 1.

Set to enable external interrupt 1.

Timer 0 overflow interrupt Enable bit

Clear to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

External interrupt 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

Reset Value = 0000 0000b

bit addressable

86

T89C5115

4128A–8051–04/02

T89C5115

Table 63. IEN1 Register

IEN1 (S:E8h)

Interrupt Enable Register

7

-

6

-

5

-

4

-

3

-

2

-

1

0

-

EADC

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

ADC Interrupt Enable bit

1

0

EADC

-

Clear to disable the ADC interrupt.

Set to enable the ADC interrupt.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reset Value = xxxx xx0xb

bit addressable

87

4128A–8051–04/02

Table 64. IPL0 Register

IPL0 (S:B8h)

Interrupt Enable Register

7

-

6

5

4

3

2

1

0

PPC

PT2

PS

PT1

PX1

PT0

PX0

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

PCA Interrupt Priority bit

Refer to PPCH for priority level.

PPC

PT2

PS

Timer 2 overflow interrupt Priority bit

Refer to PT2H for priority level.

Serial port Priority bit

Refer to PSH for priority level.

Timer 1 overflow interrupt Priority bit

Refer to PT1H for priority level.

PT1

PX1

PT0

PX0

External interrupt 1 Priority bit

Refer to PX1H for priority level.

Timer 0 overflow interrupt Priority bit

Refer to PT0H for priority level.

External interrupt 0 Priority bit

Refer to PX0H for priority level.

Reset Value = X000 0000b

bit addressable

88

T89C5115

4128A–8051–04/02

T89C5115

Table 65. IPL1 Register

IPL1 (S:F8h)

Interrupt Priority Low Register 1

7

-

6

-

5

-

4

-

3

-

2

-

1

0

-

PADCL

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

ADC Interrupt Priority level less significant bit.

Refer to PSPIH for priority level.

PADCL

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reset Value = xxxx xx0xb

bit addressable

89

4128A–8051–04/02

Table 66. IPL0 Register

IPH0 (B7h)

Interrupt High Priority Register

7

-

6

5

4

3

2

1

0

PPCH

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

Bit

Number

Mnemonic Description

Reserved

7

-

The value read from this bit is indeterminate. Do not set this bit.

PCA Interrupt Priority level most significant bit

PPCH PPC Priority level

0

1

0

1

0

1

Lowest

6

PPCH

PT2H

PSH

Highest priority

Timer 2 overflow interrupt High Priority bit

PT2H PT2 Priority Level

0

1

0

1

0

1

Lowest

5

4

3

2

1

0

Highest

Serial port High Priority bit

PSH PS

0

1

Priority Level

Lowest

0

1

0

1

Highest

Timer 1 overflow interrupt High Priority bit

PT1H PT1 Priority Level

0

1

0

1

0

1

Lowest

PT1H

PX1H

PT0H

PX0H

Highest

External interrupt 1 High Priority bit

PX1H PX1 Priority Level

0

1

0

1

0

1

Lowest

Highest

Timer 0 overflow interrupt High Priority bit

PT0H PT0 Priority Level

0

1

0

1

0

1

Lowest

Highest

External interrupt 0 high priority bit

PX0H PX0 Priority Level

0

1

0

1

0

1

Lowest

Highest

Reset Value = X000 0000b

90

T89C5115

4128A–8051–04/02

T89C5115

Table 67. IPH1 Register

IPH1 (S:F7h)

Interrupt high priority Register 1

7

-

6

-

5

-

4

-

3

-

2

-

1

0

-

PADCH

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

ADC Interrupt Priority level most significant bit

PADCH PADCL

Priority level

Lowest

0

1

0

1

0

1

PADCH

Highest

Reserved

The value read from this bit is indeterminate. Do not set this bit.

0

-

Reset Value = xxxx xx0xb

91

4128A–8051–04/02

Electrical Characteristics

Absolute Maximum Ratings

Note:

Stresses at or above those listed under “Absolute

Maximum Ratings” may cause permanent damage to

the device. This is a stress rating only and functional

operation of the device at these or any other condi-

tions above those indicated in the operational

sections of this specification is not implied. Exposure

to absolute maximum rating conditions may affect

device reliability.

Ambiant Temperature Under Bias:

I = industrial ....................................................... -40°C to 85°C

Storage Temperature ................................... -65°C to + 150°C

Voltage on V_CCfrom V_SS......................................-0.5V to + 6V

Voltage on Any Pin from V_SS....................-0.5V to V_CC+ 0.2 V

Power Dissipation ............................................................. 1 W

The power dissipation is based on the maximum

allowable die temperature and the thermal resistance

of the package.

DC Parameters for Standard Voltage

TA = -40°C to +85°C; V_SS= 0V; V_CC= 5V 10%; F = 0 to 40 MHz

Table 68. DC Parameters in Standard Voltage

Symbol

Parameter

Min

Typ⁽⁵⁾

Max

Unit Test Conditions

V_IL

Input Low Voltage

-0.5

0.2 Vcc - 0.1

V_CC+ 0.5

V

V_IH

Input High Voltage except XTAL1, RST

Input High Voltage, XTAL1, RST

0.2 V_CC+ 0.9

0.7 V_CC

V_IH1

0.3

0.45

1.0

V

I

_OL= 100 µA

_OL= 1.6 mA

V_OL

Output Low Voltage, ports 1, 2, 3 and 4⁽⁶⁾

I_OL= 3.5 mA

I_OH= -10 µA

I_OH= -30 µA

I_OH= -60 µA

V_CC= 5V 10%

V

_CC- 0.3

V

V_OH

Output High Voltage, ports 1, 2, 3, 4

V_CC- 0.7

V_CC- 1.5

R_RST

I_IL

RST Pulldown Resistor

50

90

200

-50

10

kΩ

µA

Logical 0 Input Current ports 1, 2, 3 and 4

Input Leakage Current

Vin = 0.45V

I_LI

0.45V < Vin < V_CC

Logical 1 to 0 Transition Current, ports 1, 2, 3

and 4

I_TL

-650

µA

Vin = 2.0V

Fc = 1 MHz

T^A= 25°C

C_IO

I_PD

I_CC

Capacitance of I/O Buffer

10

pF

Power-down Current

Power Supply Current

160

350

µA

4.5V < V_CC< 5.5V⁽³⁾

I_CCOP= 0.7 Freq (MHz) + 3 mA

I_CCIDLE= 0.6 Freq (MHz) + 2 mA

Vcc = SS^{(1) (2)}

Notes: 1. Operating I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns (see Figure 44.), V_IL

=

V

_SS+ 0.5V, V_IH= V_CC- 0.5V; XTAL2 N.C.; RST = V_CC. I_CCwould be slightly higher if a crystal oscillator used (see Figure 41.).

2. Idle I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns, V_IL= V_SS+ 0.5V, V_IH= V_CC

0.5V; XTAL2 N.C; Port 0 = V_CC; RST = V_SS(see Figure 42.).

-

3. Power-down I_CCis measured with all output pins disconnected; XTAL2 NC.; RST = V_SS(see Figure 43.). In addition, the

WDT must be inactive and the POF flag must be set.

4. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature.

92

T89C5115

4128A–8051–04/02

T89C5115

5. Under steady state (non-transient) conditions, I_OLmust be externally limited as fol-

lows:

Maximum I_OLper port pin: 10 mA

Maximum I_OLper 8-bit port:

Ports 1, 2 and 3: 15 mA

Maximum total I_OLfor all output pins: 71 mA

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are

not guaranteed to sink current greater than the listed test conditions.

Figure 41. I_CCTest Condition, Active Mode

V_CC

I_CC

V_CC

RST

(NC)

CLOCK

SIGNAL

XTAL2

XTAL1

V_SS

All other pins are disconnected.

Figure 42. I_CCTest Condition, Idle Mode

V_CC

I_CC

V_CC

RST

XTAL2

XTAL1

V_SS

(NC)

CLOCK

SIGNAL

All other pins are disconnected.

Figure 43. I_CCTest Condition, Power-down Mode

V_CC

I_CC

V_CC

RST

(NC)

XTAL2

XTAL1

V_SS

All other pins are disconnected

93

4128A–8051–04/02

Figure 44. Clock Signal Waveform for I_CCTests in Active and Idle Modes

V_CC-0.5V

0.7V_CC

0.2V_CC-0.1

0.45V

T_CLCH

T_CHCL

T_CLCH= T_CHCL= 5ns.

DC Parameters for A/D

Converter

Table 69. DC Parameters for AD Converter in Precision conversion

Symbol Parameter

Min

Vss - 0.2

12

Typ⁽¹⁾

Max

Vref + 0.6

24

Unit Test Conditions

AVin

Rref

Vref

Cai

Analog input voltage

V

Resistance between Vref and Vss

Reference voltage

16

kΩ

2.40

3.00

V

Analog input Capacitance

Integral non linearity

Differential non linearity

Offset error

60

1

pF During sampling

INL

2

1

2

lsb

DNL

OE

0.5

-2

Note:

1. Typicals are based on a limited number of samples and are not guaranteed.

94

T89C5115

4128A–8051–04/02

T89C5115

AC Parameters

Explanation of the AC

Symbols

Each timing symbol has 5 characters. The first character is always a “T” (stands for

time). The other characters, depending on their positions, stand for the name of a signal

or the logical status of that signal. The following is a list of all the characters and what

they stand for.

Example: T_AVLL= Time for Address Valid to ALE Low.

T

_LLPL= Time for ALE Low to PSEN Low.

T^A= -40°C to +85°C; V_SS= 0V; V_CC= 5V 10%; F = 0 to 40 MHz.

T^A= -40°C to +85°C; V_SS= 0V; V_CC= 5V 10%.

( Load Capacitance for all outputs = 60 pF.)

Table 70 and Table 74 give the description of each AC symbols.

Table 71, Table 72 and Table 73 give for each range the AC parameter.

Table 72 gives the frequency derating formula of the AC parameter for each speed

range description. To calculate each AC symbols. Take the x value and use this value in

the formula.

Example: T_LLIVand 20 MHz, Standard clock.

x = 30 ns

T = 50 ns

T_CCIV= 4T - x = 170 ns

Serial Port Timing – Shift

Register Mode

Table 70. Symbol Description (F = 40 MHz)

Symbol

T_XLXL

Parameter

Serial port clock cycle time

T_QVHX

T_XHQX

T_XHDX

T_XHDV

Output data set-up to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

Table 71. AC Parameters for a Fix Clock (F = 40 MHz)

Symbol

T_XLXL

Min

300

200

30

Max

Units

ns

T_QVHX

T_XHQX

T_XHDX

T_XHDV

ns

0

ns

117

ns

95

4128A–8051–04/02

Table 72. AC Parameters for a Variable Clock

Standard

Clock

X parameter

for -M range

Symbol

T_XLXL

Type

Min

Max

X2 Clock

6 T

Units

ns

12 T

T_QVHX

T_XHQX

T_XHDX

T_XHDV

10 T - x

2 T - x

x

5 T - x

T - x

50

20

0

ns

x

ns

10 T - x

5 T- x

133

ns

Shift Register Timing Waveforms

0

1

2

3

4

5

6

7

8

INSTRUCTION

ALE

T_XLXL

CLOCK

T_XHQX

1

T_QVXH

0

2

3

4

5

6

7

OUTPUT DATA

T_XHDX

SET TI

T_XHDV

WRITE to SBUF

INPUT DATA

VALID

SET RI

CLEAR RI

External Clock Drive

Table 73. AC Parameters

Characteristics (XTAL1)

Symbol

T_CLCL

Parameter

Min

25

5

Max

Units

Oscillator Period

High Time

ns

%

T_CHCX

T_CLCX

T_CLCH

T_CHCL

Low Time

5

Rise Time

5

Fall Time

T_CHCX/T_CLCX

Cyclic ratio in X2 mode

40

60

External Clock Drive

Waveforms

V_CC-0.5V

0.45V

0.7V_CC

0.2V_CC-0.1

T_CHCX

T_CLCH

T_CLCX

T_CHCL

T_CLCL

AC Testing Input/Output

Waveforms

V

_CC-0.5V

0.2 V_CC+ 0.9

0.2 V_CC- 0.1

INPUT/OUTPUT

0.45 V

AC inputs during testing are driven at V_CC- 0.5 for a logic “1” and 0.45V for a logic “0”.

Timing measurement are made at V_IHmin for a logic “1” and V_ILmax for a logic “0”.

96

T89C5115

4128A–8051–04/02

T89C5115

Float Waveforms

FLOAT

V_LOAD

V_OH- 0.1 V

V_OL+ 0.1 V

V_LOAD+ 0.1 V

V_LOAD- 0.1 V

For timing purposes as port pin is no longer floating when a 100 mV change from load

voltage occurs and begins to float when a 100 mV change from the loaded V_OH/V_OLlevel

occurs. I_OL/I_OH

≥

20 mA.

Flash Memory

Table 74. Memory AC Timing

VDD = 5V ± 10% , TA = -40 to +85°C

Symbol

Parameter

Min

Typ

Max

Unit

T_BHBL

Flash Internal Busy (Programming) Time

10

ms

Figure 45. Flash Memory - Internal Busy Waveforms

FBUSY bit

T_BHBL

97

4128A–8051–04/02

Ordering Information

Table 75. Possible Order Entries

Temperature

Range

Max

Frequency

Memory Size Supply Voltage

Package

PLCC28

SOIC28

Packing

Stick

Part-Number

T89C5115-SISIM

T89C5115-TISIM

T89C5115-RATIM

16K

5V

Industrial

40 MHz

Stick

VQFP32

Tray

98

T89C5115

4128A–8051–04/02

T89C5115

Package Drawing

PLCC28

99

4128A–8051–04/02

Package Drawing

SOIC28

100

T89C5115

4128A–8051–04/02

T89C5115

Package Drawing

VQFP32

101

4128A–8051–04/02

T89C5115

Table of Contents

Features ................................................................................................. 1

Description ............................................................................................ 1

Block Diagram ....................................................................................... 2

Pin Configuration .................................................................................. 3

I/O Configurations................................................................................................. 6

Port Structure........................................................................................................ 6

Read-Modify-Write Instructions ............................................................................ 7

Quasi-bidirectional Port Operation........................................................................ 7

SFR Mapping ......................................................................................... 9

Clock .................................................................................................... 13

Description.......................................................................................................... 13

Register .............................................................................................................. 16

Power Management ............................................................................ 17

Introduction......................................................................................................... 17

Reset .................................................................................................................. 17

Reset Recommendation to Prevent Flash Corruption ........................................ 17

Idle Mode............................................................................................................ 18

Power-down Mode.............................................................................................. 18

Registers..............................................................................................................20

Data Memory ....................................................................................... 21

Internal Space..................................................................................................... 21

Dual Data Pointer ............................................................................................... 23

Registers............................................................................................................. 24

EEPROM Data Memory ....................................................................... 26

Write Data in the Column Latches...................................................................... 26

Programming ...................................................................................................... 26

Read Data........................................................................................................... 26

Examples............................................................................................................ 27

Registers............................................................................................................. 28

Program/Code Memory ...................................................................... 29

Flash Memory Architecture................................................................................. 29

Overview of FM0 Operations.............................................................................. 31

Registers............................................................................................................. 37

i

4128A–8051–04/02

In-System Programming (ISP) ........................................................... 38

Flash Programming and Erasure........................................................................ 38

Boot Process ...................................................................................................... 39

Application Programming Interface..................................................................... 40

XROW Bytes....................................................................................................... 40

Hardware Security Byte...................................................................................... 41

Serial I/O Port ...................................................................................... 42

Framing Error Detection .................................................................................... 42

Automatic Address Recognition.......................................................................... 43

Given Address .....................................................................................................44

Broadcast Address ............................................................................................. 44

Registers............................................................................................................. 45

Timers/Counters ................................................................................. 48

Timer/Counter Operations .................................................................................. 48

Timer 0................................................................................................................ 48

Timer 1.................................................................................................................51

Interrupt ...............................................................................................................52

Registers............................................................................................................. 53

Timer 2 ................................................................................................. 57

Auto-reload Mode ............................................................................................... 57

Programmable Clock-Output .............................................................................. 58

Registers............................................................................................................. 59

WatchDog Timer ................................................................................. 62

WatchDog Programming .....................................................................................63

WatchDog Timer during Power-down Mode and Idle ...................... 64

Register .............................................................................................................. 64

Programmable Counter Array (PCA) ................................................ 66

PCA Timer .......................................................................................................... 66

PCA Modules...................................................................................................... 68

PCA Interrupt...................................................................................................... 69

PCA Capture Mode............................................................................................. 69

16-bit Software Timer Mode ............................................................................... 70

High Speed Output Mode ................................................................................... 71

Pulse Width Modulator Mode.............................................................................. 71

PCA Registers .................................................................................................... 73

Analog-to-Digital Converter (ADC) .................................................... 78

Features.............................................................................................................. 78

ADC Port1 I/O Functions .................................................................................... 78

ADC Converter Operation................................................................................... 79

ii

T89C5115

4128A–8051–04/02

T89C5115

Voltage Conversion ............................................................................................ 80

Clock Selection................................................................................................... 80

ADC Standby Mode............................................................................................ 80

IT ADC Management...........................................................................................81

Routine Examples............................................................................................... 81

Registers..............................................................................................................82

Interrupt System ................................................................................. 84

Introduction......................................................................................................... 84

Registers............................................................................................................. 86

Electrical Characteristics ................................................................... 92

Absolute Maximum Ratings................................................................................ 92

DC Parameters for Standard Voltage ................................................................. 92

DC Parameters for A/D Converter ...................................................................... 94

AC Parameters ....................................................................................................95

Ordering Information .......................................................................... 98

Package Drawing................................................................................ 99

PLCC28 .............................................................................................................. 99

Package Drawing.............................................................................. 100

SOIC28............................................................................................................. 100

Package Drawing.............................................................................. 101

VQFP32 ............................................................................................................ 101

iii

4128A–8051–04/02

Atmel Headquarters

Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 487-2600

Memory

RF/Automotive

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

TEL (49) 71-31-67-0

FAX (49) 71-31-67-2340

Europe

Atmel Sarl

Microcontrollers

Route des Arsenaux 41

Case Postale 80

CH-1705 Fribourg

Switzerland

TEL (41) 26-426-5555

FAX (41) 26-426-5500

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

FAX 1(719) 540-1759

Biometrics/Imaging/Hi-Rel MPU/

High Speed Converters/RF Data-

com

La Chantrerie

BP 70602

44306 Nantes Cedex 3, France

TEL (33) 2-40-18-18-18

FAX (33) 2-40-18-19-60

Asia

Room 1219

Avenue de Rochepleine

BP 123

38521 Saint-Egreve Cedex, France

TEL (33) 4-76-58-30-00

FAX (33) 4-76-58-34-80

Chinachem Golden Plaza

77 Mody Road Tsimhatsui

East Kowloon

Hong Kong

TEL (852) 2721-9778

FAX (852) 2722-1369

ASIC/ASSP/Smart Cards

Zone Industrielle

13106 Rousset Cedex, France

TEL (33) 4-42-53-60-00

FAX (33) 4-42-53-60-01

Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

TEL (81) 3-3523-3551

FAX (81) 3-3523-7581

1150 East Cheyenne Mtn. Blvd.

Colorado Springs, CO 80906

TEL 1(719) 576-3300

FAX 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

TEL (44) 1355-803-000

FAX (44) 1355-242-743

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

ATMEL^®, is a registered trademarkof Atmel.

Other terms and product names may be the trademarks of others.

Printed on recycled paper.

4128A–8051–04/02

/xM


型号：	T89C5115-TISIM
厂家：	ATMEL
描述：	Low Pin Count 8-bit MCU with A/D Converter and 16-Kbytes of Flash Memory 低引脚数的8位微控制器与A / D转换器和闪存的16字节转换器闪存微控制器和处理器外围集成电路光电二极管时钟
文件：	总105页 (文件大小：1465K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

T89C5115-TISIM [ATMEL]

相关型号：

T89C5115_03

T89C5115_06

T89C5115_08

T89C5121

T89C5121-ICRIL

T89C5121-ICSIL

T89C51AC2

T89C51AC2(PLCC44)

T89C51AC2(VQFP44)

T89C51AC2-RLSC-M

T89C51AC2-RLSE-M

T89C51AC2-RLSI-M