T89C51RB2-3CBCM [ATMEL]
8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH; 8 -bit微控制器16千字节/ 32K字节的FLASH
| 型号： | T89C51RB2-3CBCM |
| 厂家： | 
ATMEL |
| 描述： | 8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH |
| 文件： | 总9页 (文件大小：244K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
T89C51RB2/RC2
8-bit Microcontroller with 16 Kbytes/ 32 Kbytes FLASH
1. Description
T89C51RB2/RC2 is a high performance FLASH version Pinout is the standard 40/44 pins of the C52.
of the 80C51 8-bit microcontrollers. It contains a 16K
The fully static design of the T89C51RB2/RC2 allows
or 32Kbytes Flash memory block for program and data.
to reduce system power consumption by bringing the
The 16 Kbytes or 32 Kbytes FLASH memory can be clock frequency down to any value, even DC, without
programmed either in parallel mode or in serial mode loss of data.
with the ISP capability or with software. The
The T89C51RB2/RC2 has 2 software-selectable modes
programming voltage is internally generated from the
of reduced activity and 8 bit clock prescaler for further
standard V pin.
CC
reduction in power consumption. In the Idle mode the
The T89C51RB2/RC2 retains all features of the 80C52 CPU is frozen while the peripherals and the interrupt
with 256 bytes of internal RAM, a 7-source 4-level system are still operating. In the power-down mode the
interrupt controller and three timer/counters.
RAM is saved and all other functions are inoperative.
In addition, the T89C51RB2/RC2 has a Programmable The added features of the T89C51RB2/RC2 make it more
powerful for applications that need
pulse width
Counter Array, an XRAM of 1024 byte, a Hardware
Watchdog Timer, a Keyboard Interface, a SPI Interface,
modulation, high speed I/O and counting capabilities
such as alarms, motor control, corded phones, smart card
readers.
a
more versatile serial channel that facilitates
multiprocessor communication (EUART) and a speed
improvement mechanism (X2 mode).
2. Features
• 80C52 Compatible
•
•
•
•
•
•
8051 pin and instruction compatible
Four 8-bit I/O ports
Three 16-bit timer/counters
256 bytes scratch pad RAM
10 Interrupt sources with 4 priority levels
Dual Data Pointer
• On-chip 1024 bytes expanded RAM (XRAM)
•
Software selectable size (0, 256, 512, 768, 1024
bytes)
•
256 bytes selected at reset for TS87C51RB2/RC2
compatibility
• Keyboard interrupt interface on port P1
• SPI Interface (Master / Slave Mode)
• 8-bit clock prescaler
• Variable length MOVX for slow RAM/peripherals
• ISP (In System Programming) using standard V
CC
• Improved X2 mode with independant selection for
power supply.
CPU and each peripheral
• Boot ROM contains low level FLASH programming
• Programmable Counter Array 5 Channels with:
routines and a default serial loader
•
•
•
•
High Speed Output,
Compare / Capture,
Pulse Width Modulator,
Watchdog Timer Capabilities
• High-Speed Architecture
•
40 MHz in standard mode
•
20 MHz in X2 mode (6 clocks/machine cycle)
• 16K/32K bytes on-chip FLASH program / data
Memory
• Asynchronous port reset
•
•
Byte and page (128 bytes) erase and write
100k write cycles
• Full duplex Enhanced UART
• Dedicated Baud Rate Generator for UART
• Low EMI (inhibit ALE)
Rev. B - 30-Mar-01
1
Preliminary
T89C51RB2/RC2
• Hardware Watchdog Timer (One-time enabled with Reset-Out)
• Power control modes:
•
Idle Mode.
•
Power-down mode.
-
-
-
50µA at 3V
100µA Commercial at 5V
150µA Industrial at 5V
•
Power-Off Flag.
• Power supply: 4.5 to 5.5V or 2.7 to 3.6V
• Temperature ranges: Commercial (0 to +70°C) and industrial (-40°C to +85°C).
• Packages: PDIL40, PLCC44, VQFP44
Table 1. Memory Size
TOTAL RAM
Flash (bytes)
XRAM (bytes)
I/O
(bytes)
T89C51RB2
T89C51RC2
16k
32k
1024
1024
1280
1280
32
32
3. Block Diagram
(2) (2)
(1)
(1) (1)
(1)
XTAL1
XTAL2
Boot
EUART
Flash
XRAM
1Kx8
RAM
256x8
ROM
2Kx8
+
PCA
32Kx8 or
16Kx8
Timer2
BRG
ALE/PROG
PSEN
C51
CORE
IB-bus
CPU
EA
(2)
Parallel I/O Ports & Ext. Bus
Port 0 Port 1 Port 3Port I2
Timer 0
Timer 1
Watch Key
Dog Board
INT
Ctrl
RD
SPI
(2)
Port 2
WR
(2) (2)
(2) (2)
(1) (1) (1)
(1)
(1): Alternate function of Port 1
(2): Alternate function of Port 3
2
Rev. B - 30-Mar-01
Preliminary
T89C51RB2/RC2
4. SFR Mapping
The Special Function Registers (SFRs) of the T89C51RB2/RC2 fall into the following categories:
•
•
•
•
•
•
•
•
•
•
•
•
•
•
C51 core registers: ACC, B, DPH, DPL, PSW, SP
I/O port registers: P0, P1, P2, P3
Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H
Serial I/O port registers: SADDR, SADEN, SBUF, SCON
PCA ( Programmable Counter Array ) registers : CCON , CCAPMx , CL , CH , CCAPxH , CCAPxL (x : 0 to 4)
Power and clock control registers: PCON
Hardware Watchdog Timer registers : WDTRST, WDTPRG
Interrupt system registers: IE0, IPL0, IPH0 , IE1 , IPL1 , IPH1
Keyboard Interface registers : KBE , KBF , KBLS
SPI registers : SPCON , SPSTR , SPDAT
BRG ( Baud Rate Generator ) registers : BRL , BDRCON
Flash register : FCON
Clock Prescaler register : CKRL
Others: AUXR, AUXR1 , CKCON0 , CKCON1
Rev. B - 30-Mar-01
3
Preliminary
T89C51RB2/RC2
Table 2. Sfr mapping
Table below shows all SFRs with their address and their reset value.
Bit
Non Bit addressable
addressable
0/8
1/9
CH
2/A
CCAP0H
3/B
CCAP1H
4/C
CCAPL2H
5/D
CCAPL3H
6/E
CCAPL4H
7/F
F8h
F0h
E8h
E0h
D8h
D0h
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
FFh
F7h
EFh
E7h
DFh
D7h
CFh
C7h
BFh
B7h
AFh
A7h
9Fh
97h
0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
B
0000 0000
CL
CCAP0L
CCAP1L
CCAPL2L
CCAPL3L
CCAPL4L
0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX
ACC
0000 0000
CCON
00X0 0000
PSW
0000 0000
T2CON
0000 0000
CMOD
00XX X000
FCON (1)
XXXX 0000
T2MOD
XXXX XX00
CCAPM0
X000 0000
CCAPM1
X000 0000
CCAPM2
X000 0000
CCAPM3
X000 0000
CCAPM4
X000 0000
RCAP2L
0000 0000
RCAP2H
0000 0000
SPCON
0001 0100
TL2
0000 0000
SPSTA
0000 0000 XXXX XXXX
TH2
0000 0000
SPDAT
IPL0
X000 000
SADEN
0000 0000
P3
IE1
IPL1
IPH1
IPH0
1111 1111
XXXX X000 XXXX X000 XXXX X111
X000 0000
IE0
0000 0000
SADDR
0000 0000
CKCON1
XXXX XXX0
WDTPRG
P2
AUXR1
XXXX X0X0
WDTRST
XXXX XXXX XXXX X000
KBF
0000 0000
1111 1111
SCON
SBUF
BRL
BDRCON
XXX0 0000
KBLS
0000 0000
KBE
0000 0000
0000 0000 XXXX XXXX 0000 0000
P1
CKRL
1111 1111
CKCON0
0000 0000
PCON
00X1 0000
1111 1111
TCON
0000 0000
TMOD
0000 0000
SP
0000 0111
TL0
0000 0000
DPL
0000 0000
TL1
0000 0000
DPH
0000 0000
TH0
0000 0000
TH1
0000 0000
AUXR
XX0X 0000
8Fh
87h
P0
1111 1111
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
reserved
(1) FCON access is reserved for the FLASH API and ISP software.
4
Rev. B - 30-Mar-01
Preliminary
T89C51RB2/RC2
5. Pin Configurations
P1.0/T2
1
40
39
38
37
VCC
P0.0/AD0
P0.1/AD1
P0.2/AD2
P0.3/AD3
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
2
3
4
5
6
7
8
P1.1/T2EX/SS
P1.2/ECI
P1.3CEX0
P1.4/CEX1
36
35
34
33
32
31
30
29
28
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7CEX4/MOSI
RST
9
EA
ALE/PROG
PSEN
P2.7/AD15
P2.6/AD14
P3.0/RxD
P3.1/TxD
P3.2/INT0
P3.3/INT1
10
11
12
13
PDIL40
14
15
16
P3.4/T0
P3.5/T1
P3.6/WR
27
26
P2.5/AD13
6
5
4
3
2 1 44 43 42 41 40
P2.4/AD12
P2.3/AD11
25
24
23
22
21
P1.5/CEX2/MISO
P1.6/CEX3/SCK
P1.7/CEx4/MOSI
RST
39
38
37
7
8
9
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE/PROG
PSEN
17
18
19
20
P3.7/RD
XTAL2
XTAL1
VSS
P2.2/AD10
P2.1/AD9
P2.0/AD8
10
11
12
13
14
15
16
17
36
35
34
33
32
31
30
29
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
PLCC44
P2.7/A15
P2.6/A14
P2.5/A13
P3.5/T1
18 19 20 21 22 23 24 25 26 27 28
44 43 42 41 40 39 38 37 36 35 34
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA
NIC*
ALE/PROG
PSEN
P1.5/CEX2/MISO
33
32
31
1
2
3
4
P1.6/CEX3/SCK
P1.7/CEX4/MOSI
RST
30
29
28
27
26
25
24
23
P3.0/RxD
NIC*
P3.1/TxD
P3.2/INT0
P3.3/INT1
P3.4/T0
5
VQFP44 1.4
6
7
8
9
10
11
P2.7/A15
P2.6/A14
P2.5/A13
P3.5/T1
12 13 14 15 16 17 18 19 20 21 22
*NIC: No Internal Connection
Rev. B - 30-Mar-01
5
Preliminary
T89C51RB2/RC2
Table 3. Pin Description for 40/44 pin packages
Pin Number
Mnemonic
Type
Name and Function
VQFP44
DIL LCC
1.4
VSS
20
40
22
44
16
I
I
Ground: 0V reference
Power Supply: This is the power supply voltage for normal, idle and
VCC
38
power-down operation
P0.0-P0.7
39-32 43-36
37-30
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that
have 1s written to them float and can be used as high impedance inputs.
Port 0 must be polarized to VCC or VSS in order to prevent any parasitic
current consumption. Port 0 is also the multiplexed low-order address
and data bus during access to external program and data memory. In this
application, it uses strong internal pull-up when emitting 1s. Port 0 also
inputs the code bytes during FLASH programming. External pull-ups are
required during program verification during which P0 outputs the code
bytes.
P1.0-P1.7
1-8
2-9
40-44
1-3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 1 pins that have 1s written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs, Port 1 pins that are
externally pulled low will source current because of the internal pull-
ups. Port 1 also receives the low-order address byte during memory
programming and verification.
Alternate functions for T89C51RB2/RC2 Port 1 include:
1
2
2
3
40
41
I/O
I/O
I/O
I
P1.0 : Input / Output
T2 (P1.0): Timer/Counter 2 external count input/Clockout
P1.1 : Input / Output
T2EX : Timer/Counter 2 Reload/Capture/Direction Control
SS : SPI Slave Select
I
3
4
5
6
4
5
6
7
42
43
44
1
I/O
I
P1.2 : Input / Output
ECI : External Clock for the PCA
P1.3: Input / Output
CEX0 : Capture/Compare External I/O for PCA module 0
P1.4 : Input / Output
CEX1 : Capture/Compare External I/O for PCA module 1
P1.5 : Input / Output
CEX2 : Capture/Compare External I/O for PCA module 2
MISO : SPI Master Input Slave Output line
When SPI is is in master mode , MISO receives data from the slave
peripheral. When SPI is in slave mode , MISO outputs data to the master
controller.
I/O
I/O
I/O
I/O
I/O
I/O
I/O
7
8
8
9
2
3
I/O
I/O
I/O
P1.6 : Input / Output
CEX3 : Capture/Compare External I/O for PCA module 3
SCK : SPI Serial Clock
SCK outputs clock to the slave peripheral
P1.7 : Input / Output:
CEX4 : Capture/Compare External I/O for PCA module 4
MOSI : SPI Master Output Slave Input line
When SPI is is in master mode , MOSI outputs data to the slave peripheral.
When SPI is in slave mode , MOSI receives data from the master
controller.
I/O
I/O
I/O
Crystal 1: Input to the inverting oscillatamplifier and input to the
XTAL1
XTAL2
19
18
21
20
15
14
I
internal clock generator circuits.
O
Crystal 2: Output from the inverting oscillator amplifier
6
Rev. B - 30-Mar-01
Preliminary
T89C51RB2/RC2
Pin Number
Mnemonic
Type
Name and Function
VQFP44
DIL LCC
1.4
P2.0-P2.7
21-28 24-31
18-25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 2 pins that have 1s written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs, Port 2 pins that are
externally pulled low will source current because of the internal pull-
ups. Port 2 emits the high-order address byte during fetches from external
program memory and during accesses to external data memory that use
16-bit addresses (MOVX @DPTR).In this application, it uses strong
internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the
P2 SFR. Some Port 2 pins receive the high order address bits during
EPROM programming and verification:
P2.0 to P2.5 for 16Kb devices
P2.0 to P2.6 for 32Kb devices
P3.0-P3.7
10-17
11,
13-19
5,
7-13
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups.
Port 3 pins that have 1s written to them are pulled high by the internal
pull-ups and can be used as inputs. As inputs, Port 3 pins that are
externally pulled low will source current because of the internal pull-
ups. Port 3 also serves the special features of the 80C51 family, as listed
below.
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
8
I
O
I
I
I
I
O
O
RXD (P3.0): Serial input port
TXD (P3.1): Serial output port
INT0 (P3.2): External interrupt 0
INT1 (P3.3): External interrupt 1
T0 (P3.4): Timer 0 external input
T1 (P3.5): Timer 1 external input
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
Reset: A high on this pin for two machine cycles while the oscillator is
running, resets the device. An internal diffused resistor to VSS permits
a power-on reset using only an external capacitor to VCC. This pin is
an output when the hardware watchdog forces a system reset.
9
10
11
12
13
RST
9
10
33
4
I/O
ALE/PROG
30
27
O (I) Address Latch Enable/Program Pulse: Output pulse for latching the
low byte of the address during an access to external memory. In normal
operation, ALE is emitted at a constant rate of 1/6 (1/3 in X2 mode) the
oscillator frequency, and can be used for external timing or clocking.
Note that one ALE pulse is skipped during each access to external data
memory. This pin is also the program pulse input (PROG) during Flash
programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With
this bit set, ALE will be inactive during internal fetches.
PSEN
EA
29
31
32
35
26
29
O
Program Strobe ENable: The read strobe to external program memory.
When executing code from the external program memory, PSEN is
activated twice each machine cycle, except that two PSEN activations
are skipped during each access to external data memory. PSEN is not
activated during fetches from internal program memory.
External Access Enable: EA must be externally held low to enable the
device to fetch code from external program memory locations 0000H to
FFFFH (RD). If security level 1 is programmed, EA will be internally
latched on Reset.
I
Rev. B - 30-Mar-01
7
Preliminary
T89C51RB2/RC2
6. Ordering Information
T
M
-3C
89C51Rx2
C
S
Packages:
Temperature Range
C:Commercial 0 to 70oC
I:Industrial -40 to 85oC
3C: PDIL40
SL: PLCC44
RL: VQFP44 (1.4mm)
89C51RC2 ( 32k Flash )
89C51RB2 ( 16k Flash )
-M:
-L:
VCC: 5V
40 MHz, X1 mode
20 MHz, X2 mode
VCC: 3 V
40 MHz, X1 mode
20 MHz, X2 mode
Conditioning
S: Stick
T: Tray
B: Blue Tape
W: Wafer
Rev. B - 30-Mar-01
8
Preliminary
T89C51RB2/RC2
Table 4. Possible order entries
Exten-
sion
Type
T89C51RB2 T89C51RC2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-3CSCM Stick, PDIL40, Com, 5V
-3CSIM Stick, PDIL40, Ind, 5V
-SLSCM Stick, PLCC44, Com, 5V
-SLSIM Stick, PLCC44, Ind, 5V
-SLSCL Stick, PLCC44, Com, 3V
-SLSIL
Stick, PLCC44, Ind, 3V
-RLTIM Tray, VQFP44, Ind, 5V
-RLTCL Tray, VQFP44, Com, 3V
-SLSEM Stick, PLCC44, Sample, 5V
9
Rev. B - 30-Mar-01
Preliminary
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