T89C51RD2-RDVC-M_技术文档

T89C51RD2

0 to 40MHz Flash Programmable 8-bit Microcontroller

1. Description

ATMEL Wireless and Microcontrollers T89C51RD2 is mechanism (X2 mode). Pinout is either the standard 40/

high performance CMOS Flash version of the 80C51 44 pins of the C52 or an extended version with 6 ports

CMOS single chip 8-bit microcontroller. It contains a in a 64/68 pins package.

64 Kbytes Flash memory block for program and for data.

The fully static design of the T89C51RD2 allows to

The 64 Kbytes Flash memory can be programmed either reduce system power consumption by bringing the clock

in parallel mode or in serial mode with the ISP capability frequency down to any value, even DC, without loss of

or with software. The programming voltage is internally data.

generated from the standard V pin.

CC

The T89C51RD2 has 2 software-selectable modes of

The T89C51RD2 retains all features of the ATMEL reduced activity for further reduction in power

Wireless and Microcontrollers 80C52 with 256 bytes of consumption. In the idle mode the CPU is frozen while

internal RAM, a 7-source 4-level interrupt controller and the peripherals and the interrupt system are still

three timer/counters.

operating. In the power-down mode the RAM is saved

and all other functions are inoperative.

In addition, the T89C51RD2 has a Programmable

Counter Array, an XRAM of 1024 bytes, an EEPROM The added features of the T89C51RD2 makes it more

of 2048 bytes, a Hardware Watchdog Timer, a more powerful for applications that need pulse width

versatile serial channel that facilitates multiprocessor modulation, high speed I/O and counting capabilities

communication (EUART) and a speed improvement such as alarms, motor control, corded phones, smart card

readers.

2. Features

•

80C52 Compatible

•

Dual Data Pointer

•

8051 pin and instruction compatible

Four 8-bit I/O ports (or 6 in 64/68 pins packages)

Three 16-bit timer/counters

Variable length MOVX for slow RAM/peripherals

Improved X2 mode with independant selection for

CPU and each peripheral

•

2 k bytes EEPROM block for data storage

256 bytes scratch pad RAM

7 Interrupt sources with 4 priority levels

•

100K Write cycle

•

ISP (In System Programming) using standard V

power supply.

Programmable Counter Array with:

CC

•

High Speed Output,

Boot FLASH contains low level FLASH

programming routines and a default serial loader

Compare / Capture,

Pulse Width Modulator,

Watchdog Timer Capabilities

High-Speed Architecture

•

40 MHz in standard mode

•

Asynchronous port reset

Full duplex Enhanced UART

Low EMI (inhibit ALE)

20 MHz in X2 mode (6 clocks/machine cycle)

•

64K bytes on-chip Flash program / data Memory

•

Byte and page (128 bytes) erase and write

10k write cycles

Hardware Watchdog Timer (One-time enabled with

Reset-Out)

On-chip 1024 bytes expanded RAM (XRAM)

•

Power control modes:

•

Software selectable size (0, 256, 512, 768, 1024

bytes)

•

Idle Mode.

Power-down mode.

•

768 bytes selected at reset for T87C51RD2

compatibility

Rev. F - 15 February, 2001

1

T89C51RD2

•

Power supply:

- M version: Commercial and industrial

4.5V to 5.5V : 40MHz X1 Mode, 20MHz X2 Mode

3V to 5.5V : 33MHz X1 Mode, 16 MHz X2 Mode

- L version: Commercial and industrial

2.7V to 3.6V : 25MHz X1 Mode, 12MHz X2 Mode

Temperature ranges: Commercial (0 to +70°C) and industrial (-40 to +85°C).

•

Packages: PDIL40, PLCC44, VQFP44, PLCC68, VQFP64

Table 1. Memory Size

PDIL40

TOTAL RAM

(bytes)

PLCC44

Flash (bytes)

EEPROM (bytes)

XRAM (bytes)

I/O

VQFP44 1.4

T89C51RD2

64k

2k

1024

1280

32

PLCC68

EEPROM

(bytes)

TOTAL RAM

(bytes)

Flash (bytes)

XRAM (bytes)

I/O

VQFP64 1.4

T89C51RD2

64k

2k

1024

1280

48

3. Block Diagram

(3) (3)

(1)

(1) (1)

(1)

XTAL1

XTAL2

Flash

64Kx8

RAM

256x8

XRAM

1Kx8

EEPROM

2Kx8

EUART

PCA

Timer2

ALE/PROG

PSEN

C51

CORE

IB-bus

CPU

EA

(3)

Parallel I/O Ports & Ext. Bus

Port 4 Port 5

Timer 0

Timer 1

INT

Ctrl

Watch

Dog

RD

(3)

Port 0 Port 1

Port 3

Port 2

WR

(2)

(3) (3)

(1): Alternate function of Port 1

(2): Only available on high pin count packages

(3): Alternate function of Port 3

2

Rev. F - 15 February, 2001

T89C51RD2

4. SFR Mapping

The Special Function Registers (SFRs) of the T89C51RD2 fall into the following categories:

•

C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1

I/O port registers: P0, P1, P2, P3, P4, P5

Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H

Serial I/O port registers: SADDR, SADEN, SBUF, SCON

Power and clock control registers: PCON

Hardware Watchdog Timer register: WDTRST, WDTPRG

Interrupt system registers: IE, IP, IPH

Flash and EEPROM registers: FCON, EECON, EETIM

Others: AUXR, AUXR1, CKCON

Table below shows all SFRs with their address and their reset value.

Bit

address-

able

Non Bit addressable

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

CH

CCAP0H

CCAP1H

CCAPL2H

CCAPL3H

CCAPL4H

F8h

F0h

E8h

E0h

D8h

D0h

C8h

C0h

B8h

B0h

A8h

A0h

98h

90h

88h

80h

FFh

F7h

EFh

E7h

DFh

D7h

CFh

C7h

BFh

B7h

AFh

A7h

9Fh

97h

0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

B

0000 0000

P5

CL

CCAP0L

CCAP1L

CCAPL2L

CCAPL3L

CCAPL4L

1111 1111

0000 0000 XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX XXXX

ACC

0000 0000

CCON

00X0 0000

CMOD

00XX X000

CCAPM0

X000 0000

CCAPM1

X000 0000

CCAPM2

X000 0000

CCAPM3

X000 0000

CCAPM4

X000 0000

PSW

0000 0000

FCON

EECON

EETIM

0000 0000

XXXX 0000 XXXX XX00

T2CON

0000 0000

T2MOD

XXXX XX00

RCAP2L

0000 0000

RCAP2H

0000 0000

TL2

0000 0000

TH2

0000 0000

P4

P5

1111 1111

IP

SADEN

0000 0000

X000 000

P3

IPH

X000 0000

1111 1111

IE

SADDR

0000 0000

P2

AUXR1

XXXX 00X0

WDTRST

XXXX XXXX XXXX X000

WDTPRG

1111 1111

SCON

SBUF

0000 0000 XXXX XXXX

P1

1111 1111

TCON

0000 0000

TMOD

0000 0000

TL0

0000 0000

TL1

0000 0000

TH0

0000 0000

TH1

0000 0000

AUXR

XX0X 1000

CKCON

X000 0000

8Fh

87h

P0

SP

0000 0111

DPL

0000 0000

DPH

0000 0000

PCON

00X1 0000

1111 1111

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

Rev. F - 15 February, 2001

3

T89C51RD2

reserved

4

Rev. F - 15 February, 2001

T89C51RD2

5. Pin Configuration

P1.0/T2

40

39

38

1

2

VCC

P0.0/AD0

P0.1/AD1

P1.1/T2EX

P1.2/ECI

3

4

37 P0.2/AD2

P1.3CEX0

P1.4/CEX1

P1.5/CEX2

P0.3/AD3

P0.4/AD4

36

35

34

33

32

31

30

5

6

P0.5/AD5

P0.6/AD6

P0.7/AD7

7

8

P1.6/CEX3

P1.7CEX4

RST

6

5

4

3

2

1

44 43 42 41 40

P1.5/CEX2

P1.6/CEX3

P1.7/CEx4

RST

39

38

7

8

P0.4/AD4

9

P0.5/AD5

EA

P3.0/RxD 10

37

9

PDIL

P0.6/AD6

ALE/PROG

PSEN

P3.1/TxD

P3.2/INT0

11

12

10

11

12

13

36

35

34

33

P0.7/AD7

EA

29

28

P3.0/RxD

NIC*

P2.7/AD15

P2.6/AD14

P3.3/INT1 13

P3.4/T0 14

PLCC

NIC*

27

26

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P2.5/AD13

ALE/PROG

PSEN

15

16

17

18

19

20

P3.5/T1

14

15

16

17

32

31

30

29

P2.4/AD12

P2.3/AD11

25

24

23

22

21

P3.6/WR

P2.7/A15

P2.6/A14

P2.5/A13

P3.7/RD

XTAL2

P2.2/AD10

P2.1/AD9

P2.0/AD8

P3.5/T1

XTAL1

VSS

18 19 20 21 22 23 24 25 26 27 28

44 43 42 41 40 39 38 37 36 35 34

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA

P1.5/CEX2

33

32

1

2

P1.6/CEX3

P1.7/CEX4

RST

31

3

4

30

29

28

27

P3.0/RxD

NIC*

5

6

VQFP44 1.4

NIC*

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

ALE/PROG

PSEN

7

8

26

25

24

23

P2.7/A15

P2.6/A14

P2.5/A13

9

10

11

12 13 14 15 16 17 18 19 20 21 22

*NIC: No Internal Connection

Rev. F - 15 February, 2001

5

T89C51RD2

9

8

7

6

5

4

3

2

1

68 67 66 65 64 63 62 61

60

P5.5

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

25

26

P5.0

P0.3/AD3

P0.2/AD2

P5.6

59

58

57

56

55

54

53

52

51

50

49

48

47

46

45

44

P2.4/A12

P2.3/A11

P4.7

P0.1/AD1

P0.0/AD0

P5.7

P2.2/A10

P2.1/A9

P2.0/A8

P4.6

VCC

PLCC 68

NIC

VSS1

VSS

P1.0/T2

P4.0

P4.5

P1.1/T2EX

P1.2/ECI

P1.3/CEX0

P4.1

XTAL1

XTAL2

P3.7/RD

P4.4

P1.4/CEX1

P4.2

P3.6/WR

P4.3

27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43

64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49

P5.5

1

2

3

4

5

6

7

8

48

47

46

45

44

43

42

41

40

39

38

37

36

35

34

33

P2.4/A12

P2.3/A11

P4.7

P2.2/A10

P2.1/A9

P2.0/A8

P4.6

NIC

VSS

P4.5

XTAL1

XTAL2

P3.7/RD

P4.4

P3.6/WR

P4.3

P0.3/AD3

P0.2/AD2

P5.6

P0.1/AD1

P0.0/AD0

P5.7

VCC

VSS1

P1.0/T2

9

VQFP64 1.4

10

11

12

13

14

15

16

P4.0

P1.1/T2EX

P1.2/EC1

P1.3/CEX0

P4.1

P1.4/CEX1

17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

NIC: No InternalConnection

6

Rev. F - 15 February, 2001

T89C51RD2

Pin Number

Type

Mnemonic

Name and Function

DIL LCC VQFP 1.4

V

20

22

1

16

39

I

Ground: 0V reference

SS

Vss1

Optional Ground: Contact the Sales Office for ground connection.

Power Supply: This is the power supply voltage for normal, idle and power-

down operation

V

40

44

38

I

CC

P0.0-P0.7

39-32 43-36

37-30

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s

written to them float and can be used as high impedance inputs. Port 0 must be

polarized to V or V in order to prevent any parasitic current consumption.

CC

SS

Port 0 is also the multiplexed low-order address and data bus during access to

external program and data memory. In this application, it uses strong internal

pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM

programming. External pull-ups are required during program verification during

which P0 outputs the code bytes.

P1.0-P1.7

1-8

2-9

40-44

1-3

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins

that have 1s written to them are pulled high by the internal pull-ups and can be

used as inputs. As inputs, Port 1 pins that are externally pulled low will source

current because of the internal pull-ups. Port 1 also receives the low-order address

byte during memory programming and verification.

Alternate functions for TSC8x54/58 Port 1 include:

1

2

3

4

5

6

7

8

2

3

4

5

6

7

8

9

40

41

42

43

44

1

I/O

I

T2 (P1.0): Timer/Counter 2 external count input/Clockout

T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control

ECI (P1.2): External Clock for the PCA

I

I/O

CEX0 (P1.3): Capture/Compare External I/O for PCA module 0

CEX1 (P1.4): Capture/Compare External I/O for PCA module 1

CEX2 (P1.5): Capture/Compare External I/O for PCA module 2

CEX3 (P1.6): Capture/Compare External I/O for PCA module 3

CEX4 (P1.7): Capture/Compare External I/O for PCA module 4

2

3

P2.0-P2.7

21-28 24-31

18-25

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2

pins that have 1s written to them are pulled high by the internal pull-ups and

can be used as inputs. As inputs, Port 2 pins that are externally pulled low will

source current because of the internal pull-ups. Port 2 emits the high-order address

byte during fetches from external program memory and during accesses to external

data memory that use 16-bit addresses (MOVX @DPTR).In this application, it

uses strong internal pull-ups emitting 1s. During accesses to external data memory

that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.

Some Port 2 pins receive the high order address bits during EPROM programming

and verification:

P2.0 to P2.5 for RB devices

P2.0 to P2.6 for RC devices

P2.0 to P2.7 for RD devices.

P3.0-P3.7

10-17

11,

13-19

5,

7-13

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins

that have 1s written to them are pulled high by the internal pull-ups and can be

used as inputs. As inputs, Port 3 pins that are externally pulled low will source

current because of the internal pull-ups. Port 3 also serves the special features

of the 80C51 family, as listed below.

10

11

12

13

14

15

16

11

13

14

15

16

17

18

5

7

I

O

I

RXD (P3.0): Serial input port

TXD (P3.1): Serial output port

8

INT0 (P3.2): External interrupt 0

INT1 (P3.3): External interrupt 1

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

WR (P3.6): External data memory write strobe

9

I

10

11

12

I

O

Rev. F - 15 February, 2001

7

T89C51RD2

Pin Number

Type

Mnemonic

Name and Function

DIL LCC VQFP 1.4

17

9

19

10

13

4

O

RD (P3.7): External data memory read strobe

Reset

I/O

Reset: A high on this pin for two machine cycles while the oscillator is running,

resets the device. An internal diffused resistor to V permits a power-on reset

SS

using only an external capacitor to V . This pin is an output when the hardware

CC

watchdog forces a system reset.

ALE/PROG

30

33

27

O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte

of the address during an access to external memory. In normal operation, ALE

is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,

and can be used for external timing or clocking. Note that one ALE pulse is

skipped during each access to external data memory. This pin is also the program

pulse input (PROG) during Flash programming. ALE can be disabled by setting

SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal fetches.

PSEN

EA

29

31

32

35

26

29

O

Program Store ENable: The read strobe to external program memory. When

executing code from the external program memory, PSEN is activated twice each

machine cycle, except that two PSEN activations are skipped during each access

to external data memory. PSEN is not activated during fetches from internal

program memory.

I

External Access Enable: EA must be externally held low to enable the device

to fetch code from external program memory locations 0000H to FFFFH (RD).

If security level 1 is programmed, EA will be internally latched on Reset.

XTAL1

XTAL2

19

18

21

20

15

14

I

Crystal 1: Input to the inverting oscillator amplifier and input to the internal

clock generator circuits.

O

Crystal 2: Output from the inverting oscillator amplifier

8

Rev. F - 15 February, 2001

T89C51RD2

5.1. Pin Description for 64/68 pin Packages

Port 4 and Port 5 are 8-bit bidirectional I/O ports with internal pull-ups. Pins that have 1 written to them are pulled

high by the internal pull ups and can be used as inputs.

As inputs, pins that are externally pulled low will source current because of the internal pull-ups.

Refer to the previous pin description for other pins.

SQUARE

PLCC68

VQFP64 1.4

VSS

VCC

P0.0

P0.1

P0.2

P0.3

P0.4

P0.5

P0.6

P0.7

P1.0

P1.1

P1.2

P1.3

P1.4

P1.5

P1.6

P1.7

P2.0

P2.1

P2.2

P2.3

P2.4

P2.5

P2.6

P2.7

P3.0

P3.1

P3.2

P3.3

P3.4

P3.5

P3.6

P3.7

RESET

ALE/PROG

PSEN

EA

XTAL1

XTAL2

P4.0

P4.1

P4.2

P4.3

P4.4

P4.5

P4.6

P4.7

P5.0

P5.1

P5.2

P5.3

P5.4

P5.5

P5.6

P5.7

51, 18

17

15

14

12

11

9

6

5

3

9/40

8

6

5

3

2

64

61

60

59

10

12

13

14

16

18

19

20

43

44

45

47

48

50

53

54

25

28

29

30

31

32

34

36

21

56

55

58

38

37

11

15

17

33

35

39

42

46

49

51

52

62

63

1

19

21

22

23

25

27

28

29

54

55

56

58

59

61

64

65

34

39

40

41

42

43

45

47

30

68

67

2

49

48

20

24

26

44

46

50

53

57

60

62

63

7

8

10

13

16

4

7

Rev. F - 15 February, 2001

9

T89C51RD2

6. Enhanced Features

In comparison to the original 80C52, the T89C51RD2 implements some new features, which are:

•

The X2 option.

The Dual Data Pointer.

The extended RAM.

The Programmable Counter Array (PCA).

The Watchdog.

The 4 level interrupt priority system.

The power-off flag.

The ONCE mode.

The ALE disabling.

Some enhanced features are also located in the UART and the timer 2.

6.1. X2 Feature and Clock Generation

The T89C51RD2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following

advantages:

•

Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

Save power consumption while keeping same CPU power (oscillator power saving).

Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.

Increase CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main

clock input of the core (phase generator). This divider may be disabled by software.

6.1.1. Description

The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and

peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed,

the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block

diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode.

Figure 2. shows the mode switching waveforms.

XTAL1:2

2

state machine: 6 clock cycles.

CPU control

XTAL1

0

1

F_XTAL

F_OSC

X2

CKCON reg

Figure 1. Clock Generation Diagram

Rev. F - 15 February, 2001

10

T89C51RD2

XTAL1

XTAL1:2

X2 bit

CPU clock

STD Mode

X2 Mode

STD Mode

Figure 2. Mode Switching Waveforms

The X2 bit in the CKCON register (See Table 2.) allows to switch from 12 clock periods per instruction to 6

clock periods and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the

X2 feature (X2 mode).

The T0X2, T1X2, T2X2, SiX2, PcaX2 and WdX2 bits in the CKCON register (See Table 2.) allow to switch from

standard peripheral speed (12 clock periods per peripheral clock cycle) to fast peripheral speed (6 clock periods

per peripheral clock cycle). These bits are active only in X2 mode.

More information about the X2 mode can be found in the application note ANM072 "How to take advantage of

the X2 features in TS80C51 microcontroller?"

Table 2. CKCON Register

CKCON - Clock Control Register (8Fh)

7

-

6

5

4

3

2

1

0

WdX2

PcaX2

SiX2

T2X2

T1X2

T0X2

X2

Bit

Number

Bit

Mnemonic

Description

7

6

-

Reserved

Watchdog clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

WdX2

PcaX2

Programmable Counter Array clock (This control bit is validated when the CPU clock X2 is set; when X2 is

low, this bit has no effect)

5

4

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Enhanced UART clock (Mode 0 and 2) (This control bit is validated when the CPU clock X2 is set; when X2

is low, this bit has no effect)

SiX2

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

Timer2 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle.

3

2

T2X2

T1X2

Timer1 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle

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Rev. F - 15 February, 2001

T89C51RD2

Bit

Number

Bit

Mnemonic

Description

Timer0 clock (This control bit is validated when the CPU clock X2 is set; when X2 is low, this bit has no effect)

Clear to select 6 clock periods per peripheral clock cycle.

Set to select 12 clock periods per peripheral clock cycle

1

0

T0X2

X2

CPU clock

Clear to select 12 clock periods per machine cycle (STD mode) for CPU and all the peripherals.

Set to select 6clock periods per machine cycle (X2 mode) and to enable the individual peripherals "X2" bits.

Reset Value = X000 0000b

Not bit addressable

Rev. F - 15 February, 2001

12

T89C51RD2

6.2. Dual Data Pointer Register Ddptr

The additional data pointer can be used to speed up code execution and reduce code size.

The dual DPTR structure is a way by which the chip will specify the address of an external data memory location.

There are two 16-bit DPTR registers that address the external memory, and a single bit called

DPS = AUXR1/bit0 (See Table 3.) that allows the program code to switch between them (Refer to Figure 3).

External Data Memory

7

0

DPS

DPTR1

DPTR0

AUXR1(A2H)

DPH(83H) DPL(82H)

Figure 3. Use of Dual Pointer

Table 3. AUXR1: Auxiliary Register 1

AUXR1

Address 0A2H

-

GF3

0

-

DPS

0

Reset value

Function

X

Symbol

a

-

Not implemented, reserved for future use.

Data Pointer Selection.

DPS

Operating Mode

DPTR0 Selected

DPTR1 Selected

0

1

b

GF3

This bit is a general purpose user flag .

a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family

products to invoke new feature. In that case, the reset value of the new bit will be 0, and its active

value will be 1. The value read from a reserved bit is indeterminate.

b. Bit 2 stuck at 0; this allows to use INC AUXR1 to toggle DPS without changing GF3.

Application

Software can take advantage of the additional data pointers to both increase speed and reduce code size, for

example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’

pointer and the other one as a "destination" pointer.

ASSEMBLY LANGUAGE

Rev. F - 15 February, 2001

13

T89C51RD2

; Block move using dual data pointers

; Modifies DPTR0, DPTR1, A and PSW

; note: DPS exits opposite of entry state

; unless an extra INC AUXR1 is added

;

00A2 AUXR1 EQU 0A2H

;

0000 909000MOV DPTR,#SOURCE ; address of SOURCE

0003 05A2 INC AUXR1 ; switch data pointers

0005 90A000 MOV DPTR,#DEST ; address of DEST

0008 LOOP:

0008 05A2 INC AUXR1 ; switch data pointers

000A E0 MOVX A,@DPTR ; get a byte from SOURCE

000B A3 INC DPTR ; increment SOURCE address

000C 05A2 INC AUXR1 ; switch data pointers

000E F0 MOVX @DPTR,A ; write the byte to DEST

000F A3 INC DPTR ; increment DEST address

0010 70F6JNZ LOOP ; check for 0 terminator

0012 05A2 INC AUXR1 ; (optional) restore DPS

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note

that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple

routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not

its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe

that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.

14

Rev. F - 15 February, 2001

T89C51RD2

6.3. Expanded RAM (XRAM)

The T89C51RD2 provide additional Bytes of random access memory (RAM) space for increased data parameter

handling and high level language usage.

T89C51RD2 devices have expanded RAM in external data space; Maximum size and location are described in Table 4.

Table 4. Description of expanded RAM

Address

Port

XRAM size

Start

End

T89C51RD2

1024

00h

3FFh

The T89C51RD2 has internal data memory that is mapped into four separate segments.

The four segments are:

•

1. The Lower 128 bytes of RAM (addresses 00H to 7FH) are directly and indirectly addressable.

2. The Upper 128 bytes of RAM (addresses 80H to FFH) are indirectly addressable only.

3. The Special Function Registers, SFRs, (addresses 80H to FFH) are directly addressable only.

4. The expanded RAM bytes are indirectly accessed by MOVX instructions, and with the EXTRAM bit

cleared in the AUXR register. (See )

The Lower 128 bytes can be accessed by either direct or indirect addressing. The Upper 128 bytes can be accessed

by indirect addressing only. The Upper 128 bytes occupy the same address space as the SFR. That means they

have the same address, but are physically separate from SFR space.

FF or 3FF

FF

80

FF

80

FFFF

Upper

128 bytes

Internal

Special

Function

External

Data

Memory

Register

Ram

direct accesses

indirect accesses

XRAM

Lower

128 bytes

Internal

Ram

direct or indirect

accesses

0100 or 0400

0000

00

Figure 4. Internal and External Data Memory Address

When an instruction accesses an internal location above address 7FH, the CPU knows whether the access is to the

upper 128 bytes of data RAM or to SFR space by the addressing mode used in the instruction.

•

Instructions that use direct addressing access SFR space. For example: MOV 0A0H, # data ,accesses the SFR

at location 0A0H (which is P2).

•

Instructions that use indirect addressing access the Upper 128 bytes of data RAM. For example: MOV @R0,

# data where R0 contains 0A0H, accesses the data byte at address 0A0H, rather than P2 (whose address is 0A0H).

Rev. F - 15 February, 2001

15

T89C51RD2

•

The XRAM bytes can be accessed by indirect addressing, with EXTRAM bit cleared and MOVX instructions.

This part of memory which is physically located on-chip, logically occupies the first bytes of external data

memory. The bits XRS0 and XRS1 are used to hide a part of the available XRAM as explained in Table . This

can be useful if external peripherals are mapped at addresses already used by the internal XRAM.

•

With EXTRAM = 0, the XRAM is indirectly addressed, using the MOVX instruction in combination with any

of the registers R0, R1 of the selected bank or DPTR. An access to XRAM will not affect ports P0, P2, P3.6

(WR) and P3.7 (RD). For example, with EXTRAM = 0, MOVX @R0, # data where R0 contains 0A0H,

accesses the XRAM at address 0A0H rather than external memory. An access to external data memory locations

higher than the accessible size of the XRAM will be performed with the MOVX DPTR instructions in the

same way as in the standard 80C51, so with P0 and P2 as data/address busses, and P3.6 and P3.7 as write and

read timing signals. Accesses to XRAM above 0FFH can only be done thanks to the use of DPTR.

•

With EXTRAM = 1, MOVX @Ri and MOVX @DPTR will be similar to the standard 80C51. MOVX @ Ri

will provide an eight-bit address multiplexed with data on Port0 and any output port pins can be used to output

higher order address bits. This is to provide the external paging capability. MOVX @DPTR will generate a

sixteen-bit address. Port2 outputs the high-order eight address bits (the contents of DPH) while Port0 multiplexes

the low-order eight address bits (DPL) with data. MOVX @ Ri and MOVX @DPTR will generate either read

or write signals on P3.6 (WR) and P3.7 (RD).

The stack pointer (SP) may be located anywhere in the 256 bytes RAM (lower and upper RAM) internal data

memory. The stack may not be located in the XRAM.

The M0 bit allows to stretch the XRAM timings; if M0 is set, the read and write pulses are extended from 6 to

30 clock periods. This is useful to access external slow peripherals.

Auxiliary Register AUXR

AUXR

Address 08EH

-

M0

0

-

XRS1

1

XRS0 EXTRAM

AO

0

Reset value

X

0

Symbol

Function

a

-

Not implemented, reserved for future use.

Disable/Enable ALE

AO

0

Operating Mode

ALE is emitted at a constant rate of 1/6 the oscillator frequency (or 1/3 if X2 mode is used)

ALE is active only during a MOVX or MOVC instruction

1

EXTRAM

Internal/External RAM (00H-FFH) access using MOVX @ Ri/ @ DPTR

EXTRAM

Operating Mode

0

1

Internal XRAM access using MOVX @ Ri/ @ DPTR

External data memory access

XRS0

XRS1

XRAM size: Accessible size of the XRAM

XRS1:0

0 0

XRAM size

256 bytes

0 1

512 bytes

1 0

768 bytes (default)

1024 bytes

1 1

M0

Stretch MOVX control: the RD/ and the WR/ pulse length is increased according to the value of M0

M0

0

Pulse length in clock period

6

1

30

a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In

that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is

indeterminate.

16

Rev. F - 15 February, 2001

T89C51RD2

6.4. Timer 2

The timer 2 in the T89C51RD2 is compatible with the timer 2 in the 80C52.

It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in

cascade. It is controlled by T2CON register (See Table 5) and T2MOD register (See Table 6). Timer 2 operation

is similar to Timer 0 and Timer 1. C/T2 selects F

/12 (timer operation) or external pin T2 (counter operation)

OSC

as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.

Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the

combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the ATMEL Wireless and Micrcontrollers

8-bit Microcontroller Hardware description.

Refer to the ATMEL Wireless and Micrcontrollers 8-bit Microcontroller Hardware description for the description

of Capture and Baud Rate Generator Modes.

In T89C51RD2 Timer 2 includes the following enhancements:

•

Auto-reload mode with up or down counter

Programmable clock-output

6.4.1. Auto-Reload Mode

The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit

in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the ATMEL Wireless and Micrcontrollers 8-bit

Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in

Figure 5. In this mode the T2EX pin controls the direction of count.

When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates

an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded

into the timer registers TH2 and TL2.

When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and

TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh

into the timer registers.

The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2

does not generate any interrupt. This bit can be used to provide 17-bit resolution.

Rev. F - 15 February, 2001

17

T89C51RD2

:12

0

1

XTAL1

F

OSC

XTAL

T2

TR2

C/T2

T2CONreg

(DOWN COUNTING RELOAD VALUE)

T2EX:

if DCEN=1, 1=UP

if DCEN=1, 0=DOWN

if DCEN = 0, up counting

FFh

(8-bit)

FFh

(8-bit)

T2CONreg

EXF2

TOGGLE

TL2

(8-bit)

TH2

(8-bit)

TIMER 2

INTERRUPT

TF2

T2CONreg

RCAP2L

(8-bit)

RCAP2H

(8-bit)

(UP COUNTING RELOAD VALUE)

Figure 5. Auto-Reload Mode Up/Down Counter (DCEN = 1)

6.4.2. Programmable Clock-Output

In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 6) . The

input clock increments TL2 at frequency F /2. The timer repeatedly counts to overflow from a loaded value.

OSC

At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer

2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system

oscillator frequency and the value in the RCAP2H and RCAP2L registers :

F

osc

Clock – OutFrequency = --------------------------------------------------------------------------------------

4 × (65536 – RCAP2H ⁄ RCAP2L)

For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz

16)

(F

/2 to 4 MHz (F

/4). The generated clock signal is brought out to T2 pin (P1.0).

OSC

Timer 2 is programmed for the clock-out mode as follows:

•

Set T2OE bit in T2MOD register.

Clear C/T2 bit in T2CON register.

Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.

Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different

one depending on the application.

•

To start the timer, set TR2 run control bit in T2CON register.

18

Rev. F - 15 February, 2001

T89C51RD2

It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration,

the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and

RCAP2L registers.

:2

XTAL1

TR2

T2CON reg

TH2

TL2

(8-bit) (8-bit)

OVEFLOW

RCAP2H

RCAP2L

(8-bit) (8-bit)

Toggle

T2

Q

D

T2OE

T2MOD reg

TIMER 2

INTERRUPT

T2EX

EXF2

T2CON reg

EXEN2

T2CON reg

Figure 6. Clock-Out Mode C/T2 = 0

Rev. F - 15 February, 2001

19

T89C51RD2

Table 5. T2CON Register

T2CON - Timer 2 Control Register (C8h)

7

6

5

4

3

2

1

0

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

Bit

Number

Bit

Mnemonic

Description

Timer 2 overﬂow Flag

7

6

TF2

Must be cleared by software.

Set by hardware on timer 2 overﬂow, if RCLK = 0 and TCLK = 0.

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.

When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.

Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)

EXF2

Receive Clock bit

5

4

RCLK

TCLK

Clear to use timer 1 overﬂow as receive clock for serial port in mode 1 or 3.

Set to use timer 2 overﬂow as receive clock for serial port in mode 1 or 3.

Transmit Clock bit

Clear to use timer 1 overﬂow as transmit clock for serial port in mode 1 or 3.

Set to use timer 2 overﬂow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable bit

Clear to ignore events on T2EX pin for timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to

clock the serial port.

3

EXEN2

Timer 2 Run control bit

Clear to turn off timer 2.

Set to turn on timer 2.

2

1

TR2

Timer/Counter 2 select bit

Clear for timer operation (input from internal clock system: F

).

C/T2#

OSC

Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.

Timer 2 Capture/Reload bit

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overﬂow.

Clear to auto-reload on timer 2 overﬂows or negative transitions on T2EX pin if EXEN2=1.

Set to capture on negative transitions on T2EX pin if EXEN2=1.

0

CP/RL2#

Reset Value = 0000 0000b

Bit addressable

20

Rev. F - 15 February, 2001

T89C51RD2

Table 6. T2MOD Register

T2MOD - Timer 2 Mode Control Register (C9h)

7

-

6

-

5

-

4

-

3

-

2

-

1

0

T2OE

DCEN

Bit

Number

Bit

Mnemonic

Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

7

6

5

4

3

2

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 Output Enable bit

1

0

T2OE

Clear to program P1.0/T2 as clock input or I/O port.

Set to program P1.0/T2 as clock output.

Down Counter Enable bit

DCEN

Clear to disable timer 2 as up/down counter.

Set to enable timer 2 as up/down counter.

Reset Value = XXXX XX00b

Not bit addressable

Rev. F - 15 February, 2001

21

T89C51RD2

6.5. Programmable Counter Array PCA

The PCA provides more timing capabilities with less CPU intervention than the standard timer/counters. Its

advantages include reduced software overhead and improved accuracy. The PCA consists of a dedicated timer/

counter which serves as the time base for an array of five compare/ capture modules. Its clock input can be

programmed to count any one of the following signals:

•

Oscillator frequency ÷ 12 (÷ 6 in X2 mode)

Oscillator frequency ÷ 4 (÷ 2 in X2 mode)

Timer 0 overflow

External input on ECI (P1.2)

Each compare/capture modules can be programmed in any one of the following modes:

•

rising and/or falling edge capture,

software timer,

high-speed output, or

pulse width modulator.

Module 4 can also be programmed as a watchdog timer (See Section "PCA Watchdog Timer", page 31).

When the compare/capture modules are programmed in the capture mode, software timer, or high speed output

mode, an interrupt can be generated when the module executes its function. All five modules plus the PCA timer

overflow share one interrupt vector.

The PCA timer/counter and compare/capture modules share Port 1 for external I/O. These pins are listed below.

If the port is not used for the PCA, it can still be used for standard I/O.

PCA component

16-bit Counter

External I/O Pin

P1.2 / ECI

16-bit Module 0

16-bit Module 1

16-bit Module 2

16-bit Module 3

16-bit Module 4

P1.3 / CEX0

P1.4 / CEX1

P1.5 / CEX2

P1.6 / CEX3

P1.7 / CEX4

The PCA timer is a common time base for all five modules (See Figure 7). The timer count source is determined

from the CPS1 and CPS0 bits in the CMOD SFR (See Table 7) and can be programmed to run at:

•

1/12 the oscillator frequency. (Or 1/6 in X2 Mode)

1/4 the oscillator frequency. (Or 1/2 in X2 Mode)

The Timer 0 overflow

The input on the ECI pin (P1.2)

Rev. F - 15 February, 2001

22

T89C51RD2

To PCA

modules

Fosc /12

Fosc / 4

T0 OVF

P1.2

overﬂow

It

CH

CL

16 bit up/down counter

CMOD

0xD9

CIDL WDTE

CPS1 CPS0 ECF

Idle

CCON

0xD8

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

Figure 7. PCA Timer/Counter

Table 7. CMOD: PCA Counter Mode Register

CMOD

Address 0D9H

CIDL

0

WDTE

0

-

CPS1

0

CPS0

ECF

Reset value

Function

X

0

Symbol

Counter Idle control: CIDL = 0 programs the PCA Counter to continue functioning during

idle Mode. CIDL = 1 programs it to be gated off during idle.

CIDL

Watchdog Timer Enable: WDTE = 0 disables Watchdog Timer function on PCA Module 4.

WDTE = 1 enables it.

WDTE

a

-

Not implemented, reserved for future use.

CPS1

CPS0

PCA Count Pulse Select bit 1.

PCA Count Pulse Select bit 0.

b

CPS1 CPS0 Selected PCA input.

0

1

0

1

0

1

Internal clock f /12 ( Or f /6 in X2 Mode).

osc osc

Internal clock f /4 ( Or f /2 in X2 Mode).

osc

Timer 0 Overflow

External clock at ECI/P1.2 pin (max rate = f / 8)

osc

PCA Enable Counter Overflow interrupt: ECF = 1 enables CF bit in CCON to generate an

interrupt. ECF = 0 disables that function of CF.

ECF

a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family

products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its

active value will be 1. The value read from a reserved bit is indeterminate.

b.

f

= oscillator frequency

osc

The CMOD SFR includes three additional bits associated with the PCA (See Figure 7 and Table 7).

•

The CIDL bit which allows the PCA to stop during idle mode.

The WDTE bit which enables or disables the watchdog function on module 4.

23

Rev. F - 15 February, 2001

T89C51RD2

The ECF bit which when set causes an interrupt and the PCA overflow flag CF (in the CCON SFR) to be set

when the PCA timer overflows.

•

The CCON SFR contains the run control bit for the PCA and the flags for the PCA timer (CF) and each module

(Refer to Table 8).

•

Bit CR (CCON.6) must be set by software to run the PCA. The PCA is shut off by clearing this bit.

Bit CF: The CF bit (CCON.7) is set when the PCA counter overflows and an interrupt will be generated if the

ECF bit in the CMOD register is set. The CF bit can only be cleared by software.

•

Bits 0 through 4 are the flags for the modules (bit 0 for module 0, bit 1 for module 1, etc.) and are set by

hardware when either a match or a capture occurs. These flags also can only be cleared by software.

Table 8. CCON: PCA Counter Control Register

CCON

Address 0D8H

CF

0

CR

0

-

CCF4

0

CCF3

0

CCF2

0

CCF1

0

CCF0

0

Reset value

Function

X

Symbol

PCA Counter Overflow flag. Set by hardware when the counter rolls over. CF flags

an interrupt if bit ECF in CMOD is set. CF may be set by either hardware or software but

can only be cleared by software.

CF

PCA Counter Run control bit. Set by software to turn the PCA counter on. Must be cleared

by software to turn the PCA counter off.

CR

-

a

Not implemented, reserved for future use.

PCA Module 4 interrupt flag. Set by hardware when a match or capture occurs. Must be

cleared by software.

CCF4

PCA Module 3 interrupt flag. Set by hardware when a match or capture occurs. Must be

cleared by software.

CCF3

CCF2

CCF1

CCF0

PCA Module 2 interrupt flag. Set by hardware when a match or capture occurs. Must be

cleared by software.

PCA Module 1 interrupt flag. Set by hardware when a match or capture occurs. Must be

cleared by software.

PCA Module 0 interrupt flag. Set by hardware when a match or capture occurs. Must be

cleared by software.

a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family

products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its

active value will be 1. The value read from a reserved bit is indeterminate.

The watchdog timer function is implemented in module 4 (See Figure 10).

The PCA interrupt system is shown in Figure 8

Rev. F - 15 February, 2001

24

T89C51RD2

CCON

0xD8

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

PCA Timer/Counter

Module 0

Module 1

Module 2

Module 3

Module 4

To Interrupt

priority decoder

IE.6

EC

IE.7

EA

CMOD.0

CCAPMn.0

ECCFn

ECF

Figure 8. PCA Interrupt System

PCA Modules: each one of the five compare/capture modules has six possible functions. It can perform:

•

16-bit Capture, positive-edge triggered,

16-bit Capture, negative-edge triggered,

16-bit Capture, both positive and negative-edge triggered,

16-bit Software Timer,

16-bit High Speed Output,

8-bit Pulse Width Modulator.

In addition, module 4 can be used as a Watchdog Timer.

Each module in the PCA has a special function register associated with it. These registers are: CCAPM0 for module

0, CCAPM1 for module 1, etc. (See Table 9). The registers contain the bits that control the mode that each module

will operate in.

•

The ECCF bit (CCAPMn.0 where n=0, 1, 2, 3, or 4 depending on the module) enables the CCF flag in the

CCON SFR to generate an interrupt when a match or compare occurs in the associated module.

•

PWM (CCAPMn.1) enables the pulse width modulation mode.

The TOG bit (CCAPMn.2) when set causes the CEX output associated with the module to toggle when there

is a match between the PCA counter and the module's capture/compare register.

•

The match bit MAT (CCAPMn.3) when set will cause the CCFn bit in the CCON register to be set when there

is a match between the PCA counter and the module's capture/compare register.

The next two bits CAPN (CCAPMn.4) and CAPP (CCAPMn.5) determine the edge that a capture input will

be active on. The CAPN bit enables the negative edge, and the CAPP bit enables the positive edge. If both

bits are set both edges will be enabled and a capture will occur for either transition.

•

The last bit in the register ECOM (CCAPMn.6) when set enables the comparator function.

Table 10 shows the CCAPMn settings for the various PCA functions.

.

25

Rev. F - 15 February, 2001

T89C51RD2

Table 9. CCAPMn: PCA Modules Compare/Capture Control Registers

CCAPM0=0DAH

CCAPM1=0DBH

CCAPM2=0DCH

CCAPM3=0DDH

CCAPM4=0DEH

CCAPMn Address

n = 0 - 4

-

ECOMn CAPPn CAPNn MATn

TOGn PWMm ECCFn

Reset value

Function

X

0

Symbol

a

-

Not implemented, reserved for future use.

ECOMn

CAPPn

CAPNn

Enable Comparator. ECOMn = 1 enables the comparator function.

Capture Positive, CAPPn = 1 enables positive edge capture.

Capture Negative, CAPNn = 1 enables negative edge capture.

Match. When MATn = 1, a match of the PCA counter with this module's compare/capture

register causes the CCFn bit in CCON to be set, flagging an interrupt.

MATn

TOGn

PWMn

ECCFn

Toggle. When TOGn = 1, a match of the PCA counter with this module's compare/capture

register causes the CEXn pin to toggle.

Pulse Width Modulation Mode. PWMn = 1 enables the CEXn pin to be used as a pulse width

modulated output.

Enable CCF interrupt. Enables compare/capture flag CCFn in the CCON register to generate

an interrupt.

a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family

products to invoke new features. In that case, the reset or inactive value of the new bit will be 0, and its

active value will be 1. The value read from a reserved bit is indeterminate.

Table 10. PCA Module Modes (CCAPMn Registers)

ECOMn CAPPn CAPNn MATn

TOGn PWMm ECCFn

Module Function

No Operation

0

1

0

16-bit capture by a positive-edge

trigger on CEXn

X

16-bit capture by a negative trigger on

CEXn

X

1

0

1

0

1

0

1

0

X

16-bit capture by a transition on CEXn

16-bit Software Timer / Compare

mode.

1

0

1

0

1

0

1

0

X

0

16-bit High Speed Output

8-bit PWM

X

Watchdog Timer (module 4 only)

There are two additional registers associated with each of the PCA modules. They are CCAPnH and CCAPnL and

these are the registers that store the 16-bit count when a capture occurs or a compare should occur. When a module

is used in the PWM mode these registers are used to control the duty cycle of the output (See Table 11 & Table 12)

Rev. F - 15 February, 2001

26

T89C51RD2

Table 11. CCAPnH: PCA Modules Capture/Compare Registers High

CCAP0H=0FAH

CCAP1H=0FBH

CCAP2H=0FCH

CCAP3H=0FDH

CCAP4H=0FEH

CCAPnH Address

n = 0 - 4

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset value

Table 12. CCAPnL: PCA Modules Capture/Compare Registers Low

CCAP0L=0EAH

CCAP1L=0EBH

CCAP2L=0ECH

CCAP3L=0EDH

CCAP4L=0EEH

CCAPnL Address

n = 0 - 4

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Reset value

Table 13. CH: PCA Counter High

CH

Address 0F9H

7

0

6

0

5

0

4

0

3

0

2

0

1

0

Table 14. CL: PCA Counter Low

CL

Address 0E9H

7

0

6

0

5

0

4

0

3

0

2

0

1

0

6.5.1. PCA Capture Mode

To use one of the PCA modules in the capture mode either one or both of the CCAPM bits CAPN and CAPP for

that module must be set. The external CEX input for the module (on port 1) is sampled for a transition. When a

valid transition occurs the PCA hardware loads the value of the PCA counter registers (CH and CL) into the

module's capture registers (CCAPnL and CCAPnH). If the CCFn bit for the module in the CCON SFR and the

ECCFn bit in the CCAPMn SFR are set then an interrupt will be generated (Refer to Figure 9).

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Rev. F - 15 February, 2001

T89C51RD2

CCON

0xD8

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

PCA IT

PCA Counter/Timer

Cex.n

CH

CL

Capture

CCAPnH

CCAPnL

CCAPMn, n= 0 to 4

0xDA to 0xDE

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

Figure 9. PCA Capture Mode

6.5.2. 16-bit Software Timer / Compare Mode

The PCA modules can be used as software timers by setting both the ECOM and MAT bits in the modules

CCAPMn register. The PCA timer will be compared to the module's capture registers and when a match occurs

an interrupt will occur if the CCFn (CCON SFR) and the ECCFn (CCAPMn SFR) bits for the module are both

set (See Figure 10).

Rev. F - 15 February, 2001

28

T89C51RD2

CCON

0xD8

CCF4

CF

CR

CCF3 CCF2 CCF1 CCF0

Write to

CCAPnL Reset

PCA IT

Write to

CCAPnH

CCAPnL

Enable

1

0

Match

16 bit comparator

RESET *

CH

CL

PCA counter/timer

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

CMOD

0xD9

CIDL WDTE

CPS1 CPS0 ECF

* Only for Module 4

Figure 10. PCA Compare Mode and PCA Watchdog Timer

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted

match could happen. Writing to CCAPnH will set the ECOM bit.

Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur while modifying

the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first,

and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.

6.5.3. High Speed Output Mode

In this mode the CEX output (on port 1) associated with the PCA module will toggle each time a match occurs

between the PCA counter and the module's capture registers. To activate this mode the TOG, MAT, and ECOM

bits in the module's CCAPMn SFR must be set (See Figure 11).

A prior write must be done to CCAPnL and CCAPnH before writing the ECOMn bit.

29

Rev. F - 15 February, 2001

T89C51RD2

CCON

CF

CR

CCF4 CCF3 CCF2 CCF1 CCF0

0xD8

Write to

CCAPnL

Reset

PCA IT

Write to

CCAPnH

CCAPnL

0

Enable

1

Match

16 bit comparator

CEXn

CH

CL

PCA counter/timer

CCAPMn, n = 0 to 4

0xDA to 0xDE

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

Figure 11. PCA High Speed Output Mode

Before enabling ECOM bit, CCAPnL and CCAPnH should be set with a non zero value, otherwise an unwanted

match could happen.

Once ECOM set, writing CCAPnL will clear ECOM so that an unwanted match doesn’t occur while modifying

the compare value. Writing to CCAPnH will set ECOM. For this reason, user software should write CCAPnL first,

and then CCAPnH. Of course, the ECOM bit can still be controlled by accessing to CCAPMn register.

6.5.4. Pulse Width Modulator Mode

All of the PCA modules can be used as PWM outputs. Figure 12 shows the PWM function. The frequency of the

output depends on the source for the PCA timer. All of the modules will have the same frequency of output

because they all share the PCA timer. The duty cycle of each module is independently variable using the module's

capture register CCAPLn. When the value of the PCA CL SFR is less than the value in the module's CCAPLn

Rev. F - 15 February, 2001

30

T89C51RD2

SFR the output will be low, when it is equal to or greater than the output will be high. When CL overflows from

FF to 00, CCAPLn is reloaded with the value in CCAPHn. This allows updating the PWM without glitches. The

PWM and ECOM bits in the module's CCAPMn register must be set to enable the PWM mode.

CCAPnH

Overﬂow

CCAPnL

“0”

CEXn

Enable

<

≥

8 bit comparator

“1”

CL

PCA counter/timer

CCAPMn, n= 0 to 4

0xDA to 0xDE

ECOMn CAPPn CAPNn MATn TOGn PWMn ECCFn

Figure 12. PCA PWM Mode

6.5.5. PCA Watchdog Timer

An on-board watchdog timer is available with the PCA to improve the reliability of the system without increasing

chip count. Watchdog timers are useful for systems that are susceptible to noise, power glitches, or electrostatic

discharge. Module 4 is the only PCA module that can be programmed as a watchdog. However, this module can

still be used for other modes if the watchdog is not needed. Figure 10 shows a diagram of how the watchdog

works. The user pre-loads a 16-bit value in the compare registers. Just like the other compare modes, this 16-bit

value is compared to the PCA timer value. If a match is allowed to occur, an internal reset will be generated. This

will not cause the RST pin to be driven high.

In order to hold off the reset, the user has three options:

•

1. periodically change the compare value so it will never match the PCA timer,

2. periodically change the PCA timer value so it will never match the compare values, or

3. disable the watchdog by clearing the WDTE bit before a match occurs and then re-enable it.

The first two options are more reliable because the watchdog timer is never disabled as in option #3. If the program

counter ever goes astray, a match will eventually occur and cause an internal reset. The second option is also not

recommended if other PCA modules are being used. Remember, the PCA timer is the time base for all modules;

changing the time base for other modules would not be a good idea. Thus, in most applications the first solution

is the best option.

This watchdog timer won’t generate a reset out on the reset pin.

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Rev. F - 15 February, 2001

T89C51RD2

6.6. Serial I/O Port

The serial I/O port in the T89C51RD2 is compatible with the serial I/O port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as an Universal Asynchronous

Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and

reception can occur simultaneously and at different baud rates

Serial I/O port includes the following enhancements:

•

Framing error detection

Automatic address recognition

6.6.1. Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing

bit error detection feature, set SMOD0 bit in PCON register (See Figure 13).

SM0/FE SM1

SM2

REN

TB8

RB8

TI

RI

SCON (98h)

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)

SM0 to UART mode control (SMOD0 = 0)

PCON (87h)

SMOD1SMOD0

-

POF

GF1

GF0

PD

IDL

To UART framing error control

Figure 13. Framing Error Block Diagram

When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop

bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit

is not found, the Framing Error bit (FE) in SCON register (See Table 15.) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can

clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled,

RI rises on stop bit instead of the last data bit (See Figure 14. and Figure 15.).

RXD

D0

D1

D2

D3

D4

D5

D6

D7

Start

bit

Data byte

Stop

bit

RI

SMOD0=X

FE

SMOD0=1

Figure 14. UART Timings in Mode 1

Rev. F - 15 February, 2001

32

T89C51RD2

RXD

D0

D1

D2

D3

D4

D5

D6

D7

D8

Start

bit

Data byte

Ninth Stop

bit bit

RI

SMOD0=0

RI

SMOD0=1

FE

SMOD0=1

Figure 15. UART Timings in Modes 2 and 3

6.6.2. Automatic Address Recognition

The automatic address recognition feature is enabled when the multiprocessor communication feature is enabled

(SM2 bit in SCON register is set).

Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by

allowing the serial port to examine the address of each incoming command frame. Only when the serial port

recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that

the CPU is not interrupted by command frames addressed to other devices.

If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit

takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the

device’s address and is terminated by a valid stop bit.

To support automatic address recognition, a device is identified by a given address and a broadcast address.

NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON

register in mode 0 has no effect).

6.6.3. Given Address

Each device has an individual address that is specified in SADDR register; the SADEN register is a mask byte

that contains don’t-care bits (defined by zeros) to form the device’s given address. The don’t-care bits provide the

flexibility to address one or more slaves at a time. The following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask byte must be 1111 1111b.

For example:

SADDR

SADEN

Given

0101 0110b

1111 1100b

0101 01XXb

The following is an example of how to use given addresses to address different slaves:

Slave A:

Slave B:

Slave C:

SADDR

SADEN

Given

1111 0001b

1111 1010b

1111 0X0Xb

SADDR

SADEN

Given

1111 0011b

1111 1001b

1111 0XX1b

SADDR

SADEN

Given

1111 0010b

1111 1101b

1111 00X1b

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Rev. F - 15 February, 2001

T89C51RD2

The SADEN byte is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A

only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).

For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but

not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2

clear (e.g. 1111 0001b).

6.6.4. Broadcast Address

A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as

don’t-care bits, e.g.:

SADDR

0101 0110b

SADEN

1111 1100b

Broadcast =SADDR OR SADEN

1111 111Xb

The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a

broadcast address is FFh. The following is an example of using broadcast addresses:

Slave A:

Slave B:

Slave C:

SADDR

1111 0001b

SADEN

1111 1010b

Broadcast 1111 1X11b,

SADDR

SADEN

1111 0011b

1111 1001b

Broadcast 1111 1X11B,

SADDR=

SADEN

Broadcast 1111 1111b

1111 0010b

1111 1101b

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the

master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send

and address FBh.

6.6.5. Reset Addresses

On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX

XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards

compatible with the 80C51 microcontrollers that do not support automatic address recognition.

SADEN - Slave Address Mask Register (B9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Not bit addressable

SADDR - Slave Address Register (A9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Not bit addressable

Table 15. SCON Register

Rev. F - 15 February, 2001

34

T89C51RD2

SCON - Serial Control Register (98h)

7

6

5

4

3

2

1

0

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

Bit

Number

Bit

Mnemonic

Description

Framing Error bit (SMOD0=1)

Clear to reset the error state, not cleared by a valid stop bit.

Set by hardware when an invalid stop bit is detected.

7

FE

SMOD0 must be set to enable access to the FE bit

Serial port Mode bit 0

Refer to SM1 for serial port mode selection.

SMOD0 must be cleared to enable access to the SM0 bit

SM0

SM1

Serial port Mode bit 1

SM0 SM1 Mode

Description Baud Rate

Shift Register F /12 (/6 in X2 mode)

0

6

5

XTAL

0

1

0

1

2

3

8-bit UART Variable

9-bit UART /64 or F

9-bit UART Variable

F

/32 (/32 or 16 in X2 mode)

XTAL

Serial port Mode 2 bit / Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature.

Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should

be cleared in mode 0.

SM2

Reception Enable bit

4

3

REN

TB8

Clear to disable serial reception.

Set to enable serial reception.

Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

Receiver Bit 8 / Ninth bit received in modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

2

RB8

In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.

Transmit Interrupt ﬂag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other

modes.

1

0

TI

RI

Receive Interrupt ﬂag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, see Figure 14. and Figure 15. in the other modes.

Reset Value = 0000 0000b

Bit addressable

35

Rev. F - 15 February, 2001

T89C51RD2

Table 16. PCON Register

PCON - Power Control Register (87h)

7

6

5

-

4

3

2

1

0

SMOD1

SMOD0

POF

GF1

GF0

PD

IDL

Bit

Number

Bit

Mnemonic

Description

Serial port Mode bit 1

7

6

5

4

SMOD1

SMOD0

-

Set to select double baud rate in mode 1, 2 or 3.

Serial port Mode bit 0

Clear to select SM0 bit in SCON register.

Set to to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag

Clear to recognize next reset type.

POF

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.

General purpose Flag

3

2

1

0

GF1

GF0

PD

Cleared by user for general purpose usage.

Set by user for general purpose usage.

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

Power-Down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle mode bit

IDL

Clear by hardware when interrupt or reset occurs.

Set to enter idle mode.

Reset Value = 00X1 0000b

Not bit addressable

Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit.

Rev. F - 15 February, 2001

36

T89C51RD2

6.7. Interrupt System

The T89C51RD2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts

(timers 0, 1 and 2), the serial port interrupt and the PCA global interrupt. These interrupts are shown in Figure 16.

High priority

interrupt

IPH, IP

3

INT0

IE0

IE1

0

3

0

3

0

3

TF0

Interrupt

polling

sequence, decreasing

from high to low priority

INT1

TF1

0

3

PCA IT

0

3

0

RI

TI

3

TF2

EXF2

0

Low priority

interrupt

Individual Enable

Global Disable

Figure 16. Interrupt Control System

Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt

Enable register (See Table 18.). This register also contains a global disable bit, which must be cleared to disable

all interrupts at once.

Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing

a bit in the Interrupt Priority register (See Table 19.) and in the Interrupt Priority High register (See Table 20.).

shows the bit values and priority levels associated with each combination.

The PCA interrupt vector is located at address 0033H. All other vectors addresses are the same as standard C52

devices.

Rev. F - 15 February, 2001

37

T89C51RD2

Table 17. Priority Level Bit Values

IP.x

IPH.x

Interrupt Level Priority

0

1

0

1

0

1

0 (Lowest)

1

2

3 (Highest)

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt.

A high-priority interrupt can’t be interrupted by any other interrupt source.

If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level

is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence

determines which request is serviced. Thus within each priority level there is a second priority structure determined

by the polling sequence.

Table 18. IE Register

IE - Interrupt Enable Register (A8h)

7

6

5

4

3

2

1

0

EA

EC

ET2

ES

ET1

EX1

ET0

EX0

Bit

Number

Bit

Mnemonic

Description

Enable All interrupt bit

Clear to disable all interrupts.

Set to enable all interrupts.

7

EA

If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt

enable bit.

PCA interrupt enable bit

6

5

EC

Clear to disable . Set to enable.

Timer 2 overﬂow interrupt Enable bit

Clear to disable timer 2 overﬂow interrupt.

Set to enable timer 2 overﬂow interrupt.

ET2

Serial port Enable bit

4

3

2

1

0

ES

Clear to disable serial port interrupt.

Set to enable serial port interrupt.

Timer 1 overﬂow interrupt Enable bit

Clear to disable timer 1 overﬂow interrupt.

Set to enable timer 1 overﬂow interrupt.

ET1

EX1

ET0

EX0

External interrupt 1 Enable bit

Clear to disable external interrupt 1.

Set to enable external interrupt 1.

Timer 0 overﬂow interrupt Enable bit

Clear to disable timer 0 overﬂow interrupt.

Set to enable timer 0 overﬂow interrupt.

External interrupt 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

Reset Value = 0000 0000b

Bit addressable

38

Rev. F - 15 February, 2001

T89C51RD2

Table 19. IP Register

IP - Interrupt Priority Register (B8h)

7

-

6

5

4

3

2

1

0

PPC

PT2

PS

PT1

PX1

PT0

PX0

Bit

Number

Bit

Mnemonic

Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

PCA interrupt priority bit

PPC

PT2

PS

Refer to PPCH for priority level.

Timer 2 overﬂow interrupt Priority bit

Refer to PT2H for priority level.

Serial port Priority bit

Refer to PSH for priority level.

Timer 1 overﬂow interrupt Priority bit

PT1

PX1

PT0

PX0

Refer to PT1H for priority level.

External interrupt 1 Priority bit

Refer to PX1H for priority level.

Timer 0 overﬂow interrupt Priority bit

Refer to PT0H for priority level.

External interrupt 0 Priority bit

Refer to PX0H for priority level.

Reset Value = X000 0000b

Bit addressable

Rev. F - 15 February, 2001

39

T89C51RD2

Table 20. IPH Register

IPH - Interrupt Priority High Register (B7h)

7

-

6

5

4

3

2

1

0

PPCH

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

Bit

Number

Bit

Mnemonic

Description

Reserved

7

-

The value read from this bit is indeterminate. Do not set this bit.

PCA interrupt priority bit high.

PPCHPPC

Priority Level

Lowest

0

1

0

1

0

1

6

PPCH

Highest

Timer 2 overﬂow interrupt Priority High bit

PT2HPT2

Priority Level

Lowest

0

1

0

1

0

1

5

4

3

2

1

0

PT2H

PSH

Highest

Serial port Priority High bit

PSHPS Priority Level

0

1

0

1

0

1

Lowest

Highest

Timer 1 overﬂow interrupt Priority High bit

PT1HPT1

Priority Level

Lowest

0

1

0

1

0

1

PT1H

PX1H

PT0H

PX0H

Highest

External interrupt 1 Priority High bit

PX1HPX1

Priority Level

Lowest

0

1

0

1

0

1

Highest

Timer 0 overﬂow interrupt Priority High bit

PT0HPT0

Priority Level

Lowest

0

1

0

1

0

1

Highest

External interrupt 0 Priority High bit

PX0HPX0 Priority Level

Lowest

0

1

0

1

0

1

Highest

Reset Value = X000 0000b

Not bit addressable

40

Rev. F - 15 February, 2001

T89C51RD2

6.8. Idle mode

An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode.

In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port

functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word,

Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had

at the time Idle was activated. ALE and PSEN hold at logic high levels.

There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by

hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to

be executed will be the one following the instruction that put the device into idle.

The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or

during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is

terminated by an interrupt, the interrupt service routine can examine the flag bits.

The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running,

the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.

6.9. Power-Down Mode

To save maximum power, a power-down mode can be invoked by software (refer to Table 13, PCON register).

In power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last

instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated.

V

can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from

CC

power-down. To properly terminate power-down, the reset or external interrupt should not be executed before V

CC

is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize.

Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled

and configured as level or edge sensitive interrupt input.

Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 17..

When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power

down exit will be completed when the first input will be released. In this case the higher priority interrupt service

routine is executed.

Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction

that put Lynx/Fox into power-down mode.

INT0

INT1

XTAL1

Active phase

Power-down phase

Oscillator restart phase

Active phase

Figure 17. Power-Down Exit Waveform

Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect

the SFRs.

Exit from power-down by either reset or external interrupt does not affect the internal RAM content.

NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt,

PD and IDL bits are cleared and idle mode is not entered.

Rev. F - 15 February, 2001

41

T89C51RD2

This table shows the state of ports during idle and power-down modes.

Program

Memory

Mode

ALE

PSEN

PORT0

PORT1

PORT2

PORT3

Idle

Internal

External

Internal

External

1

0

1

0

Port Data*

Floating

Port Data

Address

Port Data

Idle

Power Down

Port Dat*

Floating

Port Data

* Port 0 can force a 0 level. A "one" will leave port floating.

42

Rev. F - 15 February, 2001

T89C51RD2

6.10. Hardware Watchdog Timer

The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The

WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default

disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST,

SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running

and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When

WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.

6.10.1. Using the WDT

To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When

WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow.

The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled,

it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at

least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST

is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an

output RESET pulse at the RST-pin. The RESET pulse duration is 96 x T

, where T

= 1/F

. To make

OSC

the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within

the time required to prevent a WDT reset.

7

To have a more powerful WDT, a 2 counter has been added to extend the Time-out capability, ranking from

16ms to 2s @ F

= 12MHz. To manage this feature, refer to WDTPRG register description, Table 22. (SFR0A7h).

OSC

Table 21. WDTRST Register

WDTRST Address (0A6h)

7

6

5

4

3

2

1

Reset value

X

Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.

Rev. F - 15 February, 2001

43

T89C51RD2

Table 22. WDTPRG Register

WDTPRG Address (0A7h)

7

6

5

4

3

2

1

0

T4

T3

T2

T1

T0

S2

S1

S0

Bit

Number

Bit

Mnemonic

Description

7

6

5

4

3

2

1

0

T4

T3

T2

T1

T0

S2

S1

S0

Reserved

The value read from this bit is undeterminated. Do not try to set this bit..

WDT Time-out select bit 2

WDT Time-out select bit 1

WDT Time-out select bit 0

S2

0

S1S0

0 0

0 1

1 0

1 1

0 0

0 1

1 0

1 1

Selected Time-out

14

(2 - 1) machine cycles, 16.3 ms @ 12 MHz

15

0

(2 - 1) machine cycles, 32.7 ms @ 12 MHz

16

0

(2 - 1) machine cycles, 65.5 ms @ 12 MHz

17

0

(2 - 1) machine cycles, 131 ms @ 12 MHz

18

1

(2 - 1) machine cycles, 262 ms @ 12 MHz

19

1

(2 - 1) machine cycles, 542 ms @ 12 MHz

20

1

(2 - 1) machine cycles, 1.05 s @ 12 MHz

21

1

(2 - 1) machine cycles, 2.09 s @ 12 MHz

Reset value XXXX X000

6.10.2. WDT during Power Down and Idle

In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the

user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset

or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power

Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the T89C51RD2

is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for

the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from

resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.

It is suggested that the WDT be reset during the interrupt service routine.

To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the

WDT just before entering powerdown.

In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the T89C51RD2 while in

Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter

Idle mode.

If the WDT is activated, the power consumption in stand-by mode will be above the specified value.

44

Rev. F - 15 February, 2001

T89C51RD2

(TM)

6.11. ONCE

Mode (ON Chip Emulation)

The ONCE mode facilitates testing and debugging of systems using T89C51RD2 without removing the circuit

from the board. The ONCE mode is invoked by driving certain pins of the T89C51RD2; the following sequence

must be exercised:

•

Pull ALE low while the device is in reset (RST high) and PSEN is high.

Hold ALE low as RST is deactivated.

While the T89C51RD2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit. Table 23.

shows the status of the port pins during ONCE mode.

Normal operation is restored when normal reset is applied.

Table 23. External Pin Status during ONCE Mode

ALE

PSEN

Port 0

Port 1

Port 2

Port 3

XTAL1/2

Weak pull-up

Float

Weak pull-up

Active

(a) "Once" is a registered trademark of Intel Corporation.

Rev. F - 15 February, 2001

45

T89C51RD2

6.12. Reduced EMI Mode

The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data

memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE

signal can be disabled by setting AO bit.

The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but

remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is

weakly pulled high.

Table 24. AUXR Register

AUXR - Auxiliary Register (8Eh)

7

-

6

-

5

4

-

3

2

1

0

M0

XRS1

XRS0

EXTRAM

AO

Bit

Number

Bit

Mnemonic

Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

7

6

5

4

3

2

1

-

Reserved

-

M0

The value read from this bit is indeterminate. Do not set this bit.

M0 bit: Pulse length in clock period

Stretch MOVX control: the RD/ and the WR/ pulse length is increased according to the value of M0. see table 6

Reserved

The value read from this bit is indeterminate. Do not set this bit.

-

XRS1 bit

XRAM size: Accessible size of the XRAM. See Table 6.

XRS1

XRS0

EXTRAM

XRS0 bit

XRAM size: Accessible size of the XRAM. Table 6.

EXTRAM bit

See Table 6.

ALE Output bit

0

AO

Clear to restore ALE operation during internal fetches.

Set to disable ALE operation during internal fetches.

Reset Value = XX0X 1000b

Not bit addressable

Rev. F - 15 February, 2001

46

T89C51RD2

7. EEPROM data memory

7.1. General description

The EEPROM memory block contains 2048 bytes and is organized in 32 pages (or rows) of 64 bytes. The necessary

high programming voltage is generated on-chip using the standard Vcc pin of the microcontroller.

The EEPROM memory block is located at the addresses 0000h to 07FFh of the XRAM memory space and is

selected by setting control bits in the EECON register.

A read in the EEPROM memory is done with a MOVX instruction.

A physical write in the EEPROM memory is done in two steps : write data in the column latches and transfer of

all data latches in a EEPROM memory row (programming).

The number of data written in the page may vary from 1 to 64 (the page size). When programming, only the data

written in the column latch are programmed. This provides the capability to program the whole memory by bytes,

by page or by a number of bytes in a page.

7.2. Write Data in the column latches

Data is written by byte to the column latches as if it was in an external RAM memory. Out of the 16 address bits

of the data pointer, the 10 MSB are used for page selection and 6 are used for byte selection. Between two

EEPROM programming, all addresses in the column latches must remain in the same page, thus the 10MSB must

be unchanged.

The following procedure is used to write in the colums latches :

•

Map the program space (Set bit EEE of EECON register)

Load DPTR with the address to write

Load A register with the data to be written

Execute a MOVX @DPTR, A

If needed loop the three last instructions until the end of a 64bytes page

7.3. Programming

The EEPROM programming consists on the following actions :

•

write one or more bytes in a page in the column latches. Normally, all bytes must belong to the same page;

if this is not the case, the first page address is latched and the others are discarded.

•

Set EETIM with the value corresponding to the XTAL frequency.

Launch the programming by writing the control sequence (52h or 50h followed by A2h or A0h) to the EECON

register (see Table 25).

•

EEBUSY flag in EECON is then set by hardware to indicate that programming is in progress and that EEPROM

segment is not available for read.

The end of programming is signaled by a hardware clear of the EEBUSY flag.

Rev. F - 15 February, 2001

47

T89C51RD2

Example : .....

; DPTR = EEPROM data pointer, A = Data to write

Wait : MOV A,EECON

ANL

JNZ

A,#01h

Wait

MOV EETIM,#3Ch

MOV EECON,#02h

MOVX @DPTR,A

; 12MHz*5 = 3Ch

; EEE=1 EEPROM mapped

; Write data to EEPROM

MOV EECON,#50h or 52h ; Write Sequence

MOV EECON,#A0h or A2h

....

7.4. Read Data

The following procedure is used to read the data store in the EEPROM memory:

•

Map the program space (Set bit EEE of EECON register)

Load DPTR with the address to read

Execute a MOVX A, @DPTR

Example :

...

; DPTR = EEPROM data pointer

; EEE=1 EEPROM mapped

; Read data from EEPROM

; A = Data

MOV EECON,#02h

MOVX A,@DPTR

...

7.5. Registers

Table 25. EECON Register

EECON (S:0D2h)

EEPROM Control Register

7

6

5

4

3

-

2

-

1

0

EEPL3

EEPL2

EEPL1

EEPL0

EEE

EEBUSY

Bit Number Bit Mnemonic

Description

Programming Launch command bits

7-4

EEPL3-0

Write 5Xh followed by AXh to EECON to launch the programming.

a

3

2

-

Not implemented, reserved for future use.

b

Not implemented, reserved for future use.

Enable EEPROM Space bit

Set to map the EEPROM space during MOVX instructions (Write in the column latches)

Clear to map the data space during MOVX.

1

0

EEE

Programming Busy flag

Set by hardware when programming is in progress.

Cleared by hardware when programming is done.

Can not be set or cleared by software.

EEBUSY

a. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In

that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is

indeterminate.

b. User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new features. In

that case, the reset or inactive value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is

indeterminate.

Reset Value= XXXX XX00b

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Rev. F - 15 February, 2001

T89C51RD2

Table 26. EETIM Register

EETIM (S:0D3h)

EEPROM timing Control Register

7

6

5

4

3

2

1

0

EETIM

Bit Number Bit Mnemonic

Description

Write Timer Register

The write timer register value is required to adapt the write time to the oscillator frequency

Value = 5 * Fxtal (MHz) in normal mode, 10 * Fxtal in X2 mode.

Example : Fxtal = 33 MHZ, EETIM = 0A5h

7-0

EETIM

Reset Value= 0000 0000b

Rev. F - 15 February, 2001

49

T89C51RD2

8. FLASH EEprom Memory

8.1. General description

The FLASH memory increases EPROM and ROM functionality with in-circuit electrical erasure and programming.

It contains 64K bytes of program memory organized in 512 pages of 128 bytes. This memory is both parallel and

serial In-System Programmable (ISP). ISP allows devices to alter their own program memory in the actual end

product under software control. A default serial loader (bootloader) program allows ISP of the FLASH.

The programming does not require 12v external programming voltage. The necessary high programming voltage

is generated on-chip using the standard V pins of the microcontroller.

CC

8.2. Features

•

FLASH E2PROM internal program memory.

The last 1K bytes of the FLASH is used to store the low-level in-system programming routines and a default

serial loader. If the application does not need to use the ISP and does not expect to modify the FLASH content,

the Boot FLASH sector can be erased to provide access to the full 64K byte FLASH memory.

•

Boot vector allows user provided FLASH loader code to reside anywhere in the FLASH memory space. This

configuration provides flexibility to the user.

•

Default loader in Boot FLASH allows programming via the serial port without the need of a user provided loader.

Up to 64K byte external program memory if the internal program memory is disabled (EA = 0).

Programming and erase voltage with standard 5V or 3V V supply.

CC

Read/Programming/Erase:

•

Byte-wise read (without wait state).

Byte or page erase and programming (10 ms).

Typical programming time (63K bytes) in 20 s.

•

Parallel programming with 87C51 compatible hardware interface to programmer.

Programmable security for the code in the FLASH.

100k write cycles

10 years data retention

8.3. FLASH Programming and Erasure

The 64K bytes FLASH is programmed by bytes or by pages of 128 bytes. It is not necessary to erase a byte or

a page before programming. The programming of a byte or a page includes a self erase before programming.

There are three methods to program the FLASH memory:

•

First, the on-chip ISP bootloader may be invoked which will use low level routines to program the pages. The

interface used for serial downloading of FLASH is the UART.

Second, the FLASH may be programmed or erased in the end-user application by calling low-level routines

through a common entry point in the Boot loader.

Third, the FLASH may be programmed using the parallel method by using a conventional EPROM programmer.

The parallel programming method used by these devices is similar to that used by EPROM 87C51 but it is not

identical and the commercially available programmers need to have support for the T89C51RD2.

Rev. F - 15 February, 2001

50

T89C51RD2

The bootloader and the In Application Programming (IAP) routines are located in the last kilobyte of the FLASH,

leaving 63k bytes available for the application with ISP.

8.4. FLASH registers and memory map

The T89C51RD2 FLASH memory uses several registers for his management:

•

Flash control register is used to select the Flash memory spaces and launch the Flash programming sequence.

Hardware registers can only be accessed through the parallel programming modes which are handled by the

parallel programmer.

•

Software registers are in a special page of the FLASH memory which can be accessed through the API or with

the parallel programming modes. This page, called "Extra FLASH Memory", is not in the internal FLASH

program memory addressing space.

8.4.1. FLASH register

FCON (S:D1h)

FLASH control register

7

6

5

4

3

2

1

0

FPL3

FPL2

FPL1

FPL0

FPS

FMOD1

FMOD0

FBUSY

Bit Number Bit Mnemonic

Description

Programming Launch command bits

7-4

FPL3:0

Write 5h followed by Ah to launch the programming.

FLASH Map Program Space

Clear to map the data space during MOVX

Set to map the FLASH space during MOVX (write) or MOVC (read) instructions (Write in the

column latches)

3

FPS

FLASH Mode

Select the addressed space

00: User (0000h-FFFFh)

01: XAF

10: Hardware byte

11: reserved

2-1

FMOD1:0

FBUSY

FLASH Busy

Set by hardware when programming is in progress.

Clear by hardware when programming is done.

Can not be cleared by software

0

Reset Value = xxxx 0000b

Figure 18. FCON register

The Flash programming application note and API source code are available on request.

8.4.2. Hardware register

The only hardware register of the T89C51RD2 is called Hardware Security Byte (HSB). After full FLASH erasure,

the content of this byte is FFh; each bit is active at low level.

51

Rev. F - 15 February, 2001

T89C51RD2

Table 27. Hardware Security Byte (HSB)

7

6

5

4

-

3

-

2

1

0

SB

BLJB

BLLB

LB2

LB1

LB0

Bit

Number

Bit

Mnemonic

Description

Safe Bit

7

SB

This bit must be cleared to secure the content of the HSB. Only security level can be increased.

Boot loader Jump Bit

Set to force hardware boot address at 0000h. (unless previously force by hardware conditions as

described in the chapter 9.6).

Clear to force hardware boot address at FC03h (default).

6

5

BLJB

BLLB

Boot loader Lock Bit

Set to allow programming and writing of the boot loader segment.

Clear to forbid software programming and writing of the boot loader segment (default). This protection protect

only ISP or IAP access; protection through parallel access is done globally by the lock bits LB2-0.

Reserved

4

3

-

Do not clear this bit.

Reserved

Do not clear this bit.

User Memory Lock Bits

2-0

LB2-0

See Table 29

8.4.2.1. Boot Loader Lock Bit (BLLB)

One bit of the HSB is used to secure by hardware the internal boot loader sector against software reprogramming.

When the BLLB is cleared, any attempt to write in the boot loader segment (Address FC00h to FFFFh) will have

no effect. This protection applies for software writing only.

Boot Loader Jump Bit (BLJB)

One bit of the HSB, the BLJB bit, is used to force the boot address:

•

When this bit is set the boot address is 0000h.

When this bit is reset the boot address is FC03h. By default, this bit is cleared and the ISP is enabled.

8.4.2.2. FLASH memory lock bits

The three lock bits provide different levels of protection for the on-chip code and data, when programmed according

to Table 29.

Rev. F - 15 February, 2001

52

T89C51RD2

Table 28. Program Lock bits

Protection description

Program Lock Bits

Security

LB0 LB1 LB2

level

No program lock features enabled. MOVC instruction executed from external program

memory returns non encrypted data.

1

2

U

MOVC instruction executed from external program memory are disabled from fetching

code bytes from internal memory, EA is sampled and latched on reset, and further

parallel programming of the FLASH is disabled.ISP and software programming with

API are still allowed.

P

U

3

4

X

P

U

P

Same as 2, also verify through parallel programming interface is disabled.

Same as 3, also external execution is disabled.

X

U: unprogrammed or "one" level.

P: programmed or "zero" level.

X:do not care

WARNING: Security level 2 and 3 should only be programmed after FLASH and code verification.

These security bits protect the code access through the parallel programming interface. They are set by default to

level 4. The code access through the ISP is still possible and is controlled by the "software security bits" which

are stored in the extra FLASH memory accessed by the ISP firmware.

To load a new application with the parallel programmer, a chip erase must first be done. This will set the HSB

in its inactive state and will erase the FLASH memory, including the boot loader and the "Extra FLASH Memory"

(XAF). If needed, the 1K boot loader and the XAF content must be programmed in the FLASH; the code is

provided by ATMEL Wireless and Microcontrollers (see section 8.7. ); the part reference can always be read using

FLASH parallel programming modes.

8.4.2.3. Default values

The default value of the HSB provides parts ready to be programmed with ISP:

•

SB: Cleared to secure the content of the HSB.

BLJB: Cleared to force ISP operation.

BLLB: Clear to protect the default boot loader.

LB2-0: Security level four to protect the code from a parallel access with maximum security.

8.4.3. Software registers

Several registers are used, in factory and by parallel programmers, to make copies of hardware registers contents.

These values are used by ATMEL Wireless and Microcontrollers ISP (see section 8.7. ).

These registers are in the "Extra FLASH Memory" part of the FLASH memory. This block is also called "XAF"

or eXtra Array FLASH. They are accessed in the following ways:

•

Commands issued by the parallel memory programmer.

Commands issued by the ISP software.

Calls of API issued by the application software.

53

Rev. F - 15 February, 2001

T89C51RD2

They are several software registers described in Table 29

Table 29. Default values

Mnemonic

BSB

Default value

FFh

Boot Status Byte

SBV

FCh

Software Boot Vector

HSB

18h or 1Bh

FFh

Copy of the Hardware security byte

Software Security Byte

SSB

Copy of the Manufacturer Code

ATMEL Wireless and

Microcontrollers

58h

D7h

FCh

C51 X2, Electrically Erasable

T89C51RD2 memories size

Copy of the Device ID #1: Family Code

Copy of the Device ID #2: memories

size and type

T89C51RD2, revision 0

Copy of the Device ID # 3: name and revi-

sion

FFh

After programming the part by ISP, the BSB must be reset (00h) in order to allow the application to boot at 0000h.

The content of the Software Security Byte (SSB) is described in Table 30 and Table 31

To assure code protection from a parallel access, the HSB must also be at the required level.

Table 30. Software Security Byte (SSB)

7

-

6

-

5

-

4

3

-

2

-

1

-

0

LB1

LB0

Bit

Number

Bit

Mnemonic

Description

Reserved

Do not clear this bit.

7

6

-

Reserved

Do not clear this bit.

-

Reserved

5

Do not clear this bit.

User Memory Lock Bit

4

LB1

-

See Table 31

Reserved

1-3

0

Do not clear this bit.

User Memory Lock Bit

LB0

See Table 31

The three lock bits provide different levels of protection for the on-chip code and data, when programmed according

to Table 31.

Rev. F - 15 February, 2001

54

T89C51RD2

Table 31. Program Lock bits of the SSB

Protection description

Program Lock Bits

Security

LB0 LB1

level

1

U

No program lock features enabled.

following commands are disabled:

- program byte

- program status byte and boot vector

- erase status byte and boot vector

2

P

U

Same as 2 and following commands also disabled:

- read byte

3

X

P

- read status byte and boot vector

- blank check

- program SSB level2

U: unprogrammed or "one" level.

P: programmed or "zero" level.

X:do not care

WARNING: Security level 2 and 3 should only be programmed after FLASH and code verification.

8.5. FLASH memory status

T89C51RD2 parts are delivered in standard with the ISP boot in the FLASH memory. After ISP or parallel

programming, the possible contents of the FLASH memory are summarized on the figure below:

Figure 19. FLASH memory possible contents

Boot

FC00h

Virgin

Application

Virgin

or appli

Application

Virgin

or appli

Virgin

or appli

Dedicated

ISP

Dedicated

ISP

0000h

After parallel

programming

After parallel

programming

After parallel

programming

After ISP

Default

After ISP

8.6. Boot process

Boot loader FLASH

When the user application programs its own FLASH memory, all of the low level details are handled by a code

that is permanently contained in a 1k byte “Boot FLASH” and is located in the last kilobyte of the FLASH memory

from FC00h to FFFFh (See Figure 20). A user program simply calls the common entry point in the Boot FLASH

with appropriate parameters to accomplish the desired operation. Boot FLASH operations include functions like:

55

Rev. F - 15 February, 2001

T89C51RD2

erase block, program byte or page, verify byte or page, program security lock bit, etc. The Boot FLASH can be

locked to prevent erasing. If erased, the Boot FLASH can be restored by parallel programming. Indeed, ATMEL

Wireless and Microcontrollers provides the binary code of the default FLASH boot loader (see section 8.7. ).

Entry point for API

FFF0

Status byte check

ISP start

FC03

FC00

Figure 20. Boot loader memory map

Reset Code Execution

At the falling edge of reset (unless the hardware conditions on PSEN, EA and ALE are set as described below),

the T89C51RD2 reads the BLJB bit in the HSB byte. If this bit is set, it jumps to 0000h and if not, it jumps to

FC03h. At this address, the boot software reads two special FLASH registers: the Software Boot Vector (SBV)

and the Boot Status Byte (BSB). If the BSB is set to zero, power-up execution starts at location 0000h, which is

the normal start address of the user’s application code. When the Status Byte is set to a value other than zero, the

contents of the Boot Vector is used as the high byte of the execution address and the low byte is set to 00h. The

factory default setting is FCh, corresponding to the address FC00h for the factory default FLASH ISP boot loader.

A custom boot loader can be written with the Boot Vector set to the custom boot loader address.

It is recommanded to set the BSB before any other IAP so the device automatically resumes ISP when reset. ISP

routines shall only clear BSB after succesfull IAP completion.

Hardware Activation of the Boot Loader

The default boot loader can also be executed by holding PSEN LOW, EA HIGH, and ALE HIGH (or not connected)

at the falling edge of RESET. This has the same effect as having a non-zero status byte anf the Boot Vector equal

to FCh. This allows an application to be built that will normally execute the end user’s code but can be manually

forced into default ISP operation.

As PSEN has the same structure as P1-P3, the current to force PSEN to 0 as ITL is defined in the DC parameters.

If the factory default setting for the Boot Vector (FCh) is changed, it will no longer point to the ISP default

FLASH boot loader code. It can be restored:

•

With the default ISP activated with hardware conditions on PSEN, EA and ALE.

With a customized loader (in the end user application) that provides features for erasing and reprogramming

of the Boot Vector and BSB.

•

Through the parallel programming method.

After programming the FLASH, the status byte should be programmed to zero in order to allow execution of the

user’s application code beginning at address 0000h.

Rev. F - 15 February, 2001

56

T89C51RD2

Boot process summary

The boot process is summarized on the following flowchart:

Reset Falling Edge

Yes (PSEN =0, EA =1, and ALE =1 or not connected)

Hardware

Conditions

?

No

Yes

BLJB = 1

?

No

Hardware

Software

Jump to FC03h

BSB= 0

BSB ?

Jump to 0000h

BSB ≠ 00h

USER APPLICATION

SBV= FCh

Software

Boot Vector ?

Jump to FC00h

SBV ≠ FCh = XXh

DEFAULT BOOT

LOADER

Jump to XX00h

CUSTOM BOOT

LOADER

- BSB: Boot Status Byte

- BLJB: Boot Loader Jump Bit (Hardware Bit set to

0 by default)

Figure 21. Boot process flowchart

57

Rev. F - 15 February, 2001

T89C51RD2

8.7. In-System Programming (ISP)

The In-System Programming (ISP) is performed without removing the microcontroller from the system. The In-

System Programming (ISP) facility consists of a series of internal hardware resources coupled with internal firmware

to facilitate remote programming of the T89C51RD2 through the serial port. This firmware is embedded within

each T89C51RD2 device going out of factory.

The ATMEL Wireless and Microcontrollers In-System Programming (ISP) facility has made in-circuit programming

in an embedded application possible with a minimum of additional expense in components and circuit board area.

The ISP function uses four pins: TxD, RxD, V , V . Only a small connector needs to be available to interface

SS

CC

the application to an external circuit in order to use this feature. Application schematic can found be in the

demonstration and ISP board user manual.

Using the In-System Programming (ISP)

The ISP feature allows a wide range of baud rates in the user application. It is also adaptable to a wide range of

oscillator frequencies. This is accomplished by measuring the bit-time of a single bit in a received character. This

information is then used to program the baud rate in terms of timer counts based on the oscillator frequency. The

ISP feature requires that an initial character (an uppercase U) be sent to the T89C51RD2 to establish the baud

rate. The ISP firmware provides auto-echo of received characters.

Once baud rate initialization has been performed, the ISP firmware will only accept Intel Hex-type records. Intel

Hex records consist of ASCII characters used to represent hexadecimal values and are summarized below:

:NNAAAARRDD..DDCC<crlf>

In the Intel Hex record, the “NN” represents the number of data bytes in the record. The T89C51RD2 will accept

up to 16 (10h) data bytes. The “AAAA” string represents the address of the first byte in the record. If there are

zero bytes in the record, this field is often set to ‘‘0000’’. The “RR” string indicates the record type. A record

type of “00” is a data record. A record type of “01” indicates the end-of-file mark. In this application, additional

record types will be added to indicate either commands or data for the ISP facility. The “DD” string represents

the data bytes. The maximum number of data bytes in a record is limited to 16 (decimal). The “CC” string

represents the checksum byte. ISP commands are summarized in Table 32.

As a record is received by the T89C51RD2, the information in the record is stored internally and a checksum

calculation is performed and compared to ‘‘CC’’.

The operation indicated by the record type is not performed until the entire record has been received. Should an

error occur in the checksum, the T89C51RD2 will send an “X” out the serial port indicating a checksum error. If

the checksum calculation is found to match the checksum in the record, then the command will be executed. In

most cases, successful reception of the record will be indicated by transmitting a “.” character out the serial port

(displaying the contents of the internal program memory is an exception).

In the case of a Data Record (record type ‘‘00’’), an additional check is made. A “.” character will NOT be sent

unless the record checksum matched the calculated checksum and all of the bytes in the record were successfully

programmed. For a data record, an “X” indicates that the checksum failed to match, and an “R” character indicates

that one of the bytes did not properly program.

ATMEL Wireless and Microcontrollers_ISP, a software utility to implement ISP programming with a PC, is

available from ATMEL Wireless and Microcontrollers. Please visit our web site http://www.atmel-wm.com.

Rev. F - 15 February, 2001

58

T89C51RD2

Table 32. Intel-Hex Records Used by In-System Programming

RECORD TYPE

COMMAND/DATA FUNCTION

Data Record

:nnaaaa00dd....ddcc

Where:

Nn = number of bytes (hex) in record

00

aaaa = memory address of first byte in record

dd....dd = data bytes

cc = checksum

Example:

:05008000AF5F67F060B6 (program address 80h to 85h with data AF ... 60)

End of File (EOF), no operation

:xxxxxx01cc

Where:

01

xxxxxx = required field, but value is a “don’t care”

cc = checksum

Example:

:00000001FF

Specify Oscillator Frequency (Not required, left for Philips compatibility)

:01xxxx02ddcc

Where:

xxxx = required field, but value is a “don’t care”

dd = required field, but value is a “don’t care”

cc = checksum

02

Example:

:0100000210ED

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Rev. F - 15 February, 2001

T89C51RD2

Table 32. Intel-Hex Records Used by In-System Programming

Miscellaneous Write Functions

:nnxxxx03ffssddcc

Where:

nn = number of bytes (hex) in record

xxxx = required field, but value is a “don’t care”

03 = Write Function

ff = subfunction code

ss = selection code

dd = data input (as needed)

cc = checksum

Subfunction Code = 04 (Reset Boot Vector and Status Byte)

ff = 04

ss = don’t care

dd = don’t care

Example:

:020000030400F8 Reset boot vector (FCh) and status byte (FFh)

Subfunction Code = 05 (Program Software Security Bits)

ff = 05

03

ss = 00 program software security bit 1 (Level 2 inhibit writing to FLASH)

ss = 01 program software security bit 2 (Level 3 inhibit FLASH verify)

ss = 02 program security bit 3 (No effect, left for Philips compatibity; disable external memory is already set

in the default hardware security byte)

Example:

:020000030501F6 program security bit 2

Subfunction Code = 06 (Program Status Byte or Boot Vector)

ff = 06

ss = 00 program BSB

ss = 01 program boot vector

Example:

:03000003060100F5 program boot vector with 00

Subfunction Code = 07 (Full chip erase)

ff = 07

Example:

:0100000307F5 full chip erase (include boot vector / status byte and software security bit erase)

Display Device Data or Blank Check

Record type 04 causes the contents of the entire FLASH array to be sent out the serial port in a formatted

display. This display consists of an address and the contents of 16 bytes starting with that address. No display

of the device contents will occur if security bit 2 has been programmed. The dumping of the device data to

the serial port is terminated by the reception of any character.

General Format of Function 04

:05xxxx04sssseeeeffcc

Where:

05 = number of bytes (hex) in record

xxxx = required field, but value is a “don’t care”

04 = “Display Device Data or Blank Check” function code

ssss = starting address

04

eeee = ending address

ff = subfunction

00 = display data

01 = blank check

cc = checksum

Example:

:0500000440004FFF0069 (display 4000–4FFF)

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60

T89C51RD2

Table 32. Intel-Hex Records Used by In-System Programming

Miscellaneous Read Functions

General Format of Function 05

:02xxxx05ffsscc

Where:

02 = number of bytes (hex) in record

xxxx = required field, but value is a “don’t care”

05= “Miscellaneous Read” function code

ffss = subfunction and selection code

0000 = read copy of the signature byte – manufacturer id (58H)

0001 = read copy of the signature byte – device ID# 1 (Family code)

0002 = read copy of the signature byte – device ID # 2 (Memories size and type)

0003 = read copy of the signature byte – device ID # 3 (Product name and revision)

0700 = read the software security bits

05

0701 = read status byte (BSB)

0702 = read Boot Vector (SBV)

0703 = read copy of the HSB

0800 = read bootloader version

cc = checksum

Example:

:020000050001F0 read copy of the signature byte – device id # 1

8.8. In-Application Programming Method

Several Application Program Interface (API) calls are available for use by an application program to permit selective

erasing and programming of FLASH pages. All calls are made through a common interface, PGM_MTP. The

programming functions are selected by setting up the microcontroller’s registers before making a call to PGM_MTP

at FFF0h. Results are returned in the registers. The API calls are shown in Table 33.

A set of Philips compatible API calls is provided.

When several bytes have to be programmed, it is highly recommanded to use the ATMEL Wireless and

Microcontrollers API “PROGRAM DATA PAGE” call. Indeed, this API call writes up to 128 bytes in a single

command.

Table 33. API calls

API call

Parameter

Input Parameters:

R0 = osc freq (integer Not required, left for Philips compatibility)

R1 = 02h

DPTR = address of byte to program

ACC = byte to program

PROGRAM DATA BYTE

Return Parameter

ACC = 00 if pass, !00 if fail

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Rev. F - 15 February, 2001

T89C51RD2

Table 33. API calls

Input Parameters:

R0 = osc freq (integer Not required)

R1 = 09h

DPTR0 = address of the first byte to program in the FLASH memory

DPTR1 = address in XRAM of the first data to program (second data pointer)

ACC = number of bytes to program

PROGRAM DATA PAGE

Return Parameter

ACC = 00 if pass, !00 if fail

Remark: number of bytes to program is limited such as the FLASH write remains in a single 128bytes

page. Hence, when ACC is 128, valid values of DPL are 00h, or, 80h.

Input Parameters:

R0 = osc freq (integer Not required, left for Philips compatibility)

R1 = 04h

ERASE BOOT VECTOR

STATUS BYTE

DPH = 00h

DPL = don’t care

Return Parameter

none

Input Parameters:

R0 = osc freq (integer Not required, left for Philips compatibility)

R1 = 05h

DPH = 00h

PROGRAM SOFTWARE

SECURITY BIT

DPL = 00h – security bit # 1 (inhibit writing to FLASH)

01h – security bit # 2 (inhibit FLASH verify)

10h - allows ISP writing to FLASH*

11h - allows ISP FLASH verify*

Return Parameter

none

Input Parameters:

R0 = osc freq (integer Not required, left for Philips compatibility)

R1 = 06h

PROGRAM BOOT

STATUS BYTE

DPH = 00h

DPL = 00h – program status byte

ACC = status byte

Return Parameter

ACC = status byte

Input Parameters:

R0 = osc freq (integer Not required, left for Philips compatibility)

R1 = 06h

DPH = 00h

PROGRAM BOOT

VECTOR

DPL = 01h – program boot vector

ACC = boot vector

Return Parameter

ACC = boot vector

Input Parameters:

R1 = 03h

DPTR = address of byte to read

Return Parameter

READ DEVICE DATA

ACC = value of byte read

Input Parameters:

R0 = osc freq (integer Not required, left for Philips compatibility)

R1 = 00h

DPH = 00h

DPL = 00h (manufacturer ID)

Return Parameter

READ copy of the

MANUFACTURER ID

ACC = value of byte read

Rev. F - 15 February, 2001

62

T89C51RD2

Table 33. API calls

API call

Parameter

Input Parameters:

R0 = osc freq (integer Not required, left for Philips compatibility)

R1 = 00h

DPH = 00h

DPL = 01h (device ID # 1)

Return Parameter

ACC = value of byte read

READ copy of the device

ID # 1

Input Parameters:

R0 = osc freq (integer Not required, left for Philips compatibility)

R1 = 00h

DPH = 00h

DPL = 02h (device ID # 2)

Return Parameter

ACC = value of byte read

READ copy of the device

ID # 2

Input Parameters:

R0 = osc freq (integer Not required, left for Philips compatibility)

R1 = 00h

DPH = 00h

DPL = 03h (device ID # 2)

Return Parameter

ACC = value of byte read

READ copy of the device

ID # 3

Input Parameters:

R0 = osc freq (integer Not required, left for Philips compatibility)

R1 = 07h

DPH = 00h

DPL = 00h (Software security bits)

Return Parameter

READ SOFTWARE

SECURITY BITS

ACC = value of byte read

Input Parameters:

R0 = osc freq (integer Not required, left for Philips compatibility)

READ copy of the

HARDWARE SECURITY

BITS

R1 = 07h

DPH = 00h

DPL = 03h (Hardtware security bits)

Return Parameter

ACC = value of byte read

Input Parameters:

R0 = osc freq (integer Not required, left for Philips compatibility)

R1 = 07h

READ BOOT VECTOR

DPH = 00h

DPL = 02h (boot vector)

Return Parameter

ACC = value of byte read

Input Parameters:

R0 = osc freq (integer Not required, left for Philips compatibility)

R1 = 08h

Return Parameter

ACC = value of byte read

READ BOOTLOADER

VERSION

Input Parameters:

R0 = osc freq (integer Not required, left for Philips compatibility)

R1 = 07h

DPH = 00h

DPL = 01h (status byte)

Return Parameter

ACC = value of byte read

READ BOOT STATUS

BYTE

63

Rev. F - 15 February, 2001

T89C51RD2

Note: These functions can only be called by user’s code. The standard boot loader cannot decrease the security level.

8.9. FLASH Parallel Programming

8.9.1. Signature bytes

Four hardware read only registers have to be accessed with parallel static test modes (mode TMS) in order to

control the FLASH parallel programmimg:

•

Manufacturer code

Device ID # 1: Family code

Device ID # 2: Memories size and type

Device ID # 3: Name and revision

As these registers can only be accessed by hardware, they must be read by the parallel programmers and then

copied in the XAF in order to make their values accessible by software (ISP or API).

8.9.2. Set-up modes

In order to program and verify the FLASH or to read the signature bytes, the T89C51RD2 is placed in specific

set-up modes (See Figure 22).

Control and program signals must be held at the levels indicated in Table 37. and Table 38.(Please notice that

each mode is defined over the two tables

Rev. F - 15 February, 2001

64

T89C51RD2

Ale

_ _

|_|

Mode Name

Mode

Rst Psen

EA

P2.6

P2.7

P3.6

P3.7

P0[7..0]

Program or Erase Lock.

Disable the Erasure or Programming

access

_ _

|_|

PELCK

1

0

1

0

1

0

xx

Program or Erase UnLock.

Enable the Erasure or Programming

access

PEULCK

Note3

55-AA

_ _

|_|

Write Code Data (byte)

or write Page

PGMC

1

0

1

0

1

xx

Always precedeed by PGML

Internally

timed

Memory Page Load

(up to 128 bytes)

PGML

PGMV

1

0

Note2

1

0

1

Din

_ _

|_|

Read Code Data (byte)

Dout

_ _

|_|

VSB

Read Security Byte (=HSB)

1

0

1

0

1

Dout

Write Security Byte (Note 4)

(security byte = HSB)

PGMS

CERR

1

0

10ms

1

0

Din

xx

Chip Erase User + XAF

_ _

|_|

Write Byte or Page in Extra Memory

(XAF)

Always precedeed by PGXL

PGXC

1

0

1

0

1

xx

Internally

timed

Memory Page Load XAF

(up to 128 bytes)

PGXL

TMS

1

0

Note2

1

0

1

0

Din

Read Signature bytes

30h (Manufacturer code)

31h (Device ID #1)

60h (Device ID #2)

61h (Device ID #3)

Dout =

58h

D7h

FCh

FFh

_ _

|_|

_ _

|_|

Read Extra Memory

(XAF)

RXAF

1

0

1

0

Dout

65

Rev. F - 15 February, 2001

T89C51RD2

Mode Name

Mode

P1[7..0]

P2[5..0]

P3.0 P3.1

P3.2

P3.3 P3.4 P3.5

Program or Erase Lock.

Disable the Erasure or Programming

access

PELCK

xx

x

1

0

x

Program or Erase UnLock.

Enable the Erasure or Programming

access

PEULCK

xx

x

Write Code Data (byte)

or write Page

Always precedeed by PGML

PGMC

PGML

A7-A0

A13-A8

1

x

Note1

x

0

A14

A15

Memory Page Load

(up to 128 bytes)

PGMV

VSB

Read Code Data (byte)

A7-A0

xx

A13-A8

xx

1

x

1

A14

x

A15

x

Read Security Byte (=HSB)

Write lock Byte (Note 4)

(security byte = HSB)

PGMS

CERR

xx

1

x

Note1

x

0

x

Chip Erase User + XAF

Write Byte or Page Extra Memory

(XAF)

Always precedeed by PGXL

A7-A0

(0-7F)

PGXC

PGXL

xx

1

x

Note1

x

0

1

x

Memory Page Load XAF

(up to 128 bytes)

A7-A0

(0-7F)

Read Signature bytes

30h (Manufacturer code)

31h (Device ID #1)

60h (Device ID #2)

61h (Device ID #3)

30h

31h

60h

61h

TMS

x

1

x

1

0

x

Read Extra Memory

(XAF)

Addr

(0-7F)

RXAF

00

Note 1: P3.2 is pulled low during programming to indicate RDY/BUSY.

(P3.2 = 1 Ready; P3.2 = 0 Busy).

Note 2: In Page Load Mode the current byte is loaded on ALE rising edge.

Note 3: After a power up all external test mode to program or to erase the FLASH are locked to avoid any untimely programming or erasure.

After each programming or erasure test mode, it’s advised to lock this feature (test mode PELCK).

To validate the test mode mode PEULCK the following sequence has to be applied:

Test Mode PEULCK with ALE = 1.

Pulse on ALE (min width=25clk) with P0=55 (P0 latched on ALE rising edge)

Pulse on ALE (min width=25clk) with P0=AA (P0 latched on ALE rising edge)

Note 4: The highest security bit (bit 7) is used to secure the 7 lowest bit erasure. The only way to erase this bit is to erase the whole FLASH

memory.

Procedure to program security bits (After array programming):

- program bit7 to 0, program all other bits ( 1 = erased, 0 = programmed).

- test mode PGMS (din = HSB).

Procedure to erase security byte:

- test mode CERR: erase all array included HSB.

- program hardware security byte to FF: test mode PGMS (din = FF).

8.9.3. Definition of terms

Address Lines:P1.0-P1.7, P2.0-P2.5, P3.4-P3.5, respectively for A0-A15.

Data Lines:P0.0-P0.7 for D0-D7

Control Signals:RST, PSEN, P2.6, P2.7, P3.2, P3.3, P3.6, P3.7.

Program Signals: ALE/PROG, EA

Rev. F - 15 February, 2001

66

T89C51RD2

+5V

EA

V

CC

PROGRAM

SIGNALS*

ALE/PROG

P0.0-P0.7

P1.0-P1.7

D0-D7

A0-A7

RST

PSEN

P2.6

P2.7

P3.3

P3.6

P3.7

CONTROL

SIGNALS*

A8-A13

A14

P2.0-P2.5

P3.4

P3.5

A15

4 to 6 MHz

XTAL1

VSS

GND

Figure 22. Set-Up Modes Configuration

8.9.4. Programming Algorithm

To program the T89C51RD2 the following sequence must be exercised:

•

Check the signature bytes

Check the HSB (VSB mode)

If the security bits are activated, the following commands must be done before programming:

•

Unlock test modes (PEULCK mode, pulse 55h and AAh)

Chip erase (CERR mode)

Write FFh in the HSB (PGMS mode)

Write the signature bytes content in the XAF

As the boot loader and the XAF content is lost after a "chip erase", it must be reprogrammed if needed.

Disable programming access (PELCK mode)

To write a page in the FLASH memory, execute the following steps:

•

Step 0: Enable programming access (PEULCK mode)

Step 1: Activate the combination of control signals (PGML mode)

Step 2: Input the valid address on the address lines (High order bits of the address must be stable during the

complete ALE low time)

•

Step 3: Activate the combination of control signals (PGML mode)

Step 4: Input the appropriate data on the data lines.

Step 5: Pulse ALE/PROG once.

Repeat step 2 through 5 changing the address and data for end of a 128 bytes page

•

Step 6: Enable programming access (PEULCK mode)

Step 7: Activate the combination of control signals (PGMC mode)

67

Rev. F - 15 February, 2001

T89C51RD2

•

Step 8: Input the valid address on the address lines.

Step 9: Pulse ALE/PROG once until P3.2 is high or the specified write time is reached.

Repeat step 0 through 9 changing the address and data until the entire array or until the end of the object file is

reached (See Figure 23.)

•

Step 10: Disable programming access (PELCK mode)

8.9.5. Verify algorithm

Verify must be done after each byte or block of bytes is programmed. In either case, a complete verify of the

programmed array will ensure reliable programming of the T89C51RD2.

P 2.7 is used to enable data output.

To verify the T89C51RD2 code the following sequence must be exercised:

•

Step 1:Activate the combination of program and control signals (PGMV)

Step 2: Input the valid address on the address lines.

Step 3: Read data on the data lines.

Repeat step 2 through 3 changing the address for the entire array verification (See Figure 23.).

Programming Cycle

Read/Verify Cycle

A0-A15

D0-D7

Data In

Data Out

48 clk (load latch ) or 10 ms (write)

ALE/PROG

5V

0V

EA

Control signals

P2.7

Figure 23. Programming and Verification Signal’s Waveform

8.9.6. Extra memory mapping

The memory mapping the T89C51RD2 software registers in the Extra FLASH memory is described in the table below.

Table 34. Extra Row Memory Mapping (XAF)

Address

Default content

Copy of device ID #3

0061h

FFh

Rev. F - 15 February, 2001

68

T89C51RD2

Table 34. Extra Row Memory Mapping (XAF)

Copy of device ID #2

Copy of device ID #1

0060h

0031h

FCh

D7h

58h

Copy of Manufacturer Code: ATMEL

Boot reference

0030h

0006h

0005h

Software Security Byte (level 1 by default)

FFh

Copy of HSB (level 4 by default and BLJB

= 0)

0004h

18h or 1Bh

Software Boot Vector

Boot Status Byte

0001h

0000h

FCh

FFh

All other addresses are reserved

69

Rev. F - 15 February, 2001

T89C51RD2

9. Electrical Characteristics

(1)

9.1. Absolute Maximum Ratings

Ambiant Temperature Under Bias:

C = commercial 0°C to 70°C

I = industrial -40°C to 85°C

Storage Temperature -65°C to +150°C

Voltage on V

V -0.5 V to +6.5V

CC SS

Voltage on Any Pin V -0.5 V to V +0.5 V

SS

(2)

CC

Power Dissipation 1 W

NOTES

1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only

and functional operation of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not

implied. Exposure to absolute maximum rating conditions may affect device reliability.

2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.

Rev. F - 15 February, 2001

70

T89C51RD2

9.2. DC Parameters for Standard Voltage (1)

TA = 0°C to +70°C; V = 0 V; V = 5 V ± 10%; F = 0 to 40 MHz.

SS

CC

TA = -40°C to +85°C; V = 0 V; V = 5 V ± 10%; F = 0 to 40 MHz.

SS

CC

Typ ⁽⁵⁾

Symbol

Parameter

Min

Max

Unit

V

Test Conditions

V

Input Low Voltage

-0.5

0.2 V - 0.1

CC

IL

V

Input High Voltage except XTAL1, RST

Input High Voltage, XTAL1, RST

0.2 V + 0.9

V

+ 0.5

V

IH

CC

V

0.7 V

V

IH1

CC

(6)

(4)

V

0.3

V

OL

Output Low Voltage, ports 1, 2, 3, 4 and 5

I

= 100 µA

OL

0.45

1.0

(4)

= 1.6 mA

= 3.5 mA

(4)

(6)

(4)

V

0.3

0.45

1.0

V

OL1

Output Low Voltage, port 0, ALE, PSEN

I

= 200 µA

= 3.2 mA

= 7.0 mA

OL

V

Output High Voltage, ports 1, 2, 3, 4 and 5

V

- 0.3

- 0.7

- 1.5

V

I

= -10 µA

= -30 µA

= -60 µA

OH

CC

OH

V

= 5 V ± 10%

CC

V

R

Output High Voltage, port 0, ALE, PSEN

V

- 0.3

- 0.7

- 1.5

V

I

= -200 µA

= -3.2 mA

= -7.0 mA

= 5 V ± 10%

OH1

CC

OH

V

CC

RST Pulldown Resistor

50

90

200

-50

kΩ

µA

RST

I

Logical 0 Input Current ports 1, 2, 3, 4 and 5

Input Leakage Current

Vin = 0.45 V

0.45 V < Vin < V

Vin = 2.0 V

IL

I

±10

-650

LI

CC

I

Logical 1 to 0 Transition Current, ports 1, 2, 3,

4 and 5

TL

C

Capacitance of I/O Buffer

10

pF

Fc = 1 MHz

TA = 25°C

IO

(3)

I

Power Down Current

120

150

µA

PD

V

= 3 V to 5.5 V

CC

(1)

I

Power Supply Current onnormal mode

0.7 Freq

(MHz) + 3

mA

CCOP

= 5.5 V

(2)

I

Power Supply Current on idle mode

0.4 Freq

(MHz) + 2

mA

CCIDLE

V

= 5.5 V

CC

Table 35. DC Parameters in Standard Voltage (1)

71

Rev. F - 15 February, 2001

T89C51RD2

9.3. DC Parameters for Standard Voltage (2)

TA = 0°C to +70°C; V = 0 V; V = 3 V to 5.5 V; F = 0 to 33 MHz.

SS

CC

TA = -40°C to +85°C; V = 0 V; V = 3 V to 5.5 V; F = 0 to 33 MHz.

SS

CC

Typ⁽⁵⁾

Symbol

Parameter

Min

Max

Unit

V

Test Conditions

V

Input Low Voltage

-0.5

0.2 V - 0.1

CC

IL

V

Input High Voltage except XTAL1, RST

Input High Voltage, XTAL1, RST

0.2 V + 0.9

V

+ 0.5

V

IH

CC

V

0.7 V

V

IH1

CC

(6)

(4)

V

0.45

V

OL

Output Low Voltage, ports 1, 2, 3, 4 and 5

I

= 0.8 mA

OL

(6)

(4)

V

0.45

V

OL1

Output Low Voltage, port 0, ALE, PSEN

Output High Voltage, ports 1, 2, 3, 4 and 5

Output High Voltage, port 0, ALE, PSEN

I

= 1.6 mA

= -10 µA

= -40 µA

OL

OH

V

0.9 V

V

OH

CC

V

OH1

I

Logical 0 Input Current ports 1, 2, 3, 4 and 5

Input Leakage Current

-50

±10

-650

µA

Vin = 0.45 V

IL

LI

I

0.45 V < Vin < V

Vin = 2.0 V

CC

I

Logical 1 to 0 Transition Current, ports 1, 2, 3,

4 and 5

TL

R

RST Pulldown Resistor

50

90

200

10

kΩ

RST

CIO

Capacitance of I/O Buffer

pF

Fc = 1 MHz

TA = 25°C

(3)

I

Power Down Current

120

150

µA

PD

V

= 3 V to 5.5 V

CC

I

Power Supply Current on normal mode

0.7 Freq

CCOP

(MHz)+3mA

(1)

(2)

mA

V

= 5.5 V

CC

I

Power Supply Current on idle mode

0.5 Freq

(MHz)+2mA

CCIDLE

CC

Table 36. DC Parameters for Standard Voltage (2)

Rev. F - 15 February, 2001

72

T89C51RD2

9.4. DC Parameters for Low Voltage

TA = 0°C to +70°C; V = 0 V; V = 2.7 V to 3.6 V; F = 0 to 25 MHz.

SS

CC

TA = -40°C to +85°C; V = 0 V; V = 2.7 V to 3.6 V; F = 0 to 25 MHz.

SS

CC

Typ⁽⁵⁾

Symbol

Parameter

Min

Max

Unit

V

Test Conditions

V

Input Low Voltage

-0.5

0.2 V - 0.1

CC

IL

V

Input High Voltage except XTAL1, RST

Input High Voltage, XTAL1, RST

0.2 V + 0.9

V

+ 0.5

V

IH

CC

V

0.7 V

V

IH1

CC

(6)

(4)

V

0.45

V

OL

Output Low Voltage, ports 1, 2, 3, 4 and 5

I

= 0.8 mA

OL

(6)

(4)

V

0.45

V

OL1

Output Low Voltage, port 0, ALE, PSEN

Output High Voltage, ports 1, 2, 3, 4 and 5

Output High Voltage, port 0, ALE, PSEN

I

= 1.6 mA

= -10 µA

= -40 µA

OL

OH

V

0.9 V

V

OH

CC

V

OH1

I

Logical 0 Input Current ports 1, 2, 3, 4 and 5

Input Leakage Current

-50

±10

-650

µA

Vin = 0.45 V

IL

I

0.45 V < Vin < V

Vin = 2.0 V

LI

CC

I

Logical 1 to 0 Transition Current, ports 1, 2, 3,

4 and 5

TL

R

RST Pulldown Resistor

50

90

1

200

10

kΩ

RST

CIO

Capacitance of I/O Buffer

pF

Fc = 1 MHz

TA = 25°C

(3)

I

Power Down Current

50

µA

PD

V

= 2.7 V to 3.6 V

CC

I

Power Supply Current on normal mode

0.6 Freq

CCOP

(MHz)+3mA

(1)

(2)

mA

V

= 3.6 V

CC

I

Power Supply Current on idle mode

0.3 Freq

(MHz)+2mA

CCIDLE

Table 37. DC Parameters for Low Voltage

NOTES

1. Operating I is measured with all output pins disconnected; XTAL1 driven with T

, T

= 5 ns (see Figure 27.), V = V + 0.5 V,

IL SS

CC

CLCH CHCL

V

= V - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V . I would be slightly higher if a crystal oscillator used (see Figure 24.).

CC CC CC

IH

2. Idle I is measured with all output pins disconnected; XTAL1 driven with T

, T

= 5 ns, V = V + 0.5 V, V = V - 0.5 V; XTAL2

CC

CLCH CHCL IL SS IH CC

N.C; Port 0 = V ; EA = RST = V (see Figure 25.).

CC

SS

3. Power Down I is measured with all output pins disconnected; EA = V , PORT 0 = V ; XTAL2 NC.; RST = V (see Figure 26.). In addition,

CC

SS

CC

SS

the WDT must be inactive and the POF ﬂag must be set.

4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V s of ALE and Ports 1 and 3. The noise is

OL

due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst

cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi V peak 0.6V. A Schmitt Trigger use is not necessary.

OL

5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature..

6. Under steady state (non-transient) conditions, I must be externally limited as follows:

OL

Maximum I per port pin: 10 mA

OL

Maximum I per 8-bit port:

OL

Port 0: 26 mA

Ports 1, 2 and 3: 15 mA

Maximum total I for all output pins: 71 mA

OL

If I exceeds the test condition, V may exceed the related speciﬁcation. Pins are not guaranteed to sink current greater than the listed test conditions.

OL

73

Rev. F - 15 February, 2001

T89C51RD2

V

CC

I

CC

V

CC

V

CC

P0

EA

V

CC

RST

XTAL2

XTAL1

(NC)

CLOCK

SIGNAL

V

SS

All other pins are disconnected.

Figure 24. I

Test Condition, Active Mode

CC

V

CC

I

CC

V

CC

V

CC

P0

RST

EA

(NC)

CLOCK

SIGNAL

XTAL2

XTAL1

V

SS

Figure 25. I

Test Condition, Idle Mode

CC

V

CC

I

CC

V

CC

V

CC

P0

EA

RST

(NC)

XTAL2

XTAL1

V

SS

Figure 26. I

Test Condition, Power-Down Mode

CC

Rev. F - 15 February, 2001

74

T89C51RD2

V

-0.5V

0.45V

CC

0.7V

0.2V -0.1

CC

T

CLCH

CHCL

T

= T

= 5ns.

CHCL

CLCH

Figure 27. Clock Signal Waveform for I

Tests in Active and Idle Modes

CC

9.5. AC Parameters

9.5.1. Explanation of the AC Symbols

Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters,

depending on their positions, stand for the name of a signal or the logical status of that signal. The following is

a list of all the characters and what they stand for.

Example:T

= Time for Address Valid to ALE Low.

AVLL

T

= Time for ALE Low to PSEN Low.

LLPL

TA = 0 to +70°C; V = 0 V; V = 5 V ± 10%; M range.

SS

CC

TA = -40°C to +85°C; V = 0 V; V = 5 V ± 10%; M range.

SS

CC

TA = 0 to +70°C; V = 0 V; 2.7 V < V < 3.3 V; L range.

SS

CC

TA = -40°C to +85°C; V = 0 V; 2.7 V < V < 3.3 V; L range.

SS

CC

AC characteristics of -M parts at 3 volts are similar to -L parts

(Load Capacitance for port 0, ALE and PSEN = 100 pF; Load Capacitance for all other outputs = 80 pF.)

Table 38, Table 41 and Table 44 give the description of each AC symbols.

Table 39, Table 42 and Table 45 give for each range the AC parameter.

Table 40, Table 43 and Table 46 give the frequency derating formula of the AC parameter for each speed range

description. To calculate each AC symbols. take the x value in the correponding column (-M or -L) and use this

value in the formula.

Example: T

x = 35 ns

T = 50 ns

for -M and 20 MHz, Standard clock.

LLIU

T

= 4T - x = 165 ns

CCIV

75

Rev. F - 15 February, 2001

T89C51RD2

9.5.2. External Program Memory Characteristics

Table 38. Symbol Description

Symbol

Parameter

T

Oscillator clock period

ALE pulse width

T

LHLL

T

Address Valid to ALE

AVLL

T

Address Hold After ALE

ALE to Valid Instruction In

ALE to PSEN

LLAX

T

LLIV

LLPL

PLPH

T

PSEN Pulse Width

T

PSEN to Valid Instruction In

Input Instruction Hold After PSEN

Input Instruction FloatAfter PSEN

Address to Valid Instruction In

PSEN Low to Address Float

PLIV

T

PXIX

T

PXIZ

T

AVIV

PLAZ

T

Table 39. AC Parameters for a Fix Clock

Symbol

-M

-L

Units

Min

25

Max

Min

25

Max

T

ns

T

40

LHLL

T

10

ns

AVLL

T

LLAX

T

70

35

70

35

LLIV

LLPL

PLPH

T

15

55

15

55

T

PLIV

PXIX

T

0

T

18

85

10

18

85

10

PXIZ

T

AVIV

PLAZ

T

Rev. F - 15 February, 2001

76

T89C51RD2

Table 40. AC Parameters for a Variable Clock

Symbol

Type

Standard

Clock

X2 Clock

X parameter X parameter

for -M range for -L range

Units

T

Min

Max

Min

Max

Min

Max

2 T - x

T - x

4 T - x

T - x

3 T - x

x

T - x

0.5 T - x

2 T - x

0.5 T - x

1.5 T - x

x

10

15

30

10

20

40

0

10

15

30

10

20

40

0

ns

LHLL

T

AVLL

T

LLAX

T

LLIV

LLPL

PLPH

T

PLIV

PXIX

T

T - x

5 T - x

x

0.5 T - x

2.5 T - x

x

7

PXIZ

T

40

10

40

10

AVIV

PLAZ

T

9.5.3. External Program Memory Read Cycle

12 T

CLCL

T

LLIV

LHLL

ALE

PSEN

T

LLPL

T

PLPH

T

PXAV

T

LLAX

T

PXIZ

PLIV

AVLL

T

TPLAZ

PXIX

PORT 0

PORT 2

INSTR IN

A0-A7

INSTR IN

A0-A7

INSTR IN

T

AVIV

ADDRESS

OR SFR-P2

ADDRESS A8-A15

77

Rev. F - 15 February, 2001

T89C51RD2

9.5.4. External Data Memory Characteristics

Table 41. Symbol Description

Symbol

Parameter

T

RD Pulse Width

RLRH

T

WR Pulse Width

WLWH

T

RD to Valid Data In

RLDV

RHDX

T

Data Hold After RD

Data Float After RD

ALE to Valid Data In

Address to Valid Data In

ALE to WR or RD

T

RHDZ

T

LLDV

T

AVDV

T

LLWL

T

Address to WR or RD

Data Valid to WR Transition

Data set-up to WR High

Data Hold After WR

RD Low to Address Float

RD or WR High to ALE high

AVWL

QVWX

QVWH

WHQX

T

RLAZ

T

WHLH

Rev. F - 15 February, 2001

78

T89C51RD2

Table 42. AC Parameters for a Fix Clock

Symbol

-M

-L

Units

Min

130

Max

Min

130

Max

T

ns

RLRH

T

130

WLWH

T

100

RLDV

RHDX

T

0

T

30

RHDZ

T

160

165

100

160

165

100

LLDV

T

AVDV

T

50

75

50

75

LLWL

T

AVWL

QVWX

QVWH

WHQX

T

10

160

15

160

15

T

0

RLAZ

T

10

40

10

40

WHLH

79

Rev. F - 15 February, 2001

T89C51RD2

Table 43. AC Parameters for a Variable Clock

Symbol

Type

Standard

Clock

X2 Clock

X parameter X parameter

for -M range for -L range

Units

T

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

6 T - x

5 T - x

x

3 T - x

2.5 T - x

x

20

25

0

20

25

0

ns

RLRH

T

WLWH

T

RLDV

RHDX

T

2 T - x

8 T - x

9 T - x

3 T - x

3 T + x

4 T - x

T - x

20

40

60

25

15

10

0

20

40

60

25

15

10

0

RHDZ

T

4T -x

LLDV

T

4.5 T - x

1.5 T - x

1.5 T + x

2 T - x

0.5 T - x

3.5 T - x

0.5 T - x

x

AVDV

T

LLWL

T

AVWL

QVWX

QVWH

WHQX

T

7 T - x

T - x

T

x

RLAZ

WHLH

T

T - x

0.5 T - x

0.5 T + x

15

T + x

9.5.5. External Data Memory Write Cycle

T

WHLH

ALE

PSEN

WR

T

LLWL

WLWH

T

QVWX

T

QVWH

WHQX

LLAX

PORT 0

PORT 2

A0-A7

DATA OUT

T

AVWL

ADDRESS

OR SFR-P2

ADDRESS A8-A15 OR SFR P2

Rev. F - 15 February, 2001

80

T89C51RD2

9.5.6. External Data Memory Read Cycle

T

WHLH

T

ALE

PSEN

RD

LLDV

T

RLRH

LLWL

T

RHDZ

T

AVDV

T

LLAX

RHDX

PORT 0

PORT 2

A0-A7

DATA IN

T

RLAZ

T

AVWL

ADDRESS

OR SFR-P2

ADDRESS A8-A15 OR SFR P2

9.5.7. Serial Port Timing - Shift Register Mode

Table 44. Symbol Description

Symbol

Parameter

T

Serial port clock cycle time

XLXL

QVHX

XHQX

Output data set-up to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

T_XHDX

T

Clock rising edge to input data valid

XHDV

Table 45. AC Parameters for a Fix Clock

Symbol

-M

-L

Units

Min

300

200

30

Max

Min

300

200

30

Max

T

ns

XLXL

QVHX

XHQX

XHDX

XHDV

T

0

117

81

Rev. F - 15 February, 2001

T89C51RD2

Table 46. AC Parameters for a Variable Clock

Symbol

Type

Standard

Clock

X2 Clock

X parameter X parameter

for -M range for -L range

Units

T

Min

Max

12 T

10 T - x

2 T - x

x

6 T

5 T - x

T - x

x

ns

XLXL

QVHX

XHQX

XHDX

XHDV

T

50

20

0

50

20

0

10 T - x

5 T- x

133

9.5.8. Shift Register Timing Waveforms

0

1

2

3

4

5

6

7

8

INSTRUCTION

ALE

T

XLXL

CLOCK

T

XHQX

T

QVXH

0

1

2

3

4

5

6

7

OUTPUT DATA

T

SET TI

XHDX

T

XHDV

WRITE to SBUF

INPUT DATA

VALID

SET RI

CLEAR RI

Rev. F - 15 February, 2001

82

T89C51RD2

9.5.9. FLASH EEPROM Programming and Verification Characteristics

TA = 21°C to 27°C; V = 0V; V = 5V ± 10%.

SS

CC

Table 47. Flash Programming Parameters

Symbol

Parameter

Min

Max

Units

1/T

Oscillator Frquency

4

6

MHz

CLCL

T

Control to address ﬂoat

48 T

CLCL

EHAZ

T

Address Setup to PROG Low

Adress Hold after PROG

Data Setup to PROG Low

Data Hold after PROG

48 T

CLCL

AVGL

T

48 T_CLCL

10

GHAX

T

DVGL

GHDX

T

PROG Width for PGMC and PGXC*

PROG Width for PGML

Address to Valid Data

20

ms

GLGH

T

48 T_CLCL

T

48 T_CLCL

AVQV

T

ENABLE Low to Data Valid

Data Float after ENABLE

ELQV

EHQZ

0

9.5.10. FLASH EEPROM Programming and Verification Waveforms

PROGRAMMING

ADDRESS

VERIFICATION

ADDRESS

P1.0-P1.7

P2.0-P2.4

P3.4-P3.5

T

AVQV

DATA OUT

P0

DATA IN

T

GHDX

DVGL

AVGL

T

GHAX

ALE/PROG

T

GLGH

T

EHAZ

EHQZ

ELQV

CONTROL

SIGNALS

(ENABLE)

83

Rev. F - 15 February, 2001

T89C51RD2

9.5.11. External Clock Drive Characteristics (XTAL1)

Symbol

Parameter

Min

25

5

Max

Units

ns

T

Oscillator Period

High Time

Low Time

CLCL

T

ns

CHCX

T

5

ns

CLCX

CLCH

CHCL

Rise Time

5

ns

Fall Time

ns

T

/T

Cyclic ratio in X2 mode

40

60

%

CHCX CLCX

Table 48. AC Parameters

9.5.12. External Clock Drive Waveforms

V

-0.5V

CC

0.7V

CC

0.2V -0.1

CC

0.45V

T

CHCX

T

CLCH

T

CLCX

CHCL

T

CLCL

9.5.13. AC Testing Input/Output Waveforms

V

-0.5 V

0.45 V

CC

0.2 V + 0.9

CC

INPUT/OUTPUT

0.2 V - 0.1

CC

AC inputs during testing are driven at V - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement

CC

are made at V min for a logic “1” and V max for a logic “0”.

IH

IL

9.5.14. Float Waveforms

FLOAT

V

- 0.1 V

+ 0.1 V

V

+ 0.1 V

- 0.1 V

OH

LOAD

V

LOAD

OL

For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins

to float when a 100 mV change from the loaded V /V level occurs. I /I ≥ ± 20mA.

OH OL

OL OH

Rev. F - 15 February, 2001

84

T89C51RD2

9.5.15. Clock Waveforms

Valid in normal clock mode. In X2 mode XTAL2 must be changed to XTAL2/2.

STATE4

P1 P2

STATE5

P1 P2

STATE6

P1 P2

STATE1

STATE2

P1 P2

STATE3

P1 P2

STATE4

P1 P2

STATE5

P1 P2

INTERNAL

CLOCK

P1

P2

XTAL2

ALE

THESE SIGNALS ARE NOT ACTIVATED DURING THE

EXECUTION OF A MOVX INSTRUCTION

EXTERNAL PROGRAM MEMORY FETCH

PSEN

P0

DATA

PCL OUT

DATA

PCL OUT

DATA

PCL OUT

SAMPLED

FLOAT

P2 (EXT)

INDICATES ADDRESS TRANSITIONS

READ CYCLE

RD

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

DPL OR Rt OUT

DATA

SAMPLED

P0

FLOAT

P2

INDICATES DPH OR P2 SFR TO PCH TRANSITION

WRITE CYCLE

WR

PCL OUT (EVEN IF PROGRAM

MEMORY IS INTERNAL)

DPL OR Rt OUT

P0

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

DATA OUT

P2

INDICATES DPH OR P2 SFR TO PCH TRANSITION

PORT OPERATION

MOV PORT SRC

OLD DATA

NEW DATA

P0 PINS SAMPLED

MOV DEST P0

MOV DEST PORT (P1. P2. P3)

(INCLUDES INTO. INT1. TO T1)

P1, P2, P3 PINS SAMPLED

SERIAL PORT SHIFT CLOCK

RXD SAMPLED

TXD (MODE 0)

This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,

however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin

loading. Propagation also varies from output to output and component. Typically though (T =25°C fully loaded)

A

RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays

are incorporated in the AC specifications.

85

Rev. F - 15 February, 2001

T89C51RD2

10. Ordering Information

T

M

-3C

89C51RD2

C

S

Packages:

Temperature Range

C: Commercial 0 to 70^oC

I: Industrial -40 to 85^oC

3C: PDIL40

SL: PLCC44

RL: VQFP44 (1.4mm)

SM: PLCC68

RD: VQFP64, square-

package (1.4mm)

DD: Dice in ship tray

89C51RD2 (64k Flash)

-M:

VCC: 4.5 to 5.5V

40MHz, X1 Mode

20MHz, X2 Mode

VCC: 3 to 5.5V

Conditioning

S: Stick

T: Tray

33 MHz, X1 mode

16 MHz, X2 mode

-L :

VCC: 2.7 to 3.6 V

25 MHz, X1 mode

12 MHz, X2 mode

R: Tape & Reel

U: Stick + Dry Pack

V: Tray + Dry Pack

F: Tape & Reel + Dry Pack

B: Blue Tape

W: Wafer

Rev. F - 15 February, 2001

86


型号：	T89C51RD2-RDVC-M
厂家：	ATMEL
描述：	0 to 40MHz Flash Programmable 8-bit Microcontroller 0〜 40MHz的闪存，可编程的8位微控制器闪存微控制器
文件：	总86页 (文件大小：935K)
中文：	中文翻译
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