TH7426AVWJNGB/T [ATMEL]

CCD Sensor, 2.50V, Square, Surface Mount, CERAMIC, J LEAD PACKAGE-84;


型号：	TH7426AVWJNGB/T
厂家：	ATMEL
描述：	CCD Sensor, 2.50V, Square, Surface Mount, CERAMIC, J LEAD PACKAGE-84 ATM 异步传输模式 CD 传感器换能器
文件：	总20页 (文件大小：1122K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TH7426A/27A

NEAR INFRARED InGaAs LINEAR IMAGE SENSOR

300 PIXELS

DESCRIPTION

These devices are based on a 300 InGaAs photodiode li-

near array, with a 26µm pitch, using an in line pixel layout or

a staggered pixel layout.

Two 150:1 CCD multiplexor chips, offering memory and de-

layed readout capability, are hybridized on both sides of the

photodiode array so as to build a complete module.

Specially designed to allow an accurate butting, those mo-

dules could be tied together on request so as to provide an

array extension with only one dead pixel at the splice.

These devices are also available in a full CMOS interface

version :

TH74KA26A/TH74KA27A or TH74KB26A/TH74KB27A.

MAIN FEATURES

APPLICATIONS

n Near infrared spectral response: 0.8µm to 1.7µm

n Room temperature operation

n Suited for Near Infrared imaging

n Thermal imaging in the 200°C to 800°C range

ⁿHigh resolution multichannel spectrometry

n Fluorescence free Raman spectrophotometry

ⁿOn-line inspection and monitoring

ⁿLow noise

n High detectivity, wide dynamic range (>10 000)

ⁿHigh linearity, high Modulation Transfer Function (MTF)

ⁿHigh output data rate : up to 6 MHz

ⁿIntrinsic antiblooming

ⁿBuilt in thermoelectric cooler and temperature sensor

available

ⁿAccurate mechanical indexes (ready to mount)

SELECTION GUIDE

NUMBER OF

VIDEO OUTPUTS

REFERENCE

PIXEL COUNT

LAYOUT

PIXEL AREA

PITCH

TH7426A

TH7427A

TH7428A

TH7429A

299

599

In line

Staggered

In line

20x30µm²

30x30µm²

20x30µm²

30x30µm²

26µm

Staggered

March 1998

1/20

TH7426A/27A

GEOMETRICAL CHARACTERISTICS

ELEMENT BLOCK DIAGRAM

2/20

TH7426A/27A

ABSOLUTE MAXIMUM RATINGS

Supply voltages (compare to Vss, at any pin)

Transient voltages (compare to Vss, at any pin)

DC current (at any pin),

0 to +20V

0 to +25V

10mA

Except

except

- thermoelectric cooler pins

- temperature sensor

+/-3mA

Operating temperature (temperature variation limited to 6°C/min)

Storage temperature (temperature variation limited to 6°C/min)

Electrostatic discharge sensitivity, MIL-STD-883 method 3015

-40 to +85°C

device Class 1

Stresses above those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent devices failure. Functionality at

or above these limits is not implied. Exposure to maximum ratings for extended periods may affect device reliability.

To avoid any performance degradation,the device must be handled with grounded bracelet and stored in the conductive

packing used for shipment.

TABLE 1 - ELECTRO-OPTICAL CHARACTERISTICS

15°C internal operating temperature, 3ms integration time, typical voltage input (otherwise specified).

Parameter

Symbol

TH 7426

Typ.

TH 7427

Typ.

Unit

Remarks

Min.

Max.

Min

Max.

Dark voltage signal

mean

V_D

See Fig. 6

isolated pixels

(photodiode dark current)

100

120

( I_D)

0.6

0.8

See note (1)

Noise in darkness

mean

(rms)

200

µV

σV_D

isolated pixels

1.2

Absolute photo response

mean

Vcm²/µJ See Fig. 3-4-5

non uniformity

PRNU

+/-10

1.73

+/-10

173

non linearity over 1.5V range

Spectral response

Cut-off wavelength

Temperature shift

1.66

1.68

1.1

1.66

1.68

1.1

µm

λc

dλc/dT

At 50% R(λ)

max

nm/°C

Modulation transfer function

across array

MTF

Vsat

NEP

At 19.2 lp/mm

See note (2)

0.35

0.55

0.50

0.68

0.54

0.73

0.35

0.50

0.54

along array

Output saturation voltage

2.5

Depends on

preload level.

See Fig. 7

Noise equivalent power at

λ=1.65µm

0.35

6.7

0.35

4.4

BW=1Hz

BW=167Hz

nWcm^-2BW=167Hz

5.10¹²

8.10¹¹

6.10¹²

1.10¹²

cmHz^1/2W^-1BW=1Hz

Specific detectivity at λ=1.65µm

cmHz^1/2W^-1BW=167Hz

Electron to voltage conversion factor

Quantum efficiency

0.26

0.8

0.26

0.8

µV/e

e/ph

See Fig. 5

Image grade

(number of blemishes)

See note (3)

Electrical sample

Note : 1 Already taken into account in mean V_D(V_D= Id TI Fc ; TI=Integration time ; q = 1.6 10^-19C)

Note : 2 “Maximum value” is the theoretical value computed using the corresponding diode size

Note : 3 a pixel is considered as a blemish if :

- its dark voltage is higher than isolated pixel max value

- its noise is higher than isolated pixel noise max value

- its PRNU is higher than +/- 10 %

3/20

TH7426A/27A

TABLE 2 - CONNECTION DIAGRAMS

Pin n° EVEN Sym-

Designation

Pin n° ODD Sym-

Mo- bol

Designation

Mo-

bol

dule #

1...2

Not connected

44...51

TC+ Thermoelectric cooler (positive node)

see notes (2) (3)

3...6

7...9

Temperature sensor see note (3)

Not connected

52...55

Not connected

VG1 Lateral skimming gate bias

DNC Do not connect see note (4)

NC Not connected

Photodiode lateral transfer clock

Electrical injection clock

φX

11...14

φPL

VDD Output amplifier drain & RE supplies

VOS Video output signal (pixels 0-298)

GND Video ground

VGL1 Preload skimming gate bias

VGL2 Preload storage gate bias

Shift register clock 2 (gated by RE)

φL2

VSS CCD substrate bias (phases return)

Read enable control signal

(pixels 1-299)

CCD reset clock

Shift register clock 1

φR

φL1

VDR Reset bias

Photodiode substrate bias see note (1)

VGS Output gate bias

VDR Reset bias

φL1

Photodiode substrate bias see note (1) 66

Shift register clock 1

CCD reset clock

φR

Read enable control signal

(pixels 0-298)

VSS CCD substrate bias (phases return)

Shift register clock 2 (gated by RE)

GND Video ground

φL2

VGL2 Preload storage gate bias

VGL1 Preload skimming gate bias

VOS Video output signal (pixels 1-299)

VDD Output amplifier drain & RE supplies

Electrical injection clock

72...75

Not connected

φPL

φX

Photodiode lateral transfer clock

DNC Do not connect see note (4)

VG1 Lateral skimming gate bias

NC Not connected

77...79

80...83

Not connected

31...34

35...42

Temperature sensor see note (3)

Not connected

TC- Thermoelectric cooler (negative

node) see notes (2) (3)

Not connected

Notes : 1 Pin 22 and 64 are internally connected together

Notes : 2 In each group every pins must be connected and tied together in order to lower pin current density

Notes : 3 Not connected on non cooled package

Notes : 4 DNC (Do Not Connect). Pins which are internally connected and must not be used.

4/20

TH7426A/27A

PIN DESCRIPTION

Odd and Even channels are fully independent, therefore same pin function will be found on odd and even sides.

This is the preload injection stage electrical input. Each Φ

pulse down overfills preload storage capacitance with

electrons. Φ

is connected to a diode cathode which anode is internally tied to Vss.

This is the preload stage skimming gate. Its bias determines the voltage up to which preload storage capacitance

will be biased. Thus it drives preload level.

GL1

GL2

This is the storage capacitance grid bias. It determines the bottom voltage of preload storing well, while V

deter-

GL1

mines its top level. Preload capacitance thus is charged up proportionately to (V

- V

) bias difference.

GL2

GL1

This is the main register storage grid clock. Charges are stored under Φ

when transfer is disabled (RE at low le-

vel).

is also used for lateral transfers to input nodes.

This is the main register transfer grid clock. Φ is used to isolate

content during lateral transfers. The main re-

gister is beginning and ending with

RE input, it is internally pulled down when RE is low, preventing transfers, preload injection, read out and isolating

each well.

which therefore controls main register access and outputs.

is gated by

This is the “Read Enable” input. When high, it allows Φ

input connection to main register, when low, main register

corresponding grids are pulled down whatever

input level is.

This input helps to serially read out two or more multiplexors with one single

the main register as long as RE is low, thus read out can occur later on.

signal for all. Data are stored into

This is the lateral transfer grid command. Lateral transfer is allowed when

input nodes, all photodiode information is collected at the same time.

is at high level.

is common to all

This is the lateral input stage skimming grid bias. This grid determines photodiodes reset bias, always the same

from integration time to integration time. After photodiode reset (input node capacitance reset) extra charges leading

to overcrossing V

level are skimmed back into Φ main register wells.

This is the InGaAs photodiode common cathode bias. V is available on odd and ev en side, however, both pins are

connected together, to photodiode substrate.

This is main register output grid bias. It is used to isolate read out capacitance from main register. It allows charges

to be read out when Φ is at low level.

This is the read out capacitance reset bias. After each single read out, read out capacitance is cleared off (reset) to

level, during

clock high state.

5/20

TH7426A/27A

This is the output amplifier power supply (high side). It also supplies the “Read Enable” switching device which ex-

plains that I is different whether RE is at high or low level.

This is the output amplifier low side power supply. G

is linked to V

through a diode, G

being the cathode

node. Thus G

must always be more positive than or equal to Vss.

It must be noticed that “RE” switching device is powered from V

to V . G

is specific to output amplifier.

This is the amplifier output.

This is the CCD multiplexor substrate bias. All applied biases and clock levels must be more positive or equal to V

These are the internal temperature sensor connections. Temperature sensor is floating with respect to all other pin

connections. Pins 3 to 6 are internally connected together as well as pin 80 to 83.

TC+ This is the internal thermoelectric cooler positive input (current enters) (all pins must be externally connected in or-

der to lower current density into each pin).

TC-

This is the internal thermoelectric cooler negative input (current goes out). Thermoelectric cooler connections are

floating, with respect to all other pins. All pins must be externally connected in order to lower individual pin current

density. It is advised to avoid pulsed current regulations to drive TE cooler, since it may result in EMC troubleshoo-

ting inside component cavity.

FUNCTIONAL DESCRIPTION

Individual InGaAs diodes are reversed bias. The cathode node is common to all diodes and connected to a fixed potential

Vn. The anode of each diode is wire bonded to a lateral entrance of the readout CCD stage.

These diodes behave as capacitors whose leakage current depends on dark current and illumination. This current tends to

decrease the voltage across the capacitor. Each diode capacity is first preloaded with a calibrated amount of negative char-

ges (Qb). After an integration time (TI), the amount of removed charges (QI) figures out the cumulated light absorption. So

the measurement of the remaining charge amount (Qs) in the diode capacitor gives access to QI (QI = Qb - Qs). This is

called “Vidicon” readout mode.

CCD multiplexors fulfill all those operations. They provide preloading and readout functions for the separate odd and even

pixel groups. The main CCD features consist in a two phase register (φ and φ ) with longitudinal and lateral transfer ca-

pability. Following is a description of how those devices keep photodiodes under control and capture pixel signals.

Four main functions can be considered :

- Preload

The potential gap between the two gates [V

and spilling occurs using an injection diode φ

-V

] defines a potential well for preload calibration (Qb), its filling

GL1 GL2

- Main register charge handling

At each individual transfer step, Qs moves out of the 150th stage, while Qb moves in the first stage. The longitudinal

register stage requires a series of at least 150 steps to complete the preloading cycle. This transfer operation is inhi-

bited if RE (read enable) input is maintained at a low level.

- Photodiode information collection (and reset)

The lateral input stage consists in 150 input diodes, each of them directly wire bonded to one photodiode, and con-

trolled under a single common biasing gate V

and a lateral transfer gate φ .

At the end of integration time (see timing diagram Figure 1) :

- the preload charges Qb, stored in the register, are transferred simultaneously to the 150 photodiodes when φ is at

high level and φ at low level, allowing the photodiode reset.

- charges in excess (identified as Qs) are collected back to the register by forcing φ at high level. At this step the

new TI starts.

To isolate each stage from the other one, φ must be at low level during all lateral transfer operations.

- Data read-out

At the end of the photodiode reset operation :

- if RE is forced to low level (Timing Diagram - Figure 1), all Qs information remain stored in the register and so, rea-

dout is delayed .According to this situation a next photodiode reset procedure can’t be operated until the full longitu-

dinal transfer takes place (150 steps minimum).

6/20

TH7426A/27A

- if RE is activated or always at high level (Timing Diagram - Figure 2), each stored charge is transferred to the rea-

dout capacitance; this continuous readout mode is recommended for long integration time.

Qs conversion into voltage is supported by the readout stage capacitance, linked to a low output impedance ampli-

fier. This capacitance is reset at V

bias, before each pixel readout operation (high level φ ).

Due to the “Vidicon” read out mode, Qb level needs adjustment so as to provide enough carriers to sustain photocurrent

and dark current during the integration time. Pixel antiblooming is also resulting from “Vidicon mode” since photodiodes

cannot consume more electrons than Qb.

Antismearing (frame to frame antiblooming) efficiency depends on the photodiode reset conditions, reverse bias recovering

need a minimum Qb condition such as :

Qb>Clat .V

where : - Clat is the individual lateral input node capacitance, Clat ~1.5 pF (including photodiode, bonding pads...)

where : - V is the photodiode bias : V = V - 0.78V - 8.7

G 1

7/20

TH7426A/27A

MULTIPLEXOR TIMING DIAGRAM

* First Even output data is always at preload level (multiplexor corresponding input is not connected — See “Element Block Diagram”)

8/20

TH7426A/27A

TABLE 3 - STATIC CHARACTERISTICS

Pin n°

Symbol

Function

Value

Unit

Note

EVEN/ODD

Min

Typ

Max

V_DD

I_DD

15/71

20/66

Output amplifier

17.5

18.5

(1)

(2)

with Read Enable disabled

with Read Enable activated

0.7

1.1

V_DR

V_N

Reset bias

15.3

15.5

11.3

16.5

11.5

(1)

22/64 internally

connected

Photodiode substrate bias

G_ND

V_SS

17/69

18/68

30/56

27/59

26/60

21/65

Video ground

(3)

Lateral skimming gate

Preload skimming gate

Preload storage gate

V_G1

1.9

2.8

2.1

V_GL1

(4)

V_GL2

V_GS

6.2

6.5

Note : 1 V

-V

DD DR

>1.8V

Note : 2 For each V

Note : 3 Recommendation: tied to V

Note : 4 V

GL1

Notes : to get V

or, for best operation, hold at +0.5V above V

and V

GL1

are used to calibrate preloading level see Fig. 7; to minimise noise effect, it is recommended

GL2

and V

from the same low noise supply.

GL2

TABLE 4 - DYNAMIC CHARACTERISTICS

Pin n°

Symbol

Function

Value

Typ

Unit

Note

EVEN/ODD

Min

Max

23/63

25/61

28/58

19/67

29/57

24/62

Longitudinal transfer stage

(120 pF typical)

0.1

0.3

9.5

0.7

Φ_L1low

10.5

high

0.1

0.3

9.5

0.7

10.5

Φ_L2low

(120 pF typical if all RE enabled)

high

Preload injection diode

(10 pF typ.)

5.8

9.5

6.7

12.5

Φ_PLlow

high

Read out reset gate

(10 pF typ.)

0.1

11.5

0.3

0.7

12.5

Φ_R

Φ_X

low

high

Lateral transfer stage

(10 pF typ.)

0.1

7.8

0.3

0.7

8.2

low

high

low

high

Read enable

(15 pF typ.)

0.1

(Φ_L2high

+2,5V)

0.2

0.4

TABLE 5 - MISCELLANEOUS DATA

Symbol

Pin n°

Function

Value

Typ

Unit

Note

Min

Max

I_TH

35 to 42

44 to 51

16,7

Thermo cooler

(5)

V_OS(DC)

Z_O

Video signal DC level (wrt Vss)

Output impedance

1.2

100

KΩ

Ω

(7)

(6)

Rpt

(at 0°C)

3 to 6

80 to 83

Temperature sensor resistance

(recommended max. current 1 mA)

F_P

Transfer frequency

0.5

MHz

Note : 5 See Fig. 8a, 8b, 8c, 8d.

Note : 6 See Fig. 9.

Note : 7 Short circuit to Gnd or Vss exceeding 1 min duration may permanently damage the device

9/20

TH7426A/27A

TABLE 6 - TIMING AND SWITCHING CHARACTERISTICS

Parameter

Symbol

Value

Typ.

Unit

Note

Min.

0.05

0.33

Max.

INTEGRATION TIME

CLOCK PERIOD

µs

Tck

(3)

(4)

READ ENABLE

Duration

TRE

tr/tf

149.5Tck+t1_RE+t2_RE

µs

Rise time or fall time

Delay

250

t1RE

150

120

Set-up RE

t2RE

850

LATERAL TRANSFER

Duration

µs

TΦx

tr/tf

150

(4)

Φx rise time or fall time

Φ1 low level hold time

Φ2 low level hold time

Delay

Tx1

Tx2

1.7

100

980

tΦx

Readout delay

100

200

tΦ1

LONGITUDINAL TRANSFER

ΦL1 rise time or fall time

tr/tf

150

(4)

ΦL2 rise time or fall time

Preload duration

240

TΦPL

tr/tf

Preload rise time or fall time

Preload delay

(4)

(1)

tPL

Skimming time

tsk

500

READOUT DIODE RESET

Duration

240

(2)

(4)

(2)

TΦR

tr/tf

Rise time or fall time

Delay

120

VIDEO SIGNAL SET-UP TIME

t_video

100

Note : 1 Better if no clock transition occurs during “tsk” time.

Note : 2 tR + TΦR < ΦL2 high level duration.

Note : 3 Duty cycle: 50%

Note : 4 Rise time (tr) and fall time (tf) specified between 10% and 90%

10/20

TH7426A/27A

ELECTRO-OPTICAL TYPICAL CHARACTERISTICS

Figure 4 : Clear window typical spectral response

Figure 3 : Silicon Window typical spectral response

Figure 5 : Clear window & Silicon window quantum efficiency

Figure 6 : Dark voltage per 1ms integration time

Figure 6 : vs internal operating temperature

Figure 7 : Typical preload voltage vs V

and V

gate voltages

GL2

GL1

11/20

TH7426A/27A

THERMAL CHARACTERISTICS (single stage TE cooled package -subvariant N- only)

Figure 8b : Internal to rear face temperature gap vs

Figure 8a : Internal temperature vs

Figure 8b : Thermo-electric cooler current

Figure 8a : Thermo-electric cooler current

Figure 8c : Thermo-electric cooler voltage vs.

Figure 8c : Thermo-electric cooler current

Figure 8d : Rear face power dissipation vs.

Figure 8d : Thermo-electric cooler current

Figure 9 : Pt resistance variation R = R(T°C) - R(0°C) vs. temperature

-3

-6

-12

T°C<0

T°C>0

Rpt = 100 {1+[3.90802 10 T] - [0.580195 10 T ] - [4.7350 10 (T-100) T ]}

-3

-6

Rpt = 100 {1+[3.90802 10 T] - [0.580195 10 T ]}

12/20

TH7426A/27A

OUTLINE DRAWING

In the standard version devices are hermetically sealed in a Jlead 84 like package with a near IR transparent window (see

next drawing). The package basement includes a thermoelectric cooler and a temperature sensor, see Figures 8-9 for ther-

mal characteristics.

Silicon, with an antireflective coating is the window material. An optional version used an AR coated glass and an additional

frame (numerical aperture f/3) to prevent parasitic lateral visible light.

The photodiode array location is mechanically indexed upon the package rear face (opposite to the window) for fast accu-

rate mounting.

PACKAGE VARIANT (N)

(Thermoelectric cooler version)

13/20

TH7426A/27A

ORDERING INFORMATION

V(1) W(2) a*

(1) Temperature range

V = -40 to 85°C (see § c*)

(2) Package family

Ceramic Jlead type

a* Image grade

J, K, O, E see Table 1

b* Package variant

S = standard silicon window

R = clear glass window

N = non sealed removable window

c* Package sub-variant

(The detector temperature depends on the surrounding ambient and on device energy budget which is directly

related to the built in thermo-cooler option efficiency.)

- = without thermo-electric cooler; from -40 to +15°C full performances(derated over)

N = 1 stage thermo-electric cooler; from -40 to +60°C full performances (derated over)

P = 3 stages thermo-electric cooler; from -40 to +85°C full performances

d* Quality level

- = standard

D/T = industrial level

B/T = military levels

S = space level

14/20

TH7426A/27A

APPLICATION INFORMATION

- Preload generation

Preload is fed up when Φ

is at low level. This process needs few time to be completed ( >35 ns). Then skimming is nee-

ded to calibrate Qb. This step needs as much as possible time. Therefore it is recommended to activate Φ

as soon as

is at low level, in order to spend most of

low level duration for skimming.

Qb depends on (V

- V

) difference, thus noise on Qb may result from differential fluctuations between V

and V

. It

GL2

GL1

is therefore recommended to get V

and V

biases on each side (Odd or Even) from the same power supply line.

GL1

GL2

- Preload level adjustment

Preload level must be chosen so as to covered both expected maximum signal and dark current resulting signal. It must be noti-

ced that the “Vidicon mode” implies output signal has the largest amplitude in darkness (since most of Qb is to be readout).

Since output signal treatment difficulty may arise from its large amplitude it is better to reduce as much as possible its dyna-

mic, thus to reduce preload level to the minimum required.

From Figure 6, dark voltage can be deduced, photosignal is computed from Figures 3 & 4 and application data (light flux, in-

tegration time). Preload must be 200 mV in excess to dark voltage and maximum photosignal sum. Preload can be adjusted

with (V

- V

) biases, as indicated in Figure 7, however it is recommended to act first on V

. Direct read out of pre-

GL2

GL1

GL2

load level is possible in forcing Φ at low level avoiding lateral transfer and photodiode read out.

TH7426A/27A maximum preload is about 2.5 V (corresponding to 10 electrons).

- Photodiode information collection

As explained this operation needs two steps :

a). Qb injection into input nodes.

b). Skimming back into main register of extra charges.

Step a) needs at least 1 µs to be completed (TX1). However, step b) is a longer process, which duration influences lateral

transfer efficiency. It has been measured that 20 µs is needed for less than 1 % transfer non efficiency which raises to 2 %

for 4 µs skimming time (TX2).

Thus it is recommended to allow as long as possible skimming time, compatible with application requirement.

- Output signal format

Figures 1 and 2 give details on output signal. Each reset (Φ ) pulse pulls up the output at reset level related to VDR bias.

Using typical biases, reset level reaches about 12 volts with respect to Vss. Notice that

is at high level.

must be pulsed only when

Just after reset pulse, output level is stabilizing to a steady level called “floating diode level”. This level is the very reset level

to be taken into account for useful signal amplitude measurement. It is about 200 mV lower than reset level.

Then on

falling edge, charges coming from main register last stage arrive. Consequently, output signal drops down.

The new steady level reached, counted from “floating diode” level represents the useful information - Uos -

Uos amplitude is maximum when no lateral transfer has occurred, since it represents preload level. In darkness, after pho-

todiode read out (lateral transfer) Uos is reduced by dark voltage signal. Under illumination Uos is still smaller until satura-

tion occurs (whole preload consumption), in this situation “floating diode” level is maintained until next pixel readout.

- Read enable operation

RE input simplifies device operation since it allows to use continuous

and generate external interruption during transfer. In this case, first pixel data will be read out at first falling edge of

. After 150 periods all pixel data will have been read out, on 151

clocks. However, one can force RE at high level

period, output will be unused preload and so

on until next

cycle.

When using RE input, it must be noticed that RE duration must at least allow 150 main register transfers (

periods) in

order to guaranty that all main register stages contain a preload (Qb) before next

not be properly reset at next cycle.

cycle. Otherwise all photodiodes will

When RE is low, output signal is continuously at floating diode level, with

transparencies.

- Interlacing odd even

As odd and even sides are fully separated, it is possible to drive odd and even side with 180° phase shifted

and

(

with same phase with respect to their ), being identicals. In this manner Odd output signals will be de-

layed by half a Tck period with respect to Even outputs allowing, after common sampling, natural multiplexing and double

pixel data rate. This opportunity is presented in application hints (Figures 10 to 12).

- Mechanical mounting

Accurate mechanical references are provided in N and P subvariant packages (see ordering information and outline dra-

wings). If optics are mechanically referred to these packages rear face, no tuning strategy could be implemented for scale

manufacturing.

15/20

TH7426A/27A

APPLICATION HINTS

Figure 10 : Application hint : device operation

16/20

TH7426A/27A

Figure 11 : Application hint : signal treatment

17/20

TH7426A/27A

Figure 12 : Timing diagramm for figure 10 &11 (Output data : 1 MHz)

18/20

TH7426A/27A

NOTE

19/20

TH7426A/27A

Information furnished is believed to be accurate and reliable. However THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES

assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of

third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent

rights of THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES. Specifications mentioned in this publication are subject to

change without notice. This publication supersedes and replaces all information previously supplied. THOMSON-CSF

SEMICONDUCTEURS SPECIFIQUES products are not authorized for use as critical components in life support devices or

systems without express written approval from THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES.

1998 THOMSON-

This product is manufactured by THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - 38521 SAINT-EGREVE / FRANCE.

For further information please contact : THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - Route Départementale

128 - B.P. 46 - 91401 ORSAY Cedex / FRANCE - Tél. : (33)(0) 1.69.33.00.00 / Téléfax : (33)(0) 1.69.33.03.21.

E-mail : lafrique@tcs.thomson.fr - Internet : http://www.tcs.thomson-csf.com

20/20

TH7426AVWJNGB/T [ATMEL]

相关型号：

TH7426AVWJNGD/T

TH7426AVWJNGS

TH7426AVWJNNG

TH7426AVWJNNGB/T

TH7426AVWJNNGD/T

TH7426AVWJNNGS

TH7426AVWJNPG

TH7426AVWJNPGB/T

TH7426AVWJNPGD/T

TH7426AVWJNPGS

TH7426AVWJRG

TH7426AVWJRGB/T