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TS68C000MEB/C10A [ATMEL]

Microprocessor, 32-Bit, 10MHz, HCMOS, CQCC68, CERAMIC, LCC-68;
TS68C000MEB/C10A
型号： TS68C000MEB/C10A
厂家： ATMEL    ATMEL
描述：

Microprocessor, 32-Bit, 10MHz, HCMOS, CQCC68, CERAMIC, LCC-68
文件： 总52页 (文件大小：667K)
中文：  中文翻译
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Features  
• 16-/32-bit Data and Address Register  
• 16-Mbyte Direct Addressing Range  
• 56 Powerful Instruction Types  
• Operations on Five Main Data Types  
• Memory Mapped Input/Output  
• 14 Addressing Modes  
• Three Available Versions: 8 MHz/10 MHz and 12.5 MHz  
• Military Temperature Range: -55/+125°C  
• Power Supply: 5VDC ± 10%  
Low Power  
HCMOS  
16-/32-bit  
Hi-Rel  
Description  
The TS68C000 reduced power consumption device dissipates an order of magnitude  
less power than the HMOS TS68000. The TS68C000 is an implementation of the  
TS68000 16/32 microprocessor architecture. The TS68C000 has a 16-bit data bus  
and 24-bit address bus while the full architecture provides for 32-bit address and data-  
buses. It is completely code-compatible with the HMOS TS68000, TS68008 8-bit data  
bus implementation of the TS68000 and the TS68020 32-bit implementation of the  
architecture. Any user-mode programs written using the TS68C000 instruction set will  
run unchanged on the TS68000, TS68008 and TS68020. This is possible because the  
user programming model is identical for all processors and the instruction sets are  
proper sub-sets of the complete architecture.  
Microprocessor  
TS68C000  
Screening/Quality  
This product is manufactured in full compliance with:  
• MIL-STD-883 class B  
• DESC drawing 5962-89462  
• Atmel standards  
C Suffix  
F Suffix  
DIL 64  
Ceramic Package  
CQFP 68  
Ceramic Quad Flat Pack (on request)  
E Suffix  
LCCC 68  
R Suffix  
PGA 68  
Leadless Ceramic Chip Carrier  
Pin Grid Array  
Rev. 2170A–HIREL–09/05  
1. General Description  
1.1  
Introduction  
This detail specification contains both a summary of the TS68C000 as well as detailed set of  
parametrics. The purpose is twofold to provide an instruction to the TS68C000 and support for  
the sophisticated user. For detail information on the TS68C000, refer to "68000 16-bit micropro-  
cessor user’s manual".  
1.2  
Detailed Block Diagram  
The functional block diagram is given in Figure 1-1 below.  
Figure 1-1. Block Diagram  
Status  
and  
Control  
Clock Gen.  
and  
Clock  
Timing Control  
Interrupt  
Control  
Bus  
Control  
Logic  
Instruction  
Decode  
System  
Control  
Signals  
Control  
Store  
V
V
CC  
GND  
M Store  
N Store  
Alu Function  
and Reg  
Selection  
Internal  
Control  
bus  
Instruction  
Register  
DATA BUS  
Data  
Bus  
Buffer  
16-bit  
Data  
Bus  
Address High  
Execution Unit  
and Registers  
Address Low  
Execution Unit  
and Registers  
Data Execution  
Unit  
and Registers  
Addr.  
Bus  
Buffer  
32-bit  
Address  
Bus  
16-bit  
Alu  
16-bit  
Alu  
16-bit  
Alu  
ADDRESS BUS  
2
TC68C000  
2170A–HIREL–09/05  
TS68C000  
1.3  
Pin Assignments  
Figure 1-2. 64-lead Dual-in-Line Package  
Index  
D5  
D6  
D7  
D8  
D4  
D3  
1
64  
63  
62  
61  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
2
3
D2  
D1  
4
D0  
5
D9  
AS  
6
D10  
D11  
D12  
D13  
D14  
D15  
GND  
A23  
A22  
A21  
UDS  
LDS  
R/W  
DTACK  
BG  
7
8
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
BGACK  
BR  
V
CC  
CLK  
GND  
HALT  
RESET  
VMA  
E
TOP VIEW  
V
CC  
A20  
A19  
A18  
A17  
VPA  
BERR  
IPL2  
IPL1  
IPL0  
FC2  
FC1  
FC0  
A1  
A16  
A15  
A14  
A13  
A12  
A11  
A10  
A9  
A8  
A7  
A6  
A5  
A2  
A3  
A4  
3
2170A–HIREL–09/05  
Figure 1-3. 68-terminal Pin Grid Array  
L
NC FC2 FC0 A1 A3 A4 A6 A7 A9 NC  
J
FC1 NC A2 A5 A8 A10 A11 A14  
A13 A12 A16  
BERR IPL0  
H
G
F
E
IPL2 IPL1  
A15 A17  
A18 A19  
VMA VPA  
BOTTOM VIEW  
HALT RESET  
CLK GND  
E
D
C
B
A
V
A20  
A21  
CC  
V
CC  
GND  
BR  
D13 A23 A22  
D0 D3 D6 D9 D11 D14 D15  
BGACK BG R/W  
DTACK LDS UDS  
NC  
1
D1 D2 D4 D5 D7 D8 D10 D12  
AS  
2
3
4
5
6
7
8
9
10  
Index  
Figure 1-4. 68-lead Quad Pack  
Index  
DTACK  
BG  
BGACK  
BR  
D13  
D14  
D15  
GND  
GND  
A23  
A22  
A21  
10  
60  
59  
58  
57  
56  
55  
54  
53  
52  
51  
50  
49  
48  
47  
46  
45  
44  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
V
CC  
CLK  
GND  
GND  
NC  
TOP VIEW  
V
CC  
HALT  
RESET  
VMA  
E
A20  
A19  
A18  
A17  
A16  
A15  
A14  
A13  
VPA  
BERR  
IPL2  
IPL1  
4
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Figure 1-5. 68-ceramic Quad Flat Pack  
Index  
68  
52  
1
51  
DTACK  
BG  
BGACK  
BR  
D13  
D14  
D15  
GND  
GND  
A23  
A22  
A21  
V
CC  
CLK  
GND  
GND  
NC  
TOP VIEW  
V
CC  
HALT  
RESET  
VMA  
E
A20  
A19  
A18  
A17  
A16  
A15  
A14  
A13  
VPA  
BERR  
IPL2  
IPL1  
17  
35  
18  
34  
1.4  
Terminal Designations  
The function, category and relevant symbol of each terminal of the device are given in the follow-  
ing table.  
Table 1-1.  
Symbol  
VCC  
Terminal Designations  
Function  
Category  
Supply  
Power supply (2 terminals)  
Power supply (2 terminals)  
Processor status  
(1)  
VSS  
Terminals  
Outputs  
Inputs  
FC0 to FC2  
IPL0 to IPL2  
A1 to A23  
AS  
Interrupt control  
Address bus  
Outputs  
R/W  
Outputs  
UDS  
Asynchronous bus control  
Bus arbitration control  
LDS  
DTACK  
BR  
Input  
Inputs  
Output  
BGACK  
BG  
5
2170A–HIREL–09/05  
Table 1-1.  
Symbol  
BERR  
RESET  
HALT  
Terminal Designations (Continued)  
Function  
Category  
Input  
System control  
Input/Output  
VPA  
Input  
VMA  
6800 peripheral control  
Output  
Output  
Input  
E
CLK  
Clock  
D0 to D15  
Data bus  
Input/Output  
Note:  
1. VSS is the reference terminal for the voltages  
1.5  
Signal Description  
The input and output signals are illustrated functionally in Figure 1-6 and are described in the fol-  
lowing paragraphs.  
Figure 1-6. Input and Output Signals  
V
CC  
ADDRESS  
BUS  
GND  
A1 - A23  
D0 - D15  
CLK  
DATA BUS  
AS  
R/W  
ASYNCHRONOUS  
BUS  
UDS  
LDS  
FC0  
FC1  
FC2  
PROCESSOR  
STATUS  
CONTROL  
MICROPROCESSOR  
DTACK  
BR  
E
VMA  
VPA  
BUS  
ARBITRATION  
CONTROL  
PERIPHERAL  
CONTROL  
BG  
BGACK  
IPL0  
IPL1  
IPL2  
BERR  
RESET  
HALT  
SYSTEM  
CONTROL  
INTERRUPT  
CONTROL  
Table 1-2.  
UDS  
High  
Data Strobe Control of Data Bus  
LDS  
High  
Low  
Low  
High  
Low  
Low  
High  
R/W  
D8-D15  
D0-D7  
No valid data  
No valid data  
Low  
High  
High  
High  
Low  
Low  
High  
Valid data bits 8-15  
No valid data  
Valid data bits 0-7  
Valid data bits 0-7  
No valid data  
High  
Low  
Valid data bits 8-15  
Valid data bits 8-15  
Valid data bits 0-7  
Valid data bits 8-15  
Low  
Valid data bits 0-7  
Valid data bits 0-7  
Valid data bits 8-15  
High  
Low  
6
TC68C000  
2170A–HIREL–09/05  
TS68C000  
1.5.0.1  
Address Bus (A1 through A23)  
This 24-bit, unidirectional, three-state bus is capable of addressing 16 megabytes of data. It pro-  
vides the address for bus operation during all cycles except interrupt cycles. During interrupt  
cycles, address lines A1, A2 and A3 provide information about what level interrupt is being ser-  
viced while address lines A4 through A23 are set to a logic high.  
1.5.0.2  
1.5.0.3  
Data Bus (D0 Through D15)  
This 16-bit, bidirectional, three-state bus is the general-purpose data path. It can transfer and  
accept data in either word or byte length. During an interrupt acknowledge cycle, the external  
device supplies the vector number on data lines D0-07.  
Asynchronous Bus Control  
Asynchronous data transfers are handled using the following control signals: address strobe,  
read/write, upper and lower data strobes, and data transfer acknowledge. These signals are  
explained in the following paragraphs.  
ADDRESS STROBE (AS)  
This signal indicates that there is a valid address on the address bus.  
READ/WRITE (R/W)  
This signal defines the data bus transfer as a read or write cycle. The R/W signal also works in  
conjunction with the data strobes as explained in the following paragraph.  
UPPER AND LOWER DATA STROBE (UDS, LDS)  
These signals control the flow of data on the data bus, as shown in Table 1-2. When the R/W  
line is high, the processor will read from the data bus as indicated. When the R/W line is low, the  
processor will write to the data bus as shown.  
DATA TRANSFER ACKNOWLEDGE (DTACK)  
This input indicates that the data transfer is completed. When the processor recognizes DTACK  
during a read cycle, data is latched and the bus cycle terminated. When DTACK is recognized  
during a write cycle, the bus cycle is terminated.  
1.5.0.4  
Bus Arbitration Control  
The three signals, bus request, bus grant, and bus grant acknowledge, form a bus arbitration cir-  
cuit to determine which device will be the bus master device.  
BUS REQUEST (BR)  
This input is wire ORed with all other devices that could be bus masters. This input indicates to  
the processor that some other device desires to become the bus master.  
BUS GRANT (BG)  
This output indicates to all other potential bus master devices that the processor will release bus  
control at the end of the current bus cycle.  
BUS GRANT ACKNOWLEDGE (BGACK)  
This input indicates that some other device has become the bus master.  
7
2170A–HIREL–09/05  
This signal should not be asserted until the following four conditions are met:  
1. a bus grant has been received,  
2. address strobe is inactive which indicates that the microprocessor is not using the bus,  
3. data transfer acknowledge is Inactive which indicates that neither memory nor peripher-  
als are using the bus, and  
4. bus grant acknowledge is inactive which indicates that no other device is still claiming  
bus mastership.  
1.5.0.5  
1.5.0.6  
Interrupt Control (IPL0, IPL1, IPL2)  
These Input pins indicate the encoded priority level of the device requesting an interrupt. Level  
seven is the highest priority white level zero indicates that no interrupts are requested. Level  
seven cannot be masked. The least significant bit is given in IPLO and the most significant bit is  
contained in IPL2. These lines must remain stable until the processor signals interrupt acknowl-  
edge (FC0-FC2 are all high) to insure that the interrupt is recognized.  
System Control  
The system control inputs are used to either reset or halt the processor and to indicate to the  
processor that bus errors have occurred. The three system control inputs are explained in the  
following paragraphs.  
BUS ERROR (BERR)  
This input informs the processor that there is a problem with the cycle currently being executed.  
Problems may be a result of:  
1. nonresponding devices,  
2. interrupt vector number acquisition failure,  
3. illegal access request as determined by a memory management unit, or  
4. other application dependent errors.  
The bus error signal interacts with the halt signal to determine if the current bus cycle should be  
re-executed or if exception processing should be performed.  
RESET (RESET)  
This bidirectional signal line acts to reset (start a system initialization sequence) to processor in  
response to an external reset signal. An internally generated reset (result of a RESET instruc-  
tion) causes all external devices to be reset and the internal of the processor is not affected. A  
total system reset (processor and external devices) is the result of external HALT and RESET  
signals applied at the same time.  
HALT (HALT)  
When this bldirectional line is driven by an external device, it will cause the processor to stop at  
the completion of the current bus cycle. When the processor has been halted using this input, all  
controI signals are inactive and all three-state lines are put in their high-impedance state.  
When the processor has stopped executing Instructions, such as in a double bus fault condition,  
the HALT line is driven by the processor to indicate to external devices that the processor has  
stopped.  
8
TC68C000  
2170A–HIREL–09/05  
TS68C000  
1.5.0.7  
EF 6800 Peripheral Control  
These control signals are used to allow the interfacing of synchronous EF 6800 peripheral  
devices with the asynchronous TS68C000. These signals are explained in the following  
paragraphs.  
ENABLE (E)  
This signal is the standard enable signal common to all EF 6800 type peripheral devices. The  
period for this output is ten TS68C000 clock periods (six clocks low, four clocks high). Enable is  
generated by an internal ring counter which may come up in any state (i.e., at power on, it Is  
impossible to guarantee phase relationship of E to CLK). E is a free-running crack and runs  
regardless of the state of the bus on the MPU.  
VALID PERIPHERAL ADDRESS (VPA)  
This input indicates that the device or region addressed is an TS68000 Family device and that  
data transfer should be synchronized with the enable (E) signal. This Input also indicates that  
the processor should use automatic vectoring for an interrupt during an IACK cycle.  
VALID MEMORY ADDRESS (VMA)  
This output is used to indicate to TS68000 peripheral devices that there is a valid address on the  
address bus and the processor is synchronized to enable. This signal only responds to a valid  
peripheral address (VPA) input which indicates that the peripheral is an TS68000 Family device.  
1.5.0.8  
Processor Status (FC0, FC1, FC2)  
These function code outputs indicate the state (user or supervisor) and the cycle type currently  
being executed, as shown in Table 1-3. The information indicated by the function code outputs is  
valid whenever address strobe (AS) is active.  
Table 1-3.  
Processor Status Table  
Function Code Output  
FC2  
Low  
Low  
Low  
Low  
High  
High  
High  
High  
FC1  
Low  
Low  
High  
High  
Low  
Low  
High  
High  
FC0  
Low  
High  
Low  
High  
Low  
High  
Low  
High  
Cycle Time  
(Undefined, reserved)  
User data  
User program  
(Undefined, reserved)  
(Undefined, reserved)  
Supervisor data  
Supervisor program  
Interrupt acknowledge  
1.5.0.9  
Clock (CLK)  
The clock input is a TTL-compatible signal that is internally buffered for development of the inter-  
nal clocks needed by the processor. The clock input should not be gated off at any time and the  
clock signal must conform to minimum and maximum pulse width times. The clock is a constant  
frequency square wave with no stretching or shaping techniques required.  
9
2170A–HIREL–09/05  
2. Detailed Specifications  
2.1  
Scope  
This drawing describes the specific requirements for the microprocessor TS68C000, 8 MHz, 10  
MHz and 12.5 MHz, in compliance with MIL-STD-883 class B.  
2.2  
Applicable Documents  
2.2.1  
MIL-STD-883  
1. MIL-STD-883: Test Methods and Procedures For Electronics  
2. MIL-PRF-38535 Appendix A: General Specifications for Microcircuits  
2.3  
Requirements  
2.3.1  
General  
The microcircuits are in accordance with the applicable document and as specified herein.  
2.4  
Design and Construction  
2.4.1  
Terminal Connections  
Depending on the package, the terminal connections shall be as shown in Figure 1-2, Figure 1-  
3, Figure 1-4 and Figure 1-5.  
2.4.2  
2.4.3  
Lead Material and Finish  
Lead material and finish shall be any option of MIL-PRF-38535 Appendix A-3-5-6 "Package Ele-  
ment Material and Finsh".  
Package  
The macrocircuits are packaged in hermetically sealed ceramic package which is conform to  
case outlines of MIL-PRF-38535 Appendix A-3-5-1.  
• PGA68 64 LEAD DIP  
• 64 DILSQ. LCC 68 PINS  
• 68 LCCC68 TERMINALS JCC  
• 68 CQFP  
The precise case outlines are described on figures and into MIL-M-38510.  
2.4.4  
Electrical Characteristics  
2.4.4.1  
Absolute Maximum Ratings  
Limiting conditions (ratings) defined below shall not be for inspection purposes. However some  
limiting conditions (ratings) may be taken in other parts of this specification as detail conditions  
for an applicable test.  
Unless otherwise stated, all voltages are referenced to the reference terminal as defined in  
Table 1-1, ”Terminal Designations” on page 5 of this specification.  
10  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Table 2-1.  
Absolute Maximum Ratings  
Parameter  
Symbol  
Test Conditions  
Min  
-0.3  
-0.3  
NA  
Max  
Unit  
V
VCC  
VI  
Supply voltage  
+6.5  
+6.5  
NA  
Input voltage  
V
VO  
VOZ  
IO  
Output voltage  
V
Off state voltage  
Output currents  
Input currents  
-0.3  
NA  
11.0  
NA  
V
mA  
mA  
W
Ii  
NA  
NA  
T
CASE = -55°C  
0.27  
0.27  
+150  
+150  
+270  
PDMAX  
Max power dissipation  
TCASE = +125°C  
W
TSTG  
TJ  
Storage temperature  
Junction temperature  
Lead temperature  
-55  
°C  
°C  
°C  
TLEADS  
Max 5 sec. Soldering  
2.4.4.2  
Recommended Condition of Use and Guaranteed Characteristics  
• Guaranteed Characteristics (Table 2-5 and Table 2-8)  
The characteristics associated to a specified measurement in the detail specification shall  
only be for inspection purposes.  
Such characteristic defined in this specification is guaranteed only under the conditions and  
within the limits which are specified for the relevant measurement. Unless otherwise speci-  
fied, this guarantee applies within all the recommended operating ranges specified below.  
• Recommended conditions of use (Table 2-2)  
To the correct operation of the device, the conditions of use shall be within the ranges speci-  
fied below (see also above).  
These conditions shall not be for inspection purposes.  
Some recommended values may, however, be taken in other parts of this specification as  
detail conditions for an applicable test (Table 2-9).  
• Additional Electrical Characteristics (Table 2-9), see ”Additional Electrical Characteristics” on  
page 30.  
Figure 2-1. Clock Input Timing Diagram  
t
cyc  
t
t
CL  
CH  
2.0V  
0.8V  
t
t
Cr  
Cf  
Note:  
Timing measurements are referenced to and from a low voltage of 0.8V and a high voltage of 2.0V,  
unless otherwise noted. The voltage swing through this range should start outside, and pass  
through, the range such that the rise of fall will be linear between 0.8V and 2.0V.  
Unless otherwise stated, all voltages are referenced to the reference terminal (see Table 1-1).  
11  
2170A–HIREL–09/05  
Table 2-2.  
Recommended Condition of Use  
Operating Range  
Symbol  
VCC  
VIL  
Parameter  
Model  
All  
Min  
4.5  
0
Max  
5.5  
Unit  
V
Supply voltage  
Low level input voltage  
All  
0.8  
V
VIH  
High level input voltage (see also ”Package” on page 10)  
Operating temperature  
All  
2.0  
VCC  
+125  
V
TCASE  
RL  
All  
-55  
°C  
Ω
(1)  
Value of output load resistance  
Output loading capacitance  
Clock rise time (see Figure 2-1)  
Clock fall time (see Figure 2-1)  
All  
(1)  
CL  
All  
pF  
ns  
tr(c)  
All  
10  
10  
tf(c)  
All  
ns  
TS68C000-8  
TS68C000-10  
TS68C000-12  
TS68C000-8  
TS68C000-10  
TS68C000-12  
TS68C000-8  
TS68C000-10  
TS68C000-12  
TS68C000-8  
TS68C000-10  
TS68C000-12  
4.0  
4.0  
4.0  
125  
100  
80  
8.0  
MHz  
MHz  
MHz  
ns  
fC  
Clock frequency (see Figure 2-1)  
Clock time (see Figure 2-1)  
10.0  
12.5  
250  
250  
250  
125  
125  
125  
125  
125  
125  
tCYC  
ns  
ns  
55  
ns  
tW(CL)  
Clock pulse width low (see Figure 2-1)  
Cycle pulse width high (see Figure 2-1)  
45  
ns  
35  
ns  
55  
ns  
tW(CH)  
45  
ns  
35  
ns  
Note:  
1. Load networks number 1 to 4 as specified in ”Test Conditions Specific to the Device” on page 26 (Figure 2-2 and Figure 2-3)  
gives the maximum loading for the relevant output.  
2.4.4.3  
Special Recommended Conditions for CMOS Devices  
1. CMOS Latch-up  
The CMOS cell is basically composed of two complementary transistors (a P-channel and an N-  
channel), and, in the steady state, only one transistor is turned-on. The active P-channel transis-  
tor sources current when the output is a logic high and presents a high impedance when the  
output is a logic low. Thus the overall result is extremely low power consumption because there  
is no power loss through the active P.channel transistor. Also since only once transistor is deter-  
mined by leakage currents.  
Because the basic CMOS cell is composed of two complementary transistors, a virtual semicon-  
ductor controlled rectifier (SCR) may be formed when an input exceeds the supply voltage. The  
SCR that is formed by this high input causes the device to become "Iatched" in a mode that may  
result in excessive current drain and eventual destruction of the device. Although the device is  
Implemented with input protection diodes, care should be exercised to ensure that the maximum  
input voltages specification is not exceeded tram voltage transients; others may require no addi-  
tional circuitry.  
12  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
2. CMOS Applications  
• The TS68C000 completely satisfies the input/output drive requirements of CMOS logic  
devices.  
• The HCMOS TS68C000 provides an order of magnitude power dissipation reduction when  
compared to the HMOS TS68000. However, the TS68C000 does not offer a "power down" or  
"halt" mode. The minimum operating frequency of the TS68C000 is 4 MHz.  
2.4.5  
Thermal Characteristics  
Thermal Characteristics  
Table 2-3.  
Package  
Symbol  
θJA  
Parameter  
Value  
25  
6
Unit  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
°C/W  
Thermal resistance junction to ambient  
Thermal resistance junction to case  
Thermal resistance junction to ambient  
Thermal resistance junction to case  
Thermal resistance junction to ambient  
Thermal resistance junction to case  
Thermal resistance junction to ambient  
Thermal resistance junction to case  
DIL 64  
PGA 68  
LCCC 68  
CQFP 68  
θJC  
θJA  
30  
6
θJC  
θJA  
40  
8
θJC  
θJA  
40  
10  
θJC  
2.4.5.1  
Power Considerations  
The average chip-junction temperature, TJ, in °C can be obtained from:  
TJ = TA + (PD . θJA)  
(1)  
TA = Ambient Temperature, °C  
θ
JA = Package Thermal Resistance, Junction-to-Ambient, °C/W  
PD = PINT + PI/O  
PINT = ICC x VCC, Watts – Chip Internal Power  
P
I/O = Power Dissipation on Input and Output Pins – User Determined  
For most applications PI/O < PINT and can be neglected.  
An Approximate relationship between PD and TJ (if PI/O is neglected) is:  
PD = K: (TJ + 273)  
(2)  
Solving equations (1) and (2) for K gives:  
2
K = PD. (TA + 273) + θJA · PD  
(3)  
where K is constant pertaining to the particular part K can be determined from the equation (3)  
by measuring PD (at equilibrium) for a known TA. Using this value of K, the values of PD and TJ  
can be obtained by solving equations (1) and (2) iteratively for any value of TA.  
The total thermal resistance of a package (θJA) can be separated into two components, θJC and  
θ
CA, representing the barrier to heat flow from the semiconductor junction to the package (case),  
surface (θJC) and from the case to the outside ambient (θCA).  
13  
2170A–HIREL–09/05  
These terms are related by the equation:  
θ
θ
JA = θJC + θCA  
(4)  
JA is device related and cannot be influenced by the user. However, θCA is user dependent and  
can be minimized by such thermal management techniques as heat sinks, ambient air cooling  
and thermal convection. Thus, good thermal management on the part of the user can signifi-  
cantly reduce θCA so that θJA approximately equals θJC. Substitution of θJC for θJA in equation (1)  
will result in a lower semiconductor junction temperature.  
2.4.6  
2.4.7  
Mechanical and Environmental  
The microcircuits shall meet all mechanical environmental requirements of MIL-STD-883 for  
class B devices.  
Marking  
The document where are defined the marking are identified in the related reference documents.  
Each microcircuit is legible and permanently marked with the following information as minimum:  
• Atmel Logo  
• Manufacturer’s Part Number  
• Class B Identification  
• Date-code of inspection lot  
• ESD Identifier if Available  
• Country of Manufacturing  
2.5  
Quality Conformance Inspection  
2.5.1  
DESC/MIL-STD-883  
Is in accordance with MIL-PRF-38535 and method 5005 of MIL-STD-883. Group A and B  
inspections are performed on each production lot. Group C and D inspection are performed on a  
periodical basis.  
2.6  
Electrical Characteristics  
2.6.1  
General Requirements  
All static and dynamic electrical characteristics specified for inspection purposes and the rele-  
vant measurements conditions are given below:  
• Table 2-4: Static Electrical Characteristics for all electrical variants.  
• Table 2-5, Table 2-6, Table 2-7 and Table 2-8: Dynamic electrical characteristics for 8 MHz,  
10 MHz and 12.5 MHz.  
For static characteristics (Table 2-4), test methods refer to IEC 748-2 method number, where  
existing.  
For dynamic characteristics, test methods refer to clause ”Test Conditions Specific to the  
Device” on page 26 of this specification (Table 2-5, Table 2-6, Table 2-7 and Table 2-8).  
Indication of "min" or "max" in the column "test temperature" means minimum or maximum oper-  
ating temperatures as defined in sub-clause ”Recommended Condition of Use and Guaranteed  
Characteristics” on page 11 here above.  
14  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Table 2-4.  
Static Characteristics  
V
CC = 5.0V VDC ± 10%; GND = 0 VDC; Tc = -55/+125°C and -40°C/+85°C  
Limits  
Ref  
Test  
Number  
Number  
(**)  
Test  
Conditions  
Test  
Temperature  
Min  
(*)  
Max  
(*)  
Symbol  
Parameter  
Unit  
VCC = 5.5V  
FC = 8 MHz  
FC = 10 MHz  
FC = 12 MHz  
42  
45  
50  
1
2
3
ICC  
Supply current  
41  
37  
37  
All  
mA  
VCC = 4.5V  
25°C  
max  
min  
Low level output  
(1)  
VOL  
voltage for: A1 to A23  
FC0 to FC2; BG  
0.5  
0.5  
V
V
IOL = 3.2 mA  
CC = 4.5V  
V
25°C  
max  
min  
Low level output  
voltage for:  
HALT  
(2)  
VOL  
IOL = 1.6 mA  
CC = 4.5V  
Low level output  
voltage for:  
V
25°C  
max  
(3)  
4
VOL  
AS; R/W:  
37  
0.5  
V
D0 to D15 UDS;  
LDS; VMA and E  
IOL = 5.3 mA  
CC = 4.5V  
min  
V
25°C  
max  
min  
Low level output  
voltage for:  
RESET  
(4)  
5
6
VOL  
37  
37  
38  
38  
38  
38  
0.5  
VCC – 0.75  
2.5  
V
IOL = 5.0 mA  
CC = 4.5V  
V
25°C  
max  
min  
High level output  
VOH  
2.4  
-2.5  
-20  
V
voltage for all outputs  
IOH = -400 µA  
CC = 5.5V  
V
25°C  
max  
min  
High level input current  
(1)  
7
IIH  
µA  
µA  
µA  
µA  
for all inputs excepted  
HALT and RESET  
VI = 5.5V  
VCC = 5.5V  
25°C  
max  
min  
Low level input current  
(1)  
8
IIL  
for all inputs excepted  
HALT and RESET  
VI = 0V  
VCC = 5.5V  
25°C  
max  
min  
High level input  
current for:  
(2)  
9
IIH  
20  
HALT and RESET  
VI = 5.5V  
VCC = 5.5V  
25°C  
max  
min  
Low level input  
current for:  
(2)  
10  
IIL  
HALT and RESET  
VI = 0V  
15  
2170A–HIREL–09/05  
Table 2-4.  
Static Characteristics (Continued)  
V
CC = 5.0V VDC ± 10%; GND = 0 VDC; Tc = -55/+125°C and -40°C/+85°C  
Limits  
Max  
Ref  
Number  
(**)  
Test  
Number  
Test  
Conditions  
Test  
Temperature  
Min  
(*)  
Symbol  
Parameter  
(*)  
Unit  
VCC = 5.5V  
25°C  
max  
min  
High level output  
11  
12  
IOHZ  
20  
µA  
3-state leakage current  
VOH = 2.4V  
VCC = 5.5V  
25°C  
max  
min  
Low level output  
IOLZ  
VIH  
VIL  
20  
µA  
V
3-state leakage current  
VOL = 0.4V  
VCC = 4.5V  
25°C  
max  
min  
High level input  
13  
2.0  
voltage for all inputs  
VCC = 5.5V  
VCC = 4.5V  
25°C  
max  
min  
0.8  
0.8  
0.8  
25  
V
Low level input  
14  
V
voltage for all inputs  
VCC = 5.5V  
V
25°C  
max  
min  
pF  
pF  
pF  
pF  
pF  
pF  
Reverse  
voltage = 0V  
f = 1.0 MHz  
Input capacitance  
(all inputs)  
14A  
CIN  
11  
11  
NA  
NA  
20  
25°C  
max  
min  
Reverse  
voltage = 0V  
f = 1.0 MHz  
Output capacitance  
(all inputs)  
14B  
14C  
COUT  
NA  
NA  
Internal protection  
Transient energy rating  
See note(9)  
5 cycles  
VTEST  
25°C  
-500  
+500  
V
Note:  
* Algebraic values  
** Measurement method: see ”General Requirements” on page 14 and ”Test Conditions Specific to the Device” on page 26.  
Referred notes are given on page 25.  
Table 2-5.  
Dynamic Characteristics – TS68C000-8  
V
CC = 5.0 VDC ± 10%; GND = 0 VDC; Tc = -55/+125°C and Tc = -40°C/+85°C  
Limits  
Figure  
Test  
Number  
Number  
(**)  
Test  
Conditions  
Test  
Temperature  
Min  
(*)  
Max  
(*)  
Symbol  
Parameter  
Unit  
See ”Input and  
Output Signals  
for Dynamic  
Measurements”  
on page 29  
25°C  
max  
Set-up time  
Data-in to clock low(1)  
27  
tSU (DICL)  
10 – 11  
20(10)  
ns  
min  
(a) to (c)  
fC = 8 MHz  
16  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Table 2-5.  
Dynamic Characteristics – TS68C000-8 (Continued)  
V
CC = 5.0 VDC ± 10%; GND = 0 VDC; Tc = -55/+125°C and Tc = -40°C/+85°C  
Limits  
Figure  
Test  
Number  
Number  
(**)  
Test  
Conditions  
Test  
Temperature  
Min  
(*)  
Max  
(*)  
Symbol  
Parameter  
Unit  
25°C  
max  
min  
Set-up time  
tSU  
(SDTCL)  
47  
47  
47  
47  
47  
2
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
Idem test 27  
Idem test 27  
Idem test 27  
Idem test 27  
Idem test 27  
Idem test 27  
Idem test 27  
20(10)  
20(10)  
20(10)  
20(10)  
20(10)  
55(10)  
55  
ns  
DTACK low to clock  
low(1)  
25°C  
max  
min  
Set-up time  
BR low to clock low (1)  
tSU  
(SBRCL)  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
25°C  
max  
min  
Set-up time  
tSU  
(SBGCL)  
BGACK low to clock  
low(1)  
25°C  
max  
min  
Set-up time  
tSU  
(SVPACL)  
VPA low to clock low  
(1)  
25°C  
max  
min  
tSU  
(SBERCL)  
Set-up time BERR  
low to clock low(1)  
25°C  
max  
min  
tw  
(CL)  
Clock width low  
Clock width high  
125  
125  
70  
25°C  
max  
min  
tw  
3
(CH)  
25°C  
max  
min  
tPLH  
tPHL  
(CHFCV)  
Idem  
test 27  
Load: 3  
Propagation time  
clock high to FC valid  
6A  
9
25°C  
max  
min  
Idem  
test 27  
Load: 4  
tPHL  
(CHSLX)  
Propagation time  
clock high to AS low  
60(3)  
60(3)  
70(3)  
25°C  
max  
min  
Propagation time  
CLK high to LDS,  
UDS low  
Idem  
test 27  
Load: 4  
tPHL  
(CHSL)  
9
ns  
ns  
25°C  
max  
min  
Idem  
test 27  
Load: 4  
tPLH  
(CLSH)  
Propagation time  
CLK low to AS high  
12  
17  
2170A–HIREL–09/05  
Table 2-5.  
Dynamic Characteristics – TS68C000-8 (Continued)  
V
CC = 5.0 VDC ± 10%; GND = 0 VDC; Tc = -55/+125°C and Tc = -40°C/+85°C  
Limits  
Figure  
Test  
Number  
Number  
(**)  
Test  
Conditions  
Test  
Temperature  
Min  
(*)  
Max  
(*)  
Symbol  
Parameter  
Unit  
25°C  
max  
min  
Propagation time  
CLK low to LDS, UDS  
high  
Idem  
test 27  
Load: 4  
tPLH  
(CLSH)  
12  
18  
20  
23  
6
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
12  
70(3)  
70(3)  
70(3)  
70(3)  
70  
ns  
25°C  
max  
min  
Idem  
test 27  
Load: 4  
tPLH  
(CHRHX)  
Propagation time  
CLK high to R/W high  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
25°C  
max  
min  
Idem  
test 27  
Load: 4  
tPHL  
(CHRL)  
Propagation time  
CLK high to R/W low  
25°C  
max  
min  
tPZL  
tPZH  
(CLDO)  
Propagation time  
CLK low to Data-out  
valid  
Idem  
test 27  
Load: 4  
25°C  
max  
min  
tPZL  
tPZH  
(CLAV)  
Propagation time  
CLK low to Address  
valid  
Idem  
test 27  
Load: 3  
25°C  
max  
min  
RESET/HALT input  
transition time  
Idem  
test 27  
32  
33  
34  
40  
41  
8
tHRRF  
200  
70  
25°C  
max  
min  
Idem  
test 27  
Load: 3  
tPHL  
(CHGL)  
Propagation time  
CLK high to BG low  
25°C  
max  
min  
Idem  
test 27  
Load: 3  
tPLH  
(CHGH)  
Propagation time  
CLK high to BG high  
12  
70  
25°C  
max  
min  
Idem  
test 27  
Load: 4  
tPHL  
(CLVM)  
Propagation time  
CLK low to VMA low  
13  
70  
25°C  
max  
min  
Idem  
test 27  
Load: 4  
tPHL  
(CLE)  
Propagation time  
CLK low to E low  
13  
70  
25°C  
max  
min  
Idem  
test 27  
Load: 3  
th  
Hold time CLK high  
to Address  
10 – 11  
0
(SHAZ)  
18  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Table 2-5.  
Dynamic Characteristics – TS68C000-8 (Continued)  
V
CC = 5.0 VDC ± 10%; GND = 0 VDC; Tc = -55/+125°C and Tc = -40°C/+85°C  
Limits  
Figure  
Test  
Number  
Number  
(**)  
Test  
Conditions  
Test  
Temperature  
Min  
(*)  
Max  
(*)  
Symbol  
Parameter  
Unit  
25°C  
max  
min  
Set-up time  
Address valid to  
AS, LDS, UDS low  
Idem  
test 27  
Load: 4  
tSU  
(AVSL)  
11  
35  
37  
48  
48  
26  
10 – 11  
30(4)  
ns  
25°C  
max  
min  
3.5  
CLKS  
Propagation time  
BR low to  
BG low  
Idem  
test 27  
Load: 3  
tPHL  
(BRLGL)  
(2)  
12  
1.5  
ns  
+90  
3.5  
25°C  
max  
min  
CLKS  
Propagation time  
BGACK low to  
BG high  
Idem  
test 27  
Load: 3  
tPLH  
(GALEH)  
(2)  
12  
1.5  
ns  
+90  
–
25°C  
max  
min  
Set-up time  
BERR low to  
DTACK low  
tSU  
(BELDAL)  
Idem  
test 27  
11  
20(5)  
20(5)  
30(4)  
ns  
25°C  
max  
min  
Set-up time  
BERR low to  
DTACK low  
tSU  
(BELDAL)  
Idem  
test 27  
10 – 11  
–
–
ns  
ns  
25°C  
max  
min  
Hold time  
Data-out valid to  
LDS, UDS low  
Idem  
test 27  
Load: 4  
th  
11  
(DOSL)  
Note:  
* Algebraic values  
** Measurement method: see ”General Requirements” on page 14 and ”Test Conditions Specific to the Device” on page 26  
Referred notes are given on page 25.  
Table 2-6.  
Dynamic Characteristics – TS68C000-10  
Limits  
Figure  
Number  
(**)  
Test  
Number  
Test  
Conditions  
Test  
Temperature  
Min  
(*)  
Max  
(*)  
Symbol  
Parameter  
Unit  
See ”Input and  
Output Signals  
for Dynamic  
Measurements”  
on page 29  
25°C  
max  
Set-up time  
27  
47  
t
SU (DICL)  
10 – 11  
10 – 11  
20(10)  
ns  
Data-in to clock low(1)  
min  
(a) to (c)  
fc = 10 MHz  
25°C  
max  
min  
Set-up time  
tSU  
Idem test 27  
20(10)  
ns  
DTACK low to clock  
low(1)  
(SDTCL)  
19  
2170A–HIREL–09/05  
Table 2-6.  
Dynamic Characteristics – TS68C000-10 (Continued)  
Limits  
Figure  
Test  
Number  
Number  
(**)  
Test  
Conditions  
Test  
Temperature  
Min  
(*)  
Max  
(*)  
Symbol  
Parameter  
Unit  
25°C  
max  
min  
Set-up time  
BR low to clock low (1)  
tSU  
(SBRCL)  
47  
47  
47  
47  
2
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
Idem test 27  
20(10)  
20(10)  
20(10)  
20(10)  
45  
ns  
25°C  
max  
min  
Set-up time  
tSU  
(SBGCL)  
Idem test 27  
Idem test 27  
Idem test 27  
Idem test 27  
Idem test 27  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
BGACK low to clock  
low(1)  
25°C  
max  
min  
Set-up time  
tSU  
(SVPACL)  
VPA low to clock low  
(1)  
25°C  
max  
min  
tSU  
(SBERCL)  
Set-up time BERR  
low to clock low(1)  
25°C  
max  
min  
tw  
(CL)  
Clock width low  
Clock width high  
125  
125  
60  
25°C  
max  
min  
tw  
3
45  
(CH)  
25°C  
max  
min  
tPLH  
tPHL  
(CHFCV)  
Idem  
test 27  
Load: 3  
Propagation time  
clock high to FC valid  
6A  
9
25°C  
max  
min  
Idem  
test 27  
Load: 4  
tPHL  
(CHSLX)  
Propagation time  
clock high to AS low  
55(3)  
55(3)  
55(3)  
55(3)  
25°C  
max  
min  
Propagation time  
CLK high to LDS,  
UDS low  
Idem  
test 27  
Load: 4  
tPHL  
(CHSL)  
9
25°C  
max  
min  
Idem  
test 27  
Load: 4  
tPLH  
(CLSH)  
Propagation time  
CLK low to AS high  
12  
12  
25°C  
max  
min  
Propagation time  
CLK low to LDS, UDS  
high  
Idem  
test 27  
Load: 4  
tPLH  
(CLSH)  
20  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Table 2-6.  
Dynamic Characteristics – TS68C000-10 (Continued)  
Limits  
Figure  
Test  
Number  
Number  
(**)  
Test  
Conditions  
Test  
Temperature  
Min  
(*)  
Max  
(*)  
Symbol  
Parameter  
Unit  
25°C  
max  
min  
Idem  
test 27  
Load: 4  
tPLH  
(CHRHX)  
Propagation time  
CLK high to R/W high  
18  
20  
23  
6
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
12  
60(3)  
60(3)  
55(3)  
60  
ns  
25°C  
max  
min  
Idem  
test 27  
Load: 4  
tPHL  
(CHRL)  
Propagation time  
CLK high to R/W low  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
25°C  
max  
min  
tPZL  
tPZH  
(CLDO)  
Propagation time  
CLK low to Data-out  
valid  
Idem  
test 27  
Load: 4  
25°C  
max  
min  
tPZL  
tPZH  
(CLAV)  
Propagation time  
CLK low to Address  
valid  
Idem  
test 27  
Load: 4  
25°C  
max  
min  
tHRRF  
(CHGL)  
RESET/HALT input  
transition time  
Idem  
test 27  
32  
33  
34  
40  
41  
8
200  
60  
25°C  
max  
min  
Idem  
test 27  
Load: 3  
tPHL  
(CHGL)  
Propagation time  
CLK high to BG low  
25°C  
max  
min  
Idem  
test 27  
Load: 3  
tPLH  
(CHGH)  
Propagation time  
CLK high to BG high  
12  
60  
25°C  
max  
min  
Idem  
test 27  
Load: 4  
tPHL  
(CLVM)  
Propagation time  
CLK low to VMA low  
13  
70  
25°C  
max  
min  
Idem  
test 27  
Load: 4  
tPHL  
(CLE)  
Propagation time  
CLK low to E low  
13  
55  
25°C  
max  
min  
Idem  
test 27  
Load: 3  
tH  
Hold time CLK high  
to Address  
10 – 11  
10 – 11  
0
(SHAZ)  
25°C  
max  
min  
Set-up time  
Address valid to  
AS, LDS, UDS low  
Idem  
test 27  
Load: 4  
tSU  
(AVSL)  
11  
20(4)  
21  
2170A–HIREL–09/05  
Table 2-6.  
Dynamic Characteristics – TS68C000-10 (Continued)  
Limits  
Figure  
Test  
Number  
Number  
(**)  
Test  
Conditions  
Test  
Temperature  
Min  
(*)  
Max  
(*)  
Symbol  
Parameter  
Unit  
25°C  
max  
min  
3.5  
CLKS  
Propagation time  
BR low to  
BG low  
Idem  
test 27  
Load: 3  
tPHL  
(BRLGL)  
(2)  
35  
37  
48  
48  
26  
12  
12  
1.5  
1.5  
ns  
+80  
3.5  
25°C  
max  
min  
CLKS  
Propagation time  
BGACK low to  
BG high  
Idem  
test 27  
Load: 3  
tPLH  
(GALGH)  
(2)  
ns  
+80  
25°C  
max  
min  
Set-up time  
BERR low to  
DTACK low  
tSU  
(BELDAL)  
Idem  
test 27  
11  
20(5)  
20(5)  
20(4)  
ns  
25°C  
max  
min  
Set-up time  
BERR low to  
DTACK low  
tSU  
(BELDAL)  
Idem  
test 27  
10 – 11  
ns  
ns  
25°C  
max  
min  
Hold time  
Data-out valid to  
LDS, UDS low  
Idem  
test 27  
Load: 4  
tH  
11  
(DOSL)  
Note:  
* Algebraic values  
** Measurement method: see ”General Requirements” on page 14 and ”Test Conditions Specific to the Device” on page 26  
Referred notes are given on page 25.  
Table 2-7.  
Dynamic Characteristics – TS68C000-12  
Limits  
Figure  
Number  
(**)  
Test  
Number  
Test  
Temperature  
Min  
(*)  
Max  
(*)  
Symbol  
Parameter  
Test Conditions  
Unit  
See ”Input and  
Output Signals for  
Dynamic  
Measurements” on  
page 29  
25°C  
max  
Set-up time  
27  
tSU (DICL)  
10 – 11  
10(10)  
ns  
Data-in to clock  
low(1)  
min  
(a) to (c)  
fC = 12 MHz  
25°C  
max  
min  
Set-up time  
tSU  
(SDTCL)  
47  
47  
10 – 11  
10 – 11  
Idem test 27  
Idem test 27  
20(10)  
ns  
ns  
DTACK low to  
clock low(1)  
25°C  
max  
min  
Set-up time  
tSU  
(SBRCL)  
20(10)  
BR low to clock  
low(1)  
22  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Table 2-7.  
Dynamic Characteristics – TS68C000-12 (Continued)  
Limits  
Figure  
Test  
Number  
Number  
Test  
Temperature  
Min  
(*)  
Max  
(*)  
Symbol  
Parameter  
(**)  
Test Conditions  
Unit  
25°C  
max  
min  
Set-up time  
tSU  
(SBGCL)  
47  
47  
47  
2
10 – 11  
Idem test 27  
20(10)  
20(10)  
20(10)  
35  
ns  
BGACK low to  
clock low(1)  
25°C  
max  
min  
Set-up time  
tSU  
(SVPACL)  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
10 – 11  
Idem test 27  
Idem test 27  
Idem test 27  
Idem test 27  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
VPA low to clock  
low(1)  
25°C  
max  
min  
tSU  
Set-up time BERR  
(SBERCL) low to clock low(1)  
25°C  
max  
min  
tw  
Clock width low  
(CL)  
125  
125  
55  
25°C  
max  
min  
tw  
3
Clock width high  
(CH)  
35  
25°C  
max  
min  
tPLH  
tPHL  
(CHFCV)  
Propagation time  
clock high to FC  
valid  
Idem  
test 27  
Load: 3  
6A  
9
25°C  
max  
min  
Propagation time  
clock high to AS  
low  
Idem  
test 27  
Load: 4  
tPHL  
(CHSLX)  
55(3)  
55(3)  
50(3)  
50(3)  
60(3)  
25°C  
max  
min  
Propagation time  
CLK high to LDS,  
UDS low  
Idem  
test 27  
Load: 4  
tPHL  
(CHSL)  
9
25°C  
max  
min  
Propagation time  
CLK low to LDS,  
UDS high  
Idem  
test 27  
Load: 4  
tPLH  
(CLSH)  
12  
12  
18  
25°C  
max  
min  
Propagation time  
CLK low to LDS,  
UDS high  
Idem  
test 27  
Load: 4  
tPLH  
(CLSH)  
25°C  
max  
min  
Propagation time  
CLK high to R/W  
high  
Idem  
test 27  
Load: 4  
tPLH  
(CHRHX)  
23  
2170A–HIREL–09/05  
Table 2-7.  
Dynamic Characteristics – TS68C000-12 (Continued)  
Limits  
Figure  
Test  
Number  
Number  
Test  
Temperature  
Min  
(*)  
Max  
(*)  
Symbol  
Parameter  
(**)  
Test Conditions  
Unit  
25°C  
max  
min  
Propagation time  
CLK high to R/W  
low  
Idem  
test 27  
Load: 4  
tPHL  
(CHRL)  
20  
23  
6
11  
60(3)  
55(3)  
55  
ns  
25°C  
max  
min  
tPZL  
tPZH  
(CLDO)  
Propagation time  
CLK low to Data-  
out valid  
Idem  
test 27  
Load: 4  
11  
10 – 11  
10 – 11  
8 – 9  
12  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
25°C  
max  
min  
tPZL  
tPZH  
(CLAV)  
Propagation time  
CLK low to  
Address valid  
Idem  
test 27  
Load: 4  
25°C  
max  
min  
RESET/HALT  
transition time  
Idem  
test 27  
32  
33  
34  
40  
41  
8
tHRRF  
150  
50  
25°C  
max  
min  
Propagation time  
CLK high to BG  
low  
Idem  
test 27  
Load: 3  
tPHL  
(CHGL)  
25°C  
max  
min  
Propagation time  
CLK high to BG  
high  
Idem  
test 27  
Load: 3  
tPLH  
(CHGH)  
50  
25°C  
max  
min  
Propagation time  
CLK low to VMA  
low  
Idem  
test 27  
Load: 4  
tPHL  
(CLVM)  
13  
70  
25°C  
max  
min  
Idem  
test 27  
Load: 4  
tPHL  
(CLE)  
Propagation time  
CLK low to E low  
13  
45  
25°C  
max  
min  
Idem  
test 27  
Load: 3  
tH  
Hold time CLK  
high to Address  
10 – 11  
10 – 11  
12  
0
(SHAZ)  
25°C  
max  
min  
Set-up time  
Address valid to  
AS, LDS, UDS low  
Idem  
test 27  
Load: 4  
tSU  
(AVSL)  
11  
35  
15(4)  
25°C  
max  
min  
3.5  
CLKS  
Propagation time  
BR low to  
BG low  
Idem  
test 27  
Load: 3  
tPHL  
(BRLGL)  
(2)  
1.5  
ns  
+70  
24  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Table 2-7.  
Dynamic Characteristics – TS68C000-12 (Continued)  
Limits  
Figure  
Test  
Number  
Number  
Test  
Temperature  
Min  
(*)  
Max  
(*)  
Symbol  
Parameter  
(**)  
Test Conditions  
Unit  
25°C  
max  
min  
3.5  
CLKS  
Propagation time  
BGACK low to  
BG high  
Idem  
test 27  
Load: 3  
tPLH  
(GALGH)  
(2)  
37  
48  
48  
26  
12  
1.5  
ns  
+70  
25°C  
max  
min  
Set-up time  
BERR low to  
DTACK low  
tSU  
(BELDAL)  
Idem  
test 27  
11  
10 – 11  
11  
20(5)  
20(5)  
15(4)  
ns  
25°C  
max  
min  
Set-up time  
BERR low to  
DTACK low  
tSU  
(BELDAL)  
Idem  
test 27  
ns  
ns  
25°C  
max  
min  
Hold time  
Data-out valid to  
LDS, UDS low  
Idem  
test 27  
Load: 4  
tH  
(DOSL)  
Note:  
* Algebraic values  
** Measurement method: see ”General Requirements” on page 14 and ”Test Conditions Specific to the Device” on page 26  
2.6.1.1  
Referred notes to Table 2-4, Table 2-5, Table 2-6, Table 2-7  
The following notes shall apply where referred into Table 2-4, Table 2-5, Table 2-6 and Table 2-  
7.  
Notes: 1. If the asynchronous setup tlme (47) requirements are satisfied, the DTACK low-to-data setup time (31) requirement Gan be  
ignored. The data must only satisfy the data-in to clock-low setup time (27) for the following cycle.  
2. Where "CLKS" is stated as unit time limit, the relevant time in nanoseconds shall be calculated as the actual cycle time of  
clock signal input multiply by the given number of CLKS limits.  
3. For a loading capacitance of less than or equal to 50 picofarads, substrate 5 nanoseconds from the value given in the maxi-  
mum columns.  
4. Actual value depends on period.  
5. If 47 is satisfied for bath DTACK and BERR, 48 may be 0 nanoseconds.  
6. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting  
BGACK.  
7. The falling edge of 56 triggers bath the negation of the strobes (AS, and X DS) and the falling edge of E. either of these  
events can occur first depending upon the loading on each signal. Specification 49 indicates the absolute maximum skew  
that will occur between the rising edge of the strobes and the falling edge of the E clock.  
8. When AS and R/W are equally loaded (±20%), substrate 10 nanoseconds from the values in these columns.  
9. Each terminal of the device under test shall be tested separately against all existing VCC and VSS terminals of the device  
which shall be shorted together for the test. The other untested terminals shall be unconnected during the test. One cycle  
consists of the application of the bath limits as given in Table 2-5, Table 2-6 and Table 2-7.  
10. This value should be treated as a min for design purpose. For the conformance testing the value shall be regarded as the  
maximum time.  
25  
2170A–HIREL–09/05  
Table 2-8.  
AC Electrical Specification – Clock Timing  
8 MHz  
10 MHz  
Min  
12.5 MHz  
Symbol  
Parameter  
Min  
4.0  
Max  
8.0  
Max  
10.0  
250  
Min  
Max  
12.5  
250  
Unit  
MHz  
ns  
f
Frequency of operation  
Cycle time  
4.0  
4.0  
80  
tcyc  
125  
250  
100  
tCL  
tCH  
55  
55  
125  
125  
45  
45  
125  
125  
35  
35  
125  
125  
Clock pulse width  
Rise and fall times  
ns  
ns  
tCr  
tCf  
10  
10  
10  
10  
10  
10  
2.6.2  
Test Conditions Specific to the Device  
2.6.2.1  
Loading Network  
The applicable loading network shall be as defined in column "Test Conditions" of Table 2-5,  
Table 2-6 and Table 2-7, referring to the loading network number as shown in Figure 2-2 and  
Figure 2-3 below.  
Figure 2-2. Passive Loads  
+ V  
CC  
R
n
OUTPUT  
C
1
Figure 2-3. Active Loads  
+ V  
CC  
R
n
OUTPUT  
1N 914  
C
R
1
1
26  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
(1)  
Load NBR  
Figure  
5.1  
R1  
–
Rn  
C1  
Output Application  
1
2
3
4
910Ω  
130 pF  
70 pF  
RESET  
5.1  
–
2.9 kΩ  
1.22 kΩ  
740Ω  
HALT  
5.2  
6.0 k  
6.0 k  
130 pF  
130 pF  
A1 to A23, BG and FC0 to FC2  
All other outputs  
5.2  
Note:  
Time Definitions  
1. C1 includes all parasitic capacitances of test machines  
2.6.2.2  
The times specified in Table 2-5, Table 2-6 and Table 2-7 as dynamic characteristics are defined  
in Figure 2-4 to Figure 2-7 below by a reference number given in the column "Method" of the  
tables together with the relevant figure number.  
Figure 2-4. Read Cycle Timing  
1
S0  
S1  
S2  
S3  
S4  
S5  
S6  
S7  
3
2
CLK  
5
4
6
7
A1-A23  
12  
10  
9
8
14  
AS  
15  
13  
12  
11  
LDS/UDS  
15  
19  
17  
18  
R/W  
FC0-FC2  
6A  
11A  
47  
ASYNCHRONOUS  
INPUTS  
HALT/RESET  
BERR/BR  
32  
32  
56  
30  
47  
47  
28  
48  
27  
DTACK  
29  
31  
DATA IN  
27  
2170A–HIREL–09/05  
Figure 2-5. Write Cycle Timing  
S0  
S0  
S1  
S2  
S3  
S4  
S5  
S6  
S7  
CLK  
7
6
10  
A1-A23  
8
9
16  
14  
AS  
10  
13  
15  
9
14A  
LDS/UDS  
20  
22  
21  
53  
25  
23  
R/W  
21A  
7
26  
DATA OUT  
FC0-FC2  
55  
6A  
ASYNCHRONOUS  
INPUTS  
47  
HALT/RESET  
32  
32  
56  
30  
47  
BERR/BR  
DTACK  
28  
47  
48  
28  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Figure 2-6. AC Electrical Waveforms – Bus Arbitration  
STROBES  
AND R/W  
36  
16  
BR  
37  
46  
BGACK  
35  
39  
34  
BG  
38  
33  
CLK  
Figure 2-7. Enable/Interface Timing  
S5 S6 S7 S0  
w w w w w w w  
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w
w w w  
S2 S3 S4  
S0 S1  
CLK  
41  
A1-A23  
AS  
44  
52  
51  
49  
42  
E
50  
41  
42  
43  
40  
VPA  
VMA  
45  
24  
R/W  
(READ)  
27  
DATA IN  
UDS/LDS  
READ  
R/W  
WRITE  
54  
23  
DATA OUT  
UDS/LDS  
WRITE  
2.6.2.3  
Input and Output Signals for Dynamic Measurements  
1. Input pulse characteristics  
Where input pulse generator is loaded by only a 50Ω resistor, the input pulse characteristics  
shall be as shown in Figure 2-8.  
29  
2170A–HIREL–09/05  
Figure 2-8. Input Pulse Characteristics  
2.4V  
2.0V  
0.8V  
0.45V  
t
= 0.5 ns  
t
= 0.5 ns  
ra  
ra  
2. Time measurement input voltage references  
Input voltages which are taken as reference for time measurement shall be:  
VIL = 0.8V  
V
IH = 2.0V  
3. Time measurement input voltage references  
Where output is (or becomes to) valid state, the output voltages which are taken as reference for  
time measurements, shall be as shown in Figure 2-9.  
Figure 2-9. Output Voltage References  
Voltage Reference  
V
= 2.4V  
OH  
High  
Voltage Reference  
Low  
V
= 0.5V  
OL  
t
t
t
PZH  
t
PZL  
PLH  
PHL  
2.6.3  
Additional Information  
Additional information shall not be for any inspection purposes.  
2.6.3.1  
2.6.3.2  
Power Considerations  
See ”Thermal Characteristics” on page 13.  
Additional Electrical Characteristics  
The following additional characteristics, which are obtained from circuit design, are given for  
Information only.  
Unless otherwise stated, for dynamic additional characteristics, the given reference numbers  
refer to Figure 2-1 to Figure 2-7 and loading number refer to Figure 2-2 and Figure 2-3 (see  
”Test Conditions Specific to the Device” on page 26 of this specification).  
The given limits should be valid for all operating temperature ranges as defined in ”Recom-  
mended Condition of Use and Guaranteed Characteristics” on page 11 of this specification.  
30  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Table 2-9.  
Item  
Additional Electrical Characteristics  
TS68C000-8  
Limits  
TS68C000-10  
Limits  
TS68C000-12  
Limits  
Ref  
Load  
NO.  
Symbol  
Parameter  
Number  
Number  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
High level output  
voltage for E  
with pull up  
VCC  
0.75  
-
VCC-  
0.75  
6A  
VOH  
Min  
Min  
Min  
V
CC-0.75  
V
R = 1.1K to VCC  
Propagation  
time CLK low to  
Address  
tPLZ  
Fig. 10  
Ref. 7  
37  
3
80  
70  
60  
60  
ns  
tPHZ  
(CLAZX)  
3-state  
Propagation  
time CLK high to  
(CHSZX) AS, LDS, UDS  
3-state  
Fig. 11  
Ref. 16  
tPHZ  
39  
40  
4
4
80  
70  
ns  
ns  
tPLZ  
tPHZ  
Propagation  
time CLK high to  
R/W 3-state  
Fig. 12  
Ref. 16  
80  
80  
70  
70  
60  
60  
(CHRZ)  
tPHZ  
Propagation  
time CLK high to  
Data 3-state  
Fig. 11  
Ref. 7  
41  
43  
4
3
ns  
ns  
tPLZ  
(CHAZX)  
Hold time AS,  
LDS, UDS high  
to Address  
tH  
Fig. 10  
Ref. 13  
30  
20  
10  
(SHAZ)  
tw  
Fig. 10  
Ref. 14  
240  
195  
160  
44  
45  
AS/DS width low  
ns  
ns  
(4)  
(4)  
(4)  
(SL)  
tw  
Fig. 10  
Ref. 15  
150  
(4)  
105  
(4)  
AS, LDS, UDS  
width high  
65  
(4)  
(SL)  
Set-up time  
LDS, UDS high  
to R/W high  
Fig. 10  
Ref. 17  
40  
20  
tSU  
(SHRH)  
10  
46  
47  
48  
49  
50  
52  
4
4
4
4
ns  
ns  
ns  
ns  
ns  
(4)  
(4)  
(4)  
Set-up time  
Address valid to  
R/W low  
Fig. 10  
Ref. 21  
20  
(4)  
0
(4)  
tSU  
(AVRL)  
0
(4)  
Propagation  
time R/W low to  
lds, uds low  
Fig. 11  
Ref. 22  
tPHL  
(RLSL)  
80  
50  
30  
(4)  
(4)  
(4)  
Hold time LDS,  
UDS high to  
Data-out  
Fig. 11  
Ref. 25  
tH  
30  
20  
15  
(4)  
(4)  
(4)  
(SHDO)  
Hold time AS,  
tH (SHDI) LDS, UDS high  
to Data-in  
Fig. 10  
Ref. 29  
0
0
0
Propagation  
tH  
CLKS  
Fig. 12  
Ref. 36  
(2)  
time BR high to  
(BRHGH)  
3
1.5  
3.5 + 90  
1.5  
3.5 + 80  
1.5  
3.5 + 70  
BG high(6)  
ns  
31  
2170A–HIREL–09/05  
Table 2-9.  
Item  
Additional Electrical Characteristics (Continued)  
TS68C000-8  
Limits  
TS68C000-10  
Limits  
TS68C000-12  
Limits  
Ref  
Load  
NO.  
Symbol  
Parameter  
Number  
Number  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
Propagation  
time BG low  
to Data and  
Address  
BG,  
address  
3
tPHZ  
Fig. 12  
Ref. 36  
54  
80  
70  
60  
ns  
tPLZ  
(GLZ)  
Data 4  
3-state  
Fig. 12  
Ref. 39  
CLKS  
ns  
55  
56  
tw (GH)  
BG width high  
1.5  
1.5  
1.5  
90  
Propagation  
time VMA low to  
E high  
Fig. 13  
Ref. 43  
tPLH  
(VMLEH)  
4
200  
150  
ns  
Fig. 20 Ref. 44  
(see”Although  
UDS and LDS  
are asserted,  
no data is read  
from the bus  
during the  
autovector  
cycle. The  
vector number  
is generated  
internally).” on  
page 45)  
Hold time AS,  
LDS, UDS high  
to VPA high  
tH  
57  
4
3
0
120  
0
90  
0
70  
ns  
ns  
(SHVPH)  
Fig. 13  
Ref. 45  
Hold time E low  
to address  
58  
59  
61  
62  
tH (ELAI)  
tw (BGL)  
tw (EH)  
tw (EL)  
30  
10  
1.5  
10  
1.5  
280  
440  
Fig. 12  
Ref. 46  
BGACK width  
low  
CLKS  
1.5  
(2)  
Fig. 13  
Ref. 50  
E width high  
E width low  
450  
700  
350  
550  
ns  
ns  
Fig. 13  
Ref. 51  
Fig. 10  
Ref. 1A  
or 11A  
Propagation  
time FC valid to  
AS, DS low  
tPHL  
(FCVSL)  
60  
50  
40  
63  
64  
4
4
ns  
ns  
(4)  
(4)  
(4)  
Propagation  
time AS, DS  
(SHDAH) high to DTACK  
high  
Fig. 10  
Ref. 28  
tPHL  
0
0
245(4)  
0
0
190(4)  
0
0
150(4)  
Propagation  
time AS, DS  
(SHBEH) high to BERR  
high  
Fig. 12  
Ref. 30  
tPLH  
65  
66  
4
ns  
ns  
Set-up time  
tSU  
Fig. 10  
Ref. 31  
DTACK low  
(DALDI)  
90(4)  
65(4)  
50(4)  
to Data-in(1)  
32  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Table 2-9.  
Item  
Additional Electrical Characteristics (Continued)  
TS68C000-8  
Limits  
TS68C000-10  
Limits  
TS68C000-12  
Limits  
Ref  
Load  
NO.  
Symbol  
Parameter  
Number  
Number  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
Transition time  
HALT, RESET  
input  
Fig. 10  
Ref. 32  
tTHL tTLH  
(RH)  
67  
200  
200  
200  
ns  
HALT and  
RESET pulse  
width after  
power up  
Fig. 10  
Ref. 56  
tw  
CLKS  
69  
10  
10  
10  
(2)  
(HRPW)  
Propagation  
time AS low  
to R/W valid  
Fig. 11  
tPHL  
(ASRV)  
70  
71  
73  
4
4
4
20(8)  
20(8)  
20(8)  
ns  
ns  
ns  
Ref. 20A  
Propagation  
time FC valid to  
R/W low  
Fig. 11  
tPHL  
(FCVRL)  
60  
50  
30  
(4)  
(4)  
(4)  
Ref. 21A  
Hold time CLK  
high to  
Data-out  
Fig. 11  
Ref. 53  
tH  
0
0
0
(CHDOI)  
Propagation  
time R/W low to  
Data-bus  
impedance  
change  
Fig. 11  
Ref. 55  
tPLH tPHL  
(RLDBO)  
74  
4
30  
20  
10  
ns  
Propagation  
time AS, DS low  
to E low  
Fig. 13  
Ref. 49  
tPHL  
(SHEL)  
75  
76  
4(7)  
-70  
30  
+70  
-55  
20  
+55  
-45  
15  
+45  
ns  
ns  
Hold time E low  
to  
Data-out  
Fig. 13  
Ref. 54  
tH  
4
(ELDOI)  
Notes: 1. If the asynchronous setup tlme (47) requirements are satisfied, the DTACK low-to-data setup time (31) requirement Gan be  
ignored. The data must only satisfy the data-in to clock-low setup time (27) for the following cycle.  
2. Where "CLKS" is stated as unit time limit, the relevant time in nanoseconds shall be calculated as the actual cycle time of  
clock signal input multiply by the given number of CLKS limits.  
3. For a loading capacitance of less than or equal to 50 picofarads, substrate 5 nanoseconds from the value given in the maxi-  
mum columns.  
4. Actual value depends on period.  
5. If 47 is satisfied for bath DTACK and BERR, 48 may be 0 nanoseconds.  
6. The processor will negate BG and begin driving the bus again if external arbitration logic negates BR before asserting  
BGACK.  
7. The falling edge of 56 triggers bath the negation of the strobes (AS, and X DS) and the falling edge of E. either of these  
events can occur first depending upon the loading on each signal. Specification 49 indicates the absolute maximum skew  
that will occur between the rising edge of the strobes and the falling edge of the E clock.  
8. When AS and R/W are equally loaded (±20%), substrate 10 nanoseconds from the values in these columns.  
9. Each terminal of the device under test shall be tested separately against all existing VCC and VSS terminals of the device  
which shall be shorted together for the test. The other untested terminals shall be unconnected during the test. One cycle  
consists of the application of the bath limits as given in Table 2-5, Table 2-6 and Table 2-7.  
10. This value should be treated as a min for design purpose. For the conformance testing the value shall be regarded as the  
maximum time.  
33  
2170A–HIREL–09/05  
2.7  
Functional Description  
2.7.1  
Description of Registers  
Figure 2-10. User Programming Model  
31  
16 15  
8
7
0
D0  
D1  
D2  
D3  
D4  
D5  
D6  
D7  
Eight Data Registers  
31  
16 15  
0
A0  
A1  
A2  
A3  
A4  
A5  
A6  
Seven Address Registers  
31  
31  
16 15  
0
0
0
A7 (USP) User Stack Pointer  
PC  
Program Counter  
Status Register  
7
CCR  
As shown in the user programming model (Figure 2-10), the TS68C000 offers 16/32 bits regis-  
ters and a 32 bits program counter. The first eight registers (D0 – D7) are used as data registers  
for byte (8-bit), and long word (32-bit) operations. The second set of seven registers (A0-A6) and  
the user stack pointer (USP) may be used as software stack pointers and base address regis-  
ters. In addition, the registers may be used for word and long word operations. All of the 16  
registers may be used as index registers.  
In supervisor mode, the upper byte of the status register and the supervisor stack pointer (SSP)  
are also available to the programmer. These registers are shown in Figure 2-11.  
34  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Figure 2-11. Supervisor Programming Model Supplement  
31  
16 15  
15  
0
Supervisor  
Stack Pointer  
A7 (SSP)  
0
8
7
(CCR)  
SR  
Status Register  
The status register (Figure 2-12) contains the interrupt mask (eight levels available) as well as  
the conditions codes: extend (X), negative (N), zero (Z), overflow (V), and carry (C). Additional  
status bits indicate that the processor is in a trace (T) mode and in a supervisor (S) or user state.  
Figure 2-12. Status Register  
User Byte  
(Condition Code Regiter)  
System Byte  
15  
T
13  
10  
8
0
4
0
I
I
I
1
S
X
N
Z
V
C
2
Extend  
Trace Mode  
Supervisor  
State  
Interrupt  
Mask  
Negative  
Zero  
Overflow  
Carry  
2.7.2  
Data Types and Addressing Modes  
Five basic data types are supported. These data types are:  
• Bits  
• BCD Digits (4 bits)  
• Bytes (8 bits)  
• Words (16 bits)  
• Long Words (32 bits)  
In addition, operations on other data types such as memory addresses, status ward data, etc.  
are provided in the instruction set.  
The 14 addressing modes, shown in Table 2-10, include six basic types:  
• Register Direct  
• Register Indirect  
• Absolute  
• program Counter Relative  
• Immediate  
• Implied  
35  
2170A–HIREL–09/05  
Included in the register indirect addressing modes is the capability to do post incrementing, pre-  
decrementing, offsetting, and indexing. The program counter relative mode can also be modified  
via Indexing and offsetting.  
2.7.3  
Data Transfer Operations  
Transfer of data between devices involves the following leads:  
1. address bus A1 through A23,  
2. data bus 00 through D15, and  
3. control signals.  
The address and data buses are separate parallel buses used to transfer data using an asyn-  
chronous bus structure. In all cycles, the bus master assumes responsibility for deskewing all  
signals it issues at bath the stan and end of a cycle. In addition, the bus master Is responsible for  
deskewing the acknowledge and data signals tram the slave device.  
The following paragraphs explain the read, write, and read-modify.write cycles. The indivisible  
read-modify-write cycle is the method used by the TS68C000 for interlocked multiprocessor  
communications.  
2.7.3.1  
Read Cycle  
During a read cycle, the processor receives data tram the memory of a peripheral devlce. The  
processor reads bytes of data in all cases. If the instruction specifies a ward (or double ward)  
operation, the processor reads both upper and lower bytes simultaneously. by asserting both  
upper and lower data strobes. When the instruction specifies byte operation, the processor uses  
an internal AO bit to determine which byte to read and then Issues the data strobe required for  
that byte. For byte operations, when the AO bit equals zero, the upper data strobes is issued.  
When the AO bit equals one, the lower data strobe is issued. When the data is received, the pro-  
cessor correctly positions is internally.  
2.7.3.2  
Write Cycle  
During a write cycle, the processor sends data to either the memory of a peripheral device. The  
processor writes bytes of data in all cases. If the instruction specifies a ward operation, the pro-  
cessor writes bath bytes. When the instruction specifies a byte operation, the processor uses an  
internal AO bit to determine which byte to write and then issues the data strobe required for that  
byte. For byte operations, when the AO bit equals zero, the upper data strobe is issued. When  
the AO bit equals one, the lower data strobe is issued.  
Table 2-10. Addressing Modes  
Addressing Modes  
Syntax  
Register direct addressing  
Data register direct  
Dn  
An  
Address register direct  
Absolute data addressing  
Absolute short  
xxx.W  
xxx.L  
Absolute long  
Program counter relative addressing  
Relative with offset  
d16 (PC)  
Relative with index offset  
d8 (PC, Xn)  
36  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Table 2-10. Addressing Modes (Continued)  
Addressing Modes  
Syntax  
Register Indirect Addressing  
Register Indirect  
(An)  
Postincrement Register Indirect  
Predecrement Register Indirect  
Register Indirect with Offset  
Indexed Register Indirect with Offset  
(An) +  
- (An)  
d16 (An)  
d8 (An, Xn)  
Immediate Data Addressing  
Immediate  
= XXX  
Quick Immediate  
= 1- = 8  
Implied Addressing  
Implied Register  
Notes:  
SR/USP/SP/PC  
Dn = Data Register  
An = Address Register  
Xn = Address of Data Register used as Index Register  
SR = Status Register  
PC = Program Counter  
SP = Stack Pointer  
USP = User Stack Pointer  
( ) = Effective Address  
d8 = 8-bit Offset (Displacement)  
d
16 = 16-bit Offset (Displacement)  
= xxx = Immediate Data  
37  
2170A–HIREL–09/05  
Table 2-11. Instruction Set Summary  
Mnemonic  
Description  
ABCD  
ADD  
AND  
ASL  
Add Decimal with Extend  
Add  
Logical AND  
Arithmetic Shift Left  
Arithmetic Shift Right  
ASR  
Bcc  
Branch Conditionally  
Bit Test and Change  
Bit Test and Clear  
Branch Always  
BCHG  
BCLR  
BRA  
BSET  
BSR  
Bit Test and Set  
Branch to Subroutine  
Bit Test  
BTST  
CHK  
CLR  
CMP  
Check Register Against Bounds  
Clear Operand  
Compare  
DBcc  
DIVS  
DIVU  
Test Condition, Decrement and Branch  
Signed Divide  
Unsigned Divide  
EOR  
EXG  
EXT  
Exclusive OR  
Exchange Registers  
Sign Extend  
JMP  
JSR  
Jump  
Jump to Subroutine  
LEA  
LINK  
LSL  
Lead Effective Address  
Link Stack  
Logical Shift Left  
Logical Shift Right  
LSR  
MOVE  
MULS  
MULU  
Move  
Signed Multiply  
Unsigned Multiply  
NBCD  
NEG  
NOP  
NOT  
Negate Decimal with Extend  
Negate  
No Operation  
One’s Complement  
OR  
Logical OR  
PEA  
Push Effective Address  
38  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Table 2-11. Instruction Set Summary (Continued)  
Mnemonic  
Description  
RESET  
ROL  
Rest External Devices  
Rotate Left without Extend  
Rotate Right without Extend  
Rotate Left with Extend  
Rotate Right with Extend  
Return from Exception  
Return and Restore  
ROR  
ROXL  
ROXR  
RTE  
RTR  
RTS  
Return form Subroutine  
SBCD  
Scc  
Subtract Decimal with Extend  
Set Conditional  
STOP  
SUB  
Stop  
Subtract  
SWAP  
Swap Data Register Halves  
TAS  
Test and Set Operand  
TRAP  
TRAPV  
TST  
Trap  
Trap on Overflow  
Test  
UNLK  
Unlink  
2.7.3.3  
Read Modify Write Cycle  
The read-modify-write cycle performs a read, modifies the data in the arithmetic-logic unit, and  
writes the data back to the same address. In the TS68C000, this cycle is indivisible in that the  
address strobe is asserted throughout the entire cycle. The test and set (TAS) instruction uses  
this cycle to provide meaningful communication between processors in a multiple processor  
environment. This Instruction is the only instruction that uses the read-modify-write cycles and  
since the test and set instruction only operates on bytes, all read-modify-write are byte  
operations.  
2.7.4  
Instruction Set Overview  
The TS68C000 instruction set is shown in Table 2-11. Some additional instructions are varia-  
tions, or sub-sets, of these and they appear in Table 2-12. Special emphasis has been given to  
the instruction set's support of structured high-level languages to facilitate ease of programming.  
Each instruction, with few exceptions, operates on bytes, words, and long words and most  
instructions can use any of the 14 addressing modes. Combining instruction types, data types,  
and addressing modes, over 1000 useful instructions are provided. These instructions include  
signed and unsigned, multiply and divide, "quick" arithmetic operations, BCD arithmetic, and  
expanded operations (through traps).  
39  
2170A–HIREL–09/05  
Table 2-12. Variations of Instruction Types  
Instruction Type  
Variation  
Description  
ADD  
Add  
ADDA  
ADDQ  
ADDI  
ADDX  
Add Address  
Add Quick  
ADD  
Add Immediate  
Add with Extend  
AND  
Logical AND  
ANDI  
And Immediate  
AND  
CMP  
EOR  
ANDI to CCR  
ANDI to SR  
And Immediate to Condition codes  
And Immediate to Status Register  
CMP  
Compare  
CMPA  
CMPM  
CMPI  
Compare Address  
Compare Memory  
Compare Immediate  
EOR  
Exclusive OR  
EORI  
Exclusive OR Immediate  
EORI to CCR  
EORI to SR  
Exclusive OR Immediate to condition Codes  
Exclusive OR Immediate to Status Register  
MOVE  
Move  
MOVEA  
Move Address  
MOVEM  
Move Multiple Registers  
Move Peripheral Data  
Move Quick  
MOVEP  
MOVE  
MOVEQ  
MOVE from SR  
MOVE to SR  
MOVE to CCR  
MOVE USP  
Move from Status Register  
Move to Status Register  
Move to Condition Codes  
Move User Stack Pointer  
NEG  
Negate  
NEG  
OR  
NEGX  
Negate with Extend  
OR  
Logical OR  
ORI  
OR Immediate  
ORI to CCR  
ORI to SR  
OR Immediate to Condition Codes  
OR Immediate to Status Register  
SUB  
Subtract  
SUBA  
SUBI  
SUBQ  
SUBX  
Subtract Address  
Subtract Immediate  
Subtract Quick  
Subtract Extend  
SUB  
40  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
2.7.5  
Processing States  
The TS68C000 is always in one of three processing states: normal, exception, or halted.  
2.7.5.1  
Normal Processing  
The normal processing state is that associated with instruction execution; the memory refer-  
ences are to fetch instructions and operands, and to store results. A special case of normal state  
is the stopped state which the processor enters when a stop instruction is executed. In this state,  
no further references are made.  
2.7.5.2  
2.7.5.3  
Exception Processing  
The exception processing state is associated with interrupts, trap instructions, tracing, and other  
exception conditions. The exception may be internally generated by an instruction or by an  
unusual condition arising during the execution of an instruction. Externally, exception processing  
can be forced by an interrupt, by a bus error, or by a reset. Exception processing is designed to  
provide an efficient context switch so that the processor may handle unusual conditions.  
Halted Processing  
The halted processing state is an Indication of catastrophic hardware failure. For example, if dur-  
ing the exception processing of a bus error another bus errors occurs, the processor assumes  
that the system is unusable and halts. Only an external reset can restart a halted processor.  
Note that a processor in the stopped state is not in the halted state, nor vice versa.  
Asserting the reset and halt line for ten cycles will cause a processor reset, except when VCC is  
initially applied to the processor. In this case, an external reset must be applied for least 100  
milliseconds.  
2.7.6  
Interface with EF 6800 Peripherals  
Extensive line of EF6800 peripherals are directly compatible with the TS68C000.  
Note: It is the own user's responsibility to verify the actual EF 6800 peripheral performances to  
be compatible to the actual used TS68C000 microprocessor performances.  
Soma of the EF 6800 peripheral that are particularly useful are:  
EF6821: Peripheral lnterface Adapter  
EF6840: Programmable Timer Module  
EF6850: Asynchronous Communications Interface Adapter  
EF6852: Synchronous Serial Data Adapter  
EF6854: Advanced Data Link Controller  
To interface the synchronous EF 6800 peripherals with the asynchronous TS68C000, the pro-  
cessor modifies its bus cycle to meet the EF 6800 cycle requirements whenever an EF 6800  
device address is detected. This is possible since both processors use memory mapped 1/0.  
Figure 2-13 is a flowchart of the interface operation between the processor and EF 6800  
devices.  
41  
2170A–HIREL–09/05  
Figure 2-13. EF6800 Interfacing Flowchart  
PROCESSOR  
SLAVE  
Initiate the cycle  
1) The Processor Starts a Normal Read or Write Cycle  
Define EF 6800 Cycle  
1) External Hardware Asserts Valid Peripheral  
Address (VPA)  
Synchronize with Enable  
1) The Processor Monitors Enable (E) until it is low  
(Phase 1)  
2) The Processor Asserts Valid Memory Address (VMA)  
Transfer the Data  
1) The Peripheral waits until E is active and then  
transfers the Data  
Terminate the Cycle  
1) The Processor waits until E goes low (on a read  
cycle the data is latched as E goes low (internally)  
2) The Processor negates VMA  
3) The Processor negates AS, UDS and LDS  
Start Next Cycle  
2.7.6.1  
Data Transfer Operation  
Three signals on processor provide the EF 6800 interface. They are: enable (E), valid memory  
address (VMA), and valid peripheral address (VPA). Enable corresponds to the E or phase 2 sig-  
nal i n existing EF 6800 systems. The bus frequency is one tenth of the incoming TS68C000  
clock frequency. The timing of E allows 1 MHz peripherals to be used 8 MHz TS68C000. Enable  
has a 60/40 duty cycle, that is, it is low for six input clocks and high for four input clocks. This  
duty cycle allows the processor to do successive VPA accesses on successive E pulses.  
EF6800 cycle timing is given in Figure 2-17 and Figure 2-18. At state zero (50) in the cycle, the  
address bus is in the high-impedance state. A function code is asserted on the function code  
output fines. One-half clock later, in state 1, the address bus is released from the high-imped-  
ance state.  
During state 2, the address strobe (AS) is asserted to indicate that there Is a valid address on  
the address bus. If the bus cycle is a read cycle, the upper and/or lower data strobes are also  
asserted in state 2. If the bus cycle is a write cycle, the read/write (R/W) signal is switched to low  
(write) during state 2. One-half clock later, in state 3, the write data Is placed on the data bus,  
and in state 4 the data strobes are issued to indicate valid data on the data bus. The processor  
now inserts wait states until it recognizes the assertion of VPA.  
The VPA input signals the processor that the address on the bus is the address of an EF 6800  
device (or an area reserved for EF6800 devices) and that the bus should conform to the phase 2  
transfer characteristics of the EF 6800 bus. Valid peripheral address is derived by decoding the  
address bus, conditioned by the address strobe. Chip select for the EF 6800 peripherals should  
be derived by decoding the address bus conditioned by VMA.  
42  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
After recognition of VPA, the processor assures that the enable (E) is low, by waiting if neces-  
sary, and subsequently asserts VMA. Valid memory address is then used as part of the chip  
select equation of the peripheral. This ensures that the EF6800 peripherals are selected and  
deselected at the correct time. The peripheral now runs its cycle during the high portion of the  
signal. Figure 2-17 and Figure 2-18 depict the best and worst case EF6800 cycle timing. This  
cycle length is dependent strictly upon when VPA Is asserted in relationship to the E clock.  
If it is assumed that external circuitry asserts VPA as soon as possible after the assertion of AS,  
then VPA will be recognized as being asserted on the falling edge of 54. In this case, no "extra"  
wait cycles will be inserted prior to the recognition of VPA asserted and only the wait cycles  
inserted to synchronize with the E clock will determine the total length of the cycle. In any case,  
the synchronization delay will be some integral number of clock cycles within the following two  
extremes:  
1. Best Case – VPA is recognized as being asserted on the falling edge three crack cycles  
before E rizes (or three clock cycles after E falls).  
2. Worst Case – VPA is recognized as being asserted on the falling edge two clock cycles  
before E rises (or four clock cycles after E falls).  
During a read cycle, the processor latches the peripheral data in state 6. For all cycles, the pro-  
cessor negates the address and data strobes one-half clack cycle rater in state 7 and the enable  
signal goes low at this time. Another half clock later, the address bus is put in the high-imped-  
ance state. During a write cycle the data bus is put in the high-impedance state and the  
read/write signal is switched high. The peripheral logic must remove VPA within one clock after  
the address strobe is negated.  
DTACK should not be asserted while VPA Is asserted. Notice that the TS68C000 VMA is active  
low, constrasted with the active high EF 6800 VMA. This allows the processor to put its buses in  
the high-impedance state on DMA requests without inadvertently selecting the peripherals.  
Figure 2-14. TS68C000 to EF6800 Peripheral Timing – Best Case  
S0  
S2  
S4  
w
w
w
w
S6 S0  
S2  
w
CLK  
A1-A23  
AS  
DTACK  
Data Out  
Data In  
FC0-FC2  
E
VPA  
VMA  
43  
2170A–HIREL–09/05  
Figure 2-15. TS68C000 to EF6800 Peripheral Timing – Worst Case  
w w w w S6  
S0 S2  
S4 w w w w w w w w w w w  
S0  
CLK  
A1-A23  
AS  
DTACK  
Data Out  
Data In  
FC0-FC2  
E
VPA  
VMA  
2.7.6.2  
Interrupt Interface Operation  
During an interrupt acknowledge cycle while the processor is fetching the vector, the VPA is  
asserted, the TS68C000 will assert VMA and complete a normal EF 6800 read cycle as shown  
in Figure 2-16. The processor will then use an internally generated vector that is a function of the  
interrupt being serviced. This process is know as autovectorlng. The seven autovectors are vec-  
tor number 25 through 31 (decimal).  
Autovectoring operates in the same fashion (but is not restricted to) the EF 6800 interrupt  
sequence. The basic difference is that there are six normal interrupt vectors and one NMI type  
vector. As with bath the EF 6800 and the TS68C(XX)'s normal vectored interrupt, the Interrupt  
service routine can be located any-where in the address space. This is due to the tact that while  
the vector numbers are fixed the contents of the vector table entries are assigned by the user.  
Since VMA is asserted during autovectoring. The EF 6800 peripheral address decoding should  
prevent unintended accesses.  
44  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Figure 2-16. Autovector Operation Timing Diagram  
S0 S2  
w w  
w
w
w S6  
S4 S6 S0 S2 S4  
w
w
w
w
w
S0 S2  
CLK  
A1-A3  
A4-A23  
AS  
UDS*  
LDS  
R/W  
DTACK  
D8-D15  
D0-D7  
FC0-FC2  
IPL0-IPL2  
E
VPA  
VMA  
Normal  
Cycle  
Autovector Operation  
Although UDS and LDS are asserted, no data is read from the bus during the autovector cycle.  
The vector number is generated internally).  
Table 2-13. Dynamic Electrical Characteristics TS68C000 to EF 6800 Peripheral  
8 MHz  
Limits  
10 MHz  
Limits  
12.5 MHz  
Limits  
Number  
12  
Symbol  
CLSH  
CHRH  
CHRL  
CLDO  
CLDO  
Parameter  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
ns  
Clock low to AS, DS high(1)  
Clock high to R/W high(1)  
70  
70  
70  
70  
55  
60  
60  
55  
50  
60  
60  
55  
18  
0
0
0
ns  
20  
Clock high to R/W low (write)(1)  
Clock low to data out valid (write)  
Data in to clock low (set up time on read)(2)  
ns  
23  
ns  
27  
15  
0
10  
0
10  
0
ns  
AS, DS high to Data in invalid (hold time on  
read)  
29  
SHDII  
ns  
40  
41  
42  
43  
44  
CLVML  
CLET  
Erf  
AS, DS high to VPA high  
Clock low to E transition  
E output rise and fall time  
VMA low to E high  
70  
70  
25  
70  
55  
25  
70  
45  
25  
ns  
ns  
ns  
ns  
ns  
VMLEH  
SHVPH  
200  
0
150  
0
90  
0
AS, DS high to VPA high  
120  
90  
70  
45  
2170A–HIREL–09/05  
Table 2-13. Dynamic Electrical Characteristics TS68C000 to EF 6800 Peripheral (Continued)  
8 MHz  
Limits  
10 MHz  
Limits  
12.5 MHz  
Limits  
Number  
Symbol  
Parameter  
Min  
Max  
Min  
Max  
Min  
Max  
Unit  
E low to control, address bus invalid  
(address hold time)  
45  
ELCAI  
30  
10  
10  
ns  
47  
49  
50  
51  
54  
ASI  
SHEL  
EH  
Asynchronous input setup time(2)  
AS, DS high to E low(3)  
E width high  
20  
-70  
450  
700  
30  
20  
-55  
350  
550  
20  
20  
-80  
280  
440  
15  
ns  
ns  
ns  
ns  
ns  
70  
55  
EL  
E width low  
ELDOI  
E low to data out invalid  
Notes: 1. For a loading capacitance of less than or equal to 50 picofarads, subtract 5 nanoseconds from the value given in the maxi-  
mum columns.  
2. If the asynchronous setup time (47) requirements are satisfied, the DTACK low-to-data setup time (31) required can be  
ignored. The data must only satisfy the date in clock-low setup time (27) for the following cycle.  
3. The falling edge of S6 triggers both the negation of the strobes (AS and X DS) and the falling edge of E. Either of these  
events can occur first, depending upon the loading on each signal specification 49 indicates the absolute maximum skew  
that will occur between the rising edge of the strobes and the falling edge of the E clock.  
Figure 2-17. TS68C000 to EF6800 Peripheral Timing Diagram – Best Case  
w
w
w
w
w
w
w
w
w
w
w
w
S5 S6 S7 S0  
S0 S1 S2 S3 S4  
CLK  
A1-A23  
AS  
45  
12  
41  
41  
49  
R/W  
E
18  
18  
20  
51  
50  
42  
44  
41  
42  
VPA  
45  
54  
40  
41  
43  
VMA  
DATA OUT  
27  
29  
23  
DATA IN  
Note:  
This timing diagram is included for those who wish to design their own circuit to generate VMA. It shows the worst case possibly  
attainable.  
46  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Figure 2-18. TS68C000 to EF6800 Peripheral Timing Diagram – Worse Case  
w w w w w w w w w w w w w w w w w w w w w w w w w w w w  
S5 S6S7S0  
S0 S1S2S3 S4  
CLK  
45  
A1-A23  
12  
AS  
18  
18  
20  
R/W  
E
41  
42  
41  
42  
49  
44  
45  
51  
50  
47  
VPA  
VMA  
40  
43  
54  
29  
23  
DATA OUT  
DATA IN  
27  
Note:  
This timing diagram is included for those who wish to design their own circuit to generate VMA. It shows the worst case possibly  
attainable.  
2.8  
Preparation For Delivery  
2.8.1  
2.8.2  
Packaging  
Microcircuit are prepared for delivery in accordance with MIL-PRF-38535.  
Certificate of Compliance  
Atmel offers a certificate of compliance with each shipment of parts, affirming the products are in  
compliance with MIL-STD-883 and guarantying the parameters not tested at extreme tempera-  
tures for the entire temperature range.  
2.9  
Handling  
MOS devices must be handled with certain precautions to avoid damage due to accumulation of  
static charge. Input protection devices have been designed in the chip to minimize the effect of  
this static buildup. However, the following handling practices are recommended:  
a) Device should be handled on benches with conductive and grounded surface.  
b) Ground test equipment, tools and operator.  
c) Do not handle devices by the leads.  
d) Store devices in conductive foam or carriers.  
e) Avoid use of plastic, rubber, or silk in MOS areas.  
f) Maintain relative humidity above 50%, if practical.  
47  
2170A–HIREL–09/05  
2.10 Package Mechanical Data  
Figure 2-19. 68-lead – Pin Grid Array  
TOP VIEW  
BOTTOM VIEW  
.180 ± 010  
4.57 ± 0.25  
.050 ± 010  
.900 Typ  
Index corner  
1.27 ± 0.254  
22.86 Typ  
1
10  
9
8
7
6
5
4
3
2
A
B
C
D
E
F
G
H
J
K
.065 ± 005  
1.65 ± 0.13  
1.060 ± .010  
26.92 ± 0.25  
.080 ± 008  
2.03 ± 0.20  
.097 ± 008  
2.46 ± 0.20  
Figure 2-20. 64-lead – Ceramic Side Brazed Package  
.018 ± 002  
0.46 ± 0.05  
.100 ± .002  
2.54 ± 0.05  
.010 ± 002  
0.25 ± 0.05  
.900 ± .010  
22.86 ± 0.25  
33  
64  
32  
1
Pin N° 1 Index  
3.200 ± 030  
81.28 ± 0.76  
48  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
Figure 2-21. 68-lead – Leadless Ceramic Chip Carrier  
BOTTOM VIEW  
TOP VIEW  
1
2
.085 ± .009  
2.16 ± 0.23  
.800 ± 008  
20.32 ± 0.2  
.050 ± 005  
1.27 ± 0.13  
+.012  
.950  
-.010  
+0.30  
24.13  
-0.25  
Figure 2-22. 68-lead – Ceramic Quad Flat Pack  
1.133-1.147  
28.78-29.13  
.940-.960  
Pin N° 1 index  
23.88-24.38  
68  
1
52  
51  
0°-8°  
CQFP 68  
.018-.035  
.046-0.88  
35  
17  
18  
34  
Z
.135  
3.43  
.021-.025  
.008 M  
X Y  
.004  
0.53-0.64  
49  
2170A–HIREL–09/05  
2.11 Ordering Information  
2.11.1  
MIL-STD-883  
TS68C000  
M
C1 B/C  
8
A
Device Type  
Revision level  
Operating frequency (MHz)  
MIL-STD-883 Class B  
M = -55/+125°C  
Package:  
C: Ceramic DIL  
R: PGA  
E: LCCC  
C1: Ceramic DIL, tin dipped leads  
E1: LCCC, tin dipped leads  
F: CQFP  
2.11.2  
DESC  
TS68C000DESC 02  
T
A
A
Revision level  
Device Type  
Part number for DESC Drawing 82021  
Lead finish per A = tin dipped  
MIL-M-38510 C = gold plated  
Device Type:  
01: 8 MHz  
02: 10 MHz  
03: 12.5 MHz  
Case outlines:  
U: PGA 68  
Y: CDIL 64  
X: LCCC 68 (on request)  
Z: CQFP 68 (on request)  
Note: Temperature range is -55°C ≤ T ≤ +125C for DESC product  
C
50  
TC68C000  
2170A–HIREL–09/05  
TS68C000  
2.11.3  
Standard Product  
TS68C000  
M
C
8
A
Revision level  
Device Type  
M = -55°C/+125°C  
V = -40°C/+85°C  
Operating frequency (MHz)  
Package:  
C: Ceramic DIL  
R: PGA  
E: LCCC  
F: CQFP (on request)  
Note:  
1. For availability of the different versions, contact your Atmel sale office.  
51  
2170A–HIREL–09/05  
Atmel Corporation  
Atmel Operations  
2325 Orchard Parkway  
San Jose, CA 95131, USA  
Tel: 1(408) 441-0311  
Fax: 1(408) 487-2600  
Memory  
RF/Automotive  
Theresienstrasse 2  
Postfach 3535  
74025 Heilbronn, Germany  
Tel: (49) 71-31-67-0  
Fax: (49) 71-31-67-2340  
2325 Orchard Parkway  
San Jose, CA 95131, USA  
Tel: 1(408) 441-0311  
Fax: 1(408) 436-4314  
Regional Headquarters  
Microcontrollers  
2325 Orchard Parkway  
San Jose, CA 95131, USA  
Tel: 1(408) 441-0311  
Fax: 1(408) 436-4314  
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Colorado Springs, CO 80906, USA  
Tel: 1(719) 576-3300  
Europe  
Atmel Sarl  
Route des Arsenaux 41  
Case Postale 80  
CH-1705 Fribourg  
Switzerland  
Tel: (41) 26-426-5555  
Fax: (41) 26-426-5500  
Fax: 1(719) 540-1759  
Biometrics/Imaging/Hi-Rel MPU/  
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38521 Saint-Egreve Cedex, France  
Tel: (33) 4-76-58-30-00  
Fax: (33) 4-76-58-34-80  
Asia  
Room 1219  
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Tel: (852) 2721-9778  
Fax: (852) 2722-1369  
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Tel: (33) 4-42-53-60-00  
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Tel: 1(719) 576-3300  
Japan  
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Japan  
Tel: (81) 3-3523-3551  
Fax: (81) 3-3523-7581  
Fax: 1(719) 540-1759  
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Maxwell Building  
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Tel: (44) 1355-803-000  
Fax: (44) 1355-242-743  
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www.atmel.com/literature  
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2170A–HIREL–09/05  

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