TS80C32X2-MCE_技术文档

Features

80C52 Compatible

•

– 8051 Pin and Instruction Compatible

– Four 8-bit I/O Ports

– Three 16-bit Timer/Counters

– 256 Bytes Scratchpad RAM

High-speed Architecture

•

40 MHz at 5V, 30 MHz at 3V

X2 Speed Improvement Capability (6 Clocks/Machine Cycle)

– 30 MHz at 5V, 20 MHz at 3V (Equivalent to 60 MHz at 5V, 40 MHz at 3V)

Dual Data Pointer

•

8-bit

On-chip ROM/EPROM (8Kbytes)

Programmable Clock Out and Up/Down Timer/Counter 2

Asynchronous Port Reset

Microcontroller

8 Kbytes

ROM/OTP,

ROMless

Interrupt Structure with

– 6 Interrupt Sources

– 4 Level Priority Interrupt System

Full Duplex Enhanced UART

– Framing Error Detection

•

– Automatic Address Recognition

Low EMI (Inhibit ALE)

Power Control Modes

•

– Idle Mode

– Power-down Mode

– Power-off Flag

TS80C32X2

TS87C52X2

TS80C52X2

AT80C32X2

AT80C52X2

AT87C52X2

•

Once Mode (On-chip Emulation)

Power Supply: 4.5 - 5.5V, 2.7 - 5.5V

Temperature Ranges: Commercial (0 to 70^oC) and Industrial (-40 to 85^oC)

Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 (13.9 footprint)

Description

TS80C52X2 is high performance CMOS ROM, OTP, EPROM and ROMless versions

of the 80C51 CMOS single chip 8-bit microcontroller.

The TS80C52X2 retains all features of the 80C51 with extended ROM/EPROM

capacity (8 Kbytes), 256 bytes of internal RAM, a 6-source, 4-level interrupt system,

an on-chip oscilator and three timer/counters.

In addition, the TS80C52X2 has a dual data pointer, a more versatile serial channel

that facilitates multiprocessor communication (EUART) and an X2 speed improve-

ment mechanism.

The fully static design of the TS80C52X2 allows to reduce system power consumption

by bringing the clock frequency down to any value, even DC, without loss of data.

The TS80C52X2 has 2 software-selectable modes of reduced activity for further

reduction in power consumption. In the idle mode the CPU is frozen while the timers,

the serial port and the interrupt system are still operating. In the power-down mode the

RAM is saved and all other functions are inoperative.

Rev. 4184I–8051–02/08

Table 1. Memory Size

ROM (bytes)

EPROM (bytes)

TOTAL RAM (bytes)

TS80C32X2

TS80C52X2

TS87C52X2

0

8k

0

256

8k

Block Diagram

(3) (3)

(1) (1)

XTAL1

XTAL2

ROM

/EPROM

8Kx8

RAM

256x8

EUART

Timer2

ALE/PROG

PSEN

C51

CORE

IB-bus

CPU

EA/VPP

(2)

Timer 0

Timer 1

INT

Ctrl

Parallel I/O Ports & Ext. Bus

Port 0Port 1 Port 3

RD

Port 2

WR

(2) (2)

Notes: 1. Alternate function of Port 1

2. Alternate function of Port 3

2

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

SFR Mapping

The Special Function Registers (SFRs) of the TS80C52X2 fall into the following

categories:

•

C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1

I/O port registers: P0, P1, P2, P3

Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2,

RCAP2L, RCAP2H

•

Serial I/O port registers: SADDR, SADEN, SBUF, SCON

Power and clock control registers: PCON

Interrupt system registers: IE, IP, IPH

Others: AUXR, CKCON

3

4184I–8051–02/08

Table 2. All SFRs with their address and their reset value

Bit

Addressable

Non Bit Addressable

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

F8h

F0h

E8h

E0h

FFh

F7h

EFh

E7h

B

0000 0000

ACC

0000 0000

D8

h

DFh

D7h

CFh

C7h

BFh

B7h

AFh

A7h

9Fh

97h

8Fh

87h

D0

h

PSW

0000 0000

C8

h

T2CON

0000 0000

T2MOD

XXXX XX00

RCAP2L

0000 0000

RCAP2H

0000 0000

TL2

0000 0000

TH2

0000 0000

C0

h

IP

SADEN

B8h

B0h

A8h

A0h

98h

90h

88h

80h

XX00 0000

0000 0000

P3

IPH

XX00 0000

1111 1111

IE

SADDR

0X00 0000

0000 0000

P2

AUXR1

1111 1111

XXXX XXX0

SCON

SBUF

0000 0000

XXXX XXXX

P1

1111 1111

TCON

TMOD

TL0

TL1

TH0

TH1

CKCON

AUXR

XXXXXXX0

0000 0000

XXXX XXX0

P0

PCON

SP

0000 0111

DPL

0000 0000

DPH

0000 0000

1111 1111

00X1 0000

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

Reserved

4

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Pin Configuration

P1.0 / T2

40

1

2

VCC

39

38

P0.0 / A0

P0.1 / A1

P1.1 / T2EX

P1.2

3

4

P1.3

37 P0.2 / A2

P0.3 / A3

36

P1.4

P1.5

5

6

P0.4 / A4

35

6

5 4 3 2 1

44 43 42 41 40

P0.5 / A5

34

P1.6

7

8

P1.5

P1.6

39

38

7

8

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA/VPP

NIC*

P0.6 / A6

33

P1.7

RST

P0.7 / A7

32

9

P1.7

37

9

EA/VPP

ALE/PROG

PSEN

P3.0/RxD 10

P3.1/TxD

11

31

30

RST

10

11

12

13

36

35

34

33

PDIL/

P3.0/RxD

NIC*

12

P3.2/INT0

29

28

27

26

CDIL40

PLCC/CQPJ 44

P2.7 / A15

P2.6 / A14

P3.3/INT1 13

P3.4/T0 14

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

ALE/PROG

PSEN

14

15

16

17

32

31

30

29

P2.5 / A13

15

16

17

18

19

20

P3.5/T1

P3.6/WR

P2.7/A15

P2.6/A14

P2.5/A13

P2.4 / A12

P2.3 / A11

25

24

23

22

21

P3.7/RD

XTAL2

P2.2 / A10

P2.1 / A9

P2.0 / A8

18 19 20 21 22 23 24 25 26 27 28

XTAL1

VSS

44 43 42 41 40 39 38 37 36 35 34

P1.5

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA/VPP

NIC*

33

32

1

2

P1.6

P1.7

31

3

4

30

29

28

27

RST

P3.0/RxD

NIC*

5

PQFP44

VQFP44

6

7

8

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

ALE/PROG

PSEN

26

25

24

23

P2.7/A15

P2.6/A14

P2.5/A13

9

10

11

12 13 14 15 16 17 18 19 20 21 22

*NIC: No Internal Connection

5

4184I–8051–02/08

Mnemonic

Pin Number

VQFP

Type Name and Function

DIL LCC

1.4

V_SS

20

22

1

16

I

Ground: 0V reference

Optional Ground: Contact the Sales Office for ground

connection.

Vss1

39

38

Power Supply: This is the power supply voltage for normal,

idle and power-down operation

V_CC

40

44

I

39- 43-

32 36

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0

pins that have 1s written to them float and can be used as

high impedance inputs.Port 0 pins must be polarized to Vcc

or Vss in order to prevent any parasitic current consumption.

Port 0 is also the multiplexed low-order address and data bus

during access to external program and data memory. In this

application, it uses strong internal pull-up when emitting 1s.

Port 0 also inputs the code bytes during EPROM

P0.0-P0.7

37-30

I/O

programming. External pull-ups are required during program

verification during which P0 outputs the code bytes.

P1.0-P1.7

1-8 2-9

40-44

1-3

I/O Port 1: Port 1 is an 8-bit bidirectional I/O port with internal

pull-ups. Port 1 pins that have 1s written to them are pulled

high by the internal pull-ups and can be used as inputs. As

inputs, Port 1 pins that are externally pulled low will source

current because of the internal pull-ups. Port 1 also receives

the low-order address byte during memory programming and

verification.

Alternate functions for Port 1 include:

1

2

3

40

41

I/O T2 (P1.0): Timer/Counter 2 external count input/Clockout

T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction

I

Control

21- 24-

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal

pull-ups. Port 2 pins that have 1s written to them are pulled

P2.0-P2.7

18-25

I/O

28

31

high by the internal pull-ups and can be used as inputs. As

inputs, Port 2 pins that are externally pulled low will source

current because of the internal pull-ups. Port 2 emits the high-

order address byte during fetches from external program

memory and during accesses to external data memory that

use 16-bit addresses (MOVX atDPTR).In this application, it

uses strong internal pull-ups emitting 1s. During accesses to

external data memory that use 8-bit addresses (MOVX atRi),

port 2 emits the contents of the P2 SFR. Some Port 2 pins

receive the high order address bits during EPROM

programming and verification: P2.0 to P2.4

10-

17

11,

13-

19

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal

pull-ups. Port 3 pins that have 1s written to them are pulled

high by the internal pull-ups and can be used as inputs. As

inputs, Port 3 pins that are externally pulled low will source

current because of the internal pull-ups. Port 3 also serves

the special features of the 80C51 family, as listed below.

P3.0-P3.7

5,

7-13

I/O

10

11

12

11

13

14

5

7

8

I

O

I

RXD (P3.0): Serial input port

TXD (P3.1): Serial output port

INT0 (P3.2): External interrupt 0

6

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Mnemonic

Pin Number

VQFP

Type Name and Function

DIL LCC

1.4

13

14

15

16

17

9

15

16

17

18

19

10

9

I

INT1 (P3.3): External interrupt 1

10

11

12

13

4

T0 (P3.4): Timer 0 external input

T1 (P3.5): Timer 1 external input

I

O

I

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

Reset

Reset: A high on this pin for two machine cycles while the

oscillator is running, resets the device. An internal diffused

resistor to V_SSpermits a power-on reset using only an

external capacitor to V_CC.

ALE/PROG

30

33

27

O (I) Address Latch Enable/Program Pulse: Output pulse for

latching the low byte of the address during an access to

external memory. In normal operation, ALE is emitted at a

constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,

and can be used for external timing or clocking. Note that one

ALE pulse is skipped during each access to external data

memory. This pin is also the program pulse input (PROG)

during EPROM programming. ALE can be disabled by setting

SFR’s AUXR.0 bit. With this bit set, ALE will be inactive

during internal fetches.

PSEN

29

31

32

35

26

29

O

Program Store ENable: The read strobe to external program

memory. When executing code from the external program

memory, PSEN is activated twice each machine cycle, except

that two PSEN activations are skipped during each access to

external data memory. PSEN is not activated during fetches

from internal program memory.

EA/V_PP

I

External Access Enable/Programming Supply Voltage:

EA must be externally held low to enable the device to fetch

code from external program memory locations 0000H and

3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is held

high, the device executes from internal program memory

unless the program counter contains an address greater than

3FFFH (RB) or 7FFFH (RC) EA must be held low for

ROMless devices. This pin also receives the 12.75V

programming supply voltage (V_PP) during EPROM

programming. If security level 1 is programmed, EA will be

internally latched on Reset.

XTAL1

XTAL2

19

18

21

20

15

14

I

Crystal 1: Input to the inverting oscillator amplifier and input

to the internal clock generator circuits.

O

Crystal 2: Output from the inverting oscillator amplifier

7

4184I–8051–02/08

TS80C52X2

Enhanced Features

In comparison to the original 80C52, the TS80C52X2 implements some new features,

which are

:

•

The X2 option

The Dual Data Pointer

The 4 level interrupt priority system

The power-off flag

The ONCE mode

The ALE disabling

Some enhanced features are also located in the UART and the Timer 2

X2 Feature

The TS80C52X2 core needs only 6 clock periods per machine cycle. This feature called

”X2” provides the following advantages:

•

Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power

Save power consumption while keeping same CPU power (oscillator power saving)

Save power consumption by dividing dynamically operating frequency by 2 in

operating and idle modes

•

Increase CPU power by 2 while keeping same crystal frequency

In order to keep the original C51 compatibility, a divider by 2 is inserted between the

XTAL1 signal and the main clock input of the core (phase generator). This divider may

be disabled by software.

Description

The clock for the whole circuit and peripheral is first divided by two before being used by

the CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1

input. In X2 mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic

ratio between 40 to 60%. Figure 1. shows the clock generation block diagram. X2 bit is

validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD

mode. Figure 2 shows the mode switching waveforms.

Figure 1. Clock Generation Diagram

XTAL1:2

2

state machine: 6 clock cycles.

CPU control

XTAL1

0

1

F_XTAL

F_OSC

X2

CKCON reg

8

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Figure 2. Mode Switching Waveforms

XTAL1

XTAL1:2

X2 bit

CPU clock

STD Mode

X2 Mode

STD Mode

The X2 bit in the CKCON register (See Table 3.) allows to switch from 12 clock cycles

per instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated

(STD mode). Setting this bit activates the X2 feature (X2 mode).

Note:

In order to prevent any incorrect operation while operating in X2 mode, user must be

aware that all peripherals using clock frequency as time reference (UART, timers) will

have their time reference divided by two. For example a free running timer generating an

interrupt every 20 ms will then generate an interrupt every 10 ms. UART with 4800 baud

rate will have 9600 baud rate.

Table 3. CKCON Register

CKCON - Clock Control Register (8Fh)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

X2

Bit

Number

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

7

6

5

4

3

2

1

-

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

CPU and peripheral clock bit

0

X2

Clear to select 12 clock periods per machine cycle (STD mode, F_OSC=F_XTAL

Set to select 6 clock periods per machine cycle (X2 mode, F_OSC=F_XTAL).

/2).

Reset Value = XXXX XXX0b

Not bit addressable

For further details on the X2 feature, please refer to ANM072 available on the web

(http://www.atmel.com)

9

4184I–8051–02/08

Dual Data Pointer

Register (Ddptr)

The additional data pointer can be used to speed up code execution and reduce code

size in a number of ways.

The dual DPTR structure is a way by which the chip will specify the address of an exter-

nal data memory location. There are two 16-bit DPTR registers that address the external

memory, and a single bit called

DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them

(Refer to Figure 3).

Figure 3. Use of Dual Pointer

External Data Memory

7

0

DPS

DPTR1

DPTR0

AUXR1(A2H)

DPH(83H) DPL(82H)

Table 4. AUXR1: Auxiliary Register 1

7

-

6

-

5

-

4

-

3

2

0

1

-

0

GF3

DPS

Bit

Number

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

7

6

5

-

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

4

3

2

-

GF3

0

This bit is a general purpose user flag

Reserved

Always stuck at 0

Reserved

The value read from this bit is indeterminate. Do not set this bit.

1

0

-

Data Pointer Selection

Clear to select DPTR0.

Set to select DPTR1.

DPS

Reset Value = XXXX XXX0

Not bit addressable

10

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Application

Software can take advantage of the additional data pointers to both increase speed and

reduce code size, for example, block operations (copy, compare, search ...) are well

served by using one data pointer as a ’source’ pointer and the other one as a "destina-

tion" pointer.

ASSEMBLY LANGUAGE

; Block move using dual data pointers

; Destroys DPTR0, DPTR1, A and PSW

; note: DPS exits opposite of entry state

; unless an extra INC AUXR1 is added

;

00A2 AUXR1 EQU 0A2H

;

0000 909000MOV DPTR,#SOURCE ; address of SOURCE

0003 05A2 INC AUXR1 ; switch data pointers

0005 90A000 MOV DPTR,#DEST ; address of DEST

0008 LOOP:

0008 05A2 INC AUXR1 ; switch data pointers

000A E0 MOVX A,atDPTR ; get a byte from SOURCE

000B A3 INC DPTR ; increment SOURCE address

000C 05A2 INC AUXR1 ; switch data pointers

000E F0 MOVX atDPTR,A ; write the byte to DEST

000F A3 INC DPTR ; increment DEST address

0010 70F6JNZ LOOP ; check for 0 terminator

0012 05A2 INC AUXR1 ; (optional) restore DPS

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1

SFR. However, note that the INC instruction does not directly force the DPS bit to a par-

ticular state, but simply toggles it. In simple routines, such as the block move example,

only the fact that DPS is toggled in the proper sequence matters, not its actual value. In

other words, the block move routine works the same whether DPS is '0' or '1' on entry.

Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in

the opposite state.

11

4184I–8051–02/08

Timer 2

The timer 2 in the TS80C52X2 is compatible with the timer 2 in the 80C52.

It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2

and TL2, connected in cascade. It is controlled by T2CON register (See Table 5) and

T2MOD register (See Table 6). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2

selects F_OSC/12 (timer operation) or external pin T2 (counter operation) as the timer

clock input. Setting TR2 allows TL2 to be incremented by the selected input.

Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These

modes are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as

described in the Atmel 8-bit Microcontroller Hardware description.

Refer to the Atmel 8-bit Microcontroller Hardware description for the description of Cap-

ture and Baud Rate Generator Modes.

In TS80C52X2 Timer 2 includes the following enhancements:

•

Auto-reload mode with up or down counter

Programmable clock-output

Auto-reload Mode

The Auto-reload mode configures timer 2 as a 16-bit timer or event counter with auto-

matic reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the

Atmel 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an

Up/down timer/counter as shown in Figure 4. In this mode the T2EX pin controls the

direction of count.

When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the

TF2 flag and generates an interrupt request. The overflow also causes the 16-bit value

in RCAP2H and RCAP2L registers to be loaded into the timer registers TH2 and TL2.

When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the

timer registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers.

The underflow sets TF2 flag and reloads FFFFh into the timer registers.

The EXF2 bit toggles when timer 2 overflows or underflows according to the the direc-

tion of the count. EXF2 does not generate any interrupt. This bit can be used to provide

17-bit resolution.

12

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Figure 4. Auto-reload Mode Up/Down Counter (DCEN = 1)

(:6 in X2 mode)

:12

0

1

XTAL1

F_OSC

F_XTAL

T2

TR2

C/T2

T2CONreg

T2EX:

(DOWN COUNTING RELOAD

if DCEN=1, 1=UP

FFh

(8-bit)

if DCEN=1, 0=DOWN

(8-bit)

if DCEN = 0, up counting

T2CONreg

EXF2

TOGGL

TL2

(8-bit)

TH2

(8-bit)

TIMER 2

INTERRUPT

TF2

T2CONreg

RCAP2L

(8-bit)

RCAP2H

(8-bit)

(UP COUNTING RELOAD VALUE)

Programmable Clock-output

In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock gen-

erator (See Figure 5) . The input clock increments TL2 at frequency F_OSC/2. The timer

repeatedly counts to overflow from a loaded value. At overflow, the contents of RCAP2H

and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer 2 overflows do

not generate interrupts. The formula gives the clock-out frequency as a function of the

system oscillator frequency and the value in the RCAP2H and RCAP2L registers :

F

osc

----------------------------------------------------------------------------------------

Clock – OutFrequency =

4 × (65536 – RCAP2H ⁄ RCAP2L)

For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz

(F_OSC/2¹⁶⁾to 4 MHz (F_OSC/4). The generated clock signal is brought out to T2 pin (P1.0).

Timer 2 is programmed for the clock-out mode as follows:

•

Set T2OE bit in T2MOD register.

Clear C/T2 bit in T2CON register.

Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L

registers.

•

Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the

reload value or a different one depending on the application.

To start the timer, set TR2 run control bit in T2CON register.

It is possible to use timer 2 as a baud rate generator and a clock generator simulta-

neously. For this configuration, the baud rates and clock frequencies are not

independent since both functions use the values in the RCAP2H and RCAP2L registers.

13

4184I–8051–02/08

Figure 5. Clock-Out Mode C/T2 = 0

:2

XTAL1

(:1 in X2 mode)

TR2

T2CON reg

TH2

(8-bit)

TL2

(8-bit)

OVERFLOW

RCAP2H

(8-bit)

RCAP2L

(8-bit)

Toggle

T2

Q

D

T2OE

T2MOD reg

TIMER 2

INTERRUPT

T2EX

EXF2

T2CON reg

EXEN2

T2CON reg

14

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Table 5. T2CON Register

T2CON - Timer 2 Control Register (C8h)

7

6

5

4

3

2

1

0

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

Bit

Number Mnemonic Description

Timer 2 overflow Flag

Must be cleared by software.

7

TF2

Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if

EXEN2=1.

6

EXF2

When set, causes the CPU to vector to timer 2 interrupt routine when timer 2

interrupt is enabled.

Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter

mode (DCEN = 1)

Receive Clock bit

5

4

RCLK

TCLK

Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.

Transmit Clock bit

Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable bit

Clear to ignore events on T2EX pin for timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is

detected, if timer 2 is not used to clock the serial port.

3

2

1

EXEN2

TR2

Timer 2 Run control bit

Clear to turn off timer 2.

Set to turn on timer 2.

Timer/Counter 2 select bit

Clear for timer operation (input from internal clock system: F_OSC).

Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0

for clock out mode.

C/T2#

Timer 2 Capture/Reload bit

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to Auto-reload on

timer 2 overflow.

Clear to Auto-reload on timer 2 overflows or negative transitions on T2EX pin if

EXEN2=1.

0

CP/RL2#

Set to capture on negative transitions on T2EX pin if EXEN2=1.

Reset Value = 0000 0000b

Bit addressable

15

4184I–8051–02/08

Table 6. T2MOD Register

T2MOD - Timer 2 Mode Control Register (C9h)

7

6

5

4

3

-

2

-

1

0

-

T2OE

DCEN

Bit

Number

Mnemonic Description

Reserved

7

6

5

4

3

2

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 Output Enable bit

Clear to program P1.0/T2 as clock input or I/O port.

Set to program P1.0/T2 as clock output.

1

0

T2OE

DCEN

Down Counter Enable bit

Clear to disable timer 2 as up/down counter.

Set to enable timer 2 as up/down counter.

Reset Value = XXXX XX00b

Not bit addressable

16

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

TS80C52X2 Serial I/O

Port

The serial I/O port in the TS80C52X2 is compatible with the serial I/O port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as

an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex

modes (Modes 1, 2 and 3). Asynchronous transmission and reception can occur simul-

taneously and at different baud rates

Serial I/O port includes the following enhancements:

•

Framing error detection

Automatic address recognition

Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2

and 3). To enable the framing bit error detection feature, set SMOD0 bit in PCON regis-

ter (See Figure 6).

Figure 6. Framing Error Block Diagram

SM0/FE SM1

SM2

REN

TB8

RB8

TI

RI

SCON (98h)

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)

SM0 to UART mode control (SMOD = 0)TS80C52X2

PCON (87h)

SMOD1SMOD0

-

POF GF1

GF0

PD

IDL

To UART framing error control

When this feature is enabled, the receiver checks each incoming data frame for a valid

stop bit. An invalid stop bit may result from noise on the serial lines or from simultaneous

transmission by two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in

SCON register (See Table 9.) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set,

only software or a reset can clear FE bit. Subsequently received frames with valid stop

bits cannot clear FE bit. When FE feature is enabled, RI rises on stop bit instead of the

last data bit (See Figure 7. and Figure 8.).

Figure 7. UART Timings in Mode 1

RXD

D0

D1

D2

D3

D4

D5

D6

D7

Start

bit

Data byte

Stop

bit

RI

SMOD0=X

FE

SMOD0=1

17

4184I–8051–02/08

Figure 8. UART Timings in Modes 2 and 3

RXD

D0

D1

D2

D3

D4

D5

D6

D7

D8

Start

bit

Data byte

Ninth Stop

bit

RI

SMOD0=0

RI

SMOD0=1

FE

SMOD0=1

Automatic Address

Recognition

The automatic address recognition feature is enabled when the multiprocessor commu-

nication feature is enabled (SM2 bit in SCON register is set).

Implemented in hardware, automatic address recognition enhances the multiprocessor

communication feature by allowing the serial port to examine the address of each

incoming command frame. Only when the serial port recognizes its own address, the

receiver sets RI bit in SCON register to generate an interrupt. This ensures that the CPU

is not interrupted by command frames addressed to other devices.

If desired, you may enable the automatic address recognition feature in mode 1. In this

configuration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the

received command frame address matches the device’s address and is terminated by a

valid stop bit.

To support automatic address recognition, a device is identified by a given address and

a broadcast address.

Note:

The multiprocessor communication and automatic address recognition features cannot

be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).

Given Address

Each device has an individual address that is specified in SADDR register; the SADEN

register is a mask byte that contains don’t-care bits (defined by zeros) to form the

device’s given address. The don’t-care bits provide the flexibility to address one or more

slaves at a time. The following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask byte must be 1111

1111b.

For example:

SADDR0101 0110b

SADEN1111 1100b

Given0101 01XXb

The following is an example of how to use given addresses to address different slaves:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Given1111 0X0Xb

Slave B:SADDR1111 0011b

SADEN1111 1001b

Given1111 0XX1b

Slave C:SADDR1111 0010b

SADEN1111 1101b

Given1111 00X1b

The SADEN byte is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To com-

municate with slave A only, the master must send an address where bit 0 is clear (e.g.

18

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

1111 0000b).

For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with

slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both

set (e.g. 1111 0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0

set, bit 1 clear, and bit 2 clear (e.g. 1111 0001b).

Broadcast Address

A broadcast address is formed from the logical OR of the SADDR and SADEN registers

with zeros defined as don’t-care bits, e.g.:

SADDR 0101 0110b

SADEN 1111 1100b

Broadcast =SADDR OR SADEN1111 111Xb

The use of don’t-care bits provides flexibility in defining the broadcast address, however

in most applications, a broadcast address is FFh. The following is an example of using

broadcast addresses:

Slave A:SADDR1111 0001b

SADEN1111 1010b

Broadcast1111 1X11b,

Slave B:SADDR1111 0011b

SADEN1111 1001b

Broadcast1111 1X11B,

Slave C:SADDR=1111 0010b

SADEN1111 1101b

Broadcast1111 1111b

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with

all of the slaves, the master must send an address FFh. To communicate with slaves A

and B, but not slave C, the master can send and address FBh.

Reset Addresses

On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and

broadcast addresses are XXXX XXXXb(all don’t-care bits). This ensures that the serial

port will reply to any address, and so, that it is backwards compatible with the 80C51

microcontrollers that do not support automatic address recognition.

Table 7. SADEN Register

SADEN - Slave Address Mask Register (B9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Not bit addressable

Table 8. SADDR Register

SADDR - Slave Address Register (A9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Not bit addressable

19

4184I–8051–02/08

Table 9. SCON Register

SCON - Serial Control Register (98h)

7

6

5

4

3

2

1

0

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

Bit

Number Mnemonic Description

Framing Error bit (SMOD0=1)

Clear to reset the error state, not cleared by a valid stop bit.

Set by hardware when an invalid stop bit is detected.

7

FE

SMOD0 must be set to enable access to the FE bit

Serial port Mode bit 0

Refer to SM1 for serial port mode selection.

SM0

SMOD0 must be cleared to enable access to the SM0 bit

Serial port Mode bit 1

SM0 SM1

Mode Description

Baud Rate

0

1

0

1

0

1

0

1

2

3

Shift Register F_XTAL/12 (/6 in X2 mode)

6

5

SM1

SM2

8-bit UART

9-bit UART

Variable

_XTAL/64 or F_XTAL/32 (/32, /16 in X2 mode)

Variable

F

Serial port Mode 2 bit / Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature.

Set to enable multiprocessor communication feature in mode 2 and 3, and

eventually mode 1. This bit should be cleared in mode 0.

Reception Enable bit

4

3

REN

TB8

Clear to disable serial reception.

Set to enable serial reception.

Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

Receiver Bit 8 / Ninth bit received in modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

2

1

0

RB8

TI

In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.

Transmit Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the

stop bit in the other modes.

Receive Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, see Figure 7. and Figure

8. in the other modes.

RI

Reset Value = 0000 0000b

Bit addressable

20

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Table 10. PCON Register

PCON - Power Control Register (87h)

7

6

5

4

3

2

1

0

SMOD1

SMOD0

-

POF

GF1

GF0

PD

IDL

Bit

Number

Mnemonic Description

Serial port Mode bit 1

7

6

5

SMOD1

SMOD0

-

Set to select double baud rate in mode 1, 2 or 3.

Serial port Mode bit 0

Clear to select SM0 bit in SCON register.

Set to to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Power-off Flag

Clear to recognize next reset type.

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set

by software.

4

POF

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

3

2

1

0

GF1

GF0

PD

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

Power-down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle mode bit

Clear by hardware when interrupt or reset occurs.

Set to enter idle mode.

IDL

Reset Value = 00X1 0000b

Not bit addressable

Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset

doesn’t affect the value of this bit.

21

4184I–8051–02/08

Interrupt System

The TS80C52X2 has a total of 6 interrupt vectors: two external interrupts (INT0 and

INT1), three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. These inter-

rupts are shown in Figure 9.

Figure 9. Interrupt Control System

High priority

IPH, IP

interrupt

3

INT0

IE0

0

3

0

3

0

3

0

3

0

TF0

INT1

TF1

Interrupt

polling

IE1

sequence, decreasing from

high to low priority

RI

TI

3

0

TF2

EXF2

Low priority

interrupt

Individual Enable

Global Disable

Each of the interrupt sources can be individually enabled or disabled by setting or clear-

ing a bit in the Interrupt Enable register (See Table 12.). This register also contains a

global disable bit, which must be cleared to disable all interrupts at once.

Each interrupt source can also be individually programmed to one out of four priority lev-

els by setting or clearing a bit in the Interrupt Priority register (See Table 13.) and in the

Interrupt Priority High register (See Table 14.). shows the bit values and priority levels

associated with each combination.

Table 11. Priority Level Bit Values

IPH.x

IP.x

0

Interrupt Level Priority

0

1

0 (Lowest)

1

0

2

1

3 (Highest)

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another

low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt

source.

If two interrupt requests of different priority levels are received simultaneously, the

request of higher priority level is serviced. If interrupt requests of the same priority level

22

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

are received simultaneously, an internal polling sequence determines which request is

serviced. Thus within each priority level there is a second priority structure determined

by the polling sequence.

Table 12. IE Register

IE - Interrupt Enable Register (A8h)

7

6

-

5

4

3

2

1

0

EA

ET2

ES

ET1

EX1

ET0

EX0

Bit

Number Mnemonic Description

Enable All interrupt bit

Clear to disable all interrupts.

Set to enable all interrupts.

7

EA

If EA=1, each interrupt source is individually enabled or disabled by setting or

clearing its own interrupt enable bit.

Reserved

6

5

-

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 overflow interrupt Enable bit

Clear to disable timer 2 overflow interrupt.

Set to enable timer 2 overflow interrupt.

ET2

Serial port Enable bit

4

3

2

1

0

ES

Clear to disable serial port interrupt.

Set to enable serial port interrupt.

Timer 1 overflow interrupt Enable bit

Clear to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

ET1

EX1

ET0

EX0

External interrupt 1 Enable bit

Clear to disable external interrupt 1.

Set to enable external interrupt 1.

Timer 0 overflow interrupt Enable bit

Clear to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

External interrupt 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

Reset Value = 0X00 0000b

Bit addressable

23

4184I–8051–02/08

Table 13. IP Register

IP - Interrupt Priority Register (B8h)

7

-

6

-

5

4

3

2

1

0

PT2

PS

PT1

PX1

PT0

PX0

Bit

Number

Mnemonic

Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 overflow interrupt Priority bit

Refer to PT2H for priority level.

PT2

PS

Serial port Priority bit

Refer to PSH for priority level.

Timer 1 overflow interrupt Priority bit

PT1

PX1

PT0

PX0

Refer to PT1H for priority level.

External interrupt 1 Priority bit

Refer to PX1H for priority level.

Timer 0 overflow interrupt Priority bit

Refer to PT0H for priority level.

External interrupt 0 Priority bit

Refer to PX0H for priority level.

Reset Value = XX00 0000b

Bit addressable

24

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Table 14. IPH Register

IPH - Interrupt Priority High Register (B7h)

7

-

6

-

5

4

3

2

1

0

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

Bit

Number Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

7

6

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 overflow interrupt Priority High bit

PT2H PT2 Priority Level

0

1

0

1

0

1

Lowest

5

4

3

2

1

0

PT2H

PSH

Highest

Serial port Priority High bit

PSH PS

Priority Level

Lowest

0

1

0

1

0

1

Highest

Timer 1 overflow interrupt Priority High bit

PT1H PT1 Priority Level

0

1

0

1

0

1

Lowest

PT1H

PX1H

PT0H

PX0H

Highest

External interrupt 1 Priority High bit

PX1H PX1 Priority Level

0

1

0

1

0

1

Lowest

Highest

Timer 0 overflow interrupt Priority High bit

PT0H PT0 Priority Level

0

1

0

1

0

1

Lowest

Highest

External interrupt 0 Priority High bit

PX0H PX0 Priority Level

0

1

0

1

0

1

Lowest

Highest

Reset Value = XX00 0000b

Not bit addressable

25

4184I–8051–02/08

Idle mode

An instruction that sets PCON.0 causes that to be the last instruction executed before

going into the Idle mode. In the Idle mode, the internal clock signal is gated off to the

CPU, but not to the interrupt, Timer, and Serial Port functions. The CPU status is pre-

served in its entirely : the Stack Pointer, Program Counter, Program Status Word,

Accumulator and all other registers maintain their data during Idle. The port pins hold

the logical states they had at the time Idle was activated. ALE and PSEN hold at logic

high levels.

There are two ways to terminate the Idle. Activation of any enabled interrupt will cause

PCON.0 to be cleared by hardware, terminating the Idle mode. The interrupt will be ser-

viced, and following RETI the next instruction to be executed will be the one following

the instruction that put the device into idle.

The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured dur-

ing normal operation or during an Idle. For example, an instruction that activates Idle

can also set one or both flag bits. When Idle is terminated by an interrupt, the interrupt

service routine can examine the flag bits.

The other way of terminating the Idle mode is with a hardware reset. Since the clock

oscillator is still running, the hardware reset needs to be held active for only two

machine cycles (24 oscillator periods) to complete the reset.

Power-down Mode

To save maximum power, a power-down mode can be invoked by software (Refer to

Table 10., PCON register).

In power-down mode, the oscillator is stopped and the instruction that invoked power-

down mode is the last instruction executed. The internal RAM and SFRs retain their

value until the power-down mode is terminated. V_CCcan be lowered to save further

power. Either a hardware reset or an external interrupt can cause an exit from power-

down. To properly terminate power-down, the reset or external interrupt should not be

executed before V_CCis restored to its normal operating level and must be held active

long enough for the oscillator to restart and stabilize.

Only external interrupts INT0 and INT1 are useful to exit from power-down. For that,

interrupt must be enabled and configured as level or edge sensitive interrupt input.

Holding the pin low restarts the oscillator but bringing the pin high completes the exit as

detailed in Figure 10. When both interrupts are enabled, the oscillator restarts as soon

as one of the two inputs is held low and power down exit will be completed when the first

input will be released. In this case the higher priority interrupt service routine is exe-

cuted.

Once the interrupt is serviced, the next instruction to be executed after RETI will be the

one following the instruction that put TS80C52X2 into power-down mode.

Figure 10. Power-down Exit Waveform

INT0

INT1

XTAL1

Active phase

Power-down phase Oscillator restart phase

Active phase

26

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Exit from power-down by reset redefines all the SFRs, exit from power-down by external

interrupt does no affect the SFRs.

Exit from power-down by either reset or external interrupt does not affect the internal

RAM content.

Note:

If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence

is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and

idle mode is not entered.

Table 15. The State of Ports During Idle and Power-down Modes

Program

Mode

Idle

Memory

Internal

External

Internal

ALE

PSEN

PORT0

PORT1

PORT2

Port Data

Address

Port Data

PORT3

Port

1

0

1

0

Port Data

Data⁽¹⁾

Idle

Floating

Power

Down

Port

Data⁽¹⁾

Power

Down

External

0

Floating

Port Data

Note:

1. Port 0 can force a "zero" level. A "one" will leave port floating.

27

4184I–8051–02/08

ONCE^TMMode (ON Chip The ONCE mode facilitates testing and debugging of systems using TS80C52X2 with-

out removing the circuit from the board. The ONCE mode is invoked by driving certain

pins of the TS80C52X2; the following sequence must be exercised:

Emulation)

•

Pull ALE low while the device is in reset (RST high) and PSEN is high.

Hold ALE low as RST is deactivated.

While the TS80C52X2 is in ONCE mode, an emulator or test CPU can be used to drive

the circuit Table 26. shows the status of the port pins during ONCE mode.

Normal operation is restored when normal reset is applied.

Table 16. External Pin Status during ONCE Mode

ALE

PSEN

Port 0

Port 1

Port 2

Port 3

XTAL1/2

Weak pull-

up

Weak pull-

up

Weak pull-

up

Weak pull-

up

Weak pull-

up

Float

Active

28

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Power-off Flag

The power-off flag allows the user to distinguish between a “cold start” reset and a

“warm start” reset.

A cold start reset is the one induced by V_CCswitch-on. A warm start reset occurs while

V_CCis still applied to the device and could be generated for example by an exit from

power-down.

The power-off flag (POF) is located in PCON register (See Table 17.). POF is set by

hardware when V_CCrises from 0 to its nominal voltage. The POF can be set or cleared

by software allowing the user to determine the type of reset.

The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value,

reading POF bit will return indeterminate value.

Table 17. PCON Register

PCON - Power Control Register (87h)

7

6

5

4

3

2

1

0

SMOD1

SMOD0

-

POF

GF1

GF0

PD

IDL

Bit

Number

Mnemonic Description

Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

7

6

5

SMOD1

SMOD0

-

Serial port Mode bit 0

Clear to select SM0 bit in SCON register.

Set to to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Power-off Flag

Clear to recognize next reset type.

Set by hardware when V_CCrises from 0 to its nominal voltage. Can also be

set by software.

4

POF

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

3

2

1

0

GF1

GF0

PD

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

Power-down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle mode bit

IDL

Clear by hardware when interrupt or reset occurs.

Set to enter idle mode.

Reset Value = 00X1 0000b

Not bit addressable

29

4184I–8051–02/08

Reduced EMI Mode

The ALE signal is used to demultiplex address and data buses on port 0 when used with

external program or data memory. Nevertheless, during internal code execution, ALE

signal is still generated. In order to reduce EMI, ALE signal can be disabled by setting

AO bit.

The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no

longer output but remains active during MOVX and MOVC instructions and external

fetches. During ALE disabling, ALE pin is weakly pulled high.

Table 18. AUXR Register

AUXR - Auxiliary Register (8Eh)

7

6

5

4

-

3

-

2

-

1

-

0

-

AO

Bit

Number

Mnemonic Description

Reserved

The value read from this bit is indeterminate. Do not set this bit.

7

6

5

4

3

2

1

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

-

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

ALE Output bit

Clear to restore ALE operation during internal fetches.

Set to disable ALE operation during internal fetches.

0

AO

Reset Value = XXXX XXX0b

Not bit addressable

30

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

TS80C52X2

ROM Structure

The TS80C52X2 ROM memory is divided in three different arrays:

•

the code array:8 Kbytes.

the encryption array:64 bytes.

the signature array:4 bytes.

ROM Lock System

The program Lock system, when programmed, protects the on-chip program against

software piracy.

Encryption Array

Within the ROM array are 64 bytes of encryption array that are initially unprogrammed

(all FF’s). Every time a byte is addressed during program verify, 6 address lines are

used to select a byte of the encryption array. This byte is then exclusive-NOR’ed

(XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with the

encryption array in the unprogrammed state, will return the code in its original, unmodi-

fied form.

When using the encryption array, one important factor needs to be considered. If a byte

has the value FFh, verifying the byte will produce the encryption byte value. If a large

block (>64 bytes) of code is left unprogrammed, a verification routine will display the

content of the encryption array. For this reason all the unused code bytes should be pro-

grammed with random values. This will ensure program protection.

Program Lock Bits

The lock bits when programmed according to Table 19. will provide different level of pro-

tection for the on-chip code and data.

Table 19. Program Lock bits

Program Lock Bits

Security

level

LB1

LB2

LB3

Protection Description

No program lock features enabled. Code verify will still be

encrypted by the encryption array if programmed. MOVC instruction

executed from external program memory returns non encrypted

data.

1

U

MOVC instruction executed from external program memory are

disabled from fetching code bytes from internal memory, EA is

sampled and latched on reset.

2

P

U

U: unprogrammed

P: programmed

Signature bytes

Verify Algorithm

The TS80C52X2 contains 4 factory programmed signatures bytes. To read these bytes,

perform the process described in section 9.

Refer to Section “Verify Algorithm”.

31

4184I–8051–02/08

EPROM Structure

The TS87C52X2 is divided in two different arrays:

•

the code array: 8 Kbytes

the encryption array: 64 bytes

In addition a third non programmable array is implemented:

the signature array: 4 bytes

•

EPROM Lock System

The program Lock system, when programmed, protects the on-chip program against

software piracy.

Encryption Array

Within the EPROM array are 64 bytes of encryption array that are initially unpro-

grammed (all FF’s). Every time a byte is addressed during program verify, 6 address

lines are used to select a byte of the encryption array. This byte is then exclusive-

NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm,

with the encryption array in the unprogrammed state, will return the code in its original,

unmodified form.

When using the encryption array, one important factor needs to be considered. If a byte

has the value FFh, verifying the byte will produce the encryption byte value. If a large

block (>64 bytes) of code is left unprogrammed, a verification routine will display the

content of the encryption array. For this reason all the unused code bytes should be pro-

grammed with random values. This will ensure program protection.

Program Lock Bits

The three lock bits, when programmed according to Table 1., will provide different level

of protection for the on-chip code and data.

Program Lock Bits

Security

level

LB1

LB2

LB3

Protection Description

No program lock features enabled. Code verify will still be

encrypted by the encryption array if programmed. MOVC

instruction executed from external program memory returns non

encrypted data.

1

U

MOVC instruction executed from external program memory are

disabled from fetching code bytes from internal memory, EA is

sampled and latched on reset, and further programming of the

EPROM is disabled.

2

P

U

3

4

U

P

U

P

Same as 2, also verify is disabled.

Same as 3, also external execution is disabled.

U: unprogrammed

P: programmed

WARNING: Security level 2 and 3 should only be programmed after EPROM and Core

verification.

Signature Bytes

The TS80/87C52X2 contains 4 factory programmed signatures bytes. To read these

bytes, perform the process described in section 9.

EPROM Programming

Set-up modes

In order to program and verify the EPROM or to read the signature bytes, the

TS87C52X2 is placed in specific set-up modes (See Figure 11.).

32

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Control and program signals must be held at the levels indicated in Table 35.

Definition of terms

Address Lines: P1.0-P1.7, P2.0-P2.4 respectively for A0-A12

Data Lines: P0.0-P0.7 for D0-D7

Control Signals: RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7.

Program Signals: ALE/PROG, EA/VPP.

Table 20. EPROM Set-up Modes

ALE/

EA/

Mode

RST

PSEN PROG

VPP

P2.6

P2.7

P3.3

P3.6

P3.7

12.75V

1

Program Code data

1

0

1

Verify Code data

1

0

1

0

1

0

1

0

1

0

1

0

1

0

1

0

Program Encryption

Array Address 0-3Fh

12.75V

1

Read Signature Bytes

Program Lock bit 1

Program Lock bit 2

Program Lock bit 3

12.75V

1

0

Figure 11. Set-Up Modes Configuration

+5V

EA/VPP

VCC

PROGRAM SIGNALS*

ALE/PROG

P0.0-P0.7

D0-D7

RST

PSEN

P2.6

P2.7

P3.3

P3.6

P3.7

P1.0-P1.7

P2.0-P2.4

A0-A7

CONTROL SIGNALS*

A8-A12

4 to 6 MHz

XTAL1

VSS

GND

* See Table 31. for proper value on these inputs

33

4184I–8051–02/08

Programming Algorithm

The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and

decreases the number of pulses applied during byte programming from 25 to 1.

To program the TS87C52X2 the following sequence must be exercised:

•

Step 1: Activate the combination of control signals.

Step 2: Input the valid address on the address lines.

Step 3: Input the appropriate data on the data lines.

Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V).

Step 5: Pulse ALE/PROG once.

Step 6: Lower EA/VPP from VPP to VCC

Repeat step 2 through 6 changing the address and data for the entire array or until the

end of the object file is reached (See Figure 12.).

Verify Algorithm

Code array verify must be done after each byte or block of bytes is programmed. In

either case, a complete verify of the programmed array will ensure reliable programming

of the TS87C52X2.

P 2.7 is used to enable data output.

To verify the TS87C52X2 code the following sequence must be exercised:

•

Step 1: Activate the combination of program and control signals.

Step 2: Input the valid address on the address lines.

Step 3: Read data on the data lines.

Repeat step 2 through 3 changing the address for the entire array verification (See Fig-

ure 12.)

The encryption array cannot be directly verified. Verification of the encryption array is

done by observing that the code array is well encrypted.

Figure 12. Programming and Verification Signal’s Waveform

Programming Cycle

Read/Verify Cycle

Data Out

A0-A12

D0-D7

Data In

100µs

ALE/PROG

12.75V

5V

EA/VPP

0V

Control signals

EPROM Erasure

(Windowed Packages

Only)

Erasing the EPROM erases the code array, the encryption array and the lock bits return-

ing the parts to full functionality.

Erasure leaves all the EPROM cells in a 1’s state (FF).

Erasure Characteristics

The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an

integrated dose at least 15 W-sec/cm². Exposing the EPROM to an ultraviolet lamp of

34

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

12,000 µW/cm²rating for 30 minutes, at a distance of about 25 mm, should be sufficient.

An exposure of 1 hour is recommended with most of standard erasers.

Erasure of the EPROM begins to occur when the chip is exposed to light with wave-

length shorter than approximately 4,000 Å. Since sunlight and fluorescent lighting have

wavelengths in this range, exposure to these light sources over an extended time (about

1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause inadvertent

erasure. If an application subjects the device to this type of exposure, it is suggested

that an opaque label be placed over the window.

Signature Bytes

The TS80/87C52X2 has four signature bytes in location 30h, 31h, 60h and 61h. To read

these bytes follow the procedure for EPROM verify but activate the control lines pro-

vided in Table 31. for Read Signature Bytes. Table 35. shows the content of the

signature byte for the TS80/87C52X2.

Table 21. Signature Bytes Content

Location

30h

Contents

58h

Comment

Manufacturer Code: Atmel

Family Code: C51 X2

Product name: TS80C52X2

Product name:TS87C52X2

Product name: TS80C32X2

Product revision number

31h

57h

60h

2Dh

60h

ADh

20h

60h

61h

FFh

35

4184I–8051–02/08

Electrical

Characteristics

Absolute Maximum

Ratings⁽¹⁾

Notes: 1.

Stresses at or above those listed under “ Absolute

Maximum Ratings” may cause permanent dam-

age to the device. This is a stress rating only and

functional operation of the device at these or any

other conditions above those indicated in the

operational sections of this specification is not

implied. Exposure to absolute maximum rating

conditions may affect device reliability.

Ambiant Temperature Under Bias:

C = commercial......................................................0°C to 70°C

I = industrial ........................................................-40°C to 85°C

Storage Temperature.................................... -65°C to + 150°C

Voltage on V_CCto V_SS.........................................-0.5V to + 7 V

Voltage on V_PPto V_SS.......................................-0.5V to + 13 V

Voltage on Any Pin to V_SS..........................-0.5V to V_CC+ 0.5V

Power Dissipation........................................................... 1 W⁽²⁾

2. This value is based on the maximum allowable die

temperature and the thermal resistance of the

package.

Power Consumption

Measurement

Since the introduction of the first C51 devices, every manufacturer made operating Icc

measurements under reset, which made sense for the designs were the CPU was run-

ning under reset. In Atmel new devices, the CPU is no more active during reset, so the

power consumption is very low but is not really representative of what will happen in the

customer system. That’s why, while keeping measurements under Reset, Atmel pre-

sents a new way to measure the operating Icc:

Using an internal test ROM, the following code is executed:

Label:

SJMP Label (80 FE)

Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not

connected and XTAL1 is driven by the clock.

This is much more representative of the real operating Icc.

DC Parameters for

Standard Voltage

T

A

= 0°C to +70°C; V_SS= 0 V; V_CC= 5V 10%; F = 0 to 40 MHz.

= -40°C to +85°C; V_SS= 0 V; V_CC= 5V 10%; F = 0 to 40 MHz.

Table 22. DC Parameters in Standard Voltage

Symbol

Parameter

Min

-0.5

Typ

Max

Unit

V

Test Conditions

V_IL

Input Low Voltage

0.2 V_CC- 0.1

V_CC+ 0.5

V_IH

Input High Voltage except XTAL1, RST

Input High Voltage, XTAL1, RST

0.2 V_CC+ 0.9

0.7 V_CC

V

V_IH1

V

0.3

0.45

1.0

V

I_OL= 100 µA⁽⁴⁾

I_OL= 1.6 mA⁽⁴⁾

I_OL= 3.5 mA⁽⁴⁾

V_OL

V_OL1

V_OL2

Output Low Voltage, ports 1, 2, 3 ⁽⁶⁾

Output Low Voltage, port 0 ⁽⁶⁾

0.3

0.45

1.0

V

I_OL= 200 µA⁽⁴⁾

I_OL= 3.2 mA⁽⁴⁾

I_OL= 7.0 mA⁽⁴⁾

0.3

0.45

1.0

V

I_OL= 100 µA⁽⁴⁾

I_OL= 1.6 mA⁽⁴⁾

I_OL= 3.5 mA⁽⁴⁾

Output Low Voltage, ALE, PSEN

36

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Table 22. DC Parameters in Standard Voltage (Continued)

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

I_OH= -10 µA

I_OH= -30 µA

V_CC- 0.3

V_CC- 0.7

V_CC- 1.5

V

V_OH

Output High Voltage, ports 1, 2, 3

I_OH= -60 µA

V_CC= 5V 10%

I_OH= -200 µA

I_OH= -3.2 mA

I_OH= -7.0 mA

V_CC= 5V 10%

V_CC- 0.3

V_CC- 0.7

V_CC- 1.5

V

V_OH1

Output High Voltage, port 0

I_OH= -100 µA

I_OH= -1.6 mA

I_OH= -3.5 mA

V_CC= 5V 10%

V_CC- 0.3

V_CC- 0.7

V_CC- 1.5

V

V_OH2

Output High Voltage,ALE, PSEN

R_RST

I_IL

RST Pulldown Resistor

50

90 ⁽⁵⁾

200

-50

kΩ

µA

Logical 0 Input Current ports 1, 2 and 3

Input Leakage Current

Vin = 0.45V

0.45V < Vin < V_CC

Vin = 2.0 V

I_LI

10

I_TL

Logical 1 to 0 Transition Current, ports 1, 2, 3

-650

Fc = 1 MHz

C_IO

I_PD

Capacitance of I/O Buffer

Power Down Current

10

50

pF

TA

= 25°C

20 ⁽⁵⁾

µA

2.0 V < V_{CC <}5.5V⁽³⁾

1 + 0.4 Freq

(MHz)

at12MHz 5.8

I_CC

under

RESET

Power Supply Current Maximum values, X1 mode: ⁽⁷⁾

V

_CC= 5.5V⁽¹⁾

mA

at16MHz 7.4

3 + 0.6 Freq

(MHz)

at12MHz 10.2

I_CC

operating

V

_CC= 5.5V⁽⁸⁾

at16MHz 12.6

0.25+0.3 Freq

(MHz)

I_CC

_CC= 5.5V⁽²⁾

at12MHz 3.9

at16MHz 5.1

idle

mA

37

4184I–8051–02/08

DC Parameters for Low

Voltage

T

A

= 0°C to +70°C; V_SS= 0 V; V_CC= 2.7 V to 5.5V ; F = 0 to 30 MHz.

= -40°C to +85°C; V_SS= 0 V; V_CC= 2.7 V to 5.5V ; F = 0 to 30 MHz.

Table 23. DC Parameters for Low Voltage

Symbol

Parameter

Min

-0.5

Typ

Max

0.2 V_CC- 0.1

V_CC+ 0.5

0.45

Unit

V

Test Conditions

V_IL

Input Low Voltage

V_IH

Input High Voltage except XTAL1, RST

Input High Voltage, XTAL1, RST

Output Low Voltage, ports 1, 2, 3 ⁽⁶⁾

Output Low Voltage, port 0, ALE, PSEN ⁽⁶⁾

Output High Voltage, ports 1, 2, 3

Output High Voltage, port 0, ALE, PSEN

Logical 0 Input Current ports 1, 2 and 3

Input Leakage Current

0.2 V_CC+ 0.9

0.7 V_CC

V

V_IH1

V_OL

V_OL1

V_OH

V_OH1

I_IL

V

I_OL= 0.8 mA⁽⁴⁾

I_OL= 1.6 mA⁽⁴⁾

I_OH= -10 µA

0.45

V

0.9 V_CC

V

I_OH= -40 µA

-50

10

µA

kΩ

Vin = 0.45V

I_LI

0.45V < Vin < V_CC

Vin = 2.0 V

I_TL

Logical 1 to 0 Transition Current, ports 1, 2, 3

RST Pulldown Resistor

-650

200

R_RST

50

90 ⁽⁵⁾

Fc = 1 MHz

TA = 25°C

CIO

I_PD

Capacitance of I/O Buffer

Power Down Current

10

pF

20 ⁽⁵⁾

10 ⁽⁵⁾

50

30

V_CC= 2.0 V to 5.5V⁽³⁾

V_CC= 2.0 V to 3.3 V⁽³⁾

µA

1 + 0.2 Freq

(MHz)

at12MHz 3.4

I_CC

Power Supply Current Maximum values, X1

mode: ⁽⁷⁾

under

RESET

V_CC= 3.3 V⁽¹⁾

mA

at16MHz 4.2

1 + 0.3 Freq

(MHz)

at12MHz 4.6

I_CC

Power Supply Current Maximum values, X1

mode: ⁽⁷⁾

V

_CC= 3.3 V⁽⁸⁾

operating

mA

at16MHz 5.8

0.15 Freq

(MHz) + 0.2

I_CC

Power Supply Current Maximum values, X1

mode: ⁽⁷⁾

idle

_CC= 3.3 V⁽²⁾

at12MHz 2

at16MHz 2.6

Notes: 1. I_CCunder reset is measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns (see Figure 17.), V_IL=

V_SS+ 0.5V,

V_IH= V_CC- 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V_CC. I_CCwould be slightly higher if a crystal oscillator used..

2. Idle I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns, V_IL= V_SS+ 0.5V, V_IH= V_CC

0.5V; XTAL2 N.C; Port 0 = V_CC; EA = RST = V_SS(see Figure 15.).

-

3. Power Down I_CCis measured with all output pins disconnected; EA = V_SS, PORT 0 = V_CC; XTAL2 NC.; RST = V_SS(see Fig-

ure 16.).

4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V_OLs of ALE and Ports 1

and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0

transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed

0.45V with maxi V_OLpeak 0.6V. A Schmitt Trigger use is not necessary.

5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and

5V.

6. Under steady state (non-transient) conditions, I_OLmust be externally limited as follows:

Maximum I_OLper port pin: 10 mA

Maximum I_OLper 8-bit port:

38

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Port 0: 26 mA

Ports 1, 2 and 3: 15 mA

Maximum total I_OLfor all output pins: 71 mA

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current greater

than the listed test conditions.

7. For other values, please contact your sales office.

8. Operating I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns (see Figure 17.), V_IL

V_SS+ 0.5V,

=

V

_IH= V_CC- 0.5V; XTAL2 N.C.; EA = Port 0 = V_CC; RST = V_SS. The internal ROM runs the code 80 FE (label: SJMP label). I_CC

would be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is

the worst case.

Figure 13. I_CCTest Condition, under reset

V_CC

I_CC

V_CC

P0

EA

V_CC

RST

XTAL2

XTAL1

(NC)

CLOCK

SIGNAL

V_SS

All other pins are disconnected.

Figure 14. Operating I_CCTest Condition

V_CC

I_CC

V_CC

P0

EA

Reset = Vss after a high pulse

during at least 24 clock cycles

RST

XTAL2

XTAL1

(NC)

CLOCK

SIGNAL

All other pins are disconnected.

V_SS

Figure 15. I_CCTest Condition, Idle Mode

V_CC

I_CC

V_CC

P0

EA

Reset = Vss after a high pulse

during at least 24 clock cycles

RST

(NC)

XTAL2

XTAL1

V_SS

CLOCK

SIGNAL

All other pins are disconnected.

39

4184I–8051–02/08

Figure 16. I_CCTest Condition, Power-down Mode

V_CC

I_CC

V_CC

P0

EA

Reset = Vss after a high pulse

during at least 24 clock cycles

RST

(NC)

XTAL2

XTAL1

V_SS

All other pins are disconnected.

Figure 17. Clock Signal Waveform for I_CCTests in Active and Idle Modes

V_CC-0.5V

0.7V_CC

0.2V_CC-0.1

0.45V

T_CHCL

T_CLCH

T_CLCH= T_CHCL= 5ns.

AC Parameters

Explanation of the AC

Symbols

Each timing symbol has 5 characters. The first character is always a “T” (stands for

time). The other characters, depending on their positions, stand for the name of a signal

or the logical status of that signal. The following is a list of all the characters and what

they stand for.

Example:T_AVLL= Time for Address Valid to ALE Low.

T_LLPL= Time for ALE Low to PSEN Low.

T

A

= 0 to +70°C (commercial temperature range); V_SS= 0 V; V_CC= 5V 10%; -M and -V

ranges.

= -40°C to +85°C (industrial temperature range); V_SS= 0 V; V_CC= 5V 10%; -M and

-V ranges.

= 0 to +70°C (commercial temperature range); V_SS= 0 V; 2.7 V < V_{CC <}5.5V; -L

range.

= -40°C to +85°C (industrial temperature range); V_SS= 0 V; 2.7 V < V_{CC <}5.5V; -L

T

A

T

A

T

A

range.

Table 24. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3,

and ALE and PSEN signals. Timings will be guaranteed if these capacitances are

respected. Higher capacitance values can be used, but timings will then be degraded.

Table 24. Load Capacitance versus speed range, in pF

-M

-V

50

30

-L

Port 0

100

80

100

80

Port 1, 2, 3

ALE / PSEN

100

Table 5., Table 29. and Table 32. give the description of each AC symbols.

Table 27., Table 30. and Table 33. give for each range the AC parameter.

40

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Table 28., Table 31. and Table 34. give the frequency derating formula of the AC param-

eter. To calculate each AC symbols, take the x value corresponding to the speed grade

you need (-M, -V or -L) and replace this value in the formula. Values of the frequency

must be limited to the corresponding speed grade:

Table 25. Max frequency for derating formula regarding the speed grade

-M X1 mode -M X2 mode -V X1 mode -V X2 mode -L X1 mode -L X2 mode

Freq (MHz)

T (ns)

40

25

20

50

40

25

30

20

50

33.3

Example:

T

_LLIVin X2 mode for a -V part at 20 MHz (T = 1/20^E6= 50 ns):

x= 22 (Table 28.)

T= 50ns

T_LLIV= 2T - x = 2 x 50 - 22 = 78ns

Table 26. Symbol Description

External Program Memory

Characteristics

Symbol

T

Parameter

Oscillator clock period

ALE pulse width

T_LHLL

T_AVLL

T_LLAX

T_LLIV

T_LLPL

T_PLPH

T_PLIV

T_PXIX

T_PXIZ

T_PXAV

T_AVIV

T_PLAZ

Address Valid to ALE

Address Hold After ALE

ALE to Valid Instruction In

ALE to PSEN

PSEN Pulse Width

PSEN to Valid Instruction In

Input Instruction Hold After PSEN

Input Instruction FloatAfter PSEN

PSEN to Address Valid

Address to Valid Instruction In

PSEN Low to Address Float

41

4184I–8051–02/08

Table 27. AC Parameters for Fix Clock

-V

-L

-V

X2 mode

30 MHz

X2 mode

20 MHz

standard

mode

standard

mode 40

MHz

-M

30 MHz

60 MHz

40 MHz

equiv.

Speed

Symbol

T

40 MHz

equiv.

Units

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

25

40

10

33

25

4

25

42

12

50

35

5

33

52

13

ns

T_LHLL

T_AVLL

T_LLAX

T_LLIV

4

5

70

35

45

25

78

50

65

30

98

55

T_LLPL

T_PLPH

T_PLIV

T_PXIX

T_PXIZ

T_AVIV

T_PLAZ

15

55

9

17

60

10

50

18

75

35

0

18

85

10

12

53

10

20

95

10

80

10

18

122

10

Table 28. AC Parameters for a Variable Clock: derating formula

Standard

Symbol

T_LHLL

T_AVLL

T_LLAX

T_LLIV

Type

Min

Clock

2 T - x

T - x

4 T - x

T - x

3 T - x

x

X2 Clock

T - x

-M

10

15

30

10

20

40

0

-V

8

-L

Units

ns

15

20

35

15

25

45

0

Min

0.5 T - x

2 T - x

0.5 T - x

1.5 T - x

x

13

22

8

ns

Min

ns

Max

Min

ns

T_LLPL

T_PLPH

T_PLIV

ns

Min

15

25

0

ns

Max

Min

ns

T_PXIX

T_PXIZ

T_AVIV

ns

Max

T - x

5 T - x

x

0.5 T - x

2.5 T - x

x

7

5

15

45

10

ns

40

10

30

10

ns

T_PLAZ

ns

42

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

External Program Memory

Read Cycle

Figure 18. External Program Memory Read Cycle

12 T_CLCL

T_LHLL

T_LLIV

T_LLPL

ALE

PSEN

T_PLPH

T_PXAV

T_PXIZ

T_LLAX

T_AVLL

T_PLIV

TPLAZ

T_PXIX

INSTR IN

PORT 0

PORT 2

INSTR IN

A0-A7

INSTR IN

T_AVIV

ADDRESS A8-A15

ADDRESS

OR SFR-P2

ADDRESS A8-A15

External Data Memory

Characteristics

Table 29. Symbol Description

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Parameter

RD Pulse Width

WR Pulse Width

RD to Valid Data In

Data Hold After RD

Data Float After RD

ALE to Valid Data In

Address to Valid Data In

ALE to WR or RD

T_AVDV

T_LLWL

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

Address to WR or RD

Data Valid to WR Transition

Data set-up to WR High

Data Hold After WR

RD Low to Address Float

RD or WR High to ALE high

T_WHLH

43

4184I–8051–02/08

Table 30. AC Parameters for a Fix Clock

-V

-L

-V

X2 mode

30 MHz

X2 mode

20 MHz

standard

mode

standard

mode 40

MHz

Speed

-M

30 MHz

60 MHz

equiv.

40 MHz

equiv.

40 MHz

Units

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

130

85

135

125

175

ns

100

60

102

95

137

0

30

18

98

35

165

175

95

25

42

160

165

100

155

160

105

222

235

130

T_AVDV

T_LLWL

100

70

50

75

30

47

7

55

80

45

70

5

70

103

13

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

10

15

160

15

107

9

165

17

155

10

213

18

0

T_WHLH

10

40

7

27

15

35

5

45

13

53

44

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Table 31. AC Parameters for a Variable Clock: Derating Formula

Standard

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Type

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

Clock

6 T - x

5 T - x

x

X2 Clock

3 T - x

2.5 T - x

x

-M

20

25

0

-V

15

23

0

-L

Units

ns

25

30

0

2 T - x

8 T - x

9 T - x

3 T - x

3 T + x

4 T - x

T - x

20

40

60

25

15

10

0

15

35

50

20

10

8

25

45

65

30

20

15

0

4T -x

T_AVDV

T_LLWL

4.5 T - x

1.5 T - x

1.5 T + x

2 T - x

0.5 T - x

3.5 T - x

0.5 T - x

x

T_LLWL

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

T_WHLH

7 T - x

T - x

x

0

T - x

0.5 T - x

0.5 T + x

15

10

20

T + x

External Data Memory Write

Cycle

Figure 19. External Data Memory Write Cycle

T_WHLH

ALE

PSEN

WR

T_LLWL

T_WLWH

T_QVWX

T_WHQX

T_LLAX

A0-A7

T_QVWH

DATA OUT

PORT 0

PORT 2

T_AVWL

ADDRESS

ADDRESS A8-A15 OR SFR P2

OR SFR-P2

45

4184I–8051–02/08

External Data Memory Read

Cycle

Figure 20. External Data Memory Read Cycle

T_WHLH

T_LLDV

ALE

PSEN

RD

T_LLWL

T_RLRH

T_RLDV

T_RHDZ

T_AVDV

T_LLAX

T_RHDX

DATA IN

PORT 0

PORT 2

A0-A7

T_RLAZ

T_AVWL

ADDRESS

ADDRESS A8-A15 OR SFR P2

OR SFR-P2

Serial Port Timing - Shift

Register Mode

Table 32. Symbol Description

Symbol

T_XLXL

Parameter

Serial port clock cycle time

T_QVHX

T_XHQX

T_XHDX

T_XHDV

Output data set-up to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

Table 33. AC Parameters for a Fix Clock

-V

-L

-V

X2 mode

30 MHz

X2 mode

20 MHz

-L

standard

mode 40

MHz

standard

mode

-M

60 MHz

equiv.

40 MHz

equiv.

Speed

Symbol

T_XLXL

40 MHz

30 MHz

Units

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

300

200

30

200

117

13

300

200

30

300

200

30

400

283

47

ns

T_QVHX

T_XHQX

T_XHDX

T_XHDV

0

117

34

117

200

46

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Table 34. AC Parameters for a Variable Clock: Derating Formula

Standard

Symbol

T_XLXL

Type

Min

Max

Clock

X2 Clock

6 T

-M

-V

-L

Units

ns

12 T

T_QVHX

T_XHQX

T_XHDX

T_XHDV

10 T - x

2 T - x

x

5 T - x

T - x

50

20

0

50

20

0

50

20

0

ns

x

ns

10 T - x

5 T- x

133

ns

Shift Register Timing

Waveforms

Figure 21. Shift Register Timing Waveforms

0

1

2

3

4

5

6

7

8

INSTRUCTION

ALE

T_XLXL

CLOCK

T_XHQX

1

T_QVXH

0

2

3

4

5

6

7

OUTPUT DATA

T_XHDX

VALID

SET TI

T_XHDV

WRITE to SBUF

INPUT DATA

VALID

SET RI

CLEAR RI

47

4184I–8051–02/08

EPROM Programming and

Verification Characteristics

T = 21°C to 27°C; V_SS= 0V; V_CC= 5V 10% while programming. V_CC= operating

range while verifying.

A

Table 35. EPROM Programming Parameters

Symbol

Parameter

Min

Max

13

75

6

Units

V

V_PP

Programming Supply Voltage

Programming Supply Current

Oscillator Frquency

12.5

I_PP

mA

1/T_CLCL

T_AVGL

T_GHAX

T_DVGL

T_GHDX

T_EHSH

T_SHGL

T_GHSL

T_GLGH

T_AVQV

T_ELQV

T_EHQZ

4

MHz

Address Setup to PROG Low

Adress Hold after PROG

Data Setup to PROG Low

Data Hold after PROG

(Enable) High to V_PP

48 T_CLCL

10

V_PPSetup to PROG Low

µs

V

_PPHold after PROG

10

PROG Width

90

110

Address to Valid Data

ENABLE Low to Data Valid

Data Float after ENABLE

48 T_CLCL

0

EPROM Programming and

Verification Waveforms

Figure 22. EPROM Programming and Verification Waveforms

PROGRAMMING

VERIFICATION

ADDRESS

T_AVQV

P1.0-P1.7

ADDRESS

P2.0-P2.5

P3.4-P3.5*

P

DATA OUT

P0

DATA IN

T_GHDX

T_GHAX

T_DVGL

T_AVGL

ALE/PROG

EA/V_PP

T_SHGL

T_GHSL

T_GLGH

V_PP

V_CC

T_ELQV

T_EHSH

T_EHQZ

CONTROL

SIGNALS

(ENABLE)

* 8KB: up to P2.4, 16KB: up to P2.5, 32KB: up to P3.4, 64KB: up to P3.5

48

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

External Clock Drive

Characteristics (XTAL1)

Table 36. AC Parameters

Symbol

Parameter

Oscillator Period

High Time

Low Time

Min

25

5

Max

Units

ns

T_CLCL

T_CHCX

T_CLCX

T_CLCH

T_CHCL

ns

5

ns

Rise Time

5

ns

Fall Time

ns

T_CHCX/T_CLCXCyclic ratio in X2 mode

40

60

%

External Clock Drive

Waveforms

Figure 23. External Clock Drive Waveforms

VCC-0.5V

0.7VCC

0.2VCC-0.1 V

TCHCL

0.45V

TCHCX

TCLCH

TCLCL

TCLCX

AC Testing Input/Output

Waveforms

Figure 24. AC Testing Input/Output Waveforms

VCC-0.5V

0.2VCC+0.9

0.2VCC-0.1

INPUT/OUTPUT

0.45V

AC inputs during testing are driven at V_CC- 0.5 for a logic “1” and 0.45V for a logic “0”.

Timing measurement are made at V_IHmin for a logic “1” and V_ILmax for a logic “0”.

Float Waveforms

Figure 25. Float Waveforms

FLOAT

VOH-0.1 V

VOL+0.1 V

VLOAD

VLOAD+0.1 V

VLOAD-0.1 V

For timing purposes a port pin is no longer floating when a 100 mV change from load

voltage occurs and begins to float when a 100 mV change from the loaded V_OH/V_OLlevel

occurs. I_OL/I_OH

≥

20mA.

49

4184I–8051–02/08

Clock Waveforms

Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2

divided by two.

Figure 26. Clock Waveforms

STATE1

P1P2

STATE2

P1P2

STATE3

P1P2

STATE4

P1P2

STATE4

P1P2

STATE5

P1P2

STATE6

P1P2

STATE5

P1P2

INTERNAL

CLOCK

XTAL2

ALE

THESE SIGNALS ARE NOT ACTIVATED DURING THE

EXECUTION OF A MOVX INSTRUCTION

EXTERNAL PROGRAM MEMORY FETCH

PSEN

PCL OUT

DATA

P0

DATA

SAMPLED

FLOAT

SAMPLED

FLOAT

SAMPLED

FLOAT

INDICATES ADDRESS TRANSITIONS

P2 (EXT)

READ CYCLE

RD

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

P0

P2

DPL OR Rt

FLOAT

INDICATES DPH OR P2 SFR TO PCH TRANSITION

WRITE CYCLE

WR

PCL OUT (EVEN IF PROGRAM

MEMORY IS INTERNAL)

P0

DPL OR Rt

DATA OUT

INDICATES DPH OR P2 SFR TO PCH TRANSITION

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

P2

PORT OPERATION

OLD DATA

NEW DATA

P0 PINS SAMPLED

MOV DEST P0

P1, P2, P3 PINS SAMPLED

RXD SAMPLED

P1, P2, P3 PINS SAMPLED

MOV DEST PORT (P1, P2, P3)

(INCLUDES INT0, INT1, TO, T1)

RXD SAMPLED

SERIAL PORT SHIFT CLOCK

TXD (MODE 0)

This diagram indicates when signals are clocked internally. The time it takes the signals

to propagate to the pins, however, ranges from 25 to 125 ns. This propagation delay is

dependent on variables such as temperature and pin loading. Propagation also varies

from output to output and component. Typically though (T_A= 25°C fully loaded) RD and

WR propagation delays are approximately 50ns. The other signals are typically 85 ns.

Propagation delays are incorporated in the AC specifications.

50

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Ordering Information

Table 37. Possible Ordering Entries

Temperature

Range

Part Number⁽³⁾

TS80C32X2-MCA

TS80C32X2-MCB

TS80C32X2-MCC

TS80C32X2-MCE

TS80C32X2-LCA

TS80C32X2-LCB

TS80C32X2-LCC

TS80C32X2-LCE

TS80C32X2-VCA

TS80C32X2-VCB

TS80C32X2-VCC

TS80C32X2-VCE

TS80C32X2-MIA

TS80C32X2-MIB

TS80C32X2-MIC

TS80C32X2-MIE

TS80C32X2-LIA

TS80C32X2-LIB

TS80C32X2-LIC

TS80C32X2-LIE

TS80C32X2-VIA

TS80C32X2-VIB

TS80C32X2-VIC

TS80C32X2-VIE

Memory Size

Supply Voltage

Max Frequency

Package

Packing

OBSOLETE

AT80C32X2-3CSUM

AT80C32X2-SLSUM

AT80C32X2-RLTUM

AT80C32X2-RLRUM

AT80C32X2-SLRUM

AT80C32X2-3CSUL

ROMLess

5V 10%

2.7 to 5.5V

Industrial & Green

40 MHz⁽¹⁾

30 MHz⁽¹⁾

PDIL40

PLCC44

VQFP44

PLCC44

PDIL40

Stick

Tray

Tape & Reel

Stick

52

4184I–8051–02/08

Table 37. Possible Ordering Entries (Continued)

Temperature

Range

Part Number⁽³⁾

Memory Size

ROMLess

Supply Voltage

2.7 to 5.5V

5V 10%

Max Frequency

30 MHz⁽¹⁾

Package

PLCC44

VQFP44

PDIL40

Packing

Stick

AT80C32X2-SLSUL

AT80C32X2-RLTUL

AT80C32X2-3CSUV

AT80C32X2-SLSUV

AT80C32X2-RLTUV

Industrial & Green

30 MHz⁽¹⁾

Tray

60 MHz⁽³⁾

Stick

5V 10%

60 MHz⁽³⁾

PLCC44

VQFP44

Stick

5V 10%

60 MHz⁽³⁾

Tray

TS80C52X2zzz-MCA

TS80C52X2zzz-MCB

TS80C52X2zzz-MCC

TS80C52X2zzz-MCE

TS80C52X2zzz-LCA

TS80C52X2zzz-LCB

TS80C52X2zzz-LCC

TS80C52X2zzz-LCE

TS80C52X2zzz-VCA

TS80C52X2zzz-VCB

TS80C52X2zzz-VCC

TS80C52X2zzz-VCE

TS80C52X2zzz-MIA

TS80C52X2zzz-MIB

TS80C52X2zzz-MIC

TS80C52X2zzz-MIE

TS80C52X2zzz-LIA

TS80C52X2zzz-LIB

TS80C52X2zzz-LIC

TS80C52X2zzz-LIE

TS80C52X2zzz-VIA

TS80C52X2zzz-VIB

TS80C52X2zzz-VIC

TS80C52X2zzz-VIE

OBSOLETE

AT80C52X2zzz-3CSUM

AT80C52X2zzz-SLSUM

8K ROM

5V 10%

Industrial & Green

40 MHz⁽¹⁾

PDIL40

Stick

PLCC44

53

TS8xCx2X2

4184I–8051–02/08

TS8xCx2X2

Table 37. Possible Ordering Entries (Continued)

Temperature

Range

Part Number⁽³⁾

Memory Size

8K ROM

Supply Voltage

5V 10%

Max Frequency

40 MHz⁽¹⁾

30 MHz⁽¹⁾

60 MHz⁽³⁾

Package

VQFP44

PDIL40

Packing

Tray

AT80C52X2zzz-RLTUM

AT80C52X2zzz-3CSUL

AT80C52X2zzz-SLSUL

AT80C52X2zzz-RLTUL

AT80C52X2zzz-3CSUV

AT80C52X2zzz-SLSUV

AT80C52X2zzz-RLTUV

Industrial & Green

2.7 to 5.5V

5V 10%

Stick

Tray

PLCC44

VQFP44

PDIL40

Stick

Tray

5V 10%

PLCC44

VQFP44

5V 10%

TS87C52X2-MCA

TS87C52X2-MCB

TS87C52X2-MCC

TS87C52X2-MCE

TS87C52X2-LCA

TS87C52X2-LCB

TS87C52X2-LCC

TS87C52X2-LCE

TS87C52X2-VCA

TS87C52X2-VCB

TS87C52X2-VCC

TS87C52X2-VCE

TS87C52X2-MIA

TS87C52X2-MIB

TS87C52X2-MIC

TS87C52X2-MIE

TS87C52X2-LIA

TS87C52X2-LIB

TS87C52X2-LIC

TS87C52X2-LIE

TS87C52X2-VIA

TS87C52X2-VIB

TS87C52X2-VIC

TS87C52X2-VIE

AT87C52X2-3CSUM

OBSOLETE

8K OTP

5V 10%

Industrial & Green

40 MHz⁽¹⁾

PDIL40

Stick

54

4184I–8051–02/08

Table 37. Possible Ordering Entries (Continued)

Temperature

Range

Part Number⁽³⁾

Memory Size

8K OTP

Supply Voltage

5V 10%

Max Frequency

40 MHz⁽¹⁾

30 MHz⁽¹⁾

60 MHz⁽³⁾

Package

PLCC44

VQFP44

PDIL40

Packing

Stick

Tray

AT87C52X2-SLSUM

AT87C52X2-RLTUM

AT87C52X2-3CSUL

AT87C52X2-SLSUL

AT87C52X2-RLTUL

AT87C52X2-3CSUV

AT87C52X2-SLSUV

AT87C52X2-RLTUV

Industrial & Green

5V 10%

2.7 to 5.5V

5V 10%

Stick

Tray

PLCC44

VQFP44

PDIL40

Stick

Tray

5V 10%

PLCC44

VQFP44

5V 10%

Notes: 1. 20 MHz in X2 Mode.

2. Tape and Reel available for SL, PQFP and RL packages

3. 30 MHz in X2 Mode.

55

TS8xCx2X2

4184I–8051–02/08

Atmel Headquarters

Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

Postfach 3535

74025 Heilbronn, Germany

TEL (49) 71-31-67-0

FAX (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

Europe

Microcontrollers

Atmel Sarl

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

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TEL 1(719) 576-3300

Route des Arsenaux 41

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FAX 1(719) 540-1759

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FAX (33) 4-76-58-34-80

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FAX (41) 26-426-5500

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TEL (33) 2-40-18-18-18

FAX (33) 2-40-18-19-60

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Chinachem Golden Plaza

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East Kowloon

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TEL (852) 2721-9778

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TEL (33) 4-42-53-60-00

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e-mail

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http://www.atmel.com

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or

otherwise, to any intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET

FORTH IN ATMEL’S TERMS AND CONDITIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER

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Atmel Corporation or its subsidiaries. Other terms and product names may be trademarks of others.

4184I–8051–02/08

/xM


型号：	TS80C32X2-MCE
厂家：	ATMEL
描述：	8-bit Microcontroller 8 Kbytes ROM/OTP, ROMless 8位微控制器8K字节ROM / OTP ，无ROM 微控制器和处理器外围集成电路时钟
文件：	总55页 (文件大小：596K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TS80C32X2-MCE [ATMEL]

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