TS8388BMFSB/QQC1_技术文档

Features

• 8-bit Resolution

• ADC Gain Adjust

• 1.5 GHz Full Power Input Bandwidth (-3 dB)

• 1 GSPS (min) Sampling Rate

• SINAD = 44.3 dB (7.2 Effective Bits), SFDR = 58 dBc,

at F_S= 1 GSPS, F_IN= 20 MHz

• SINAD = 42.9 dB (7.0 Effective Bits), SFDR = 52 dBc,

at F_S= 1 GSPS, F_IN= 500 MHz

• SINAD = 40.3 dB (6.8 Effective Bits), SFDR = 50 dBc,

at F_S= 1 GSPS, F_IN= 1000 MHz (-3 dB FS)

• 2-tone IMD: -52 dBc (489 MHz, 490 MHz) at 1 GSPS

• DNL = 0.3 lsb, INL = 0.7 lsb

ADC 8-bit

1 GSPS

• Low Bit Error Rate (10^-13) at 1 GSPS

• Very Low Input Capacitance: 3 pF

• 500 mVpp Differential or Single-ended Analog Inputs

• Differential or Single-ended 50Ω ECL Compatible Clock Inputs

• ECL or LVDS/HSTL Output Compatibility

• Data Ready Output with Asynchronous Reset

• Gray or Binary Selectable Output Data; NRZ Output Mode

• Power Consumption: 3.4W at Tj = 70°C Typical

• Radiation Tolerance Oriented Design (150 Krad (Si) measured)

• Two Package Versions

TS8388BF

• ESA/SCC Detailed Specification Available on Request

• Enhanced CQFP68 Packaged Device: TS8388BFS

• Evaluation board: TSEV8388BF

• Demultiplexer: TS81102G0: Companion Device Available

Applications

•

Digital Sampling Oscilloscopes

Satellite Receiver

Electronic Countermeasures/Electronic Warfare

Direct RF Down-conversion

Screening

•

Atmel Standard Screening Level

Mil-PRF-38535, QML Level Q for Package Version, DSCC 5962-0050401QYC

Temperature Range: up to -55°C < Tc; Tj < +125°C

Description

The TS8388BF is a monolithic 8-bit analog-to-digital converter, designed for digitizing

wide bandwidth analog signals at very high sampling rates of up to 1 GSPS.

The TS8388BF uses an innovative architecture,

including an on-chip Sample and Hold (S/H),

and is fabricated with an advanced

high speed bipolar process.

The on-chip S/H has a 1.5 GHz full power

input bandwidth, providing excellent dynamic

performance in undersampling applications

(High IF digitizing).

F Suffix: CQFP 68

Ceramic Quad Flat Pack

Rev. 2144A–BDC–04/02

1

Functional

Description

Block Diagram

The following figure shows the simplified block diagram.

Figure 1. Simplified Block Diagram

GAIN

MASTER/SLAVE TRACK & HOLD AMPLIFIER

ANALOG

ENCODING

BLOCK

V_IN,V_INB

4

RESISTOR

CHAIN

INTERPOLATION

STAGES

G=2

T/H

G=1

T/H

G=1

5

4

REGENERATION

LATCHES

ERROR CORRECTION &

DECODE LOGIC

CLK, CLKB

CLOCK

BUFFER

8

OUTPUT LATCHES &

BUFFERS

8

GORB

DATA, DATAB OR, ORB

DRRB DR, DRB

Functional

Description

The TS8388BF is an 8-bit 1 GSPS ADC based on an advanced high-speed bipolar technology

featuring a cutoff frequency of 25 GHz.

The TS8388BF includes a front-end master/slave Track and Hold stage (S/H), followed by an

analog encoding stage and interpolation circuitry.

Successive banks of latches regenerate the analog residues into logical data before entering

an error correction circuitry and a resynchronization stage followed by 75Ω differential output

buffers.

The TS8388BF works in fully differential mode from analog inputs up to digital outputs.

The TS8388BF features a full-power input bandwidth of 1.5 GHz.

A control pin GORB is provided to select either Gray or Binary data output format.

A gain control pin is provided in order to adjust the ADC gain.

A Data Ready output asynchronous reset (DRRB) is available on TS8388BF.

The TS8388BF uses only vertical isolated NPN transistors together with oxide isolated polysil-

icon resistors, which allow enhanced radiation tolerance (no performance drift measured at

150 kRad total dose).

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TS8388BF

2144A–BDC–04/02

TS8388BF

Specifications

Absolute

Maximum Ratings

Table 1. Absolute Maximum Ratings

Parameter

Symbol

V_CC

Comments

Value

Unit

Positive supply voltage

GND to 6

GND to -5.7

GND -0.3 to 2.8

GND to -6

0.3

V

Digital negative supply voltage

Digital positive supply voltage

Negative supply voltage

DV_EE

V_PLUSD

V_EE

V

Maximum difference between negative supply voltage

Analog input voltages

DV_EEto V_EE

V

_INor V_INB

-1 to +1

V

Maximum difference between V_INand V_INB

Digital input voltage

V_IN- V_INB

-2 to +2

V

V_D

V_O

GORB

DRRB

-0.3 to V_CC+0.3

V_EE-0.3 to +0.9

V_PLUSD-3 to V_PLUSD-0.5

-3 to +1.5

V

Digital input voltage

V

Digital output voltage

V

Clock input voltage

V_CLKor V_CLKB

V

Maximum difference between V_CLKand V_CLKB

Maximum junction temperature

Storage temperature

V_CLK- V_CLKB

-2 to +2

V

T_j

+135

°C

T_stg

T_leads

-65 to +150

+300

Lead temperature (soldering 10s)

Note:

Absolute maximum ratings are limiting values (referenced to GND = 0V), to be applied individually, while other parameters are

within specified operating conditions. Long exposure to maximum rating may affect device reliability. The use of a thermal heat

sink is mandatory. See “The board set comes fully assembled and tested, with the TS8388BF in CQFP68 package installed.” on

page 37.

Recommended

Operating

Conditions

Table 2. Recommended Operating Conditions

Recommended Value

Parameter

Symbol

V_CC

Comments

Min

Typ

+5

Max

Unit

V

Positive supply voltage

Positive digital supply voltage

Negative supply voltage

4.5

–

5.25

–

V_PLUSD

V_EE,DV_EE

ECL output compatibility

LVDS output compatibility

GND

+2.4

-5

V

+1.4

-5.25

+2.6

-4.75

V

3

2144A–BDC–04/02

Table 2. Recommended Operating Conditions (Continued)

Recommended Value

Parameter

Symbol

Comments

Min

Typ

Max

Unit

Differential analog input voltage

(Full Scale)

V_IN,V_INB

50Ω differential or single-ended

±113

450

±125

500

±137

550

mV

V_IN- V_INB

mVpp

Clock input power level

P

_CLK,P_CLKB

50Ω single-ended clock input

3

4

10

dBm

Operating temperature range

T_J

Commercial grade: “C”

Industrial grade: “V”

Military grade: “M”

0 < Tc; Tj < 90

-40 < Tc; Tj < 110

-55 < Tc; Tj < +125

°C

Electrical

Operating

Characteristics

V_EE= DV_EE= -5V; V_CC= +5V; V_IN-V_INB= 500 mVpp Full Scale differential input;

Digital outputs 75 or 50Ω differentially terminated;

Tj (typical) = 70°C. Full Temperature Range: up to -55°C < Tc; Tj < +125°C.

Table 3. Electrical Specifications

Value

Typ

Test

Level

Parameter

Symbol

Min

Max

Unit

Note

Power Requirements

Positive supply voltage

Analog

Digital (ECL)

Digital (LVDS)

V_CC

1, 2, 6

4.7

–

5

0

5.3

–

V

V_PLUSD

4

1.4

2.4

2.6

Positive supply current

Analog

Digital

I_CC

1, 2

6

–

385

395

115

120

445

145

mA

I_PLUSD

1, 2

6

Negative supply voltage

Negative supply current

V_EE

1, 2, 6

-5.3

-5

-4.7

V

Analog

Digital

AI_EE

DI_EE

1, 2

6

–

165

170

135

145

200

180

mA

1, 2

6

Nominal power dissipation

1, 2

6

–

3.4

3.6

4.1

4.3

W

PD

Power supply rejection ratio

PSRR

–

4

–

0.5

8

2

–

mW

bits

(2)

Resolution

4

TS8388BF

2144A–BDC–04/02

TS8388BF

Table 3. Electrical Specifications (Continued)

Value

Typ

Test

Level

Parameter

Symbol

Min

Max

Unit

Note

Analog Inputs

Full Scale Input Voltage range (differential mode)

(0V common mode voltage)

V_IN

4

–

-125

–

125

mV

V_INB

Full Scale Input Voltage range (single-ended input

option) (See Application Notes)

V_IN

4

–

-250

–

0

250

–

mV

V_INB

Analog input capacitance

Input bias current

C_IN

I_IN

4

–

3

10

1

3.5

20

–

pF

µA

–

Input Resistance

R_IN

0.5

1.3

1.5

MΩ

GHz

Full Power input Bandwidth

Small signal input Bandwidth (10% full scale)

Clock Inputs

FPBW

SSBW

1.5

1.7

–

Logic compatibility for clock inputs

(See Application Notes)

ECL or specified clock input

power level in dBm

(10)

–

ECL Clock inputs voltages (V_CLKor V_CLKB):

Logic “0” voltage

–

V_IL

V_IH

I_IL

4

–

4

–

-1.5

–

V

–

Logic “1” voltage

-1.1

–

V

Logic “0” current

5

50

µA

–

Logic “1” current

I_IH

–

5

Clock input power level into 50Ω termination

Clock input power level

Clock input capacitance

Digital Outputs

–

dBm into 50Ω

–

-2

–

4

3

10

dBm

pF

C_CLK

3.5

(1)(6)

Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format,

Tj (typical) = 70°C.

Logic compatibility for digital outputs

(Depending on the value of V_PLUSD

)

–

4

ECL or LVDS

–

(See Application Notes)

Differential output voltage swings

(assuming V_PLUSD= 0V):

–

75Ω open transmission lines (ECL levels)

75Ω differentially terminated

–

1.5

1.620

0.825

0.660

–

V

0.70

0.54

50Ω differentially terminated

Output levels (assuming V_PLUSD= 0V)

(6)

–

4

–

75Ω open transmission lines:

Logic “0” voltage

Logic “1” voltage

V_OL

V_OH

–

-1.62

-0.8

-1.54

–

V

-0.88

5

2144A–BDC–04/02

Table 3. Electrical Specifications (Continued)

Value

Typ

Test

Level

Parameter

Symbol

Min

Max

Unit

Note

Output levels (assuming V_PLUSD= 0V)

(6)

–

4

–

75Ω differentially terminated:

Logic “0” voltage

Logic “1” voltage

V_OL

V_OH

–

-1.41

-1

-1.34

–

V

-1.07

Output levels (assuming V_PLUSD= 0V)

(6)

–

50Ω differentially terminated:

Logic “0” voltage

V_OL

1, 2

6

–

-1.40

-1.32

-1.25

V

Logic “1” voltage

V_OH

1, 2

6

-1.16

-1.25

-1.10

–

V

Differential Output Swing

Output level drift with temperature

DC Accuracy

DOS

–

4

270

–

300

–

mV

1.6

mV/°C

Single-ended or differential input mode, 50% clock duty cycle (CLK, CLKB), Binary output data format

Tj (typical) = 70°C.

Differential non linearity

Integral non linearity

1, 2

6

-0.5

-0.6

-0.25

-0.35

–

lsb

(2)(3)

DNL-

DNL+

INL-

1, 2

6

–

0.3

0.4

0.6

0.7

lsb

1, 2

6

-1.0

-1.2

0.7

0.9

–

lsb

(2)(3)

1, 2

6

–

0.7

0.9

1.0

1.2

lsb

INL+

(3)

No missing code

Gain error

–

Guaranteed over specified temperature range

1, 2

6

-10

-11

-2

10

11

% F_S

Input offset voltage

1, 2

6

-26

-30

-5

26

30

mV

–

Gain error drift

Offset error drift

–

4

100

40

125

50

150

60

ppm/°C

Transient Performance

Bit Error Rate

Error/

sample

(2)(4)

BER

4

–

1E-12

F_S= 1 GSPS F_IN= 62.5 MHz

ADC settling time

(2)

TS

4

–

0.5

1

ns

V_IN-V_INB= 400 mVpp

Overvoltage recovery time

TOR

6

TS8388BF

2144A–BDC–04/02

TS8388BF

Table 3. Electrical Specifications (Continued)

Value

Typ

Test

Level

Parameter

Symbol

Min

Max

Unit

Note

AC Performance

Single-ended or differential input and clock mode, 50% clock duty cycle (CLK, CLKB), Binary output data format,

Tj = 70°C, unless otherwise specified.

(2)

Signal to Noise and Distortion ratio

F_S= 1 GSPS, F_IN= 20 MHz

–

42

41

38

40

–

44

43

40

44

–

4

dB

–

F_S= 1 GSPS, F_IN= 500 MHz

F_S= 1 GSPS, F_IN= 1000 MHz (-1 dBFs)

F_S= 50 MSPS, F_IN= 25 MHz

Effective Number Of Bits

SINAD

ENOB

SNR

4

1, 2, 6

–

F_S= 1 GSPS, F_IN= 20 MHz

4

7.0

6.6

6.2

7.0

–

7.2

6.8

6.4

7.2

–

Bits

–

F_S= 1 GSPS, F_IN= 500 MHz

F_S= 1 GSPS, F_IN= 1000 MHz (-1 dBFs)

F_S= 50 MSPS, F_IN= 25 MHz

Signal to Noise Ratio

4

1, 2, 6

(2)

–

F_S= 1 GSPS, F_IN= 20 MHz

4

42

41

44

–

45

44

45

–

dB

–

F_S= 1 GSPS, F_IN= 500 MHz

F_S= 1 GSPS, F_IN= 1000 MHz (-1 dBFs)

F_S= 50 MSPS, F_IN= 25 MHz

Total Harmonic Distortion

4

1, 2, 6

–

F_S= 1 GSPS, F_IN= 20 MHz

4

50

46

42

46

–

54

50

46

45

–

dB

–

F_S= 1 GSPS, F_IN= 500 MHz

F_S= 1 GSPS, F_IN= 1000 MHz (-1 dBFs)

F_S= 50 MSPS, F_IN= 25 MHz

Spurious Free Dynamic Range

F_S= 1 GSPS, F_IN= 20 MHz

THD

4

1, 2, 6

–

4

52

47

42

45

40

–

57

52

47

50

54

–

dBc

–

F_S= 1 GSPS, F_IN= 500 MHz

F_S= 1 GSPS, F_IN= 1000 MHz (-1 dBFs)

F_S= 1 GSPS, F_IN= 1000 MHz (-3 dBFs)

F_S= 50 MSPS, F_IN= 25 MHz

Two-tone Inter-modulation Distortion

4

SFDR

4

1, 2, 6

4

(2)

IMD

F_IN1= 489 MHz at F_S= 1 GSPS,

F_IN2= 490 MHz at F_S= 1 GSPS

–

-47

-52

–

dBc

Switching Performance and Charcteristics – See Figure 2 and Figure 3 on page 9

(14)

(15)

Maximum clock frequency

Minimum clock frequency

F_S

–

4

1

–

1.4

50

GSPS

MSPS

ns

10

Minimum Clock pulse width (high)

TC1

0.280

0.500

7

2144A–BDC–04/02

Table 3. Electrical Specifications (Continued)

Value

Typ

Test

Level

Parameter

Symbol

TC2

Min

0.350

100

–

Max

50

Unit

ns

Note

Minimum Clock pulse width (low)

Aperture delay

4

0.500

+250

0.4

(2)

Ta

400

0.6

ps

(2)(5)

Aperture uncertainty

Data output delay

Jitter

ps (rms)

(2)(10)

TDO

4

1150

1360

1660

ps

(11)(12)

(11)

Output rise/fall time for DATA (20% – 80%)

Output rise/fall time for DATA READY (20% – 80%)

Data ready output delay

TR/TF

4

250

350

550

ps

(2)(10)

TDR

TRDR

4

1110

1320

720

40

1620

1000

80

ps

(11)(12)

Data ready reset delay

–

0

(9)(13)

(14)

Data to data ready – Clock low pulse width

(See “Timing Diagrams” on page 9.)

TOD-TDR

Data to data ready output delay (50% duty cycle)

at 1 GSPS (See “Timing Diagrams” on page 9.)

(2)(15)

TD1

TPD

4

420

460

4

500

ps

Data pipeline delay

clock

cycles

Notes: 1. Differential output buffers are internally loaded by 75Ω resistors. Buffer bias current = 11 mA.

2. See “Definition of Terms” on page 41.

3. Histogram testing based on sampling of a 10 MHz sinewave at 50 MSPS.

4. Output error amplitude < ± 4 lsb around correct code (including gain and offset error).

5. Maximum jitter value obtained for single-ended clock input on the JTS8388B die (chip on board): 200 fs. (500 fs expected on

TS8388BG)

6. Digital output back termination options depicted in Application Notes.

7. With a typical value of TD = 465 ps, at 1 GSPS, the timing safety margin for the data storing using the ECLinPS 10E452 out-

put registers from Motorola^®is of ± 315 ps, equally shared before and after the rising edge of the Data Ready signals (DR,

DRB).

8. The clock inputs may be indifferently entered in differential or single-ended, using ECL levels or 4 dBm typical power level

into the 50Ω termination resistor of the inphase clock input. (4 dBm into 50Ω clock input correspond to 10 dBm power level

for the clock generator.)

9. At 1 GSPS, 50/50 clock duty cycle, TC2 = 500 ps (TC1). TDR - TOD = -100 ps (typ) does not depend on the sampling rate.

10. Specified loading conditions for digital outputs:

- 50Ω or 75Ω controlled impedance traces properly 50/75Ω terminated, or unterminated 75Ω controlled impedance traces.

- Controlled impedance traces far end loaded by 1 standard ECLinPS register from Motorola. (i.e.: 10E452) (Typical input

parasitic capacitance of 1.5 pF including package and ESD protections.)

11. Termination load parasitic capacitance derating values:

- 50Ω or 75Ω controlled impedance traces properly 50/75Ω terminated: 60 ps/pF or 75 ps per additionnal ECLinPS load.

- Unterminated (source terminated) 75Ω controlled impedance lines: 100 ps/pF or 150 ps per additionnal ECLinPS termina-

tion load.

12. Apply proper 50/75Ω impedance traces propagation time derating values: 6 ps/mm (155 ps/inch) for TSEV8388BF Evalua-

tion Board.

13. Values for TOD and TDR track each other over temperature, (1% variation for TOD-TDR per 100°C temperature variation).

Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip) and package skews between

each Data TODs and TDR effect can be considered as negligible. Consequently, minimum values for TOD and TDR are

never more than 100 ps apart. The same is true for the TOD and TDR maximum values (see Advanced Application Notes

about “TOD-TDR Variation Over Temperature” on page 23).

14. Min value guarantees performance. Max value guarantees functionality.

15. Min value guarantees functionality. Max value guarantees performance.

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TS8388BF

2144A–BDC–04/02

TS8388BF

Timing Diagrams

Figure 2. TS8388BF Timing Diagram (1 GSPS Clock Rate), Data Ready Reset, Clock Held at LOW Level

TA = 250 ps TBC

X

N+5

X

N+4

X

N+3

X

N+2

X

N+1

X

N

(VIN, VINB)

X

N-1

TC = 1000 ps

TC1 TC2

(CLK, CLKB)

TOD = 1360 ps

TPD: 4.0 Clock periods

1360 ps

DIGITAL

OUTPUTS

1000 ps

DATA

N-5

DATA

N-4

DATA

N-3

DATA

N-2

DATA

N-1

DATA

N

N+1

TD1 = TC1+TDR-TOD

= TC1-40 ps = 460 ps

TDR = 1320 ps

Data Ready

(DR, DRB)

TD2 = TC2+TOD-TDR

= TC2+40 ps = 540 ps

TRDR = 720 ps

DRRB

1 ns (min)

Figure 3. TS8388BF Timing Diagram (1 GSPS Clock Rate), Data Ready Reset, Clock Held at HIGH Level

TA = 250 ps TBC

X

N+5

X

N+4

X

N+2

N+1

N

(VIN, VINB)

X

N-1

TC = 1000 ps

TC1 TC2

(CLK, CLKB)

TOD = 1360 ps

TPD: 4.0 Clock periods

1360 ps

1000 ps

DIGITAL

OUTPUTS

DATA

N-5

DATA

N-4

DATA

N-3

DATA

N-2

DATA

N-1

DATA

N

DATA

N+1

TD1 = TC1+TDR-TOD

= TC1-40 ps = 460 ps

TDR = 1320 ps

Data Ready

(DR, DRB)

TD2 = TC2+TOD-TDR

= TC2+40 ps = 540 ps

TRDR = 720 ps

DRRB

1 ns (min)

9

2144A–BDC–04/02

Explanation of

Test Levels

Table 4. Explanation of Test Levels

Num

Characteristics

1

100% production tested at +25°C⁽¹⁾(for “C” Temperature range⁽²⁾).

100% production tested at +25°C⁽¹⁾, and sample tested at specified temperatures

2

3

4

5

6

(for “V” and “M” Temperature range⁽²⁾).

Sample tested only at specified temperatures.

Parameter is guaranteed by design and characterization testing (thermal steady-state

conditions at specified temperature).

Parameter is a typical value only.

100% production tested over specified temperature range

(for “B/Q” Temperature range⁽²⁾).

Notes: 1. Unless otherwise specified, all tests are pulsed tests: therefore Tj = Tc = Ta, where Tj, Tc

and Ta are junction, case and ambient temperature respectively.

2. Refer to “Ordering Information” on page 43.

3. Only MIN and MAX values are guaranteed (typical values are issuing from characterization

results).

Functions

Description

Table 5. Functions Description

Name

V_CC

Function

Positive power supply

Analog negative power supply

Digital positive power supply

Ground

VPLUSD = +0V (ECL)

VPLUSD = +2.4V (LVDS)

V_EE

VCC = +5V

V_PLUSD

GND

VIN

OR

V_IN, V_INB

CLK, CLKB

Differential analog inputs

Differential clock inputs

Differential output data port

VINB

ORB

CLK

CLKB

GAIN

<D0:D7>

D0

D0B

D7

D7B

16

TS8388BF

<D0B:D7B>

DR

DR, DRB

OR, ORB

GAIN

Differential data ready outputs

Out of range outputs

GORG

DRB

DIOD/

DRRB

ADC gain adjust

GORB

Gray or Binary digital output select

DIOD/DRRB

Die junction temperature measurement/

asynchronous data ready reset

DVEE = -5V VEE = -5V GND

10

TS8388BF

2144A–BDC–04/02

TS8388BF

Digital Output

Coding

NRZ (Non Return to Zero) mode, ideal coding: does not include gain, offset, and linearity volt-

age errors.

Table 6. Digital Output Coding

Digital Output

Binary

Gray

Differential

Analog Input

Out of

Range

Voltage Level

GORB = VCC or Floating

GORB = GND

> +251 mV

> Positive full scale + 1/2 lsb

1 1 1 1 1 1 1 1

1 0 0 0 0 0 0 0

1

+251 mV

+249 mV

Positive full scale + 1/2 lsb

Positive full scale - 1/2 lsb

1 1 1 1 1 1 1 1

1 1 1 1 1 1 1 0

1 0 0 0 0 0 0 0

1 0 0 0 0 0 0 1

0

+126 mV

+124 mV

Positive 1/2 scale + 1/2 lsb

Positive 1/2 scale - 1/2 lsb

1 1 0 0 0 0 0 0

1 0 1 1 1 1 1 1

1 0 1 0 0 0 0 0

1 1 1 0 0 0 0 0

0

+1 mV

-1 mV

Bipolar zero + 1/2 lsb

Bipolar zero - 1/2 lsb

1 0 0 0 0 0 0 0

0 1 1 1 1 1 1 1

1 1 0 0 0 0 0 0

0 1 0 0 0 0 0 0

0

-124 mV

-126 mV

Negative 1/2 scale + 1/2 lsb

Negative 1/2 scale - 1/2 lsb

0 1 0 0 0 0 0 0

0 0 1 1 1 1 1 1

0 1 1 0 0 0 0 0

0 0 1 0 0 0 0 0

0

-249 mV

-251 mV

Negative full scale + 1/2 lsb

Negative full scale - 1/2 lsb

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

0 0 0 0 0 0 0 1

0 0 0 0 0 0 0 0

0

< -251 mV

< Negative full scale - 1/2 lsb

0 0 0 0 0 0 0 0

1

11

2144A–BDC–04/02

Package

Description

Pin Description

Table 7. TS8388BF Pin Description

Symbol

Pin number

Function

GND

5, 13, 27, 28, 34, 35, 36, 41, 42, 43, 50, 51,

52, 53, 58, 59

Ground pins.

To be connected to external ground plane.

V_PLUSD

1, 2, 16, 17, 18, 68

Digital positive supply (0V for ECL compatibility, 2.4V for

LVDS compatibility).⁽²⁾

V_CC

V_EE

DV_EE

V_IN

26, 29, 32, 33, 46, 47, 61

30, 31, 44, 45, 48

8, 9, 10

+5V positive supply.

-5V analog negative supply.

-5V digital negative supply.

54⁽¹⁾, 55

In phase (+) analog input signal of the Sample and Hold

differential preamplifier.

V_INB

CLK

56, 57⁽¹⁾

37⁽¹⁾, 38

Inverted phase (-) of analog input signal (V_IN).

In phase (+) ECL clock input signal. The analog input is

sampled and held on the rising edge of the CLK signal.

CLKB

39, 40⁽¹⁾

Inverted phase (-) of ECL clock input signal (CLK).

D0, D1, D2, D3, D4,

D5, D6, D7

23, 21, 19, 14, 6, 3, 66, 64

In phase (+) digital outputs.

B0 is the LSB. B7 is the MSB.

D0B, D1B, D2B, D3B,

D4B, D5B, D6B, D7B

24, 22, 20, 15, 7, 4, 67, 65

62

Inverted phase (-) digital outputs.

B0B is the inverted LSB. B7B is the inverted MSB.

OR

In phase (+) Out of Range Bit. Out of Range is high on the

leading edge of code 0 and code 256.

ORB

DR

63

11

12

25

Inverted phase (+) Out of Range Bit (OR).

In phase (+) output of Data Ready Signal.

Inverted phase (-) output of Data Ready Signal (DR).

Gray or Binary select output format control pin.

DRB

GORB

- Binary output format if GORB is floating or V_CC

.

- Gray output format if GORB is connected at ground (0V).

GAIN

60

49

ADC gain adjust pin.

DIOD/DRRB

This pin has a double function (can be left open or grounded

if not used):

- DIOD: die junction temperature monitoring pin.

- DRRB: asynchronous data ready reset function.

Notes: 1. Following pin numbers 37 (CLK), 40 (CLKB), 54 (V_IN) and 57 (V_INB) have to be connected to GND through a 50Ω resistor as

close as possible to the package (50Ω termination preferred option).

2. The common mode level of the output buffers is 1.2V below the positive digital supply.

For ECL compatibility the positive digital supply must be set at 0V (ground).

For LVDS compatibility (output common mode at +1.2V) the positive digital supply must be set at 2.4V.

If the subsequent LVDS circuitry can withstand a lower level for input common mode, it is recommended to lower the posi-

tive digital supply level in the same proportion in order to spare power dissipation.

12

TS8388BF

2144A–BDC–04/02

TS8388BF

TS8388BF Pinout

Figure 4. TS8388BF Pinout

TOP VIEW

17 16 15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

Pin 1 index

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

33

34

VPLUSD

D2

VPLUSD

D6B

D6

68

67

66

65

64

63

62

61

60

59

58

57

56

55

54

53

52

D2B

D1

D7B

D7

D1B

D0

ORB

D0B

GORB

VCC

OR

VCC

Gain

TS8388BF

GND

VCC

VEE

VCC

GND

VINb

VIN

GND

35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51

13

2144A–BDC–04/02

Typical

Characterization

Results

Static Linearity

F_S= 50 MSPS/F_IN= 10 MHz

Figure 5. Integral Non Linearity

Note:

Clock Frequency = 50 MSPS; Signal Frequency = 10 MHz;

Positive peak: 0.78 lsb; Negative peak: -0.73 lsb

Figure 6. Differential Non Linearity

Note:

Clock Frequency = 50 MSPS; Signal Frequency = 10 MHz;

Positive peak: 0.3 lsb; Negative peak: -0.39 lsb

14

TS8388BF

2144A–BDC–04/02

TS8388BF

Effective Number

of Bits Versus

Power Supplies

Variation

Figure 7. Effective Number of Bits = f (V_EEA); F_S= 500 MSPS; F_IN= 100 MHz

8

7

6

5

4

3

2

1

0

-7

-6.5

-6

-5.5

-5

-4.5

-4

VEEA (V)

Figure 8. Effective Number of Bits = f (V_CC); F_S= 500 MSPS; F_IN= 100 MHz

8

7

6

5

4

3

2

1

0

3

3.5

4

4.5

5

5.5

6

6.5

7

VCC (V)

Figure 9. Effective Number of Bits = f (V_EED); F_S= 500 MSPS; F_IN= 100 MHz

8

7

6

5

4

3

2

1

0

-6

-5.5

-5

-4.5

-4

-3.5

-3

VEED (V)

15

2144A–BDC–04/02

Typical FFT Results

Figure 10. F_S= 1 GSPS; F_IN= 20 MHz

Figure 11. F_S= 1 GSPS; F_IN= 495 MHz

Figure 12. F_S= 1 GSPS; F_IN= 995 MHz (-3 dB Full Scale Input)

16

TS8388BF

2144A–BDC–04/02

TS8388BF

Spurious Free

Dynamic Range

Versus Input

Amplitude

Figure 13. Sampling Frequency: F_S= 1 GSPS; Input Frequency F_IN= 995 MHz; Full Scale; ENOB = 6.4;

SINAD = 40 dB; SNR = 44 dB; THD = -46 dBc; SFDR = -47 dBc; Gray or Binary Output Coding

Figure 14. Sampling Frequency: F_S= 1 GSPS; Input Frequency F_IN= 995 MHz; -3 dB Full Scale; ENOB = 6.6;

SINAD = 40.8 dB; SNR = 44 dB; THD = -48 dBc; SFDR = -50 dBc; Gray or Binary Output Coding

17

2144A–BDC–04/02

Dynamic

F_S= 1 GSPS, F_IN= 0 up to 1600 MHz, Full Scale input (F_S), F_S-3 dB

Performance

Versus Analog

Input Frequency

Clock duty cycle 50/50, Binary/Gray output coding, fully differential or single-ended analog and

clock inputs.

Figure 15. ENOB (dB)

8

7

6

5

4

-3 dB FS

FS

3

0

200

400

600

800

1000

1200

1400

1600

1800

Input frequency (MHz)

Figure 16. SNR (dB)

50

48

46

44

42

40

38

36

34

32

FS

-3 dB FS

30

0

800

1000

1400

1600

Input frequency (MHz)

Figure 17. SFDR (dBc)

-20

-25

-30

-35

-40

-45

-50

-55

FS

-3 dB FS

-60

0

800

1000

1400

1600

Input frequency (MHz)

18

TS8388BF

2144A–BDC–04/02

TS8388BF

Effective Number

of Bits (ENOB)

Versus Sampling

Frequency

Analog Input Frequency: F_IN= 495 MHz and Nyquist conditions (F_IN= F_S/2)

Clock duty cycle 50/50, Binary output coding

Figure 18. ENOB (dB)

8

FIN = FS/2

7

6

5

4

3

2

FIN = 500 MHz

0

200

400

600

800

1000

1200

1400

1600

Sampling frequency (MSPS)

SFDR Versus

Sampling

Frequency

Analog Input Frequency: F_IN= 495 MHz and Nyquist conditions (F_IN= F_S/2)

Clock duty cycle 50/50, Binary output coding

Figure 19. SFDR (dBc)

-20

-25

-30

-35

-40

-45

-50

-55

FIN = FS/2

FIN = 500 MHz

-60

0

200

400

600

800

1000

1200

1400

1600

Sampling frequency (MSPS)

19

2144A–BDC–04/02

TS8388BF ADC

Performances

Versus Junction

Temperature

Figure 20. Effective Number of Bits Versus Junction Temperature

F_S= 1 GSPS; F_IN= 500 MHz; Duty Cycle = 50%

8

7

6

5

4

3

-40

-20

0

20

40

60

80

100

120

140

160

Temperature (°C)

Figure 21. Signal to Noise Ratio Versus Junction Temperature

F_S= 1 GSPS; F_IN= 507 MHz; Differential Clock; Single-ended Analog Input (V_IN= -1 dBFs)

46

45

44

43

42

-60

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

Figure 22. Total Harmonic Distorsion Versus Junction Temperature

F_S= 1 GSPS; F_IN= 507 MHz; Differential Clock; Single-ended Analog Input (V_IN= -1 dBFs)

53

51

49

47

45

43

-60

-40

-20

0

20

40

60

80

100

120

Temperature (°C)

20

TS8388BF

2144A–BDC–04/02

TS8388BF

Figure 23. Power Consumption Versus Junction Temperature

F_S= 1 GSPS; F_IN= 500 MHz; Duty Cycle = 50%

5

4

3

2

1

0

-40

-20

0

20

40

60

80

100

120

140

160

Temperature (°C)

Typical Full Power

Input Bandwidth

Figure 24. 1.5 GHz at -3 dB (-2 dBm Full Power Input)

Frequency (MHz)

900

100

300

500

700

1100

1300

1500

1700

0

-1

-2

-3

-4

-5

-6

21

2144A–BDC–04/02

ADC Step

Response

Test pulse input characteristics: 20% to 80% input full scale and rise time ~ 200 ps.

Note: This step response was obtained with the TSEV8388B chip on-board (device in die form).

Figure 25. Test Pulse Digitized with 20 GHz DSO

Vpp ~ 260 mV

Tr ~ 240 ps

50 mV/div

500 ps/div

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Time (ns)

Figure 26. Same Test Pulse Digitized with TS8388BF ADC

200

150

Tr ~ 280 ps

50 codes/div (Vpp ~ 260 mV)

500 ps/div

100

ADC calculated rise time: between 150 and 200 ps

50

0

0.5

1.0

1.5

2.0

2.5

3.0

3.5

4.0

4.5

5.0

Time (ns)

Note:

Ripples are due to the test setup (they are present on both measurements).

22

TS8388BF

2144A–BDC–04/02

TS8388BF

TS8388BF Main

Features

Timing

Information

Timing Value for

TS8388BF

Timing values as defined in Table 3 on page 4 are advanced data, issued from electric simula-

tions and first characterizations results fitted with measurements.

Timing values are given at CQFP68 package inputs/outputs, taking into account package

internal controlled impedance traces propagation delays, gullwing pin model, and specified

termination loads.

Propagation delays in 50/75Ω impedance traces are NOT taken into account for TOD and

TDR.

Apply proper derating values corresponding to termination topology.

The min/max timing values are valid over the full temperature range in the following

conditions:

•

Specified Termination Load (Differential output Data and Data Ready):

50Ω resistor in parallel with 1 standard ECLinPS register from Motorola (i.e.: 10E452)

Typical ECLinPS inputs shows a typical input capacitance of 1.5 pF (including package

and ESD protections).

If addressing an output Dmux, take care if some Digital outputs do not have the same

termination load and apply corresponding derating value given below.

•

Output Termination Load derating values for TOD and TDR:

~ 35 ps/pF or 50 ps per additional ECLinPS load.

Propagation time delay derating values have also to be applied for TOD and TDR:

~ 6 ps/mm (155 ps/inch) for TSEV8388B Evaluation Board.

Apply proper time delay derating value if a different dielectric layer is used.

Propagation Time

Considerations

TOD and TDR Timing values are given from pin to pin and DO NOT include the additional

propagation times between device pins and input/output termination loads. For the

TSEV8388B Evaluation Board, the propagation time delay is 6 ps/mm (155 ps/inch) corre-

sponding to 3.4 (at 10 GHz) dielectric constant of the RO4003 used for the Board.

If a different dielectric layer is used (for instance Teflon), please use appropriate propagation

time values.

TD does NOT depend on propagation times because it is a differential data (TD is the time dif-

ference between Data Ready output delay and digital Data output delay).

TD is also the most straightforward data to measure, again because it is differential: TD can be

measured directly onto termination loads, with matched Oscilloscopes probes.

TOD-TDR Variation

Over Temperature

Values for TOD and TDR track each other over temperature (1% variation for TOD-TDR per

100°C temperature variation).

Therefore TOD-TDR variation over temperature is negligible. Moreover, the internal (on-chip)

and package skews between each Data TODs and TDR effect can be considered as

negligible.

23

2144A–BDC–04/02

Consequently, minimum values for TOD and TDR are never more than 100 ps apart. The

same is true for the TOD and TDR maximum values.

In other terms :

–

If TOD is at 1150 ps, TDR will not be at 1620 ps (maximum time delay for TDR).

If TOD is at 1660 ps, TDR will not be at 1110 ps (minimum time delay for TDR).

However, external TOD-TDR values may be dictated by total digital datas skews

between every TODs (each digital data) and TDR: MCM Board, bonding wires and

output lines lengths differences, and output termination impedance mismatches.

The external (on board) skew effect has NOT been taken into account for the specification of

the minimum and maximum values for TOD-TDR.

Principle of Operation

The Analog input is sampled on the rising edge of external clock input (CLK, CLKB) after TA

(aperture delay) of typically 250 ps. The digitized data is available after 4 clock periods latency

(pipeline delay (TPD)), on clock rising edge, after 1360 ps typical propagation delay TOD.

The Data Ready differential output signal frequency (DR, DRB) is half the external clock fre-

quency, that is it switches at the same rate as the digital outputs.

The Data Ready output signal (DR, DRB) switches on external clock falling edge after a prop-

agation delay TDR of typically 1320 ps.

A Master Asynchronous Reset input command DRRB (ECL compatible single-ended input) is

available for initializing the differential Data Ready output signal (DR, DRB). This feature is

mandatory in certain applications using interleaved ADCs or using a single ADC with demulti-

plexed outputs. Actually, without Data Ready signal initialization, it is impossible to store the

output digital datas in a defined order.

Principle of Data

Ready Signal

Control by DRRB

Input Command

Data Ready Output

Signal Reset

The Data Ready signal is reset on falling edge of DRRB input command, on ECL logical low

level (-1.8V). DRRB may also be tied to V_EE= -5V for Data Ready output signal Master Reset.

So long DRRB remains at logical low level, (or tied to V_EE= -5V), the Data Ready output

remains at logical zero and is independant of the external free running encoding clock.

The Data Ready output signal (DR, DRB) is reset to logical zero after TRDR = 920 ps typical.

TRDR is measured between the -1.3V point of the falling edge of DRRB input command and

the zero crossing point of the differential Data Ready output signal (DR, DRB).

The Data Ready Reset command may be a pulse of 1 ns minimum time width.

24

TS8388BF

2144A–BDC–04/02

TS8388BF

Data Ready Output

Signal Restart

The Data Ready output signal restarts on DRRB command rising edge, ECL logical high levels

(-0.8V). DRRB may also be Grounded, or is allowed to float, for normal free running Data

Ready output signal.

The Data Ready signal restart sequence depends on the logical level of the external encoding

clock, at DRRB rising edge instant:

•

The DRRB rising edge occurs when external encoding clock input (CLK, CLKB) is LOW:

The Data Ready output first rising edge occurs after half a clock period on the clock falling

edge, after a delay time TDR = 1320 ps already defined hereabove.

•

The DRRB rising edge occurs when external encoding clock input (CLK, CLKB) is HIGH:

The Data Ready output first rising edge occurs after one clock period on the clock falling

edge, and a delay TDR = 1320 ps.

Consequently, as the analog input is sampled on clock rising edge, the first digitized data cor-

responding to the first acquisition (N) after Data Ready signal restart (rising edge) is always

strobed by the third rising edge of the data ready signal.

The time delay (TD1) is specified between the last point of a change in the differential output

data (zero crossing point) to the rising or falling edge of the differential Data Ready signal (DR,

DRB) (zero crossing point).

For normal initialization of Data Ready output signal, the external encoding clock signal fre-

quency and level must be controlled. It is reminded that the minimum encoding clock sampling

rate for the ADC is 10 MSPS and consequently the clock cannot be stopped.

One single pin is used for both DRRB input command and die junction temperature monitor-

ing. Pin denomination will be DRRB/DIOD. On the former version denomination was DIOD.

Temperature monitoring and Data Ready control by DRRB is not possible simultaneously.

Analog Inputs (V_IN)

The analog input Full Scale range is 0.5V peak to peak (Vpp), or -2 dBm into the 50Ω termina-

tion resistor.

(V_INB

)

In differential mode input configuration, that means 0.25V on each input, or ±125 mV around

0V. The input common mode is GROUND.

The typical input capacitance is 3 pF for TS8388B in CQFP package.

The input capacitance is mainly due to the package. The ESD protections are not connected

(but present) on the inputs.

Differential Inputs

Voltage Span

Figure 27. Differiential Inputs Voltage Span

[mV]

VIN

VINB

125

500 mV

Full Scale

250 mV

-250 mV

0V

analog input

-125

t

(VIN, VINB) = ±250 mV = 500 mV diff

25

2144A–BDC–04/02

Differential Versus

Single-ended Analog

Input Operation

The TS8388BF can operate at full speed in either differential or single-ended configuration.

This is explained by the fact the ADC uses a high input impedance differential preamplifier

stage, (preceeding the Sample and hold stage), which has been designed in order to be

entered either in differential mode or single-ended mode.

This is true so long as the out-of-phase analog input pin V_INBis 50Ω terminated very closely to

one of the neighboring shield ground pins (52, 53, 58, 59) which constitute the local ground

reference for the inphase analog input pin (V_IN).

Thus the differential analog input preamplifier will fully reject the local ground noise (and any

capacitively and inductively coupled noise) as common mode effects.

In typical single-ended configuration, enter on the (V_IN) input pin, with the inverted phase input

pin (V_INB) grounded through the 50Ω termination resistor.

In single-ended input configuration, the in-phase input amplitude is 0.5V peak to peak, cen-

tered on 0V (or -2 dBm into 50Ω). The inverted phase input is at ground potential through the

50Ω termination resistor.

However, dynamic performances can be somewhat improved by entering either analog or

clock inputs in differential mode.

Typical Single-ended

Analog Input

Configuration

Figure 28. Typical Single-ended Analog Input Configuration

[mV]

VIN or VINB double pad (pins 54, 55 or 56, 57)

VIN or VINB

VIN

250

500 mV

Full Scale

VINB = 0V

1 MΩ

3 pF

50Ω

(external)

analog input

VINB

-250

t

VIN = ±250 mV = 500 mV diff

50Ω reverse termination

Clock Inputs (CLK)

(CLKB)

The TS8388BF can be clocked at full speed without noticeable performance degradation in

either differential or single-ended configuration.

This is explained by the fact the ADC uses a differential preamplifier stage for the clock buffer,

which has been designed in order to be entered either in differential or single-ended mode.

Recommended sinewave generator characteristics are typically -120 dBc/Hz phase noise floor

spectral density, at 1 kHz from carrier, assuming a single tone 4 dBm input for the clock signal.

Single-ended Clock

Input (Ground

Common Mode)

Although the clock inputs were intended to be driven differentially with nominal -0.8V/-1.8V

ECL levels, the TS8388BF clock buffer can manage a single-ended sinewave clock signal

centered around 0V. This is the most convenient clock input configuration as it does not

require the use of a power splitter.

No performance degradation (i.e.: due to timing jitter) is observed in this particular single-

ended configuration up to 1.2 GSPS Nyquist conditions (F_IN= 600 MHz).

26

TS8388BF

2144A–BDC–04/02

TS8388BF

This is true so long as the inverted phase clock input pin is 50Ω terminated very closely to one

of the neighboring shield ground pins, which constitutes the local Ground reference for the

inphase clock input.

Thus the TS8388BF differential clock input buffer will fully reject the local ground noise (and

any capacitively and inductively coupled noise) as common mode effects. Moreover, a very

low phase noise sinewave generator must be used for enhanced jitter performance.

The typical inphase clock input amplitude is 1V peak to peak, centered on 0V (ground) com-

mon mode. This corresponds to a typical clock input power level of 4 dBm into the 50Ω

termination resistor. Do not exceed 10 dBm to avoid saturation of the preamplifier input

transistors.

The inverted phase clock input is grounded through the 50Ω termination resistor.

Figure 29. Single-ended Clock Input (Ground common mode):

VCLK Common Mode = 0V; VCLKB = 0V; 4 dBm Typical Clock Input Power Level (into 50Ω termination resistor)

CLK or CLKB double pad (pins 37, 38 or 39, 40)

[V]

VCLK

+0.5V

CLK or CLKB

1 MΩ

0.4 pF

50Ω

(external)

VCLK = 0V

VCLK

-0.5V

t

50Ω reverse termination

Note:

Do not exceed 10 dBm into the 50Ω termination resistor for single clock input power level.

Differential ECL Clock

Input

The clock inputs can be driven differentially with nominal -0.8V/-1.8V ECL levels.

In this mode, a low phase noise sinewave generator can be used to drive the clock inputs, fol-

lowed by a power splitter (hybrid junction) in order to obtain 180 degrees out of phase

sinewave signals. Biasing tees can be used for offseting the common mode voltage to ECL

levels.

Note: As the biasing tees propagation times are not matching, a tunable delay line is required

in order to ensure the signals to be 180 degrees out of phase especially at fast clock rates in

the GSPS range.

Figure 30. Differential Clock Inputs (ECL Levels)

[mV]

CLK or CLKB double pad (pins 37, 38 or 39, 40)

CLK or CLKB

VCLK

-0.8V

VCLKB

1 MΩ

0.4 pF

Common mode = -1.3V

50Ω

(external)

-2V

-1.8V

t

50Ω reverse termination

27

2144A–BDC–04/02

Single-ended ECL

Clock Input

In single-ended configuration enter on CLK (resp. CLKB) pin, with the inverted phase Clock

input pin CLKB (respectively CLK) connected to -1.3V through the 50Ω termination resistor.

The inphase input amplitude is 1V peak to peak, centered on -1.3V common mode.

Figure 31. Single-ended Clocl Input (ECL):

VCLK Common Mode = -1.3V; VCLKB = -1.3V

[V]

VCLK

-0.8V

-1.8V

VCLKB = -1.3V

t

Noise Immunity

Information

Circuit noise immunity performance begins at design level.

Efforts have been made on the design in order to make the device as insensitive as possible

to chip environment perturbations resulting from the circuit itself or induced by external cir-

cuitry (Cascode stages isolation, internal damping resistors, clamps, internal (on-chip)

decoupling capacitors).

Furthermore, the fully differential operation from analog input up to the digital outputs provides

enhanced noise immunity by common mode noise rejection.

Common mode noise voltage induced on the differential analog and clock inputs will be can-

celed out by these balanced differential amplifiers.

Moreover, proper active signals shielding has been provided on the chip to reduce the amount

of coupled noise on the active inputs.

The analog inputs and clock inputs of the TS8388BF device have been surrounded by ground

pins, which must be directly connected to the external ground plane.

Digital Outputs

The TS8388BF differential output buffers are internally 75Ω loaded. The 75Ω resistors are

connected to the digital ground pins through a -0.8V level shift diode (see Figure 32, Figure

33, Figure 34 on page 30).

The TS8388BF output buffers are designed for driving 75Ω (default) or 50Ω properly termi-

nated impedance lines or coaxial cables. An 11 mA bias current flowing alternately into one of

the 75Ω resistors when switching ensures a 0.825V voltage drop across the resistor (untermi-

nated outputs).

The V_PLUSDpositive supply voltage allows the adjustment of the output common mode level

from -1.2V (V_PLUSD= 0V for ECL output compatibility) to +1.2V (V_PLUSD= 2.4V for LVDS output

compatibility).

Therefore, the single-ended output voltages vary approximately between -0.8V and -1.625V,

(outputs unterminated), around -1.2V common mode voltage.

28

TS8388BF

2144A–BDC–04/02

TS8388BF

Three possible line driving and back-termination scenarios are proposed (assuming V_PLUSD

0V):

=

1. 75Ω impedance transmission lines, 75Ω differentially terminated (Figure 32):

Each output voltage varies between -1V and -1.42V (respectively +1.4V and +1V), leading

to ±0.41V = 0.825V in differential, around -1.21V (respectively +1.21V) common mode for

V_PLUSD= 0V (respectively 2.4V).

2. 50Ω impedance transmission lines, 50Ω differentially termination (Figure 33):

Each output voltage varies between -1.02V and -1.35V (respectively +1.38V and +1.05V),

leading to ±0.33V = 660 mV in differential, around -1.18V (respectively +1.21V) common

mode for V_PLUSD= 0V (respectively 2.4V).

3. 75Ω impedance open transmission lines (Figure 34):

Each output voltage varies between -1.6V and -0.8V (respectively +0.8V and +1.6V),

which are true ECL levels, leading to ±0.8V = 1.6V in differential, around -1.2V (respec-

tively +1.2V) common mode for V_PLUSD= 0V (respectively 2.4V). Therefore, it is possible

to drive directly high input impedance storing registers, without terminating the 75Ω trans-

mission lines. In time domain, that means that the incident wave will reflect at the 75Ω

transmission line output and travel back to the generator (i.e.: the 75Ω data output buffer).

As the buffer output impedance is 75Ω, no back reflection will occur.

Note: This is no longer true if a 50Ω transmission line is used, as the latter is not matching the

buffer 75Ω output impedance.

Each differential output termination length must be kept identical. It is recommended to decou-

ple the midpoint of the differential termination with a 10 nF capacitor to avoid common mode

perturbation in case of slight mismatch in the differential output line lengths.

Too large mismatches (keep < a few mm) in the differential line lengths will lead to switching

currents flowing into the decoupling capacitor leading to switching ground noise.

The differential output voltage levels (75Ω or 50Ω termination) are not ECL standard voltage

levels, however it is possible to drive standard logic ECL circuitry like the ECLinPS logic line

from Motorola^®.

At sampling rates exceeding 1 GSPS, it may be difficult to trigger the HP16500 or any other

Acquisition System with digital outputs. It becomes necessary to regenerate digital data and

Data Ready by means of external amplifiers, in order to be able to test the TS8388BF at its

optimum performance conditions.

29

2144A–BDC–04/02

Differential Output Loading Configurations (Levels for ECL Compatibility)

Figure 32. Differential Output: 75Ω Terminated

VPLUSD = 0V

-0.8V

Out

-1V/-1.41V

75Ω

Differential output:

+0.41V = 0.825V

75Ω

Common mode level: -1.2V

(-1.2V below VPLUSD level)

75Ω

impedance

10 nF

+

-

OutB -1.41V/-1V

11 mA

DVEE

Figure 33. Differential Output: 50Ω Terminated

VPLUSD = 0V

-0.8V

Out

-1.02V/-1.35V

75Ω

50Ω

Differential output:

+0.33V = 0.660V

50Ω

Common mode level: -1.2V

(-1.2V below VPLUSD level)

50Ω

impedance

10 nF

+

-

OutB -1.35V/-1.02V

11 mA

DVEE

Figure 34. Differential Output: Open Loaded

VPLUSD = 0V

-0.8V

Out

-0.8V/-1.6V

75Ω

Differential output:

+0.8V = 1.6V

75Ω

Common mode level: -1.2V

(-1.2V below VPLUSD level)

75Ω

impedance

+

-

OutB -1.6V/-0.8V

11 mA

DVEE

30

TS8388BF

2144A–BDC–04/02

TS8388BF

Differential Output Loading Configurations (Levels for LVDS Compatibility)

Figure 35. Differential Output: 75Ω Terminated

VPLUSD = 2.4V

1.6V

Out

1.4V/0.99V

75Ω

Differential output:

+0.41V = 0.825V

75Ω

Common mode level: -1.2V

(-1.2V below VPLUSD level)

75Ω

impedance

10 nF

+

-

OutB 0.99V/1.4V

11 mA

DVEE

Figure 36. Differential Output: 50Ω Terminated

VPLUSD = 2.4V

1.6V

Out

1.38V/1.05V

75Ω

50Ω

Differential output:

+0.33V = 0.660V

50Ω

Common mode level: -1.2V

(-1.2V below VPLUSD level)

50Ω

impedance

10 nF

+

-

OutB 1.05V/1.38V

11 mA

DVEE

Figure 37. Differential Output: Open Loaded

VPLUSD = 2.4V

1.6V

Out

1.6V/0.8V

75Ω

Differential output:

+0.8V = 1.6V

75Ω

Common mode level: -1.2V

(-1.2V below VPLUSD level)

75Ω

impedance

+

-

OutB 0.8V/1.6V

11 mA

DVEE

31

2144A–BDC–04/02

Out of Range Bit

An Out of Range (OR, ORB) bit is provided that goes to logical high state when the input

exceeds the positive full scale or falls below the negative full scale.

When the analog input exceeds the positive full scale, the digital output datas remain at high

logical state, with (OR, ORB) at logical one.

When the analog input falls below the negative full scale, the digital outputs remain at logical

low state, with (OR, ORB) at logical one again.

Gray or Binary

Output Data

Format Select

The TS8388BF internal regeneration latches indecision (for inputs very close to latches

threshold) may produce errors in the logic encoding circuitry and leading to large amplitude

output errors.

This is due to the fact that the latches are regenerating the internal analog residues into logical

states with a finite voltage gain value (Av) within a given positive amount of time ∆(t):

Av = exp(∆(t)/τ), with τ the positive feedback regeneration time constant.

The TS8388BF has been designed for reducing the probability of occurrence of such errors to

approximately 10^-13(targeted for the TS8388BF at 1 GSPS).

A standard technique for reducing the amplitude of such errors down to ± 1 lsb consists of out-

putting the digital datas in Gray code format. Though the TS8388BF has been designed for

featuring a Bit Error Rate of 10^-13with a binary output format, it is possible for the user to

select between the Binary or Gray output data format, in order to reduce the amplitude of such

errors when occurring, by storing Gray output codes.

Digital Datas format selection:

•

BINARY output format if GORB is floating or V_CC

.

GRAY output format if GORB is connected to ground (0V).

Diode Pin 49

One single pin is used for both DRRB input command and die junction monitoring. The pin

denomination is DRRB/DIOD. Temperature monitoring and Data Ready control by DRRB is

not possible simultaneously.

(See “Principle of Data Ready Signal Control by DRRB Input Command” on page 24 for Data

Ready Reset input command).

The operating die junction temperature must be kept below 145°C, therefore an adequate

cooling system has to be set up. The diode mounted transistor measured Vbe value versus

junction temperature is given below.

Figure 38. Diode Pin 49

1000

960

920

880

840

800

760

720

680

640

600

-55

-35

-15

5

25

45

65

85

105

125

Junction temperature (°C)

32

TS8388BF

2144A–BDC–04/02

TS8388BF

ADC Gain Control

Pin 60

The ADC gain is adjustable by the means of the pin 60 (input impedance is 1 MΩ in parallel

with 2 pF).

The gain adjust transfer function is given below.

Figure 39. ADC Gain Control Pin 60

1.20

1.15

1.10

1.05

1.00

0.95

0.90

0.85

0.80

-500

-400

-300

-200

-100

0

100

200

300

400

500

Vgain (command voltage) (mV)

Note:

For more information, please refer to the document "DEMUX and ADCs Application Notes".

33

2144A–BDC–04/02

Equivalent

Input/Output

Schematics

Figure 40. Equivalent Analog Input Circuit and ESD Protections

VCC = +5V

VCC

VCLAMP = +2.4V

-0.8V

-5.8V

GND

GND = 0V

-5.8V

+1.65V

50Ω

E21V

VEE

200Ω

VIN

VINB

Pad

capacitance

340 fF

Pad

capacitance

340 fF

5.8V

0.8V

-1.55V

0.8V

E21G

VEE = -5V

Note:

The ESD protection equivalent capacitance is 150 fF.

Figure 41. Equivalent Analog Clock Input Circuit and ESD Protections

VCC

VCC = +5V

+0.8V

-5.8V

-0.8V

-5.8V

GND = 0V

-5.8V

VEE

E31V

150Ω

CLK

CLKB

Pad

capacitance

340 fF

Pad

capacitance

340 fF

5.8V

0.8V

380 µA

0.8V

E21G

VEE = -5V

Note:

The ESD protection equivalent capacitance is 150 fF.

34

TS8388BF

2144A–BDC–04/02

TS8388BF

Figure 42. Equivalent Data Output Buffer Circuit and ESD Protections

VPLUSD = 0V to 2.4V

-5.8V

E01V

VEE

OUT

OUTB

5.8V

Pad

capacitance

180 fF

Pad

capacitance

180 fF

0.8V

DVEE = -5V

E21GA

VEE = -5V

Note:

The ESD protection equivalent capacitance is 150 fF.

Figure 43. ADC Gain Adjust Equivalent Analog Input Circuit and ESD Protections

VCC = +5V

GND

-0.8V

+0.8V

NP1032C2

-5.8V

E22V

1 kΩ

GA

Pad

capacitance

180 fF

0.8V

2 pF

0.8V

5.8V

GND

500 µA

E22GA

VEE

VEE = -5V

Note:

The ESD protection equivalent capacitance is 150 fF.

35

2144A–BDC–04/02

Figure 44. GORB Equivalent Input Schematic and ESD Protections

GORB: Gray or Binary Select Input; Floating or Tied to VCC -> Binary

VCC = +5V

-0.8V

-5.8V

1 kΩ

E21VA

VEE

5 kΩ

GORB

Pad

capacitance

180 fF

5.8V

250 µA

E31G

VEE = -5V

GND = 0V

Note:

The ESD protection equivalent capacitance is 150 fF.

Figure 45. DRRB Equivalent Input Schematic and ESD Protections

Actual Protection Range: 6.6V above VEE, in fact stress above GND are clipped by the CB diode used for Tj monitoring

VCC = +5V

GND=0V

NP1032C2

10 kΩ

200Ω

DRRB

-1.3V

Pad

capacitance

180 fF

-2.6V

5.8V

0.8V

E21G

VEE

VEE = -5V

Note:

The ESD protection equivalent capacitance is 150 fF.

36

TS8388BF

2144A–BDC–04/02

TS8388BF

TSEV8388BF:

Device

For complete specification, see separate TSEV8388B document.

Evaluation

Board

General

Description

The TSEV8388BF Evaluation Board (EB) is a board which has been designed in order to facil-

itate the evaluation and the characterization of the TS8388BF device up to its 1.5 GHz full

power bandwidth at up to 1 GSPS in the military temperature range.

The high speed of the TS8388BF requires careful attention to circuit design and layout to

achieve optimal performance.

This four metal layer board with internal ground plane has the adequate functions in order to

allow a quick and simple evaluation of the TS8388BF ADC performances over the tempera-

ture range.

The TSEV8388BF Evaluation Board is very straightforward as it only implements the

TS8388BF ADC, SMA connectors for input/output accesses and a 2.54 mm pitch connector

compatible with HP16500C high frequency probes.

The board also implements a de-embedding fixture in order to facilitate the evaluation of the

high frequency insertion loss of the input microstrip lines, and a die junction temperature mea-

surement setting.

The board is constituted by a sandwich of two dielectric layers, featuring low insertion loss and

enhanced thermal characteristics for operation in the high frequency domain and extended

temperature range.

The board dimensions are 130 mm x 130 mm.

The board set comes fully assembled and tested, with the TS8388BF in CQFP68 package

installed.

37

2144A–BDC–04/02

Nominal CQFP68

Thermal

Although the power dissipation is low for this performance, the use of a heat sink is

mandatory.

Characteristics

The user will find some advice on this topics below.

Thermal Resistance

from Junction to

Ambient: RTHJA

The following table lists the converter thermal performance parameters, with or without

heatsink.

For the following measurements, a 50 x 50 x 16 mm heatsink has been used (see Figure 47

on page 39).

Table 8. Thermal Resitance

ja Thermal Resistance (°C/W)

CQFP68 on Board

Air Flow

(m/s)

0

Estimated – Without Heatsink

Targeted – With Heatsink⁽¹⁾

50

40

10

0.5

1

8.9

7.9

7.3

6.8

6.5

6.2

5.8

5.6

35

1.5

2

32

30

2.5

3

28

26

4

24

5

23.5

Note:

1. Heatsink is glued to backside of package or screwed and pressed with thermal grease.

Figure 46. Thermal Resistance from Junction to Ambient: Rthja

60

50

40

30

Without heatsink

20

10

0

With heatsink

4 5

0

1

2

3

Air flow (m/s)

38

TS8388BF

2144A–BDC–04/02

TS8388BF

Thermal Resistance

from Junction to

Case: RTHJC

Typical value for Rthjc is given to 4.75°C/W.

CQFP68 Board

Assembly

Figure 47. CQFP68 Board Assembly with a 50 x 50 x 16 mm External Heatsink

28.96

24.13

Printed circuit

Aluminum heatsink

1.4

4.0

15.0

Interface: Af-filled epoxy or thermal

conductive grease - 100 µm max.

2.5

16.0

1.3 3.2

50.0

39

2144A–BDC–04/02

Enhanced CQFP68

Thermal

Characteristics

Enhanced CQFP68

The CQFP68 has been modified, in order to improve the thermal characteristics:

•

A CuW heatspreader has been added at the bottom of the package.

The die has been electrically isolated with the ALN substrate.

Thermal Resistance

from Junction to

Case: RTHJC

Typical value for Rthjc is given to 1.56°C/W.

This value does not include thermal contact resistance between package and external compo-

nent (heatsink or PCBoard).

As an example, 2.0°C/W can be taken for 50 µm of thermal grease.

Heatsink

It is recommended to use an external heatsink, or PCBoard special design.

The stand off has been calculated to permit the simultaneous soldering of the leads and of the

heatspreader with the solder paste.

Figure 48. Enhanced CQFP68 Suggested Assembly

28.78

24.13

Printed

circuit board

CuW heatspreader

Thermal via

Solid ground plane

Cooling system efficiency can be monitored using the Temperature Sensing Diode, integrated

in the device.

40

TS8388BF

2144A–BDC–04/02

TS8388BF

Definitions

Definition of

Terms

(BER) Bit Error Rate

Probability to exceed a specified error threshold for a sample. An error code is a code that dif-

fers by more than ± 4 lsb from the correct code.

(FPBW) Full Power

Input Bandwidth

Analog input frequency at which the fundamental component in the digitally reconstructed out-

put has fallen by 3 dB with respect to its low frequency value (determined by FFT analysis) for

input at Full Scale.

(SINAD) Signal to Noise

and Distortion Ratio

Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS

sum of all other spectral components, including the harmonics except DC.

(SNR) Signal to Noise

Ratio

Ratio expressed in dB of the RMS signal amplitude, set to 1 dB below Full Scale, to the RMS

sum of all other spectral components excluding the five first harmonics.

(THD) Total Harmonic

Distorsion

Ratio expressed in dBc of the RMS sum of the first five harmonic components, to the RMS

value of the measured fundamental spectral component.

(SFDR) Spurious Free

Dynamic Range

Ratio expressed in dB of the RMS signal amplitude, set at 1 dB below Full Scale, to the RMS

value of the next highest spectral component (peak spurious spectral component). SFDR is

the key parameter for selecting a converter to be used in a frequency domain application

(Radar systems, digital receiver, network analyzer, etc.). It may be reported in dBc (i.e.:

degrades as signal levels is lowered), or in dBFS (i.e.: always related back to converter full

scale).

(ENOB) Effective

Number Of Bits

SINAD - 1.76 + 20 log (A/V/2)

ENOB =

6.02

Where A is the actual input amplitude and V is the full scale range of the ADC under test.

(DNL) Differential Non

Linearity

The Differential Non Linearity for an output code i is the difference between the measured step

size of code i and the ideal LSB step size. DNL (i) is expressed in LSBs. DNL is the maximum

value of all DNL (i). DNL error specification of less than 1 lsb guarantees that there are no

missing output codes and that the transfer function is monotonic.

(INL) Integral Non

Linearity

The Integral Non Linearity for an output code i is the difference between the measured input

voltage at which the transition occurs and the ideal value of this transition.

INL (i) is expressed in LSBs, and is the maximum value of all |INL (i)|.

(DG) Differential Gain

(DP) Differential Phase

(TA) Aperture Delay

The peak gain variation (in percent) at five different DC levels for an AC signal of 20% Full

Scale peak to peak amplitude. F_IN= 5 MHz (TBC).

Peak Phase variation (in degrees) at five different DC levels for an AC signal of 20% Full

Scale peak to peak amplitude. F_IN= 5 MHz (TBC).

Delay between the rising edge of the differential clock inputs (CLK, CLKB) (zero crossing

point), and the time at which (V_IN, V_INB) is sampled.

41

2144A–BDC–04/02

(JITTER) Aperture

Uncertainty

Sample to sample variation in aperture delay. The voltage error due to jitter depends on the

slew rate of the signal at the sampling point.

(TS) Settling Time

Time delay to achieve 0.2% accuracy at the converter output when a 80% Full Scale step

function is applied to the differential analog input.

(ORT) Overvoltage

Recovery Time

Time to recover 0.2% accuracy at the output, after a 150% full scale step applied on the input

is reduced to midscale.

(TOD) Digital Data

Output Delay

Delay from the falling edge of the differential clock inputs (CLK, CLKB) (zero crossing point) to

the next point of change in the differential output data (zero crossing) with specified load.

(TD1) Time Delay from

Data to Data Ready

Time delay from Data transition to Data ready.

(TD2) Time Delay from

Data Ready to Data

General expression is TD1 = TC1 + TDR - TOD with TC = TC1 + TC2 = 1 encoding clock

period.

(TC) Encoding Clock

Period

TC1 = Minimum clock pulse width (high) TC = TC1 + TC2

TC2 = Minimum clock pulse width (low)

(TPD) Pipeline Delay

Number of clock cycles between the sampling edge of an input data and the associated output

data being made available, (not taking in account the TOD). For the TS8388BF the TPD is 4

clock periods.

(TRDR) Data Ready

Reset Delay

Delay between the falling edge of the Data Ready output asynchronous Reset signal (DDRB)

and the reset to digital zero transition of the Data Ready output signal (DR).

(TR) Rise Time

(TF) Fall Time

Time delay for the output DATA signals to rize from 20% to 80% of delta between low level

and high level.

Time delay for the output DATA signals to fall from 80% to 20% of delta between low level and

high level.

(PSRR) Power Supply

Rejection Ratio

Ratio of input offset variation to a change in power supply voltage.

(NRZ) Non Return to

Zero

When the input signal is larger than the upper bound of the ADC input range, the output code

is identical to the maximum code and the Out of Range bit is set to logic one. When the input

signal is smaller than the lower bound of the ADC input range, the output code is identical to

the minimum code, and the Out of range bit is set to logic one. (It is assumed that the input sig-

nal amplitude remains within the absolute maximum ratings).

(IMD) InterModulation

Distortion

The two tones intermodulation distortion (IMD) rejection is the ratio of either input tone to the

worst third order intermodulation products. The input tones levels are at -7 dB Full Scale.

(NPR) Noise Power

Ratio

The NPR is measured to characterize the ADC performance in response to broad bandwidth

signals. When using a notch-filtered broadband white-noise generator as the input to the ADC

under test, the Noise Power Ratio is defined as the ratio of the average out-of-notch to the

average in-notch power spectral density magnitudes for the FFT spectrum of the ADC output

sample test.

42

TS8388BF

2144A–BDC–04/02

TS8388BF

Ordering

Information

Package Device

TS 8388B

M

F

B/Q

Manufacturer prefix

Device or family

Screening Level

__: Standard

B/Q: Mil-PRF-38535, QML level Q

Space: according to ESA/scc 9000

Package:

Temperature Range:

M: -55°C < Tc; Tj < 125°C

V: -40°C < Tc < 110°C

C: 0°C < Tc < 90°C

F: CQFP68 gullwing

FS: Enhanced CQFP68 with

heatspreader

Evaluation Board

TS

EV 8388B F

ZA2

ZA2: with MC100EL16

digital recivers

__: No receivers

CQFP68 package

Evaluation board

prefix

The evaluation board is delivered with an ADC and includes the heat sink.

43

2144A–BDC–04/02

Outline

Figure 49. Package Dimension – 68-lead Ceramic Quad Flat Pack (CQFP)

Dimensions

TOP VIEW

0.8 BCS

20.32 BSC

0.050 BCS

1.27 BSC

Pin N° 1 index

CQFP 68

0.950 ± 0.006

24.13 ± 0.152

1.133 - 1.147

28.78 - 29.13

0.027 - 0.037

0.70 - 0.95

0.005 - 0.010

0.13 - 0.25

44

TS8388BF

2144A–BDC–04/02

TS8388BF

Figure 50. Package Dimension – 68-lead Enhanced CQFP with Heatspreder

TOP VIEW

0.8 BCS

20.32 BSC

0.050 BCS

1.27 BSC

Pin N° 1 index

CQFP 68

0.950 ± 0.006

24.13 ± 0.152

1.133 - 1.147

28.78 - 29.13

0.027 - 0.037

0.70 - 0.95

0.005 - 0.010

0.13 - 0.25

45

2144A–BDC–04/02

Datasheet

Status

Description

Table 9. Datasheet Status

Datasheet Status

Validity

Objective specification

This datasheet contains target and

goal specifications for discussion with

customer and application validation.

Before design phase

Target specification

This datasheet contains target or

goal specifications for product

development.

Valid during the design phase

Preliminary specification

α-site

This datasheet contains preliminary

data. Additional data may be

published later; could include

simulation results.

Valid before characterization

phase

Preliminary specification

β-site

This datasheet contains also

characterization results.

Valid before the

industrialization phase

Product specification

This datasheet contains final product

specification.

Valid for production purposes

Limiting Values

Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress

above one or more of the limiting values may cause permanent damage to the device. These are

stress ratings only and operation of the device at these or at any other conditions above those given in

the Characteristics sections of the specification is not implied. Exposure to limiting values for extended

periods may affect device reliability.

Application Information

Where application information is given, it is advisory and does not form part of the specification.

Life Support

Applications

These products are not designed for use in life support appliances, devices or systems where

malfunction of these products can reasonably be expected to result in personal injury. Atmel

customers using or selling these products for use in such applications do so at their own risk

and agree to fully indemnify Atmel for any damages resulting from such improper use or sale.

46

TS8388BF

2144A–BDC–04/02

Atmel Headquarters

Atmel Operations

Corporate Headquarters

2325 Orchard Parkway

San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 487-2600

Memory

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74025 Heilbronn, Germany

TEL (49) 71-31-67-0

FAX (49) 71-31-67-2340

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San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

Europe

Microcontrollers

Atmel Sarl

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San Jose, CA 95131

TEL 1(408) 441-0311

FAX 1(408) 436-4314

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TEL 1(719) 576-3300

Route des Arsenaux 41

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Switzerland

FAX 1(719) 540-1759

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FAX 1(719) 540-1759

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FAX (81) 3-3523-7581

Scottish Enterprise Technology Park

Maxwell Building

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TEL (44) 1355-803-000

FAX (44) 1355-242-743

e-mail

literature@atmel.com

Web Site

http://www.atmel.com

Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty

which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors

which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does

not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted

by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical

components in life support devices or systems.

ATMEL^®is the registered trademark of Atmel.

Motorola^®is the registered trademark of Motorola Company.

Other terms and product names may be the trademark of others.

Printed on recycled paper.

2144A–BDC–04/02


型号：	TS8388BMFSB/QQC1
厂家：	ATMEL
描述：	ADC, Proprietary Method, 8-Bit, 1 Func, 1 Channel, Parallel, 8 Bits Access, Bipolar, CQFP68, CERAMIC, QFP-68 ATM 异步传输模式转换器
文件：	总47页 (文件大小：1043K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TS8388BMFSB/QQC1 [ATMEL]

相关型号：

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TS8388BVFS9NB1ZB9

TS8388BVFS9QB1ZB9

TS8388BVFS9QB3ZB9

TS8388BVFS9QC1ZB9

TS8388BVFS9QC2ZB9

TS8388BVFS9QC3ZB9

TS8388BVFSB/Q

TS8388BVGL

TS83C194