TS83C51U2ZZZ-VIAD [ATMEL]
Microcontroller, 8-Bit, MROM, 40MHz, CMOS, PDIP40, PLASTIC, DIP-40;
| 型号： | TS83C51U2ZZZ-VIAD |
| 厂家： | 
ATMEL |
| 描述： | Microcontroller, 8-Bit, MROM, 40MHz, CMOS, PDIP40, PLASTIC, DIP-40 时钟 ATM 异步传输模式 微控制器 光电二极管 外围集成电路 |
| 文件： | 总67页 (文件大小：1073K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TS80C51U2
TS83C51U2
TS87C51U2
Double UART 8-bit CMOS Microcontroller
1. Description
TS80C51U2 is high performance CMOS ROM, OTP The fully static design of the TS80C51U2 allows to
and EPROM versions of the 80C51 CMOS single chip reduce system power consumption by bringing the clock
8-bit microcontroller.
frequency down to any value, even DC, without loss of
data.
The TS80C51U2 retains all features of the 80C51 with
extended ROM/EPROM capacity (16 Kbytes), 256 bytes The TS80C51U2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
of internal RAM, a 7-source , 4-level interrupt system,
an on-chip oscilator and three timer/counters.
In addition, the TS80C51U2 has a second UART,
enhanced functions on both UART, enhanced timer 2,
a hardware watchdog timer, a dual data pointer, a baud
rate generator and a X2 speed improvement mechanism.
2. Features
● 80C52 Compatible
● Asynchronous port reset
● Interrupt Structure with
•
•
•
•
8051 pin and instruction compatible
Four 8-bit I/O ports
•
•
7 Interrupt sources
4 level priority interrupt system
Three 16-bit timer/counters
256 bytes scratchpad RAM
● Full duplex Enhanced UARTs
•
•
Framing error detection
● High-Speed Architecture
Automatic address recognition
•
•
40 MHz @ 5V, 30MHz @ 3V
● Low EMI (inhibit ALE)
● Power Control modes
X2 Speed Improvement capability (6 clocks/
machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
•
•
•
Idle mode
Power-down mode
Power-off Flag
● Second UART
● Baud Rate Generator
● Dual Data Pointer
● Once mode (On-chip Emulation)
● Power supply: 4.5-5.5V, 2.7-5.5V
● On-chip ROM/EPROM (16K-bytes)
● Temperature ranges: Commercial (0 to 70oC) and
● Programmable Clock Out and Up/Down Timer/
Industrial (-40 to 85oC)
Counter 2
● Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44
● Hardware Watchdog Timer (One-time enabled with
(window), CDIL40 (window)
Reset-Out)
3. The second UART
In this document, UART_0 will make reference to the The second UART (UART_1) can be seen as an alternate
first UART (present in all Atmel Wireless function of Port 1 (P1.2 or P1.6 for RXD1 and P1.3 or
&
Microcontrollers C51 derivatives) and UART_1 will P1.7 for TXD1) or can be connected to (pin6 or pin12)
make reference to the second UART, only present in and (pin28 or pin34) of 44-pin package (see Pin
the TS80C51U2 part.
Rev. D - 15 January, 2001
1
TS80C51U2
TS83C51U2
TS87C51U2
configuration). UART_1 is fully compliant with the first one allowing an internal baud rate generator to be the
clock source. This common internal baud rate generator can be used independently by each UART or both as clock
source allowing to program various speeds.
The TS80C51U2 provides 7 sources of interrupt with four priority levels. UART_1 has a lower priority than Timer
2. The Serial Ports are full duplex meaning they can transmit and receive simultaneously. They are also receive
buffered, meaning they can start reception of a second byte before a previously received byte has been read from
the receive register. The Serial Port receive and transmit registers of UART_1 are both accessed at Special Function
Register SBUF_1. Writing to SBUF_1 loads the transmit register and reading SBUF_1 accesses a physical separate
receive register.
The UART_1 port control and status is the Special Function Register SCON_1. This register contains not only the
mode selection bit but also the 9th bit for transmit and receive (TB8_1 and RB8_1) and the serial port interrupt
bits (TI_1 and RI_1). The automatic address recognition feature is enabled when multiprocessor communication
is enabled. Implemented in hardware, automatic address recognition enhances the multiprocessor communication
feature by allowing the Serial Port to examine address of each incoming frame and provides filtering capability.
The UART_1 also comes with Frame error detection, similar to the UART_0.
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Rev. D - 15 January, 2001
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TS83C51U2
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Table 1. Memory size
ROM (bytes)
PDIL40
PLCC44
EPROM (bytes)
VQFP44 1.4
TS80C51U2
TS83C51U2
TS87C51U2
0
16k
0
0
0
16k
4. Block Diagram
(2) (2)
(1) (1)
(3) (3)
XTAL1
XTAL2
ROM
/EPROM
16Kx8
RAM
256x8
UART_0
Timer2
UART_1
ALE/PROG
PSEN
C51
CORE
IB-bus
CPU
EA/VPP
(2)
Parallel I/O Ports
Port 0 Port 1 Port 3
Timer 0
Timer 1
INT
Ctrl
RD
WatchDog
(2)
Port 2
WR
(2) (2)
(2) (2)
(1): Alternate function of Port 1
(2): Alternate function of Port 3
(3): See pin description
Rev. D - 15 January, 2001
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5. SFR Mapping
The Special Function Registers (SFRs) of the TS80C51U2 fall into the following categories:
•
•
•
•
•
•
•
•
•
•
C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
I/O port registers: P0, P1, P2, P3
Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H
Serial I/O port registers for UART_0: SADDR_0, SADEN_0, SBUF_0, SCON_0
Serial I/O port registers for UART_1: SADDR_1, SADEN_1, SBUF_1, SCON_1
Baud Rate Generator registers: BRL, BDRCON, BDRCON_1
Power and clock control registers: PCON
HDW Watchdog Timer Reset: WDTRST, WDTPRG
Interrupt system registers: IE, IP, IPH
Others: AUXR, CKCON
Table 2. All SFRs with their address and their reset value
Bit
address-
able
Non Bit addressable
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
F8h
F0h
FFh
F7h
B
0000 0000
E8h
E0h
EFh
E7h
ACC
0000 0000
D8h
D0h
DFh
D7h
PSW
0000 0000
T2CON
0000 0000
T2MOD
XXXX XX00
RCAP2L
0000 0000
RCAP2H
0000 0000
TL2
0000 0000
TH2
0000 0000
C8h
C0h
B8h
B0h
A8h
A0h
98h
90h
88h
80h
CFh
C7h
BFh
B7h
AFh
A7h
9Fh
97h
8Fh
87h
SCON_1
0000 0000
SBUF_1
XXXX XXXX
IP
SADEN_0
0000 0000
SADEN_1
0000 0000
X000 0000
P3
IPH
X000 0000
1111 1111
IE
SADDR_0
0000 0000
SADDR_1
0000 0000
0X00 0000
P2
AUXR1
XXXX XXX0
WDTRST
XXXX XXXX
WDTPRG
XXXX X000
1111 1111
SCON_0
0000 0000
SBUF_0
XXXX XXXX
BRL
0000 0000
BDRCON
0XXX 0000
BDRCON_1
0X00 00XX
P1
1111 1111
TCON
0000 0000
TMOD
0000 0000
TL0
0000 0000
TL1
0000 0000
TH0
0000 0000
TH1
0000 0000
AUXR
00XX XXX0
CKCON
XXXX XXX0
P0
SP
0000 0111
DPL
0000 0000
DPH
0000 0000
PCON
00X1 0000
1111 1111
0/8
1/9
2/A
3/B
4/C
5/D
6/E
7/F
reserved
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6. Pin Configuration
s
P1.0 / T2
P1.1 / T2EX
P1.2/RxD_1
P1.3/TxD_1
P1.4
40
39
38
1
2
VCC
P0.0 / A0
P0.1 / A1
3
4
37 P0.2 / A2
6
5
4
3
2
1
44 43 42 41 40
P0.3 / A3
36
5
6
P0.4 / A4
P1.5
P1.6/RxD_1
P1.7/TxD_1
RST
P1.5
35
39
38
7
8
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
TxD_1
P0.5 / A5
34
P0.6 / A6
33
P0.7 / A7
32
P1.6/RxD_1
7
8
37
9
P1.7/TxD_1
RST
9
10
11
12
13
36
35
34
33
P3.0/RxD_0
RxD_1
EA/VPP
ALE/PROG
PSEN
P3.0/RxD_0
P3.1/TxD_0
10
11
12
13
31
30
PDIL/
PLCC/CQPJ 44
P3.1/TxD_0
P3.2/INT0
P3.3/INT1
P3.4/T0
P3.2/INT0
P3.3/INT1
29
28
27
26
CDIL40
ALE/PROG
PSEN
P2.7 / A15
P2.6 / A14
14
15
16
17
32
31
30
29
P3.4/T0
14
15
16
17
18
19
20
P2.7/A15
P2.6/A14
P2.5/A13
P2.5 / A13
P3.5/T1
P3.6/WR
P2.4 / A12
P2.3 / A11
P3.5/T1
25
24
23
22
21
P3.7/RD
XTAL2
18 19 20 21 22 23 24 25 26 27 28
P2.2 / A10
P2.1 / A9
P2.0 / A8
XTAL1
VSS
44 43 42 41 40 39 38 37 36 35 34
P1.5
P0.4/AD4
P0.5/AD5
P0.6/AD6
P0.7/AD7
EA/VPP
TxD_1
33
32
1
2
P1.6/RxD_1
P1.7/TxD_1
RST
31
3
4
30
29
28
27
P3.0/RxD_0
RxD_1
5
6
VQFP44 1.4
P3.1/TxD_0
ALE/PROG
PSEN
7
8
26
25
24
23
P3.2/INT0
P3.3/INT1
P3.4/T0
P2.7/A15
P2.6/A14
P2.5/A13
9
10
11
P3.5/T1
12 13 14 15 16 17 18 19 20 21 22
*NIC: No Internal Connection
See “Alternate function on Port 1” on page 32 for accurate RxD_1 and TxD_1 pin location, depending on AUXR
register configuration.
Rev. D - 15 January, 2001
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TS80C51U2
TS83C51U2
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Table 3. Pin Description for 40/44 pin packages
PIN NUMBER
MNEMONIC
NAME AND FUNCTION
TYPE
DIL LCC VQFP 1.4
V
20
22
1
16
39
I
I
Ground: 0V reference
SS
Vss1
Optional Ground: Contact the Sales Office for ground connection.
Power Supply: This is the power supply voltage for normal, idle and power-
down operation
V
40
44
38
I
CC
P0.0-P0.7
39-32 43-36
37-30
I/O
Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s
written to them float and can be used as high impedance inputs. Port 0 pins must
be polarized to Vcc or Vss in order to prevent any parasitic current consumption.
Port 0 is also the multiplexed low-order address and data bus during access to
external program and data memory. In this application, it uses strong internal
pull-up when emitting 1s. Port 0 also inputs the code bytes during EPROM
programming. External pull-ups are required during program verification during
which P0 outputs the code bytes.
P1.0-P1.7
1-8
2-9
40-44
1-3
I/O
Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 1 pins that are externally pulled low will
source current because of the internal pull-ups. Port 1 also receives the low-order
address byte during memory programming and verification.
Alternate functions for TSC8x54/58 Port 1 include:
1
2
2
3
40
41
I/O
I
T2 (P1.0): Timer/Counter 2 external count input/Clockout
T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control
Depending on values of (M1UA_1, M0UA_1) bits located into AUXR register,
the UART_1 pins are alternate functins of P1 with two possible locations.
First location:
P1.2: RxD_1, serial input port for UART_1
P1.3: TxD_1, serial output port for UART_1
Second location:
3
4
4
5
42
43
I
O
P1.6: RxD_1, serial input port for UART_1
P1.7: TxD_1, serial output port for UART_1
7
8
8
9
2
3
I
O
See “Alternate function on Port 1” on page 32
P2.0-P2.7
21-28 24-31
18-25
I/O
Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 2 pins that are externally pulled low will
source current because of the internal pull-ups. Port 2 emits the high-order address
byte during fetches from external program memory and during accesses to external
data memory that use 16-bit addresses (MOVX @DPTR).In this application, it
uses strong internal pull-ups emitting 1s. During accesses to external data memory
that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR.
Some Port 2 pins receive the high order address bits during EPROM programming
and verification: P2.0 to P2.5
P3.0-P3.7
10-17
11,
13-19
5,
7-13
I/O
Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3
pins that have 1s written to them are pulled high by the internal pull-ups and
can be used as inputs. As inputs, Port 3 pins that are externally pulled low will
source current because of the internal pull-ups. Port 3 also serves the special
features of the 80C51 family, as listed below.
10
11
12
13
14
15
16
17
11
13
14
15
16
17
18
19
5
7
I
O
I
RxD_0 (P3.0): Serial input port for UART_0
TxD_0 (P3.1): Serial output port for UART_0
INT0 (P3.2): External interrupt 0
8
9
I
INT1 (P3.3): External interrupt 1
10
11
12
13
I
T0 (P3.4): Timer 0 external input
I
T1 (P3.5): Timer 1 external input
O
O
WR (P3.6): External data memory write strobe
RD (P3.7): External data memory read strobe
6
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
Table 3. Pin Description for 40/44 pin packages
PIN NUMBER
MNEMONIC
NAME AND FUNCTION
TYPE
DIL LCC VQFP 1.4
Reset
9
10
4
I
Reset: A high on this pin for two machine cycles while the oscillator is running,
resets the device. An internal diffused resistor to V permits a power-on reset
SS
using only an external capacitor to V
If the hardware watchdog reaches its
CC.
time-out, the reset pin becomes an output during the time the internal reset is
activated.
ALE/PROG
30
33
27
O (I) Address Latch Enable/Program Pulse: Output pulse for latching the low byte
of the address during an access to external memory. In normal operation, ALE
is emitted at a constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency,
and can be used for external timing or clocking. Note that one ALE pulse is
skipped during each access to external data memory. This pin is also the program
pulse input (PROG) during EPROM programming. ALE can be disabled by
setting SFR’s AUXR.0 bit. With this bit set, ALE will be inactive during internal
fetches.
PSEN
29
31
32
35
26
29
O
Program Store ENable: The read strobe to external program memory. When
executing code from the external program memory, PSEN is activated twice each
machine cycle, except that two PSEN activations are skipped during each access
to external data memory. PSEN is not activated during fetches from internal
program memory.
EA/V
I
External Access Enable/Programming Supply Voltage: EA must be externally
held low to enable the device to fetch code from external program memory
locations 0000H and 3FFFH (RB) or 7FFFH (RC), or FFFFH (RD). If EA is
held high, the device executes from internal program memory unless the program
counter contains an address greater than 3FFFH (RB) or 7FFFH (RC) EA must
be held low for ROMless devices. This pin also receives the 12.75V programming
PP
supply voltage (V ) during EPROM programming. If security level 1 is
PP
programmed, EA will be internally latched on Reset.
XTAL1
19
21
15
I
Crystal 1: Input to the inverting oscillator amplifier and input to the internal
clock generator circuits.
XTAL2
RxD_1
18
-
20
12
14
6
O
I
Crystal 2: Output from the inverting oscillator amplifier
Serial Input for UART_1. For 44-pin package only.
Serial Ouput for UART_1. This pin is pulled up by a 100K resistor when not
selected. For 44-pin package only.
TxD_1
-
34
28
O
Rev. D - 15 January, 2001
7
TS87C51U2
7. TS80C51U2 Enhanced Features
In comparison to the original 80C52, the TS80C51U2 implements some new features, which are:
•
•
•
•
•
•
•
•
•
•
The X2 option.
The second full duplex enhanced UART.
The Baud Rate generator.
The Dual Data Pointer.
The Watchdog.
The 4 level interrupt priority system.
The power-off flag.
The ONCE mode.
The ALE disabling.
Some enhanced features are also located in the UARTs and the timer 2.
7.1 X2 Feature
The TS80C51U2 core needs only 6 clock periods per machine cycle. This feature called ”X2” provides the following
advantages:
● Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
● Save power consumption while keeping same CPU power (oscillator power saving).
● Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.
● Increase CPU power by 2 while keeping same crystal frequency.
In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main
clock input of the core (phase generator). This divider may be disabled by software.
7.1.1 Description
The clock for the whole circuit and peripheral is first divided by two before being used by the CPU core and
peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2 mode, as this divider is bypassed,
the signals on XTAL1 must have a cyclic ratio between 40 to 60%. Figure 1. shows the clock generation block
diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode.
Figure 2. shows the mode switching waveforms.
XTAL1:2
2
state machine: 6 clock cycles.
CPU control
XTAL1
0
1
FXTAL
FOSC
X2
CKCON reg
Figure 1. Clock Generation Diagram
8
Rev. D - 06 december, 2000
TS87C51U2
XTAL1
XTAL1:2
X2 bit
CPU clock
STD Mode
X2 Mode
STD Mode
Figure 2. Mode Switching Waveforms
The X2 bit in the CKCON register (See Table 4.) allows to switch from 12 clock cycles per instruction to 6 clock
cycles and vice versa. At reset, the standard speed is activated (STD mode). Setting this bit activates the X2 feature
(X2 mode).
CAUTION
In order to prevent any incorrect operation while operating in X2 mode, user must be aware that all peripherals
using clock frequency as time reference (UARTs, timers) will have their time reference divided by two. For example
a free running timer generating an interrupt every 20 ms will then generate an interrupt every 10 ms. UART with
4800 baud rate will have 9600 baud rate.
Rev. D - 06 december, 2000
9
TS87C51U2
Table 4. CKCON Register
CKCON - Clock Control Register (8Fh)
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
X2
Bit
Number
Bit
Mnemonic
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
7
6
5
4
3
2
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
-
-
-
-
-
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
CPU and peripheral clock bit
Clear to select 12 clock periods per machine cycle (STD mode, F
=FXTAL/2).
0
X2
OSC
Set to select 6 clock periods per machine cycle (X2 mode, F
=F
).
OSC XTAL
Reset Value = XXXX XXX0b
Not bit addressable
For further details on the X2 feature, please refer to ANM072 available on the web (http://www.atmel-wm.com)
10
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7.2 Dual Data Pointer Register Ddptr
The additional data pointer can be used to speed up code execution and reduce code size in a number of
ways.
The dual DPTR structure is a way by which the chip will specify the address of an external data memory
location. There are two 16-bit DPTR registers that address the external memory, and a single bit called
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer to Figure 3).
External Data Memory
7
0
DPS
DPTR1
DPTR0
AUXR1(A2H)
DPH(83H) DPL(82H)
Figure 3. Use of Dual Pointer
Rev. D - 15 January, 2001
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TS80C51U2
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TS87C51U2
Table 5. AUXR1: Auxiliary Register 1
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
DPS
Bit
Number
Bit
Mnemonic
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
7
6
5
4
3
2
1
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
-
-
-
-
-
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Data Pointer Selection
Clear to select DPTR0.
Set to select DPTR1.
0
DPS
Reset Value = XXXX XXX0
Not bit addressable
User software should not write 1s to reserved bits. These bits may be used in future 8051 family products to invoke new feature. In that case, the reset
value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate.
Application
Software can take advantage of the additional data pointers to both increase speed and reduce code size, for
example, block operations (copy, compare, search ...) are well served by using one data pointer as a ’source’
pointer and the other one as a "destination" pointer.
12
Rev. D - 15 January, 2001
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ASSEMBLY LANGUAGE
; Block move using dual data pointers
; Destroys DPTR0, DPTR1, A and PSW
; note: DPS exits opposite of entry state
; unless an extra INC AUXR1 is added
;
00A2
;
AUXR1 EQU 0A2H
0000 909000MOV DPTR,#SOURCE
0003 05A2 INC AUXR1
0005 90A000 MOV DPTR,#DEST
; address of SOURCE
; switch data pointers
; address of DEST
0008
LOOP:
0008 05A2 INC AUXR1
; switch data pointers
000A E0
000B A3
000C 05A2 INC AUXR1
MOVX A,@DPTR
INC DPTR
; get a byte from SOURCE
; increment SOURCE address
; switch data pointers
000E F0
000F A3
0010 70F6 JNZ LOOP
0012 05A2 INC AUXR1
MOVX @DPTR,A
INC DPTR
; write the byte to DEST
; increment DEST address
; check for 0 terminator
; (optional) restore DPS
INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However,
note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it.
In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence
matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1'
on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the
opposite state.
Rev. D - 15 January, 2001
13
TS80C51U2
TS83C51U2
TS87C51U2
7.3 Timer 2
The timer 2 in the TS80C51U2 is compatible with the timer 2 in the 80C52.
It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2, connected in
cascade. It is controlled by T2CON register (See Table 6) and T2MOD register (See Table 7). Timer 2 operation
is similar to Timer 0 and Timer 1. C/T2 selects F
/12 (timer operation) or external pin T2 (counter operation)
OSC
as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input.
Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes are selected by the
combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the Atmel Wireless & Microcontrollers 8-
bit Microcontroller Hardware description.
Refer to the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description for the description of
Capture and Baud Rate Generator Modes.
In TS80C51U2 Timer 2 includes the following enhancements:
● Auto-reload mode with up or down counter
● Programmable clock-output
7.3.1 Auto-Reload Mode
The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic reload. If DCEN bit
in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel Wireless & Microcontrollers 8-bit
Microcontroller Hardware description). If DCEN bit is set, timer 2 acts as an Up/down timer/counter as shown in
Figure 4. In this mode the T2EX pin controls the direction of count.
When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag and generates
an interrupt request. The overflow also causes the 16-bit value in RCAP2H and RCAP2L registers to be loaded
into the timer registers TH2 and TL2.
When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer registers TH2 and
TL2 equals the value stored in RCAP2H and RCAP2L registers. The underflow sets TF2 flag and reloads FFFFh
into the timer registers.
The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the count. EXF2
does not generate any interrupt. This bit can be used to provide 17-bit resolution.
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Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
(:6 in X2 mode)
:12
0
1
XTAL1
F
F
OSC
XTAL
T2
TR2
C/T2
T2CONreg
T2CONreg
(DOWN COUNTING RELOAD VALUE)
T2EX:
if DCEN=1, 1=UP
if DCEN=1, 0=DOWN
if DCEN = 0, up counting
FFh
(8-bit)
FFh
(8-bit)
T2CONreg
EXF2
TOGGLE
TL2
(8-bit)
TH2
(8-bit)
TIMER 2
INTERRUPT
TF2
T2CONreg
RCAP2L
(8-bit)
RCAP2H
(8-bit)
(UP COUNTING RELOAD VALUE)
Figure 4. Auto-Reload Mode Up/Down Counter (DCEN = 1)
7.3.2 Programmable Clock-Output
In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator (See Figure 5) . The
input clock increments TL2 at frequency F /2. The timer repeatedly counts to overflow from a loaded value.
OSC
At overflow, the contents of RCAP2H and RCAP2L registers are loaded into TH2 and TL2. In this mode, timer
2 overflows do not generate interrupts. The formula gives the clock-out frequency as a function of the system
oscillator frequency and the value in the RCAP2H and RCAP2L registers:
F
osc
Clock – OutFrequency = --------------------------------------------------------------------------------------
4 × (65536 – RCAP2H ⁄ RCAP2L)
For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz
16)
(F
/2 to 4 MHz (F
/4). The generated clock signal is brought out to T2 pin (P1.0).
OSC
OSC
Timer 2 is programmed for the clock-out mode as follows:
● Set T2OE bit in T2MOD register.
● Clear C/T2 bit in T2CON register.
● Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.
● Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different
one depending on the application.
Rev. D - 15 January, 2001
15
TS80C51U2
TS83C51U2
TS87C51U2
● To start the timer, set TR2 run control bit in T2CON register.
It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration,
the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and
RCAP2L registers.
:2
XTAL1
(:1 in X2 mode)
TR2
T2CON reg
TH2
TL2
(8-bit) (8-bit)
OVERFLOW
RCAP2H
RCAP2L
(8-bit) (8-bit)
Toggle
T2
Q
D
T2OE
T2MOD reg
TIMER 2
INTERRUPT
T2EX
EXF2
T2CON reg
EXEN2
T2CON reg
Figure 5. Clock-Out Mode C/T2 = 0
16
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
Table 6. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Number
Bit
Mnemonic
Description
Timer 2 overflow Flag
7
6
TF2
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)
EXF2
Receive Clock bit for UART_0
5
4
RCLK_0
TCLK_0
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit for UART_0
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to
clock the serial port.
3
EXEN2
Timer 2 Run control bit
Clear to turn off timer 2.
Set to turn on timer 2.
2
1
TR2
Timer/Counter 2 select bit
Clear for timer operation (input from internal clock system: F
).
C/T2#
OSC
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow.
Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
0
CP/RL2#
Reset Value = 0000 0000b
Bit addressable
Rev. D - 15 January, 2001
17
TS80C51U2
TS83C51U2
TS87C51U2
Table 7. T2MOD Register
T2MOD - Timer 2 Mode Control Register (C9h)
7
-
6
-
5
-
4
-
3
-
2
-
1
0
T2OE
DCEN
Bit
Number
Bit
Mnemonic
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit.
7
6
5
4
3
2
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
-
-
-
-
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Timer 2 Output Enable bit
1
0
T2OE
Clear to program P1.0/T2 as clock input or I/O port.
Set to program P1.0/T2 as clock output.
Down Counter Enable bit
DCEN
Clear to disable timer 2 as up/down counter.
Set to enable timer 2 as up/down counter.
Reset Value = XXXX XX00b
Not bit addressable
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TS83C51U2
TS87C51U2
7.4 TS80C51U2 Serial I/O Ports enhancements
The serial I/O ports in the TS80C51U2 are compatible with the serial I/O port in the 80C52.
They provide both synchronous and asynchronous communication modes. They operate as Universal Asynchronous
Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2 and 3). Asynchronous transmission and
reception can occur simultaneously and at different baud rates
Serial I/O ports include the following enhancements:
● Framing error detection
● Automatic address recognition
As these improvements apply to both UART, most of the time in the following lines, there won’t be any reference
to UART_0 or UART_1, but only to UART, generally speaking. Idem for the bits in registers.
7.4.1 Framing Error Detection
Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To enable the framing
bit error detection feature, set SMOD0 bit in PCON register (See Figure 6).
SM0/FE SM1
SM2
REN
TB8
RB8
TI
RI
SCON_0 for UART_0 (98h)
(SCON_1 for UART_1 (C0h))
Set FE bit if stop bit is 0 (framing error) (SMOD0_0 = 1 for UART_0)
SM0 to UART mode control (SMOD0_0 = 0 for UART_0)
SMOD1_0 SMOD0_0
PCON for UART_0 (87h)
(SMOD bits for UART_1 are
located in BDRCON_1)
-
POF
GF1
GF0
PD
IDL
To UART framing error control
Figure 6. Framing Error Block Diagram
When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit. An invalid stop
bit may result from noise on the serial lines or from simultaneous transmission by two CPUs. If a valid stop bit
is not found, the Framing Error bit (FE) in SCON register (See Table 8.) bit is set.
Rev. D - 15 January, 2001
19
TS80C51U2
TS83C51U2
TS87C51U2
Software may examine FE bit after each reception to check for data errors. Once set, only software or a reset can
clear FE bit. Subsequently received frames with valid stop bits cannot clear FE bit. When FE feature is enabled,
RI rises on stop bit instead of the last data bit (See Figure 7. and Figure 8.).
RXD
D0
D1
D2
D3
D4
D5
D6
D7
Start
bit
Data byte
Stop
bit
RI
SMOD0=X
FE
SMOD0=1
Figure 7. UART Timings in Mode 1
RXD
RI
D0
D1
D2
D3
D4
D5
D6
D7
D8
Start
bit
Data byte
Ninth Stop
bit bit
SMOD0=0
RI
SMOD0=1
FE
SMOD0=1
Figure 8. UART Timings in Modes 2 and 3
7.4.2 Automatic Address Recognition
The automatic address recognition feature is enabled for each UART when the multiprocessor communication
feature is enabled (SM2 bit in SCON register is set).
Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by
allowing the serial port to examine the address of each incoming command frame. Only when the serial port
recognizes its own address, the receiver sets RI bit in SCON register to generate an interrupt. This ensures that
the CPU is not interrupted by command frames addressed to other devices.
If desired, you may enable the automatic address recognition feature in mode 1. In this configuration, the stop bit
takes the place of the ninth data bit. Bit RI is set only when the received command frame address matches the
device’s address and is terminated by a valid stop bit.
To support automatic address recognition, a device is identified by a given address and a broadcast address.
NOTE: The multiprocessor communication and automatic address recognition features cannot be enabled in mode 0 (i.e. setting SM2 bit in SCON
register in mode 0 has no effect).
7.4.3 Given Address
Each UART has an individual address that is specified in SADDR_0 or SADDR_1 register; the SADEN_0 or
SADEN_1 register is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given
address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The following example
20
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
illustrates how a given address is formed.
To address a device by its individual address, the SADEN mask byte must be 1111 1111b.
For example:
SADDR
SADEN
Given
0101 0110b
1111 1100b
0101 01XXb
The following is an example of how to use given addresses to address different slaves:
Slave A:
Slave B:
Slave C:
SADDR
SADEN
Given
1111 0001b
1111 1010b
1111 0X0Xb
SADDR
SADEN
Given
1111 0011b
1111 1001b
1111 0XX1b
SADDR
SADEN
Given
1111 0010b
1111 1101b
1111 00X1b
The SADEN byte is selected so that each slave may be addressed separately.
For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A
only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).
For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but
not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111 0011b).
To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2
clear (e.g. 1111 0001b).
7.4.4 Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as
don’t-care bits, e.g.:
SADDR
0101 0110b
1111 1100b
1111 111Xb
SADEN
Broadcast =SADDR OR SADEN
The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a
broadcast address is FFh. The following is an example of using broadcast addresses:
Slave A:
Slave B:
Slave C:
SADDR
1111 0001b
SADEN
1111 1010b
Broadcast 1111 1X11b,
SADDR
SADEN
1111 0011b
1111 1001b
Broadcast 1111 1X11B,
SADDR=
SADEN
Broadcast 1111 1111b
1111 0010b
1111 1101b
For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the
master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send
and address FBh.
7.4.5 Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses are XXXX
XXXXb (all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards
compatible with the 80C51 microcontrollers that do not support automatic address recognition.
Rev. D - 15 January, 2001
21
TS80C51U2
TS83C51U2
TS87C51U2
7.4.6 Baud Rate Selection for UART0_0 for mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via the T2CON and BDRCON
registers.
TIMER1_BRG
TIMER_BRG
0
1
0
1
TIMER2_BRG
/ 16
Rx_0 Clock
RCLK_0
INT_BRG_0
RBCK_0
TIMER1_BRG
TIMER2_BRG
TIMER_BRG
0
1
0
/ 16
1
Tx_0 Clock
TCLK_0
INT_BRG_0
TBCK_0
Figure 9. Baud Rate selection
7.4.7 Baud Rate Selection for UART1_1 for mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via the BDRCON_1 register.
TIMER1_BRG
TIMER_BRG
0
1
0
TIMER2_BRG
/ 16
Rx_1 Clock
1
RCLK_1
INT_BRG_1
RBCK_1
TIMER1_BRG
TIMER2_BRG
TIMER_BRG
0
1
0
/ 16
1
Tx_1 Clock
TCLK_1
INT_BRG_1
TBCK_1
Figure 10. Baud Rate selection
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Rev. D - 15 January, 2001
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TS87C51U2
7.4.8 Baud Rate selection table for UART_0
TCLK_0 RCLK_0 TBCK_0 RBCK_0 ClockSourcefor
UART_0 Tx
Clock Source
UART_0 Rx
0
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
1
1
1
Timer 1
Timer 2
Timer 1
Timer 1
0
1
Timer 1
Timer 2
1
1
Timer 2
Timer 2
X
X
0
0
INT_BRG_0
INT_BRG_0
Timer 1
Timer 1
1
Timer 2
X
X
X
INT_BRG_0
INT_BRG_0
INT_BRG_0
1
Timer 2
X
INT_BRG_0
7.4.9 Baud Rate selection table for UART_1
TCLK_1 RCLK_1 TBCK_1 RBCK_1 ClockSourcefor
UART_1 Tx
Clock Source
UART_1 Rx
0
1
0
0
0
0
0
0
1
1
0
0
1
0
0
0
0
0
0
1
1
1
Timer 1
Timer 2
Timer 1
Timer 1
0
1
Timer 1
Timer 2
1
1
Timer 2
Timer 2
X
X
0
0
INT_BRG_1
INT_BRG_1
Timer 1
Timer 1
1
Timer 2
X
X
X
INT_BRG_1
INT_BRG_1
INT_BRG_1
1
Timer 2
X
INT_BRG_1
7.4.10 Internal Baud Rate Generator (BRG)
When the internal Baud Rate Generator is used, the Baud Rates are determined by the BRG overflow depending on the
BRL reload value, the X2 bit in CKON register, the value of SPD bit (Speed Mode) in BDRCON register and the value
of the SMOD1_0 bit in PCON register (for UART_0) or SMOD1_1 in BDRCON_1 register (for UART_1). The Internal
Baud Rate Generator is common to both UARTs:
SMOD1_0
/2
0
INT_BRG_0
XTAL1
FXTAL
1
auto reload counter
/2
0
1
0
1
/6
BRG
overflow
/2
BRL
X2
0
1
SPD
BRR
INT_BRG_1
SMOD1_1
Figure 11. Internal Baud Rate
Rev. D - 15 January, 2001
23
TS80C51U2
TS83C51U2
TS87C51U2
● for UART_1
SMOD1_1
(1-SPD)
X2
2
x 2 x FXTAL
Baud_Rate =
(BRL) = 256 -
2 x 2 x 6
x 16 x [256 - (BRL)]
SMOD1_1
X2
2
x 2 x FXTAL
(1-SPD)
2 x 2 x 6
x 16 x Baud_Rate
● for UART_0
SMOD1_0
X2
2
x 2 x FXTAL
Baud_Rate =
(BRL) = 256 -
(1-SPD)
2 x 2 x 6
x 16 x [256 - (BRL)]
SMOD1_0
(1-SPD)
X2
2
x 2 x FXTAL
2 x 2 x 6
x 16 x Baud_Rate
Example of computed value when X2=1, SMOD1=1, SPD=1
FXTAL = 16.384 MHz
FXTAL = 24MHz
Baud Rates
BRL
Error (%)
BRL
Error (%)
115200
57600
38400
28800
19200
9600
247
238
229
220
203
149
43
1.23
1.23
1.23
1.23
0.63
0.31
1.23
243
230
217
204
178
100
-
0.16
0.16
0.16
0.16
0.16
0.16
-
4800
Example of computed value when X2=0, SMOD1=0, SPD=0
FOSC = 16.384 MHz
Error (%)
FOSC = 24MHz
Baud Rates
BRL
BRL
Error (%)
4800
2400
1200
600
247
238
220
185
1.23
1.23
1.23
0.16
243
230
202
152
0.16
0.16
3.55
0.16
The baud rate generator can be used for mode 1 or 3 (refer to figures 9 and 10), but also for mode 0 for both
UARTs, thanks to the bit SRC located in BDRCON register (Table 12)
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Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
7.5 UARTs registers
SADEN_0 - Slave Address Mask Register for UART_0 (B9h)
7
6
5
4
3
3
3
3
3
3
2
2
2
2
2
2
1
1
1
1
1
1
0
0
0
0
0
0
0
Reset Value = 0000 0000b
SADEN_1 - Slave Address Mask Register for UART_1 (BAh)
7
6
5
4
Reset Value = 0000 0000b
SADDR_0 - Slave Address Register for UART_0 (A9h)
7
6
5
4
Reset Value = 0000 0000b
SADDR_1 - Slave Address Register for UART_1 (AAh)
7
6
5
4
4
4
Reset Value = 0000 0000b
SBUF_0 - Serial Buffer Register for UART_0 (99h)
7
6
5
Reset Value = XXXX XXXXb
SBUF_1 - Serial Buffer Register for UART_1 (C1h)
7
6
5
Reset Value = XXXX XXXXb
BRL - Baud Rate Reload Register for the internal baud rate generator, UART_0 and UART_1 (9Ah)
7
6
5
4
3
2
1
Reset Value = 0000 0000b
Rev. D - 15 January, 2001
25
TS80C51U2
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TS87C51U2
Table 8. SCON Register
SCON_0 - Serial Control Register for UART_0 (98h)
7
6
5
4
3
2
1
0
FE_0/
SM1_0
SM2_0
REN_0
TB8_0
RB8_0
TI_0
RI_0
SM0_0
Bit
Number
Bit
Mnemonic
Description
Framing Error bit (SMOD0_0=1) for UART_0
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
7
FE_0
SMOD0_0 must be set to enable access to the FE bit
Serial port Mode bit 0 (SMOD0_0=0) for UART_0
Refer to SM1 for serial port mode selection.
SMOD0_0 must be cleared to enable access to the SM0_0 bit
SM0_0
SM1_0
Serial port Mode bit 1 for UART_0
SM0_0 SM1_0 Mode
Description
Baud Rate
/12 (F
0
0
0
Shift Register
F
/6 X2 mode)
XTAL
6
5
XTAL
0
1
1
1
0
1
1
2
3
8-bit UART
9-bit UART
9-bit UART
Variable
/64 or F
F
/32 (F
/32 or F /16 X2 mode)
XTAL
XTAL
XTAL
XTAL
Variable
Serial port Mode 2 bit / Multiprocessor Communication Enable bit for UART_0
Clear to disable multiprocessor communication feature.
SM2_0
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should
be cleared in mode 0.
Reception Enable bit for UART_0
Clear to disable serial reception.
Set to enable serial reception.
4
3
REN_0
TB8_0
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 for UART_0.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8 / Ninth bit received in modes 2 and 3 for UART_0
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
2
RB8_0
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag for UART_0
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
modes.
1
0
TI_0
RI_0
Receive Interrupt flag for UART_0
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 7. and Figure 8. in the other modes.
Reset Value = 0000 0000b
Bit addressable
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Rev. D - 15 January, 2001
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TS83C51U2
TS87C51U2
Table 9. SCON Register
SCON_1 - Serial Control Register for UART_1 (C0h)
7
6
5
4
3
2
1
0
FE_1/
SM1_1
SM2_1
REN_1
TB8_1
RB8_1
TI_1
RI_1
SM0_1
Bit
Number
Bit
Mnemonic
Description
Framing Error bit (SMOD0_1=1) for UART_1
Clear to reset the error state, not cleared by a valid stop bit.
Set by hardware when an invalid stop bit is detected.
7
FE_1
SMOD0_1 must be set to enable access to the FE bit
Serial port Mode bit 0 (SMOD0_1=0) for UART_1
Refer to SM1 for serial port mode selection.
SMOD0_1 must be cleared to enable access to the SM0_1 bit
SM0_1
SM1_1
Serial port Mode bit 1 for UART_1
SM0_1 SM1_1 Mode
Description
Baud Rate
/12 (F
0
0
0
Shift Register
F
/6 X2 mode)
XTAL
6
5
XTAL
0
1
1
1
0
1
1
2
3
8-bit UART
9-bit UART
9-bit UART
Variable
/64 or F
F
/32 (F
/32 or F /16 X2 mode)
XTAL
XTAL
XTAL
XTAL
Variable
Serial port Mode 2 bit / Multiprocessor Communication Enable bit for UART_1
Clear to disable multiprocessor communication feature.
SM2_1
Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode 1. This bit should
be cleared in mode 0.
Reception Enable bit for UART_1
Clear to disable serial reception.
Set to enable serial reception.
4
3
REN_1
TB8_1
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 for UART_1.
Clear to transmit a logic 0 in the 9th bit.
Set to transmit a logic 1 in the 9th bit.
Receiver Bit 8 / Ninth bit received in modes 2 and 3 for UART_1
Cleared by hardware if 9th bit received is a logic 0.
Set by hardware if 9th bit received is a logic 1.
2
RB8_1
In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
Transmit Interrupt flag for UART_1
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in the other
modes.
1
0
TI_1
RI_1
Receive Interrupt flag for UART_1
Clear to acknowledge interrupt.
Set by hardware at the end of the 8th bit time in mode 0, see Figure 7. and Figure 8. in the other modes.
Reset Value = 0000 0000b
Bit addressable
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Table 10. T2CON Register
T2CON - Timer 2 Control Register (C8h)
7
6
5
4
3
2
1
0
TF2
EXF2
RCLK
TCLK
EXEN2
TR2
C/T2#
CP/RL2#
Bit
Number
Bit
Mnemonic
Description
Timer 2 overflow Flag
7
6
TF2
Must be cleared by software.
Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
Timer 2 External Flag
Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.
When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.
Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode (DCEN = 1)
EXF2
Receive Clock bit for UART_0
5
4
RCLK_0
TCLK_0
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
Transmit Clock bit for UART_0
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.
Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
Timer 2 External Enable bit
Clear to ignore events on T2EX pin for timer 2 operation.
Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer 2 is not used to
clock the serial port.
3
EXEN2
Timer 2 Run control bit
Clear to turn off timer 2.
Set to turn on timer 2.
2
1
TR2
Timer/Counter 2 select bit
Clear for timer operation (input from internal clock system: F
).
C/T2#
OSC
Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.
Timer 2 Capture/Reload bit
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow.
Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1.
Set to capture on negative transitions on T2EX pin if EXEN2=1.
0
CP/RL2#
Reset Value = 0000 0000b
Bit addressable
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Table 11. PCON Register
PCON - Power Control Register (87h)
7
6
5
-
4
3
2
1
0
SMOD1_0
SMOD0_0
POF
GF1
GF0
PD
IDL
Bit
Number
Bit
Mnemonic
Description
Serial port Mode bit 1 for UART_0
7
6
5
4
SMOD1_0
SMOD0_0
-
Set to select double baud rate in mode 1, 2 or 3.
Serial port Mode bit 0 for UART_0
Clear to select SM0_0 bit in SCON_0 register.
Set to to select FE_0 bit in SCON_0 register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Power-Off Flag
Clear to recognize next reset type.
POF
Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
General purpose Flag
3
2
1
0
GF1
GF0
PD
Cleared by user for general purpose usage.
Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle mode bit
IDL
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00X1 0000b
Not bit addressable
Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit.
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Table 12. BDRCON Register
BDRCON - Baud Rate Control Register (9Bh)
7
-
6
-
5
-
4
3
2
1
0
BRR
TBCK_0
RBCK_0
SPD
SRC
Bit
Number
Bit Mne-
monic
Description
Reserved
The value read from this bit is indeterminate. Do not set this bit
7
6
5
-
-
-
Reserved
The value read from this bit is indeterminate. Do not set this bit
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Baud Rate Run Control bit
4
3
2
1
0
BRR
TBCK_0
RBCK_0
SPD
Clear to stop the internal Baud Rate Generator.
Set to start the internal Baud Rate Generator.
Transmission Baud rate Generator Selection bit for UART_0
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
Reception Baud Rate Generator Selection bit for UART_0
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator.
Set to select internal Baud Rate Generator.
Baud Rate Speed Control bit for UART_0
Clear to select the SLOW Baud Rate Generator.
Set to select the FAST Baud Rate Generator.
Baud Rate Source select bit in Mode 0 for UART_0 and UART_1
Clear to select F
/12 as the Baud Rate Generator (F
/6 in X2 mode).
SRC
OSC
OSC
Set to select the internal Baud Rate Generator for UARTs in mode 0..
Reset Value = XXX0 0000b
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Table 13. BDRCON_1 Register
BDRCON_1 - Baud Rate Control Register for UART_1 (9Ch)
7
6
5
4
3
2
1
-
0
-
SMOD1_1
SMOD0_1
RCLK_1
TCLK_1
TBCK_1
RBCK_1
Bit
Number
Bit Mne-
monic
Description
Serial port Mode bit 1 for UART_1
7
6
SMOD1_1
Set to select double baud rate, in mode 1, 2 and 3.
SCON Select bit for UART_1
SMOD0_1
RCLK_1
TCLK_1
TBCK_1
RBCK_1
Clear to select SM0_1 bit in SCON_1 register..
Set to to select FE_1 bit in SCON_1 register.
Receive Clock bit for UART_1
5
4
3
2
Clear to select Timer 1 as Receive Baud Rate Generator for the UART_1
Set to Select Timer 2 as the Receive Baud Rate Generator for the UART_1
Transmit Clock bit for UART_1
Clear to select Timer 1 as Transmit Baud Rate Generator for the UART_1
Set to Select Timer 2 as the Transmit Baud Rate Generator for the UART_1.
Transmission Baud rate Generator Selection bit for UART_1
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator, for Tx.
Set to select internal Baud Rate Generator for Tx.
Reception Baud Rate Generator Selection bit for UART_1
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator for Rx.
Set to select internal Baud Rate Generator for Rx.
Reserved
1
0
-
-
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reset Value = 0000 00XXb
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7.6 Alternate function on Port 1
The M1UA_1 and M0UA_1 bits located into AUXR register at bit location 7 and 6 permit to validate alternate functions
located on Port 1. Following the combination of these two bits, the TxD_1 output and RxD_1 input of UART_1 take
place on Port 1 pins (two different locations are possible) and the other locations of TxD_1 and RxD_1 available only
for 44-pin package are no more valid.
Table 14. AUXR Register
AUXR - Auxiliary Register (8Eh)
7
6
5
-
4
-
3
-
2
-
1
-
0
M1UA_1
M0UA_1
AO
Bit
Number
Bit Mne-
monic
Description
Multiplex I/Os of UART_1 bit 1
7
M1UA_1
This bit is used in conjunction with M0UA_1 bit to specify where are multiplexed UART_1 pins.
Multiplex I/Os of UART_1 bit 0
This bit is used in conjunction with M1UA_1 bit bit to specify where are multiplexed UART_1 pins.
M1UA_1M0UA_1Result
6
M0UA_1
0
0
1
1
0
1
0
1
UART_1 pins are disabled.
UART_1 pins are located on pins (6, 28) or (12, 34) for 44-package only.
UART_1 pins are alternate functions of P1 located at P1.2 and P1.3.
UART_1 pins are alternate functions of P1 located at P1.6 and P1.7.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
4
3
2
1
-
-
-
-
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
ALE Output bit
Clear to restore ALE operation during internal fetches.
Set to disable ALE operation during internal fetches.
0
AO
Reset Value = 00XX XXX0b
Not bit addressable
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7.7 Interrupt System
The TS80C51U2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1), three timer interrupts
(timers 0, 1 and 2) and the two serial port interrupts. These interrupts are shown in Figure 12.
High priority
interrupt
IPH, IP
3
IE0
IE1
INT0
0
3
0
3
0
3
0
TF0
INT1
TF1
Interrupt
polling
sequence, decreasing
from high to low priority
3
RI_0
TI_0
0
3
TF2
EXF2
0
RI_1
TI_1
Individual Enable
Global Disable
Figure 12. Interrupt Control System
Low priority
interrupt
Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit in the Interrupt
Enable register (See Table 16.). This register also contains a global disable bit, which must be cleared to disable
all interrupts at once.
Each interrupt source can also be individually programmed to one out of four priority levels by setting or clearing
a bit in the Interrupt Priority register (See Table 17.) and in the Interrupt Priority High register (See Table 18.).
shows the bit values and priority levels associated with each combination.
The second UART interrupt vector is located at address 0033H. All other vector addresses are the same as standard
C52 devices.
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Table 15. Priority Level Bit Values
IP.x
IPH.x
Interrupt Level Priority
0
0
1
1
0
1
0
1
0 (Lowest)
1
2
3 (Highest)
A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt.
A high-priority interrupt can’t be interrupted by any other interrupt source.
If two interrupt requests of different priority levels are received simultaneously, the request of higher priority level
is serviced. If interrupt requests of the same priority level are received simultaneously, an internal polling sequence
determines which request is serviced. Thus within each priority level there is a second priority structure determined
by the polling sequence.
Table 16. IE Register
IE - Interrupt Enable Register (A8h)
7
6
5
4
3
2
1
0
EA
ES_1
ET2
ES_0
ET1
EX1
ET0
EX0
Bit
Number
Bit
Mnemonic
Description
Enable All interrupt bit
Clear to disable all interrupts.
Set to enable all interrupts.
7
EA
If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its own interrupt
enable bit.
Serial port Enable bit for UART_1
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
6
5
4
3
2
1
0
ES_1
ET2
ES_0
ET1
EX1
ET0
EX0
Timer 2 overflow interrupt Enable bit
Clear to disable timer 2 overflow interrupt.
Set to enable timer 2 overflow interrupt.
Serial port Enable bit for UART_0
Clear to disable serial port interrupt.
Set to enable serial port interrupt.
Timer 1 overflow interrupt Enable bit
Clear to disable timer 1 overflow interrupt.
Set to enable timer 1 overflow interrupt.
External interrupt 1 Enable bit
Clear to disable external interrupt 1.
Set to enable external interrupt 1.
Timer 0 overflow interrupt Enable bit
Clear to disable timer 0 overflow interrupt.
Set to enable timer 0 overflow interrupt.
External interrupt 0 Enable bit
Clear to disable external interrupt 0.
Set to enable external interrupt 0.
Reset Value = 0000 0000b
Bit addressable
34
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Table 17. IP Register
IP - Interrupt Priority Register (B8h)
7
-
6
5
4
3
2
1
0
PS_1
PT2
PS_0
PT1
PX1
PT0
PX0
Bit
Number
Bit
Mnemonic
Description
Reserved
7
6
5
4
3
2
1
0
-
The value read from this bit is indeterminate. Do not set this bit.
Serial port Priority bit for UART_1
PS_1
PT2
PS_0
PT1
PX1
PT0
PX0
Refer to PSH for priority level.
Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
Serial port Priority bit for UART_0
Refer to PSH for priority level.
Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
External interrupt 1 Priority bit
Refer to PX1H for priority level.
Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
External interrupt 0 Priority bit
Refer to PX0H for priority level.
Reset Value = X000 0000b
Bit addressable
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Table 18. IPH Register
IPH - Interrupt Priority High Register (B7h)
7
-
6
5
4
3
2
1
0
PSH_1
PT2H
PSH_0
PT1H
PX1H
PT0H
PX0H
Bit
Number
Bit
Mnemonic
Description
Reserved
7
-
The value read from this bit is indeterminate. Do not set this bit.
Serial port Priority High bit for UART_1
PSH_1
PS_1
Priority Level
Lowest
0
0
1
1
0
1
0
1
6
PSH_1
PT2H
PSH_0
PT1H
PX1H
PT0H
PX0H
Highest
Timer 2 overflow interrupt Priority High bit
PT2H
PT2
0
1
0
1
Priority Level
Lowest
0
0
1
1
5
4
3
2
1
0
Highest
Serial port Priority High bit for UART_0
PSH_0
PS_0
Priority Level
Lowest
0
0
1
1
0
1
0
1
Highest
Timer 1 overflow interrupt Priority High bit
PT1H
PT1
0
1
0
1
Priority Level
Lowest
0
0
1
1
Highest
External interrupt 1 Priority High bit
PX1H
PX1
Priority Level
Lowest
0
0
1
1
0
1
0
1
Highest
Timer 0 overflow interrupt Priority High bit
PT0H
PT0
0
1
0
1
Priority Level
Lowest
0
0
1
1
Highest
External interrupt 0 Priority High bit
PX0H
PX0
Priority Level
Lowest
0
0
1
1
0
1
0
1
Highest
Reset Value = X000 0000b
Not bit addressable
36
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7.8 Idle mode
An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode.
In the Idle mode, the internal clock signal is gated off to the CPU, but not to the interrupt, Timer, and Serial Port
functions. The CPU status is preserved in its entirely : the Stack Pointer, Program Counter, Program Status Word,
Accumulator and all other registers maintain their data during Idle. The port pins hold the logical states they had
at the time Idle was activated. ALE and PSEN hold at logic high levels.
There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0 to be cleared by
hardware, terminating the Idle mode. The interrupt will be serviced, and following RETI the next instruction to
be executed will be the one following the instruction that put the device into idle.
The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during normal operation or
during an Idle. For example, an instruction that activates Idle can also set one or both flag bits. When Idle is
terminated by an interrupt, the interrupt service routine can examine the flag bits.
The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is still running,
the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.
7.9 Power-Down Mode
To save maximum power, a power-down mode can be invoked by software (Refer to 7.4.6, PCON register).
In power-down mode, the oscillator is stopped and the instruction that invoked power-down mode is the last
instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated.
V
can be lowered to save further power. Either a hardware reset or an external interrupt can cause an exit from
CC
power-down. To properly terminate power-down, the reset or external interrupt should not be executed before V
CC
is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize.
Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt must be enabled
and configured as level or edge sensitive interrupt input.
Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 13.
When both interrupts are enabled, the oscillator restarts as soon as one of the two inputs is held low and power
down exit will be completed when the first input will be released. In this case the higher priority interrupt service
routine is executed.
Once the interrupt is serviced, the next instruction to be executed after RETI will be the one following the instruction
that put TS80C51U2 into power-down mode.
INT0
INT1
XTAL1
Active phase
Power-down phase
Oscillator restart phase
Active phase
Figure 13. Power-Down Exit Waveform
Exit from power-down by reset redefines all the SFRs, exit from power-down by external interrupt does no affect
the SFRs.
Exit from power-down by either reset or external interrupt does not affect the internal RAM content.
NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence is unchanged, when execution is vectored to interrupt,
PD and IDL bits are cleared and idle mode is not entered.
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Table 19. The state of ports during idle and power-down modes
Program
Memory
Mode
ALE
PSEN
PORT0
PORT1
PORT2
PORT3
Idle
Internal
External
Internal
External
1
1
0
0
1
1
0
0
Port Data*
Floating
Port Data
Port Data
Port Data
Port Data
Port Data
Address
Port Data
Port Data
Port Data
Port Data
Idle
Power Down
Power Down
Port Data*
Floating
Port Data
Port Data
* Port 0 can force a "zero" level. A "one" Level will leave port floating.
38
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7.10 Hardware Watchdog Timer
The WDT is intended as a recovery method in situations where the CPU may be subjected to software upset. The
WDT consists of a 14-bit counter and the WatchDog Timer ReSeT (WDTRST) SFR. The WDT is by default
disabled from exiting reset. To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST,
SFR location 0A6H. When WDT is enabled, it will increment every machine cycle while the oscillator is running
and there is no way to disable the WDT except through reset (either hardware reset or WDT overflow reset). When
WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.
7.10.1 Using the WDT
To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When
WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow.
The 14-bit counter overflows when it reaches 16383 (3FFFH) and this will reset the device. When WDT is enabled,
it will increment every machine cycle while the oscillator is running. This means the user must reset the WDT at
least every 16383 machine cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST
is a write only register. The WDT counter cannot be read or written. When WDT overflows, it will generate an
output RESET pulse at the RST-pin. The RESET pulse duration is 96 x T
, where T
= 1/F
. To make
OSC
OSC
OSC
the best use of the WDT, it should be serviced in those sections of code that will periodically be executed within
the time required to prevent a WDT reset.
7
To have a more powerful WDT, a 2 counter has been added to extend the Time-out capability, ranking from
16ms to 2s @ F
= 12MHz. To manage this feature, refer to WDTPRG register description, Table 21. (SFR0A7h).
OSC
Table 20. WDTRST Register
WDTRST Address (0A6h)
7
6
5
4
3
2
1
Reset value
X
X
X
X
X
X
X
Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
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Table 21. WDTPRG Register
WDTPRG Address (0A7h)
7
6
5
4
3
2
1
0
T4
T3
T2
T1
T0
S2
S1
S0
Bit
Number
Bit
Mnemonic
Description
7
6
5
4
3
2
1
0
T4
T3
T2
T1
T0
S2
S1
S0
Reserved
Do not try to set or clear this bit.
WDT Time-out select bit 2
WDT Time-out select bit 1
WDT Time-out select bit 0
S2
0
S1
0
S0
0
Selected Time-out
14
(2 - 1) machine cycles, 16.3 ms @ 12 MHz
15
0
0
1
(2 - 1) machine cycles, 32.7 ms @ 12 MHz
16
0
1
0
(2 - 1) machine cycles, 65.5 ms @ 12 MHz
17
0
1
1
(2 - 1) machine cycles, 131 ms @ 12 MHz
18
1
0
0
(2 - 1) machine cycles, 262 ms @ 12 MHz
19
1
0
1
(2 - 1) machine cycles, 542 ms @ 12 MHz
20
1
1
0
(2 - 1) machine cycles, 1.05 s @ 12 MHz
21
1
1
1
(2 - 1) machine cycles, 2.09 s @ 12 MHz
Reset value XXXX X000
7.10.2 WDT during Power Down and Idle
In Power Down mode the oscillator stops, which means the WDT also stops. While in Power Down mode the
user does not need to service the WDT. There are 2 methods of exiting Power Down mode: by a hardware reset
or via a level activated external interrupt which is enabled prior to entering Power Down mode. When Power
Down is exited with hardware reset, servicing the WDT should occur as it normally should whenever the TS80C51U2
is reset. Exiting Power Down with an interrupt is significantly different. The interrupt is held low long enough for
the oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the WDT from
resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high.
It is suggested that the WDT be reset during the interrupt service routine.
To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best to reset the
WDT just before entering powerdown.
In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the TS80C51U2 while in
Idle mode, the user should always set up a timer that will periodically exit Idle, service the WDT, and re-enter
Idle mode.
40
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TS87C51U2
TM
7.11 ONCE
Mode (ON Chip Emulation)
The ONCE mode facilitates testing and debugging of systems using TS80C51U2 without removing the circuit from
the board. The ONCE mode is invoked by driving certain pins of the TS80C51U2; the following sequence must
be exercised:
● Pull ALE low while the device is in reset (RST high) and PSEN is high.
● Hold ALE low as RST is deactivated.
While the TS80C51U2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 26.
shows the status of the port pins during ONCE mode.
Normal operation is restored when normal reset is applied.
Table 22. External Pin Status during ONCE Mode
ALE
PSEN
Port 0
Port 1
Port 2
Port 3
XTAL1/2
Weak pull-up
Weak pull-up
Float
Weak pull-up
Weak pull-up
Weak pull-up
Active
Rev. D - 15 January, 2001
41
TS80C51U2
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TS87C51U2
7.12 Power-Off Flag
The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset.
A cold start reset is the one induced by V switch-on. A warm start reset occurs while V is still applied to
CC
CC
the device and could be generated for example by an exit from power-down.
The power-off flag (POF) is located in PCON register (See Table 23.). POF is set by hardware when V rises
CC
from 0 to its nominal voltage. The POF can be set or cleared by software allowing the user to determine the type
of reset.
The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading POF bit will
return indeterminate value.
Table 23. PCON Register
PCON - Power Control Register (87h)
7
6
5
-
4
3
2
1
0
SMOD1_0
SMOD0_0
POF
GF1
GF0
PD
IDL
Bit
Number
Bit
Mnemonic
Description
Serial port Mode bit 1 for UART_0
Set to select double baud rate in mode 1, 2 or 3.
7
SMOD1_0
Serial port Mode bit 0 for UART_0
6
SMOD0_0
Clear to select SM0_0 bit in SCON_0 register.
Set to to select FE_0 bit in SCON_0 register.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
4
-
Power-Off Flag
Clear to recognize next reset type.
POF
Set by hardware when V rises from 0 to its nominal voltage. Can also be set by software.
CC
General purpose Flag
3
2
1
0
GF1
GF0
PD
Cleared by user for general purpose usage.
Set by user for general purpose usage.
General purpose Flag
Cleared by user for general purpose usage.
Set by user for general purpose usage.
Power-Down mode bit
Cleared by hardware when reset occurs.
Set to enter power-down mode.
Idle mode bit
IDL
Clear by hardware when interrupt or reset occurs.
Set to enter idle mode.
Reset Value = 00X1 0000b
Not bit addressable
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7.13 Reduced EMI Mode
The ALE signal is used to demultiplex address and data buses on port 0 when used with external program or data
memory. Nevertheless, during internal code execution, ALE signal is still generated. In order to reduce EMI, ALE
signal can be disabled by setting AO bit.
The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer output but
remains active during MOVX and MOVC instructions and external fetches. During ALE disabling, ALE pin is
weakly pulled high.
Table 24. AUXR Register
AUXR - Auxiliary Register (8Eh)
7
6
5
-
4
-
3
-
2
-
1
-
0
M1UA_1
M0UA_1
AO
Bit
Number
Bit Mne-
monic
Description
Multiplex I/Os of UART_1 bit 1
7
M1UA_1
This bit is used in conjunction with M0UA_1 bit to specify where are multiplexed UART_1 pins.
Multiplex I/Os of UART_1 bit 0
This bit is used in conjunction with M1UA_1 bit bit to specify where are multiplexed UART_1 pins.
M1UA_1M0UA_1Result
6
M0UA_1
0
0
1
1
0
1
0
1
UART_1 pins are disabled.
UART_1 pins are located on pins (6, 28) or (12, 34) for 44-package only.
UART_1 pins are alternate functions of P1 located at P1.2 and P1.3.
UART_1 pins are alternate functions of P1 located at P1.6 and P1.7.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
5
4
3
2
1
-
-
-
-
-
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
Reserved
The value read from this bit is indeterminate. Do not set this bit.
ALE Output bit
Clear to restore ALE operation during internal fetches.
Set to disable ALE operation during internal fetches.
0
AO
Reset Value = 00XX XXX0b
Not bit addressable
Rev. D - 15 January, 2001
43
TS80C51U2
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TS87C51U2
8. TS80C51U2 ROM
8.1 ROM Structure
The TS83C51U2 ROM memory is divided in three different arrays:
● the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Kbytes.
● the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes.
● the signature array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 bytes.
8.2 ROM Lock System
The program Lock system, when programmed, protects the on-chip program against software piracy.
8.2.1 Encryption Array
Within the ROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time a
byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This
byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with
the encryption array in the unprogrammed state, will return the code in its original, unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying
the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a
verification routine will display the content of the encryption array. For this reason all the unused code bytes
should be programmed with random values. This will ensure program protection.
8.2.2 Program Lock Bits
The lock bits when programmed according to Table 25. will provide different level of protection for the on-chip
code and data.
Table 25. Program Lock bits
Program Lock Bits
Protection description
Securi-
LB1
LB2
LB3
ty level
No program lock features enabled. Code verify will still be encrypted by the encryption
array if programmed. MOVC instruction executed from external program memory returns
non encrypted data.
1
U
P
U
U
U
U
MOVC instruction executed from external program memory are disabled from fetching
code bytes from internal memory, EA is sampled and latched on reset.
2
U: unprogrammed
P: programmed
8.2.3 Signature bytes
The TS83C51U2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described
in section 10.
8.2.4 Verify Algorithm
Refer to 9.3.4
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TS87C51U2
9. TS87C51U2 EPROM
9.1 EPROM Structure
The TS87C51U2 EPROM is divided in two different arrays:
● the code array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Kbytes.
● the encryption array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 bytes.
In addition a third non programmable array is implemented:
● the signature array: . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 bytes.
9.2 EPROM Lock System
The program Lock system, when programmed, protects the on-chip program against software piracy.
9.2.1 Encryption Array
Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s). Every time
a byte is addressed during program verify, 6 address lines are used to select a byte of the encryption array. This
byte is then exclusive-NOR’ed (XNOR) with the code byte, creating an encrypted verify byte. The algorithm, with
the encryption array in the unprogrammed state, will return the code in its original, unmodified form.
When using the encryption array, one important factor needs to be considered. If a byte has the value FFh, verifying
the byte will produce the encryption byte value. If a large block (>64 bytes) of code is left unprogrammed, a
verification routine will display the content of the encryption array. For this reason all the unused code bytes
should be programmed with random values. This will ensure program protection.
9.2.2 Program Lock Bits
The three lock bits, when programmed according to Table 26., will provide different level of protection for the
on-chip code and data.
Table 26. Program Lock bits
Program Lock Bits
Protection description
Security
LB1
LB2
LB3
level
No program lock features enabled. Code verify will still be encrypted by the encryption
array if programmed. MOVC instruction executed from external program memory
returns non encrypted data.
1
U
U
U
MOVC instruction executed from external program memory are disabled from fetching
code bytes from internal memory, EA is sampled and latched on reset, and further
programming of the EPROM is disabled.
2
P
U
U
3
4
U
U
P
U
P
Same as 2, also verify is disabled.
U
Same as 3, also external execution is disabled.
U: unprogrammed,
P: programmed
WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification.
Rev. D - 15 January, 2001
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TS80C51U2
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TS87C51U2
9.2.3 Signature bytes
The TS87C51U2 contains 4 factory programmed signatures bytes. To read these bytes, perform the process described
in section 10.
9.3 EPROM Programming
9.3.1 Set-up modes
In order to program and verify the EPROM or to read the signature bytes, the TS87C51U2 is placed in specific
set-up modes (See Figure 14.).
Control and program signals must be held at the levels indicated in Table 27.
9.3.2 Definition of terms
Address Lines:P1.0-P1.7, P2.0-P2.5 respectively for A0-A13.
Data Lines:P0.0-P0.7 for D0-D7
Control Signals:RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7.
Program Signals:ALE/PROG, EA/VPP.
Table 27. EPROM Set-Up Modes
ALE/
PROG
EA/
VPP
Mode
RST
PSEN
P2.6
P2.7
P3.3
P3.6
P3.7
Program Code data
1
0
12.75V
1
0
1
1
1
1
Verify Code data
1
1
1
1
1
1
0
0
0
0
0
0
1
1
0
0
0
1
1
1
0
1
0
1
1
1
1
0
0
1
0
1
1
1
0
1
0
0
Program Encryption Array
Address 0-3Fh
12.75V
1
1
Read Signature Bytes
Program Lock bit 1
Program Lock bit 2
Program Lock bit 3
12.75V
12.75V
12.75V
1
1
0
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Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
+5V
EA/VPP
VCC
PROGRAM
SIGNALS*
ALE/PROG
P0.0-P0.7
D0-D7
RST
PSEN
P2.6
P2.7
P3.3
P3.6
P3.7
P1.0-P1.7
P2.0-P2.5
A0-A7
CONTROL
SIGNALS*
A8-A13
4 to 6 MHz
XTAL1
VSS
GND
* See Table 31. for proper value on these inputs
Figure 14. Set-Up Modes Configuration
9.3.3 Programming Algorithm
The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the number of pulses
applied during byte programming from 25 to 1.
To program the TS87C51U2 the following sequence must be exercised:
● Step 1: Activate the combination of control signals.
● Step 2: Input the valid address on the address lines.
● Step 3: Input the appropriate data on the data lines.
● Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V).
● Step 5: Pulse ALE/PROG once.
● Step 6: Lower EA/VPP from VPP to VCC
Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is
reached (See Figure 15.).
9.3.4 Verify algorithm
Code array verify must be done after each byte or block of bytes is programmed. In either case, a complete verify
of the programmed array will ensure reliable programming of the TS87C51U2.
P 2.7 is used to enable data output.
To verify the TS87C51U2 code the following sequence must be exercised:
● Step 1: Activate the combination of program and control signals.
● Step 2: Input the valid address on the address lines.
● Step 3: Read data on the data lines.
Repeat step 2 through 3 changing the address for the entire array verification (See Figure 15.)
The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the
code array is well encrypted.
Rev. D - 15 January, 2001
47
TS80C51U2
TS83C51U2
TS87C51U2
Programming Cycle
Read/Verify Cycle
Data Out
A0-A12
D0-D7
Data In
100µs
ALE/PROG
EA/VPP
12.75V
5V
0V
Control sig-
nals
Figure 15. Programming and Verification Signal’s Waveform
9.4 EPROM Erasure (Windowed Packages Only)
Erasing the EPROM erases the code array, the encryption array and the lock bits returning the parts to full
functionality.
Erasure leaves all the EPROM cells in a 1’s state (FF).
9.4.1 Erasure Characteristics
The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an integrated dose at least 15
2
2
W-sec/cm . Exposing the EPROM to an ultraviolet lamp of 12,000 µW/cm rating for 30 minutes, at a distance
of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers.
Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength shorter than approximately
4,000 Å. Since sunlight and fluorescent lighting have wavelengths in this range, exposure to these light sources
over an extended time (about 1 week in sunlight, or 3 years in room-level fluorescent lighting) could cause
inadvertent erasure. If an application subjects the device to this type of exposure, it is suggested that an opaque
label be placed over the window.
48
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TS80C51U2
TS83C51U2
TS87C51U2
10. Signature Bytes
The TS83/87C51U2 has four signature bytes in location 30h, 31h, 60h and 61h. To read these bytes follow the
procedure for EPROM verify but activate the control lines provided in Table 27. for Read Signature Bytes. Table
28. shows the content of the signature byte for the TS83/87C51U2.
Table 28. Signature Bytes Content
Location
30h
Contents
58h
Comment
Manufacturer Code: Atmel Wireless & Microcontrollers
Family Code: C51 X2
31h
57h
60h
2Bh
Product name: TS83C51U2
60h
ABh
Product name: TS87C51U2
61h
FFh
Product revision number
Rev. D - 15 January, 2001
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TS87C51U2
11. Electrical Characteristics
(1)
11.1 Absolute Maximum Ratings
Ambiant Temperature Under Bias:
C = commercial
0°C to 70°C
I = industrial
Storage Temperature
Voltage on V to V
Voltage on V to V
-40°C to 85°C
-65°C to + 150°C
-0.5 V to + 7 V
-0.5 V to + 13 V
CC
SS
PP
SS
Voltage on Any Pin to V
Power Dissipation
-0.5 V to V + 0.5 V
1 W
SS
CC
(2)
NOTES
1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not
implied. Exposure to absolute maximum rating conditions may affect device reliability.
2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
11.2 Power consumption measurement
Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset,
which made sense for the designs were the CPU was running under reset. In Atmel Wireless & Microcontrollers
new devices, the CPU is no more active during reset, so the power consumption is very low but is not really
representative of what will happen in the customer system. That’s why, while keeping measurements under Reset,
Atmel Wireless & Microcontrollers presents a new way to measure the operating Icc:
Using an internal test ROM, the following code is executed:
Label:
SJMP Label (80 FE)
Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not connected and XTAL1
is driven by the clock.
This is much more representative of the real operating Icc.
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Rev. D - 15 January, 2001
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TS87C51U2
11.3 DC Parameters for Standard Voltage
TA = 0°C to +70°C; V = 0 V; V = 5 V ± 10%; F = 0 to 40 MHz.
SS
CC
TA = -40°C to +85°C; V = 0 V; V = 5 V ± 10%; F = 0 to 40 MHz.
SS
CC
Table 29. DC Parameters in Standard Voltage
Symbol
Parameter
Min
Typ
Max
Unit
V
Test Conditions
V
Input Low Voltage
-0.5
0.2 V - 0.1
CC
IL
V
Input High Voltage except XTAL1, RST
Input High Voltage, XTAL1, RST
0.2 V + 0.9
V
V
+ 0.5
+ 0.5
V
IH
CC
CC
CC
V
0.7 V
V
IH1
CC
(6)
(4)
V
0.3
V
V
V
OL
Output Low Voltage, ports 1, 2, 3
I
I
I
= 100 µA
OL
OL
OL
0.45
1.0
(4)
= 1.6 mA
= 3.5 mA
(4)
(6)
(4)
(4)
(4)
V
V
0.3
0.45
1.0
V
V
V
OL1
OL2
Output Low Voltage, port 0
I
I
I
= 200 µA
= 3.2 mA
= 7.0 mA
OL
OL
OL
(4)
(4)
(4)
Output Low Voltage, ALE, PSEN
Output High Voltage, ports 1, 2, 3
0.3
0.45
1.0
V
V
V
I
I
I
= 100 µA
= 1.6 mA
= 3.5 mA
OL
OL
OL
V
V
V
V
- 0.3
- 0.7
- 1.5
V
V
V
I
I
I
= -10 µA
= -30 µA
= -60 µA
OH
CC
CC
CC
OH
OH
OH
V
= 5 V ± 10%
CC
V
V
R
Output High Voltage, port 0
V
V
V
- 0.3
- 0.7
- 1.5
V
V
V
I
I
I
= -200 µA
= -3.2 mA
= -7.0 mA
= 5 V ± 10%
OH1
OH2
RST
CC
CC
CC
OH
OH
OH
V
CC
Output High Voltage,ALE, PSEN
V
V
V
- 0.3
- 0.7
- 1.5
V
V
V
I
I
I
= -100 µA
= -1.6 mA
= -3.5 mA
= 5 V ± 10%
CC
CC
CC
OH
OH
OH
V
CC
(5)
RST Pulldown Resistor
50
200
-50
kΩ
µA
µA
µA
pF
90
I
Logical 0 Input Current ports 1, 2 and 3
Input Leakage Current
Vin = 0.45 V
0.45 V < Vin < V
Vin = 2.0 V
IL
LI
I
±10
-650
10
CC
I
Logical 1 to 0 Transition Current, ports 1, 2, 3
Capacitance of I/O Buffer
TL
C
Fc = 1 MHz
TA = 25°C
IO
(5)
(3)
I
Power Down Current
50
µA
PD
20
2.0 V < V
5.5 V
CC <
I
Power Supply Current Maximum values, X1
mode:
1 + 0.4 Freq
(MHz)
@12MHz 5.8
CC
(7)
(1)
V
= 5.5 V
CC
under
RESET
mA
@16MHz 7.4
Rev. D - 15 January, 2001
51
TS80C51U2
TS83C51U2
TS87C51U2
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
I
Power Supply Current Maximum values, X1
mode:
3 + 0.6 Freq
(MHz)
@12MHz 10.2
@16MHz 12.6
CC
(7)
(8)
mA
operating
V
V
= 5.5 V
CC
CC
I
Power Supply Current Maximum values, X1
mode:
0.25+0.3Freq
(MHz)
@12MHz 3.9
@16MHz 5.1
CC
(7)
(2)
mA
idle
= 5.5 V
11.4 DC Parameters for Low Voltage
TA = 0°C to +70°C; V = 0 V; V = 2.7 V to 5.5 V ; F = 0 to 30 MHz.
SS
CC
TA = -40°C to +85°C; V = 0 V; V = 2.7 V to 5.5 V ; F = 0 to 30 MHz.
SS
CC
Table 30. DC Parameters for Low Voltage
Symbol
Parameter
Min
Typ
Max
Unit
V
Test Conditions
V
Input Low Voltage
-0.5
0.2 V - 0.1
CC
IL
V
Input High Voltage except XTAL1, RST
Input High Voltage, XTAL1, RST
0.2 V + 0.9
V
V
+ 0.5
+ 0.5
V
IH
CC
CC
CC
V
0.7 V
V
IH1
CC
(6)
(4)
V
0.45
V
OL
Output Low Voltage, ports 1, 2, 3
I
= 0.8 mA
OL
(6)
(4)
V
0.45
V
OL1
Output Low Voltage, port 0, ALE, PSEN
Output High Voltage, ports 1, 2, 3
Output High Voltage, port 0, ALE, PSEN
Logical 0 Input Current ports 1, 2 and 3
Input Leakage Current
I
I
I
= 1.6 mA
= -10 µA
= -40 µA
OL
OH
OH
V
0.9 V
0.9 V
V
OH
CC
CC
V
V
OH1
I
-50
±10
-650
200
10
µA
µA
µA
kΩ
pF
Vin = 0.45 V
IL
LI
I
0.45 V < Vin < V
Vin = 2.0 V
CC
I
Logical 1 to 0 Transition Current, ports 1, 2, 3
RST Pulldown Resistor
TL
RST
(5)
R
50
90
CIO
Capacitance of I/O Buffer
Fc = 1 MHz
TA = 25°C
(5)
(3)
(3)
I
Power Down Current
µA
PD
20
V
V
= 2.0 V to 5.5 V
50
30
CC
CC
(5)
10
= 2.0 V to 3.3 V
I
Power Supply Current Maximum values, X1
mode:
1 + 0.2 Freq
(MHz)
@12MHz 3.4
CC
(7)
(1)
V
V
= 3.3 V
under
CC
CC
mA
mA
RESET
@16MHz 4.2
I
Power Supply Current Maximum values, X1
1 + 0.3 Freq
(MHz)
@12MHz 4.6
CC
(7)
(8)
mode:
= 3.3 V
operating
@16MHz 5.8
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Rev. D - 15 January, 2001
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TS87C51U2
Symbol
Parameter
Min
Typ
Max
Unit
Test Conditions
I
Power Supply Current Maximum values, X1
mode:
0.15 Freq
(MHz) + 0.2
CC
(7)
(2)
mA
idle
V
= 3.3 V
CC
@12MHz 2
@16MHz 2.6
NOTES
1.
I
under reset is measured with all output pins disconnected; XTAL1 driven with T
, T
= 5 ns (see Figure 20.), V = V + 0.5 V,
CC
CLCH CHCL IL SS
V
= V - 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V . I would be slightly higher if a crystal oscillator used..
CC CC CC
IH
2. Idle I is measured with all output pins disconnected; XTAL1 driven with T
, T
= 5 ns, V = V + 0.5 V, V = V - 0.5 V; XTAL2
CC
CLCH CHCL IL SS IH CC
N.C; Port 0 = V ; EA = RST = V (see Figure 18.).
CC
SS
3. Power Down I is measured with all output pins disconnected; EA = V , PORT 0 = V ; XTAL2 NC.; RST = V (see Figure 19.).
CC
SS
CC
SS
4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V s of ALE and Ports 1 and 3. The noise is
OL
due to external bus capacitance discharging into the Port 0 and Port 2 pins when these pins make 1 to 0 transitions during bus operation. In the worst
cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi V peak 0.6V. A Schmitt Trigger use is not necessary.
OL
5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V.
6. Under steady state (non-transient) conditions, I must be externally limited as follows:
OL
Maximum I per port pin: 10 mA
OL
Maximum I per 8-bit port:
OL
Port 0: 26 mA
Ports 1, 2 and 3: 15 mA
Maximum total I for all output pins: 71 mA
OL
If I exceeds the test condition, V may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
OL
OL
7. For other values, please contact your sales office.
8. Operating I is measured with all output pins disconnected; XTAL1 driven with T
, T
= 5 ns (see Figure 20.), V = V + 0.5 V,
IL SS
CC
CLCH CHCL
V
= V - 0.5V; XTAL2 N.C.; EA = Port 0 = V ; RST = V . The internal ROM runs the code 80 FE (label: SJMP label). I would be slightly
CC CC SS CC
IH
higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case.
V
CC
I
CC
V
CC
V
CC
P0
EA
V
CC
RST
XTAL2
XTAL1
(NC)
CLOCK
SIGNAL
V
SS
All other pins are disconnected.
Figure 16. I
Test Condition, under reset
CC
Rev. D - 15 January, 2001
53
TS80C51U2
TS83C51U2
TS87C51U2
V
CC
I
CC
V
CC
V
CC
P0
EA
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
XTAL2
XTAL1
(NC)
CLOCK
SIGNAL
All other pins are disconnected.
V
SS
Figure 17. Operating I
Test Condition
CC
V
CC
I
CC
V
CC
V
CC
P0
EA
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
(NC)
XTAL2
XTAL1
CLOCK
SIGNAL
All other pins are disconnected.
V
SS
Figure 18. I
Test Condition, Idle Mode
CC
V
CC
I
CC
V
CC
V
CC
P0
EA
Reset = Vss after a high pulse
during at least 24 clock cycles
RST
(NC)
XTAL2
XTAL1
V
All other pins are disconnected.
SS
Figure 19. I
Test Condition, Power-Down Mode
CC
V
-0.5V
CC
0.7V
CC
0.2V -0.1
CC
0.45V
T
T
CLCH
CHCL
T
= T
= 5ns.
CHCL
CLCH
Figure 20. Clock Signal Waveform for I
Tests in Active and Idle Modes
CC
54
Rev. D - 15 January, 2001
TS80C51U2
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TS87C51U2
11.5 AC Parameters
11.5.1 Explanation of the AC Symbols
Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The other characters,
depending on their positions, stand for the name of a signal or the logical status of that signal. The following is
a list of all the characters and what they stand for.
Example:T
= Time for Address Valid to ALE Low.
AVLL
T
= Time for ALE Low to PSEN Low.
LLPL
TA = 0 to +70°C (commercial temperature range); V = 0 V; V = 5 V ± 10%; -M and -V ranges.
SS
CC
TA = -40°C to +85°C (industrial temperature range); V = 0 V; V = 5 V ± 10%; -M and -V ranges.
SS
CC
TA = 0 to +70°C (commercial temperature range); V = 0 V; 2.7 V < V
5.5 V; -L range.
SS
CC <
TA = -40°C to +85°C (industrial temperature range); V = 0 V; 2.7 V < V
5.5 V; -L range.
SS
CC <
Table 31. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE and PSEN signals.
Timings will be guaranteed if these capacitances are respected. Higher capacitance values can be used, but timings
will then be degraded.
Table 31. Load Capacitance versus speed range, in pF
-M
100
80
-V
50
50
30
-L
100
80
Port 0
Port 1, 2, 3
ALE / PSEN
100
100
Table 33., Table 36. and Table 39. give the description of each AC symbols.
Table 34., Table 37. and Table 40. give for each range the AC parameter.
Table 35., Table 38. and Table 41. give the frequency derating formula of the AC parameter. To calculate each
AC symbols, take the x value corresponding to the speed grade you need (-M, -V or -L) and replace this value
in the formula. Values of the frequency must be limited to the corresponding speed grade:
Table 32. Max frequency for derating formula regarding the speed grade
-M X1 mode
-M X2 mode
-V X1 mode
-V X2 mode
-L X1 mode
-L X2 mode
Freq (MHz)
T (ns)
40
25
20
50
40
25
30
30
20
50
33.3
33.3
Example:
E6
T
in X2 mode for a -V part at 20 MHz (T = 1/20 = 50 ns):
LLIV
x= 22 (Table 35.)
T= 50ns
T
= 2T - x = 2 x 50 - 22 = 78ns
LLIV
Rev. D - 15 January, 2001
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TS80C51U2
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11.5.2 External Program Memory Characteristics
Table 33. Symbol Description
Symbol
Parameter
T
Oscillator clock period
ALE pulse width
T
LHLL
T
Address Valid to ALE
AVLL
T
Address Hold After ALE
ALE to Valid Instruction In
ALE to PSEN
LLAX
T
LLIV
LLPL
PLPH
T
T
PSEN Pulse Width
T
PSEN to Valid Instruction In
Input Instruction Hold After PSEN
Input Instruction FloatAfter PSEN
PSEN to Address Valid
PLIV
PXIX
T
T
PXIZ
T
PXAV
T
Address to Valid Instruction In
PSEN Low to Address Float
AVIV
T
PLAZ
Table 34. AC Parameters for Fix Clock
Speed
-M
-V
-V
-L
-L
Units
40 MHz
X2 mode
30 MHz
standard mode
40 MHz
X2 mode
20 MHz
standard mode
30 MHz
60 MHz equiv.
40 MHz equiv.
Symbol
Min
Max
Min
33
Max
Min
25
Max
Min
50
Max
Min
33
Max
T
25
40
ns
ns
T
25
42
35
52
LHLL
T
10
10
4
4
12
12
5
5
13
13
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
AVLL
T
LLAX
T
70
35
45
25
78
50
65
30
98
55
LLIV
LLPL
PLPH
T
T
15
55
9
17
60
10
50
18
75
35
T
PLIV
PXIX
T
0
0
0
0
0
T
18
85
10
12
53
10
20
95
10
10
80
10
18
122
10
PXIZ
T
AVIV
PLAZ
T
56
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
Table 35. AC Parameters for a Variable Clock: derating formula
Symbol
Type
Standard X2 Clock
Clock
-M
-V
-L
Units
T
Min
Min
Min
Max
Min
Min
Max
Min
Max
Max
Max
2 T - x
T - x
T - x
4 T - x
T - x
3 T - x
3 T - x
x
T - x
0.5 T - x
0.5 T - x
2 T - x
0.5 T - x
1.5 T - x
1.5 T - x
x
10
15
15
30
10
20
40
0
8
15
20
20
35
15
25
45
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
LHLL
T
13
13
22
8
AVLL
T
LLAX
T
LLIV
LLPL
PLPH
T
T
15
25
0
T
PLIV
T
PXIX
T
T - x
5 T - x
x
0.5 T - x
2.5 T - x
x
7
5
15
45
10
PXIZ
T
40
10
30
10
AVIV
PLAZ
T
11.5.3 External Program Memory Read Cycle
12 T
CLCL
T
T
LLIV
LHLL
ALE
PSEN
T
LLPL
T
PLPH
T
PXAV
T
T
LLAX
T
T
PXIZ
PLIV
AVLL
T
TPLAZ
PXIX
PORT 0
PORT 2
INSTR IN
A0-A7
INSTR IN
A0-A7
INSTR IN
T
AVIV
ADDRESS
OR SFR-P2
ADDRESS A8-A15
ADDRESS A8-A15
Figure 21. External Program Memory Read Cycle
Rev. D - 15 January, 2001
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11.5.4 External Data Memory Characteristics
Table 36. Symbol Description
Symbol
Parameter
T
RD Pulse Width
RLRH
T
WR Pulse Width
WLWH
T
RD to Valid Data In
RLDV
RHDX
T
Data Hold After RD
Data Float After RD
ALE to Valid Data In
Address to Valid Data In
ALE to WR or RD
T
RHDZ
T
LLDV
T
AVDV
T
LLWL
T
Address to WR or RD
Data Valid to WR Transition
Data set-up to WR High
Data Hold After WR
RD Low to Address Float
RD or WR High to ALE high
AVWL
QVWX
QVWH
WHQX
T
T
T
T
RLAZ
T
WHLH
58
Rev. D - 15 January, 2001
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TS87C51U2
Table 37. AC Parameters for a Fix Clock
Speed
-M
-V
-V
-L
-L
Units
40 MHz
X2 mode
30 MHz
standard mode
40 MHz
X2 mode
20 MHz
standard mode
30 MHz
60 MHz equiv.
40 MHz equiv.
Symbol
Min
Max
Min
85
Max
Min
135
Max
Min
125
Max
Min
175
Max
T
130
130
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
T
T
85
135
125
175
WLWH
T
100
60
102
95
137
RLDV
0
0
0
0
0
RHDX
T
30
18
98
35
165
175
95
25
42
RHDZ
T
160
165
100
155
160
105
222
235
130
LLDV
T
100
70
AVDV
T
50
75
30
47
7
55
80
45
70
5
70
103
13
LLWL
T
AVWL
QVWX
QVWH
WHQX
T
T
T
10
15
160
15
107
9
165
17
155
10
213
18
T
0
0
0
0
0
RLAZ
T
10
40
7
27
15
35
5
45
13
53
WHLH
Rev. D - 15 January, 2001
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TS80C51U2
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TS87C51U2
Table 38. AC Parameters for a Variable Clock: derating formula
Symbol
Type
Standard X2 Clock
Clock
-M
-V
-L
Units
T
Min
Min
Max
Min
Max
Max
Max
Min
Max
Min
Min
Min
Min
Max
Min
Max
6 T - x
6 T - x
5 T - x
x
3 T - x
3 T - x
2.5 T - x
x
20
20
25
0
15
15
23
0
25
25
30
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
RLRH
T
WLWH
T
RLDV
T
RHDX
T
2 T - x
8 T - x
9 T - x
3 T - x
3 T + x
4 T - x
T - x
T - x
20
40
60
25
25
25
15
15
10
0
15
35
50
20
20
20
10
10
8
25
45
65
30
30
30
20
20
15
0
RHDZ
T
4T -x
LLDV
T
4.5 T - x
1.5 T - x
1.5 T + x
2 T - x
0.5 T - x
3.5 T - x
0.5 T - x
x
AVDV
T
LLWL
LLWL
T
T
AVWL
QVWX
QVWH
WHQX
T
T
T
7 T - x
T - x
T
x
0
RLAZ
WHLH
WHLH
T
T
T - x
0.5 T - x
0.5 T + x
15
15
10
10
20
20
T + x
11.5.5 External Data Memory Write Cycle
T
WHLH
ALE
PSEN
WR
T
T
LLWL
WLWH
T
QVWX
T
T
T
QVWH
WHQX
LLAX
PORT 0
PORT 2
A0-A7
DATA OUT
T
AVWL
ADDRESS
OR SFR-P2
ADDRESS A8-A15 OR SFR P2
Figure 22. External Data Memory Write Cycle
60
Rev. D - 15 January, 2001
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11.5.6 External Data Memory Read Cycle
T
WHLH
T
ALE
PSEN
RD
LLDV
T
T
RLRH
LLWL
T
RLDV
T
RHDZ
T
AVDV
T
T
LLAX
RHDX
PORT 0
PORT 2
A0-A7
DATA IN
T
RLAZ
T
AVWL
ADDRESS
OR SFR-P2
ADDRESS A8-A15 OR SFR P2
Figure 23. External Data Memory Read Cycle
11.5.7 Serial Port Timing - Shift Register Mode
Table 39. Symbol Description
Symbol
Parameter
T
T
T
Serial port clock cycle time
XLXL
QVHX
XHQX
Output data set-up to clock rising edge
Output data hold after clock rising edge
Input data hold after clock rising edge
TXHDX
T
Clock rising edge to input data valid
XHDV
Table 40. AC Parameters for a Fix Clock
Speed
-M
40 MHz
-V
X2 mode
30 MHz
-V
-L
X2 mode
20 MHz
-L
Units
standard mode
40 MHz
standard mode
30 MHz
60 MHz equiv.
40 MHz equiv.
Symbol
Min
Max
Min
200
117
13
Max
Min
300
200
30
Max
Min
300
200
30
Max
Min
400
283
47
Max
T
300
200
30
ns
ns
ns
ns
ns
XLXL
QVHX
XHQX
XHDX
XHDV
T
T
T
T
0
0
0
0
0
117
34
117
117
200
Rev. D - 15 January, 2001
61
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TS87C51U2
Table 41. AC Parameters for a Variable Clock: derating formula
Symbol
Type
Standard X2 Clock
Clock
-M
-V
-L
Units
T
Min
Min
Min
Min
Max
12 T
10 T - x
2 T - x
x
6 T
5 T - x
T - x
x
ns
ns
ns
ns
ns
XLXL
QVHX
XHQX
XHDX
XHDV
T
T
T
T
50
20
0
50
20
0
50
20
0
10 T - x
5 T- x
133
133
133
11.5.8 Shift Register Timing Waveforms
0
1
2
3
4
5
6
7
8
INSTRUCTION
ALE
T
XLXL
CLOCK
T
XHQX
T
QVXH
0
1
2
3
4
5
6
7
OUTPUT DATA
T
SET TI
XHDX
T
XHDV
WRITE to SBUF
INPUT DATA
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
SET RI
CLEAR RI
Figure 24. Shift Register Timing Waveforms
62
Rev. D - 15 January, 2001
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11.5.9 EPROM Programming and Verification Characteristics
TA = 21°C to 27°C; V = 0V; V = 5V ± 10% while programming. V = operating range while verifying
SS
CC
CC
Table 42. EPROM Programming Parameters
Symbol
Parameter
Min
Max
13
Units
V
V
Programming Supply Voltage
Programming Supply Current
Oscillator Frquency
12.5
PP
I
75
mA
PP
1/T
4
6
MHz
CLCL
T
Address Setup to PROG Low
Adress Hold after PROG
Data Setup to PROG Low
Data Hold after PROG
48 T
CLCL
AVGL
GHAX
T
48 TCLCL
48 TCLCL
48 TCLCL
T
T
DVGL
GHDX
T
(Enable) High to V
48 T
CLCL
EHSH
SHGL
PP
T
T
T
VPP Setup to PROG Low
VPP Hold after PROG
PROG Width
10
µs
µs
µs
10
90
GHSL
110
GLGH
T
Address to Valid Data
ENABLE Low to Data Valid
Data Float after ENABLE
48 TCLCL
48 TCLCL
48 TCLCL
AVQV
T
ELQV
EHQZ
T
0
11.5.10 EPROM Programming and Verification Waveforms
PROGRAMMING
VERIFICATION
ADDRESS
P1.0-P1.7
ADDRESS
P2.0-P2.5
P3.4-P3.5*
T
AVQV
DATA OUT
P0
DATA IN
T
T
GHDX
DVGL
AVGL
T
T
GHAX
ALE/PROG
T
T
SHGL
GHSL
T
GLGH
V
EA/V
PP
PP
V
V
CC
CC
T
T
T
EHSH
EHQZ
ELQV
CONTROL
SIGNALS
(ENABLE)
* 8KB: up to P2.4, 16KB: up to P2.5, 32KB: up to P3.4, 64KB: up to P3.5
Figure 25. EPROM Programming and Verification Waveforms
Rev. D - 15 January, 2001
63
TS80C51U2
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TS87C51U2
11.5.11 External Clock Drive Characteristics (XTAL1)
Table 43. AC Parameters
Symbol
Parameter
Min
25
5
Max
Units
ns
T
Oscillator Period
High Time
Low Time
CLCL
T
ns
CHCX
T
T
T
5
ns
CLCX
CLCH
CHCL
Rise Time
5
5
ns
Fall Time
ns
T
/T
Cyclic ratio in X2 mode
40
60
%
CHCX CLCX
11.5.12 External Clock Drive Waveforms
V
-0.5 V
CC
0.7V
CC
0.2V -0.1 V
0.45 V
T
CHCX
CC
T
T
T
CHCL
CLCH
CLCX
T
CLCL
Figure 26. External Clock Drive Waveforms
11.5.13 AC Testing Input/Output Waveforms
V
-0.5 V
CC
0.2V +0.9
CC
INPUT/OUTPUT
0.2V -0.1
CC
0.45 V
Figure 27. AC Testing Input/Output Waveforms
AC inputs during testing are driven at V - 0.5 for a logic “1” and 0.45V for a logic “0”. Timing measurement
CC
are made at V min for a logic “1” and V max for a logic “0”.
IH
IL
11.5.14 Float Waveforms
FLOAT
V
-0.1 V
+0.1 V
OH
V
V
V
+0.1 V
-0.1 V
LOAD
LOAD
LOAD
V
OL
Figure 28. Float Waveforms
64
Rev. D - 15 January, 2001
TS80C51U2
TS83C51U2
TS87C51U2
For timing purposes as port pin is no longer floating when a 100 mV change from load voltage occurs and begins
to float when a 100 mV change from the loaded V /V level occurs. I /I
≥ ± 20mA.
OH OL
OL OH
11.5.15 Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two.
STATE1
P1 P2
STATE2
STATE3
STATE4
P1 P2 P1
STATE4
P1 P2
STATE5
P1 P2
STATE6
P1 P2
STATE5
INTERNAL
CLOCK
P1
P2 P1 P2
P2
XTAL2
ALE
THESE SIGNALS ARE NOT ACTIVATED DURING THE
EXECUTION OF A MOVX INSTRUCTION
EXTERNAL PROGRAM MEMORY FETCH
PSEN
PCL OUT
PCL OUT
PCL OUT
DATA
P0
DATA
SAMPLED
DATA
SAMPLED
SAMPLED
FLOAT
FLOAT
FLOAT
INDICATES ADDRESS TRANSITIONS
P2 (EXT)
READ CYCLE
RD
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
P0
P2
DPL OR Rt OUT
FLOAT
INDICATES DPH OR P2 SFR TO PCH TRANSITION
WRITE CYCLE
WR
PCL OUT (EVEN IF PROGRAM
MEMORY IS INTERNAL)
P0
DPL OR Rt OUT
DATA OUT
PCL OUT (IF PROGRAM
MEMORY IS EXTERNAL)
INDICATES DPH OR P2 SFR TO PCH TRANSITION
P2
PORT OPERATION
OLD DATA
P0 PINS SAMPLED
NEW DATA
P0 PINS SAMPLED
MOV DEST P0
P1, P2, P3 PINS SAMPLED
RXD SAMPLED
P1, P2, P3 PINS SAMPLED
MOV DEST PORT (P1, P2, P3)
(INCLUDES INT0, INT1, TO, T1)
RXD SAMPLED
SERIAL PORT SHIFT CLOCK
TXD (MODE 0)
Figure 29. Clock Waveforms
This diagram indicates when signals are clocked internally. The time it takes the signals to propagate to the pins,
however, ranges from 25 to 125 ns. This propagation delay is dependent on variables such as temperature and pin
loading. Propagation also varies from output to output and component. Typically though (T =25°C fully loaded)
A
RD and WR propagation delays are approximately 50ns. The other signals are typically 85 ns. Propagation delays
are incorporated in the AC specifications.
Rev. D - 15 January, 2001
65
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12. Ordering Information
TS
R
-V
87C51U2
B
I
-V:
-L:
VCC: 5V +/- 10%
40 MHz, X1 mode
30 MHz, X2 mode
VCC: 2.7 to 5.5 V
30 MHz, X1 mode
20 MHz, X2 mode
Packages:
A: PDIL 40
B: PLCC 44
E: VQFP 44 (1.4mm)
-E : Samples
J: Window CDIL 40*
K: Window CQPJ 44*
Conditioning
R: Tape & Reel
D: Dry Pack
B: Tape & Reel and
Dry Pack
Part Number
TS80C51U2:
ROMless
TS83C51U2zzz: 16k ROM, zzz is the customer code
TS87C51U2:
16k OTP EPROM
Temperature Range
I: Commercial and Industrial -40 to 85oC
(*) Check with Atmel Wireless & Microcontrollers Sales Office for availability - Ceramic parts only for OTP (TS87C51U2)
Ceramic packages (J, K) are available for prototyping, not for volume production.
Table 44. Maximum Clock Frequency
-M
-V
-L
Unit
Code
Standard Mode, oscillator frequency
Standard Mode, internal frequency
40
40
40
40
30
30
MHz
X2 Mode, oscillator frequency
X2 Mode, internal equivalent frequency
20
40
30
60
20
40
MHz
66
Rev. D - 15 January, 2001
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TS83C51U2
TS87C51U2
Table 45. Possible Ordering Entries
TS80C51U2 ROMless
TS83C51U2zzz 16K ROM
TS87C51U2 16K OTP
-VIA
-VIB
-VIE
-LIA
-LIB
-LIE
-EA
-EB
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
-EE
-EJ
-EK
● -Ex for samples
● Tape and Reel available for B and E packages
● Dry pack mandatory for E packages
Rev. D - 15 January, 2001
67
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