TS87C58X2_14_技术文档

Features

• 80C52 Compatible

• 8051 pin and instruction compatible

• Four 8-bit I/O ports

• Three 16-bit timer/counters

• 256 bytes scratchpad RAM

• High-Speed Architecture

• 40 MHz @ 5V, 30MHz @ 3V

• X2 Speed Improvement capability (6 clocks/machine cycle)

– 30 MHz @ 5V, 20 MHz @ 3V (Equivalent to

– 60 MHz @ 5V, 40 MHz @ 3V)

8-bit CMOS

Microcontroller

16/32 Kbytes

ROM/OTP

• Dual Data Pointer

• On-chip ROM/EPROM (16K-bytes, 32K-bytes)

• Programmable Clock Out and Up/Down Timer/Counter 2

• Hardware Watchdog Timer (One-time enabled with Reset-Out)

• Asynchronous port reset

• Interrupt Structure with

• 6 Interrupt sources

TS80C54/58X2

TS87C54/58X2

AT80C54/58X2

AT87C54/58X2

• 4 level priority interrupt system

• Full duplex Enhanced UART

• Framing error detection

• Automatic address recognition

• Low EMI (inhibit ALE)

• Power Control modes

• Idle mode

• Power-down mode

• Power-off Flag

• Once mode (On-chip Emulation)

• Power supply: 4.5-5.5V, 2.7-5.5V

• Temperature ranges: Commercial (0 to 70^oC) and Industrial (-40 to 85^oC)

• Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP44 F1, CQPJ44 (window), CDIL40

(window)

1. Description

TS80C54/58X2 is high performance CMOS ROM, OTP and EPROM versions of the

80C51 CMOS single chip 8-bit microcontroller.

The TS80C54/58X2 retains all features of the Atmel 80C51 with extended

ROM/EPROM capacity (16/32 Kbytes), 256 bytes of internal RAM, a 6-source , 4-level

interrupt system, an on-chip oscilator and three timer/counters.

In addition, the TS80C54/58X2 a Hardware Watchdog Timer, a more versatile serial

channel that facilitates multiprocessor communication (EUART) and a X2 speed

improvement mechanism.

The fully static design of the TS80C54/58X2 allows to reduce system power consump-

tion by bringing the clock frequency down to any value, even DC, without loss of data.

Rev. 4431E–8051–04/06

The TS80C54/58X2 has 2 software-selectable modes of reduced activity for further reduction in

power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the

interrupt system are still operating. In the power-down mode the RAM is saved and all other

functions are inoperative.

PDIL40

PLCC44

PQFP44 F1

VQFP44 1.4

ROM (bytes)

EPROM (bytes)

TS80C54X2

TS80C58X2

16k

32k

0

TS87C54X2

TS87C58X2

0

16k

32k

2. Block Diagram

(2) (2)

(1) (1)

XTAL1

XTAL2

ROM

RAM

256x8

/EPROM

EUART

Timer2

16/32Kx8

ALE/PROG

PSEN

C51

CORE

IB-bus

CPU

EA/VPP

(2)

Timer 0

Timer 1

Parallel I/O Ports

INT

Ctrl

Watch

Dog

RD

Port 0Port 1

Port 3

Port 2

WR

(2) (2)

(1): Alternate function of Port 1

(2): Alternate function of Port 3

2

AT/TS8xC54/8X2

4431E–8051–04/06

AT/TS8xC54/8X2

4. SFR Mapping

The Special Function Registers (SFRs) of the TS80C54/58X2 fall into the following categories:

• C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1

• I/O port registers: P0, P1, P2, P3

• Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L,

RCAP2H

• Serial I/O port registers: SADDR, SADEN, SBUF, SCON

• Power and clock control registers: PCON

• HDW Watchdog Timer Reset: WDTRST, WDTPRG

• Interrupt system registers: IE, IP, IPH

• Others: AUXR, CKCON

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Table 4-1.

All SFRs with their address and their reset value

Bit

address-

able

Non Bit addressable

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

F8h

F0h

FFh

F7h

B

0000 0000

E8h

E0h

EFh

E7h

ACC

0000 0000

D8h

D0h

DFh

D7h

PSW

0000 0000

T2CON

0000 0000

T2MOD

XXXX XX00

RCAP2L

0000 0000

RCAP2H

0000 0000

TL2

0000 0000

TH2

0000 0000

C8h

C0h

CFh

C7h

IP

SADEN

B8h

B0h

A8h

A0h

98h

90h

88h

80h

BFh

B7h

AFh

A7h

9Fh

97h

8Fh

87h

XX00 0000

0000 0000

P3

IPH

XX00 0000

1111 1111

IE

SADDR

0X00 0000

0000 0000

P2

AUXR1

WDTRST

WDTPRG

1111 1111

XXXX 0XX0

XXXX XXXX

XXXX X000

SCON

SBUF

0000 0000

XXXX XXXX

P1

1111 1111

TCON

TMOD

TL0

TL1

TH0

TH1

CKCON

AUXR

XXXX XXX0

0000 0000

XXXX XXX0

P0

PCON

SP

DPL

DPH

0000 0111

0000 0000

1111 1111

00X1 0000

0/8

1/9

2/A

3/B

4/C

5/D

6/E

7/F

reserved

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AT/TS8xC54/8X2

4431E–8051–04/06

AT/TS8xC54/8X2

5. Pin Configuration

P1.0 / T2

40

39

38

1

2

VCC

P0.0 / A0

P0.1 / A1

P1.1 / T2EX

P1.2

3

4

P1.3

37 P0.2 / A2

P0.3 / A3

36

P1.4

P1.5

P1.6

5

6

P0.4 / A4

35

P0.5 / A5

P0.6 / A6

P0.7 / A7

34

33

32

31

30

7

8

6

5 4 3 2 1

44 43 42 41 40

P1.7

RST

P1.5

P1.6

39

38

7

8

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA/VPP

NIC*

9

EA/VPP

ALE/PROG

PSEN

10

P3.0/RxD

P3.1/TxD

P1.7

37

36

9

PDIL/

11

12

13

RST

10

P3.2/INT0

P3.3/INT1

29

28

27

26

P3.0/RxD

NIC*

CDIL40

11

12

13

35

34

33

P2.7 / A15

P2.6 / A14

PLCC/CQPJ 44

14

15

16

17

18

19

20

P3.4/T0

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

ALE/PROG

PSEN

P2.5 / A13

P3.5/T1

P3.6/WR

14

15

16

17

32

31

30

29

P2.4 / A12

P2.3 / A11

25

P2.7/A15

P2.6/A14

P2.5/A13

24

23

22

21

P3.7/RD

XTAL2

P2.2 / A10

P2.1 / A9

P2.0 / A8

XTAL1

VSS

18 19 20 21 22 23 24 25 26 27 28

44 43 42 41 40 39 38 37 36 35 34

P1.5

P1.6

P0.4/AD4

P0.5/AD5

P0.6/AD6

P0.7/AD7

EA/VPP

NIC*

33

1

2

32

31

30

P1.7

3

4

RST

29

28

27

P3.0/RxD

NIC*

5

6

7

8

PQFP44 F1

VQFP44 1.4

P3.1/TxD

P3.2/INT0

P3.3/INT1

P3.4/T0

P3.5/T1

ALE/PROG

PSEN

26

25

24

P2.7/A15

P2.6/A14

P2.5/A13

9

10

11

23

12 13 14 15 16 17 18 19 20 21 22

*NIC: No Internal Connection

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4431E–8051–04/06

Table 5-1.

Pin Description for 40/44 pin packages

PIN NUMBER

TYPE

MNEMONIC

DIL

LCC

VQFP 1.4

Name And Function

V_SS

20

22

16

39

I

Ground: 0V reference

Vss1

1

Optional Ground: Contact the Sales Office for ground connection.

Power Supply: This is the power supply voltage for normal, idle and power-down

operation

V_CC

40

44

38

I

P0.0-P0.7

39-32

43-36

37-30

I/O

Port 0: Port 0 is an open-drain, bidirectional I/O port. Port 0 pins that have 1s written to

them float and can be used as high impedance inputs. Port 0 pins must be polarized to

Vcc or Vss in order to prevent any parasitic current consumption. Port 0 is also the

multiplexed low-order address and data bus during access to external program and

data memory. In this application, it uses strong internal pull-up when emitting 1s. Port 0

also inputs the code bytes during EPROM programming. External pull-ups are required

during program verification during which P0 outputs the code bytes.

P1.0-P1.7

1-8

2-9

40-44

1-3

I/O

Port 1: Port 1 is an 8-bit bidirectional I/O port with internal pull-ups. Port 1 pins that

have 1s written to them are pulled high by the internal pull-ups and can be used as

inputs. As inputs, Port 1 pins that are externally pulled low will source current because

of the internal pull-ups. Port 1 also receives the low-order address byte during memory

programming and verification.

Alternate functions for Port 1 include:

1

2

3

40

41

I/O

I

T2 (P1.0): Timer/Counter 2 external count input/Clockout

T2EX (P1.1): Timer/Counter 2 Reload/Capture/Direction Control

P2.0-P2.7

21-28

24-31

18-25

I/O

Port 2: Port 2 is an 8-bit bidirectional I/O port with internal pull-ups. Port 2 pins that

have 1s written to them are pulled high by the internal pull-ups and can be used as

inputs. As inputs, Port 2 pins that are externally pulled low will source current because

of the internal pull-ups. Port 2 emits the high-order address byte during fetches from

external program memory and during accesses to external data memory that use 16-

bit addresses (MOVX @DPTR).In this application, it uses strong internal pull-ups

emitting 1s. During accesses to external data memory that use 8-bit addresses (MOVX

@Ri), port 2 emits the contents of the P2 SFR. Some Port 2 pins receive the high order

address bits during EPROM programming and verification:

P2.0 to P2.5 for A8 to A13

P3.0-P3.7

10-17

11,

13-19

5,

7-13

I/O

Port 3: Port 3 is an 8-bit bidirectional I/O port with internal pull-ups. Port 3 pins that

have 1s written to them are pulled high by the internal pull-ups and can be used as

inputs. As inputs, Port 3 pins that are externally pulled low will source current because

of the internal pull-ups. Some Port 3 pin P3.4 receive the high order address bits during

EPROM programming and verification for TS8xC58X2 devices.

Port 3 also serves the special features of the 80C51 family, as listed below.

10

11

12

13

14

15

16

17

11

13

14

15

16

17

18

19

5

7

I

O

I

RXD (P3.0): Serial input port

TXD (P3.1): Serial output port

8

INT0 (P3.2): External interrupt 0

9

I

INT1 (P3.3): External interrupt 1

10

11

12

13

I

T0 (P3.4): Timer 0 external input

I

T1 (P3.5): Timer 1 external input

O

WR (P3.6): External data memory write strobe

RD (P3.7): External data memory read strobe

P3.4 also receives A14 during TS87C58X2 EPROM Programming.

Reset

9

10

4

I

Reset: A high on this pin for two machine cycles while the oscillator is running, resets

the device. An internal diffused resistor to V_SSpermits a power-on reset using only an

external capacitor to V_CC.

6

AT/TS8xC54/8X2

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AT/TS8xC54/8X2

Table 5-1.

Pin Description for 40/44 pin packages

PIN NUMBER

TYPE

MNEMONIC

DIL

LCC

VQFP 1.4

Name And Function

MNEMONIC

PIN NUMBER

33

TYPE

O (I)

NAME AND FUNCTION

ALE/PROG

30

27

Address Latch Enable/Program Pulse: Output pulse for latching the low byte of the

address during an access to external memory. In normal operation, ALE is emitted at a

constant rate of 1/6 (1/3 in X2 mode) the oscillator frequency, and can be used for

external timing or clocking. Note that one ALE pulse is skipped during each access to

external data memory. This pin is also the program pulse input (PROG) during EPROM

programming. ALE can be disabled by setting SFR’s AUXR.0 bit. With this bit set, ALE

will be inactive during internal fetches.

PSEN

29

31

32

35

26

29

O

Program Store ENable: The read strobe to external program memory. When

executing code from the external program memory, PSEN is activated twice each

machine cycle, except that two PSEN activations are skipped during each access to

external data memory. PSEN is not activated during fetches from internal program

memory.

EA/V_PP

I

External Access Enable/Programming Supply Voltage: EA must be externally held

low to enable the device to fetch code from external program memory locations 0000H

and 3FFFH (54X2) or 7FFFH (58X2). If EA is held high, the device executes from

internal program memory unless the program counter contains an address greater

than 3FFFH (54X2) or 7FFFH (58X2). This pin also receives the 12.75V programming

supply voltage (V_PP) during EPROM programming. If security level 1 is programmed,

EA will be internally latched on Reset.

XTAL1

XTAL2

19

18

21

20

15

14

I

Crystal 1: Input to the inverting oscillator amplifier and input to the internal clock

generator circuits.

O

Crystal 2: Output from the inverting oscillator amplifier

7

4431E–8051–04/06

6. TS80C54/58X2 Enhanced Features

In comparison to the original 80C52, the TS80C54/58X2 implements some new features, which

are:

• The X2 option.

• The Dual Data Pointer.

• The Watchdog.

• The 4 level interrupt priority system.

• The power-off flag.

• The ONCE mode.

• The ALE disabling.

• Some enhanced features are also located in the UART and the timer 2.

6.1

X2 Feature

The TS80C54/58X2 core needs only 6 clock periods per machine cycle. This feature called ”X2”

provides the following advantages:

• Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.

• Save power consumption while keeping same CPU power (oscillator power saving).

• Save power consumption by dividing dynamically operating frequency by 2 in operating and

idle modes.

• Increase CPU power by 2 while keeping same crystal frequency.

In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 sig-

nal and the main clock input of the core (phase generator). This divider may be disabled by

software.

6.1.1

Description

The clock for the whole circuit and peripheral is first divided by two before being used by the

CPU core and peripherals. This allows any cyclic ratio to be accepted on XTAL1 input. In X2

mode, as this divider is bypassed, the signals on XTAL1 must have a cyclic ratio between 40 to

60%. Figure 6-2. shows the clock generation block diagram. X2 bit is validated on XTAL1÷2 ris-

ing edge to avoid glitches when switching from X2 to STD mode. Figure 6-2. shows the mode

switching waveforms.

Figure 6-1. Clock Generation Diagram

XTAL1:2

2

state machine: 6 clock cycles.

CPU control

XTAL1

0

1

F_XTAL

F_OSC

X2

CKCON reg

8

AT/TS8xC54/8X2

4431E–8051–04/06

AT/TS8xC54/8X2

Figure 6-2. Mode Switching Waveforms

XTAL1

XTAL1:2

X2 bit

CPU clock

STD Mode

X2 Mode

STD Mode

The X2 bit in the CKCON register (See Table 6-1.) allows to switch from 12 clock cycles per

instruction to 6 clock cycles and vice versa. At reset, the standard speed is activated (STD

mode). Setting this bit activates the X2 feature (X2 mode).

CAUTION

In order to prevent any incorrect operation while operating in X2 mode, user must be aware that

all peripherals using clock frequency as time reference (UART, timers) will have their time refer-

ence divided by two. For example a free running timer generating an interrupt every 20 ms will

then generate an interrupt every 10 ms. UART with 4800 baud rate will have 9600 baud rate.

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4431E–8051–04/06

Table 6-1.

CKCON Register

CKCON - Clock Control Register (8Fh)

7

-

6

-

5

-

4

-

3

-

2

-

1

-

0

X2

Bit

Number Mnemonic

Description

Reserved

7

6

5

4

3

2

1

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

CPU and peripheral clock bit

0

X2

Clear to select 12 clock periods per machine cycle (STD mode, F_OSC=F_XTAL/2).

Set to select 6 clock periods per machine cycle (X2 mode, F_OSC=F_XTAL).

Reset Value = XXXX XXX0b

Not bit addressable

For further details on the X2 feature, please refer to ANM072 available on the web

(http://www.atmel.com)

10

AT/TS8xC54/8X2

4431E–8051–04/06

AT/TS8xC54/8X2

7. Dual Data Pointer Register Ddptr

The additional data pointer can be used to speed up code execution and reduce code size in a

number of ways.

The dual DPTR structure is a way by which the chip will specify the address of an external data

memory location. There are two 16-bit DPTR registers that address the external memory, and a

single bit called

DPS = AUXR1/bit0 (See Table 7-1.) that allows the program code to switch between them

(Refer to Figure 7-1).

Figure 7-1. Use of Dual Pointer

External Data Memory

7

0

DPS

DPTR1

DPTR0

AUXR1(A2H)

DPH(83H) DPL(82H)

11

4431E–8051–04/06

Table 7-1.

AUXR1: Auxiliary Register 1

7

-

6

-

5

-

4

-

3

2

0

1

-

0

GF3

DPS

Bit

Number Mnemonic

Description

Reserved

7

6

5

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

4

3

2

-

GF3

0

The value read from this bit is indeterminate. Do not set this bit.

This bit is a general purpose user flag

Reserved

Always stuck at 0.

Reserved

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Data Pointer Selection

Clear to select DPTR0.

Set to select DPTR1.

DPS

Reset Value = XXXX 00X0

Not bit addressable

User software should not write 1s to reserved bits. These bits may be used in future 8051 family

products to invoke new feature. In that case, the reset value of the new bit will be 0, and its

active value will be 1. The value read from a reserved bit is indeterminate.

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AT/TS8xC54/8X2

7.1

Application

Software can take advantage of the additional data pointers to both increase speed and reduce

code size, for example, block operations (copy, compare, search ...) are well served by using

one data pointer as a ’source’ pointer and the other one as a "destination" pointer.

ASSEMBLY LANGUAGE

; Block move using dual data pointers

; Destroys DPTR0, DPTR1, A and PSW

; note: DPS exits opposite of entry state

; unless an extra INC AUXR1 is added

;

00A2

AUXR1 EQU 0A2H

;

0000 909000

0003 05A2

0005 90A000

0008

MOV DPTR,#SOURCE

; address of SOURCE

; switch data pointers

; address of DEST

INC

AUXR1

MOV DPTR,#DEST

LOOP:

0008 05A2

000A E0

000B A3

000C 05A2

000E F0

000F A3

0010 70F6

0012 05A2

INC

AUXR1

; switch data pointers

MOVX A,@DPTR

INC

; get a byte from SOURCE

; increment SOURCE address

; switch data pointers

; write the byte to DEST

; increment DEST address

; check for 0 terminator

; (optional) restore DPS

DPTR

AUXR1

MOVX @DPTR,A

INC

JNZ

INC

DPTR

LOOP

AUXR1

INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR.

However, note that the INC instruction does not directly force the DPS bit to a particular state,

but simply toggles it. In simple routines, such as the block move example, only the fact that DPS

is toggled in the proper sequence matters, not its actual value. In other words, the block move

routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruc-

tion (INC AUXR1), the routine will exit with DPS in the opposite state.

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8. Timer 2

The timer 2 in the TS80C54/58X2 is compatible with the timer 2 in the 80C52.

It is a 16-bit timer/counter: the count is maintained by two eight-bit timer registers, TH2 and TL2,

connected in cascade. It is controlled by T2CON register (See Table 8-1) and T2MOD register

(See Table 8-2). Timer 2 operation is similar to Timer 0 and Timer 1. C/T2 selects F_OSC/12 (timer

operation) or external pin T2 (counter operation) as the timer clock input. Setting TR2 allows TL2

to be incremented by the selected input.

Timer 2 has 3 operating modes: capture, autoreload and Baud Rate Generator. These modes

are selected by the combination of RCLK, TCLK and CP/RL2 (T2CON), as described in the

Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description.

Refer to the Atmel Wireless & Microcontrollers 8-bit Microcontroller Hardware description for the

description of Capture and Baud Rate Generator Modes.

In TS80C54/58X2 Timer 2 includes the following enhancements:

• Auto-reload mode with up or down counter

• Programmable clock-output

8.1

Auto-Reload Mode

The auto-reload mode configures timer 2 as a 16-bit timer or event counter with automatic

reload. If DCEN bit in T2MOD is cleared, timer 2 behaves as in 80C52 (refer to the Atmel Wire-

less & Microcontrollers 8-bit Microcontroller Hardware description). If DCEN bit is set, timer 2

acts as an Up/down timer/counter as shown in Figure 8-1. In this mode the T2EX pin controls

the direction of count.

When T2EX is high, timer 2 counts up. Timer overflow occurs at FFFFh which sets the TF2 flag

and generates an interrupt request. The overflow also causes the 16-bit value in RCAP2H and

RCAP2L registers to be loaded into the timer registers TH2 and TL2.

When T2EX is low, timer 2 counts down. Timer underflow occurs when the count in the timer

registers TH2 and TL2 equals the value stored in RCAP2H and RCAP2L registers. The under-

flow sets TF2 flag and reloads FFFFh into the timer registers.

The EXF2 bit toggles when timer 2 overflows or underflows according to the the direction of the

count. EXF2 does not generate any interrupt. This bit can be used to provide 17-bit resolution

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AT/TS8xC54/8X2

Figure 8-1. Auto-Reload Mode Up/Down Counter (DCEN = 1)

:12

0

1

XTAL1

F_XTAL

F_OSC

T2

TR2

T2CONreg

C/T2

T2CONreg

(DOWN COUNTING RELOAD VALUE)

T2EX:

FFh

(8-bit)

FFh

(8-bit)

if DCEN=1, 1=UP

if DCEN=1, 0=DOWN

T2CONreg

EXF2

TOG-

TL2

(8-bit)

TH2

(8-bit)

TIMER 2

INTERRUPT

TF2

T2CONreg

RCAP2L

(8-bit)

RCAP2H

(8-bit)

(UP COUNTING RELOAD VALUE)

8.1.1

Programmable Clock-Output

In the clock-out mode, timer 2 operates as a 50%-duty-cycle, programmable clock generator

(See Figure 8-2) . The input clock increments TL2 at frequency F_OSC/2. The timer repeatedly

counts to overflow from a loaded value. At overflow, the contents of RCAP2H and RCAP2L reg-

isters are loaded into TH2 and TL2. In this mode, timer 2 overflows do not generate interrupts.

The formula gives the clock-out frequency as a function of the system oscillator frequency and

the value in the RCAP2H and RCAP2L registers :

4 × (65536

2

⁄

2 )

For a 16 MHz system clock, timer 2 has a programmable frequency range of 61 Hz

(F_OSC/2¹⁶⁾to 4 MHz (F_OSC/4). The generated clock signal is brought out to T2 pin (P1.0).

Timer 2 is programmed for the clock-out mode as follows:

• Set T2OE bit in T2MOD register.

• Clear C/T2 bit in T2CON register.

• Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L

registers.

15

4431E–8051–04/06

• Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value

or a different one depending on the application.

• To start the timer, set TR2 run control bit in T2CON register.

It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For

this configuration, the baud rates and clock frequencies are not independent since both func-

tions use the values in the RCAP2H and RCAP2L registers.

Figure 8-2. Clock-Out Mode C/T2 = 0

:2

XTAL1

TR2

T2CON reg

TH2

(8-bit)

TL2

(8-bit)

OVERFLOW

RCAP2H

(8-bit)

RCAP2L

(8-bit)

Toggle

T2

Q

D

T2OE

T2MOD reg

T2EX

EXF2

T2CON reg

INTERRUPT

EXEN2

T2CON reg

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AT/TS8xC54/8X2

Table 8-1.

T2CON Register

T2CON - Timer 2 Control Register (C8h)

7

6

5

4

3

2

1

0

TF2

EXF2

RCLK

TCLK

EXEN2

TR2

C/T2#

CP/RL2#

Bit

Number Mnemonic

Description

Timer 2 overflow Flag

7

6

TF2

Must be cleared by software.

Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.

Timer 2 External Flag

Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1.

When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is

enabled.

EXF2

Must be cleared by software. EXF2 doesn’t cause an interrupt in Up/down counter mode

(DCEN = 1)

Receive Clock bit

5

4

RCLK

TCLK

Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.

Transmit Clock bit

Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3.

Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.

Timer 2 External Enable bit

Clear to ignore events on T2EX pin for timer 2 operation.

Set to cause a capture or reload when a negative transition on T2EX pin is detected, if timer

2 is not used to clock the serial port.

3

2

1

EXEN2

TR2

Timer 2 Run control bit

Clear to turn off timer 2.

Set to turn on timer 2.

Timer/Counter 2 select bit

Clear for timer operation (input from internal clock system: F_OSC).

Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock

out mode.

C/T2#

Timer 2 Capture/Reload bit

If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2

0

CP/RL2# overflow.

Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1.

Set to capture on negative transitions on T2EX pin if EXEN2=1.

Reset Value = 0000 0000b

Bit addressable

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Table 8-2.

T2MOD Register

T2MOD - Timer 2 Mode Control Register (C9h)

7

-

6

5

4

3

2

-

1

0

-

T2OE

DCEN

Bit

Number Mnemonic

Description

Reserved

7

6

5

4

3

2

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 Output Enable bit

1

0

T2OE

DCEN

Clear to program P1.0/T2 as clock input or I/O port.

Set to program P1.0/T2 as clock output.

Down Counter Enable bit

Clear to disable timer 2 as up/down counter.

Set to enable timer 2 as up/down counter.

Reset Value = XXXX XX00b

Not bit addressable

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AT/TS8xC54/8X2

9. TS80C54/58X2 Serial I/O Port

The serial I/O port in the TS80C54/58X2 is compatible with the serial I/O port in the 80C52.

It provides both synchronous and asynchronous communication modes. It operates as an Uni-

versal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (Modes 1, 2

and 3). Asynchronous transmission and reception can occur simultaneously and at different

baud rates

Serial I/O port includes the following enhancements:

• Framing error detection

• Automatic address recognition

9.1

Framing Error Detection

Framing bit error detection is provided for the three asynchronous modes (modes 1, 2 and 3). To

enable the framing bit error detection feature, set SMOD0 bit in PCON register (See Figure 9-1).

Figure 9-1. Framing Error Block Diagram

SM0/FE SM1

SM2

REN

TB8

RB8

TI

RI

SCON (98h)

Set FE bit if stop bit is 0 (framing error) (SMOD0 = 1)

SM0 to UART mode control (SMOD = 0)

PCON (87h)

SMOD1SMOD0

-

POF GF1

GF0

PD

IDL

To UART framing error control

When this feature is enabled, the receiver checks each incoming data frame for a valid stop bit.

An invalid stop bit may result from noise on the serial lines or from simultaneous transmission by

two CPUs. If a valid stop bit is not found, the Framing Error bit (FE) in SCON register (See Table

9-3.) bit is set.

Software may examine FE bit after each reception to check for data errors. Once set, only soft-

ware or a reset can clear FE bit. Subsequently received frames with valid stop bits cannot clear

FE bit. When FE feature is enabled, RI rises on stop bit instead of the last data bit (See Figure 9-

2. and Figure 9-3.).

Figure 9-2. UART Timings in Mode 1

RXD

D0

D1

D2

D3

D4

D5

D6

D7

Start

bit

Data byte

Stop

bit

RI

SMOD0=X

FE

SMOD0=1

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4431E–8051–04/06

Figure 9-3. UART Timings in Modes 2 and 3

RXD

D0

D1

D2

D3

D4

D5

D6

D7

D8

Start

bit

Data byte

Ninth Stop

bit

RI

SMOD0=0

RI

SMOD0=1

FE

SMOD0=1

9.1.1

Automatic Address Recognition

The automatic address recognition feature is enabled when the multiprocessor communication

feature is enabled (SM2 bit in SCON register is set).

Implemented in hardware, automatic address recognition enhances the multiprocessor commu-

nication feature by allowing the serial port to examine the address of each incoming command

frame. Only when the serial port recognizes its own address, the receiver sets RI bit in SCON

register to generate an interrupt. This ensures that the CPU is not interrupted by command

frames addressed to other devices.

If desired, you may enable the automatic address recognition feature in mode 1. In this configu-

ration, the stop bit takes the place of the ninth data bit. Bit RI is set only when the received

command frame address matches the device’s address and is terminated by a valid stop bit.

To support automatic address recognition, a device is identified by a given address and a broad-

cast address.

NOTE: The multiprocessor communication and automatic address recognition features cannot

be enabled in mode 0 (i.e. setting SM2 bit in SCON register in mode 0 has no effect).

9.1.2

Given Address

Each device has an individual address that is specified in SADDR register; the SADEN register

is a mask byte that contains don’t-care bits (defined by zeros) to form the device’s given

address. The don’t-care bits provide the flexibility to address one or more slaves at a time. The

following example illustrates how a given address is formed.

To address a device by its individual address, the SADEN mask byte must be 1111 1111b.

For example:

SADDR

SADEN

Given

01010110b

11111100b

010101XXb

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AT/TS8xC54/8X2

4431E–8051–04/06

AT/TS8xC54/8X2

The following is an example of how to use given addresses to address different slaves:

SlaveA:

SlaveB:

SlaveC:

SADDR

SADEN

Given

11110001b

11111010b

11110X0Xb

SADDR

SADEN

Given

11110011b

11111001b

11110XX1b

SADDR

SADEN

Given

11110010b

11111101b

111100X1b

The SADEN byte is selected so that each slave may be addressed separately.

For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate

with slave A only, the master must send an address where bit 0 is clear (e.g. 1111 0000b).

For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves

B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g. 1111

0011b).

To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1

clear, and bit 2 clear (e.g. 1111 0001b).

9.1.3

Broadcast Address

A broadcast address is formed from the logical OR of the SADDR and SADEN registers with

zeros defined as don’t-care bits, e.g.:

SADDR

SADEN

01010110b

11111100b

1111111Xb

Broadcast=SADDRORSADEN

The use of don’t-care bits provides flexibility in defining the broadcast address, however in most

applications, a broadcast address is FFh. The following is an example of using broadcast

addresses:

SlaveA:

SlaveB:

SlaveC:

SADDR

SADEN

11110001b

11111010b

Broadcast 11111X11b,

SADDR

SADEN

11110011b

11111001b

Broadcast 11111X11B,

SADDR=

SADEN

11110010b

11111101b

Broadcast 11111111b

For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of

the slaves, the master must send an address FFh. To communicate with slaves A and B, but not

slave C, the master can send and address FBh.

9.1.4

Reset Addresses

On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast

addresses are XXXX XXXXb(all don’t-care bits). This ensures that the serial port will reply to any

address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not

support automatic address recognition.

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4431E–8051–04/06

Table 9-1.

SADEN - Slave Address Mask Register (B9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Not bit addressable

Table 9-2.

SADDR - Slave Address Register (A9h)

7

6

5

4

3

2

1

0

Reset Value = 0000 0000b

Not bit addressable

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AT/TS8xC54/8X2

Table 9-3.

SCON Register

SCON - Serial Control Register (98h)

7

6

5

4

3

2

1

0

FE/SM0

SM1

SM2

REN

TB8

RB8

TI

RI

Bit

Number Mnemonic

Description

Framing Error bit (SMOD0=1)

Clear to reset the error state, not cleared by a valid stop bit.

Set by hardware when an invalid stop bit is detected.

7

FE

SMOD0 must be set to enable access to the FE bit

Serial port Mode bit 0

Refer to SM1 for serial port mode selection.

SM0

SMOD0 must be cleared to enable access to the SM0 bit

Serial port Mode bit 1

SM0

SM1Mode Description Baud Rate

6

5

SM1

SM2

0

1

0

1

0

1

0

1

2

3

Shift RegisterF_XTAL/12 (/6 in X2 mode)

8-bit UARTVariable

9-bit UARTF_XTAL/64 or F_XTAL/32 (/32, /16 in X2 mode)

9-bit UARTVariable

Serial port Mode 2 bit / Multiprocessor Communication Enable bit

Clear to disable multiprocessor communication feature.

Set to enable multiprocessor communication feature in mode 2 and 3, and eventually mode

1. This bit should be cleared in mode 0.

Reception Enable bit

4

3

REN

TB8

Clear to disable serial reception.

Set to enable serial reception.

Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3.

Clear to transmit a logic 0 in the 9th bit.

Set to transmit a logic 1 in the 9th bit.

Receiver Bit 8 / Ninth bit received in modes 2 and 3

Cleared by hardware if 9th bit received is a logic 0.

Set by hardware if 9th bit received is a logic 1.

2

RB8

In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.

Transmit Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0 or at the beginning of the stop bit in

1

0

TI

the other

modes.

Receive Interrupt flag

Clear to acknowledge interrupt.

Set by hardware at the end of the 8th bit time in mode 0, see Figure 9-2. and Figure 9-3. in

the other modes.

RI

Reset Value = 0000 0000b

Bit addressable

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Table 9-4.

PCON Register

Table 9-5.

PCON - Power Control Register (87h)

7

6

5

4

3

2

1

0

SMOD1

SMOD0

-

POF

GF1

GF0

PD

IDL

Bit

Number Mnemonic

Description

Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

7

6

5

4

SMOD1

SMOD0

-

Serial port Mode bit 0

Clear to select SM0 bit in SCON register.

Set to to select FE bit in SCON register.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag

Clear to recognize next reset type.

POF

Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.

General purpose Flag

3

2

1

0

GF1

GF0

PD

Cleared by user for general purpose usage.

Set by user for general purpose usage.

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

Power-Down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle mode bit

Clear by hardware when interrupt or reset occurs.

Set to enter idle mode.

IDL

Reset Value = 00X1 0000b

Not bit addressable

Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect

the value of this bit.

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AT/TS8xC54/8X2

10. Interrupt System

The TS80C54/58X2 has a total of 7 interrupt vectors: two external interrupts (INT0 and INT1),

three timer interrupts (timers 0, 1 and 2) and the serial port interrupt. These interrupts are shown

in Figure 10-1.

Figure 10-1. Interrupt Control System

High priority

IPH, IP

interrupt

3

INT0

IE0

0

3

0

TF0

INT1

TF1

Interrupt

3

IE1

polling

0

3

0

sequence, decreasing from

high to low priority

3

RI

TI

0

3

TF2

EXF2

0

Individual Enable

Global Disable

Low priority

interrupt

Each of the interrupt sources can be individually enabled or disabled by setting or clearing a bit

in the Interrupt Enable register (See Table 10-2.). This register also contains a global disable bit,

which must be cleared to disable all interrupts at once.

Each interrupt source can also be individually programmed to one out of four priority levels by

setting or clearing a bit in the Interrupt Priority register (See Table 10-3.) and in the Interrupt Pri-

ority High register (See Table 10-4.). shows the bit values and priority levels associated with

each combination.

Table 10-1. Priority Level Bit Values

IPH.x

IP.x

0

Interrupt Level Priority

0

1

0 (Lowest)

1

2

0

1

3 (Highest)

A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-prior-

ity interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source.

25

4431E–8051–04/06

If two interrupt requests of different priority levels are received simultaneously, the request of

higher priority level is serviced. If interrupt requests of the same priority level are received simul-

taneously, an internal polling sequence determines which request is serviced. Thus within each

priority level there is a second priority structure determined by the polling sequence.

Table 10-2. IE Register

IE - Interrupt Enable Register (A8h)

7

6

5

4

3

2

1

0

EA

-

ET2

ES

ET1

EX1

ET0

EX0

Bit

Number Mnemonic

Description

Enable All interrupt bit

Clear to disable all interrupts.

Set to enable all interrupts.

7

EA

If EA=1, each interrupt source is individually enabled or disabled by setting or clearing its

own interrupt enable bit.

Reserved

6

5

-

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 overflow interrupt Enable bit

Clear to disable timer 2 overflow interrupt.

Set to enable timer 2 overflow interrupt.

ET2

Serial port Enable bit

4

3

2

1

0

ES

Clear to disable serial port interrupt.

Set to enable serial port interrupt.

Timer 1 overflow interrupt Enable bit

Clear to disable timer 1 overflow interrupt.

Set to enable timer 1 overflow interrupt.

ET1

EX1

ET0

EX0

External interrupt 1 Enable bit

Clear to disable external interrupt 1.

Set to enable external interrupt 1.

Timer 0 overflow interrupt Enable bit

Clear to disable timer 0 overflow interrupt.

Set to enable timer 0 overflow interrupt.

External interrupt 0 Enable bit

Clear to disable external interrupt 0.

Set to enable external interrupt 0.

Reset Value = 0X00 0000b

Bit addressable

26

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AT/TS8xC54/8X2

Table 10-3. IP Register

IP - Interrupt Priority Register (B8h)

7

6

5

4

3

2

1

0

-

PT2

PS

PT1

PX1

PT0

PX0

Bit

Number Mnemonic

Description

Reserved

7

6

5

4

3

2

1

0

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 overflow interrupt Priority bit

Refer to PT2H for priority level.

PT2

PS

Serial port Priority bit

Refer to PSH for priority level.

Timer 1 overflow interrupt Priority bit

Refer to PT1H for priority level.

PT1

PX1

PT0

PX0

External interrupt 1 Priority bit

Refer to PX1H for priority level.

Timer 0 overflow interrupt Priority bit

Refer to PT0H for priority level.

External interrupt 0 Priority bit

Refer to PX0H for priority level.

Reset Value = XX00 0000b

Bit addressable

27

4431E–8051–04/06

Table 10-4. IPH Register

IPH - Interrupt Priority High Register (B7h)

7

6

5

4

3

2

1

0

-

PT2H

PSH

PT1H

PX1H

PT0H

PX0H

Bit

Number Mnemonic

Description

Reserved

7

6

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Timer 2 overflow interrupt Priority High bit

PT2H PT2 Priority Level

0

1

0

1

0

1

Lowest

5

4

3

2

1

0

PT2H

PSH

Highest

Serial port Priority High bit

PSH

0

1

PS

0

1

0

1

Priority Level

Lowest

Highest

Timer 1 overflow interrupt Priority High bit

PT1H PT1 Priority Level

0

1

0

1

0

1

Lowest

PT1H

PX1H

PT0H

PX0H

Highest

External interrupt 1 Priority High bit

PX1H PX1 Priority Level

0

1

0

1

0

1

Lowest

Highest

Timer 0 overflow interrupt Priority High bit

PT0H PT0 Priority Level

0

1

0

1

0

1

Lowest

Highest

External interrupt 0 Priority High bit

PX0H PX0 Priority Level

0

1

0

1

0

1

Lowest

Highest

Reset Value = XX00 0000b

Not bit addressable

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AT/TS8xC54/8X2

11. Idle mode

An instruction that sets PCON.0 causes that to be the last instruction executed before going into

the Idle mode. In the Idle mode, the internal clock signal is gated off to the CPU, but not to the

interrupt, Timer, and Serial Port functions. The CPU status is preserved in its entirely : the Stack

Pointer, Program Counter, Program Status Word, Accumulator and all other registers maintain

their data during Idle. The port pins hold the logical states they had at the time Idle was acti-

vated. ALE and PSEN hold at logic high levels.

There are two ways to terminate the Idle. Activation of any enabled interrupt will cause PCON.0

to be cleared by hardware, terminating the Idle mode. The interrupt will be serviced, and follow-

ing RETI the next instruction to be executed will be the one following the instruction that put the

device into idle.

The flag bits GF0 and GF1 can be used to give an indication if an interrupt occured during nor-

mal operation or during an Idle. For example, an instruction that activates Idle can also set one

or both flag bits. When Idle is terminated by an interrupt, the interrupt service routine can exam-

ine the flag bits.

The other way of terminating the Idle mode is with a hardware reset. Since the clock oscillator is

still running, the hardware reset needs to be held active for only two machine cycles (24 oscilla-

tor periods) to complete the reset.

11.1 Power-Down Mode

To save maximum power, a power-down mode can be invoked by software (Refer to Table 9-4.,

PCON register).

In power-down mode, the oscillator is stopped and the instruction that invoked power-down

mode is the last instruction executed. The internal RAM and SFRs retain their value until the

power-down mode is terminated. V_CCcan be lowered to save further power. Either a hardware

reset or an external interrupt can cause an exit from power-down. To properly terminate power-

down, the reset or external interrupt should not be executed before V_CCis restored to its normal

operating level and must be held active long enough for the oscillator to restart and stabilize.

Only external interrupts INT0 and INT1 are useful to exit from power-down. For that, interrupt

must be enabled and configured as level or edge sensitive interrupt input.

Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed

in Figure 11-1. When both interrupts are enabled, the oscillator restarts as soon as one of the

two inputs is held low and power down exit will be completed when the first input will be

released. In this case the higher priority interrupt service routine is executed.

Once the interrupt is serviced, the next instruction to be executed after RETI will be the one fol-

lowing the instruction that put TS80C54/58X2 into power-down mode.

29

4431E–8051–04/06

Figure 11-1. Power-Down Exit Waveform

INT0

INT1

XTAL1

Active phase

Power-down phase Oscillator restart phase

Active phase

Exit from power-down by reset redefines all the SFRs, exit from power-down by external inter-

rupt does no affect the SFRs.

Exit from power-down by either reset or external interrupt does not affect the internal RAM

content.

NOTE: If idle mode is activated with power-down mode (IDL and PD bits set), the exit sequence

is unchanged, when execution is vectored to interrupt, PD and IDL bits are cleared and idle

mode is not entered.

Table 11-1. The state of ports during idle and power-down modes

Program

Mode

Idle

Memory

Internal

External

Internal

External

ALE

PSEN

PORT0

Port Data*

Floating

PORT1

PORT2

Port Data

Address

Port Data

PORT3

Port Data

1

0

1

0

Port Data

Idle

Power Down

Port Data*

Floating

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AT/TS8xC54/8X2

12. Hardware Watchdog Timer

The WDT is intended as a recovery method in situations where the CPU may be subjected to

software upset. The WDT consists of a 14-bit counter and the WatchDog Timer ReSeT

(WDTRST) SFR. The WDT is by default disabled from exiting reset. To enable the WDT, user

must write 01EH and 0E1H in sequence to the WDTRST, SFR location 0A6H. When WDT is

enabled, it will increment every machine cycle while the oscillator is running and there is no way

to disable the WDT except through reset (either hardware reset or WDT overflow reset). When

WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.

12.1 Using the WDT

To enable the WDT, user must write 01EH and 0E1H in sequence to the WDTRST, SFR loca-

tion 0A6H. When WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to

WDTRST to avoid WDT overflow. The 14-bit counter overflows when it reaches 16383 (3FFFH)

and this will reset the device. When WDT is enabled, it will increment every machine cycle while

the oscillator is running. This means the user must reset the WDT at least every 16383 machine

cycle. To reset the WDT the user must write 01EH and 0E1H to WDTRST. WDTRST is a write

only register. The WDT counter cannot be read or written. When WDT overflows, it will generate

an output RESET pulse at the RST-pin. The RESET pulse duration is 96 x T_OSC, where T_OSC

=

1/F_OSC. To make the best use of the WDT, it should be serviced in those sections of code that

will periodically be executed within the time required to prevent a WDT reset.

To have a more powerful WDT, a 2⁷counter has been added to extend the Time-out capability,

ranking from 16ms to 2s @ F_OSC= 12MHz. To manage this feature, refer to WDTPRG register

description, Table 12-2. (SFR0A7h).

Table 12-1. WDTRST Register

WDTRST Address (0A6h)

7

6

5

4

3

2

1

Reset value

X

Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.

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4431E–8051–04/06

Table 12-2. WDTPRG Register

WDTPRG Address (0A7h)

7

6

5

4

3

2

1

0

T4

T3

T2

T1

T0

S2

S1

S0

Bit

Number Mnemonic

Description

7

6

5

4

3

2

1

0

T4

T3

T2

T1

T0

S2

S1

S0

Reserved

Do not try to set or clear this bit.

WDT Time-out select bit 2

WDT Time-out select bit 1

WDT Time-out select bit 0

S2S1

S0

0

1

0

1

Selected Time-out

0

1

0

1

0

1

0

1

0

1

(2¹⁴- 1) machine cycles, 16.3 ms @ 12 MHz

(2¹⁵- 1) machine cycles, 32.7 ms @ 12 MHz

(2¹⁶- 1) machine cycles, 65.5 ms @ 12 MHz

(2¹⁷- 1) machine cycles, 131 ms @ 12 MHz

(2¹⁸- 1) machine cycles, 262 ms @ 12 MHz

(2¹⁹- 1) machine cycles, 542 ms @ 12 MHz

(2²⁰- 1) machine cycles, 1.05 s @ 12 MHz

(2²¹- 1) machine cycles, 2.09 s @ 12 MHz

Reset value XXXX X000

12.1.1

WDT during Power Down and Idle

In Power Down mode the oscillator stops, which means the WDT also stops. While in Power

Down mode the user does not need to service the WDT. There are 2 methods of exiting Power

Down mode: by a hardware reset or via a level activated external interrupt which is enabled prior

to entering Power Down mode. When Power Down is exited with hardware reset, servicing the

WDT should occur as it normally should whenever the TS80C54/58X2 is reset. Exiting Power

Down with an interrupt is significantly different. The interrupt is held low long enough for the

oscillator to stabilize. When the interrupt is brought high, the interrupt is serviced. To prevent the

WDT from resetting the device while the interrupt pin is held low, the WDT is not started until the

interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine.

To ensure that the WDT does not overflow within a few states of exiting of powerdown, it is best

to reset the WDT just before entering powerdown.

In the Idle mode, the oscillator continues to run. To prevent the WDT from resetting the

TS80C54/58X2 while in Idle mode, the user should always set up a timer that will periodically

exit Idle, service the WDT, and re-enter Idle mode.

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13. ONCE^TMMode (ON Chip Emulation)

The ONCE mode facilitates testing and debugging of systems using TS80C54/58X2 without

removing the circuit from the board. The ONCE mode is invoked by driving certain pins of the

TS80C54/58X2; the following sequence must be exercised:

• Pull ALE low while the device is in reset (RST high) and PSEN is high.

• Hold ALE low as RST is deactivated.

While the TS80C54/58X2 is in ONCE mode, an emulator or test CPU can be used to drive the

circuit Table 13-1 shows the status of the port pins during ONCE mode.

Normal operation is restored when normal reset is applied.

Table 13-1. External Pin Status during ONCE Mode

ALE

PSEN

Port 0

Port 1

Port 2

Port 3

XTAL1/2

Weak pull-up

Float

Weak pull-up

Active

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14. Power-Off Flag

The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start”

reset.

A cold start reset is the one induced by V_CCswitch-on. A warm start reset occurs while V_CCis still

applied to the device and could be generated for example by an exit from power-down.

The power-off flag (POF) is located in PCON register (See Table 14-1.). POF is set by hardware

when V_CCrises from 0 to its nominal voltage. The POF can be set or cleared by software allow-

ing the user to determine the type of reset.

The POF value is only relevant with a Vcc range from 4.5V to 5.5V. For lower Vcc value, reading

POF bit will return indeterminate value.

Table 14-1. PCON Register

PCON - Power Control Register (87h)

7

6

5

4

3

2

1

0

SMOD1

SMOD0

-

POF

GF1

GF0

PD

IDL

Bit

Number Mnemonic

Description

Serial port Mode bit 1

Set to select double baud rate in mode 1, 2 or 3.

7

6

5

4

SMOD1

Serial port Mode bit 0

SMOD0 Clear to select SM0 bit in SCON register.

Set to to select FE bit in SCON register.

Reserved

-

The value read from this bit is indeterminate. Do not set this bit.

Power-Off Flag

Clear to recognize next reset type.

Set by hardware when V_CCrises from 0 to its nominal voltage. Can also be set by software.

POF

GF1

GF0

PD

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

3

2

1

0

General purpose Flag

Cleared by user for general purpose usage.

Set by user for general purpose usage.

Power-Down mode bit

Cleared by hardware when reset occurs.

Set to enter power-down mode.

Idle mode bit

Clear by hardware when interrupt or reset occurs.

Set to enter idle mode.

IDL

Reset Value = 00X1 0000b

Not bit addressable

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15. Reduced EMI Mode

The ALE signal is used to demultiplex address and data buses on port 0 when used with exter-

nal program or data memory. Nevertheless, during internal code execution, ALE signal is still

generated. In order to reduce EMI, ALE signal can be disabled by setting AO bit.

The AO bit is located in AUXR register at bit location 0. As soon as AO is set, ALE is no longer

output but remains active during MOVX and MOVC instructions and external fetches. During

ALE disabling, ALE pin is weakly pulled high.

Table 15-1. AUXR Register

AUXR - Auxiliary Register (8Eh)

7

-

6

5

4

3

-

2

-

1

0

-

RESERVED

AO

Bit

Number

Mnemonic

Description

Reserved

7

6

5

4

3

2

1

-

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

Reserved

The value read from this bit is indeterminate. Do not set this bit.

ALE Output bit

0

AO

Clear to restore ALE operation during internal fetches.

Set to disable ALE operation during internal fetches.

Reset Value = XXXX XXX0b

Not bit addressable

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4431E–8051–04/06

16. TS80C54/58X2 ROM

16.1 ROM Structure

The TS80C54/58X2 ROM memory is in three different arrays:

• the code array:16/32 Kbytes.

• the encryption array:64 bytes.

• the signature array:4 bytes.

16.2 ROM Lock System

The program Lock system, when programmed, protects the on-chip program against software

piracy.

16.2.1

Encryption Array

Within the ROM array are 64 bytes of encryption array that are initially unprogrammed (all FF’s).

Every time a byte is addressed during program verify, 6 address lines are used to select a byte

of the encryption array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, creating

an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed state,

will return the code in its original, unmodified form.

When using the encryption array, one important factor needs to be considered. If a byte has the

value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes)

of code is left unprogrammed, a verification routine will display the content of the encryption

array. For this reason all the unused code bytes should be programmed with random values.

This will ensure program protection.

16.2.2

Program Lock Bits

The lock bits when programmed according to Table 16-1. will provide different level of protection

for the on-chip code and data.

Table 16-1. Program Lock bits

Program Lock Bits

Security

level

LB1

LB2

LB3

Protection Description

No program lock features enabled. Code verify will still be encrypted by

the encryption array if programmed. MOVC instruction executed from

external program memory returns non encrypted data.

1

U

MOVC instruction executed from external program memory are disabled

from fetching code bytes from internal memory, EA is sampled and

latched on reset.

2

P

U

U: unprogrammed

P: programmed

16.2.3

16.2.4

Signature bytes

The TS80C54/58X2 contains 4 factory programmed signatures bytes. To read these bytes, per-

form the process described in section 8.3.

Verify Algorithm

Refer to 17.3.4

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AT/TS8xC54/8X2

17. TS87C54/58X2 EPROM

17.1 EPROM Structure

The TS87C54/58X2 EPROM is divided in two different arrays:

• the code array:16/32 Kbytes.

• the encryption array:64 bytes.

• In addition a third non programmable array is implemented:

• the signature array: 4 bytes.

17.2 EPROM Lock System

The program Lock system, when programmed, protects the on-chip program against software

piracy.

17.2.1

Encryption Array

Within the EPROM array are 64 bytes of encryption array that are initially unprogrammed (all

FF’s). Every time a byte is addressed during program verify, 6 address lines are used to select a

byte of the encryption array. This byte is then exclusive-NOR’ed (XNOR) with the code byte, cre-

ating an encrypted verify byte. The algorithm, with the encryption array in the unprogrammed

state, will return the code in its original, unmodified form.

When using the encryption array, one important factor needs to be considered. If a byte has the

value FFh, verifying the byte will produce the encryption byte value. If a large block (>64 bytes)

of code is left unprogrammed, a verification routine will display the content of the encryption

array. For this reason all the unused code bytes should be programmed with random values.

This will ensure program protection.

17.2.2

Program Lock Bits

The three lock bits, when programmed according to Table 17-1., will provide different level of

protection for the on-chip code and data.

Table 17-1. Program Lock bits

Program Lock Bits

Security

level

LB1

LB2

LB3

Protection Description

No program lock features enabled. Code verify will still be encrypted by

the encryption array if programmed. MOVC instruction executed from

external program memory returns non encrypted data.

1

U

MOVC instruction executed from external program memory are

disabled from fetching code bytes from internal memory, EA is sampled

and latched on reset, and further programming of the EPROM is

disabled.

2

P

U

3

4

U

P

U

P

Same as 2, also verify is disabled.

Same as 3, also external execution is disabled.

U: unprogrammed,

P: programmed

WARNING: Security level 2 and 3 should only be programmed after EPROM and Core

verification.

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4431E–8051–04/06

17.2.3

Signature bytes

The TS87C54/58X2 contains 4 factory programmed signatures bytes. To read these bytes, per-

form the process described in section 8.3.

17.3 EPROM Programming

17.3.1

Set-up modes

In order to program and verify the EPROM or to read the signature bytes, the TS87C54/58X2 is

placed in specific set-up modes (See Figure 17-1.).

Control and program signals must be held at the levels indicated in Table 17-2.

17.3.2

Definition of terms

Address Lines:P1.0-P1.7, P2.0-P2.5, P3.4 respectively for A0-A14 (P2.5 (A13) for

TS87C54X2, P3.4 (A14) for TS87C58X2).

Data Lines:P0.0-P0.7 for D0-D7

Control Signals:RST, PSEN, P2.6, P2.7, P3.3, P3.6, P3.7.

Program Signals:ALE/PROG, EA/VPP.

Table 17-2. EPROM Set-Up Modes

ALE/PR

Mode

RST

PSEN

OG

EA/VPP

P2.6

P2.7

P3.3

P3.6

P3.7

Program Code data

Verify Code data

Program Encryption

Array Address 0-3Fh

Read Signature Bytes

Program Lock bit 1

Program Lock bit 2

Program Lock bit 3

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AT/TS8xC54/8X2

Figure 17-1. Set-Up Modes Configuration

EA/VPP

VCC

PROGRAM

SIGNALS*

ALE/PROG

P0.0-P0.7

D0-D7

RST

PSEN

P2.6

P2.7

P3.3

P3.6

P3.7

P1.0-P1.7

A0-A7

CONTROL

SIGNALS*

A8-A14

P2.0-P2.5,

4 to 6 MHz

XTAL1

VSS

GND

* See Table 31. for proper value on these inputs

17.3.3

Programming Algorithm

The Improved Quick Pulse algorithm is based on the Quick Pulse algorithm and decreases the

number of pulses applied during byte programming from 25 to 1.

To program the TS80C54/58X2 the following sequence must be exercised:

• Step 1: Activate the combination of control signals.

• Step 2: Input the valid address on the address lines.

• Step 3: Input the appropriate data on the data lines.

• Step 4: Raise EA/VPP from VCC to VPP (typical 12.75V).

• Step 5: Pulse ALE/PROG once.

• Step 6: Lower EA/VPP from VPP to VCC

Repeat step 2 through 6 changing the address and data for the entire array or until the end of

the object file is reached (See Figure 17-2.).

17.3.4

Verify algorithm

Code array verify must be done after each byte or block of bytes is programmed. In either case,

a complete verify of the programmed array will ensure reliable programming of the

TS87C54/58X2.

P 2.7 is used to enable data output.

To verify the TS87C54/58X2 code the following sequence must be exercised:

• Step 1: Activate the combination of program and control signals.

• Step 2: Input the valid address on the address lines.

• Step 3: Read data on the data lines.

Repeat step 2 through 3 changing the address for the entire array verification (See Figure 17-2.)

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4431E–8051–04/06

The encryption array cannot be directly verified. Verification of the encryption array is done by

observing that the code array is well encrypted.

Figure 17-2. Programming and Verification Signal’s Waveform

Programming Cycle

Read/Verify Cycle

Data Out

A0-A12

D0-D7

Data In

μ

ALE/PROG

EA/VPP

12.75V

5V

0V

Control

signals

17.4 EPROM Erasure (Windowed Packages Only)

Erasing the EPROM erases the code array, the encryption array and the lock bits returning the

parts to full functionality.

Erasure leaves all the EPROM cells in a 1’s state (FF).

17.4.1

Erasure Characteristics

The recommended erasure procedure is exposure to ultraviolet light (at 2537 Å) to an integrated

dose at least 15 W-sec/cm². Exposing the EPROM to an ultraviolet lamp of 12,000 μW/cm²rat-

ing for 30 minutes, at a distance of about 25 mm, should be sufficient. An exposure of 1 hour is

recommended with most of standard erasers.

Erasure of the EPROM begins to occur when the chip is exposed to light with wavelength

shorter than approximately 4,000 Å. Since sunlight and fluorescent lighting have wavelengths in

this range, exposure to these light sources over an extended time (about 1 week in sunlight, or 3

years in room-level fluorescent lighting) could cause inadvertent erasure. If an application sub-

jects the device to this type of exposure, it is suggested that an opaque label be placed over the

window.

18. Signature Bytes

The TS87C54/58X2 has four signature bytes in location 30h, 31h, 60h and 61h. To read these

bytes follow the procedure for EPROM verify but activate the control lines provided in Table 31.

for Read Signature Bytes. Table 18-1. shows the content of the signature byte for the

TS80C54/58X2.

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AT/TS8xC54/8X2

Table 18-1. Signature Bytes Content

Location

Contents

Comment

Manufacturer Code: Atmel Wireless &

Microcontrollers

30h

58h

31h

60h

61h

57h

37h

B7h

3Bh

BBh

FFh

Family Code: C51 X2

Product name: TS80C58X2

Product name: TS87C58X2

Product name: TS80C54X2

Product name: TS87C54X2

Product revision number

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4431E–8051–04/06

19. Electrical Characteristics

19.1 Absolute Maximum Ratings ⁽¹⁾

Ambiant Temperature Under Bias:

C = commercial0°C to 70°C

I = industrial -40°C to 85°C

Storage Temperature-65°C to + 150°C

Voltage on V_CCto V_SS-0.5 V to + 7 V

Voltage on V_PPto V_SS-0.5 V to + 13 V

Voltage on Any Pin to V_SS-0.5 V to V_CC+ 0.5 V

Power Dissipation1 W⁽²⁾

1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause per-

manent damage to the device. This is a stress rating only and functional operation of

the device at these or any other conditions above those indicated in the operational

sections of this specification is not implied. Exposure to absolute maximum rating con-

ditions may affect device reliability.

2. This value is based on the maximum allowable die temperature and the thermal resis-

tance of the package.

19.2 Power consumption measurement

Since the introduction of the first C51 devices, every manufacturer made operating Icc measure-

ments under reset, which made sense for the designs were the CPU was running under reset. In

Atmel new devices, the CPU is no more active during reset, so the power consumption is very

low but is not really representative of what will happen in the customer system. That’s why, while

keeping measurements under Reset, Atmel presents a new way to measure the operating Icc:

Using an internal test ROM, the following code is executed:

Label:

SJMP Label (80 FE)

Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not con-

nected and XTAL1 is driven by the clock.

This is much more representative of the real operating Icc.

19.3 DC Parameters for Standard Voltage

TA = 0°C to +70°C; V_SS= 0 V; V_CC= 5 V 10%; F = 0 to 40 MHz.

T^A= -40°C to +85°C; V_SS= 0 V; V_CC= 5 V 10%; F = 0 to 40 MHz.

Table 19-1. DC Parameters in Standard Voltage

Symbol

V_IL

Parameter

Min

-0.5

Typ

Max

Unit

V

Test Conditions

Input Low Voltage

0.2 V_CC- 0.1

V_CC+ 0.5

V_IH

Input High Voltage except XTAL1, RST

Input High Voltage, XTAL1, RST

0.2 V_CC+ 0.9

0.7 V_CC

V

V_IH1

V

0.3

0.45

1.0

V

I_OL= 100 μA⁽⁴⁾

I_OL= 1.6 mA⁽⁴⁾

I_OL= 3.5 mA⁽⁴⁾

V_OL

Output Low Voltage, ports 1, 2, 3 ⁽⁶⁾

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AT/TS8xC54/8X2

Symbol

Parameter

Min

Typ

Max

Unit

Test Conditions

0.3

0.45

1.0

V

I_OL= 200 μA⁽⁴⁾

I_OL= 3.2 mA⁽⁴⁾

I_OL= 7.0 mA⁽⁴⁾

V_OL1

Output Low Voltage, port 0 ⁽⁶⁾

0.3

0.45

1.0

V

I_OL= 100 μA⁽⁴⁾

I_OL= 1.6 mA⁽⁴⁾

I_OL= 3.5 mA⁽⁴⁾

V_OL2

Output Low Voltage, ALE, PSEN

Output High Voltage, ports 1, 2, 3

I_OH= -10 μA

I_OH= -30 μA

I_OH= -60 μA

V_CC= 5 V 10%

V

_CC- 0.3

V

V_OH

V_CC- 0.7

V_CC- 1.5

I

_OH= -200 μA

I_OH= -3.2 mA

_OH= -7.0 mA

V_CC- 0.3

V

V_OH1

Output High Voltage, port 0

V_CC- 0.7

I

V_CC- 1.5

V_CC= 5 V 10%

I_OH= -100 μA

I_OH= -1.6 mA

I_OH= -3.5 mA

V_CC= 5 V 10%

V_CC- 0.3

V_CC- 0.7

V_CC- 1.5

V

V_OH2

Output High Voltage,ALE, PSEN

R_RST

I_IL

RST Pulldown Resistor

50

90 ⁽⁵⁾

200

-50

kΩ

μA

Logical 0 Input Current ports 1, 2 and 3

Input Leakage Current

Vin = 0.45 V

I_LI

10

0.45 V < Vin < V_CC

Vin = 2.0 V

I_TL

Logical 1 to 0 Transition Current, ports 1, 2, 3

-650

Fc = 1 MHz

T^A= 25°C

C_IO

I_PD

Capacitance of I/O Buffer

Power Down Current

10

50

pF

20 ⁽⁵⁾

μA

2.0 V < V_{CC <}5.5 V⁽³⁾

1 + 0.4 Freq

(MHz)

@12MHz 5.8

I_CC

Power Supply Current Maximum values, X1

mode: ⁽⁷⁾

under

RESET

V

_CC= 5.5 V⁽¹⁾

mA

@16MHz 7.4

3 + 0.6 Freq

(MHz)

@12MHz 10.2

I_CC

Power Supply Current Maximum values, X1

mode: ⁽⁷⁾

operating

V_CC= 5.5 V⁽⁸⁾

@16MHz 12.6

0.25+0.3 Freq

(MHz)

I_CC

Power Supply Current Maximum values, X1

mode: ⁽⁷⁾

V_CC= 5.5 V⁽²⁾

@12MHz 3.9

@16MHz 5.1

idle

mA

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4431E–8051–04/06

19.4 DC Parameters for Low Voltage

TA = 0°C to +70°C; V_SS= 0 V; V_CC= 2.7 V to 5.5 V 10%; F = 0 to 30 MHz.

T^A= -40°C to +85°C; V_SS= 0 V; V_CC= 2.7 V to 5.5 V 10%; F = 0 to 30 MHz.

Table 19-2. DC Parameters for Low Voltage

Symbol

V_IL

Parameter

Min

-0.5

Typ

Max

0.2 V_CC- 0.1

V_CC+ 0.5

0.45

Unit

V

Test Conditions

Input Low Voltage

V_IH

Input High Voltage except XTAL1, RST

Input High Voltage, XTAL1, RST

Output Low Voltage, ports 1, 2, 3 ⁽⁶⁾

Output Low Voltage, port 0, ALE, PSEN ⁽⁶⁾

Output High Voltage, ports 1, 2, 3

Output High Voltage, port 0, ALE, PSEN

Logical 0 Input Current ports 1, 2 and 3

Input Leakage Current

0.2 V_CC+ 0.9

0.7 V_CC

V

V_IH1

V_OL

V_OL1

V_OH

V_OH1

I_IL

V

I_OL= 0.8 mA⁽⁴⁾

0.45

V

I_OL= 1.6 mA⁽⁴⁾

I_OH= -10 μA

0.9 V_CC

V

I_OH= -40 μA

-50

10

μA

kΩ

Vin = 0.45 V

0.45 V < Vin < V_CC

Vin = 2.0 V

I_LI

I_TL

Logical 1 to 0 Transition Current, ports 1, 2, 3

RST Pulldown Resistor

-650

200

R_RST

50

90 ⁽⁵⁾

Fc = 1 MHz

T^A= 25°C

CIO

I_PD

Capacitance of I/O Buffer

10

pF

20 ⁽⁵⁾

10 ⁽⁵⁾

50

30

V_CC= 2.0 V to 5.5 V⁽³⁾

V_CC= 2.0 V to 3.3 V⁽³⁾

Power Down Current

μA

1 + 0.2 Freq

(MHz)

@12MHz 3.4

I_CC

Power Supply Current Maximum values, X1

mode: ⁽⁷⁾

under

RESET

V_CC= 3.3 V⁽¹⁾

mA

@16MHz 4.2

1 + 0.3 Freq

(MHz)

@12MHz 4.6

I_CC

Power Supply Current Maximum values, X1

mode: ⁽⁷⁾

V

_CC= 3.3 V⁽⁸⁾

operating

mA

@16MHz 5.8

0.15 Freq (MHz)

+ 0.2

I_CC

Power Supply Current Maximum values, X1

mode: ⁽⁷⁾

idle

V_CC= 3.3 V⁽²⁾

@12MHz 2

@16MHz 2.6

1.

I

_CCunder reset is measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns (see Figure

19-5.), V_IL= V_SS+ 0.5 V,

_IH= V_CC- 0.5V; XTAL2 N.C.; EA = RST = Port 0 = V_CC. I_CCwould be slightly higher if a crystal oscillator used..

2. Idle I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns, V_IL= V_SS+ 0.5 V,

_IH= V_CC- 0.5 V; XTAL2 N.C; Port 0 = V_CC; EA = RST = V_SS(see Figure 19-3.).

V

3. Power Down I_CCis measured with all output pins disconnected; EA = V_SS, PORT 0 = V_CC; XTAL2 NC.; RST = V_SS

(see Figure 19-4.).

4. Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the V_OLs of ALE

and Ports 1 and 3. The noise is due to external bus capacitance discharging into the Port 0 and Port 2 pins when

these pins make 1 to 0 transitions during bus operation. In the worst cases (capacitive loading 100pF), the noise

pulse on the ALE line may exceed 0.45V with maxi V_OLpeak 0.6V. A Schmitt Trigger use is not necessary.

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AT/TS8xC54/8X2

5. Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temper-

ature and 5V.

6. Under steady state (non-transient) conditions, I_OLmust be externally limited as follows:

Maximum I_OLper port pin: 10 mA

Maximum I_OLper 8-bit port:

Port 0: 26 mA

Ports 1, 2 and 3: 15 mA

Maximum total I_OLfor all output pins: 71 mA

If I_OLexceeds the test condition, V_OLmay exceed the related specification. Pins are not guaranteed to sink current

greater than the listed test conditions.

7. For other values, please contact your sales office.

8. Operating I_CCis measured with all output pins disconnected; XTAL1 driven with T_CLCH, T_CHCL= 5 ns (see Figure

19-5.), V_IL= V_SS+ 0.5 V,

V

_IH= V_CC- 0.5V; XTAL2 N.C.; EA = Port 0 = V_CC; RST = V_SS. The internal ROM runs the code 80 FE (label: SJMP

label). I_CCwould be slightly higher if a crystal oscillator is used. Measurements are made with OTP products when

possible, which is the worst case.

Figure 19-1. I_CCTest Condition, under reset

V_CC

I_CC

V_CC

P0

V_CC

RST

EA

XTAL2

XTAL1

(NC)

CLOCK

SIGNAL

V_SS

All other pins are disconnected.

Figure 19-2. Operating I_CCTest Condition

V_CC

I_CC

V_CC

P0

EA

RST

XTAL2

XTAL1

(NC)

CLOCK

SIGNAL

All other pins are disconnected.

V_SS

45

4431E–8051–04/06

Figure 19-3. I_CCTest Condition, Idle Mode

V_CC

I_CC

V_CC

P0

EA

RST

(NC)

CLOCK

SIGNAL

XTAL2

XTAL1

All other pins are disconnected.

V_SS

Figure 19-4. I_CCTest Condition, Power-Down Mode

V_CC

I_CC

V_CC

P0

EA

RST

(NC)

XTAL2

XTAL1

V_SS

All other pins are disconnected.

Figure 19-5. Clock Signal Waveform for I_CCTests in Active and Idle Modes

V_CC-0.5V

0.7V_CC

0.2V_CC-0.1

0.45V

T_CLCH

T_CHCL

T_CLCH= T_CHCL= 5ns.

46

AT/TS8xC54/8X2

4431E–8051–04/06

AT/TS8xC54/8X2

19.5 AC Parameters

19.5.1

Explanation of the AC Symbols

Each timing symbol has 5 characters. The first character is always a “T” (stands for time). The

other characters, depending on their positions, stand for the name of a signal or the logical sta-

tus of that signal. The following is a list of all the characters and what they stand for.

Example:T_AVLL= Time for Address Valid to ALE Low.

T_LLPL= Time for ALE Low to PSEN Low.

T^A= 0 to +70°C (commercial temperature range); V_SS= 0 V; V_CC= 5 V 10%; -M and -V ranges.

T^A= -40°C to +85°C (industrial temperature range); V_SS= 0 V; V_CC= 5 V 10%; -M and -V

ranges.

T^A= 0 to +70°C (commercial temperature range); V_SS= 0 V; 2.7 V < V_{CC <}5.5 V; -L range.

T^A= -40°C to +85°C (industrial temperature range); V_SS= 0 V; 2.7 V < V_{CC <}5.5 V; -L range.

Table 19-3. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE

and PSEN signals. Timings will be guaranteed if these capacitances are respected. Higher

capacitance values can be used, but timings will then be degraded.

Table 19-3. Load Capacitance versus speed range, in pF

-M

100

80

-V

50

30

-L

Port 0

100

80

Port 1, 2, 3

ALE / PSEN

100

Table 19-5., Table 19-8. and Table 19-11. give the description of each AC symbols.

Table 19-6., Table 19-9. and Table 19-12. give for each range the AC parameter.

Table 19-7., Table 19-10. and Table 19-13. give the frequency derating formula of the AC

parameter. To calculate each AC symbols, take the x value corresponding to the speed grade

you need (-M, -V or -L) and replace this value in the formula. Values of the frequency must be

limited to the corresponding speed grade:

Table 19-4. Max frequency for derating formula regarding the speed grade

-M X1 mode

-M X2 mode

-V X1 mode

-V X2 mode

-L X1 mode

-L X2 mode

Freq (MHz)

T (ns)

40

25

20

50

40

25

30

20

50

33.3

Example:

T_LLIVin X2 mode for a -V part at 20 MHz (T = 1/20^E6= 50 ns):

x= 22 (Table 19-7.)

T= 50ns

T

_LLIV= 2T - x = 2 x 50 - 22 = 78ns

47

4431E–8051–04/06

19.5.2

External Program Memory Characteristics

Table 19-5. Symbol Description

Symbol

T

Parameter

Oscillator clock period

ALE pulse width

T_LHLL

T_AVLL

T_LLAX

T_LLIV

T_LLPL

T_PLPH

T_PLIV

T_PXIX

T_PXIZ

T_PXAV

T_AVIV

T_PLAZ

Address Valid to ALE

Address Hold After ALE

ALE to Valid Instruction In

ALE to PSEN

PSEN Pulse Width

PSEN to Valid Instruction In

Input Instruction Hold After PSEN

Input Instruction FloatAfter PSEN

PSEN to Address Valid

Address to Valid Instruction In

PSEN Low to Address Float

Table 19-6. AC Parameters for Fix Clock

-V

-L

-V

X2 mode

30 MHz

X2 mode

20 MHz

-L

standard mode 40

MHz

-M

standard mode

30 MHz

Speed

Symbol

T

40 MHz

60 MHz equiv.

40 MHz equiv.

Units

Min

Max

Min

33

25

4

Max

Min

25

Max

Min

50

35

5

Max

Min

33

Max

25

40

10

ns

T_LHLL

T_AVLL

T_LLAX

T_LLIV

42

52

12

13

4

12

5

13

70

35

45

25

78

50

65

30

98

55

T_LLPL

T_PLPH

T_PLIV

T_PXIX

T_PXIZ

T_AVIV

T_PLAZ

15

55

9

17

60

10

50

18

75

35

0

18

85

10

12

53

10

20

95

10

80

10

18

122

10

48

AT/TS8xC54/8X2

4431E–8051–04/06

AT/TS8xC54/8X2

Table 19-7. AC Parameters for a Variable Clock: derating formula

Standard

Clock

Symbol

T_LHLL

T_AVLL

T_LLAX

T_LLIV

Type

Min

X2 Clock

T - x

-M

10

15

30

10

20

40

0

-V

8

-L

15

20

35

15

25

45

0

Units

ns

2 T - x

T - x

4 T - x

T - x

3 T - x

x

Min

0.5 T - x

2 T - x

0.5 T - x

1.5 T - x

x

13

22

8

ns

Min

ns

Max

Min

ns

T_LLPL

T_PLPH

T_PLIV

T_PXIX

T_PXIZ

T_AVIV

ns

Min

15

25

0

ns

Max

Min

ns

Max

T - x

5 T - x

x

0.5 T - x

2.5 T - x

x

7

5

15

45

10

ns

40

10

30

10

ns

T_PLAZ

ns

19.5.3

External Program Memory Read Cycle

Figure 19-6. External Program Memory Read Cycle

12 T_CLCL

T_LHLL

T_LLIV

T_LLPL

ALE

PSEN

T_PLPH

T_PXAV

T_PXIZ

T_LLAX

T_AVLL

T_PLIV

TPLAZ

T_PXIX

INSTR IN

PORT 0

PORT 2

INSTR IN

A0-A7

INSTR IN

T_AVIV

ADDRESS A8-A15

ADDRESS

OR SFR-P2

ADDRESS A8-A15

49

4431E–8051–04/06

19.5.4

External Data Memory Characteristics

Table 19-8. Symbol Description

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Parameter

RD Pulse Width

WR Pulse Width

RD to Valid Data In

Data Hold After RD

Data Float After RD

ALE to Valid Data In

Address to Valid Data In

ALE to WR or RD

T_AVDV

T_LLWL

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

Address to WR or RD

Data Valid to WR Transition

Data set-up to WR High

Data Hold After WR

RD Low to Address Float

RD or WR High to ALE high

T_WHLH

Table 19-9. AC Parameters for a Fix Clock

-V

-L

-V

X2 mode

30 MHz

X2 mode

20 MHz

standard mode

30 MHz

standard mode 40

MHz

Speed

-M

40 MHz

60 MHz equiv.

40 MHz equiv.

Units

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Min

Max

Min

85

Max

Min

135

Max

Min

125

Max

Min

175

Max

130

ns

85

100

60

102

95

137

0

30

18

98

35

165

175

95

25

42

160

165

100

155

160

105

222

235

130

T_AVDV

100

70

T_LLWL

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

50

75

30

47

7

55

80

45

70

5

70

103

13

10

15

160

15

107

9

165

17

155

10

213

18

0

T_WHLH

10

40

7

27

15

35

5

45

13

53

50

AT/TS8xC54/8X2

4431E–8051–04/06

AT/TS8xC54/8X2

Table 19-10. AC Parameters for a Variable Clock: derating formula

Standard

Clock

Symbol

T_RLRH

T_WLWH

T_RLDV

T_RHDX

T_RHDZ

T_LLDV

Type

Min

Max

Min

Max

Min

Max

Min

Max

Min

Max

X2 Clock

3 T - x

2.5 T - x

x

-M

20

25

0

-V

15

23

0

-L

25

30

0

Units

ns

6 T - x

5 T - x

x

2 T - x

8 T - x

9 T - x

3 T - x

3 T + x

4 T - x

T - x

20

40

60

25

15

10

0

15

35

50

20

10

8

25

45

65

30

20

15

0

4T -x

T_AVDV

T_LLWL

4.5 T - x

1.5 T - x

1.5 T + x

2 T - x

0.5 T - x

3.5 T - x

0.5 T - x

x

T_LLWL

T_AVWL

T_QVWX

T_QVWH

T_WHQX

T_RLAZ

T_WHLH

7 T - x

T - x

x

0

T - x

0.5 T - x

0.5 T + x

15

10

20

T + x

19.5.5

External Data Memory Write Cycle

Figure 19-7. External Data Memory Write Cycle

T_WHLH

ALE

PSEN

WR

T_LLWL

T_WLWH

T_QVWX

T_WHQX

T_LLAX

T_QVWH

DATA OUT

PORT 0

PORT 2

A0-A7

T_AVWL

ADDRESS

ADDRESS A8-A15 OR SFR P2

OR SFR-P2

51

4431E–8051–04/06

19.5.6

External Data Memory Read Cycle

Figure 19-8. External Data Memory Read Cycle

T_WHLH

T_LLDV

ALE

PSEN

RD

T_LLWL

T_RLRH

T_RHDZ

T_AVDV

T_LLAX

T_RHDX

DATA IN

PORT 0

PORT 2

A0-A7

T_RLAZ

T_AVWL

ADDRESS

OR SFR-P2

ADDRESS A8-A15 OR SFR P2

19.5.7

Serial Port Timing - Shift Register Mode

Table 19-11. Symbol Description

Symbol

Parameter

T_XLXL

T_QVHX

T_XHQX

T_XHDX

T_XHDV

Serial port clock cycle time

Output data set-up to clock rising edge

Output data hold after clock rising edge

Input data hold after clock rising edge

Clock rising edge to input data valid

Table 19-12. AC Parameters for a Fix Clock

-V

-L

X2 mode

30 MHz

standard mode 40

MHz

X2 mode

20 MHz

standard mode

30 MHz

-M

Speed

40 MHz

60 MHz equiv.

40 MHz equiv.

Units

Symbol

T_XLXL

Min

Max

Min

200

117

13

Max

Min

300

200

30

Max

Min

300

200

30

Max

Min

400

283

47

Max

300

200

30

ns

T_QVHX

T_XHQX

T_XHDX

T_XHDV

0

117

34

117

200

52

AT/TS8xC54/8X2

4431E–8051–04/06

AT/TS8xC54/8X2

Table 19-13. AC Parameters for a Variable Clock: derating formula

Standard

Clock

Symbol

T_XLXL

Type

Min

Max

X2 Clock

6 T

-M

-V

-L

Units

ns

12 T

10 T - x

2 T - x

x

T_QVHX

T_XHQX

T_XHDX

T_XHDV

5 T - x

T - x

50

20

0

50

20

0

50

20

0

ns

x

ns

10 T - x

5 T- x

133

ns

19.5.8

Shift Register Timing Waveforms

Figure 19-9. Shift Register Timing Waveforms

0

1

2

3

4

5

6

7

8

INSTRUCTION

ALE

T_XLXL

CLOCK

T_XHQX

1

T_QVXH

0

2

3

4

5

6

7

OUTPUT DATA

T_XHDX

SET TI

T_XHDV

WRITE to SBUF

INPUT DATA

SET RI

CLEAR RI

53

4431E–8051–04/06

19.5.9

EPROM Programming and Verification Characteristics

T^A= 21°C to 27°C; V_SS= 0V; V_CC= 5V 10% while programming. V_CC= operating range while

verifying

Table 19-14. EPROM Programming Parameters

Symbol

V_PP

Parameter

Programming Supply Voltage

Programming Supply Current

Oscillator Frquency

Min

Max

13

75

6

Units

V

12.5

I_PP

mA

1/T_CLCL

T_AVGL

T_GHAX

T_DVGL

T_GHDX

T_EHSH

T_SHGL

T_GHSL

T_GLGH

T_AVQV

T_ELQV

T_EHQZ

4

MHz

Address Setup to PROG Low

Adress Hold after PROG

Data Setup to PROG Low

Data Hold after PROG

(Enable) High to V_PP

48 T_CLCL

10

V_PPSetup to PROG Low

V_PPHold after PROG

PROG Width

μs

10

90

110

Address to Valid Data

48 T_CLCL

ENABLE Low to Data Valid

Data Float after ENABLE

0

19.5.10 EPROM Programming and Verification Waveforms

Figure 19-10. EPROM Programming and Verification Waveforms

PROGRAMMING

ADDRESS

VERIFICATION

ADDRESS

T_AVQV

P1.0-P1.7

P2.0-P2.5

P3.4-P3.5*

P

DATA OUT

P0

DATA IN

T_GHDX

T_GHAX

T_DVGL

T_AVGL

ALE/PROG

EA/V_PP

T_SHGL

T_GHSL

T_GLGH

V_PP

V_CC

T_ELQV

T_EHSH

T_EHQZ

CONTROL

SIGNALS

(ENABLE)

54

AT/TS8xC54/8X2

4431E–8051–04/06

AT/TS8xC54/8X2

19.5.11 External Clock Drive Characteristics (XTAL1)

Table 19-15. AC Parameters

Symbol

T_CLCL

Parameter

Min

25

5

Max

Units

ns

Oscillator Period

High Time

T_CHCX

ns

T_CLCX

Low Time

5

ns

T_CLCH

Rise Time

5

ns

T_CHCL

Fall Time

ns

T_CHCX/T_CLCX

Cyclic ratio in X2 mode

40

60

%

19.5.12 External Clock Drive Waveforms

Figure 19-11. External Clock Drive Waveforms

55

4431E–8051–04/06

19.5.13 AC Testing Input/Output Waveforms

Figure 19-12. AC Testing Input/Output Waveforms

AC inputs during testing are driven at V_CC- 0.5 for a logic “1” and 0.45V for a logic “0”. Timing

measurement are made at V_IHmin for a logic “1” and V_ILmax for a logic “0”.

19.5.14 Float Waveforms

Figure 19-13. Float Waveforms

For timing purposes a port pin is no longer floating when a 100 mV change from load voltage

occurs and begins to float when a 100 mV change from the loaded V_OH/V_OLlevel occurs. I_OL/I_OH

≥

20mA.

19.5.15 Clock Waveforms

Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by

two.

56

AT/TS8xC54/8X2

4431E–8051–04/06

AT/TS8xC54/8X2

Figure 19-14. Clock Waveforms

STATE1

P1P2

STATE2

P1P2

STATE3

P1P2

STATE4

P1P2

STATE4

P1P2

STATE5

P1P2

STATE6

P1P2

STATE5

P1P2

CLOCK

XTAL2

ALE

THESE SIGNALS ARE NOT ACTIVATED DURING THE

EXECUTION OF A MOVX INSTRUCTION

PSEN

P0

PCL OUT

DATA

SAMPLED

FLOAT

DATA

SAMPLED

FLOAT

SAMPLED

FLOAT

INDICATES ADDRESS

P2 (EXT)

RD

P0

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

DPL OR Rt

FLOAT

P2

INDICATES DPH OR P2 SFR TO PCH

TRANSITION

WR

P0

PCL OUT (EVEN IF PROGRAM

MEMORY IS INTERNAL)

DPL OR Rt OUT

DATA OUT

PCL OUT (IF PROGRAM

MEMORY IS EXTERNAL)

P2

INDICATES DPH OR P2 SFR TO PCH

TRANSITION

OLD DATA

P0 PINS SAMPLED

NEW DATA

P0 PINS SAMPLED

MOV DEST P0

P1, P2, P3 PINS SAMPLED

RXD SAMPLED

P1, P2, P3 PINS SAMPLED

MOV DEST PORT (P1, P2, P3)

(INCLUDES INT0, INT1, TO, T1)

RXD SAMPLED

TXD (MODE 0)

This diagram indicates when signals are clocked internally. The time it takes the signals to prop-

agate to the pins, however, ranges from 25 to 125 ns. This propagation delay is dependent on

variables such as temperature and pin loading. Propagation also varies from output to output

and component. Typically though (T_A=25°C fully loaded) RD and WR propagation delays are

approximately 50ns. The other signals are typically 85 ns. Propagation delays are incorporated

in the AC specifications.

57

4431E–8051–04/06

20. Ordering Information

Table 20-1. Possible Ordering Entries

Part Number

Supply Voltage

-5 to +/-10%

Temperature Range

Commercial

Industrial

Package

PDIL40

Packing

Stick

Tray

Stick

Tray

Stick

Tray

Stick

Tray

Stick

Tray

Stick

Tray

TS80C54X2xxx-MCA

TS80C54X2xxx-MCB

TS80C54X2xxx-MCC

TS80C54X2xxx-MCE

TS80C54X2xxx-VCA

TS80C54X2xxx-VCB

TS80C54X2xxx-VCC

TS80C54X2xxx-VCE

TS80C54X2xxx-LCA

TS80C54X2xxx-LCB

TS80C54X2xxx-LCC

TS80C54X2xxx-LCE

TS80C54X2xxx-MIA

TS80C54X2xxx-MIB

TS80C54X2xxx-MIC

TS80C54X2xxx-MIE

TS80C54X2xxx-VIA

TS80C54X2xxx-VIB

TS80C54X2xxx-VIC

TS80C54X2xxx-VIE

TS80C54X2xxx-LIA

TS80C54X2xxx-LIB

TS80C54X2xxx-LIC

TS80C54X2xxx-LIE

PLCC44

PQFP44

VQFP44

PDIL40

PLCC44

PQFP44

VQFP44

PDIL40

PLCC44

PQFP44

VQFP44

PDIL40

Industrial

PLCC44

PQFP44

VQFP44

PDIL40

Industrial

PLCC44

PQFP44

VQFP44

PDIL40

Industrial

PLCC44

PQFP44

VQFP44

Industrial

AT80C54X2zzz-3CSUM

AT80C54X2zzz-SLSUM

AT80C54X2zzz-RLTUM

AT80C54X2zzz-3CSUL

AT80C54X2zzz-SLSUL

AT80C54X2zzz-RLTUL

AT80C54X2zzz-3CSUV

AT80C54X2zzz-SLSUV

AT80C54X2zzz-RLTUV

-5 to +/-10%

Industrial & Green

PDIL40

PLCC44

VQFP44

PDIL40

PLCC44

VQFP44

PDIL40

PLCC44

VQFP44

Stick

Tray

Stick

Tray

Stick

Tray

TS87C54X2-MCA

TS87C54X2-MCB

5V ±10%

Commercial

PDIL40

Stick

PLCC44

58

AT/TS8xC54/8X2

4431E–8051–04/06

AT/TS8xC54/8X2

Part Number

TS87C54X2-MCC

TS87C54X2-MCE

TS87C54X2-VCA

TS87C54X2-VCB

TS87C54X2-VCC

TS87C54X2-VCE

TS87C54X2-LCA

TS87C54X2-LCB

TS87C54X2-LCC

TS87C54X2-LCE

TS87C54X2-MIA

TS87C54X2-MIB

TS87C54X2-MIC

TS87C54X2-MIE

TS87C54X2-VIA

TS87C54X2-VIB

TS87C54X2-VIC

TS87C54X2-VIE

TS87C54X2-LIA

TS87C54X2-LIB

TS87C54X2-LIC

TS87C54X2-LIE

Supply Voltage

5V ±10%

2.7 to 5.5V

5V ±10%

2.7 to 5.5V

Temperature Range

Commercial

Industrial

Package

PQFP44

VQFP44

PDIL40

Packing

Tray

Stick

Tray

Stick

Tray

Stick

Tray

Stick

Tray

Stick

Tray

PLCC44

PQFP44

VQFP44

PDIL40

PLCC44

PQFP44

VQFP44

PDIL40

Industrial

PLCC44

PQFP44

VQFP44

PDIL40

Industrial

PLCC44

PQFP44

VQFP44

PDIL40

Industrial

PLCC44

PQFP44

VQFP44

Industrial

AT87C54X2-3CSUM

AT87C54X2-SLSUM

AT87C54X2-RLTUM

AT87C54X2-3CSUL

AT87C54X2-SLSUL

AT87C54X2-RLTUL

AT87C54X2-3CSUV

AT87C54X2-SLSUV

AT87C54X2-RLTUV

5V ±10%

2.7 to 5.5V

5V ±10%

Industrial & Green

PDIL40

PLCC44

VQFP44

PDIL40

Stick

Tray

Stick

Tray

Stick

Tray

PLCC44

VQFP44

PDIL40

PLCC44

VQFP44

59

4431E–8051–04/06

Part Number

Supply Voltage

-5 to +/-10%

Temperature Range

Commercial

Industrial

Package

PDIL40

Packing

Stick

Tray

Stick

Tray

Stick

Tray

Stick

Tray

Stick

Tray

Stick

Tray

TS80C58X2xxx-MCA

TS80C58X2xxx-MCB

TS80C58X2xxx-MCC

TS80C58X2xxx-MCE

TS80C58X2xxx-VCA

TS80C58X2xxx-VCB

TS80C58X2xxx-VCC

TS80C58X2xxx-VCE

TS80C58X2xxx-LCA

TS80C58X2xxx-LCB

TS80C58X2xxx-LCC

TS80C58X2xxx-LCE

TS80C58X2xxx-MIA

TS80C58X2xxx-MIB

TS80C58X2xxx-MIC

TS80C58X2xxx-MIE

TS80C58X2xxx-VIA

TS80C58X2xxx-VIB

TS80C58X2xxx-VIC

TS80C58X2xxx-VIE

TS80C58X2xxx-LIA

TS80C58X2xxx-LIB

TS80C58X2xxx-LIC

TS80C58X2xxx-LIE

PLCC44

PQFP44

VQFP44

PDIL40

PLCC44

PQFP44

VQFP44

PDIL40

PLCC44

PQFP44

VQFP44

PDIL40

Industrial

PLCC44

PQFP44

VQFP44

PDIL40

Industrial

PLCC44

PQFP44

VQFP44

PDIL40

Industrial

PLCC44

PQFP44

VQFP44

Industrial

AT80C58X2zzz-3CSUM

AT80C58X2zzz-SLSUM

AT80C58X2zzz-RLTUM

AT80C58X2zzz-3CSUL

AT80C58X2zzz-SLSUL

AT80C58X2zzz-RLTUL

AT80C58X2zzz-3CSUV

AT80C58X2zzz-SLSUV

AT80C58X2zzz-RLTUV

-5 to +/-10%

Industrial & Green

PDIL40

PLCC44

VQFP44

PDIL40

Stick

Tray

Stick

Tray

Stick

Tray

PLCC44

VQFP44

PDIL40

PLCC44

VQFP44

TS87C58X2-MCA

TS87C58X2-MCB

TS87C58X2-MCC

5V ±10%

Commercial

PDIL40

PLCC44

PQFP44

Stick

Tray

60

AT/TS8xC54/8X2

4431E–8051–04/06

AT/TS8xC54/8X2

Part Number

TS87C58X2-MCE

TS87C58X2-VCA

TS87C58X2-VCB

TS87C58X2-VCC

TS87C58X2-VCE

TS87C58X2-LCA

TS87C58X2-LCB

TS87C58X2-LCC

TS87C58X2-LCE

TS87C58X2-MIA

TS87C58X2-MIB

TS87C58X2-MIC

TS87C58X2-MIE

TS87C58X2-VIA

TS87C58X2-VIB

TS87C58X2-VIC

TS87C58X2-VIE

TS87C58X2-LIA

TS87C58X2-LIB

TS87C58X2-LIC

TS87C58X2-LIE

Supply Voltage

5V ±10%

Temperature Range

Commercial

Industrial

Package

VQFP44

PDIL40

Packing

Tray

Stick

Tray

Stick

Tray

Stick

Tray

Stick

Tray

Stick

Tray

5V ±10%

PLCC44

PQFP44

VQFP44

PDIL40

5V ±10%

2.7 to 5.5V

5V ±10%

PLCC44

PQFP44

VQFP44

PDIL40

5V ±10%

Industrial

PLCC44

PQFP44

VQFP44

PDIL40

5V ±10%

Industrial

5V ±10%

Industrial

5V ±10%

Industrial

5V ±10%

Industrial

PLCC44

PQFP44

VQFP44

PDIL40

5V ±10%

Industrial

5V ±10%

Industrial

2.7 to 5.5V

Industrial

PLCC44

PQFP44

VQFP44

Industrial

AT87C58X2-3CSUM

AT87C58X2-SLSUM

AT87C58X2-RLTUM

AT87C58X2-3CSUL

AT87C58X2-SLSUL

AT87C58X2-RLTUL

AT87C58X2-3CSUV

AT87C58X2-SLSUV

AT87C58X2-RLTUV

5V ±10%

2.7 to 5.5V

5V ±10%

Industrial & Green

PDIL40

PLCC44

VQFP44

PDIL40

Stick

Tray

Stick

Tray

Stick

Tray

PLCC44

VQFP44

PDIL40

PLCC44

VQFP44

21. Datasheet Revision History

21.1 Changes from Rev. C 01/01 to Rev. D 11/05

1. Added green product Ordering Information.

21.2 Changes from Rev. D 11/05 to Rev. E 04/06

1. Changed value of AUXR register.

61

4431E–8051–04/06

Atmel Corporation

Atmel Operations

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Tel: 1(408) 441-0311

Fax: 1(408) 487-2600

Memory

RF/Automotive

Theresienstrasse 2

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74025 Heilbronn, Germany

Tel: (49) 71-31-67-0

Fax: (49) 71-31-67-2340

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

Regional Headquarters

Microcontrollers

2325 Orchard Parkway

San Jose, CA 95131, USA

Tel: 1(408) 441-0311

Fax: 1(408) 436-4314

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Tel: 1(719) 576-3300

Europe

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Switzerland

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Biometrics/Imaging/Hi-Rel MPU/

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Avenue de Rochepleine

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Fax: (33) 2-40-18-19-60

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Fax: (33) 4-76-58-34-80

Asia

Room 1219

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East Kowloon

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ASIC/ASSP/Smart Cards

Zone Industrielle

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Japan

9F, Tonetsu Shinkawa Bldg.

1-24-8 Shinkawa

Chuo-ku, Tokyo 104-0033

Japan

Tel: (81) 3-3523-3551

Fax: (81) 3-3523-7581

Fax: 1(719) 540-1759

Scottish Enterprise Technology Park

Maxwell Building

East Kilbride G75 0QR, Scotland

Tel: (44) 1355-803-000

Fax: (44) 1355-242-743

Literature Requests

www.atmel.com/literature

Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any

intellectual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN ATMEL’S TERMS AND CONDI-

TIONS OF SALE LOCATED ON ATMEL’S WEB SITE, ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS, IMPLIED OR STATUTORY

WARRANTY RELATING TO ITS PRODUCTS INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTY OF MERCHANTABILITY, FITNESS FOR A PARTICULAR

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Printed on recycled paper.

4431E–8051–04/06


型号：	TS87C58X2_14
厂家：	ATMEL
描述：	Programmable Clock Out and Up/Down Timer/Counter 2
文件：	总62页 (文件大小：527K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TS87C58X2_14 [ATMEL]

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