TSPC2605MG66 [ATMEL]
Microprocessor Circuit, BICMOS, CBGA241, CERAMIC, BGA-241;
| 型号： | TSPC2605MG66 |
| 厂家： | 
ATMEL |
| 描述： | Microprocessor Circuit, BICMOS, CBGA241, CERAMIC, BGA-241 ATM 异步传输模式 信息通信管理 外围集成电路 |
| 文件： | 总36页 (文件大小：291K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TSPC2605
INTEGRATED SECONDARY CACHE MODULE
FOR PowerPCt MICROPROCESSORS
DESCRIPTION
The TSPC2605 is a single chip, 256KB integrated look–aside
cache with copy–back capability designed for PowerPC
applications (TSPC603e). Using 0.38 µm technology along
with standard cell logic technology, the TSPC2605 integrates
data, tag, host interface, and least recently used (LRU)
memory with a cache controller to provide a 256KB, 512KB, or
1 MB Level 2 cache with one, two, or four chips on a 64–bit
PowerPC bus.
MAIN FEATURES
H Single Chip L2 Cache for PowerPC
H 66 MHz Zero Wait State Performance (2–1–1–1 Burst)
H Four–Way Set Associative Cache Design
H 32K x 72 Data Memory Array
PBGA 241
ZP suffix
Plastic Ball Grid Array
H 8K x 18 Tag Array
H Address Parity Support
H LRU Cache Control Logic
H Copy–Back or Write–Through Modes of Operation
H Copy–Back Buffer for Improved Performance
H Single 3.3 V Power Supply
H 5 V Tolerant I/O
H 1, 2, or 4 Chip Cache Solution (256KB, 512KB, or 1MB)
H Single Clock Operation
H Compliant with IEEE Standard 1149.1 Test Access Port
(JTAG)
H Supports up to 4 Processors in a Shared Cache
Configuration
SCREENING / QUALITY / PACKAGING
CBGA 241
G suffix
This product is manufactured in full compliance with :
H MIL-STD-883 class B or According to TCS standards
H Upscreening based upon TCS standards
Ceramic Ball Grid Array
(To be introduced)
H Full military temperature range (Tc = -55°C, Tc = +125°C)
Industrial temperature range (Tc = –40°C, Tc = +110°C)
H Power Supply = 3.3 V ± 5 %.
H 241–pin PBGA and CBGA packages
May 1998
1/36
TSPC2605
SUMMARY
5.4.3.Data Streaming . . . . . . . . . . . . . . . . . . . . . . 15
5.4.4.Data Bus Parking . . . . . . . . . . . . . . . . . . . . 15
5.4.5.Processor Reads . . . . . . . . . . . . . . . . . . . . . 15
5.4.6.Processor Writes . . . . . . . . . . . . . . . . . . . . . 16
5.4.7.Transaction Pipelining . . . . . . . . . . . . . . . . 16
A. GENERAL DESCRIPTION . . . . . . . . . . . . . . 3
1. PIN ASSIGNMENT . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2. SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 4
3. SIMPLIFIED BLOCK DIAGRAM . . . . . . . . . . . . . . 6
5.5. Memory coherence . . . . . . . . . . . . . . . . . . . . 16
5.5.1.Snoop Reads . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5.2.Snoop Writes . . . . . . . . . . . . . . . . . . . . . . . . 16
5.5.3.Snoop Kills . . . . . . . . . . . . . . . . . . . . . . . . . . 16
B. DETAILED SPECIFICATIONS . . . . . . . . . . . 7
1. SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
2. APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . . 7
3. REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.1. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3.2. Design and construction . . . . . . . . . . . . . . . . . 7
5.6. Two/Four Chip Implementation . . . . . . . . . . 17
5.6.1.Multiple Castouts . . . . . . . . . . . . . . . . . . . . . 17
5.6.2.Snoop Hit Before Castout . . . . . . . . . . . . . 17
5.7. Multiprocessing . . . . . . . . . . . . . . . . . . . . . . . . 17
5.8. Powering–Down . . . . . . . . . . . . . . . . . . . . . . . 17
3.2.1.Terminal connections . . . . . . . . . . . . . . . . .
3.2.2.Lead material and finish . . . . . . . . . . . . . . .
3.2.3.Hermetic Package . . . . . . . . . . . . . . . . . . . .
7
7
7
5.9. Asynchronous signals . . . . . . . . . . . . . . . . . . 17
5.9.1.L2 FLUSH . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.9.2.L2 MISS INH . . . . . . . . . . . . . . . . . . . . . . . . 18
5.9.3.L2 TAG CLR . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.9.4.L2 UPDATE INH . . . . . . . . . . . . . . . . . . . . . 18
3.3. Absolute maximum ratings . . . . . . . . . . . . . . . 7
3.4. Thermal Characteristics . . . . . . . . . . . . . . . . . 7
3.4.1.PBGA Package . . . . . . . . . . . . . . . . . . . . . .
3.4.2.CBGA Package . . . . . . . . . . . . . . . . . . . . . .
7
8
3.5. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . 9
4.1. Recommanded Operating Conditions . . . . . . 9
4.2. DC Characteristics . . . . . . . . . . . . . . . . . . . . . . 9
4.3. Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
5.11.Test Access Port Description . . . . . . . . . . . . 28
5.11.1.Instruction Set . . . . . . . . . . . . . . . . . . . . . . 28
5.11.2.Standard Instructions . . . . . . . . . . . . . . . . 28
5.11.3.SAMPLE/PRELOAD TAP Instruction . . . 28
5.11.4.EXTEST TAP Instruction . . . . . . . . . . . . . 28
5.11.5.CLAMP TAP Instruction . . . . . . . . . . . . . . 28
5.11.6.HIGHZ TAP Instruction . . . . . . . . . . . . . . . 28
5.11.7.BYPASS TAP Instruction . . . . . . . . . . . . . 28
5.11.8.Disabling the TAP and Boundary Scan . 29
4.4. AC Operating Conditions . . . . . . . . . . . . . . . 10
4.4.1.AC Clock Specification . . . . . . . . . . . . . . . . 10
4.4.2.AC Specifications . . . . . . . . . . . . . . . . . . . . 10
4.4.3.Response to 60X Transfer Attributes . . . . 11
4.4.4.Response to Chipset Transfer Attributes . 11
4.4.5.Transfer Attributes for L2 Copy–Back . . . 11
5.12.Boundary Scan Order . . . . . . . . . . . . . . . . . . 30
5.12.1.Bit number . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.12.2.Bit/pin name . . . . . . . . . . . . . . . . . . . . . . . . 30
5.12.3.Bit/pin type . . . . . . . . . . . . . . . . . . . . . . . . . 30
5.12.4.Output enable . . . . . . . . . . . . . . . . . . . . . . 30
4.5. JTAG AC Operating Conditions . . . . . . . . . . 12
4.5.1.TAP Controller Timing . . . . . . . . . . . . . . . . . 12
5. FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . 13
5.1. System Usage and Requirments . . . . . . . . . 13
5.1.1.Comprehension of L2 CLAIM . . . . . . . . . . 13
5.1.2.Pipeline Depth . . . . . . . . . . . . . . . . . . . . . . . 13
5.1.3.Bus mastering . . . . . . . . . . . . . . . . . . . . . . . 13
6. PREPARATION FOR DELIVERY . . . . . . . . . . . . . 33
6.1. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
6.2. Certificate of compliance . . . . . . . . . . . . . . . . 33
7. HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
8. PACKAGE MECHANICAL DATA . . . . . . . . . . . . 34
8.1. 241 pins – PBGA . . . . . . . . . . . . . . . . . . . . . . 34
8.2. 241 pins – CBGA . . . . . . . . . . . . . . . . . . . . . . 35
9. ORDERING INFORMATION . . . . . . . . . . . . . . . . 36
5.2. Configuration pins . . . . . . . . . . . . . . . . . . . . . 13
5.2.1.CFG0 – CFG2 . . . . . . . . . . . . . . . . . . . . . . . 13
5.2.2.CFG3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.2.3.CFG4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
5.3. Reset/Initialization . . . . . . . . . . . . . . . . . . . . . 14
5.4. 60X bus operation . . . . . . . . . . . . . . . . . . . . . 14
5.4.1.Address Tenures . . . . . . . . . . . . . . . . . . . . . 14
5.4.2.Data Tenures . . . . . . . . . . . . . . . . . . . . . . . . 15
2/36
TSPC2605
A. GENERAL DESCRIPTION
1. PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
A
ABB L2 BG DH20 DH19 DH17 DH31 DH29 DH27 DH26 DL16 DL19 DL22 DP6 DL25 DL27 DL29 DL30
B
C
D
E
CPU3 CFG4 L2 DH23 DH21 DH18 DH16 DH30 DH28 DH25 DL17 DL20 DL23 DL24 DL26 DL28 DL31 DP7 APE
MISS INH
BG
FDN CPU3 CPU3
BR DBG
V
DP2 DH22
V
DP3
V
DH24 DL18 DL21
V
V
V
V
DD
AP3 AP2
AP1
DD
SS
SS
SS
SS
DD
L2 BR CPU2 CPU2
BR DBG
V
V
V
V
V
V
V
AP0
L2
FLUSH
L2
CI
SS
SS
DD
DD
DD
SS
SS
APEN
TA L2 DBG CPU2
BG
CFG3
GBL
F
CPU
DBG CLAIM
L2
NC
TSIZ1 TSIZ0 TSIZ2
A13
G
ARTRY CI AAC
K
V
V
V
V
V
SS
SS
SS
SS
SS
SS
H
J
WT
TEA CPU
BR
V
V
V
V
V
SS
V
A14 A15 A16
A19 A18 A17
DD
DD
DD
SS
DD
SS
SS
SS
SS
HRESET DBB PWRDN V
V
V
V
V
V
V
V
V
V
V
V
V
V
V
DD
DD
DD
DD
SS
SS
SS
DD
DD
DD
K
L
TT1
TT4
TT0 TBST
TT2 TS
V
V
V
V
A20 A22
A25 A24
A28 A27
A31 A30
A21
A23
A26
A29
A12
DD
D
D
V
V
V
V
V
SS
SS
DD
DD
DD
DD
M
TT
3
CPU CLK
BG
V
V
V
V
V
SS
SS
SS
DD
SS
SS
N
P
SRESET L2
TAG CLR
L2 UPDATE
V
SS
INH
TDI
TCK TMS
A10
A7
A11
R
T
TDO
TRST NC
A8
A5
A3
A9
A6
A4
CPU4
BG
V
V
V
V
V
V
V
V
V
CPU4
DBG
V
V
SS
SS
SS
DD
DD
DD
SS
SS
SS
DD
DD
U
V
W
CPU4 CFG0
BR
V
V
V
V
DH14 DH10 DL1 DL4
V
V
V
DP5
V
DD
DD
DD
SS
SS
SS
SS
DD
CFG2 CFG1 DH7
DH5 DH3 DH1 DP1 DH13 DH11 DL0 DL3 DL6 DP4 DL10 DL12 DL14 DL15 A1
A2
DP0 DH6 DH4 DH2 DH0 DH15 DH12 DH9 DH8 DL2 DL5 DL7 DL8 DL9 DL11 DL13 A0
TOP VIEW (X–RAY VIEW)
3/36
TSPC2605
2. SIGNAL DESCRIPTION
Pin Locations
Pin Name
Type
Description
19G, 17H – 19H, 17J – 19J, 17K –
19K, 17L – 19L,17M – 19M, 17N –
19N,17P – 19P, 17R – 19R,18T,
A0 – A31
I/O
Address inputs from processor. Can also be outputs for processor snoop
addresses. A0 is the MSB. A31 is the LSB.
19T, 18U, 19U,18V, 19V, 18W *
3G
AACK
ABB
I/O
I/O
Address acknowledge input/output.
2A
Used as an input to qualify bus grants. Driven as an output during address tenure
initiated by the TSPC2605.
AP0 – AP3
APE
I/O
O
Address parity.
17C – 19C, 17D
19B
*
Addressparityerror. Whenanaddressparityerrorisdetected, APEwillbedriven
low one clock cycle after the assertion of TS then High–Z following clock cycle.
18E
1G
APEN
I
I/O
I
Address parity enable. When tied low, enables address parity bits and the
address parity error bit.
ARTRY
Address retry status I/O. Generated when a read or write snoop to a dirty
processor cache line has occurred.
2U
2V
1V
17E
2B
CFG0
CFG1
CFG2
CFG3
CFG4
Configuration inputs. These must be tied to either V or V
.
SS
DD
CFG0
CFG1
CFG2
0
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
256KB
512KB; A26 = 0
512KB; A26 = 1
1MB; A25 – A26 = 00
1MB; A25 – A26 = 01
1MB; A25 – A26 = 10
1MB; A25 – A26 = 11
CFG3
Snoop Data Tenure Selector
0
1
Supports snoop data tenure
Does not support snoop data tenure
CFG4
AACK Driver Enable
0
1
Disable AACK driver
Enable AACK driver
2G
3M
2M
3E
CI
I/O
Cache inhibit I/O.
CLK
I
I
I
Clock input. This must be the same as the processor clock input.
CPU bus grant input.
CPU BG
CPU2 BG
TSPC2605 logically ORs this signal with CPU BG. Used in multiprocessor
configuration as the second CPU BG.
1B
1T
CPU3 BG
CPU4 BG
I
I
TSPC2605 logically ORs this signal with CPU BG. Used in multiprocessor
configuration as the third CPU BG.
TSPC2605 logically ORs this signal with CPU BG. Used in multiprocessor
configuration as the fourth CPU BG.
2H
2D
CPU BR
I
I
CPU bus request input.
CPU2 BR
TSPC2605 logically ORs this signal with CPU BR. Used in multiprocessor
configuration as the second CPU BR.
2C
1U
CPU3 BR
CPU4 BR
I
I
TSPC2605 logically ORs this signal with CPU BR. Used in multiprocessor
configuration as the third CPU BR.
TSPC2605 logically ORs this signal with CPU BR. Used in multiprocessor
configuration as the fourth CPU BR.
1F
3D
CPU DBG
I
I
CPU data bus grant input from arbiter.
CPU2 DBG
TSPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor
configuration as the second CPU DBG.
3C
CPU3 DBG
I
TSPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor
configuration as the third CPU DBG.
* See pin diagram (page 2) for specific pin assignment of these bus signals.
4/36
TSPC2605
Pin Locations
Pin Name
Type
Description
2T
CPU4 DBG
I
TSPC2605 logically ORs this signal with CPU DBG. Used in multiprocessor
configuration as the fourth CPU DBG.
11A – 13A, 15A – 18A,11B – 17B,
11C, 12C, 10U,11U, 10V – 12V,
DL0 – DL31
I/O
Data bus low input and output. DL0 is the MSB. DL31 is the LSB.
14V – 17V, 11W – 17W *
4A – 10A, 4B – 10B, 6C,10C, 8U,
DH0 – DH31
DBB
I/O
I/O
Data bus high input and output. DH0 is the MSB. DH31 is the LSB.
9U, 3V – 6V,8V, 9V, 3W –10W *
2J
Databus busy. Used as input when processor is master, driven as an output after
a qualified L2 DBG when TSPC2605 is the bus master. Note: To operate in Fast
L2 mode, this pin must be tied high.
14A, 18B, 5C, 8C,16U, 7V, 13V,
DP0 – DP7
FDN
I/O
I/O
Data bus parity input and output.
2W *
1C
FlushdoneI/OusedforcommunicationbetweenotherTSPC2605devices. Must
be tied together between all TSPC2605 parts along with a pullup resistor.
19E
1J
GBL
O
I
Global transaction. Always negated when MPC2604 is bus master.
HRESET
Hard reset input from processor bus. This is an asynchronous input that must be
low for at least 16 clock cycles to ensure the TSPC2605 is properly reset. For
proper initialization, TRST must be asserted before HRESET is asserted.
3A
1D
L2 BG
L2 BR
L2 CI
I
I/O
I
Bus grant input from arbiter.
Bus request I/O. Normally used as an output.
19D
Secondary cache inhibit sampled, after assertion of TS. Assertion prevents
linefill.
2F
L2 CLAIM
O
L2 cache claim output. Used to claim the bus for processor initiated memory
operationsthat hit the L2 cache. L2 CLAIM goes true (low) before the rising edge
of CLK following TS true. Because this output is not always driven, a pullup
resistor may be necessary to ensure proper system functioning.
2E
L2 DBG
I
Data bus grant input. Comes from system arbiter, used to start data tenure for
bus operations where TSPC2605 is the bus master.
18D
3B
L2 FLUSH
L2 MISS INH
L2 TAG CLR
I
I
I
I
Causes cache to write back dirty lines and clears all tag valid bits.
Prevents line fills on misses when asserted.
2N
3N
Invalidates all tags and holds cache in a reset condition.
L2 UPDATE
INH
Cache disable. When asserted, the TSPC2605 will not respond to signals on the
local bus and internal states do not change.
3J
PWRDN
I
Provides low power mode. Prevents address and data transitions into the RAM
array. TSPC2605 becomes active 4 µs after deassertion. Clock must be
externally disabled.
1N
1E
3K
SRESET
TA
I
Soft reset input from processor bus.
I/O
I/O
Transfer acknowledge status I/O from processor bus.
TBST
Transfer burst status I/O from processor bus. Used to distinguish between
burstable and non–burstable memory operations.
2P
1P
1R
1H
3P
TCK
TDI
I
I
Test clock input for IEEE 1149.1 boundary scan (JTAG).
Test data input for IEEE 1149.1 boundary scan (JTAG).
Test data output for IEEE 1149.1 boundary scan (JTAG).
Transfer error acknowledge status input from processor bus.
Test mode select for IEEE 1149.1 boundary scan (JTAG).
TDO
TEA
TMS
O
I
I
* See pin diagram (page 2) for specific pin assignment of these bus signals.
5/36
TSPC2605
Pin Locations
Pin Name
Type
Description
2R
TRST
I
Test reset input for IEEE 1149.1 boundary scan (JTAG). If JTAG will not be used,
TRST should be tied low.
3L
TS
I/O
Transfer start I/O from processor bus (can also come from any bus master on the
processor bus). Signals the start of either a processor or bus master cycle.
TSIZ0–TSIZ2
TT0–TT4
WT
I/O
I/O
I/O
Transfer size I/O from processor bus.
Transfer type I/O from processor bus.
17F – 19F *
1K, 2K, 1L, 2L, 1M *
3H
Write through status input from processor bus. When tied to ground, the
TSPC2605 will operate in write–through mode only (no copy–back).
4C, 15C, 16C, 9D – 11D,8H – 10H,
4J, 8J, 9J, 16J, 4K, 8K, 12K, 16K,
4L, 11L, 12L, 16L, 10M – 12M, 3T,
9T – 11T, 17T, 3U, 4U, 15U, 17U
V
DD
Supply Power supply: 3.3 V ± 5%.
7C, 9C, 13C, 14C, 7D, 8D,
12D, 13D, 4G, 16G – 18G,
4H, 11H, 12H, 16H, 10J – 12J, 9K
– 11K, 8L – 10L, 4M,
V
SS
Supply Ground.
8M, 9M, 16M, 4N, 16N, 7T, 8T,
12T, 13T, 5U – 7U, 12U – 14U
3F, 3R
NC
—
No connection: There is no connection to the chip.
* See pin diagram (page 2) for specific pin assignment of these bus signals.
3. SIMPLIFIED BLOCK DIAGRAM
COPY–BACK
BUFFER
CONTROL
RD/WR
DH0 –
DH31
DL0 –
DL31
DP0 –
DP7
60X BUS
INTERFACE
CONTROLLER
AND
BUS INTERFACE
A27,
A28
8K x 72 x 4
DATA RAM
A0 –
A31
WAY SELECT
RD/WR
2K x 18 x 4
TAG RAM
COMPARE
2K x 8 LRU
6/36
TSPC2605
B. DETAILED SPECIFICATIONS
1. SCOPE
This drawing describes the specific requirements for the microprocessor TSPC2605, in compliance with MIL-STD-883 class B or
TCS standard screening.
2. APPLICABLE DOCUMENTS
1) MIL-STD-883 : Test methods and procedures for electronics.
2) MIL-PRF-38535 appendix A : General specifications for microcircuits.
3. REQUIREMENTS
3.1. General
The microcircuits are in accordance with the applicable documents and as specified herein.
3.2. Design and construction
3.2.1.Terminal connections
Depending on the package, the terminal connections shall be is shown in § A.1 PIN ASSIGNMENT.
3.2.2.Lead material and finish
Lead material and finish shall be as specified in MIL-STD-1835 (see enclosed § 8)
3.2.3.Hermetic Package
The macrocircuits are packaged in 241 pin ceramic and plastic ball grid array packages (see § 8.1 and 8.2)
The precise case outlines are described at the end of the specification (§ 8.1 and 8.2) and into MIL-STD-1835.
3.3. Absolute maximum ratings
This device contains circuitry to protect the
Rating
Power Supply Voltage
Voltage Relative to V
Symbol
Value
Unit
V
inputs against damage due to high static volt-
ages or electric fields; however, it is advised
that normal precautions be taken to avoid
application of any voltage higher than maxi-
mum rated voltages to this high–impedance
circuit.
This BiCMOS memory circuit has been
designed to meet the dc and ac specifications
shown in the tables, after thermal equilibrium
has been established.
V
DD
– 0.5 to + 4.6
V , V
in out
– 0.5 to V + 0.5
V
SS
DD
Output Current (per I/O)
Power Dissipation (Note 2)
Temperature Under Bias
Operating Temperature
Storage Temperature
NOTES:
I
± 20
mA
W
out
P
D
—
T
bias
– 10 to + 85
–55 to +125
– 55 to +125
°C
°C
°C
T
c
T
stg
1. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are
exceeded. Functional operation should be restricted to RECOMMEND
OPERATING CONDITIONS. Exposure to higher than recommended voltages for
extended periods of time could affect device reliability.
2. Power dissipation capability is dependent upon package characteristics and use envi-
ronment. See Package Thermal Characteristics.
7/36
TSPC2605
3.4. Thermal Characteristics
3.4.1.PBGA Package
Rating
Symbol
Max
26.5
23.2
15.9
6.6
Unit
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to Ambient (Still Air, Test Board with Two Internal Planes)
Thermal Resistance Junction to Ambient (200 lfpm, Test Board with Two Internal Planes)
Thermal Resistance Junction to Board (Bottom)
R
R
R
θ
θ
θ
θ
JA
JA
JB
JC
Thermal Resistance Junction to Case (Top)
R
3.4.2.CBGA Package
Rating
Symbol
Max
TBD
TBD
TBD
TBD
Unit
°C/W
°C/W
°C/W
°C/W
Thermal Resistance Junction to Ambient (Still Air, Test Board with Two Internal Planes)
Thermal Resistance Junction to Ambient (200 lfpm, Test Board with Two Internal Planes)
Thermal Resistance Junction to Board (Bottom)
R
R
R
θ
θ
θ
θ
JA
JA
JB
JC
Thermal Resistance Junction to Case (Top)
R
3.5. Marking
The document where are defined the marking are identified in the related reference documents. Each microcircuit are legible and
permanently marked with the following information as minimum :
- Thomson logo,
- Manufacturer’s part number,
- Class B identification if applicable,
- Date-code of inspection lot,
- ESD identifier if available,
- Country of manufacturing.
8/36
TSPC2605
4. ELECTRICAL CHARACTERISTICS
4.1. Recommanded Operating Conditions
Parameter
Supply Voltage (Operating Voltage Range)
Input High Voltage
Symbol
Min
3.135
2.0
Typ
3.3
—
Max
3.465
5.5
Unit
V
V
DD
V
IH
V
Input Low Voltage
V
IL
– 0.5*
—
0.8
V
* V (min) = – 2.0 V ac (pulse width ≤ 20 ns).
IL
4.2. DC Characteristics
Parameter
Input Leakage Current (All Inputs, V = 0 to V
Symbol
Min
—
Max
± 1.0
± 1.0
720
Unit
µA
)
I
lkg(I)
in
DD
Output Leakage Current (High–Z State, V = 0 to V
)
I
lkg(O)
—
µA
out
DD
AC Supply Current (I = 0 mA, All inputs = V or V , V = 0 V, and V ≥ 3.0 V,
I
CCA
—
mA
out
IL
IH
IL
IH
Cycle Time = 15 ns, max value assumes a constant burst read hit, with 100% bus utilization,
and 100% hit rate)
AC Quiescent Current (I = 0 mA, All inputs = V or V , V = 0 V and V ≥ 3.0 V,
I
Q
—
195
mA
out
IL
IH
IL
IH
Cycle Time = 15 ns, All Other Inputs DC)
Output Low Voltage (I = + 8.0 mA)
V
—
0.4
—
V
V
OL
OL
Output High Voltage (I = – 4.0 mA)
V
OH
2.4
OH
4.3. Capacitance
Parameter
Symbol
Typ
4
Max
6
Unit
pF
Input Capacitance
C
in
Output Capacitance
Input/Output Capacitance
C
out
C
I/O
6
8
pF
8
10
pF
* f = 1.0 MHz, dV = 3.0 V, T = 25°C, Periodically Sampled Rather Than 100% Tested
A
9/36
TSPC2605
4.4. AC Operating Conditions and Characteristics (T = –55 to +125°C, Unless Otherwise Noted)
C
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 ns
Output Measurement Timing Level . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . 50 Ω Termination to 1.5 V
4.4.1.AC Clock Specification
TSPC2605–66
Timing
Reference
Parameter
Frequency of Operation
Unit
MHz
ns
Notes
Min
Max
66.67
—
—
Clock Cycle Time
ꢀ
15
1.0
40
—
Clock Rise and Fall Time
ꢁ,
ꢂ
2.0
ns
1, 2
1
Clock Duty Cycle Measured at 1.5 V
Clock Short–Term Jitter (Cycle to Cycle)
60
%
± 150
ps
NOTES:
1. This parameter is sampled and not 100% tested.
2. Rise and fall times for the clock input are measured from 0.4 to 2.4 V.
CLOCK INPUT TIMING DIAGRAM
ꢀ
ꢁ
ꢂ
V
I
I
V
M
H
V
L
VM = Midpoint Voltage (1.5 V)
4.4.2.AC Specifications
TSPC2605–66
Timing
Reference
Parameter
Unit
Notes
Min
Max
—
—
—
9
Clock Cycle Time
ꢀ
ꢁ
ꢂ
ꢃ
ꢄ
ꢅ
ꢆ
15
4.5
2
ns
ns
ns
ns
ns
ns
ns
µs
Input Setup Time
1
1
2
Clock to Input Invalid (Input Hold)
Clock to Output Driven
Clock to Output Valid
Clock to Output Invalid
Clock to Output High–Z
PWRDN Disable to Recovery
NOTES:
2
2
9
2
—
12
4
2
2
2
2
—
1. All input specifications are measured from the TTL level (0.8 or 2.0 V) of the signal in question to the 1.4 V level of the rising edge of the input
clock. Both input and output timings are measured at the pin.
2. This parameter is sampled and not 100% tested.
CLK
INPUTS
ꢂ
ꢁ
OUTPUTS
ꢃ
ꢄ
ꢅ
ꢆ
ꢀ
10/36
TSPC2605
4.4.3.TSPC2605 Response to 60X Transfer Attributes
TT0 – TT4
X1X10
TBST
CI
1
WT
X
Tag Status
Miss
TSPC2605 Response
Line–fill (processor read miss)
Notes
1, 2, 3
4
0
0
1
X1X10
1
X
Hit
L2 CLAIM, AACK, TA (processor read hit)
X1010
0
X
Hit Clean
Paradox — Invalidate the line (processor n–cacheable read hit
clean line)
X1010
00110
00110
1
0
0
0
1
1
X
X
1
Hit Dirty
Miss
Paradox — ARTRY, L2 BR, then write back data, invalidate the line
(processor n–cacheable read hit dirty line)
Line–fill except right after a snoop hit to processor (processor write 1, 3, 5, 6
miss)
Hit
L2 CLAIM, AACK, TA except after a snoop hit to processor
(processor write hit)
5, 6
00X10
00110
00010
X
0
1
1
1
1
0
0
0
Hit Clean
Hit Dirty
Hit Dirty
Cache update (processor write through WT hit clean)
Cache update, clear dirty bit
Paradox — ARTRY, L2 BR, write back data, keep valid, clear dirty
bit
X0010
X0010
1
1
0
0
X
X
Hit Clean
Hit Dirty
Paradox — Invalidate the line (processor n–cacheable write hit
clean line)
Paradox — ARTRY, L2 BR, then write back data, invalidate the line
(processor n–cacheable SB write hit dirty line)
00100
00100
X
X
X
X
X
X
Hit Clean
Hit Dirty
Invalidate tag (flush block address–only)
ARTRY, L2 BR, write back data, invalidate tag (flush block
address–only)
00000
00000
X
X
X
X
X
X
Hit Clean
Hit Dirty
No action (clean block address–only)
ARTRY, L2 BR, write back data, reset dirty bit (clean block
address–only)
01100
X
X
X
Hit
Invalidate tag (kill block address–only)
NOTES:
1. If a line fill is going to replace a dirty line and the cast out buffer (COB) is full, the line fill will be cancelled. (Unless the line fill is a write which
hits in the COB. In this case, the line fill will occur.)
2. If a burst read misses the cache but hits the COB, the TSPC2605 will supply the data from the COB, but not perform a line fill.
3. If ARTRY is asserted during a line fill to replace a dirty line, the line fill will be cancelled, the to–be–replaced line will recover its old tag (valid,
dirty, tag field), and the COB goes back to an invalid condition, even if the line fill is a burst write to the line in the COB.
4. If ARTRY is asserted during a read hit, the TSPC2605 will abort the process.
5. If a processor burst write occurs right after a snoop write that was a cache hit, the TSPC2605 will invalidate the line. If the snoop was a cache
miss, the TSPC2605 will not perform a write allocate.
6. If a processor burst write occurs right after a snoop read that was a cache hit, the TSPC2605 will update the cache and clear the dirty bit. If
the snoop was a cache miss, the TSPC2605 will perform a write allocate.
4.4.4.TSPC2605 Response to Chipset Transfer Attributes
TT0 – TT4
Tag Status
TSPC2605 Response
00100
X0010
X1110
Hit Clean
Invalidate line
00100
X0010
X1110
Hit Dirty
ARTRY and L2 BR write back data, invalidate line (see Note)
00000
X1010
Hit Clean
Hit Dirty
Hit
No action
00000
X1010
ARTRY and L2 BR, write back data, reset dirty bit (see Note)
Invalidate (kill block)
0110X
00110
NOTE: In all snoop push cases, BR is sampled the cycle after the ARTRY window. If BR is asserted in this cycle, L2 BR will be immediately negated
and an assertion of L2 BG will be ignored.
4.4.5.Transfer Attributes Generated for L2 Copy–Back
TT0 – TT4
TBST
CI
WT
00010
0
1
1
11/36
TSPC2605
4.5. JTAG AC Operating Conditions and Characteristics for the Test Access Port (IEEE 1149.1)
Input Timing Measurement Reference Level . . . . . . . . . . . . . . . 1.5 V
Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 3.0 V
Input Rise/Fall Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 ns
Output Measurement Timing Level . . . . . . . . . . . . . . . . . . . . . . . 1.5 V
Output Load . . . . . . . . . . . . . . . . . . . . . . . . 50 Ω Termination to 1.5 V
4.5.1.TAP Controller Timing
TSPC2605–66
Parameter
Symbol
Unit
ns
Notes
Min
30
12
12
5
Max
—
—
—
9
Cycle Time
t
CK
Clock High Time
t
ns
1
1
CKH
Clock Low Time
t
ns
CKL
Clock Low to Output Valid
Clock Low to Output High–Z
Clock Low to Output Active
Setup Times:
t
A
ns
t
0
9
ns
2
3, 4
1
CKZ
CKX
t
0
9
ns
TMS
TDI
t
s
2
—
ns
t
sd
Hold Times:
TMS
TDI
t
2
—
ns
1
h
t
hd
NOTES:
1. This parameter is sampled and not 100% tested.
2. TDO will High–Z from a clock low edge depending on the current state of the TAP state machine.
3. TDO is active only in the SHIFT–IR and SHIFT–DR state of the TAP state machine.
4. Transition is measured ± 500 mV from steady–state voltage. This parameter is sampled and not 100% tested.
t
CK
H
t
t
CK
CK
L
TCK
TEST
CLOCK
t
H
t
S
TMS TEST
MODE
SELECT
t
HD
t
SD
TDI
TEST
DATA
IN
t
t
CKX
t
CKZ
A
TDO
TEST
DATA
OUT
Figure 1. TAP Controller Timing
12/36
TSPC2605
5. FUNCTIONAL DESCRIPTION
5.1. System Usage and Requirements
The TSPC2605 is a high–performance look–aside cache for PowerPC systems. A look–aside cache is defined as a cache that
resides on the same bus as the processor, the memory controller, the DMA bridge, and the arbiter. The advantage of a look–aside
cache is that, when the processor makes a memory request, the cache adds no delay to the memory controller’s response time in the
event that the request cannot be satisfied by the cache. However, there are certain system requirements that must be met before a
look–aside cache can be used.
5.1.1.Comprehension of L2 CLAIM
Becausethememorycontrollerseeseverymemoryrequestthatisissuedbytheprocessor, theremustbeamechanismforthecache
to inform the memory controller that it has detected a cache hit and that it will satisfy the processor’s request. The TSPC2605 has a
signal calledL2 CLAIM that is asserted whenever a cache hit is detected. Any memory controller with which the TSPC2605 is to be
used must have the ability to monitor this signal.
5.1.2.Pipeline Depth
The 60X bus allows pipelining of transactions such that a new transaction can be initiated before a previous transaction has fully
completed. The level of pipelining that exists on the bus is defined by how many new data transactions have been initiated while the
original transaction is still being processed. By this definition the TSPC2605 can only work in a one level deep pipeline. In the pres-
ence of transactions for which it has asserted L2 CLAIM, the TSPC2605 can control the level of pipelining by delaying its assertion of
AACK. However, for transactions that it cannot control, the TSPC2605 is dependent upon the memory controller to control pipeline
depth. Thus, another system requirement for the use of the TSPC2605 is the use of a memory controller that only allows one level
deep of pipelining on the 60X bus.
5.1.3.Bus mastering
Bus mastering is a requirement only for systems which seek to use the TSPC2605 as a copyback, as opposed to a write–through,
cache. The requirement is that the system arbiter must have the ability to allow the TSPC2605 to become a bus master. Specifically,
the system arbiter must be able to recognize assertions of L2 BR and must have the ability to assert L2 BG and L2 DBG.
These are the only requirements above and beyond what should already exist in a PowerPC system. All other necessary control
signals are signals that are required for the processor to communicate with the memory controller, the DMA bridge, and the arbiter.
5.2. Configuration pins
The TSPC2605 has five configuration pins: CFG0, CFG1, CFG2, CFG3, and CFG4.
5.2.1.CFG0 – CFG2
These three configuration pins are used to implement the different cache sizes supported by the TSPC2605.
256KB:
512KB:
For a single chip implementation, CFG0, CFG1, and CFG2 should all be tied low.
This two chip configuration requires both parts to have CFG0 tied low and CFG1 tied high. CFG2 is used as a chip
select when it matches the value of A26. Therefore, one device must have CFG2 tied low and the other device must
have CFG2 tied high.
1MB:
The four chip configuration requires all four devices to have CFG0 tied high. The CFG1, CFG2 vector becomes the
chip select when it matches the A25, A26 vector. Therefore, each of the four parts must have a unique value of the
CFG[1:2] vector.
5.2.2.CFG3
Many core logic chipsets are designed such that the DMA bridge and the memory controller are resident in the same device. In such
systems there is internal communication between these two functional units. Bus transactions generated by the DMA bridge are
solely for the purpose of keeping the system coherent. They are not explicit requests from memory that have data tenures associated
with them. However, some chipsets are designed with the memory controller and the DMA bridge partitioned into different devices. In
systems such as these, transactions generated by the DMA bridge are true memory requests that have data tenures associated with
them. These are called snoop data tenures. Because these two types of systems are fundamentally different, the TSPC2605 must
know in which type of system it is resident in order to respond properly to the different types of transactions. For systems that do not
have snoop data tenures, CFG3 must be tied high. For systems that do use snoop data tenures, CFG3 must be tied low.
13/36
TSPC2605
5.2.3.CFG4
When the TSPC2605 asserts L2 CLAIMto signal to the memory controller that a cache hit has been detected, it is taking control of the
address and data tenures of the transaction (see 60X Bus Operation and MemoryCoherence). This means that the TSPC2605 will
assert AACK to end the address tenure, and it will assert TA as needed for the data tenure. If the data bus is idle when a processor
request is initiated, the TSPC2605 will assert AACKthe cycle after TS was asserted. If the data bus is busy when the request is made,
the TSPC2605 will wait until the outstanding data tenure has completed before asserting AACK. By holding off on the assertion of
AACK, the TSPC2605 enforces the policy of, at most, two outstanding data transactions at any one time. Tying CFG4 low prevents
the TSPC2605 from asserting AACK to end transactions for which it has asserted L2 CLAIM. In systems that tie CFG4 low it is neces-
sary for the memory controller to assert AACK for all transactions. This allows the DMA bridge to initiate snoop transactions (as
defined later) even when there are two outstanding data transactions. If this type of system is implemented, the arbiter must ensure
that the processor’s bus grant is negated once there are two outstanding data transactions. It is expected that most systems will tie
CFG4 high.
5.3. Reset/Initialization
To ensure proper initialization and system functionality, the HRESET pin of the TSPC2605 should be connected to the same signal
that is used to reset the processor. The TRST signal must be negated before HRESET is negated. When HRESET is negated, the
TSPC2605 commences an internal initialization sequence to clear all of the valid bits in the cache. The sequence takes approxi-
mately 4000 clock cycles. During this time the TSPC2605 will not participate in any bus transaction that occurs. All transactions are,
however, monitored so that, regardless of when the initialization sequence completes, the TSPC2605 is prepared to take action on
the next transaction initiated by the processor.
At some point after this 4000 cycle sequence, the TSPC2605 will detect its first cache hit. At this time the system will experience its
first assertion of L2 CLAIM. If the memory controller must be configured via software to comprehend assertions of L2 CLAIM, this
configurationoperation must have completed by this time. For systems that cannot guarantee that this requirement is met, it isneces-
sarytodisabletheTSPC2605untilsuchtimeasthisconfigurationcanbeguaranteed. DisablingtheTSPC2605canbeaccomplished
by asserting L2 UPDATE INH sometime during reset and negating it when it is deemed safe for caching to commence.
5.4. 60X bus operation
All transactions have what is called an address tenure. An address tenure is a set number of bus cycles during which the address bus
and its associated control signals are being used for the transaction at hand. In general, there are two types of transactions. Those
that only have address tenures, called address–only transactions. And those that require the use of the data bus and therefore will
have a data tenure. These transactions are called data transactions. This section describes how address and data tenures are
defined as viewed by the TSPC2605.
5.4.1.Address Tenures
Addresstenuresonthe60Xbusarefairlywelldefined. TheystartwithanassertionofTSbyadevicethathasbeengrantedthebusby
the system arbiter. This device is called the bus master for this transaction. At the same time that TS is asserted, the bus master also
drives the address and all other relevant control signals that define the transaction. TS is only asserted for one cycle but all other
signals are held valid by the bus master until some other device asserts AACK. The device that asserts AACK becomes the slave to
this transaction. Typically, the slave is the memory controller, although for transactions that are cache hits the TSPC2605 becomes
the slave by driving L2 CLAIM.
Transactions can be aborted by any device on the bus by asserting ARTRY. ARTRY may be asserted at any time after TS is asserted,
but must be held through the cycle after AACK is asserted. This cycle is referred to as the ARTRY window, since it is the cycle in which
all devices sample ARTRY to determine if the address tenure has completed successfully.
If an address tenure is not aborted by an assertion of ARTRY, then the next bus master is free to assert TS, the cycle after the ARTRY
window to start a new address tenure. If ARTRY is asserted in the ARTRY window, all devices that are not asserting ARTRY must
negate their bus request in the following cycle. This next cycle is called the BR window. The purpose of this protocol is to give immedi-
ate bus mastership to the device that asserted ARTRY with the expectation that that device will take this opportunity to clean up
whatever circumstances caused it to assert ARTRY. Typically, this involves writing data back to memory to maintain coherence in the
system.
14/36
TSPC2605
5.4.2.Data Tenures
Data tenures are more complicated to define than address tenures. They require two conditions to start: an assertion of TS that initi-
atesadatatransactionandaqualifiedassertionofthebusmaster’sdatabusgrant. Foradatabusgranttobeconsideredqualified, no
device on the bus may be asserting DBB in the cycle that the data bus grant is asserted.
Data transactions come in two types: single–beat transactions and burst transactions. The type is determined by the state of TBST
duringthe address tenure of the transaction. If the bus master asserts TBST, thetransactionisabursttransactionandwillrequirefour
assertions of TA in order to complete normally. If TBSTis negated during the address tenure, the transaction only requires one asser-
tion of TA, thus the name single–beat.
Which device drives the data bus during a data transaction depends upon whether the transaction is a read or a write. For a read
transaction, the slave device drives the data bus. For a write transaction, the master drives the data bus. In all data transactions, the
slave device asserts TA toindicatethateithervaliddataispresentonthebus, inthecaseofaread;orthatitisreadingdataoffthedata
bus, in the case of a write. The master device asserts DBB the cycle after it has been granted the data bus and keeps it asserted until
the data tenure has completed.
A data tenure can be aborted in two different ways. The address tenure for the transaction can be aborted by an assertion of ARTRY.
Or, the slave device may assert TEA to indicate that some error condition has been detected. Either event will prematurely terminate
the data tenure.
5.4.3.Data Streaming
For the majority of data transactions there must be a wait state between the completion of one data tenure and the start of the next.
This turnaround cycle avoids the contention on the data bus that would occur if one device starts driving data before another device
has had a chance to turn off its data bus drivers. When a cache read hit is pipelined on top of another cache read hit, there is no need
forthisturnaroundcyclesincethesamedevicewillbedrivingthedatabusforbothdatatenures. The60Xbushastheabilitytoremove
this unnecessary wait state and allow back–to–back cache read hits to stream together. This ability is only enabled if the system is put
into Fast L2 mode. Note that not all PowerPC processors support Fast L2 mode.
Oneoftherequirementsfortakingadvantageofthisdatastreamingcapabilityisthatthesystemarbitermustbesophisticatedenough
toidentifysituationsinwhichstreamingmayoccur. Uponrecognizingthesesituations, itmustasserttheprocessor’sdatabusgrantin
the cycle coincident with the fourth assertion of TA of the first cache read, so that the data tenure for the second cache read may
commence in the next cycle.
Because it only recognizes qualified assertions of CPU DBG, the TSPC2605 must not be aware of the processor’s assertions of
DBB. This means that the DBB pin of the TSPC2605 must be tied to a pullup resistor rather than connected to the system DBB to
which all other devices are connected. This forces the system arbiter to a level of sophistication such that it only supplies qualified
data bus grants and thus the DBB signal is unnecessary to the whole system.
Note: In a multi–chip configuration each TSPC2605 device acts as an independent cache. Zero wait state data streaming can only
occur if the back to back read hits occur in a given device. If the second read hit is not in the device as the first read hit, a wait state will
occur between the two data tenures (2–1–1–1–2–1–1–1 timing).
5.4.4.Data Bus Parking
TheTSPC2605hastheabilitytorespondtoaprocessorreadorwritehitstartinginthecycleaftertheprocessorhasassertedTS. This
is referred to as a 2–1–1–1 response. However, even though the TSPC2605 has this ability, it is dependent upon the system to allow
thisquickofaresponsetooccur. Asdiscussedabove, adatatenurecannotstartuntilthemasterhasbeengivenaqualifiedbusgrant.
In order for the data tenure to start the cycle after TS is asserted, the data bus must be granted in the cycle coincident with the asser-
tion of TS. At bus speeds of 66 MHz it is extremely difficult for an arbiter to detect an assertion of TS and itself assert CPU DBG in the
same cycle. In order to realistically allow this situation to occur, CPU DBGmust be asserted independent of the processor’s assertion
of TS.
Databusparkingisasystemfeaturewherebytheprocessoralwayshasaqualifieddatabusgrantwhenthedatabusisidle. Itisalsoa
requirement for systems which seek to take advantage of the 2–1–1–1 response time capabilities of the TSPC2605. This feature is
typicallypresentinarbitersthathavethelevelofsophisticationnecessarytosupportdatastreaming. Butitisalsoafeatureofsystems
that do not even have a data bus arbiter. In these systems the data bus grant of every device in the system is tied to ground. The
assertionofDBBbythecurrentdatabusmastereffectivelyremovesthequalifieddatabusgrantofalldevicesinthesystem, including
its own. Note that in systems that have no data bus arbiter that it is impossible to take advantage of data streaming.
There is another caveat associated with data bus parking. Care must be taken when using data bus parking along with Fast L2 mode.
In normal bus mode when the processor reads data off the bus, it will wait one cycle before passing the data on to internal functional
units. The purpose of this one cycle waiting period is to check for an assertion of DRTRY, which invalidates the data that has been
already read. One of the advantages of running the processor in Fast L2 mode is that this internal processor wait state is removed.
A problem will arise, however, if the processor is given data the cycle after TS is asserted, as is possible with the TSPC2605, and the
transaction is aborted by some other device asserting ARTRY. Because the processor will not sample ARTRY until two cycles after
the assertion of TS, the data read off the bus will have already been forwarded to theinternal functional units. Thus, incorrect results
may occur in the system.
ToavoidthissituationinasystemthatseekstorunFastL2modewiththedatabusparked, theremustbeaguaranteethatARTRY will
never be asserted for cache read hits. This is a further requirement to be imposed upon the DMA bridge and the memory controller. If
this guarantee cannot be made, the data bus cannot be parked when running in Fast L2 mode.
15/36
TSPC2605
5.4.5.Processor Reads
When the processor issues a read transaction, the TSPC2605 does a tag lookup to determine if this data is inthe cache. If there is a
cachehitandCIisnotasserted, theTSPC2605willassertL2CLAIM andsupplythedatatotheprocessorwhenthedatatenurestarts.
If the processor issues a cache–inhibited read (CI asserted) and the TSPC2605 detects a cache hit to a non–dirty, or clean, cache
line, thelinewillbemarkedinvalid. Ifthecache–inhibitedreadhitsadirtyline, theTSPC2605willassertARTRYandwritethedirtyline
back to memory.
Ifthereadmissesinthecache, theTSPC2605willperformalinefillonlyifitisaburstreadanditisnotmarkedcache–inhibited. During
a linefill, the TSPC2605 stores the data present on the bus as it is supplied by the memory controller.
5.4.6.Processor Writes
The conditions for asserting L2 CLAIM for processor writes are almost the same as for processor reads. There must be a cache hit
and CI must not be asserted. In addition, however, WT must not be asserted. Single beat writes that are marked either write–through
or cache–inhibited that hit in the cache cause the TSPC2605 to assert ARTRY and write the dirty line back to memory.
5.4.7.Transaction Pipelining
As explained in Pipeline Depth, the TSPC2605 can only handle one level of pipelining on the bus. Since the assertion of L2 CLAIM
gives it the ability to assert AACK, the TSPC2605 has the ability to control this pipeline depth for transactions that are cache hits by
delaying its assertion of AACK.
Pipelined cache hits are transactions that hit in the cache but occur while there is still an outstanding data transaction on the bus. The
timing of the assertion of AACK for a pipelined cache hit is dependent upon the completion of the previous transaction. For explana-
tion purposes, the previous transaction will be referred to as transaction one. The pipelined cache hit will be referred to as transaction
two.
If transaction one is a cache hit, the TSPC2605 will be the slave device for the transaction. Since, for burst operations, theTSPC2605
always asserts TA for four consecutive clock cycles, the end of the data tenure for transaction one will be at a deterministic clock
cycle. In this case, AACKfor transaction two can be asserted coincident with the last assertion of TAfor transaction one. Iftransaction
one is not a cache hit, the TSPC2605 will wait until after the data tenure for transaction one has completed before asserting AACK to
complete the address tenure of transaction two.
5.5. Memory coherence
When a processor brings data into its on–chip cache and modifies it, a situation has arisen in which the main memory now contains
irrelevant, or stale, data. Given that most systems support some form of DMA there must exist a means by which the processor is
forced to write this modified, or dirty, data back to main memory. The DMA bridge is responsible for generating bus transactions to
ensure that main memory locations accessed by DMA operations do not contain stale data. These transactions, called snoops, come
in three different categories, each of which will be discussed below.
Snoops cause the processor and the TSPC2605 to check to see if they have dirty copies of the memory location specified in the
snoop transaction. If either device does have a dirty copy it will assert ARTRY and make use of the opportunity presented in the BR
window to write this data back to main memory.
Situations can arise where a cache line is dirty in both the processor’s L1 cache and in the TSPC2605. In cases such as these, snoop
transactions should cause the processor to write its data back to memory since it is by definition more recent than the data in the
TSPC2605. Since ARTRY is a shared signal and it cannot be determined which devices are driving it, the TSPC2605 samples CPU
BR in the BR window to determine if the snoop hit a dirty line in the L1 cache. If CPU BRisassertedduringthiswindow, theTSPC2605
will defer to the processor.
5.5.1.Snoop Reads
A snoop read causes dirty data to be written back to memory but allows both the L1 and L2 to keep a valid copy. In cases where the
snoop hits a dirty cache line in the processor, the TSPC2605 will update its contents as the processor writes the data back to main
memory.
Snoop reads can be implemented in two ways. One is that the DMA bridge can issue a clean transaction (TT[0:4] = 00000). The other
is that the DMA bridge can do a read transaction (TT[0:4] = x1010). If the DMA bridge does a read transaction, the TSPC2605 deter-
mines that it is a snoop read rather than a processor read by the state of CPU BG the cycle before TS was asserted. If the processor
was not granted the bus then the transaction had to have been issued by the DMA bridge and is therefore a snoop read.
5.5.2.Snoop Writes
Snoop writes also cause dirty data to be written back to main memory. The difference from a snoop read is that the cache line must
thenbe invalidated in both the processor’s cache and in the L2 cache. When the processor writes data back to memory in responseto
a snoop write, the TSPC2605 will not cache the data as it appears on the bus. If a valid copy resides in the cache, the TSPC2605 will
invalidate it.
Again there are multiple transactions that can be used by the DMA bridge to implement a snoop write. It can issue a flush transaction
(TT[0:4] = 00100), a read with intent to modify (TT[0:4] = x1110), or a write with flush (TT[0:4] = 00010). As with snoop reads, the
TSPC2605 distinguishes between processor issued data transactions and snoop transactions by the state of CPU BG in the cycle
previous to the assertion of TS.
16/36
TSPC2605
5.5.3.Snoop Kills
Kills are snoops that cause cache entries to be immediately invalidated, regardless of whether they are dirty. This saves time if the
DMA operation is going to modify all the data in the cache line. To implement a snoop kill the DMA bridge can issue a kill transaction
(TT[0:4] = 01100) or a write with kill (TT[0:4] = 00110).
5.6. Two/Four Chip Implementation
5.6.1.Multiple Castouts
Because each TSPC2605 has its own castout buffer (COB), it is possible for situations to arise in which more than one device needs
to do a copyback operation. Under normal circumstances each device will enter castout conditions at different times. In these cases,
when a device determines that it needs to do a castout, the L2 BR signal is first sampled. If L2 BR is already asserted then it is clear
that another device is also in a castout situation. The late device will wait until L2 BR is negated before continuing in its attempt to
perform its castout.
Because of the BR window protocol associated with assertions of ARTRY, it is possible for a situation to arise where device two is
waiting for device one to do its castout before asserting L2 BR. If there is an assertion of ARTRY by a device other than device one,
device one is required to negate L2 BR in the BR window. In order to prevent device two from interpreting device one’s negation of L2
BR as an indication that device one has completed its castout, a simple arbitration mechanism is used. All devices have a simple
two–bit counter that is synchronized such that all counters always have the same value. For the purposes of performing a castout
operation, a given pair can only assert L2 BR if the counter is equal to its value of CFG[1:2]. This simple mechanism prevents more
than one device from asserting L2 BR in the same cycle and therefore not being cognizant of the another device’s need to perform a
castout.
5.6.2.Snoop Hit Before Castout
The other situation that can cause problems with a shared bus request occurs when a snoop hits a dirty line in one of the TSPC2605
devices. If device one has a cache line in its COB, it will assert L2 BR so that it may perform a castout operation. If a snoop hits a dirty
line in device two, it will assert both ARTRY and L2 BR so that it can write the snoop data back to main memory. When device one
detects that ARTRY has been asserted, it needs to be made aware that device two needs to request the bus. Otherwise, at the same
time that device two is asserting L2 BR, device one will attempt to conform to the BR window protocol and negate L2 BR. This situa-
tion is avoided by device one sampling FDN when it detects that ARTRY has been asserted. If FDN is asserted at the same time as
ARTRY is asserted, device one will recognize that device two is asserting ARTRY. device one will then high–Z L2 BR so that there will
not be contention when device two is asserting L2 BR.
5.7. Multiprocessing
The TSPC2605 can be used as a common cache for up to four processors. For each processor there is a bus request, bus grant, and
data bus grant signal pin on the TSPC2605. Each of these pins needs to be connected to the respective processor’s arbitration sig-
nals in the system.
The TSPC2605 treats multiple processors as one processor. Thus, the same restrictions on pipelining depth are true with regard to
how many processor transactions can be outstanding at any one time. There can only be one data transaction from ANY processor
pipelined on top of a current data transaction that was issued by ANY processor.
Thedatatenuresforallprocessorsmustbeperformedinthesameorderastheaddresstenuresonasystem–widebasis. Ifprocessor
one makes a request and then processor two makes a request, processor one’s data tenure must precede processor two’s data
tenure. Note that this is not a 60X bus restriction, but rather a restriction necessary for proper operation of the TSPC2605.
The TSPC2605 keeps coherent with the L1 caches of multiple processors as defined by the MESI (modified–exclusive–shared–in-
valid) protocol without actually implementing the protocol. This is possible for two reasons. Since the TSPC2605 is a look–aside
cache, all transactions are monitored by all devices on the bus. Also, the TSPC2605 cannot, on its own, modify data. Thus, if one
processor requests exclusive access to a cache line, it is not necessary for the TSPC2605 to invalidate its copy of the data, as would
be required under the MESI protocol. If a second processor requests the same data, the transaction will cause the first processor to
assert ARTRY. This will prevent the TSPC2605 from supplying stale data to the second processor.
As discussed in Data Bus Parking, care must be taken when parking the data bus in Fast L2 mode. By the nature of MP systems
running under the MESI protocol there will be assertions of ARTRY to abort cache read hits. Thus, in an MP system, the data bus
cannot be parked to any processor if the system is to be run in Fast L2 mode.
5.8. Powering–Down
An assertion of PWRDN will cause the TSPC2605 to go into a low–power sleep state. This state is entered after PWRDN is synchro-
nized and both the address and data buses are idle. All data is retained while in the sleep state.
The behavior of the TSPC2605 upon negation of PWRDN is dependent upon the state of WT at the rising edge of HRESET. If WT is
asserted at reset, the TSPC2605 will invalidate all cache entries when PWRDN is negated. If WT is negated at reset, the TSPC2605
will leave all cache entries as they were prior to the assertion of PWRDN. However, in this situation, the system designer must insure
that no bus activity occur within two microseconds of the negation of PWRDN.
Note: While in the sleep state the TSPC2605 does not disable its internal clock network. The low power state current stated in this
specification assumes that the system clock is not toggling.
17/36
TSPC2605
5.9. Asynchronous signals
The TSPC2605 supports four asynchronous control signals. These signals were originally defined in the PowerPC reference plat-
form (PReP) specification. Because these signals are defined to be asynchronous, the TSPC2605 must synchronize them internally.
This process takes eight clock cycles. Thus, to guarantee recognition by the TSPC2605, assertions of any one of these signals must
last a minimum of eight clock cycles.
5.9.1.L2 FLUSH
When L2 FLUSH is asserted, the TSPC2605 initiates an internal sequence that steps through every cache line present. Valid lines
that are clean are immediately marked invalid. Valid lines that are dirty must be written back to main memory.
To keep memory up to date, the TSPC2605 must still monitor all transactions on the bus. Any transaction that is not a processorburst
write will cause the TSPC2605 to assert ARTRY. Burst writes cause the TSPC2605 to do a lookup on the affected address and mark
the line invalid if it is present.
Because the TSPC2605 must still monitor all transactions, it cannot use the tag RAM for the flush sequence unless there is a guaran-
tee that no new transaction will be initiated on the bus. The only way to ensure that no new transactions will occur is for the TSPC2605
to be granted the bus. Thus, upon entering the sequence initiated by the assertion of L2 FLUSH, the TSPC2605 will assert L2 BR. As
soon as L2 BG is asserted, the TSPC2605 can start stepping through the tag RAM entries.
L2 FLUSH need not be held asserted for the flush sequence to complete. Once started the sequence will run to completion unless
overridden by an assertion of HRESET.
5.9.2.L2 MISS INH
When L2 MISS INH is asserted, the TSPC2605 will not load any new data into the cache. The data already present will remain valid
and the TSPC2605 will respond to cache hits. This condition only lasts as long as L2 MISS INH is asserted. When L2 MISS INH is
negated, the TSPC2605 will start to bring new data into the cache when there are cache misses.
5.9.3.L2 TAG CLR
When L2 TAG CLR is asserted, the TSPC2605 will invalidate all entries in the cache. This internal sequence is the same as the one
initiated by an assertion of HRESET. During this sequence, the TSPC2605 will not participate in any bus transaction. However, it will
keep track of all bus transactions so that when the sequence is finished, the TSPC2605 can immediately participate in the next bus
transaction.
As is the case with assertions of L2 FLUSH, an assertion of L2 TAG CLR need not be held for the duration of the sequence. Once
asserted the sequence will run to completion regardless of the state of L2 TAG CLR.
5.9.4.L2 UPDATE INH
When L2 UPDATE INHis asserted, theTSPC2605isdisabledfromrespondingtocacheabletransactions. Bustransactionscontinue
to be monitored so that as soon as L2 UPDATE INH is negated, the MPC204GA can participate in the next transaction.
18/36
TSPC2605
5.10. Waveforms
5.10.1.Read HIT/Write HIT
Figure 1 shows a read hit from an idle bus state. The TSPC2605 asserts L2 CLAIM the cycle after TS to inform the memory controller
that there is a cache hit and the cache will control the rest of the transaction. L2 CLAIM is held through the cycle after AACK is
asserted. Since there are no active data tenures from previous transactions, the TSPC2605 asserts AACK the cycle after TS is
asserted. Note there must be a qualified assertion of CPU DBG in the same cycle as the assertion of TSfor the TSPC2605 to respond
with TA in the next cycle. CPU DBG does not affect the timing of L2 CLAIM or AACK.
The write hit timing is virtually the same. The only difference is the processor drives the data instead of the TSPC2605.
1
2
3
4
5
6
CLK
CPU BG
TS
A
A0 – A31
TBST
L2
CLAIM
AACK
CPU DBG
DBB
TA
DH0 – DH31,
DL0 – DL31
A1
A2
A3
A4
LEGEND
Signal driven to the TSPC2605
Signal driven by the TSPC2605
High–Z
Figure 1. Burst Read (or Write) Hit
19/36
TSPC2605
5.10.2.Multiple Read/Write HITS (NORMAL BUS MODE)
Figure 2 is an illustration of TSPC2605 pipeline depth limit with multiple read hits. The TSPC2605 supports only one level of address
pipeliningfor data transfer. Therefore, it must hold off on its assertion of AACK for a pipelined TS until the data tenure for the first TS is
done. The TSPC2605 asserts AACK at the same time as the fourth TA for data tenures that it controls.
1
2
3
4
5
6
7
8
9
10
11
CLK
CPU
BG
TS
A0 –
A31
A
B
C
TBST
L2
CLAIM
AACK
CPU
DBG
DBB
TA
DH0 –
DH31, DL0
– DL31
A1
A2
A3
A4
B1
B2
B3
B4
LEGEND
Signal driven to the TSPC2605
Signal driven by the TSPC2605
High–Z
Figure 2. Multiple Burst Read (or Write) Hits
20/36
TSPC2605
5.10.3.Read MISS (NORMAL BUS MODE)
Figure 3 is an illustration of TSPC2605 pipeline depth with a read miss followed by a read hit.
For illustration purposes the read miss is shown as a 3–1–1–1 response from memory. AACK for the second access is not driven true
until the cycle after the fourth TA of the read miss. This is because the TSPC2605 is not in control of TA for the first access and must,
therefore, wait until the first access’ data tenure is complete before it can drive AACK true for the read hit.
1
2
3
4
5
6
7
8
9
10
11
12
CL
K
CPU
BG
TS
A0 –
A31
A
B
TBS
T
L2
CLAIM
AAC
K
CPU
DBG
DBB
TA
DH0 –
DH31, DL0
– DL31
A1
A2
A3
A4
B1
B2
B3
B4
LEGEND
Signal driven to the TSPC2605
Signal driven by the TSPC2605
High–Z
Figure 3. Read Miss Followed by a Burst Read Hit for MPC603/604
21/36
TSPC2605
5.10.4.Multiple read HITS (FAST L2 MODE)
Back to back pipelined burst read hits for the MPC604 in Fast L2 mode, also called data streaming mode, are shown in Figure 4. Note
that CPU DBG is negated except for the cycles coincident with the fourth TA of each data tenure. This is a requirement for data
streaming. Note also that DBB is not shown. For proper operation in Fast L2 mode the DBB pin of the TSPC2605 must be tied to a
pull–up resistor.
1
2
3
4
5
6
7
8
9
10
11
12
CLK
CPU
BG
TS
A
B
C
D
A0 –
A31
TBST
L2
CLAIM
AACK
CPU
DBG
TA
DH0 –
DH31, DL0
– DL31
A1
A2
A3
A4
B1
B2
B3
B4
C1
C2
C3
LEGEND
Signal driven to the TSPC2605
Signal driven by the TSPC2605
High–Z
Figure 4. Multiple Burst Read Hits in Fast L2 Mode
22/36
TSPC2605
5.10.5.Write Through Burst Write HIT
Figure 5 shows the fastest possible burst write hit to a write–through mode L2 cache line, read miss or write miss processing that
replaces a clean line. For these operations TSPC2605 will not assert any signals on the 60X bus. A cache line is considered write
through if WT is asserted by the processor when it asserts TS.
The speed at which a write–through operation completes is
solely dependent on the memory controller. The timing shown
here assumes that the memory controller has a write buffer
that can accept data this quickly.
1
2
3
4
5
6
7
8
CLK
CPU
BG
TS
A
A0 – A31
TBS
T
WT
L2
CLAIM
AACK
CPU
DBG
DBB
TA
DH0 – DH31,
DL0 – DL31
A1
A2
A3
A4
LEGEND
Signal driven to the TSPC2605
Signal driven by the TSPC2605
High–Z
Figure 5. Fastest Possible Write Through Burst Write Hit for MPC603/604
23/36
TSPC2605
5.10.6.Read/Write MISS
Figure 6 is an illustration of a processor read or write miss that causes the TSPC2605 to replace a dirty line. L2 BR is asserted two
clocks after TS. The dirty data to be replaced is moved into the internal cast out buffer (COB) at the same time the new data is written
into the cache. Note that the copyback operation occurs after the processor request is satisfied. In addition, no delay is added to the
processor transaction. It proceeds as fast as the memory controller will allow.
1
2
3
4
5
6
7
8
9
10
11
12
CLK
CPU
BG
L2 BR
L2 BG
TS
A0 –
A31
A
B
TBS
T
L2
CLAIM
AACK
CPU
DBG
L2
DBG
DBB
TA
DH0 –
DH31, DL0
– DL31
A1
A2
A3
A4
B1
B2
B3
B4
LEGEND
Signal driven to the TSPC2605
Signal driven by the TSPC2605
High–Z
Figure 6. Read or Write Miss Followed by Castout
24/36
TSPC2605
5.10.7.Read/Write Snoop HIT (DIRTY L2 LINE)
Figure 7 is an illustration of a read or write snoop to a cache line that is dirty in the L2, but is not dirty in the processor’s cache. When a
snoop hits a dirty line, the TSPC2605 will assert ARTRY through the cycle following the assertion of AACK. This cycle is called the
ARTRY window. Note that the TSPC2605 also asserts L2 BR at the same time it asserts ARTRY. Because the snoop could also have
hit a dirty line in the processor’s cache, the TSPC2605 samples the processor’s BR signal the cycle following the ARTRY window.
This cycle is called the BR window. If the processor’s BR signal is not asserted, the TSPC2605 will start sampling L2 BG, the cycle
after the BR window.
Note that the TSPC2605 cannot do a 2–1–1–1 copy back burst. The earliest that it can handle the first assertion of TA is two cycles
after its assertion of TS.
1
2
3
4
5
6
7
8
9
10
11
12
CLK
CPU
BR
CPU
BG
L2 BR
L2 BG
TS
A0 –
A31
A
A
A
L2
CLAIM
AACK
ARTRY
CPU
DBG
L2
DBG
DBB
TA
DH0 –
DH31, DL0
– DL31
A1
A2
A3
A4
LEGEND
Signal driven to the TSPC2605
Signal driven by the TSPC2605
High–Z
Figure 7. Read or Write Snoop Hit to Dirty L2 Cache Line and Clean Processor Cache Line
25/36
TSPC2605
5.10.8.Read/Write Snoop HIT (DIRTY L2 AND PROCESSOR LINE)
An illustration of PowerPC read or write snoop hit to a dirty L2 cache line is shown in Figure 8. The processor has a dirty copy of the
cache line. In this case, both the processor and the TSPC2605 assert ARTRY. This situation is detected by sampling CPU BR in the
BR window, as described in the previous example. If CPU BR is asserted in the BR window, the TSPC2605 will negate L2 BR. It will
also ignore assertions of L2 BG. This allows the processor to write back its dirty cache line, at which time the TSPC2605 will either
update or invalidate its copy depending on whether it is a snoop read or snoop write.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
CLK
CPU
BR
CPU
BG
L2 BR
L2 BG
TS
A0 –
A31
A
A
A
L2
CLAIM
AACK
ARTRY
CPU
DBG
L2
DBG
DBB
TA
DH0 –
DH31, DL0
– DL31
A1
A2
A3
A4
LEGEND
Signal driven to the TSPC2605
Signal driven by the TSPC2605
High–Z
Figure 8. Read or Write Snoop Hit to Dirty L2 Cache Line and Dirty Processor Cache Line
26/36
TSPC2605
5.10.9.Read HIT/Write HIT (WITHOUT CPU DBG PARKED)
Most of the previous examples have assumed CPU DBG is asserted in the same cycle that the processor asserts TS. This implies
CPU DBGisparked. InsomesystemsitmaynotbedesirableorpossibletoparkCPUDBG. Figure9showstheresponseforareadhit
from the TSPC2605 is gated by the assertion of CPU DBG. The fastest response possible in a system that does not park CPU DBG is
3–1–1–1.
1
2
3
4
5
6
7
CL
K
CPU
BG
TS
A0 –
A31
A
TBS
T
L2
CLAIM
AAC
K
CPU
DBG
DB
B
TA
DH0 –
DH31, DL0
– DL31
A1
A2
A3
A4
LEGEND
Signal driven to the TSPC2605
Signal driven by the TSPC2605
High–Z
Figure 9. Burst Read (or Write) Hit Without CPU DBG Parked
27/36
TSPC2605
5.11.Test Access Port Description
5.11.1.Instruction Set
A five pin IEEE Standard 1149.1 Test Port (JTAG) is included on this device. When the TAP (Test Access Port) controller is in the
SHIFT–IR state, the instruction register is placed between TDI and TDO. In this state, the desired instruction would be serially loaded
through the TDI input. TRST resets the TAP controller to the test–logic reset state. The TAP instruction set for this device are as
follows.
5.11.2.Standard Instructions
Code
(Binary)
Instruction
BYPASS
Description
1111*
Bypass instruction
SAMPLE/PRELOAD
0010
Sample and/or preload
instruction
EXTEST
HIGHZ
0000
1001
Extest instruction
High–Z all output pins while
bypass register is between
TDI and TDO
CLAMP
1100
Clamp output pins while
bypass register is between
TDI and TDO
* Default state at power–up.
5.11.3.SAMPLE/PRELOAD TAP Instruction
The SAMPLE/PRELOAD TAP instruction is used to allow scanning of the boundary–scan register without causing interference to the
normal operation of the chip logic. The 169–bit boundary–scan register contains bits for all device signal and clock pins and
associated control signals. This register is accessible when the SAMPLE/PRELOAD TAP instruction is loaded into the TAP instruc-
tion register in the SHIFT–IR state. When the TAP controller is then moved to the SHIFT–DR state, the boundary–scan register is
placed between TDI and TDO. This scan register can then be used prior to the EXTEST instruction to preload the output pins with
desired values so that these pins will drive the desired state when the EXTEST instruction is loaded. As data is written into TDI, data
also streams out TDO which can be used to pre–sample the inputs and outputs.
SAMPLE/PRELOAD would also be used prior to the CLAMP instruction to preload the values on the output pins that will be driven out
when the CLAMP instruction is loaded.
5.11.4.EXTEST TAP Instruction
The EXTEST instruction is intended to be used in conjunction with the SAMPLE/PRELOAD instruction to assist in testing board level
connectivity. Normally, the SAMPLE/PRELOAD instruction would be used to preload all output pins. The EXTEST instruction would
then be loaded. During EXTEST, the boundary–scan register is placed between TDI and TDO in the SHIFT–DR state of the TAP
controller. Once the EXTEST instruction is loaded, the TAP controller would then be moved to the run–test/idle state. In this state, one
cycle of TCK would cause the preloaded data on the output pins to be driven while the values on the input pins would be sampled.
Note the TCK, not the clock pin (CLK), is used as the clock input while CLK is only sampled during EXTEST. After one clock cycle of
TCK, the TAP controller would then be moved to the SHIFT–DR state where the sampled values would be shifted out of TDO (and
new values would be shifted in TDI). These values would normally be compared to expected values to test for board connectivity.
5.11.5.CLAMP TAP Instruction
The CLAMP instruction is provided to allow the state of the signals driven from the output pins to be determined from the boundary–
scan register while the bypass register is selected as the serial path between TDI and TDO. The signals driven from the output pins
will not change while the CLAMP instruction is selected. EXTEST could also be used for this purpose, but CLAMP shortens the board
scan path by inserting only the bypass register between TDI and TDO. To use CLAMP, the SAMPLE/PRELOAD instruction would be
used first to scan in the values that will be driven on the output pins when the CLAMP instruction is active.
5.11.6.HIGHZ TAP Instruction
The HIGH–Z instruction is provided to allow all the outputs to be placed in an inactive drive state (high–Z). During the HIGH–Zinstruc-
tion the bypass register is connected between TDI and TDO.
5.11.7.BYPASS TAP Instruction
TheBYPASSinstructionisthedefaultinstructionloadedatpowerup. ThisinstructionwillplaceasingleshiftregisterbetweenTDIand
TDO during the SHIFT–DR state of the TAP controller. This allows the board level scan path to be shortened to facilitate testing of
other devices in the scan path.
28/36
TSPC2605
5.11.8.Disabling the Test Access Port and Boundary Scan
It is possible to use this device without utilizing the four pins used for the test access port. To circuit disable the device, TCK must be
tied to VSS to preclude mid level inputs. TRST should be tied to VSS to ensure proper HRESET operation. Although TDI and TMS are
designedin such a way that an undriven input will produce a response equivalent to the application of a logic 1, it is still advisable to tie
these inputs to VDD through a 1K resistor. TDO should remain unconnected.
TEST–LOGIC
1
RESET
0
1
RUN–TEST/
IDLE
0
SELECT DR–
SCAN
0
SELECT IR–
SCAN
0
1
1
1
1
CAPTURE–DR
CAPTURE–IR
0
0
SHIFT–IR
SHIFT–DR
0
0
1
1
1
1
EXIT1–DR
EXIT1–IR
0
0
PAUSE–IR
PAUSE 1–DR
0
0
1
1
0
0
EXIT2–DR
EXIT2–IR
1
1
UPDATE–DR
UPDATE–IR
1
1
0
0
NOTE: The value adjacent to each state transition represents the signal present at TMS at the rising edge of TCK.
Figure 10. TAP Controller State Diagram
29/36
TSPC2605
5.12.Boundary Scan Order
5.12.1.Bit number
The order of the boundary scan chain. Bit 0 is the closest to TDO.
5.12.2.Bit/pin name
The name of the physical pin. For an output enable cell, this is the name of the corresponding output enable.
5.12.3.Bit/pin type
Input — Input only pin.
I/O — Bi–directional pin that can be put into high–Z state.
Output — Output only pin.
Output Enable — Boundary scan cell to hold the output enable state of other I/O pads. Output enable does not correspond to a
physical pin. To set an I/O to an input, the output enable must have a 1. To set an I/O to an output, the output enable must have a 0.
Note that these internal output enables are active low.
Reserved – This signal is reserved and must always be a 1.
5.12.4.Output enable
The name of the output enable cell that determines if the cell is enabled or in the high–Z state. If the pin type is input or output enable,
this entry will be empty.
Bit
Number
Bit/Pin
Type
Output
Enable
Bit
Number
Bit/Pin
Type
Output
Enable
Bit/Pin Name
Reserved
DL16
DL17
DL18
DL19
DL20
DL21
DL22
DL23
DP6
Bit/Pin Name
DP3
0
1
Reserved
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
I/O
I/O
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DH16
2
DH17
I/O
3
DH18
I/O
4
DH19
I/O
5
DH20
I/O
6
DH21
I/O
7
DH22
I/O
8
DH23
I/O
9
DP2
I/O
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
DL24
DL25
DL26
DL27
DL28
DL29
DL30
DL31
DP7
L2 BG
Input
Input
I/O
L2 MISS INH
ABB
ABBOE
CPU3 DBG
CPU3 BG
CPU3 BR
CPU2 DBG
CPU2 BG
CPU2 BR
FDN
Input
Input
Input
Input
Input
Input
I/O
DH24
DH25
DH26
DH27
DH28
DH29
DH30
DH31
FDNOE
L2 DBG
L2 BR
Input
I/O
L2BROE
TAOE
TA
I/O
L2 CLAIM
CPU DBG
AACK
Output
Input
I/O
L2CLAIMOE
AACKOE
AOE
CI
I/O
30/36
TSPC2605
Bit
Number
Bit/Pin
Type
Output
Enable
Bit
Number
Bit/Pin
Type
Output
Enable
Bit/Pin Name
ARTRY
WT
Bit/Pin Name
DL1
DL2
DL3
DL4
DL5
DL6
DL7
DP4
DL8
DL9
DL10
DL11
DL12
DL13
DL14
DL15
DP5
A0
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
79
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
I/O
I/O
ARTRYOE
AOE
97
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
98
CPU BR
TEA
Input
Input
Input
I/O
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
PWRDN
DBB
DBBOE
HRESET
TBST
TT0
Input
I/O
AOE
AOE
AOE
AOE
AOE
AOE
AOE
I/O
TS
I/O
TT1
I/O
TT2
I/O
TT4
I/O
TT3
I/O
CPU BG
SRESET
L2 TAG CLR
L2 UPDATE INH
CPU4 BG
CPU4 DBG
CPU4 BR
CFG0
CFG2
CFG1
DH8
Input
Input
Input
Input
Input
Input
Input
Input
Input
Input
I/O
A1
A2
A3
A4
A5
A6
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
DOE
A7
DH9
I/O
A8
DH10
DH11
I/O
A9
I/O
A10
A11
A12
A31
A30
A29
A28
A27
A26
A25
A24
A23
A22
A21
A20
A19
DH12
DH13
DH14
DH15
DP1
I/O
I/O
I/O
I/O
I/O
DH0
I/O
DH1
I/O
DH2
I/O
Dh3
I/O
DH4
I/O
DH5
I/O
DH6
I/O
DH7
I/O
DP0
I/O
DL0
I/O
31/36
TSPC2605
Bit
Number
Bit/Pin
Type
Output
Enable
Bit/Pin Name
A18
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
I/O
I/O
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
AOE
A17
A16
I/O
A15
I/O
A14
I/O
A13
I/O
TSIZ2
TSIZ0
TSIZ1
GBL
I/O
I/O
I/O
Output
Input
Input
Input
I/O
CFG3
L2 CI
L2 FLUSH
AP0
AOE
AOE
AP1
I/O
AP2
I/O
AOE
AP3
I/O
AOE
APE
Output
APEOE
TAOE
Output
Enable
159
160
L2CLAIMOE
L2BROE
Output
Enable
Output
Enable
32/36
TSPC2605
6. PREPARATION FOR DELIVERY
6.1. Packaging
Microcircuits are prepared for delivery in accordance with MIL-PRF-38535.
6.2. Certificate of compliance
TCSoffersacertificateofcomplianceswitheachshipmentofparts, affirmingtheproductsareincomplianceeitherwithMIL-STD-883
and guarantying the parameters not tested at temperature extremes for the entire temperature range.
7. HANDLING
MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devi-
ces have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recom-
mended :
a) Devices should be handled on benches with conductive and grounded surfaces.
b) Ground test equipment, tools and operator.
c) Do not handle devices by the leads.
d) Store devices in conductive foam or carriers.
e) Avoid use of plastic, rubber, or silk in MOS areas.
f) Maintain relative humidity above 50 percent if practical.
33/36
TSPC2605
8. PACKAGE MECHANICAL DATA
8.1. 241 pins – PBGA
PACKAGE DIMENSIONS
ZP PACKAGE
PBGA
CASE 1138–01
0.20
4X
D
A
C
0.20 C
0.25 C
0.35 C
NOTES:
E
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
E2
2. DIMENSIONS IN MILLIMETERS.
3. DIMENSION b IS THE SOLDER BALL
DIAMETER MEASURED PARALLEL TO
DATUM C.
MILLIMETERS
DIM MIN MAX
A
A1
A2
A3
b
–––
0.50
0.95
0.70
0.60
2.05
0.70
1.35
0.90
0.90
D2
TOP VIEW
D1
D
D1
25.00 BSC
22.86 BSC
B
D2 22.40 22.60
e
E
1.27 BSC
25.00 BSC
22.86 BSC
E1
18X
e
E2 22.40 22.60
W
V
U
T
R
P
N
M
L
K
J
A2
A3
A1
E1
A
H
G
F
SIDE VIEW
E
D
C
B
A
241
b
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
M
M
0.03
0.15
C A B
C
BOTTOM VIEW
34/36
TSPC2605
8.2. 241 pins – CBGA (To Be Confirmed)
PACKAGE DIMENSIONS
G PACKAGE
CBGA
D
NOTES:
E
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
E2
2. DIMENSIONS IN MILLIMETERS.
MILLIMETERS
DIM MIN MAX
A
A2
A3
b
2.524 3.004
1.37
2.26
0.76
1.63
2.70
0.96
D2
TOP VIEW
D1
D
25.00 BSC
22.86 BSC
D1
D2
e
E
E1
E2
16.3
16.7
1.27 BSC
25.00 BSC
22.86 BSC
16.3
16.7
18X
e
W
V
U
T
R
P
N
M
L
K
J
A2
A3
E1
A
H
G
F
SIDE VIEW
E
D
C
B
A
241
b
1
2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
BOTTOM VIEW
35/36
TSPC2605
9. ORDERING INFORMATION
TS (X) PC2605 M G B / C 66
(1)
TCS prefix
Prototype
Type
Temperature range : Tc
M : –55, +125 °C
V : –40, +110 °C
(2)
Speed
66 : 66 MHz
Package :
ZP : PBGA
G
:
CBGA
(2)
Screening level
__ : Standard
:
B/C : MIL-STD-883, class B
B/T : according to MIL-STD-883
U
:
Upscreening
U/T : Upscreening + burn-in
(1) THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES
(2) For availability of the different versions, contact your TCS sale office
Information furnished is believed to be accurate and reliable. However THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES
assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of THOM-
SON-CSF SEMICONDUCTEURS SPECIFIQUES. Specifications mentioned in this publication are subject to change without notice.
This publication supersedes and replaces all information previously supplied. THOMSON-CSF SEMICONDUCTEURS SPECIFI-
QUES products are not authorized for use as critical components in life support devices or systems without express written approval
from THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES.
The PowerPC names and logo type are trademarks of International Business Machines Corporation, used under licence
1997 THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - Printed in France - All rights reserved.
This product is manufactured and commercialized by THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - Avenue de Roche-
plaine PO Box 123 - 38521 SAINT-EGREVE Cedex - FRANCE.
For further information please contact :
THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - Route Départementale 128 - PO Box 46 - 91401 ORSAY Cedex -
FRANCE - Phone +33 (0)1 69 33 00 00 - Fax +33 (0)1 69 33 03 21 - Telex 616780 F TCS - Email : lafrique@tcs.thomson.fr
36/36
相关型号：
©2020 ICPDF网 联系我们和版权申明