TSS901E [ATMEL]
Tripple Point to Point IEEE 1355 High Speed Controller; TRIPPLE点对点IEEE 1355高速控制器
| 型号： | TSS901E |
| 厂家： | 
ATMEL |
| 描述： | Tripple Point to Point IEEE 1355 High Speed Controller |
| 文件： | 总31页 (文件大小：285K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• 3 identical bidirectional link channels allowing full duplex communication under
selectable transmit rate from 1.25 up to 200 Mbit/s in each direction
• A COmmunication Memory Interface (COMI) provides autonomous accesses to a
communication memory which are controlled by an arbitration unit, allowing two
TSS901E to share one Dual Port Ram without external arbitration
• The scalable databus width (8/16/32 bit) allows flexible integration with any CPU type
• Little or big endian mode is configurable
• AHOst Control Interface (HOCI) gives read/write accesses to the TSS901E
configuration registers and to the DS-link channels for the controlling CPU
• Device control via one of the three links allows its use in systems without a local
controller
• Link disconnect detection and parity check at token (data and control) level; possible
checksum generation for packet level check
• Power saving mode relying on automatic transmit rate reduction
• Auser’s manual of the TSS901E (also called SMCS332) is available at:
http://www.omimo.be/companies/dasa_000.htm
Tripple Point to
Point IEEE 1355
High Speed
• Designed on Atmel MG1140E matrix and packaged into MQFPL196
Controller
Description and Applications
The TSS901E provides an interface between a Data-Strobe link - according to the
IEEE Std 1355-1995 specification carrying a simple interprocessor communication
protocol - and a data processing node consisting of a CPU and a communication and
data memory.
TSS901E
The TSS901E offers hardware supported execution of the major parts of the interpro-
cessor communication protocol: data transfer between two nodes of a multi-processor
system is performed with minimal host CPU intervention. The TSS901E can execute
simple commands to provide basic features for system control functions; a provision of
fault tolerant features exists as well.
Although the TSS901E initial exploitation is for use in multi-processor systems where
the high speed links standardisation is an important issue and where reliability is a
requirement, it could be used in applications such as heterogeneous systems or mod-
ules without any communication feature like special image compression chips, some
signal processors, application specific programmable logic or mass memory.
The TSS901E may also be used in single board systems where standardised high
speed interfaces are needed and systems containing "non-intelligent" modules such
as A/D-converter or sensor interfaces which can be assembled with the TSS901E
thanks to the "control by link" feature.
Rev. C – 24-Aug-01
1
TSS901E
Introduction
The TSS901E provides an interface between a Data-Strobe link according to the IEEE
Std 1355-1995 specification carrying the simple interprocessor communication proto-
col (1) and a data processing node consisting of a CPU and communication and data
memory. The TSS901E provides HW supported execution of the major parts of the sim-
ple interprocessor communication protocol, particularly:
•
•
•
transfer of data between two modes of a multi-processor system with minimal host
CPU intervention,
execution of simple commands to provide basic features for system control
functions,
provision of fault tolerant features.
However, with disabling of features such as the protocol handling or with reduction of
the transmit rate (TSS901E automatically reduces transmit rate for sending null tokens)
also low power usage is supported.
Figure 1. TSS901E Block Diagram
CADR
Receive
CCTRL
COMI
CDATA
RX1_DS
TX1_DS
DS
macro
cell
Protocol
HADR
HCTRL
HDATA
Transmit
HOCI
Channel 1
HINT
RCPU
SES
RX2_DS
TX2_DS
Channel 2
Channel 3
PRCI
JTAG
UTIL
Test
RX3_DS
TX3_DS
Target applications are heterogeneous multi-processor systems supported by scalable
interfaces including the little/big endian swapping. The TSS901E connects modules with
different processors (e.g. TSC21020F, ERC32, TSC695E and others). Any kind of net-
work topology could be realized through the high speed point-to-point IEEE1355-links
(see chapter Applications).
1.
Rastetter P. et.al., Simple Interprocessor Communication Protocol Specification, DIP-
SAPII-DAS-31-01, Issue 3, 08.10.96, also available on the same web site as the users
guide.
2
Rev. C – 24-Aug-01
Interfaces
The TSS901E consists of the following blocks (See Figure 1):
•
bidirectional link channels, all comprising the DS-link macro cell (DSM), receive
and transmit sections (each including FIFOs) and a protocol processing unit (PPU).
Each channel allows full duplex communication up to 200 Mbit/s in each direction.
With protocol command execution a higher level of communication is supported.
Link disconnect detection and parity check at token level are performed. A
checksum generation for a check at packet level can be enabled.
The transmit rate is selectable between 1.25 and 200 Mbit/s; an additional power
saving mode can be enabled, where the transmit rate is automatically reduced to 10
Mbit/s when only Null tokens are being transmitted over the link. The default trans-
mit rate is 10 Mbit/s. For special applications the data transmit rate can be
programmed to values even below 10 Mbit/s; the lowest possible (to be within the
IEEE-1355 specification) transmit rate is 1.25 Mbit/s (the next values are 2.5 and 5
Mbit/s).
•
Communication Memory Interface (COMI) performs autonomous accesses to the
communication memory of the module to store data received via the links or to read
data to be transmitted via the links. The COMI consists of individual memory
address generators for the receive and transmit direction of every DS link channel.
The access to the memory is controlled via an arbitration unit providing a fair
arbitration scheme. Two TSS901E can share one DPRAM without external
arbitration.
The data bus width is scalable (8/16/32 bit) to allow flexible integration with any
CPU type.
Operation in little or big endian mode is configurable through internal registers.
The COMI address bus is 16 bit wide allowing direct access of up to 64K words of
the DPRAM. Two chip select signals are provided to allow splitting of the 64k
address space in two memory banks.
•
Host Control Interface (HOCI) gives read and write access to the TSS901E
configuration registers and to the DS-link channels for the controlling CPU. Viewed
from the CPU, the interface behaves like a peripheral that generates acknowledges
to synchronize the data transfers and which is located somewhere in the CPU's
address space.
Packets can be transmitted or received directly via the HOCI. In this case the Com-
munication Memory (DPRAM) is not strictly needed. However, in this case the
packet size should be limited to avoid frequent CPU interaction.
The data bus width is scalable (8/16/32 bit) to allow flexible integration with any
CPU type. The byte alignment can be configured for little or big endian mode
through an external pin.
Additionally the HOCI contains the interrupt signalling capability of the TSS901E by
providing an interrupt output, the interrupt status register and interrupt mask register
to the local CPU.
A special pin is provided to select between control of the TSS901E by HOCI or by
link. If control by link is enabled, the host data bus functions as a 32-bit general pur-
pose interface (GPIO).
•
•
Protocol Command Interface (PRCI) that collects the decoded commands from all
PPUs and forwards them to external circuitry via 5 special pins.
JTAG Test Interface that represents the boundary scan testing provisions specified
by IEEE Standard 1149.1 of the Joint Testing Action Group (JTAG). The TSS901E'
test access port and on-chip circuitry is fully compliant with the IEEE 1149.1
specification. The test access port enables boundary scan testing of circuitry
connected to the TSS901E I/O pins.
3
TSS901E
Rev. C – 24-Aug-01
TSS901E
Operation Modes
According to the different protocol formats expected for the operation of the TSS901E,
two major operation modes are implemented into the TSS901E. The operation modes
are chosen individually for each link channel by setting the respective configuration reg-
isters via the HOCI or via the link.
•
Transparent Mode (default after reset): This mode allows complete transparent
data transfer between two nodes without performing any interpretation of the
databytes and without generating any acknowledges. It is completely up to the host
CPU to interpret the received data and to generate acknowledges if required.
The TSS901E accepts EOP1 and EOP2 control tokens as packet delimiters and
generates autonomously EOP1/EOP2 (as configured) markers after each end of a
transmission packet.
This mode also includes as a special submode:
–
Wormhole routing: This mode allows hardware routing of packets by the
TSS901E.
•
Simple Interprocessor Communication (SIC) Protocol Mode: This mode executes
the simple interprocessor communication protocol as described in the protocol
specification (1). The following capabilities of the protocol are implemented into the
TSS901E:
–
–
interpretation of the first 4 data tokens as the header bytes of the protocol
autonomous execution of the simple control commands as described in the
protocol specification(1)
–
autonomous acknowledgement of received packets if configured
In transmit direction no interpretation of the data is performed. This means that for
transmit packets, the four header bytes must be generated by the host CPU and
must be available as the first data read from the communication memory.
EOP1/EOP2 control tokens are automatically inserted by the TSS901E when one
configured transfer from the communication memory has finished.
1.
Rastetter P. et.al., Simple Interprocessor Communication Protocol Specification, DIP-
SAPII-DAS-31-01, Issue 3, 08.10.96, also available on the same web site as the users
guide.
4
Rev. C – 24-Aug-01
TSS901E Control by Link A feature of the TSS901E is the possibility to control the TSS901E not only via HOCI but
via one of the three links. This allows to use the TSS901E in systems without a local
controller (µController, FPGA etc.). Since the HOCI is no longer used in this operation
mode, it is instead available as a set of general purpose I/O (GPIO) lines.
Wormhole Routing
The TSS901E introduces a wormhole routing function similar to the routing implemented
in the ST-Microelectronics C104 routing switch. Each of the three links and the
TSS901E itself can be assigned an eight bit address. When routing is enabled in the
TSS901E, the first byte of a packet will be interpreted as the address destination byte,
analysed and removed from the packet (header deletion). If this address matches one of
the two other link addresses or the TSS901E address assigned previously, the packet
will be automatically forwarded to this link or the FIFO of the TSS901E. If the header
byte does not match a link address, the packet will be written to the internal FIFO as well
and an error interrupt (maskable) will be raised.
PPU Functional
Description
Since the Protocol Processing Unit (PPU) determines a major part of the TSS901E func-
tionality, the principal blocks of the PPU and their function are described here. This
functionality is provided for every DS link channel of the TSS901E.
•
Protocol Execution Unit: This unit serves as the main controller of the PPU block.
It receives the tokens from the DS macrocell and interprets (in protocol mode) the
four header data characters received after an EOP1/EOP2 control character. If the
address field matches the link channel address and the command field contains a
valid command then forwarding of data into the receive FIFO is enabled. If the
command field contains a "simple control command" then the execution request is
forwarded to the command execution unit.
The protocol execution unit also enables forwarding of header data characters to
the acknowledge generator and provides an error signal in case of address mis-
match, wrong commands or disabled safety critical "simple control commands".
The protocol execution unit is disabled in "transparent" or “wormhole routing” opera-
tion mode.
•
•
Receive, Transmit, Acknowledge: The transmit and receive FIFOs decouple the
DS link related operations from the TSS901E related operations in all modes and
such allows to keep the speed of the different units even when the source or sink of
data is temporarily blocked.
In the protocol mode a further FIFO (acknowledge FIFO) is used to decouple send-
ing of acknowledges from receiving new data when the transmit path is currently
occupied by a running packet transmission.
Command Execution Unit: This unit performs activating resp. deactivating of the
CPU reset and the specific external signals and provides the capability to reset one
or all links inside the TSS901E, all actions requested by the decoded commands
from the protocol execution unit.
The unit contains a register controlling the enable/disable state of safety critical
commands which is set into the 'enable' state upon command request and which is
reset after a safety critical command has been executed.
The CPU reset and the specific external signals are forwarded to the Protocol Com-
mand Interface (PRCI).
5
TSS901E
Rev. C – 24-Aug-01
TSS901E
Fault Tolerance
Applications
The IEEE Std 1355-1995 specifies low level checks as link disconnect detection and
parity check at token level. The TSS901E provides, through the Protocol Processing
Unit, features to reset a link or all links inside the TSS901E, to reset the local CPU or to
send special signals to the CPU commanded via the links.
Additionally it is possible to enable a checksum coder/decoder to have fault detection
capabilities at packet level.
The TSS901E is a very high speed, scalable link-interface chip with fault tolerance fea-
tures. The initial exploitation is for use in multi-processor systems where the
standardisation or the high speed of the links is an important issue and where reliability
is a requirement. Further application examples are heterogeneous systems or modules
without any communication features as special image compression chips, certain signal
processors (TSC21020F, ERC32, ...), application specific programmable logic or mass
memory.
The TSS901E could also be used for single board systems where standardised high
speed interfaces are needed. Even "non-intelligent" modules such as A/D-converter or
sensor interfaces can be assembled with the TSS901E because of the "control by link"
feature. The complete control of the TSS901E can be done via link from a central con-
troller-node.
6
Rev. C – 24-Aug-01
Register Set
This chapter describes the TSS901E registers which can be read or written by the HOCI
or via the link (in case the "control by link" is enabled) to control TSS901E operations.
All TSS901E control operations are performed by writes or reads of the respective regis-
ters. Most of the control operations are obvious from the content of the registers.
General Conventions:
•
•
•
bit 0 (D0) = least significant bit,
bit 7 (D7) = most significant bit (or bit 15 resp. bit 31)
D x:0 means data bit x until bit 0.
Access by HOCI: HOCI data transfer
Big/Little endian selection of the HOCI is done using a special pin (HOSTBIGE) of the
TSS901E. By connecting this pin to either Vcc or GND the HOCI is configured to be in
little or big endian mode as follows:
When Signal HOSTBIGE = '0' (GND), the HOCI data port is in little endian mode.
When Signal HOSTBIGE = '1' (Vcc), the HOCI data port is in big endian mode.
Little endian mode selected:
•
8 bit data port (default after reset)
register byte 0 is connected with pin HDATA0 - HDATA7
16 bit data port
–
•
–
–
register byte 0 is connected with pin HDATA0 - HDATA7
register byte 1 is connected with pin HDATA8 - HDATA15
•
32 bit data port
–
–
–
–
register byte 0 is connected with pin HDATA0 - HDATA7
register byte 1 is connected with pin HDATA8 - HDATA15
register byte 2 is connected with pin HDATA16 - HDATA23
register byte 3 is connected with pin HDATA24 - HDATA31
Big endian mode selected:
•
8 bit data port (default after reset)
register byte 0 is connected with pin HDATA24 - HDATA31
16 bit data port
–
•
–
–
register byte 0 is connected with pin HDATA24 - HDATA31
register byte 1 is connected with pin HDATA16 - HDATA23
•
32 bit data port
–
–
–
–
register byte 0 is connected with pin HDATA24 - HDATA31
register byte 1 is connected with pin HDATA16 - HDATA23
register byte 2 is connected with pin HDATA8 - HDATA15
register byte 3 is connected with pin HDATA0 - HDATA7
The registers of the TSS901E are 1, 2 or 4 Bytes wide. That means, if the HOCI data
port is in 8 bit mode, 4 read or write accesses are necessary to access a 4 Byte register
(e. g. the interrupt mask register). In 16/32 bit mode the data bits 31 - 8 are '0' if an 8 bit
register is read.
7
TSS901E
Rev. C – 24-Aug-01
TSS901E
Register Address Map
The addresses of the TSS901E registers are directly mapped with pins HADR7 - 0. The
tables below shows the addresses of all the TSS901E registers depending on the HOCI
port width.
TSS901E status and control registers
Port Width / Address
(hex)
Reset Value
(hex)
32
00
01
02
03
16
00
01
02
03
8
Register
SICR
Function
Access
r / w
r / w
r
00
01
02
03
TSS901E Interface Control Register
Transmit-Speed-Base Register
Routing Enable / Status Register
reserved
00
0A
00
00
TRS_CTRL
ROUTE_CTRL
04
05
06
07
04
06
04
ISR
Interrupt Status Register
Interrupt Mask Register
04010040
ro
08
09
0A
0B
08
0A
08
IMR
00000000
FF
r / w
r / w
COMI Chip Select 0 upper address boundary
Register
0C
0C
0C
COMI_CS0R
0D
0E
0F
0D
0E
0F
0D
0E
0F
reserved
COMI Arbitration Control Register
PRCI Register
00
08
00
COMI_ACR
PRCIR
r / w
r / w
TSS901E channel 1 status and control registers
Port Width / Address
(hex)
Reset Value
(hex)
32
10
11
12
13
14
15
16
17
16
10
11
12
13
14
15
16
17
8
Register
Function
Access
r / w
r / w
r / w
r / w
r / w
r / w
r / w
---
10
11
12
13
14
15
16
17
CH1_DSM_MODR
CH1_DSM_CMDR
CH1_DSM_STAR
CH1_DSM_TSTR
CH1_ADDR
channel 1 DSM mode Register
channel 1 DSM command Register
channel 1 DSM status Register
channel 1 DSM test Register
channel 1 address Register
channel 1 Route Address Register
channel 1 Protocol Status Register
reserved
03
00
00
00
00
00
04
00
CH1_RT_ADDR
CH1_PR_STAR
8
Rev. C – 24-Aug-01
Port Width / Address
(hex)
Reset Value
(hex)
32
18
19
1A
1B
1C
1D
1E
1F
16
18
19
1A
1B
1C
1D
1E
1F
8
Register
Function
Access
r / w
r / w
ro
18
19
1A
1B
1C
1D
1E
1F
CH1_CNTRL1
CH1_CNTRL2
CH1_HTID
channel 1 control Register 1
channel 1 control Register 2
channel 1 Header Transaction ID byte
channel 1 Header control byte
channel 1 detailed error source register 1
channel 1 detailed error source register 2
reserved
00
00
00
00
00
00
00
00
CH1_HCNTRL
CH1_ESR1
CH1_ESR2
ro
r / w
r / w
---
CH1_COMICFG
CH1_TX_SAR
channel 1 COMI configuration register
r / w
20
21
20
22
24
20
22
24
channel 1 transmit Start Address Register
channel 1 transmit End Address Register
channel 1 transmit Current Address Register
0000
0000
0000
r / w
r / w
ro
22
23
CH1_TX_EAR
CH1_TX_CAR
24
25
26
27
26
27
26
27
CH1_TX_FIFO
CH1_TX_EOPB
channel 1 transmit FIFO
--
--
wo
wo
channel 1 transmit EOP Bit Register
28
29
28
2A
2C
28
2A
2C
CH1_RX_SAR
CH1_RX_EAR
CH1_RX_CAR
channel 1 receive Start Address Register
channel 1 receive End Address Register
channel 1 receive Current Address Register
0000
0000
0000
r / w
r / w
ro
2A
2B
2C
2D
2E
2F
2E
2F
2E
2F
CH1_RX_FIFO
CH1_STAR
channel 1 receive FIFO
xxxxxxxx
01
ro
ro
channel 1 Status Register
TSS901E channel 2 status and control registers
Port Width / Address
(hex)
Reset Value
(hex)
32
30
31
32
33
34
35
16
30
31
32
33
34
35
8
Register
Function
Access
r / w
30
31
32
33
34
35
CH2_DSM_MODR
CH2_DSM_CMDR
CH2_DSM_STAR
CH2_DSM_TSTR
CH2_ADDR
channel 2 DSM mode Register
channel 2 DSM command Register
channel 2 DSM status Register
channel 2 DSM test Register
channel 2 address Register
channel 2 Route Address Register
03
00
00
00
00
00
r / w
r / w
r / w
r / w
CH2_RT_ADDR
r / w
9
TSS901E
Rev. C – 24-Aug-01
TSS901E
Port Width / Address
(hex)
Reset Value
32
36
37
38
39
3A
3B
3C
3D
3E
3F
16
36
37
38
39
3A
3B
3C
3D
3E
3F
8
Register
Function
(hex)
Access
36
37
38
39
3A
3B
3C
3D
3E
3F
CH2_PR_STAR
channel 2 Protocol Status Register
reserved
04
r / w
00
CH2_CNTRL1
CH2_CNTRL2
CH2_HTID
channel 2 control Register 1
channel 2 control Register 2
channel 2 Header Transaction ID byte
channel 2 Header control byte
channel 2 detailed error source register 1
channel 2 detailed error source register 2
reserved
00
r / w
r / w
ro
00
00
CH2_HCNTRL
CH2_ESR1
00
ro
00
r / w
r / w
CH2_ESR2
00
00
CH2_COMICFG
CH2_TX_SAR
channel 2 COMI configuration register
00
r / w
r / w
40
41
40
42
44
40
42
44
channel 2 transmit Start Address Register
channel 2 transmit End Address Register
channel 2 transmit Current Address Register
00
00
00
42
43
CH2_TX_EAR
CH2_TX_CAR
r / w
ro
44
45
46
47
46
47
46
47
CH2_TX_FIFO
CH2_TX_EOPB
channel 2 transmit FIFO
00
00
wo
wo
channel 2 transmit EOP Bit Register
48
49
48
4A
4C
48
4A
4C
CH2_RX_SAR
CH2_RX_EAR
CH2_RX_CAR
channel 2 receive Start Address Register
channel 2 receive End Address Register
channel 2 receive Current Address Register
00
00
00
r / w
r / w
ro
4A
4B
4C
4D
4E
4F
4E
4F
4E
4F
CH2_RX_FIFO
CH2_STAR
channel 2 receive FIFO
xxxxxxxx
01
ro
ro
channel 2 Status Register
TSS901E channel 3 status and control registers
Port Width / Address
(hex)
Reset Value
(hex)
32
50
51
52
16
50
51
52
8
Register
Function
Access
r / w
50
51
52
CH3_DSM_MODR
CH3_DSM_CMDR
CH3_DSM_STAR
channel 3 DSM mode Register
channel 3 DSM command Register
channel 3 DSM status Register
03
00
00
r / w
r / w
10
Rev. C – 24-Aug-01
Port Width / Address
(hex)
Reset Value
(hex)
32
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
16
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
8
Register
Function
Access
r / w
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
CH3_DSM_TSTR
CH3_ADDR
channel 3 DSM test Register
channel 3 address Register
channel 3 Route address Register
channel 3 Protocol Status Register
reserved
00
00
00
04
00
00
00
00
00
00
00
00
00
r / w
CH3_RT_ADDR
CH3__PR_STAR
r / w
r / w
CH3_CNTRL1
CH3_CNTRL2
CH3_HTID
channel 3 control Register 1
channel 3 control Register 2
channel 3 Header Transaction ID byte
channel 3 Header control byte
channel 3 detailed error source register 1
channel 3 detailed error source register 2
reserved
r / w
r / w
ro
CH3_HCNTRL
CH3_ESR1
ro
r / w
r / w
CH3_ESR2
CH3_COMICFG
CH3_TX_SAR
channel 3 COMI configuration register
r / w
r / w
60
61
60
62
64
60
62
64
channel 3 transmit Start Address Register
channel 3 transmit End Address Register
channel 3 transmit Current Address Register
00
00
00
62
63
CH3_TX_EAR
CH3_TX_CAR
r / w
ro
64
65
66
67
66
67
66
67
CH3_TX_FIFO
CH3_TX_EOPB
channel 3 transmit FIFO
00
00
wo
wo
channel 3 transmit EOP Bit Register
68
69
68
6A
6C
68
6A
6C
CH3_RX_SAR
CH3_RX_EAR
CH3_RX_CAR
channel 3 receive Start Address Register
channel 3 receive End Address Register
channel 3 receive Current Address Register
00
00
00
r / w
r / w
ro
6A
6B
6C
6D
6E
6F
6E
6F
6E
6F
CH3_RX_FIFO
CH3_STAR
channel 3 receive FIFO
xxxxxxxx
01
ro
ro
channel 3 Status Register
11
TSS901E
Rev. C – 24-Aug-01
TSS901E
TSS901E GPIO control
registers
These registers are only enabled when the TSS901E is configured for "control by link"
using the ’BOOTLINK’ pin.
Port Width / Address
(hex)
Reset Value
32
16
8
Register
Function
(hex)
Access
70
71
72
73
GPIO_DIR0
GPIO_DIR1
GPIO_DIR2
GPIO_DIR3
GPIO direction register 0
GPIO direction register 1
GPIO direction register 2
GPIO direction register 3
00
00
00
00
r / w
r / w
r / w
r / w
74
75
76
77
GPIO_DATA0
GPIO_DATA1
GPIO_DATA2
GPIO_DATA3
GPIO data register 0
GPIO data register 1
GPIO data register 2
GPIO data register 3
00
00
00
00
r / w
r / w
r / w
r / w
12
Rev. C – 24-Aug-01
Signal Description
The Figure below shows the TSS901E (also called SMCS332) embedded in a typical
module environment:
This section describes the pins of the TSS901E. Groups of pins represent busses where
the highest number is the MSB.
O = Output; I = Input; Z = High Impedance; (*) = active low signalO/Z = if using a config-
uration with two TSS901Es these signals can directly be connected together (WIROR)
max. output
Signal Name
HSEL*
Type
Function
current [mA]
load [pF]
I
I
I
Select host interface
HRD*
host interface read strobe
host interface write strobe
HWR*
TSS901E register address lines. This address lines will be
used to access (address) the TSS901E registers.
HADR(7:0)
I
HDATA(31:0)
IO/Z
TSS901E data
3
3
3
50
50
50
host acknowledge. TSS901E deasserts this output to add wait
states to a TSS901E access. After TSS901E is ready this
output will be asserted.
HACK
O/Z
HINTR*
O/Z
I
host interrupt request line
TSS901EADR(3:0
)
TSS901E Address. The binary value of this lines will be
compared with the value of the TSS901E ID lines.
TSS901E ID lines: offers possibility to use sixteen TSS901E
within one HSEL*
TSS901EID(3:0)
I
13
TSS901E
Rev. C – 24-Aug-01
TSS901E
max. output
Signal Name
Type
Function
current [mA]
load [pF]
1: host I/F Big Endian
0: host I/F Little Endian
HOSTBIGE
I
1: control by link
0: control by host
BOOTLINK
CMCS(1:0)*
I
Communication memory select lines. These pins are asserted
as chip selects for the corresponding banks of the
communication memory.
O/Z
8
25
Communication memory read strobe. This pin is asserted when
the TSS901E reads data from memory.
CMRD*
CMWR*
O/Z
O/Z
O/Z
IOZ
8
8
8
25
25
25
Communication memory write strobe. This pin is asserted
when the TSS901E writes to data memory.
Communication memory address. The TSS901E outputs an
address on these pins.
CMADR(15:0)
CMDATA(31:0)
Communication memory data. The TSS901E inputs and
outputs data from and to com. memory on these pins.
3
3
50
50
COCI
I
Communication interface ’occupied’ input signal
Communication interface ’occupied’ output signal
COCO
O/Z
Communication interface arbitration master input signal
CAM
I
1: master
0: slave
CPUR*
SES(3:0)*
LDI1
O/Z
O/Z
I
CPU Reset Signal
3
3
50
50
Specific External Signals
Link Data Input channel 1
LSI1
I
Link Strobe Input channel 1
Link Data Output channel 1
Link Strobe Output channel 1
Link Enable Out (for external drivers)
Link Data Input channel 2
LDO1
LSO1
LEN1
LDI2
O/Z
O/Z
O/Z
I
12
12
3
25
25
50
LSI2
I
Link Strobe Input channel 2
Link Data Output channel 2
Link Strobe Output channel 2
Link Enable Out (for external drivers)
Link Data Input channel 3
LDO2
LSO2
LEN2
LDI3
O/Z
O/Z
O/Z
I
12
12
3
25
25
50
LSI3
I
Link Strobe Input channel 3
Link Data Output channel 3
Link Strobe Output channel 3
Link Enable Out (for external drivers)
Test Reset. Resets the test state machine.
LDO3
LSO3
LEN3
TRST*
O/Z
O/Z
O/Z
I
12
12
3
25
25
50
14
Rev. C – 24-Aug-01
max. output
current [mA]
Signal Name
TCK
Type
Function
load [pF]
Test Clock. Provides an asynchronous clock for JTAG boundary
scan.
I
I
I
TMS
Test Mode Select. Used to control the test state machine.
Test Data Input. Provides serial data for the boundary scan
logic.
TDI
Test Data tt. Serial scan outCKL f the boundary scan
CKH
TDO
O/Z
I
3
50
path.
TSS901E Reset. Sets the TSS901E to a known state. This
input must be asserted (low) at power-up. The minimum width
of RESET low is 5 cycles of CLK10 in parallel with CLK
running.
RESET*
External clock input to TSS901E (max. 25 Mhz).
Must be derived from RAM access time.
CLK
I
I
External clock input to TSS901E DS-links (application specific,
nominal 10 Mhz). Used to generate to transmission speed and
link disconnect timeout.
CLK10
PLLOUT
Output of internal PLL. Used to connect a network of external
RC devices.
O
VCC
GND
Power Supply
Ground
15
TSS901E
Rev. C – 24-Aug-01
TSS901E
Electrical Specifications
The following data is provided for information only; for the guaranteed values, refer to
Atmel procurement specification.
Absolute Maximum Ratings
Parameter
Symbol
Value
-0.5 to +7
Unit
V
Supply Voltage
I/O Voltage
VCC
-0.5 to VCC + 0.5
-55 to +125
TJ < TA +20
-65 to +150
V
Operating Temperature Range (Ambient)
Junction Temperature
TA
TJ
°C
°C
°C
Storage Temperature Range
Tstg
Stresses above those listed may cause permanent damage to the device.
DC Electrical Characteristics
Specified at VCC = + 5 V ± 10% (TSS901E will only work with 5V)
Parameter
Operating Voltage
Symbol
VCC
Min.
4.5
Max.
Unit
V
Conditions
5.5
Input HIGH Voltage
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
VIH
2.0
V
VIL
0.8
V
VOH
2.4
V
max. output current
VOL
0.4
V
max. output current
160
130
mA
mA
VOUT = VCC
Output Short circuit current
IOS
VOUT = GND
Although specified for TTL outputs, all TSS901E outputs are CMOS compatible and will
drive to VCC and GND assuming no dc loads.
Max. power consumption figures (at 5.5V, 125°C) are:
Operation Mode
Power consumption [mA]
not clocked
5
TSS901E in RESET
TSS901E in IDLE
Maximum
45
70
190
16
Rev. C – 24-Aug-01
PLL Filter
The pin PLLOUT should be connected as shown below:
TSS90E
PLLOUT
R1
C2
C1
R1 = 249Ω ± 5%, ¼1/4W
C1 = 1nF, ± 5%, 200V
C2 = 15nF, ± 5%, 200V
17
TSS901E
Rev. C – 24-Aug-01
TSS901E
Timing Parameters
Clock Signals
Description
Symbol
tCLK
Min.
40
Max.
Unit
ns
CLK period 1)
CLK width high
CLK width low
tCLKH
tCLKL
17
ns
17
ns
Note:
1) Max. 25 MHz
Description
Symbol
tCLK10
Min.
100
40
Max.
Unit
ns
CLK10 period 1)
CLK10 width high
CLK10 width low
100
tCLK10H
tCLK10L
ns
40
ns
Note:
1) Typically 10 MHz
18
Rev. C – 24-Aug-01
Reset
Description
RESET setup before CLK high
Symbol
tRSTS
Min.
5
Max.
Unit
ns
RESET low pulse width
tRSTW
tOUTD
tOUTE
2 * tCLK
ns
Output disable after CLK high
42
ns
Output enable after CLK high
2 * tCLK + 26
ns
CAM, HOSTBIGE, BOOTLINK setup before RESET high
tCAMS
1
19
TSS901E
Rev. C – 24-Aug-01
TSS901E
Host Read
Description
Symbol
tHRSU
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
HSEL*, HRD* and TSS901EADR and HADR setup before CLK high
HADR, TSS901EADR hold after HSEL*, HRD* high
HRD* pulse width high
5
0
5
tHRAH
tHRDH
HACK low after HRD*, HSEL* active and TSS901EADR valid 1)
HACK high after CLK high
tHRACKL
tHRACKH
tHRACKA
tHRDV
16
3 * tCLK + 23
12
1 * tCLK + 5
HACK disable after HRD*, HSEL* inactive or TSS901EADR invalid 2)
HDATA valid before HACK high
0
5
HDATA hold after HRD*, HSEL* inactive or TSS901EADR invalid 2)
tHRDH
19
Note:
1) Signal HACK active when HRD* low and HSEL* low and TSS901EADR = TSS901EID
2) Signal HACK disable when HRD* high or HSEL* high or TSS901EADR ¼ TSS901EID
20
Rev. C – 24-Aug-01
Host Write
Description
Symb.
tHWSU
Min.
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
HSEL*, HWR* and TSS901EADR and HADR setup before CLK high
HADR, TSS901EADR hold after HSEL*, HWR* high
5
0
tHWAH
HWR* pulse width high
tHWWH
tHWACKL
tHWACKH
tHWACKA
tHWDSU
tHWDH
1 * tCLK + 5
HACK low after HWR*, HSEL* active and TSS901EADR valid 1)
HACK high after HSEL* and HWR* and TSS901EADR = TSS901EID
HACK disable after HWR* or HSEL* inactive or TSS901EADR invalid 2)
HDATA setup before HSEL* or HWR* high or TSS901EADR ≠ TSS901EID
HDATA hold after HWR* or HSEL* inactive or TSS901EADR invalid 2)
16
2.5 * tCLK + 24
12
1 * tCLK + 5
5
0
21
TSS901E
Rev. C – 24-Aug-01
TSS901E
COMI Read
tCRCH
tCRCA
CLK
tCRPW
CMCS0
CMCS1
tCRCH
tCRCA
tCRPW
CMRD
CMWR
tCRPW
tCRCA
tCRCA
Addr. Valid
Addr. Valid
Addr. Valid
CMADR
CMDATA
tCRDS
tCRDH
tCRDS tCRDH
Description
Symbol
tCRCA
Min.
Max.
Unit
ns
CMCS0*, CMCS1* and CMRD* low and CMADR valid after CLK high
CMCS0*, CMCS1* or CMRD* high after CLK high
18
18
tCRCH
ns
CMCS0*, CMCS1*, CMRD*, CMADR pulse width
tCRPW
tCLK - 1
4
ns
CMDATA setup before CMCS0* or CMCS1* or CMRD* high or new address
on CMADR
tCRDS
ns
ns
CMDATA hold after CMCS0* or CMCS1* or CMRD* high or new address on
CMADR
tCRDH
0
22
Rev. C – 24-Aug-01
COMI Write
tCWCH
tCWCA
CLK
tCWPW
CMCS0
CMCS1
CMWR
tCWCH
tCWCA
tCWPW
CMRD
tCWCA
Addr. Valid
Addr. Valid
CMADR
Data Valid
Data Valid
CMDATA
tCWDE
tCWDS
tCWDH
Description
Symbol
tCWCA
tCWCH
tCWPW
tCWDE
tCWDS
tCWDH
Min.
Max.
Unit
ns
CMCS0*, CMCS1* and CMWR* low and CMADR valid after CLK high
CMCS0*, CMCS1* or CMWR* high after CLK high
CMCS0*, CMCS1*, CMWR* pulse width
18
18
ns
tCLK - 1
ns
CMDATA valid after CLK high
15
CMDATA valid before CMCS0* or CMCS1* or CMWR* high
CMDATA hold after CMCS0* or CMCS1* or CMWR* high
25
ns
ns
tCLK/2 + 18
23
TSS901E
Rev. C – 24-Aug-01
TSS901E
COMI Arbitration
Description
COM Interface disable after CLK low
Symbol
tCAID
Min.
Max.
23
Unit
ns
COM Interface enable after CLK high
COCI setup before CLK low
COCO low after CLK low
tCAIE
22
ns
tCOCIS
tCOCOL
tCOCOH
tCOCOW
2
ns
11
11
ns
COCO high after CLK high
COCO pulse width 3)
ns
N - 1 tCLK
ns
Note:
3) N = content of COMI_ACR
24
Rev. C – 24-Aug-01
CPUR, SES, Interrupt
CLK
tOUTC
CPUR
SESx
HINTR
Description
Symbol
Min.
Max.
Unit
CPUR*, SESx*, HINTR* delay after CLK high
tOUTC
22
ns
Links
tLBITP
LSOx
LDOx
tLOUT
tLOUT
LDIx
tLDSI
tLDSI
LSIx
Description
Symbol
tLBITP
Min.
Max.
Unit
ns
Bit Period
4
LDOx, LSOx output skew
Data/Strobe edge separation
tLOUTS
tLDSI
0.5
ns
1
ns
25
TSS901E
Rev. C – 24-Aug-01
TSS901E
Test Port (JTAG)
tTCK
TCK
tTCKH
tTCKL
tTIS
tTIH
TMS
TDI
tTDO
TDO
tTRST
TRST
tSYSS tSYSH
INPUTS
tSYSO
OUTPUTS
Description
Symbol
Min.
100
40
40
8
Max.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TCK period
tTCK
tTCKH
tTCKL
tTIS
TCK width high
TCK width low
TMS, TDI setup before TCK high
TMS, TDI hold after TCK high
TDO delay after TCK low
TRST* pulse width
tTIH
8
tTDO
17
27
tTRST
tSYSS
tSYSM
tSYSO
2 * tTCK
TSS901E Inputs setup before TCK high
TSS901E Inputs hold after TCK high
TSS901E Outputs delay after TCK low
8
8
Note:
The BSDL file is printed in the Annex of this document.
26
Rev. C – 24-Aug-01
Mechanical Data
Package Dimensions
MQFPL 196
Code: FX
Date:13/10/00
27
TSS901E
Rev. C – 24-Aug-01
TSS901E
Pin Assignment
Pin Number
Name
Pin Number
67
Name
HDATA18
Pin Number
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
Name
1
VCC
GND
GND
CLK
CMDATA8
2
68
HDATA19
HDATA20
HDATA21
HDATA22
HDATA23
VCC
VCC
3
69
GND
4
70
CMDATA9
CMDATA10
CMDATA11
CMDATA12
CMDATA13
CMDATA14
VCC
5
RESET*
CLK10
71
6
72
7
HOSTBIGE
TCK
73
8
74
GND
9
TMS
75
HDATA24
HDATA25
HDATA26
VCC
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
TDI
76
TRST*
77
GND
TDO
78
CMDATA15
CMDATA16
CMDATA17
CMDATA18
CMDATA19
CMDATA20
VCC
VCC
79
GND
GND
80
HDATA27
HDATA28
HDATA29
VCC
HSEL*
81
HRD*
82
HWR*
83
HACK
84
GND
HINTR*
VCC
85
HDATA30
HDATA31
CPUR*
SES0*
GND
86
CMDATA21
CMDATA22
CMDATA23
VCC
GND
87
HADR0
HADR1
HADR2
HADR3
HADR4
HADR5
HADR6
HADR7
VCC
88
89
SES1*
90
SES2*
GND
91
SES3*
CMDATA24
CMDATA25
CMDATA26
VCC
92
CAM
93
COCI
94
COCO
95
CMCS0*
CMCS1*
VCC
GND
96
CMDATA27
CMDATA28
CMDATA29
CMDATA30
CMDATA31
NC
GND
97
BOOTLINK
TSS901EADR0
TSS901EADR1
TSS901EADR2
TSS901EADR3
TSS901EID0
TSS901EID1
TSS901EID2
TSS901EID3
VCC
98
GND
99
CMRD*
CMWR*
CMADR0
CMADR1
CMADR2
CMADR3
CMADR4
VCC
100
101
102
103
104
105
106
107
108
109
110
NC
NC
NC
NC
VCC
GND
GND
GND
CMADR5
CMADR6
CMADR7
GND
HDATA0
HDATA1
LEN1
LDI1
28
Rev. C – 24-Aug-01
Pin Number
Name
HDATA2
Pin Number
111
Name
CMADR8
Pin Number
177
Name
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
LSI1
HDATA3
HDATA4
HDATA5
HDATA6
VCC
112
CMADR9
CMADR10
CMADR11
VCC
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
LDO1
LSO1
LDI2
113
114
115
LSI2
116
GND
LEN2
VCC
GND
117
CMADR12
CMADR13
CMADR14
CMADR15
CMDATA0
CMDATA1
CMDATA2
VCC
HDATA7
HDATA8
HDATA9
HDATA10
HDATA11
VCC
118
VCC
119
VCC
120
LDO2
LSO2
LDI3
121
122
123
LSI3
GND
124
LDO3
LSO3
LEN3
GND
GND
VCC
HDATA12
HDATA13
HDATA14
HDATA15
HDATA16
HDATA17
VCC
125
GND
126
CMDATA3
CMDATA4
CMDATA5
VCC
127
128
129
130
GND
PLLOUT
131
CMDATA6
CMDATA7
GND
132
29
TSS901E
Rev. C – 24-Aug-01
TSS901E
Ordering Information
Part-number
TSS901EMA-E
TSS901EAM
Temp. Range
25°C
Package
MQFPL 196-pin
MQFPL 196-pin
MQFPL 196-pin
MQFPL 196-pin
MQFPL 196-pin
MQFPL 196-pin
MQFPL 196-pin
MQFPL 196-pin
Die
Quality Flow
Engineering sample
MIL
-55°C +125°C
-55°C +125°C
-55°C +125°C
-55°C +125°C
-55°C +125°C
-55°C +125°C
-55°C +125°C
25°C
5962-01A1701QXC
TSS901EA/883(*)
TSS901EASC
QML-Q
/883S Class B
SCC 9000 level C
QML-V
5962-01A1701VXC
TSS901EASB
SCC 9000 level B
/883S Class S
Engineering sample
QML-Q
TSS901EAS/883(*)
TSS901EMC-E
5962-01A1701Q9A
5962-01A1701V9A
-55°C +125°C
-55°C +125°C
Die
Die
QML-V
(*) Contact factory
30
Rev. C – 24-Aug-01
Atmel Wireless & Microcontrollers Sales Offices
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Tel: 85223789 789
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Tel: 468587 48 800
Fax: 468587 48 850
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Germany
Tel: 49893 19 70 0
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Web site
http://www.atmel-wm.com
© Atmel Nantes SA, 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
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