TSSIO16E-TIRA [ATMEL]
暂无描述;
ATMEL 
1. Features
• Management of 16 inputs-outputs (16-bit or two 8-bit configurable ports)
• VAN protocol V4.0
• 3 external wired address
• Safety mode in case of transmission loss
• Automatic adaptation to speed of bus from 8kTS/s to 250kTS/s
• CMOS 0,5μm, IO CMOS TTL compatible
• Internal power-on-reset
• Internal ring oscillator from 10 to 40MHz (for internal clock)
• 500kHz oscillator with external RC network (for safety mode clock usage)
• Supply voltage 5V±10%
• Typical power consomption 4mA
• SO28 package
VAN Peripheral
Circuit
16 Inputs-Outputs
TSSIO16E
Rev. 4421B–ASSP–10/05
2. General Description / Block Diagram
The block diagram given below shows the organization of the circuit as two blocks: the VAN con-
troller (block 1), and the groups of specific functions (block 2) relative to the TSSIO16E. These
are based on management of 16 inputs-outputs grouped together to form two 8-bit bi-directional
programmable ports: port A and port B. The circuit thus ensures double exchange of informa-
tion with the VAN bus (via the line interface) on the one hand and the active environment on the
other.
The bus data is supplied to the circuit (after shaping by the line transmitter/receiver) through 3
input lines RXD0, RXD1 and RXD2 selected one after another when communication on one of
the lines is defective (line diagnosis system). Operation outside of the RXD0 line is referred to
as in degrated mode. If perturbations persist in reception the circuit switches to the safety
mode (INT = 1) which, by default, ensures safety functions by activating or inhibiting external cir-
cuitry. Two CONTROL and STATUS 8-bit registers, are used respectively for setting operation
to a given configuration, and for diagnosing the state of the circuit.
The write and read modes of ports A and B are determined by decoding the local address of the
identifier field in the VAN frame.
The behaviour of each port can be configured by three registers: DATA, DDR (Data Direction
Register) and OPT (Option Register).
External address decoding by 3 pins produces 8 TSSIO16E circuits on the same bus.
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TSSIO16E
4421B–ASSP–10/05
TSSIO16E
3. Pinout / Package
The pinout of the circuit is given below.
pin
name
I/O
description
13, 14, 15, 16,
17, 18, 19, 20
PA[0..7]
I/O
Port A, 8 bi-directional bits, TTL compatible, Schmitt trigger
22, 23, 24, 25,
26, 27, 28, 1
PB[0..7]
H500
I/O
I/O
I
Port B event type, 8 bi-directional bits, TTL compatible, Schmitt trigger
Safety mode clock connection to ground or connection of a RC dipole for
500kHz oscillator.
2
3
In application, this input is tied to 1. In test mode, this input is tied to 0. TTL
compatible with pull-up.
TSTb
4
5
6
AD1
AD2
AD3
I
I
I
External wired address - TTL compatible.
Receives output of comparator controlled by the Data signal from the
interface circuit. TTL compatible
7
8
RXD1
RXD2
RXD0
INT
I
I
I
Receiving the output of the comparator driven by the Data_B signal of
the interface circuit. TTL compatible.
Receives the comparator output driven by the differential (Data signal -
Data_B).of the interface circuit. TTL compatible.
9
Interrupt. Used to generate an external active safety mode. TTL
compatible.
12
O
O
11
10
21
TXD
VSS
VDD
Drives the line interface circuit. TTL compatible.
Ground.
External power supply.
The package is SO28.
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4421B–ASSP–10/05
4. Functional Features
4.1 Content of Identifier Field
The TSSIO16E circuit identifier field is structured as shown below.
External wired address
Identifier field
(undecoded)
Local address
The local address consists of bits I1, I2 and I3 of the identifier field for the VAN frame addressing
the circuit, the Bit I1 indicates reading or writing. The table below gives the significance of these
bits.
I3
0
0
0
0
1
1
1
1
I2
0
0
1
1
0
0
1
1
I1
0
1
0
1
0
1
0
1
local address
action
writing of VAN CONTROL register
reading of VAN STATUS register (RANK 16)
writing of port A
0
1
2
3
4
5
6
7
reading of port A (RANK 16)
writing of port AB
reading of port AB (RANK 16)
writing of port B
reading of port B (RANK 16)
4.2
Addressing of ports A and B and of COMMAND and STATUS registers
The specific functions of the circuit are activated by the selection of one or two ports depending
on the local address decoding (see § 4.1) as contained in the identifier field of the VAN frame
received by the circuit and by the content of the data bytes for this frame.
4.2.1
Local address 0 and 1
I3
0
I2
0
I1
0
Writing of the COMMAND register
Reading of the STATUS register
0
0
1
Writing and reading of these registers are described in paragraph 4.4.
The writing of the COMMAND register uses a single data byte. The reading of the STATUS reg-
ister sends a data byte to RANK 16.
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TSSIO16E
4421B–ASSP–10/05
TSSIO16E
4.2.2
Local address 2 and 3
I3
0
I2
1
I1
0
Writing of port A
The writing of port A must be carried out with 1, 2 or 3 data bytes, otherwise the frame will not be
acknowledged and not taken into consideration. If writing uses a single byte, the port will be set
as output and output the DATA_A value. The automobile environment is thus affected by inter-
ference (possibility of deprogramming), it is advisable to write to ports A and B systematically
using 3 bytes.
DATA_A
or
DATA_A
DDR_A
or
DATA_A
DDR_A
OPT_A
DATA_A :
DDR_A :
OPT_A :
Output byte value for port A.
Defines, bit by bit, the direction of the I/O pins for port A (0 = input, 1 = output).
Unused register, this register must be forced to 0.
I3
I2
1
I1
Reading of port A
0
1
A read frame RANK16 at local address 3 recovers the data byte present on port A wether the
direction is input or output.
4.2.3
Local address 4 and 5
I3
1
I2
0
I1
0
Writing of port A and B
A write frame for port A and B contains 6 bytes. The management of the DATA, DDR and OPT
bytes is the same as in the case of port A alone.
DATA_A
DDR_A
OPT_A
DATA_B
DDR_B
OPT_B
OPT_B register must be forced to 0.
I3
1
I2
0
I1
1
Reading of port A and B
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4421B–ASSP–10/05
A read frame (RANK 16) at local address 5 recovers of two data bytes present on port A and B
wether the direction is input or output.
4.2.4
Local address 6 and 7
I3
1
I2
1
I1
0
Writing of port B
In the same way as for port A, port B is write-accessible by frames 1, 2 or 3 data bytes.
I3
1
I2
I1
1
Reading of port B
1
The read mechanism for port B is identical to that of port A.
4.3
Programming and Structure of port A and B
Table below summarizes the programming of a port for the corresponding bits in the DATA,
DDR and OPT bytes, and shows the structural organization of the logic ports.
OPT_X(n)
DDR_X(n)
DATA_X(n)
programming of pin n of port X
logic input
0
0
0
0
1
0
0
1
1
X
0
1
0
1
X
forbidden case (even input)
logic output set to 0
logic output set to 1
forbidden case
bi-directional access
B
B
PA[n]
PB[n]
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TSSIO16E
4421B–ASSP–10/05
TSSIO16E
4.4
COMMAND and STATUS registers
These two specialized registers ensure command and monitoring functions as follows:
• Lines management according to a line diagnosis carried out constantly. This line diagnosis
analyzes the transmission state and allows a choice of the RXD0, RXD1, RXD2 inputs
depending on some of the TIME-OUT’s (STO, MTO, LTO and SLTO);
• Accesses management to common peripherals shared by several circuits.
These registers have the following structure:
Protection bit or occupation flag
Surveillance or mode bit
User module number
Selection/status input lines
4.4.1
Management of RXD0, RXD1, RXD2 lines and common access to peripherals
The purpose of line diagnosis is to find a line that operates before exiting from NORMAL mode
to enter SAFETY mode. This diagnosis is covered by events or TIME-OUT’s with which the
time-out’s are associated.
Short time-out: the bus remains in a dominant state for a period of time incompatible with the definition of
STO
the frames.
MTO
LTO
Medium time-out: absence of coherent frame on VAN bus
Long time-out: no coherent frame addressing the circuit
Super long time-out: 4×TOL
SLTO
The duration of the time-out depends from the internal oscillator which varies in a ratio of 1 to 5.
The implementing of the 500kHz external RC oscillator dedicated to the safety mode permits
more accurate time delays, for example: Rext = 8.66kΩ± 5% and Cext = 1nF±5%. The toler-
ances on R and C include all drifts (temperature, ageing...).
relative
duration
T/16
500 kHz external oscillator
min
typ
62.5
250
max
min
13
typ
62.5
250
max
132
STO (ms)
MTO (ms)
LTO (ms)
SLTO (ms)
30
200
900
2700
75
T/4
300
90
525
T
1000
4000
1150
4650
400
1200
1000
4000
2100
8400
4×T
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4421B–ASSP–10/05
4.4.1.1
Line diagnosis operation
The below shows the mechanism for changing to the safety mode. Exit from the safety mode
must be managed by the application.
after RESET
7 transitions on RXi
STO or MTO or LTO
coherent frame
VAN bus
conform
definitions' frame
STO or MTO or LTO
STO
STO
7 transitions on RXi
normal or
degraded mode
SLTO
STO
LTO
SAFETY mode
7 transitions on RXi
STO or MTO or LTO
Note: FR7 status corresponds to the detection of an activity on the lines.
Bits B0, B1 and B2
4.4.1.2
The 3 low significant bits of the COMMAND register define the input line and its mode of use.
The 3 low significant bits of the STATUS register inform about the componant’s status (line
selected by the application) and the possibility of using other lines.
B
2
B
1
B
0
input line selection mode
COMMAND register
input line selection status
STATUS register
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
automatic, initialized on RXD0
automatic, initialized on RXD1
automatic, initialized on RXD2
automatic transparent mode
forced to RXD0
RXD0 / triple sampling incorrect
RXD1 / triple sampling incorrect
RXD2 / triple sampling incorrect
triple sampling incorrect
RXD0 / triple sampling correct
RXD1 / triple sampling correct
RXD2 / triple sampling correct
triple sampling correct
forced to RXD1
forced to RXD2
forced to RXD0 with RXD0 = RXD1 = RXD2
• Automatic mode
RDXi:
successive use of lines RXD0, RXD1, RXD2, starting from RDXi.
• Automatic
Transparent mode:
• Forced mode:
no effect on line selection mode, allows modification of bits from
B7 to B3 without modifying the selected line
line unchanged in spite of presence of TIME-OUT.
The "triple sampling correct" function (RXD0 = RXD1 = RXD2) is defined by the logic condition:
E = (RXD0 x RXD1 x RXD2) + (/RXD0 x /RXD1 x /RXD2)
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TSSIO16E
4421B–ASSP–10/05
TSSIO16E
4.4.1.3
Bit B3
Bit B3 is used for activating or inhibiting line surveillance.
B3
0
COMMAND
STATUS
active surveillance
inhibited surveillance
circuit in NORMAL mode
circuit in SAFETY mode
1
Active surveillance: default status.
Inhibited surveillance: no more possibility to switch safety mode. Then, INT pin delivers an inter-
ruption at the end of each identified frame adressing the system.
14/16 TS
RXDi
INT
1 TS
4.4.1.4
Bits B4, B5, B6 and B7
Bits B6, B5 and B4 form an address giving the user module number (see example below). Bit
B7 is a protection bit which enables or disables access to the peripheral.
B
7
B
6
B
5
B
4
COMMAND
STATUS
0
The peripheral becomes free of access
The peripheral is free of access
The peripheral becomes busy with a
module
module
The peripheral is busy with a module
of address B6 B5 B4
1
which address is B6 B5 B4
Note: whatever the status mode, it is always possible to write into the command register.
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4421B–ASSP–10/05
Example: Case of a LCD display with a TSSIO16E shared simul-
taneously by car radio and vehicle computer. In this case, the car
radio (B7 = 1) inhibits access to the display line until the full mes-
sage is displayed.
VAN lines
VAN lines
car radio
This access control strategy is only meaningful if the computer
(car radio or on-board computer) wants access to the peripheral
(display) and reads the control register to ensure that the periph-
eral is available. Writing to the port is never inhibited.
LCD display with TSSIO16E
vehicle computer
4.5
State on power on and safety mode
power-on
high Z
high Z
0
safety mode
high Z
Port A
Port B
INT pin
unchanged
1
This table indicates the state of ports A and B and the INT pin on power on and changeover to
the safety mode. In power on mode the command register is initialized to 0.
• selection of RDX0 acces in automatic mode,
• line diagnosis activated,
• access free peripheral.
4.5.1
Condition for enter in safety mode (see Figure )
• After reset:
• During operation:
in the absence of writing or reading in the circuit for a SLTO
in the presence of coherent frames but the absence of reading or writing in the circuit for a LTO
4.5.2
Condition for exit from safety mode
Writing of port A is a way of exiting from the safety mode. Pin INT returns to 0.
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TSSIO16E
4421B–ASSP–10/05
TSSIO16E
5. Wiring of pin H500 (safety mode clock)
After reset and 32 clock periods, the safety mode
clock switches automaticaly from internal oscillator to
external clock H500.
For greater precision on safety mode temporarisa-
tions and on line diagnosis, connect a RC dipole.
Ex: (Rext = 8.66kΩ and Cext = 1nF) to pin H500 in
accordance with opposite figure. It must be con-
nected to ground in case it’s not used.
6. Electrical Characteristics
6.1
Consumption
The consumption in the -40°C / +125°C range, whatever the VAN speed is, is given in the follow-
ing table:
symbol
description
typ
4
max
unit
test conditions
VDD = 5V
IDD
power supply current
12
mA
ports A and B not loaded
6.2
I/O’s Description
The electric characteristics of the inputs-outputs are specified below. They are given for
VDD = 5V±10% in the -40°C / +125°C temperature range.
CMOS input buffer TTL compatible with pull-up (PWDF123IOTST)
pins
A
B
see protection in § 5.3
R24K
L
H
Hi-
Z
L
H
H
TSTb
DC Characteristics
symbol
VIL-TTL
VIH-TTL
description
min
max
unit
V
test conditions
Input Low Voltage
Input High Voltage
0.8
Vcc=4.5V
Vcc=5.5V
2.2
V
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4421B–ASSP–10/05
CMOS input buffer TTL compatible with pull-up (PWDF123IOTST)
pins
IIL
A
B
Input leakage at Low level
Input leakage at High level
137
400
13
μA
μA
Vcc=5.5V
Vcc=5.5V
IIH
During 500ms max
during 5 ms max
and DC = 1 mA
±2.5
±5
mA
mA
Transitory overcurrent of 1/10 of
time
Isur
CMOS input/output buffer TTL compatible (PWDF000IOTST)
pins
C
EN
A
B
L
H
Hi-
Z
L
H
X
X
X
L
L
L
L
H
H
L
H
X
L
PA[7..0]
PB[7...0]
H
H
A
B
L
H
L
H
RxD[2...0]
AD[3...1]
INT
A
B
L
H
L
H
TXD
EN
A
B
Hi-Z
K
L
H
H
L
H
L
H
12
TSSIO16E
4421B–ASSP–10/05
TSSIO16E
DC Characteristics
min
symbol
VIL_TTL
VIH_TTL
description
max
unit
V
test conditions
Vcc=4.5V
Input low Voltage
Input high Voltage
0.8
2.2
2.4
V
Vcc=5.5V
0.4
0.6
V
V
IOL=3mA
IOL=6mA
VOL
Output low Voltage
Output high Voltage
VOH
IIL
V
IOH=6mA
Vcc=5.5V
Vcc=5.5V
Vcc=5.5V
Vcc=5.5V
Input Leakage at low level
Input Leakage at high level
5
5
5
5
μA
μA
μA
μA
IIH
IOZL
IOZH
Output Leakage in High Z in Low level
Output Leakage in High Z in High level
max duration: 1 sec
EN=H
short-circuit current
48
36
mA
mA
IOS
IOSN
IOSP
Vout=Vcc
Vout=Vcc
Vss-
0.5
Vcc+0
.5
V
tension area transitorily tolerated
V
during 500 ms max.
during 5 ms max.
and DC = 1 mA
±2.5
±5
mA
mA
Isur
transitory over current of 1/10 of time
RC 500kHz oscillator (PWDOSC500C5V)
pins
E
A
O
Fou
T
L
X
H
L
L
H500
L
H
H
AC/DC Characteristics
min
400
-40
400
40
typ
max
1200
+125
600
unit
μA
oC
kHz
%
test conditions
Current consomption
Temperature range
Oscillator frequency range
Cyclic ratio range
500
50
Rext = 8.66kΩ, Cext = 1nF
60
E = High
13
4421B–ASSP–10/05
6.3
Internal Clock
The internal clock is the main clock which controls all the state machines. It can be the safety
mode clock if the external clock H500 is connected to ground. It is generated by a ring oscillator
which frequency is given by this table:
min
typ
Max
Temperature
Frequency
-40oC
10Mhz
25oC
125oC
40Mhz
22Mhz
6.4
Diagram of Input Protections
The protections types are:
1kohm
The triac T1 is activated by the
substract current of transitor T2
when the pad tension strongly
increases (ESD pulse).
14
TSSIO16E
4421B–ASSP–10/05
TSSIO16E
7. Operating Environment
7.1
Power Supply Voltage
• Nominal power supply voltage:5V
• Operating power supply voltage:5V±10%
• Extreme power supply voltages not causing destruction:-0.5V / +6V
7.2
Temperature Range
• Operating temperature:-40°C / +125°C
• Storage temperature:-65°C / +150°C
7.3
7.4
Electrostatic Discharge
• ESD protection (according to method AEC-Q100-002 rev C):±±2kV
Overvoltages
Latch-up
The inputs-outputs are protected internally against overshoot and undershoot by clamping
diodes.
7.5
7.6
Inputs-outputs are immunized to latch-up according to IEA/JESD78 norm (equivalent to AEC-
Q100-004rev C). The maximum injected garanteed power is 50mW.
Shortcuts
The outputs are protected against shortcuts for a maximal period of 1 second.
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4421B–ASSP–10/05
8. Typical Application
8.1
Examples of use
8.1.1
Headlight control (writing of port PA5)
Frame sent by central processing unit:
I11 I10
I9
X
I8
1
I7
1
I6
1
I5
1
I4
1
I3
0
I2
1
I1
0
I0 EXT
R/W RTR
5
4
0
5
1
4
X
X
1
1
0
0
1
0
IDEN
COM
DATA_A
DDR_A
8.1.2
Blinkers status (reading of port PB2 - transmission RANK 16)
The TSS IO16E takes over on RTR bit of the COM field:
I11 I10
I9
X
I8
X
I7
1
I6
1
I5
1
I4
1
I3
0
I2
1
I1
0
I0 EXT
R/W RTR
X
X
1
1
1
1
frame transmitted by the master
IDEN
COM
2
1
in frame response
0
DATA_B
16
TSSIO16E
4421B–ASSP–10/05
TSSIO16E
8.2
Circuit Diagram
+12V
1k
TSSIO16E
1.5k
hood contact
+12V
+5V
Side position Lights
Lignes
transmitter/
receiver
Blinkers
Stop fog lights
Horn
High beam headlights
passive back-up
Low beam headlights
+12V
+5V
Position light
active
Notes: 1. The use of the INT pin defines the application status in safety mode
2. INT can only work on port A (configured for high impedance in safety mode)
3. The unused ports PAx and PBx must be connected to ground or to Vcc via a serial resistance
in order to polarize those inputs and avoid a conflict (Shortcut) in case of an output
configuration.
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4421B–ASSP–10/05
9. Ordering Information
TSSIO16E-TISA
SO28 package
TSSIO16E-TIRA
TSSIO16E-TISZ
TSSIO16E-TISZ
SO28 package Tape and Reel
SO28 package Green
SO28 package Tape and Reel Green
18
TSSIO16E
4421B–ASSP–10/05
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