TSX88915TCRD/T70_技术文档

TS88915T

LOW SKEW CMOS PLL CLOCK DRIVER

3-State 70 and 100 MHz Versions

DESCRIPTION

The TS88915T Clock Driver utilizes a phazed–locked loop

(PLL) technology to lock its low skew outputs’ frequency and

phase onto an input reference clock. It is designed to provide

clock distribution for high performance microprocessors such

as TS68040, TSPC603E,TSPC603P,TSPC603R, PCI bridge,

RAM’s, MMU’s...

MAIN FEATURES

H Vcc = 5V ꢀ 5 %

H MILITARY TEMPERATURE RANGE

H TS68040 FULL COMPATIBLE

H FIVE LOW SKEW OUTPUTS

Five Outputs (Q0-Q4) with Output–to–Output skew < 500

ps each being phase end frequency locked to the SYNC

input.

R Suffix

PGA 29

Ceramic Pin grid array

H ADDITIONAL OUTPUTS

Three additional outputs are available :

– The 2X_Q output runs twice the system ”Q” frequency.

– The Q/2 output runs at 1/2 the system ”Q” frequency.

– The Q5 output is inverted (180° phase shift).

H TWO SELECTABLE CLOCK INPUTS

– Two selectable CLOCK inputs are available for test or

redundancy purposes.

– Test Mode pin (PLL_EN) provided for low frequency test-

ing.

– All outputs can go into high impedance (3-state) for board

test purpose.

H INPUT FREQUENCY RANGE FROM 5MHz to 2X_Q

FMAX

H THREE INPUT/OUTPUT RATIOS

Input/Output phase–locked frequency ratios of 1:2, 1:1 and

2:1 are available.

H LOW PART-TO-PART SKEW

The phase variation from part–to–part between the SYNC

andFEEDBACKinputsislessthan550ps(derivedfromthe

W suffix

LDCC 28

Leaded Ceramic Chip Carrier

t_PDspecification, which defines the part-to-part skew).

H CMOS AND TTL COMPATIBLE

– All outputs can drive either CMOS or TTL inputs.

– All inputs are TTL-level compatible.

H LOCK Indicator (LOCK) indicated a phase–locked

state.

SCREENING / QUALITY

This product is manufactured :

H based upon the generic flow of MIL–STD–883.

H or according to TCS standard.

April 1999

1/20

TS88915T

SUMMARY

4. ELECTRICAL CHARACTERISTICS . . . . . . . . . . . 7

A. GENERAL DESCRIPTION . . . . . . . . . . . . . . 3

1. INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

2. PIN ASSIGNMENTS . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1. 29-Lead Pin Grid Array (PGA) . . . . . . . . . . . . 4

4.1. General requirements . . . . . . . . . . . . . . . . . . . 7

4.2. Static characteristics . . . . . . . . . . . . . . . . . . . . 7

4.2.1. DC electrical characteristics . . . . . . . . 7

4.2.2. Capacitance and power specifications 8

2.2. 28-Lead Ceramic Leaded Chip Carrier

(LDCC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

4.3. Dynamic characteristics . . . . . . . . . . . . . . . . . 8

4.3.1. Frequency applications . . . . . . . . . . . 8

4.3.2. SYNC input timing requirements . . . 8

4.3.3. AC characteristics . . . . . . . . . . . . . . . . 8

3. SIGNAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . 5

B. DETAILED SPECIFICATIONS . . . . . . . . . . . 6

1. SCOPE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

2. APPLICABLE DOCUMENTS . . . . . . . . . . . . . . . . . 6

3. REQUIREMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

3.1. General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6

5. APPLICATION INFORMATION . . . . . . . . . . . . . . 11

5.1. General AC specification notes . . . . . . . . . . 11

5.2. Timing notes . . . . . . . . . . . . . . . . . . . . . . . . . . 14

5.3 Notes concerning loop filter and board layout

issues . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

5.4. TS88915T system level testing functionality17

6. PREPARATION FOR DELIVERY . . . . . . . . . . . . . 17

6.1. Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

6.2. Certificate of compliance . . . . . . . . . . . . . . . . 17

7. HANDLING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

8. PACKAGE MECHANICAL DATA . . . . . . . . . . . . 18

9. ORDERING INFORMATION . . . . . . . . . . . . . . . . . 19

3.2. Design and construction . . . . . . . . . . . . . . . . . 6

3.2.1. Terminal connections . . . . . . . . . . . . . 6

3.2.2. Lead material and finish . . . . . . . . . . . 6

3.2.3. Package . . . . . . . . . . . . . . . . . . . . . . . . 6

3.3. Electrical characteristics . . . . . . . . . . . . . . . . . 6

3.4. Mechanical and environment . . . . . . . . . . . . . 7

3.5. Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2/20

TS88915T

A. GENERAL DESCRIPTION

1. INTRODUCTION

The TS88915T is a CMOS PLL Clock Driver using phase–locked loop (PLL) technology. The PLL allows the high current, low skew

outputs to lock onto a single input and distribute it with essentially zero delay to multiple components on a board. The PLL also allows

the TS88915T to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. Multiple 88915’s can

lock onto a single reference clock, which is ideal for applications when a central system clock must be distributed synchronously to

multiple boards (see Figure 12).

Figure 1 shows TS88915T block diagram.

FEEDBACK

LOCK

SYNC[0]

0

VOLTAGE

CONTROLLED

OSCILLATOR

PHASE/FREQ.

DETECTOR

CHARGE PUMP/

LOOP FILTER

M

U

X

SYNC[1]

1

EXT. REC NETWORK

(RC1 pin)

REF_SEL

0

1

2X_Q

Q0

PLL_EN

MUX

D

Q

(+1)

(+2)

CP

1

0

R

M

U

X

DIVIDE

BY TWO

D

Q1

Q2

Q

CP

R

FREQ_SEL

OE/RST

D

Q

CP

D

Q3

Q4

Q

CP

R

D

Q

CP

D

Q

Q5

CP

D

Q/2

Q

CP

Figure 1 : TS88915T Block Diagram

(All versions)

3/20

TS88915T

2. PIN ASSIGNMENTS

2.1. 29-Lead Pin Grid Array (PGA)

F

E

D

C

B

A

Q0

VCC

Q1

F/SL

GND

P/EN

GNDA

VCCA

SYC0

SYC1

GND

LOCK

TS88915T

(BOTTOM VIEW)

RC1

GND

Q3

Q2

R/SL

VCC

FDBK

RST

Q5

VCC

Q/2

GND

VCC

2

GND

3

Q4

4

Q*2

5

NC

1

6

Figure 2 : 29-Lead PGA (Bottom View)

2.2. 28-Lead Ceramic Leaded Chip Carrier (LDCC)

OE/RST VCC

Q5

GND

1

Q4

28

VCC

27

2X_Q

26

4

3

2

FEEDBACK

REF_SEL

Q/2

5

6

25

24

GND

SYNC[0]

VCC (AN)

RC1

Q3

7

8

23

22

VCC

TS88915T

(TOP VIEW)

9

Q2

21

20

GND (AN)

SYNC[1]

GND

LOCK

10

11

19

12

13

14

15

16

Q1

17

18

FREQ_SEL GND

Q0

VCC

GND PLL_EN

Figure 3 : 28–Lead LDCC (Top View)

4/20

TS88915T

3. SIGNAL DESCRIPTION

Pin Name

SYNC[0]

SYNC[1]

REF_SEL

FREQ_SEL

FEEDBACK

RC1

Num

I/O

Signal function

1

5

1

11

Input

Reference clock input

Input

Chooses reference between SYNC[0] and SYNC[1]

Doubles VCO internal frequency

Input

Feedback input to phase detector

Input for external RC network

Input

Q(0–4)

Output

Input

Clock output (locked to SYNC)

Q5

Inverse of clock output

2x_Q

2 x clock output (Q) frequency (synchronous)

Q/2

Clock output (Q) frequency B 2 (synchronous)

LOCK

Indicates phase lock has been achieved (high when locked)

Output Enable / Asynchronous reset (active low)

Disables phase–lock for low frequency testing

OE/RST

PLL_EN

VCC, GND

Input

Power

Power and Ground pins

Pins 8 and 10 are ”analog” supply pins for internal PLL only

Table 1 : Signal index

5/20

TS88915T

B. DETAILED SPECIFICATIONS

1. SCOPE

This drawing describes the specific requirements for the clock driver TS88915T, in compliance with MIL-STD-883 class B or TCS

standard screening.

2. APPLICABLE DOCUMENTS

1) MIL-STD-883 : Test methods and procedures for electronics.

2) MIL-PRF-38535 appendix A : General specifications for microcircuits.

3. REQUIREMENTS

3.1. General

The microcircuits are in accordance with the applicable documents and as specified herein.

3.2. Design and construction

3.2.1. Terminal connections

Depending on the package, the terminal connections shall be as shown in Figure 2 and Figure 3 (§ A. GENERAL DESCRIPTION).

3.2.2. Lead material and finish

Lead material and finish shall be as specified in MIL-STD-1835 (see § 8).

3.2.3. Package

The macrocircuits are packaged in hermetically sealed ceramic packages which are conform to case outlines of MIL-STD-1835, but

see § 8

The precise case outlines are described at the end of the specification (§ 8) and into MIL-STD-1835.

3.3. Absolute maximum ratings

Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum

levels may degrade performance and affect reliability.

Parameter

Symbol

Min

–0.5

–65

Max

Unit

V

Supply voltage

Input voltage

V

CC

6.0

V

in

V

+ 0.5

V

CC

Storage temperature range

T

stg

+150

500

°C

Power dissipation

PGA Package

P

D

mW

LDCC package

Thermal resistance Junction–Case

PGA29

LDCC28

Q

–

7

°C/W

JC

Note : Functional operating conditions are given in AC and DC electrical specifications. Stresses beyond the absolute maximums

listed may affect device reliability or cause permanent damage to the device.

Caution:inputvoltagemustnotbegreaterthanthesupplyvoltagebymorethan2.5Vatalltimesincludingduringpower-on

reset.

Table 2 : Absolute maximum rating for the TS88915T

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TS88915T

3.4. Mechanical and environment

The microcircuits shall meet all environmental requirements of either MIL-STD-883 for class B devices or for TCS standard scree-

ning.

3.5. Marking

The document where are defined the marking are identified in the related reference documents. Each microcircuit are legible and

permanently marked with the following information as minimum :

– Thomson logo

– Manufacturer’s part number

– Class B identification

– Date–code of inspection lot

– ESD identifier if available

– Country of manufacturing

4. ELECTRICAL CHARACTERISTICS

4.1. General requirements

All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions aregiven

below:

– Table Static Electrical Characteristics for the electrical variants

– Table Dynamic Electrical Characteristics for TS88915T (70MHz and 100MHz versions)

4.2. Static characteristics

4.2.1. DC electrical characteristics

(Voltages Referenced to GND) T_c= –55°C to +125°C for 70 MHz and 100 MHz version ; VCC= 5.0 V " 5 %

Symbol

Parameter

Minimum High-Level Input Voltage

Maximum Low–Level Input Voltage

Minimum High–Level Output Voltage

Test Conditions

V_out= 0.1 V or V_CC– 0.1 V

Limits

2.0

Unit

V

V_IH

V_IL

0.8

V

V_OH

V_in= V_IHor V_IL, I_OH= -36 mA ^1,V_CCmin

V_CCmax

4.01

4.51

V

V_OL

Maximum Low–Level Output Voltage

V_in= V_IHor V_IL, I_OL= 36 mA ¹

0.44 ⁴

0.50 ⁵

0.20

V

V_in= V_IHor V_IL, I_OL= 15 mA ⁶

V_I= V_CCor GND, V_CCmax

V_I= V_CC- 2.1 V, V_CCmax

I_in

I_CCT

I_CC

I_OZ

Maximum Input Leakage Current

Maximum I_CC/Input

$1.0

2.0 ²

1.0

mA

Maximum Quiescent Supply Current (per package) V_I= V_CCor GND, V_CCmax

Maximum 3–State Leakage Current V_I= V_IHor V_IL,V_O=V_{CC or}GND, V_CCmax

$50

Note 1 : I_OLand I_OHare 12 mA and -12 mA respectively for the LOCK output.

Note 2 : The PLL_EN input pin is not guaranteed to meet this specification.

Note 3 : Maximum test duration is 2.0 ms, one output loaded at a time.

Note 4 : Specification value for static tests at 25°C and at minimum rated operating temperature.

Note 5 : Specification value for static tests at maximum rated operating temperature.

Note 6 : Specifications values which can be used for compability with the Power PC.

7/20

TS88915T

4.2.2. Capacitance and power specifications

Symbol

C_IN

Parameter

Typical values

Unit

pF

Conditions

V_CC= 5.0 V

Input Capacitance

10

40

C_PD

Power Dissipation Capacitance

pF

PD₁

Power Dissipation @ 50 MHz with 50W Thevenin Termina-

tion

23mW/Output

184mW/Device

mW

V_CC= 5.0 V

T = 25°C

PD₂

Power Dissipation @ 50 MHz with 50W Parallel Termination

to GND

57mW/Output

456mW/Device

mW

V_CC= 5.0 V

T = 25°C

Note : PD₁and PD₂mW/Output are for a ’Q’ output.

4.3. Dynamic characteristics (T_c=-55° C to +125° C, V_CC= 5.0 V $ 5%)

4.3.1. Frequency specifications

Guaranteed Minimum

Symbol

Parameter

Unit

88915T–70

88915T–100

1

f_max

Maximum Operating Frequency (2X_Q Output)

70

35

100

50

MHz

Maximum Operating Frequency (Q0–Q4, Q5 Out-

puts)

Note 1 : Maximum Operating Frequency is guaranteed with the part in a phase–locked condition, and all outputs loaded with 50 W

terminated to V_CC/2.

4.3.2. SYNC input timing requirements

Minimum

88915T–70 88915T–100

Symbol

Parameter

Maximum Unit

t_RISE/FALL, SYNC Inputs Rise/Fall Time, SYNC Inputs

From 0.8 to 2.0 V

–

3.0

ns

t_CYCLE, SYNC Inputs

Input Clock Period, SYNC Inputs

Input Duty Cycle, SYNC Inputs

28.5 ¹

20.0 ¹

200 ²

Duty Cycle SYNC

Inputs

50 % $ 25 %

Note 1 : These t_CYCLEminimum values are valid when ’Q’ output is fed back and connected to the FEEDBACK pin.

Note 2 : Informationin Table 1 and in Note 3 of the AC specification notes describe this specification and its limits dependingon what

output is fed back, and if FREQ_SEL is high or low.

8/20

TS88915T

Conditions

4.3.3. AC characteristics (T_c=-55° C to +125° C, V_CC= 5.0 V $ 5%, Load = 50W terminated to V_CC/2)

Symbol

Parameter

Min

Max

Unit

t_RISE/FALL

Outputs

Rise/Fall Time, All Outputs

(Between 0.2V_CCand 0.8V_CC)

1.0

2.5

ns

into a 50W Load

Terminated to

V_CC/2

(1)

t_RISE/FALL

Rise/Fall Time into a 20 PF Load, with

Termination specified in Note ²

0.5

1.6

ns

t_RISE:0.8V – 2.0V

t_FALL:2.0V – 0.8V

2X_Q Output

(1)

t_{PULSE WIDTH}

(Q0–Q4, Q5,

Q/2)

Output Pulse Width: Q0, Q1, Q2, Q3,

Q4, Q5, Q/2 @ V_CC/2

0.5t_CYCLE- 0.5 ²0.5t_CYCLE+ 0.5 ²

into a 50W Load

Terminated to

V_CC/2

t_{PULSE WIDTH}

(2X_Q Output)

Output Pulse Width:

2X_Q @ 1.5V

40 MHz 0.5t_CYCLE- 1.5 ²0.5t_CYCLE+ 1.5 ²

50 MHz

66 MHz

ns

Must use

0.5t_CYCLE- 1.0

0.5t_CYCLE- 0.5

0.5t_CYCLE+ 1.0

0.5t_CYCLE+ 0.5

termination

specified in Note²

100 MHz

(1)

t_{PULSE WIDTH}

Output Pulse Width:

2X_Q @ V_CC/2

40–49 MHz 0.5t_CYCLE- 1.5 ²0.5t_CYCLE+ 1.5 ²

ns

into a 50W Load

Terminated to

V_CC/2

(2X_Q Output)

50–65 MHz

66–100 MHz

0.5t_CYCLE- 1.0

0.5t_CYCLE- 0.5

0.5t_CYCLE+ 1.0

0.5t_CYCLE+ 0.5

(1, 3)

t_PD

SYNC Input to Feedback Delay

(Measured at SYNC0 or 1 and

(With 1MW from RC1 to An V_CC

)

See Note 4 and

Figure 6 for

detailed

SYNC Feedback

FEEDBACK input pins)

70 MHz

–1.05

–0.40

–0.30

explanation

100 MHz

(With 1MW from RC1 to An GND)

+1.25

–

+3.25

500

(1, 4)

t_SKEWr

Output–to–Output Skew between Out-

See puts Q0–Q4, Q/2 (Rising edges only)

ps

All Outputs into a

matched 50W

load Terminated

to V_CC/2

(Rising)

Note ⁵

(1, 4)

t_SKEWf

Output–to–Output Skew between Out-

puts Q0–Q4 (Falling edges only)

–

750

All Outputs into a

matched 50W

load Terminated

to V_CC/2

(Falling)

(1, 4)

t_SKEWall

(Falling)

Output–to–Output Skew 2X_Q, Q/2,

Q0–Q4 Rising, Q5 Falling

All Outputs into a

matched 50W

load Terminated

to V_CC/2

(5)

t_LOCK

Time required to acquire Phase–Lock

from time SYNC inputs signal is

received

1.0

3.0

10

14

ms

ns

Also time to lock

indicator High

t_PZL

Output Enable Time OE/RST to 2X_Q,

Q0–Q4, Q5 and Q/2

Measured with

the PLL_EN pin

Low

t_PHZ, t_PLZ

Output Disable Time OE/RST to 2X_Q,

Q0–Q4, Q5 and Q/2

Measured with

the PLL_EN pin

Low

Note 1 : These specification are not tested, they are guaranteed by statistical characterization. See General AC specification Note 1

.

Note 2 : t_CYCLEin this specification is 1/Frequency at which the particular output is running.

Note 3 : The T_PDspecification’s min/max values may shift closer to zero of a larger pull up resistor is used.

Note 4 : Under equally loaded conditions and at a fixed temperature and voltage.

9/20

TS88915T

Note 5 : With VCC fully powered-on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1 mF,

tLOCK minimum is with C1 = 0.01 mF.

SYNC INPUT

(SYNC[1] or

SYNC[0])

t

SYNC INPUT

CYCLE

t

PD

FEEDBACK

INPUT

Q/2 OUTPUT

t

SKEWr

SKEWall

SKEWf

SKEWr

SKEWf

Q0–Q4

OUTPUTS

t

’Q’ OUTPUTS

CYCLE

Q5 OUTPUT

2X_Q OUTPUT

Figure 4 : Output/Input switching waveforms and timing diagrams

(These waveforms represent the hook-up configuration of Figure 8)

10/20

TS88915T

5. APPLICATION INFORMATION

5.1. General AC specification notes

1. Several specifications can only be measured when th TS88915T is in phase–locked operation. TS88915T units were

fabricated with key transistor properties intentionally varied to create a 14 cell designed experimental matrix.

2. These two specs (t_RISE/FALLand t_{PULSE WIDTH}2X_Q output) guarantee that the TS88915T meets the 33MHz TS68040

P–Clock input specification (at 66MHz). For these two specs to be guaranteed by TCS, the termination scheme shown

below in Figure 5 must be used.

Z0 (CLOCK TRACE)

TS88915

2X_Q

Output

TS68040

P–Clock

Input

Rs

Rp

Rp=1.5Z0

Rs=Z0–7W

Figure 5 : TS68040 P–Clock input termination scheme

3 To meet the 25 MHz TS68040 P–clock input specification (2 x Q tpulse width at 50 Mhz) FREQ–SEL must be low. This

configuration improve the accuracy of the 88915T duty cycle.

4. The wiring diagrams and explanations in Figure 8, 9 and 10 demonstrate the input and output frequency relationships for

three possible feedback configurations. The allowable SYNC input range for each case is also indicated. There are two

allowableSYNC frequency ranges, depending whether FREQ_SEL is high or low. Although not shown, it is possible to feed

back the Q5 output, thus creating a 180° phase shift between the SYNC input and the ”Q” outputs. Table 3 below

summarizes the allowable SYNC frequency range for each possible configuration.

FREQ_SEL

Level

FEEDBACK

Output

Allowable SYNC Input

Frequency Range (MHz)

Corresponding VCO

Frequency Range

Phase Relation-

ships of the ”Q”

Outputs to Rising

SYNC Edge

HIGH

Q/2

any ”Q” (Q0–Q4)

Q5

5 to (2X_Q FMAX Spec)/4

20 to (2X_Q FMAX Spec)

0°

10 to (2X_Q FMAX Spec)/2 20 to (2X_Q FMAX Spec)

180°

0°

2X_Q

20 to (2X_Q FMAX Spec)

LOW

Q/2

any ”Q” (Q0–Q4)

Q5

2.5 to (2X_Q FMAX Spec)/8 20 to (2X_Q FMAX Spec)

0°

5 to (2X_Q FMAX Spec)/4

20 to (2X_Q FMAX Spec)

180°

0°

2X_Q

10 to (2X_Q FMAX Spec)/2 20 to (2X_Q FMAX Spec)

Table 3 : Allowable SYNC input frequency range for different feedback configurations

11/20

TS88915T

5. A 1 MW resistor tied to either Analog V_CCor Analog GND as shown in Figure 5 is required to ensure no jitter is present on the

TS88915T outputs. This technique causes a phase offset between the SYNC input and the output connected to the

FEEDBACK input, measuredattheinputpins. TheT_PDspec describes howthisoffsetvarieswithprocess, temperatureand

voltage. Thespecswerearrivedatbymeasuringthephaserelationshipforthe14lotsdescribedinNote1whilethepartwas

in phase–locked operation. The actual measurements were made with 10MHz SYNC input (1.0ns edge rate from 0.8V –

2.0V) with the Q/2 output fed back. The phase measurements were made at 1.5V. The Q/2 output was terminated at the

FEEDBACK input with 100W to V_CCand 100W to GND.

RC1

EXTERNAL LOOP

FILTER

RC1

1MW

330W

R2

C1

REFERENCE

RESISTOR

R2

C1

330W

0.1mF

1MW

REFERENCE

RESISTOR

ANALOG GND

With the 1MW resistor tied in this fashion, the t specification

measured at the input pins is:

PD

With the 1MW resistor tied in this fashion, the t specification

measured at the input pins is:

PD

t

= –0.775ns $ 0.275ns

PD

t

= 2.25ns $ 1.0ns

PD

3.0V

–0.775ns OFFSET

SYNC INPUT

2.25ns OFFSET

5.0V

FEEDBACK OUTPUT

Figure 6 : Depiction of the fixed SYNC to Feedback offset (t_PD) which is

present when a 1MW resistor is tied to VCC or GND

6. The t_SKEWrspecification guarantees that the rising edges of outputs Q/2, Q0, Q1, Q2, Q3 and Q4 will always fall within a

500ps window within one part. However, if the relative position of each output within this window is not specified, the 500ps

window must be added to each side of the t_PDspecification limits to calculate the total part–to–part skew. For this reason the

absolutedistributionoftheseoutputsareprovidedinTable4. Whentakingtheskewdata, Q0wasusedasareference, soall

measurements are relative to this output. The information in Table 4 is derived from measurements taken from the 14

process lots described in Note 1, over the temperature and voltage range.

–

(ps)

+

(ps)

Output

Q0

Q1

Q2

Q3

Q4

Q/2

2X_Q

0

40

275

255

–34

250

–35

–72

–44

–40

–274

–16

–633

Table 4 : Relative position of outputs Q/2, Q0–Q4, 2X_Q,

within the 500ps t_SKEWrspec window

12/20

TS88915T

7. Calculation of Total Output-to-Output skew between multiple parts (Part-to-Part Skew)

By combining the t_PDspecification and the information in Note 5, the worst case Output-to-Output skew between multiple

TS88915’s connected in parallel can be calculated. This calculation assumes that all parts have a common SYNC input

clock with equal delay that input signal to each part. This skew value is valid at the TS88915 output pins only (equally

loaded), it does not include PCB trace delays due to varying loads.

With a 1 MW resistor tied to analog VCC as shown in Note 4, the t_PDspec. limits between SYNC and the Q/2 output

(connected to the FEEDBACK pin) are –1.05ns and –0.5ns. To calculate the skew of any given output between two or more

parts, the absolute value of the distribution of that output given in Table 4 must be subtracted and added to the lower and

upper t_PDspec limits respectively. For output Q2, [276–(–44)] = 320ps is the absolute value of the distribution. Therefore

[–1.05–0.32]=–1.37nsisthelower t_PDlimit,and[–0.5+0.32]=–0.18nsistheupperlimit. Thereforetheworstcaseskewof

output Q2 between any number of part is [(–1.37)–(–0.18)] = 1.19ns. Q2 has the worst case skew distribution of any output,

so 1.2ns is the absolute worst case Output-to-Output skew between multiple parts.

8. Note 4 explains that the t_PDspecification was measured and is guaranteed for the configuration of the Q/2 output connected

to the FEEDBACK pin and the SYNC input running at 10MHz. The fixed offset (t_PD) as described above has some

dependence on the input frequency and what frequency the VCO is running. The graphs of Figure 6 demonstrate this

dependence.

The data presented in Figure 6 is from devices representing process extremes, and the measurements were also taken at

the voltage extremes (V_CC= 5.25V and 4.75V). Therefore the data in Figure 6 is a realistic representation of the variation of

t_PD

.

–0.50

–0.75

–0.50

–1.00

tPD

SYNC to

FEEDBACK

(ns)

tPD

SYNC to

FEEDBACK

(ns)

–1.00

–1.25

–1.50

–2.00

2.5

5.0

7.5

10.0

12.5

15.0

17.5

2.5 5.0 7.5 10 12.5 15 17.5 20 22.5 25 27.5

SYNC INPUT FREQUENCY (MHz)

tPD versus Frequency for Q/2 output fed back,

including process and voltage variation @ 25°C

(with 1MW resistor tied to analog VCC)

tPD versus Frequency for Q4 output fed back,

including process and voltage variation @ 25°C

(with 1MW resistor tied to analog VCC)

3.5

3.0

2.5

3.5

3.0

2.5

2.0

tPD

SYNC to

FEEDBACK

(ns)

tPD

SYNC to

FEEDBACK

2.0

(ns)

1.5

1.0

0.5

1.5

1.0

0.5

2.5

5.0

7.5

10.0

12.5

15.0

17.5

0

5

10

15

20

25

SYNC INPUT FREQUENCY (MHz)

tPD versus Frequency for Q/2 output fed back,

including process and voltage variation @ 25°C

(with 1MW resistor tied to analog GND)

tPD versus Frequency for Q4 output fed back,

including process and voltage variation @ 25°C

(with 1MW resistor tied to analog GND)

Figure 7 :

9. The Lock indicator pin (LOCK) will reliably indicate a phase–locked condition at SYNC input frequencies down to 10MHz. At

frequencies below 10MHz, the frequency of correction pulses going into the phase detector from the SYNC and

FEEDBACK pins may not be sufficient to allow the lock indicator circuitry to accurately predict a phase–locked condition.

The TS88915T is guaranteed to provide stable phase–locked operation down to the appropriate minimum input frequency

given in Table 3, even though the LOCK pin may be low at frequencies below 10MHz.

13/20

TS88915T

5.2. Timing notes

1. The TS88915T aligns rising edges of the FEEDBACK input and the SYNC input, therefore the SYNC input does not require

a 50% duty cycle.

2. All skew specs are measured between VCC/2 crossing point of the appropriate output edges. All skews are specified as

’windows’, not as a " deviation around a center point.

3. If a ”Q” output is connected to the FEEDBACK input (this situation is not shown), the ”Q” output frequency would match the

SYNC input frequency, the 2X_Q output would run twice the SYNC frequency, and the Q/2 output would run at half the

SYNC frequency.

See Figures 7, 8 and 9 below.

1:2 Input to ”Q” Output Frequency Relationship

100MHz SIGNAL

25MHz FEEDBACK SIGNAL

In this application, the Q/2 output is connected to

HIGH

the FEEDBACK input. The internal PLL will line up

Q5

RST

Q4

2X_Q

Q/2

the positive edges of Q/2 and SYNC, thus the Q/2

frequency will equal the SYNC frequency. The ”Q”

outputs (Q0–Q4, Q5) will always run at 2X the Q/2

frequency, and the 2X_Q output will run at 4X the

Q/2 frequency.

FEEDBACK

LOW

REF_SEL

SYNC[0]

CRYSTAL

OSC.

25MHz INPUT

Q3

Q2

50 MHz

”Q”

CLOCK

ANALOG Vcc

RC1

EXTERNAL

LOOP

FILTER

OUTPUTS

Allowable Input Frequency Range:

ANALOG GND

5 MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL HIGH)

2.5 MHz to (2X_Q FMAX Spec)/8 (for FREQ_SEL LOW)

FQ_SEL

HIGH

Q0

Q1

PLL_EN

HIGH

Note: If the OE/RST input is active, a pull-up or pull-down resis-

tor isn’t necessary at the FEEDBACK pin so it won’t when the

fed back output goes into 3-state.

Figure 8 : Wiring diagram and frequency relationship with Q/2 output fed back

1:1 Input to ”Q” Output Frequency Relationship

100MHz SIGNAL

50MHz FEEDBACK SIGNAL

HIGH

In this application, the Q4 output is connected to

the FEEDBACK input. The internal PLL will line up

the positive edges of Q4 and SYNC, thus the Q4

frequency (and the rest of the ”Q” outputs) will

equal the SYNC frequency. The Q/2 output will

always run at 1/2 the ”Q” frequency, and the 2X_Q

output will run 2X the ”Q” frequency.

Q5

RST

Q4

2X_Q

25MHz

SIGNAL

FEEDBACK

Q/2

Q3

Q2

LOW

REF_SEL

SYNC[0]

CRYSTAL

OSC.

50MHz INPUT

50 MHz

”Q”

CLOCK

ANALOG Vcc

RC1

EXTERNAL

LOOP

FILTER

OUTPUTS

Allowable Input Frequency Range:

ANALOG GND

10 MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL HIGH)

5 MHz to (2X_Q FMAX Spec)/4 (for FREQ_SEL LOW)

FQ_SEL

HIGH

Q0

Q1

PLL_EN

HIGH

Figure 9 : Wiring diagram and frequency relationship with Q4 output fed back

14/20

TS88915T

2:1 Input to ”Q” Output Frequency Relationship

100MHz FEEDBACK SIGNAL

HIGH

In this application, the 2X_Q output is connected

to the FEEDBACK input. The internal PLL will line

up the positive edges of 2X_Q and SYNC, thus the

2X_Q frequency will equal the SYNC frequency.

The Q/2 output will always run at 1/4 the ”Q” fre-

quency, and the ”Q” outputs will run at 1/2 the

2X_Q frequency.

Q5

RST

Q4

2X_Q

Q/2

25MHz

SIGNAL

FEEDBACK

LOW

REF_SEL

SYNC[0]

100MHz INPUT

CRYSTAL

OSC.

Q3

Q2

50 MHz

”Q”

CLOCK

ANALOG Vcc

RC1

EXTERNAL

LOOP

FILTER

OUTPUTS

Allowable Input Frequency Range:

ANALOG GND

20MHz to (2X_Q FMAX Spec) (for FREQ_SEL HIGH)

10MHz to (2X_Q FMAX Spec)/2 (for FREQ_SEL LOW)

FQ_SEL

HIGH

Q0

Q1

PLL_EN

HIGH

Figure 10 : Wiring diagram and frequency relationship with 2X_Q output fed back

5.3. Notes concerning Loop Filter and Board Layout issues

1. Figure 10 shows a loop filter and analog isolation scheme which will be effective in most applications. The following

guidelines should be followed to ensure stable and jitter–free operation:

1a. All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing

through the parasitics of long traces can cause undesirable voltage transients at the RC1 pin.

1b. The 47W resistors, the 10mF low frequency bypass capacitor, and the 0.1mF high frequency bypass capacitor form a wide

bandwidth filter that will minimize the 88915T’s sensitivity to voltage transients from the system digital V_CCsupply and

ground planes. This filter will typically ensure that a 100mV step deviation on the digital V_CCsupply will cause no more than

100ps phase deviation on the 88915T outputs. a 250mV step deviation on V_CCusing the recommended filter values should

cause no more than a 250ps phase deviation; if a 25mF bypass capacitor is used (instead of 1mF) a 250mV V_CCstep should

cause no more than a 100ps phase deviation.

IfgoodbypasstechniquesareusedonaboarddesignnearcomponentswhichmaycausedigitalV_CCandgroundnoise, the

above described V_CCstep deviations should not occur at the 88915T’s digital V_CCsupply. The purpose of the bypass

filtering scheme shown in Figure 10 is to give the 88915T additional protection from the power supply and ground plane

transients that can occur in a high frequency, high speed digital system.

1c. There are no special requirements set forth for the loop filter resistors (1MW and330W). The loop filter capacitor (0.1mF) can

be a ceramic chip capacitor, the same as a standard bypass capacitor.

1d. The 1MW reference resistor injects current into the internal charge pump of the PLL, causing a fixed offset between the

outputs and the SYNC input. This also prevents excessive jitter caused by inherent PLL dead–band. If the VCO (2X_Q

output) is running above 40MHz, the 1MW resistor provides the correct amount of current injection into the charge pump

(2–3mA). For the70and100MHzversions, iftheVCOisrunningbelow40MHz, a1.5MW resistorshouldbeused(insteadof

1MW).

2. In addition to the bypass capacitors used in the analog filter of Figure 10, there should be a 0.1mF bypass capacitor between

each of the other (digital) four V_CCpins and the board ground plane. This will reduce output switching noise caused by the

88915T outputs, in addition to reducing potential for noise in the ’analog’ section of the chip. These bypass capacitors

should also be tied as close to the package as possible.

15/20

TS88915T

BOARD Vcc

47W

ANALOG Vcc

RC1

8

1MW

ANALOG LOOP FILTER/VCO

SECTION OF THE TS88915T

(NOT DRAWN TO SCALE)

0.1mF HIGH

FREQ

BYPASS

330W

10mF LOW

FREQ BYPASS

9

ANALOG GND

10

47W

A SEPARATE ANALOG POWER SUPPLY IS NOT NECESSARY AND

SHOULD NOT BE USED. FOLLOWING THESE PRESCRIBED GUIDE-

LINES IS ALL THAT IS NECESSARY TO USE THE TS88915T IN A NOR-

MAL DIGITAL ENVIRONMENT.

BOARD GND

Figure 11 : Recommended loop filter and analog isolation scheme for the TS88915T

CPU

CARD

CMMU CMMU

TS88915T

PLL

CLOCK

@ f

2f

CMMU

CPU

CMMU CMMU

SYSTEM

CLOCK

SOURCE

CPU

CARD

TS88915T

PLL

2f

CMMU

CPU

DISTRIBUTE

CLOCK @ f

CMMU CMMU

CLOCK @ 2f

AT POINT OF USE

TS88915T

PLL

MEMORY

CONTROL

2f

MEMORY

CARDS

CLOCK @ 2f

AT POINT OF USE

Figure 12 : Representation of a potential Multi–Processing application utilizing the TS88915T

for frequency multiplication and low Board-to-Board skew

16/20

TS88915T

5.4. TS88915T System level testing functionality

3-State functionality has been added to the TS88915T to ease system board testing. Bringing the OE/RST pin low will put all outputs

(except for LOCK) into a high impedance state. As long as the PLL_EN pin is low, the Q0–Q4, Q5 and Q/2 outputs will remain in the

low state after the OE/RST until a falling SYNC edge is seen. The 2X_Q output will be the inverse of the SYNC signal in this mode. If

the 3–state functionality will be used, a pull–up or a pull–down resistor must be tied to the FEEDBACK input pin to prevent it from

floating when the feedback output goes into high impedance.

WiththePLL_ENpinlowtheselectedSYNCsignalisgateddirectlyintothesignalclockdistributionnetwork, bypassinganddisabling

the VCO. In this mode the outputs are directly driven by the SYNC input (per the block diagram). This mode can also be used for low

frequency board testing.

Note: If the outputs are put into 3-state during normal PLL operation, the loop will be broken and phase-lock will be lost. It will take a

maximum of 10ms (t_LOCKspec) to regain phase-lock after the OE/RST pin goes back high.

6. PREPARATION FOR DELIVERY

6.1. Packaging

Microcircuits are prepared for delivery in accordance with MIL-PRF-38535.

6.2. Certificate of compliance

TCSoffersacertificateofcomplianceswitheachshipmentofparts, affirmingtheproductsareincomplianceeitherwithMIL-STD-883

and guarantying the parameters not tested at temperature extremes for the entire temperature range.

7. HANDLING

MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devi-

ces have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recom-

mended :

a) Devices should be handled on benches with conductive and grounded surfaces.

b) Ground test equipment, tools and operator.

c) Do not handle devices by the leads.

d) Store devices in conductive foam or carriers.

e) Avoid use of plastic, rubber, or silk in MOS areas.

f) Maintain relative humidity above 50 percent if practical.

17/20

TS88915T

8. PACKAGE MECHANICAL DATA

8.1. 29-pins PGA

(TOP VIEW)

C

INCHES

MILLIMETERS

E

DIM

A

MIN

MAX

0.606

0.107

0.19

MIN

15.087

–

MAX

15.392

2.72

0.594

–

G

C

D

0.17

0.045

4.32

4.83

F

E

0.055

1.143

1.397

F

G

0.100 BSC

2.54 BSC

H

0.017

0.019

0.43

0.48

A

(BOTTOM VIEW)

1

6

D

A

8.2. 28–pins LDCC

Note : This package is pin compatible with civil PLCC

(TOP VIEW)

(BOTTOM VIEW)

18/20

TS88915T

9. ORDERING INFORMATION

TS(X)/ TS 88915T

M R B / T 70

Maximum Output Frequency :

Prototype prefix

70 : 70 MHz

(1)

TCS prefix

100 : 100 MHz

Type

(2)

Screening level

__ :Standard

:

Temperature range : Tc

M : -55, +125°C

V : -40, +85°C

C : 0, +70°C

B/T :according to MIL-STD-883

D/T : Burn-in

Package :

R : PGA

W : LDCC

(1) THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES

(2) For availability of the different versions, contact your TCS sales office

19/20

TS88915T

Information furnished is believed to be accurate and reliable. However THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES

assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third

parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of THOM-

SON-CSF SEMICONDUCTEURS SPECIFIQUES. Specifications mentioned in this publication are subject to change without notice.

This publication supersedes and replaces all information previously supplied. THOMSON-CSF SEMICONDUCTEURS SPECIFI-

QUES products are not authorized for use as critical components in life support devices or systems without express written approval

from THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES. 1999 THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES -

This product is manufactured by THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - 38521 SAINT-EGREVE - FRANCE.

For further information please contact : THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - Route Départementale 128 -

B.P. 46 - 91401 ORSAY Cedex - FRANCE - Phone +33 (0)1 69 33 00 00 - Fax +33 (0)1 69 33 03 21 - E-mail : lafrique@tcs.thomson.fr

10.

20/20


型号：	TSX88915TCRD/T70
厂家：	ATMEL
描述：	PLL Based Clock Driver, 7 True Output(s), 1 Inverted Output(s), CMOS, CPGA29, CERAMIC, PGA-29 驱动逻辑集成电路
文件：	总20页 (文件大小：168K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

TSX88915TCRD/T70 [ATMEL]

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