TSXPC750ADVIP266DE [ATMEL]
RISC Microprocessor, 32-Bit, 266MHz, CMOS, 2.54 MM PITCH, PCM, PGA-288;
| 型号： | TSXPC750ADVIP266DE |
| 厂家： | 
ATMEL |
| 描述： | RISC Microprocessor, 32-Bit, 266MHz, CMOS, 2.54 MM PITCH, PCM, PGA-288 PC |
| 文件： | 总17页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
TSPC750IP
Processor and Cache Module
DESCRIPTION
The Processor and Cache Module (PCM) is a 17 x 17 pin grid
array (PGA) circuit assembly which combines a PowerPCt
microprocessor and SRAM components into a CPU subsys-
tem. The PCM provides a standard mechanical, electrical, and
functional interface which can be socketed on a computer sys-
tem board and allows many combinations of processors and
optional components to be easily interchanged. This docu-
ment describes the general characteristics for a module con-
sisting of a single PowerPCt microprocessor and two SRAM
devices for L2 cache. The PCM packaging and PGA signal
definition also accomodates single processors without SRAM,
and multiple processors.
The PCM consists of an epoxy–glass (FR4) substrate which
adapts a processor in a ceramic ball grid array (CBGA) pac-
kage with 50 mil spacing to a 288–pin PGA with 100 mil spac-
ing that can be easily socketed and hence, easily upgraded.
The FR4 substrate can be extended beyond the area of the 17
x 17 pin grid array to provide an interconnect area for SRAM
components configured as closely coupled L2 cache. The
resulting PCM provides numerous flexible configurations of
processor and cache for various price/performance system
designs.
FR4 PCM on PGA 288 Interposer
I
N
T
60x Address
L2 Addr
L2–Cache
Memory
Chips
60x Data
TSPC750
L2 Data
E
R
P
O
S
E
R
60x Control
L2 Control
Processor
PLL_CFG
P
I
N
S
General
Support
Circuits
VID
PID
Simplified Block Diagram
1/17
April 1999
TSPC750IP
1. PIN ASSIGNEMENT
Figure 1(inpartA)showsthepinoutofthePCMasviewedfromthetopsurface. PartBshowsthesideprofileofthemoduletoindicate
the direction of the top surface view.
Part A
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
17
16
15
14
13
12
11
10
09
08
07
06
05
04
03
02
01
Not to Scale
Part B
CBGA Substrate
Microprocessor Die
View
TQFP Packaged SRAM
FR4 PCM
Figure 117 x 17 PGA Processor + Cache Module
2/17
TSPC750IP
2. PINOUT LISTING
Table 1 provides the pinout listing for the 17 x 17 PGA PCM. This pinout is the superset of all 17 x 17 PCMs and should be followed for
maximum interchangeability between modules; however, particular implementations may not connect all signals between the PGA
pins and the PowerPC microprocessor. See the individual part number specifications for specific pinouts by part number.
Table 1. Pinout Listing for the 17 x 17 PGA Module
Signal Name
A[0–31]
Pin Number
Active
High
I/O
I/O
F13, E1, D17, F3, E16,F1, E17, G5, F15, G4, G13, G3,
F17, G2, G14, G1, G15, H1, G16, H3, G17, J1, H13, H5,
H15, J2, H17, J3, J13, L1, K13, M1
AACK
K3
Low
Low
High
Low
Low
Low
High
Low
Low
Low
Low
Low
—
Input
I/O
ABB
L3
AP[0–3]
APE
E6, C4, C5, A4
I/O
C8
Output
Input
I/O
ARRAY_WR 2
ARTRY
AVDD
A8
K5
A11
J5
Input
Input
Input
Output
Output
Output
Output
Input
Output
Output
I/O
BG
BG2
E13
E8
BR
BR2
A17
E2
CI
CLK_OUT
CKSTP_IN
CKSTP_OUT
CSE0–CSE1 1
DBB
A6
C9
Low
Low
High
Low
Low
Low
Low
Low
High
E9
E7, B5
L17
J15
K1
DBDIS
DBG
Input
Input
Input
Input
I/O
DBG2
R15
J4
DBWO
DH[0–31]
P13, N12, T15, U15, R13, U14, N10,P11, T11, U11, R10,
U10, U9, T9, N9,P9, R9, U8, R8, U7, N8, P7, T7,U6, R7,
R6, N7, U5, T5, U4, R5,U3
DL[0–31]
L16, K15, M17, L14, N17, M15, N16, L13, M13, N15, P17,
R17, N14, P15, R16, U16, R14, N11, T13, R12, U13, R11,
U12, N3, P3, N4, R2, T1, T3, R4, P5, N6
High
I/O
3/17
TSPC750IP
Table 1. Pinout Listing for the 17 x 17 PGA Module (cont’d)
Pin Number
Signal Name
Active
High
Low
I/O
I/O
DP[0–7]
DPE
L4, N1, M3, N2, P1, L5, R1, M5
B7
Output
Input
Input
I/O
DRTRY
DRVMOD[0–1]
GBL
J17
E3, D3
F5
Low
—
Low
GND
B4, B8, B10, B14, D2, D6, D12, D16,F4, F6, F8, F10, F12, Low
F14, G7, G9, G11, H2, H6, H8, H10, H12, H16, J7, J9, J11,
K2, K6, K8, K10, K12, K16, L7, L9, L11, M4, M6, M8, M10,
M12, M14, P2, P6, P12, P16, T4, T8, T10, T14
Input
HALTED
HRESET
INT
D9
High
Low
Low
Low
Low
—
Output
Input
Input
Input
Input
Input
Input
Input
Input
Input
–
B9
E14
U17
D11
B11
A7
INT2
LSSD_MODE 2
L1_TSTCLK 2
L2_INT
High
—
L2_TSTCLK2
MCP
E10
D15
D7
Low
High
—
NAP_RUN
NC 5
N13
OVDD 3
B2, B6, B12, B16, D4, D8, D10, D14, F2, F9, F16, H4,
H14, J6, J12, K4, K14, M2, M9, M16, P4, P8, P10, P14,
T2, T6, T12, T16
High
Input
PID[0–2]
PLL_CFG[0–3]
QACK
U1, U2, R3
High
High
Low
Low
Low
—
I/O
A9, A10, A13, C11
Input
Input
Output
Output
Input
I/O
E5
N5
D5
A3
C1
L2
QREQ
RSRV
SCLK
SDATA
SHD
—
Low
Low
I/O
SMI
B17
Input
4/17
TSPC750IP
Table 1. Pinout Listing for the 17 x 17 PGA Module (cont’d)
Pin Number
Signal Name
SRESET
Active
Low
I/O
Input
D13
SYSCLK
SYSCLK2
TA
C10
—
—
Input
Input
Input
Input
I/O
T17
J16
Low
High
Low
High
—
TBEN
TBST
E4
E12
TC[0–2] 4
TCK
C6, A5, C7
Output
Input
Input
Output
Input
Input
Input
Input
I/O
C12
TDI
B13
High
High
Low
Low
High
Low
High
Low
High
High
TDO
A14
TEA
J14
TLBISYNC
TMS
C15
C13
TRST
TSIZ[0–2]
TS
A12
E11, A15, B15
L15
I/O
TT[0–4]
VDD 3
A16, C14, C16, C17, E15
I/O
F7, F11, G6, G8, G10, G12, H7, H9, H11, J8, J10, K7, K9,
K11, L6, L8, L10, L12, M7, M11
Input
VID[0–4]
WT
B1, C2, A2, B3, C3
High
Low
Low
Input
D1
Output
Output
XATS 1
K17
Notes:
1. Not recommended for new designs.
2. These are test signals for factory use only and must be pulled up to Vdd for normal machine operation.
3. OVdd inputs supply power to the I/O drivers and Vdd inputs supply power to the processor core.
4. TC2 defined for PowerPC 604 –class processors only.
5. These signals are undefined and must be left disconnected.
Many of the PCM signals have the same definition and timing as that of the attached processor. The actual signals present vary
depending upon the type of the PowerPC microprocessor used; refer to the corresponding processor hardware specifications for
details.
The PCM implements several signals that are not part of the PowerPC 60x bus specification, nor of any particular PowerPC proces-
sor. These pins are unique to the PCM and are used to set operational parameters or indicate the features the PCM provides. Table 2
describes the functions of the signals provided for identification or configuration of the PCM.
5/17
TSPC750IP
Table 2. PCM Unique/Redefined Pins
Pin Name
Definitions
Notes
VID[4–0]
The VID pins encode the voltage encoding as
described in Section 5.6. , “Voltage Encoding.”
Note the little–endian bit ordering, used for
compatibility with industry standard parts.
These pins must be pulled up by the power
controller for proper operation. The pullups must be
wired to a voltage level which is stable while the
power controller ramps up after power up.
Many power controllers include internal pullups to
handle this.
PID[0–2]
PLL[0–3]
The PID pins carry the presence detect codes as
described in Section 5.7. , “Presence Detect.”
These pins must be pulled up by the system with
1K to 10K pullup resistors.
Specified PLL setting to use.
These PLL pins may be connected to VDD or
ground on the PCM if a PLL–encoded PCM is
ordered; otherwise, the motherboard may control
the CPU’s PLL pins directly as usual with PowerPC
CPUs.
SYSCLK2 Clock for second processor. Same timing as
SYSCLK for PowerPC CPUs.
Unused signal—Reserved for future function; signal
should remain disconnected
INT2
Interrupt for second processor. Same timing as INT Unused signal—Reserved for future function; signal
for PowerPC CPUs.
should remain disconnected
BR2
Bus request for second processor. Same timing as
BR for PowerPC CPUs.
Unused signal—Reserved for future function; signal
should remain disconnected
BG2
Bus grant for second processor. Same timing as BG Unused signal—Reserved for future function; signal
for PowerPC CPUs.
should remain disconnected
DBG2
SCLK
SDATA
Data Bus grant for second processor. Same timing
as DBG for PowerPC CPUs.
Unused signal—Reserved for future function; signal
should remain disconnected
I2C serial clock input
Connected when EEPROM presence detect mode
is implemented.
I2C command input/ data output
Connected when EEPROM presence detect mode
is implemented.
6/17
TSPC750IP
3. GENERAL PARAMETERS
The following list provides a summary of the general parameters of the PCM with a PC750 processor and 256 Kbytes, 512 Kbytes, or
1 Mbyte of SRAM:
Technology
See General Parameters of individual components.
See General Parameters of individual components.
See General Parameters of individual components.
17 x 17 pin grid array
Die Size
Transistor Count
Package
Core Power Supply
Generally 2.6 + 5% V dc but refer to the part number specifications
for a specific part for accurate information
I/O Power Supply
3.3 + 5% V dc
4. ELECTRICAL AND THERMAL CHARACTERISTICS
The AC and DC electrical specifications for the PCM are identical to the electrical specifications for the attached microprocessor
unless otherwise specified in the part number specifications for a particular module.
The thermal characteristics for the PCM are generally the composite of the thermal characteristics for the attached microprocessor
and SRAMs. The variety of processor and SRAM speeds possible dictate that thermal characteristics are unique to a particular mod-
ule and therefore are described in its associated part number specifications.
5. SYSTEM DESIGN INFORMATION
Refer to the device–specific user’s manuals and hardware specifications for system design information about the processor and
SRAM attached to the module. This section provides descriptions of functionality and electrical or thermal design recommendations
unique to the PCM.
5.1. PLL Configuration
The system utilizing the PCM is expected to configure the processor PLL by the PLL_CFG[0–3] signals appropriate to the attached
processor. For a given SYSCLK (bus) frequency, the PLL configuration signals set the internal CPU and VCO frequency of operation.
Refer to the system design information of the appropriate processor’s hardware specifications for appropriate PLL settings. It is pos-
sible during manufacture to fix the settings of PLL_CFG[0–3] via jumpers on the substrate to one particular combination that will be
independent of the signals asserted by the system on the pins; if this is done for a particular part number, it will be noted in the part
number specifications for that specific part.
The interface between the processor and the SRAMs on the module will operate at CPU–to–L2 frequency divisors of B1, B1.5, B2,
B2.5, and B3. These ratios will have to be programmed into the L2 cache control registers on the processor by the operating system
and the L2 cache enabled before the SRAM will be functional on the module. See the part number specifications for the CPU–to–L2
frequency divisor(s) supported on a particular part.
7/17
TSPC750IP
5.2. PLL Power Supply Filtering
The AVdd power signal provides power to the clock generation phase–locked loop. To ensure stability of the internal clock, the power
supplied to the AVdd input signal of the microprocessor should be as electrically quiet as possible. For maximum effectiveness the
filter circuit of Figure 2 which is normally recommended for inclusion in the system design has been included on the PCM itself.
10Ω
Vdd
AVdd (or L2AVdd)
10µF
0.1µF
GND
Figure 2. PLL Power Supply Filter Circuit
The PCM resistors are used to program the connection between the external signals and the microprocessor PLL supply as shown in
Figure 3. If required, the system can provide additional power supply filteringfortheAVdd signal, shown in Figure 2, to thePCM AVdd
signal. The PCM provides AVdd power supply filtering as shown in Figure 3.
10Ω
Internal AVdd
Internal L2AVDD
External Vdd
External AVdd
10µF
0.1µF
0.1µF
NC
GND
Figure 3. PCM PLL Power Supply Filter Circuit
5.3. Decoupling Recommandations
The microprocessor and cache on the PCM can generate transient power surges and high frequency noise in its power supply, espe-
cially while driving large capacitive loads. This noise must be prevented from reaching other components in the system, and the
moduleitself requires a clean, tightly regulated source of power. Therefore, it is recommended that the system designer placeat least
one decoupling capacitor at each Vdd and OVdd pin of the module. It is also recommended that these decoupling capacitors receive
their power from separate Vdd, OVdd, and GND power planes in the PCB, utilizing short traces to minimize inductance.
The module will provide some bulk decoupling and high frequency decoupling capacitors on the module itself to improve the overall
system noise immunity.
5.4. Connection Recommandations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal level. Unused active low
inputs should be tied to Vdd. Unused active high inputs should be connected to GND. All NC (no–connect) signals must remain
unconnected.
Power and ground connections must be made to all external Vdd, OVdd, and GND pins of the PCM.
5.5. Socketing
The PCM is specifically designed for the flexibility of a socket. The PGA footprint is compatible with the widely available Socket #3
footprint popular in the PC industry. Several vendors provide this socket, including Amp Incorporated (part number: 916668–1).
8/17
TSPC750IP
5.6. Voltage Encoding
The core operating voltage (Vdd and AVdd) for PowerPC processors has varied with semiconductor process technology. Within a
narrow range determined by the process technology, Motorola has specified non–standard core voltages for some processors in
device–specific part number specifications.
The PCM provides additional pins to communicate the attached processor’s preferred core voltage. The desired voltage setting is
encoded on the VID[4–0] signals. This 5–bit bus encodes various voltage settings which match existing industry standards. In most
systems these signals are connected directly to a Voltage Regulator Module (VRM) or to an on–board power supply which accepts
the VID encoded voltage setting.
The encoding for the VID voltage levels supported by the PCM are shown in Table 3.
Table 3. Voltage Encoding
VID[4–0] Output
01111
Voltage (V)
1.30 V
1.35 V
1.40 V
1.45 V
1.50 V
1.55 V
1.60 V
1.65 V
1.70 V
1.75 V
1.80 V
1.85 V
1.90 V
1.95 V
2.00 V
2.05 V
VID[4–0] Output
10000
10001
10010
10011
Voltage (V)
3.50 V
3.40 V
3.30 V
3.20 V
3.10 V
3.00 V
2.90 V
2.80 V
2.70 V
2.60 V
2.50 V
2.40 V
2.30 V
2.20 V
2.10 V
No CPU
01110
01101
01100
01011
10100
10101
10110
01010
01001
01000
00111
10111
11000
11001
11010
11011
00110
00101
00100
00011
11100
00010
00001
00000
11101
11110
11111
Note: The bit numbering shown here is little–endian due to pre–existing
standards. This differs from most other PowerPC bus numbering
conventions.
The PCM encodes the voltage setting by selectively installing 0–ohm resistors on the VID bus. The regulator must have internal
pullups to properly encode the settings (this is true of all known 5–bit encoded switching controllers).
9/17
TSPC750IP
5.7. Presence Detect
The PCM provides a means of self–identification (called presence detection after the method(s) used to identify memory and cache
modules). Themoduleimplementsathree–wiresolutionwhichcombinestheinexpensiveparallelencodingofSingleIn–lineMemory
Modules (SIMMs) with the more flexible serial solution found on Dual In–line Memory Modules (DIMMs). Figure 4 shows the architec-
ture of the presence detection:
VCC VCC VCC
PCM
PID0
PID1
PID2
SCLK
I2C
SDATA
Figure 4. CPU Present Detect Hardware
Note that either the pull–down resistors are installed, or the I2C EEPROM, but not both.
For the simplest case, the three presence detect pins encode seven specific configurations of processor or processor/cache com-
binations, with one reserved for identification of the serial EEPROM method. The motherboard requires pullups on the parallel lines
(1K to 10K ohms), and the PCM selectively pulls down the PID lines to create the PID encoding.
The possible combinations of processor and cache with all the attendant settings are too numerous to directly encode in the three bits
allotted, so predefined configurations are assigned an identifier. Additionally, the table used will be associated with the processor
attached (determined by reading the processor PVR). Together, the processor ID register and PID bits are used to determine the
most difficult cache settings, with the remainder handled by software, as shown in Table 4.
Table 4. Processor Presence Detect (PPD) Information
Parameter
Determined by
Cache size
PPD encoding
PPD encoding
PPD encoding
Software
Processor core/cache bus clock ratio
Cache type
Cache enable
Cache parity
Software, or always off
Software, or always copyback
Always 0.5 ns
Cache write–through/copyback
Cache output hold
Cache clock type
If late–write: differential
If pipelined: single–ended
10/17
TSPC750IP
Table 5 shows example settings for an PC750–based PCM with cache:
Table 5. PC750 Presence Detect Table
Cache/Core
Ratio
Example Module
CPU/Cache
PID[0–2]
SRAM Type
Hold (ns)
Size
SRAM Speed
0 0 0
0 0 1
3:2
Late–write
Pipelined
0.5
1 M
300/200
200
2:1
0.5
512 K
300/150
266/133
233/117
150
133
117
0 1 0
2:1
Pipelined
0.5
1 M
300/150
266/133
233/117
200/100
150
133
117
100
0 1 1
1 0 0
5:2
5:2
Pipelined
Pipelined
0.5
0.5
512 K
1 M
300/120
266/106
233/ 93
120
117
100
300/120
266/106
233/ 93
120
117
100
1 0 1
1 1 0
1 1 1
3:1
Pipelined
Pipelined
0.5
0.5
512 K
1 M
300/100
266/ 88
100
90
3:1
300/100
266/88
100
90
No Module ID
This indicates the presence of a serial
EEPROM or non–cache PCM.
Note that there are various cache speeds for each entry. The processor does not need to know the actual speed of its cache, only the
proper ratio of core:cache, in order to properly configure the cache controller. If the cache speed is of interest, the bus frequency and
PLL settings must be determined via software.
Foreachnewprocessorwithcacheasimilartablewillbecreated. IfaPCMneedsaparticularcombinationthatwasnotpre–definedin
this table, then a serial presence detect EEPROM will be used. A serial EEPROM is detected when all ones are sensed on the PID
lines. To determine the system configuration, software will have to read the data from the EEPROM, as shown in Figure 4.
Either software or an I2C controller may be used to address EEPROM #2 (the address of the presence detect EEPROM) and load the
configuration data.
11/17
TSPC750IP
5.7.1.Presence Detect EEPROM Format
The data within presence detect EEPROM memory generally follows JEDEC DIMM outline and reuses the same data formats. The
format is not JEDEC approved, and will not be since it cannot be shared with DIMM memory presence detect lines.
The format of the data is based upon the following criteria:
•
The Software Presence Detect (SPD) describes the PCM but does not tell the software what register bits to use
(interfaces change over time).
•
Minimize software impact by re–using memory SPD data formats. This also implies that little–endian multi–byte
ordering is retained.
•
•
Keep the block/length structure so that I2C readers can be re–used.
The first few bytes should not be all ones, so that the I2C EEPROM reader routine can easily detect the
presence/absence of data.
Table 6 shows the PCM SPD format.
Table 6. PCM SPD Data Format
Byte
Field
Description
Range of Values
64, 128, 255
Example
0
NO
Number of bytes written into
EEPROM
80
1
2
SIZE
TYPE
WIDTH
VID
Total number blocks of SPD RAM 4, 8, 16
08
00
Module type
CPU
5, 6
7
Data width of module
1–65536
3.3V
80, 00
12
Voltage level of module
(Mirrors VID encoding)
2.5V
1A
01
02
03
00
00
8
SIGLEV
Signaling level
1:LVTTL
2:SSTL
3:GTL
9
TAU0
TAU calibration, 0 °C
–128..127
–128..127
10
TAU100
TAU calibration, 100 °C
11–15
16
Reserved for other general information
Cache type 0:None
CTYPE
00
01
02
03
1:Flow–through
2:Pipelined
3:Late–write
12/17
TSPC750IP
17, 18
CSIZE
Cache size LSB, MSB (K)
0
00, 00
00, 02
00, 04
00, 08
00, 00
B4, 00
C8, 00
00
512K
1M
2M
19, 20
CSPEED
Cache speed LSB, MSB (MHz)
0
180
200
21
22
CCLOCK
CHOLD
Cache clock type
Cache output hold
0:Single–ended
1:Differential
0.0 ns
0.5 ns
1.0 ns
1.5 ns
01
00
05
10
15
23–31
32
Reserved for other cache information
CPUS
CPU count
0–n
01
33
SPEED
CPU speed LSB, MSB (MHz)
66
42, 00
C8, 00
4D, 01
42, 00
64, 00
200
333
66
34, 35
BUSSPD
Bus speed LSB, MSB (MHz)
100
36–63
64–67
68–90
Reserved for other CPU information
Manufacturers ID
MANUF
CPUID
Stock name
Part marking
“MOT“
CPU ID
“MPC603RRX3
66LARX”
91–127
Manufacturers data
Unused
TBD
FF
FF
128–nnn
13/17
TSPC750IP
The first eight bytes are fairly similar to the DIMM SPDs in the hope that it will enable the EEPROM access software to retrieve a
block from either SPD with minimal effort. Thereafter, the formats diverge but should allow the re–use of existing DIMM data
conversion routines (for example, the format for output hold).
The fields of the EEPROM are described in detail as follows:
NO
This field contains the total number of bytes written during manufacture. This field is retained for
compatibility with existing SPD standards.
SIZE
This field contains the number of 16–byte blocks available in the EEPROM. A value of 0x10 indicates the
EEPROM is 16 x 16 = 256 bytes long. This field is retained for compatibility with existing SPD standards.
TYPE
WIDTH
VID
The type encoding field is zero to indicate that it is not a memory DIMM. This field is retained for
compatibility with existing SPD standards.
This field describes the width of the module. The value is the width of the PCM, either 0x0080 (64–bit) or
0x0100 (128–bit). This field is retained for compatibility with existing SPD standards.
The VID field contains a copy of the encoding presented to the motherboard via the VID pins. Refer to the
VRM table for the encoded values.
SIGLEV
The SIGLEV field contains an encoded description of the PCM interface level; see Table 7.
Table 7. PCM Interface Level
Interface Level
LVTTL
Code
01
SSTL
GTL
02
03
TAU
This field describes the calibration factors necessary to temperature compensate a thermal assist unit
(TAU), such as found on PC750 processors. The current TAU units have a high relative accuracy, but an
absolute accuracy of "12°C. With the appropriate compensation factors stored in EEPROM, the
TAU–handling software can determine the temperature to the specified accuracy.
The parameters describe the numerical offset applied at 0°C and 100°C. The software can elect to adjust
the temperature over the described interval for greatest accuracy (using linear interpolation), or apply only
the 100°C factor for faster compensation (with less accuracy).
CTYPE
The CTYPE field contains an encoding which indicates the type of cache attached to the processor
dedicated L2 interface, if any. If zero is present, indicating no cache, none of the other cache parameters
have any meaning; see Table 8.
Table 8. CTYPE Field Encoding
CTYPE
Cache Type
0
1
2
3
None
Flow–through
Pipelined
Late–write
14/17
TSPC750IP
CSIZE
The CSIZE field contains the size of the cache, in kilobytes.
CSPEED
CCLOCK
The CSPEED field contains the speed of the cache, in megahertz.
The CCLOCK field is used to configure the L2 clock signals as single–ended (0 value) or differential (1
value).
CHOLD
The CHOLD field contains the hold time needed for the cache memories, encoded in the pseudo–BCD
method used for SPD data values. The lower nibble ranges from 0..9, and describes fractions of
nanoseconds. The upper range is from 0..15, and is in nanoseconds. The lower nibble may be used as–is,
or simply to round up the upper nibble, as needed.
CPUS
The CPUS field contains the number of CPUs present on the PCM.
SPEED
BUSSPD
MANUF
The SPEED field contains the maximum specified core operating speed of the CPU(s), in megahertz.
The BUSSPD field contains the maximum specified bus operating speed of the CPU(s), in megahertz.
The MANUF field contains the stock ticker symbol of the manufacturer of the CPU. The encoding method
is ASCII; unused bytes are filled with zero.
CPUID
The CPUID field contains the literal ASCII name (part ordering number) of the CPU(s) installed. For
example, a 300 MHz PowerPC 603e would be encoded as MPC603RRX300LA. Unused bytes are filled
with zeroes.
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TSPC750IP
6. PACKAGE MECHANICAL DATA
The package parameters are as provided in the following list. The package consists of a 288–lead pin grid array (PGA) on the
bottom of a 1.75 x 2.5 inch glass–epoxy (FR4) substrate with a PowerPC microprocessor in a ceramic ball grid array (CBGA)
package and two fast static RAMs (FSRAMs) in ceramic quad flat pack (CQFP) or plastic ball grid array (PBGA) packages attached
on the top. The package parameters for the PGA PCM are:
B
D
(D4)
2X (D5)
NOTES:
(E4)
a. DIMENSIONS AND TOLERANCING PER
ASME Y14.5M, 1994.
b. DIMENSIONS IN INCHES.
2X (E5)
2X (E7)
c. TOP SIDE A1 CORNER INDEX IS A SILK
SCREENED FEATURE WITH VARIOUS
SHAPES. BOTTOM SIDE A1 CORNER IS
DESIGNATED WITH A PIN MISSING FROM
THE ARRAY
E
(E3)
d. DIMENSIONS D1 AND E1 ARE LESS THAN
(E6)
OR EQUAL TO D AND E.
e. MINIMUM HANDLING CLEARANCE
BETWEEN PACKAGE EDGE AND PASSIVE
COMPONENTS IS 0.020.
(D6)
(D3)
(D7)
A1
CORNER
C
A
TOP VIEW
Inches
MIN
DIM
A
MAX
0.420
0.190
0.065
0.115
0.063
0.098
0.132
0.020
2.550
D1
0.390
0.170
—
A1
A2
A3
A4
A5
A6
b
A B C D
E F G H J K L M N P R T U
1
2
3
4
5
6
7
8
9
0.090
0.055
—
(E2)
E1
0.0980
0.016
2.480
10
11
12
13
14
15
16
17
D
D1
D2
D3
D4
D5
D6
D7
e
See Note 4
1.600 REF
0.984 REF
0.870 REF
0.787 BSC
0.532 REF
0.560 REF
0.100 BSC
16X
e
A1
A2
A3
(D2)
BOTTOM VIEW
288X
b
A B C
0.010 A
A4
A5
A6
A
E
1.740
1.780
E1
E2
E3
E4
E5
E6
E7
See Note 4
1.600 REF
0.984 REF
0.630 BSC
0.551 BSC
0.532 REF
0.420 REF
SIDE VIEW
Figure 5. Mechanical Dimensions and Bottom Surface Nomenclature of the PCM
16/17
TSPC750IP
7. ORDERING INFORMATION
This section provides the part numbering nomenclature for the PCM. Note that the individual part numbers correspond to a
particular PowerPC microprocessor at a maximum core frequency and a certain size of SRAM. Often the ratio of core to L2
frequency is called out in the part number also because this ratio and the maximum core frequency set the maximum frequency of
the attached SRAM.
M
TS (X) PC750A F
C E
IP
233
(1)
TCS prefix
Prototype
Revision Level
Part Identifier
(2)
Part Modifier
(2)
Application Modifier
C
D
E
F
:
:
:
:
750 with 256K pipeline burst
750 with 1M pipeline burst
750 with 1 M late write flow–through
750 with 512K pipeline burst
C
D
E
: 2:1 core:L2
: 5:1 core:L2
: 3:1 core:L2
(2)
Max Internal Processor Speed
Temperature range : T
A
200 : 200 MHz
233 : 233 MHz
266 : 266MHz
300 : 300MHz
C
V
:
:
0, 70 °C
–40, +85 °C
(2)
Package Code
IP
: PGA FR4 PCM
(1) THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES
(2) For availability of the different versions, contact your TCS sale office
Information furnished is believed to be accurate and reliable. However THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES
assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third
parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of THOM-
SON-CSF SEMICONDUCTEURS SPECIFIQUES. Specifications mentioned in this publication are subject to change without notice.
This publication supersedes and replaces all information previously supplied. THOMSON-CSF SEMICONDUCTEURS SPECIFI-
QUES products are not authorized for use as critical components in life support devices or systems without express written approval
from THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES. 1999 THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES -
Printed in France - All rights reserved.
This product is manufactured by THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - 38521 SAINT-EGREVE - FRANCE.
For further information please contact : THOMSON-CSF SEMICONDUCTEURS SPECIFIQUES - Route Départementale 128 -
B.P. 46 - 91401 ORSAY Cedex - FRANCE - Phone +33 (0)1 69 33 00 00 - Fax +33 (0)1 69 33 03 21 -
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8.
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