U2730B-N [ATMEL]
L-band Down-converter for DAB Receivers; L波段下变频器的DAB接收器
| 型号： | U2730B-N |
| 厂家： | 
ATMEL |
| 描述： | L-band Down-converter for DAB Receivers |
| 文件： | 总17页 (文件大小：201K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Supply Voltage: 8.5 V
• RF Frequency Range: 1400 MHz to 1550 MHz
• IF Frequency Range: 150 MHz to 250 MHz
• Enhanced IM3 Rejection
• Overall Gain Control Range: 30 dB Typically
• DSB Noise Figure: 10 dB
• Gain-controlled Amplifier and L-band Mixer
• Power-down Function for the Analog Part
• On-chip Gain-control Circuitry
• On-chip VCO, Typical Frequency 1261.568 MHz
• Internal VCO Can Be Overdriven by an External LO
• On-chip Frequency Synthesizer
L-band
Down-converter
for DAB
– Fixed LO Divider Factor: 2464
– Nine Selectable Reference Divider Factors : 32, 33, 35, 36, 48, 49, 63, 64, 65
– A Reference Oscillator (Can Be Overdriven by an External Reference Signal)
– Tristate Phase Detector with Programmable Charge Pump
– Programmable Deactivation of Tuning Output
– Lock-status Indication
Receivers
U2730B-N
– Test Interface
Electrostatic sensitive device.
Observe precautions for handling.
Preliminary
Description
The U2730B-N is a monolithically integrated L-band down-converter circuit fabricated
with Atmel’s advanced UHF5S technology. This IC covers all functions of an L-band
down-converter in a DAB receiver. The device includes a gain-controlled amplifier, a
gain-controlled mixer, an output buffer, a gain control block, a power save function for
the analog part, an L-band oscillator and a complete frequency syntheziser unit. The
frequency syntheziser block consists of a reference oscillator/buffer, a reference
divider, an RF divider, a tri-state phase detector, a loop filter amplifier, a lock detector,
a programmable charge pump, a test interface and a control interface.
4719A–DAB–05/03
Figure 1. Block Diagram
IF
VCC1 VCC3 VCC4 VCC2
GND
TH
17
19
3
20
28
9
6, 7, 8, 21,
22, 23, 24
18
Internal 5 V supply voltage
for frequency synthesizer
AGC
Voltage
stabilizer
U
Analog
Band-
gap
14
part
PLCK
26
RF
25
Lock
detector
NRF
20k
5
4
TANK
VREF
RF counter
: 2464
12
13
VCO
CD
PD
Charge
pump
Tristate
phase
200 ꢀ/300 ꢀ
detector
Power save
(analog part)
Reference
counter
: Nref
Power
down
Control
interface
Test
interface
10
1
15
OSCB
16
OSCE
11
27
2
PSM
TI
CI SI1 SI2
2
U2730B-N
4719A–DAB–05/03
U2730B-N
Pin Configuration
Figure 2. Pinning SSO28
VCC4
1
2
3
4
5
6
7
8
9
PSM
28
27
26
SI2
VCC1
VREF
TANK
GND
SI1
RF
25
24
NRF
GND
GND
GND
GND
VCC3
23
22
GND
21
20
19
18
GND
VCC2
10
11
IF
CI
TI
AGC
CD
12
13
14
17 TH
16
15
PD
OSCE
OSCB
PLCK
3
4719A–DAB–05/03
Pin Description
Pin
Symbol
Function
1
PSM
Power save mode
Control input
2
SI2
3
VCC1
VREF
TANK
Supply voltage VCO
Reference pin of VCO
Tank pin of VCO
4
5
6, 7, 8, 21,
22, 23, 24
GND
Ground
9
VCC2
CI
Supply voltage PLL
10
11
12
13
14
15
16
17
18
19
20
25
26
27
28
Control input
TI
Test interface
CD
Active filter output
PD
Tristate charge pump output
Lock-indication output (open collector)
Input of internal oscillator/buffer
Output of internal oscillator/buffer
Threshold voltage of comparator
Charge-pump output of comparator, AGC input for amplifier and mixer
Intermediate frequency output
Supply voltage
PLCK
OSCB
OSCE
TH
AGC
IF
VCC3
NRF
RF
RF input (inverted)
RF input
SI1
Control input
VCC4
Supply voltage
4
U2730B-N
4719A–DAB–05/03
U2730B-N
Functional Description
The U2730B-N is an L-band down-converter circuit covering a gain-controlled amplifier,
a gain-controlled mixer, an output buffer, a gain control circuitry, an L-band oscillator
and a frequency synthesizer block. Designed for applications in a DAB receiver, the cir-
cuit down-converts incoming L-band signals in the frequency range of 1452 MHz to
1492 MHz to an IF frequency in a range of 190 MHz to 230 MHz which can be handled
by a subsequent DAB tuner. A block diagram of this circuit is shown in Figure 1.
Gain-controlled Amplifier RF signals applied to the 'RF' input pin are amplified by a gain-controlled amplifier. The
complementary pin NRF is not internally blocked, it is recommended to block this pin
carefully by an external capacitor. The gain-control voltage is generated by an internal
gain-control circuitry. The output signal of this amplifier is fed to a gain-controlled mixer.
Gain-controlled Mixer
and Output Buffer
The purpose of this mixer is to down-convert the L-band signal in the frequency range of
1452 MHz to 1492 MHz to an IF frequency in the range of about 190 MHz to 230 MHz.
Like the amplifier, the gain of the mixer is controlled by the gain-control circuitry. The IF
signal is buffered and filtered by a one-pole low-pass filter at a 3 dB frequency of about
500 MHz, and then it is fed to the single-ended output pin IF.
Gain-control Circuitry
The gain-control circuitry measures the signal power, compares it with a certain power
level and generates control voltages for the gain-controlled amplifier and mixer. An
equivalent circuit of this functional block is shown in Figure 6.
In order to meet this functionality, the output signal of the buffer amplifier is weakly
band-pass filtered (transition range of about 60 MHz to 550 MHz), rectified, low-pass fil-
tered and fed to a comparator whose threshold can be defined by an external resistor,
RTH, at pin TH. By varying the value of this resistor, a power threshold of about -33 dBm
to -20 dBm can be selected. In order to achieve a good intermodulation ratio, it is recom-
mended to keep the power threshold below -25 dBm. An appropriate application is
shown in Figure 3. Depending on the selection made by the comparator, a charge pump
charges or discharges a capacitor which is applied to the AGC pin. By varying this
capacitor, different time constants of the AGC loop can be realized. The voltage arising
at the AGC pin is used to control the gain setting of the gain-controlled amplifier and
mixer. The voltage at pin AGC is in the range of 5.75 V for maximum gain and 0.3 V for
minimum gain. This voltage can be use to control a dual-gate GaAs-FET in front of the
U2730B-N to achieve an extended AGC range. By applying an external voltage to the
AGC pin, the internal AGC loop can be overdriven.
Voltage-controlled
Oscillator
A voltage-controlled oscillator supplies a LO signal to the mixer. An equivalent circuit of
this oscillator is shown in Figure 7. In the application circuits Figure 8 and Figure 9, a
ceramic coaxial resonator is applied to the oscillator's TANK and VREF pins. It should
be noted that Vref has to be blocked carefully. Figure 9 shows a different application
where the oscillator is overdriven by an external oscillator. In any case, a DC path at a
low impedance must be established between the TANK and VREF pins. The output sig-
nal of the oscillator is fed to the LO divider block of the frequency synthesizer unit which
locks the VCO's frequency on the frequency of a reference oscillator. Figure 5 shows
the typical phase-noise performance of the oscillator in locked state.
5
4719A–DAB–05/03
Overall Properties of the The overall gain of this circuit amounts to 24 dB, the gain-control range is about 30 dB.
With a new AGC concept in the amplifier and mixer, the U2730B-N reaches better inter-
modulation distances (DIM3) at higher IF output power levels.
Signal Path
Power Save Mode
For VPSM > 2 V (pin 1) the power consumption in the analog part (gain-controlled
amplifier and mixer and gain-controlled circuitry) is reduced by 80%. The VCO and the
PLL is not influenced by the power-down mode.
Frequency Synthesizer
The frequency synthesizer block consists of a reference oscillator, a reference divider, a
LO divider in order to divide the frequency of the internal oscillator, a tri-state phase
detector, a lock detector, a programmable charge pump, a loop filter amplifier, a control
interface and a test interface. The control interface is accessed by three control pins, CI,
SI1 and SI2. The test interface provides test signals which represent output signals of
the reference and the LO divider.
The purpose of this unit is to lock the frequency fVCO of the internal VCO on the fre-
quency fref of the reference signal applied to the input pin OSCB phase-locked loop
according to the following relation:
fVCO = SF Pꢀfref /SFref
where: SF = 2464,
SFref is the scaling factor of the reference divider according to Table 1
Table 1. Scaling Factors of the Reference Frequency
Reference Oscillator
Voltage at Pin SI1
GND
Voltage at Pin SI2
OPEN
VCC
SF
ref
36
Frequency
18.432 MHz
GND
33
48
65
63
64
35
32
49
–
GND
GND
24.576 MHz
OPEN
OPEN
OPEN
VCC
OPEN
VCC
–
–
GND
32.768 MHz
17.920 MHZ
16.384 MHz
–
OPEN
VCC
VCC
VCC
GND
Reference Oscillator
An on-chip crystal oscillator generates the reference signal which is fed to the reference
divider. By connecting a quartz crystal to pins OSCE and OSCB according to Figure 10,
this oscillator generates a highly stable reference signal. The U2731B (Atmel’s one-chip
front-end IC) offers the reference signal at pin FREF. This reference signal (LC-filtered
to suppress harmonics) can be used to overdrive the oscillator. In this application (see
Figure 11) the reference signal has to be applied to the pin OSCB and the pin OSCE
must be left open.
6
U2730B-N
4719A–DAB–05/03
U2730B-N
Reference Divider
Nine different scaling factors of the reference divider can be selected by different volt-
age settings at the input pins SI1, SI2: 32, 33(1), 35, 36, 48, 49(1), 65(1), 64, 63(1). The
reference divider factors result in reference oscillator frequencies shown in Table 1.
Note:
1. These scaling factors result in an output frequency of the reference divider of
512 kHz. If harmonics of the Bd. 3 VCO are falling in the L-band reception band, this
spurious can influence the AGC of U2730B-N. That could be a problem for small
incoming signals. In this case it is possible to switch the reference divider from nref to
nref+1.
LO Divider
The LO divider is operated at the fixed division ratio 2464. Assuming the settings
described in the section “Reference Divider”, the oscillator's frequency is controlled to
be 1261.568 MHz in locked state and the output frequency of the RF divider is 512 kHz.
Phase Comparator,
Charge Pump and Loop
Filter
The tri-state phase detector causes the charge pump to source or to sink current at the
output pin PD depending on the phase relation of its input signals which are provided by
the reference and the RF divider respectively. By means of the control pin CI, two differ-
ent values of this current can be selected, and furthermore the charge-pump current can
be switched off.
The input of the high-gain amplifier (output pin CD) which is implemented in order to
construct a loop filter, as shown in the application circuit, can be switched to GND by
means of the control pin CI (see Table 2). In the application circuit, the loop filter is com-
pleted by connecting the pins PD and CD by an appropriate RC network.
Lock Detector
Test Interface
An internal lock detector checks if the phase difference of the input signals of the phase
detector is smaller than approximately 250 ns in seven subsequent comparisons. If a
phase lock is detected, the open collector output pin PLCK is set to HIGH. It should be
noted that the output current of this pin must be limited by external circuitry as it is not
limited internally. If the voltage at the control pin CI is chosen to be half the supply volt-
age, or if this control pin is left open, the lock-detector function is deactivated and the
logical value of the PLCK output is undefined.
If the input control pin CI is left open (high impedance state), a test signal which moni-
tors the output frequency of the reference divider appears at the output pin TI.
In analogy to the reference divider a test signal which monitors the output frequency of
the RF divider appears at the test interface output pin TI if the input control pin CI is con-
nected to VCC/2.
Table 2. Control Interface (CI) Settings
CI
GND
Vs
PD
200 µA
PLCK
ok
TI
–
–
300 µA
ok
VCC/2
Open
0 µA
Undefined
Undefined
RF divider
Reference divider
Connected to GND
7
4719A–DAB–05/03
Absolute Maximum Ratings
Parameters
Pins
Symbol
VCC
Value
-0.3 to +9.5
750
Unit
V
Supply voltage
RF input voltage
Voltage at pin AGC
Voltage at pin TH
3, 9, 20 and 28
25 and 26
VRF
mVpp
V
18
17
VAGC
VTH
0.5 to 6
-0.3 to +4.0
V
Input voltage at pin TANK
(internal oscillator overdriven)
5
VTANK
1
Vpp
Current at IF output
19
IIF
OSCB
CI, SI1, SI2, PD
IPLCK
4.0
1
mA
Vpp
V
Reference input voltage (diff.)
Control input voltage
PLCK output current
PLCK output voltage
Junction temperature
Storage temperature
15
1, 2, 10 and 27
-0.3 to +9.5
0.5
14
14
mA
V
VPLCK
-0.3 to +5.5
125
Tj
LC
LC
Tstg
-40 to +125
Operating Range
Parameters
Pins
Symbol
VCC
Value
Unit
V
Supply voltage
Ambient Temperature
3, 9, 20 and 28
8 to 9.35
-40 to +85
Tamb
LC
Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient SSO28 (mod.)
RthJA
50
K/W
Electrical Characteristics
Operating conditions: VCC = 8.5 V, Tamb = 25LC, see application circuit (Figure 8), unless otherwise specified
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
pRF = -60 dBm
VPSM < 0.5 V
Supply current (max. gain)
IS,MAX
40
48
mA
mA
mA
A
pRF = -10 dBm
VPSM < 0.5 V
Supply current (min. gain)
IS,MIN
IS,PD
41
20
50
24
B
A
Supply current
(power save mode)
pRF = -10 dBm
VPSM > 2 V
Amplifier Mixer Pin 26
26 J 19
Maximum conversion gain pRF = -60 dBm
gc,max
gc,min
ꢀgc
20
28
24
-8
dB
dB
dB
A
B
A
Minimum conversion gain
AGC range
pRF = -15 dBm
32
Third order 2 tone
intermodulation ratio
pRF1 + pRF2 = -10 dBm
pRF1 + pRF2 = -15 dBm
30
35
35
40
dB
dB
B
A
dim3
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
8
U2730B-N
4719A–DAB–05/03
U2730B-N
Electrical Characteristics (Continued)
Operating conditions: VCC = 8.5 V, Tamb = 25LC, see application circuit (Figure 8), unless otherwise specified
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
DSB noise figure
(50-ꢁ system)
Maximum gain
Minimum gain
10
30
dB
dB
NF
D
RF Input
26
Frequency range
Maximum input power
Input impedance
IF Output
fin,RF
pin,max,RF
Zin,RF
1400
1550
MHz
dBm
C
C
D
dim3 O 20 dB
-6
200 ||ꢂ1
ꢁ || pF
19
Frequency range
Output impedance
Voltage standing wave ratio
Gain Control
fout,IF
Zout,IF
150
250
MHz
C
D
D
50
ꢁ
VSWRIF
2.0
Threshold adjustment
External resistor
17
18
RTH
ICP,P
100
100
kꢁ
D
A
pRF = -10 dBm
VAGC = 3.5 V
75
125
-75
0.6
µA
Charge pump current
pRF = -60 dBm
ICP,N
-125
-100
0.1
µA
V
A
A
A
VAGC = 3.5 V
Minimum gain control
voltage
pRF = -10 dBm
pRF = -60 dBm
18
VAGCmin
VAGCmax
Maximum gain control
voltage
18
5.5
5.75
V
VCO
5
Frequency
fLO
1000
1261.568
-75
1500
MHz
dBc/Hz
dBm
Phase noise
Minimum input power
1 kHz distance
L1kHz
C
C
VCO over-driven, see
“Application Circuit”
(Figure 8)
pLO,MIN
-11
Maximum input power
pLO,MAX
-5
dBm
C
Frequency Synthesizer
RF divide factor
SF
2464
A
SI1 = GND, SI2 = GND
SI1 = GND, SI2 = VCC
SI1 = GND, SI2 = open
SI1 = VCC, SI2 = GND
SI1 = VCC, SI2 = VCC
SI1 = VCC, SI2 = open
SI1 = open, SI2 = GND
SI1 = open, SI2 = VCC
SI1 = open, SI2 = open
48
33
36
49
32
35
64
63
65
Reference divide factor
SFref
A
Input frequency range
Input sensitivity
fref
Vrefs
Vrefmax
Zref
5
50
30
MHz
mVrms
mVrms
kꢁ || pF
C
C
C
D
15
15
Maximum input signal
Input impedance
300
Single-ended
2.7k || 2.5
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
9
4719A–DAB–05/03
Electrical Characteristics (Continued)
Operating conditions: VCC = 8.5 V, Tamb = 25LC, see application circuit (Figure 8), unless otherwise specified
No. Parameters
Phase Detector
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
Pin CI connected to GND
Pin CI connected to VCC
Pin CI connected to VCC/2
Pin CI open, Pin
13
IPD2
IPD1
IPD1,tri
VPD
160
240
200
300
240
360
100
0.3
µA
µA
nA
V
A
A
A
A
B
C
Charge-pump current
Output voltage PD
13
Internal reference frequency
Typical tuning voltage range
Lock Indication PLCK
Leakage current
fPD
512
kHz
V
12
Vtune
0.3
5
14
VPLCK = 5.5 V
IPLCK
10
µA
V
A
A
Saturation voltage
IPLCK = 0.25 mA
VPLCK,sat
0.5
Control Inputs SI
2 and 27
Pin connected to GND
Pin open
VL
VM
VH
0
0.9
0
0.1
1
VCC
A
A
A
Input voltage
open
Pin connected to VCC
VCC
Control Input CI
10
Pin connected to GND
Pin connected to VCC/2
Pin open
VL
VM
0.1
VCC
VCC
A
A
A
A
0.5
Input voltage
Vopen
VH
open
Pin connected to VCC
0.9
1
VCC
Test Interface TI
11
Reference test frequency
LO test frequency
Pin CI open
ftest,ref
ftest,LO
512
512
kHz
kHz
B
B
Pin CI = VCC/2
Rload O 1 Mꢁ, Cload
?
Voltage swing
15 pF, Pin CI open or
VCC/2
Vsw
400
mVpp
C
Power-save Mode PSM
1
PSM not active
PSM active
VPSM
VPSM
0.6
V
V
A
A
2.0
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Example: reference divider factor = 35, fREF = 17.92 MHz, charge-pump current = 200 µA
10
U2730B-N
4719A–DAB–05/03
U2730B-N
Gain Control
Charateristics
Operating conditions: VCC = 8.5 V, Tamb = 27LC, fRF = 1490 MHz, FLO = 1261.568 MHz
Figure 3. IF Output Power (Pin 19)
-10
-15
-20
-25
Rth = 100 kꢀ
-30
-35
-40
-60
-50
-40
-30
-20
-10
0
pRF (dBm)
Figure 4. Gain Control Voltage (Pin 11)
6
5
Rth = 100 kꢀ
4
3
2
1
0
-60
-50
-40
-30
-20
-10
0
pRF (dBm)
11
4719A–DAB–05/03
Phase-noise
Performance
Measurement conditions:
Values acquired at Pin 19 with HP 70000 spectrum analyzer. RF input (Pin 26) is
blocked with 100 pF to GND.
A low phase-noise signal generator (Marconi 2042) was taken as PLL reference.
Figure 5. Phase-noise Performance operating Conditions: fREF = 17.92 MHz, -10 dB, IPD = 200 µA
RL -29.29 dBm
ATTEN 10 dB
10.00 dB/DIV
< -75 dBc/Hz
Span 50.00 kHz
ST 15.00 sec
Center 1.261 568 GHz
RB 100 Hz VB 100 Hz
12
U2730B-N
4719A–DAB–05/03
U2730B-N
Equivalent Circuits
Figure 6. AGC Control Circuit
Gain-
controlled
mixer
Gain-
controlled
amplifier
VRef1
550 MHz
IF
output
60 MHz
VRef2
AGC
TH
Rth
Figure 7. VCO Circuit
VCC
BBY51
VTune
47k
1.8 p
15 p
TANK
Resonator
1 p
VREF
100 p
Resonator: Ceramic coaxial resonator
Murata 3 x 3 mm, 1.6 GHz
DRR030 KE1R600TC
13
4719A–DAB–05/03
Figure 8. Application Circuit
VAGC
3.3 ꢀF
8.5 V
IF
8.5 V
RF
100 pF
10 nF
100 pF
1 nF 100K
100 pF
18 pF
33 pF
Quartz
100
pF
crystal
1 nF
10 nF
100 pF
68 pF
25
NRF
22
28
27
26
24
23
21
20
19
18
17
16
15
GND
VCC4 SI1
RF
GND GND
GND VCC3 IF AGC TH OSCE OSCB
U2730B-N
PSM SI2 VCC1VREF TANK GND
GND VCC2 CI
TI
11
CD
12
PD PLCK
13 14
GND
7
1
2
3
4
5
6
8
9
10
Power save
5 V
1 pF
100 pF
10 nF
Lock
indication
10 nF
56K
*100 pF
100 pF
100 pF
1 nF
8.5 V
1.8 pF
8.5 V
1K
1K
*3.3
nF
47K
* optional
*3.3
nF
1 nF
15 pF
D1
14
U2730B-N
4719A–DAB–05/03
U2730B-N
Application Circuit
for External LO
Signal
With an external LO signal it is possible to overdrive the VCO. In this case, the internal
VCO acts as a LO buffer.
Figure 9. Application Circuit for External LO Signal
ext. LO signal
TANK
(50 ꢀ signal gen.)
PLO = -10 dBm
100 p
470 nH
VREF
50
1 n
Figure 10. Reference Oscillator Operation
Reference devider
68 pF
OSCB
33 pF
18 pF
OSCE
Quartz crystal
Figure 11. Rerference Oscillator Overdriven
Reference devider
OSCB
Reference signal
C1
L1
OSCE
15
4719A–DAB–05/03
Ordering Information
Extended Type Number
Package
SSO28
SSO28
Remarks
U2730B-NFS
Tube
U2730B-NFSG1
Taped and reeled according to IEC 286-3
Package Information
5.7
5.3
Package SSO28
Dimensions in mm
9.10
9.01
4.5
4.3
1.30
0.15
0.15
0.05
0.25
0.65
6.6
6.3
8.45
28
15
technical drawings
according to DIN
specifications
1
14
16
U2730B-N
4719A–DAB–05/03
Atmel Corporation
Atmel Operations
2325 Orchard Parkway
San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 487-2600
Memory
RF/Automotive
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San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
Theresienstrasse 2
Postfach 3535
74025 Heilbronn, Germany
Tel: (49) 71-31-67-0
Fax: (49) 71-31-67-2340
Regional Headquarters
Microcontrollers
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San Jose, CA 95131
Tel: 1(408) 441-0311
Fax: 1(408) 436-4314
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
Tel: 1(719) 576-3300
Europe
Atmel Sarl
Route des Arsenaux 41
Case Postale 80
CH-1705 Fribourg
Switzerland
Tel: (41) 26-426-5555
Fax: (41) 26-426-5500
Fax: 1(719) 540-1759
Biometrics/Imaging/Hi-Rel MPU/
High Speed Converters/RF Datacom
Avenue de Rochepleine
BP 123
38521 Saint-Egreve Cedex, France
Tel: (33) 4-76-58-30-00
La Chantrerie
BP 70602
44306 Nantes Cedex 3, France
Tel: (33) 2-40-18-18-18
Fax: (33) 2-40-18-19-60
Asia
Room 1219
ASIC/ASSP/Smart Cards
Zone Industrielle
13106 Rousset Cedex, France
Tel: (33) 4-42-53-60-00
Fax: (33) 4-42-53-60-01
Fax: (33) 4-76-58-34-80
Chinachem Golden Plaza
77 Mody Road Tsimshatsui
East Kowloon
Hong Kong
Tel: (852) 2721-9778
Fax: (852) 2722-1369
1150 East Cheyenne Mtn. Blvd.
Colorado Springs, CO 80906
Tel: 1(719) 576-3300
Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
Japan
Fax: 1(719) 540-1759
Scottish Enterprise Technology Park
Maxwell Building
East Kilbride G75 0QR, Scotland
Tel: (44) 1355-803-000
Tel: (81) 3-3523-3551
Fax: (81) 3-3523-7581
Fax: (44) 1355-242-743
e-mail
literature@atmel.com
Web Site
http://www.atmel.com
Disclaimer: Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard
warranty which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any
errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and
does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are
granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use
as critical components in life support devices or systems.
© Atmel Corporation 2003. All rights reserved.
Atmel® and combinations thereof are the registered trademarks of Atmel Corporation or its subsidiaries.
Other terms and product names may be the trademarks of others.
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