U2741B [ATMEL]
UHF ASK/FSK TRANSMITTER; 超高频ASK / FSK发射器
| 型号： | U2741B |
| 厂家： | 
ATMEL |
| 描述： | UHF ASK/FSK TRANSMITTER |
| 文件： | 总9页 (文件大小：186K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Very High Transmitting Frequency Accuracy Compared to SAW Solutions
(Enables Receivers at Lower Bandwidth than with SAW Resonators)
• Lower Cost than the Usual Discrete Solutions Using SAW and Transistors
• Supply Voltage 2.0 V to 5.5 V in the Temperature Range -20LC to 70LC
Supply Voltage 2.2 V to 5.5 V in the Temperature Range -40LC to 85LC
• XTO Output for Clocking the Microcontroller, Thereby Together with the ATAR090 or
ATAR890 Results in the Optimum System Cost-effectiveness
• One-chip Solution with Minimum External Circuitry
UHF ASK/FSK
Transmitter
• Very Small SSO16 Package, Pitch 0.635, 150 mil
• “Single-ended Open-collector” Output (Same Antennas as in Discrete Solutions Can
Be Used, Simpler Adaptation of Magnetic Loop Antennas)
• Very Large FSK Frequency Deviation Achievable by ±100 ppm Pulling of the Reference
Crystal
• Enables Receivers at Lower Bandwidth than with SAW Resonators
• ESD Protection According to MIL-STD.883 (4 KV HBM) Except Pins XTO1/ 2,
ANT and LF
U2741B
Electrostatic sensitive device.
Observe precautions for handling.
Description
The U2741B is a PLL transmitter IC which has been especially developed for the
demands of RF low-cost data transmission systems at data rates up to 20 kBaud.
The transmitting frequency range is 300 MHz to 450 MHz. The device can be used in
both FSK and ASK systems.
Rev. 4733A–RKE–11/03
Figure 1. System Block Diagram
UHF ASK/FSK
Remote control transmitter
UHF ASK/FSK
Remote control receiver
1 Li cell
U3741BM
U2741B
1...3
Demod.
Control
XTO
Encoder
ATARx9x
PLL
IF Amp
Keys
Antenna Antenna
XTO
VCO
PLL
Power
amp.
LNA
VCO
Figure 2. Block Diagram
ASK
DIVC
OR
FSK
VCC
PWRSET
PWRVCC
ANT
Power
up
PA
VCO
CLK
f
PWRGND1
GND
64
PWRGND2
LFVCC
LFGND
LF
f
XTO
n
XTO1
XTO2
U2741B
2
U2741B
4733A–RKE–11/03
U2741B
Pin Configuration
Figure 3. Pinning SSO16
DIVIC
ASK
FSK
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
PWRSET
PWRVCC
ANT
VCC
CLK
GND
U2741B
PWRGND1
PWRGND2
XTO1
LFVCC
LFGND
LF
XTO2
Pin Description
Pin
Symbol
Function
1
ASK
Modulation input ASK
Modulation input FSK
Supply voltage
Clock output
2
FSK
3
VCC
4
CLK
5
GND
Ground
6
LFVCC
LFGND
LF
Supply voltage VCO
VCO ground
7
8
Circuit PLL loop
FM modulation output
Connection for crystal
Power GND2
9
XTO2
10
11
12
13
14
15
XTO1
PWRGND2
PWRGND1
ANT
Power GND1
RF output
PWRVCC
PWRSET
Supply voltage power amplifier
Applied to VCC
Pitch factor setting for crystal
L: high crystal frequency
H: low crystal frequency
16
DIVIC
3
4733A–RKE–11/03
General Description
The fully integrated VCO and the “single-ended open-collector” output allow particularly
simple, low-cost RF miniature transmitters to be assembled. The single-ended output
enables a considerably simplified adaptation of both a magnetic loop antenna of any
form or a ꢀ/4 antenna. This is because the load impedance must not be balanced as
would be the case with a differential output.
The XTO's frequency can be selected at either 13.56 MHz (USA 9.844 MHz) or
6.78 MHz (USA 4.9219 MHz). Thus, it is possible to use not only exceptionally small
SMD crystals at 13.56 MHz but also very low-cost 6.78 MHz crystals in a wired metal
package (e.g., in the HC49S housing). The frequency is selected by connecting pin 16
(DIVC) to either GND or VS.
At high frequencies, crystals have a very fast start-up time (< 1.5 ms at 13.56 MHz,
< 3 ms at 6.78 MHz), whereby a wait time of 5 to 10 ms is required until the transmitter
IC is locked. This means that the processor does not need to poll a lock detect output.
Functional
Description
The IC can be switched on at both the FSK and the ASK input. The IC's ChipSelect is
performed by the logical OR operation of ASK and FSK input. In the case of VFSK
,
VASK ? 0.3 V, the power-down supply current is ISoff < 0.35 µA. The ASK input activates
the power amplifier and the PLL. The FSK input only activates the PLL and, if capacitor
C3 is installed, pulls the crystal to the lower frequency, whereby the transmitter is FSK
modulated. After switching on at FSK, the VCO locks onto the 32 or 64 times higher fre-
quency of the crystal oscillator.
FSK Transmission
ASK Transmission
The U2741B is switched on by VFSK = VS. 5 ms later, VS is applied to VASK. The output
can then be modulated by means of pin FSK. This is done by connecting capacitor C3 in
parallel to the load capacitor C4.
The U2741B is activated by VFSK = VS. VASK remains 0 V for 5 ms, then the output power
can be modulated by means of pin ASK. In this case, VFSK remains = VS during the mes-
sage, the capacitor C3 is not mounted.
Take-over of the Clock
Pulse in the
Microcontroller
The clock of the crystal oscillator can be used for clocking the microcontroller. The
ATAR090 and ATAR890 have the special feature of starting with an integrated RC oscil-
lator to switch on the U2741B with VFSK = VS. 5 ms later, the 3.39-MHz clock frequency
is present, so that the message can be sent with crystal accuracy.
Application Circuit
The following component values are recommendations for a typical application. C5, C6,
and C7 are block capacitors. The values of these capacitors depend on the board layout.
C5 = 1 nF, C6 = 1 nF, and C7 = 22 nF are typically used here. For C5, the impedance
between f = 100 MHz and f = 1 GHz should be as low as possible.
C3 is not needed in ASK transmitter applications. In the case of FSK, C3 is selected in
such a way that the desired transmission frequency deviation is achieved (typical
±30 kHz). The capacitance here depends upon the crystal's load capacity (C4) recom-
mended by the manufacturer of the crystal. C2 = 3.9 nF, C1 = 15 nF, and R4 = 220 ꢁ.
C
Loop1 and CLoop2 are selected so that the antenna oscillates in resonance and the adap-
tation to the appropriate impedance transformation is possible.
LFeed is an inductor for the antenna's DC current supply. A typical value is
LFeed = 220 nH. LFeed can be either printed on the PC board or be a discrete component.
4
U2741B
4733A–RKE–11/03
U2741B
Output Power
Measurement
The output network [as shown in Figure 4] can be used for output power evaluation, the
exact values of L10 and C10 depend on the layout.
L10 and C10 form the transformation network to adopt the output impedance of the IC to
50 ꢁ. Table 1 shows the values for an output power of 2 mW and an RPWRSET = 1.2 kꢁ.
Table 1. Transformation Network
f/MHz
315
C10/pF
2.7
L10/nH
56
ZLoad_opt/ꢀ
260 + j330
185 + j268
433.92
1.8
33
Figure 4. Measurement Output Network
VS
PWRVCC
L10
ANT
ZLoad-opt
C10
50 ꢀ
Figure 5. Application Circuit
+VS = 2.0 ... 5.5 V
ASK
DIVC
ASK
FSK
1
16
OR
CLoop2
FSK
2
PWRSET
15
PWRVCC
14
ANT
13
PWRGND1
12
PWRGND2
11
XTO1
10
RPWRSET
Power
up
VCC
3
C7
LFeed
C5
CLK
4
VCO
f
PA
CLK
3.39 MHz
CLoop1
GND
5
64
LFVCC
6
C6
f
13.56 MHz
XTO
LFGND
7
n
C4
C1
LF
8
XTO2
9
R4
U2741B
C3
Antenna
C2
5
4733A–RKE–11/03
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameters
Symbol
VS
Min.
Max.
6
Unit
V
Supply voltage
Power dissipation
Junction temperature
Storage temperature
Ambient temperature
Ptot
250
150
125
105
mW
LC
Tj
Tstg
-55
-40
LC
Tamb
LC
Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient
RthJA
180
K/W
Electrical Characteristics
All parameters are refered to GND (pin 5). The possible operating ranges refer to different circuit conditions:
VS = 2.0 V to 5.5 V at Tamb = -20LC to +70LC, VS = 2.2 V to 5.5 V at Tamb = -40LC to +85LC (typically 25LC, 3 V)
Parameters
Test Conditions
Symbol
ISoff
Min.
Typ.
Max.
Unit
µA
Supply current (power down)
VASK, VFSK ? 0.3 V, VS < 3.6 V
0.35
6.2
Supply current (power up, output OFF) VASK = GND, VFSK = VS, Vs = 3 V
ISon
4.7
10
mA
mA
Supply current (power up, output ON)
V
ASK = VS, VS = 3 V, RPWRSET = 1.2 kꢀ
VS = 3 V, Tamb = 25LC, f = 433.92 MHz
PWRSET = 1.2 kꢀ
RPWRSET = 1.8 kꢀ
amb = -40LC to +85LC, f = 433.92 MHz,
IStransmit
12.5
Output power
R
PRef
PRef
1.5
-0.5
3
1
5
3
dBm
dBm
T
VS = 3.0 V
VS = 2.4 V
ꢁPRef
ꢁPRef
-1.5
-4.0
dB
dB
Output power variation for the full
temperature range
T
amb = -20LC to +85LC, f = 433.92 MHz,
VS = 2.0 V
out = PRef + ꢁPRef
ꢁPRef
-5.5
dB
dB
P
Output power variation for
f = 315 MHz compared to
f = 433.92 MHz
f = 315 MHz
out = PRef + ꢁPRef
ꢁPRef
1.5
P
at Pout = 2.0 mW,
the load impedance must be selected to
meet the Vout maximum requirement
the supply current is not dependent on
the load impedance tolerance
Maximum peak output
antenna voltage
Voutmax
VS - 0.7 V
V(peak)
at Tamb = 25LC
fo ±(n P fPC) where fPC = 6.78 MHz
Load capacitance at CLK ? 3 pF
f = 230 MHz to 470 MHz
f < 230 MHz, f > 470 MHz
Spurious emission
Em
Em
-40
-58
dBC
dBC
6
U2741B
4733A–RKE–11/03
U2741B
Electrical Characteristics (Continued)
All parameters are refered to GND (pin 5). The possible operating ranges refer to different circuit conditions:
VS = 2.0 V to 5.5 V at Tamb = -20LC to +70LC, VS = 2.2 V to 5.5 V at Tamb = -40LC to +85LC (typically 25LC, 3 V)
Parameters
Test Conditions
Symbol
Min.
Typ.
Max.
Unit
M-version: at Tamb = 25LC
N-version: full temperature range
(monitoring)
Crystal frequency = 13.56 MHz
fXTO
13.56 -
30 ppm
13.56
6.78
13.56 +
30 ppm
MHz
MHz
Oscillator frequency XTO
Crystal frequency = 6.78 MHz
fXTO
6.78 -
6.78 +
30 ppm
30 ppm
Load capacity of the crystal must be
selected accordingly
For best LO noise
Loop bandwidth
Phase noise PLL
Loop filter components:
C2 = 3.9 nF, C1 = 15 nF, R4 = 220 ꢀ
BLoop
100
kHz
Referring to the phase comparator
PNPLL
-111
-105
dBC/Hz
fPC = 6.78 MHz
at 1 MHz
at 36 MHz
PNVCO
PNVCO
-91
-123
-87
-119
Phase noise VCO
dBC/Hz
MHz
MHz
pF
Frequency range of the VCO
fVCO
Clkout
CCLK
300
450
Clock output
(CMOS microcontroller compatible)
fout/128
Load capacitance at CLK
10
fXTO = 13.56 MHz
fXTO = 9.84 MHz
fXTO = 6.78 MHz
fXTO = 4.90 MHz
Rs
Rs
Rs
Rs
80
100
150
225
Series resonance R of the crystal
ꢀ
Duty cycle of the
modulation signal = 50%
FSK modulation frequency rate
ASK modulation frequency rate
fmodFSK
fmodASK
0
0
20
20
kHz
kHz
Duty cycle of the
modulation signal = 50%
CLK output
- Output current Low
- Output current Low
- Output current High
- Output current High
V
CLK = 0.2 P VS
Iol
Iol
Ioh
Ioh
150
200
-150
-200
µA
µA
µA
µA
VCLK = 0.3 P VS
VCLK = 0.8 P VS
VCLK = 0.7 P VS
100
ASK input
- Low level input voltage
- High level input voltage
- Input current High
VASKl
VASKh
IASKh
0.3
V
V
µA
1.7
1.7
140
FSK input
- Low level input voltage
- High level input voltage
- Input current High
VFSKl
VFSKh
IFSKh
0.3
V
V
µA
140
7
4733A–RKE–11/03
Ordering Information
Extended Type Number
Package
SSO16
SSO16
Remarks
Tube, optimized power-supply rejection, value of C4
differs from M-version, enhanced XTO stability
U2741B-NFB
U2741B-NFBG3
Taped and reeled, see above
Package Information
8
U2741B
4733A–RKE–11/03
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4733A–RKE–11/03
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