U2790B_06 [ATMEL]
1000-MHz Quadrature Modulator; 1000 MHz的正交调制器
| 型号： | U2790B_06 |
| 厂家： | 
ATMEL |
| 描述： | 1000-MHz Quadrature Modulator |
| 文件： | 总16页 (文件大小：313K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Supply Voltage 5V (Typically)
• Very Low Power Consumption: 150 mW (Typically) for –1 dBm Output Level
• Very Good Sideband Suppression by Means of Duty Cycle Regeneration of the LO
Input Signal
• Phase Control Loop for Precise 90° Phase Shifting
• Power-down Mode
• Low LO Input Level: –10 dBm (Typically)
• 50-ΩSingle-ended LO and RF Port
• LO Frequency from 100 MHz to 1 GHz
• SO16 Package
1000-MHz
Quadrature
Modulator
Benefits
• No External Components Required for Phase Shifting
• Adjustment Free, Hence Saves Manufacturing Time
• Only Three External Components Necessary, this Results in Cost and Board Space
Saving
U2790B
Electrostatic sensitive device.
Observe precautions for handling.
1. Description
The U2790B is a 1000-MHz quadrature modulator using Atmel®’s advanced UHF pro-
cess. It features a frequency range from 100 MHz up to 1000 MHz, low current
consumption, and single-ended RF and LO ports. Adjustment-free application makes
the direct converter suitable for all digital radio systems up to 1000 MHz, e.g., GSM,
ADC, JDC.
Figure 1-1. Block Diagram
SPU
PU
1
6
8
7
BBAI
BBAI
Power
up
VS
5,4
RFO
12
15
0°
Frequency
doubler
Duty cycle
regenerator
90°/control
loop
Σ
LOi
90°
3
16
9
Phadj
BBBi
10
BBBI
2,11,13,14
GND
4583D–CELL–07/06
2. Pin Configuration
Figure 2-1. Pinning SO16
PU
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
Phadj
Phadj
GND
GND
RFO
GND
LOi
VS
VS
SPD
GND
BBBi
BBBi
BBAi
BBAi
Table 2-1.
Pin Description
Pin
Symbol
PU
Function
1
Power-up input
Ground
2, 11, 13, 14
GND
RFo
3
4, 5
6
RF output
VS
Supply voltage
SPU
Settling time power-up
Baseband input A
7
BBAi
BBAi
BBBi
BBBi
LOi
8
Baseband input A inverse
Baseband input B
9
10
12
15, 16
Baseband input B inverse
LO input
Phadj
Phase adjustment (not necessary for regular applications)
2
U2790B
4583D–CELL–07/06
U2790B
3. Absolute Maximum Ratings
Parameters
Symbol
Value
6
Unit
V
Supply voltage
VS
Vi
Input voltage
0 to VS
125
V
Junction temperature
Storage temperature range
Tj
°C
°C
TStg
–55 to +125
4. Operating Range
Parameters
Symbol
VS
Value
Unit
V
Supply voltage range
Ambient temperature range
4.5 to 5.5
–40 to +85
Tamb
°C
5. Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient SO16
RthJA
110
K/W
6. Electrical Characteristics
Test conditions (unless otherwise specified): VS = 5V, Tamb = 25°C, referred to test circuit, system impedance ZO = 50Ω, fLO = 900 MHz,
PLO = –10 dBm, VBBi = 1 Vpp differential.
Parameters
Test Conditions
Pin
4, 5
4, 5
Symbol
Min.
4.5
24
Typ.
Max.
5.5
Unit
V
Type*
No.
1.1
1.2
2
Supply voltage range
Supply current
VS
IS
A
A
30
37
mA
Baseband Inputs
Input-voltage range
(differential)
7-8,
9-10
2.1
2.2
VBBi
ZBBi
1000
3.2
1500
mVpp
D
D
Input impedance
(single ended)
kΩ
Input-frequency
range(5)
2.3
2.4
2.5
fBBi
0
250
2.65
<1
MHz
V
D
A
D
Internal bias voltage
VBBb
TCBB
2.35
2.5
0.1
Temperature
coefficient
mV/°C
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. The required LO level is a function of the LO frequency.
2. In reference to an RF output level ≤ –1 dBm and I/Q input level of 400 mVpp differential.
3. Sideband suppression is tested without connection at pins 15 and 16. For higher requirements a potentiometer can be
connected at these pins.
4. For Tamb = –30°C to +85°C and VS = 4.5V to 5.5V.
5. By low impedance signal source.
3
4583D–CELL–07/06
6. Electrical Characteristics (Continued)
Test conditions (unless otherwise specified): VS = 5V, Tamb = 25°C, referred to test circuit, system impedance ZO = 50Ω, fLO = 900 MHz,
PLO = –10 dBm, VBBi = 1 Vpp differential.
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
No.
3
LO Input
3.1
3.2
3.3
Frequency range
Input level(1)
12
fLOi
PLOi
ZiLO
50
1000
–5
MHz
dBm
Ω
D
D
D
–12
–10
50
Input impedance
Voltage standing
wave ratio
3.4
VSWRLO
DCRLO
1.4
2
D
D
3.5
4
Duty cycle range
RF Output
0.4
–5
0.6
4.1
Output level
3
PRFo
–1
+2
dBm
dB
B
B
fLO = 900 MHz
fLO = 150 MHz
30
32
35
35
4.2
4.3
LO suppression(2)
LORFo
Sideband
fLO = 900 MHz
fLO = 150 MHz
35
30
40
35
SBSRFo
dB
B
suppression(2, 3)
4.4
4.5
Phase error(4)
Pe
Ae
<1
deg.
dB
D
D
Amplitude error
< ±0.25
VBBi = 2V, VBBi = 3V
VBBi = VBBi = 2.5V
–132
–144
4.6
4.7
Noise floor
NFL
dBm/Hz
D
D
VSWR
VSWRRF
1.6
2
3rd-order baseband
harmonic
suppression
4.8
SBBH
35
45
dB
dB
D
D
RF harmonic
suppression
4.9
5
SRFH
35
Power-up Mode
V
PU ≤ 0.5V
5.1
Supply current
4, 5
IPU
10
10
1
1
µA
µs
D
D
VPU = 1V
C
SPU = 100 pF
5.2
Settling time
CLO = 100 pF
CRFo = 1 nF
6 to 3
tsPU
6
Switching Voltage
Power-on
6.1
6.2
1
1
VPUon
4
V
V
D
D
Power-up
VPUdown
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Notes: 1. The required LO level is a function of the LO frequency.
2. In reference to an RF output level ≤ –1 dBm and I/Q input level of 400 mVpp differential.
3. Sideband suppression is tested without connection at pins 15 and 16. For higher requirements a potentiometer can be
connected at these pins.
4. For Tamb = –30°C to +85°C and VS = 4.5V to 5.5V.
5. By low impedance signal source.
4
U2790B
4583D–CELL–07/06
U2790B
7. Diagrams
Figure 7-1. Typical Single Sideband Output Spectrum at VS = 4.5V and VS = 5.5V,
LO = 900 MHz, PLO = –10 dBm, VBBI = 1 VPP (differential) Tamb = 25°C
f
Figure 7-2. Typical GMSK Output Spectrum
5
4583D–CELL–07/06
Figure 7-3. Demo Board Layout
Figure 7-4. OIP3 versus Tamb, LO = 150 MHz, Level –20 dBm
16
VBBI = 0.2 VPP
12
VBBi= 0.4 VPP
8
4
0
-40 -20
0
20
Temperature (°C)
80
100
40
60
6
U2790B
4583D–CELL–07/06
U2790B
Figure 7-5. OIP3 versus Tamb, LO = 900 MHz, Level –10 dBm
12
10
VBBi = 0.4 VPP
8
6
VBBi = 1.0 VPP
4
2
0
100
40
60
-40 -20
0
20
80
Temperature (°C)
Figure 7-6. Output Power versus Tamb
0.5
0
FLO = 150 MHz
-0,5
-1
-1.5
FLO = 900 MHz
-2
-2.5
100
-40
-20
0
20
Temperature (°C)
80
40
60
Figure 7-7. Supply Current versus Tamb
40
30
20
10
0
100
-40 -20
0
20
Temperature (°C)
80
40
60
7
4583D–CELL–07/06
Figure 7-8. Typical S11 Frequency Response of the RF Output
Figure 7-9. Typical VSWR Frequency Response of the RF Output
8
U2790B
4583D–CELL–07/06
U2790B
Figure 7-10. Typical S11 Frequency Response of the LO Input
Figure 7-11. Typical VSWR Frequency Response of the LO input
10
8
6
4
2
0
1000
100
LO Frequency (MHz)
9
4583D–CELL–07/06
Figure 7-12. Typical Supply Current versus Temperature at VS = 5V
60
50
40
30
20
10
100
-40
-20
0
20
40
60
80
Temperature (°C)
Figure 7-13. Typical Output Power versus LO-Frequency at Tamb = 25°C,
VBBI = 230 mVPP (differential)
0
-5
0
200 400 600 800 1000 1200
LO Frequency ( MHz )
1400
Figure 7-14. Typical required VBBi Input Signal (differential) versus LO Frequency for
PO = 0 dBm and PO = –2 dBm
2
1
0
0
200 400 600 800 1000 1200
LO Frequency (MHz)
1400
10
U2790B
4583D–CELL–07/06
U2790B
Figure 7-15. Typical useful LO Power Range versus LO Frequency at Tamb = 25°C
0
-10
-20
-30
-40
-50
0
200 400
600 800 1000 1200
LO Frequency (MHz)
1400
Figure 7-16. Application Circuit
PU
1n
CPU
SPU
Power
down
Ainv
220n
1
6
8
7
Power
down
220n
BBAi
BBAi
A
VS
5,4
VS
100n
1n
RFO
Baseband
processing
100p
12
Duty cycle
regenerator
Frequency
doubler
0°
90°/ control
OUT
LO
Σ
loop
LOi
Phadj
90°
3
10k
15
VS
B
16
9
BBBi
10
220n
BBBi
2,11,13,14
GND
220n
Binv
11
4583D–CELL–07/06
Figure 7-17. Demo Board Layout
12
U2790B
4583D–CELL–07/06
U2790B
8. Application Notes
8.1
Noise Floor and Settling Time
In order to reduce noise on the power-up control input and improve the wide-off noise floor of the
900-MHz RF output signal, capacitor CPU should be connected from pin 6 to ground in the
shortest possible way.
The settling time has to be considered for the system under design. For GSM applications, a
value of CPU = 1 nF defines a settling time, tsPU, equal or less than 3 ms. This capacitance does
not have any influence on the noise floor within the relevant GSM mask. For mobile applications
the mask requirements can be achieved very easily without CPU.
A significant improvement of the wide-off noise floor is obtainable with CPU greater than 100 nF.
Such values are recommended for applications where the settling time is not critical such as in
base stations. Coupling capacitors for LOi and RFO also have a certain impact on the settling
time. The values used for the measurements are CLOi = 100 pF and CRFo = 1 nF.
8.2
Baseband Coupling
The U2790B-FP (SO16) has an integrated biasing network which allows AC coupling of the
baseband signal at a low count of external components. The bias voltage is 2.5V ±0.15V.
Figure 7-17 shows the baseband input circuitry with a resistance of 3.2 kΩ for each asymmetric
input. The internal DC offset between A and A, and B and B is typically < ±1 mV with a maximum
of ±3 mV. DC coupling is also possible with an external DC voltage of 2.5 ±0.15V.
Figure 8-1. Baseband Input Circuitry
Mixer input stage
3.2 kΩ
A
B
,
A
B
,
13
4583D–CELL–07/06
RF Output Circuitry LO Input Circuitry
VS
RFO
3
20
Ω
Figure 8-2. LO Input Circuitry
LO
12
50 Ω
20 pF
14
U2790B
4583D–CELL–07/06
U2790B
9. Ordering Information
Extended Type Number
Package
SO16
Remarks
U2790B-NFPH
Tube, Pb-free
U2790B-NFPG3H
SO16
Taped and reeled, Pb-free
10. Package Information
5.2
4.8
Package SO16
Dimensions in mm
10.0
9.85
3.7
1.4
0.25
0.2
0.4
3.8
0.10
1.27
6.15
5.85
8.89
16
9
technical drawings
according to DIN
specifications
1
8
11. Revision History
Please note that the following page numbers referred to in this section refer to the specific revision
mentioned, not to this document.
Revision No.
History
• Page 3, Abs. Max.Ratings table: Storage temperature values changed
• Page 2, Pin Description table: symbol of Pins 8 and 10 changed
• Put datasheet in a new template
4583D-CELL-07/06
15
4583D–CELL–07/06
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