U4256BM-RSG3 [ATMEL]
Frequency Synthesizer for Radio Tuning; 频率合成调谐收音机
| 型号： | U4256BM-RSG3 |
| 厂家： | 
ATMEL |
| 描述： | Frequency Synthesizer for Radio Tuning |
| 文件： | 总19页 (文件大小：386K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Reference Oscillator up to 15 MHz (Tuned)
• Oscillator Buffer Output (for AM Up/Down Conversion)
• Two Programmable 16-bit Dividers
• Fine-tuning Steps Possible
• Fast Response Time due to Integrated Loop Push-pull Stage
• 3-wire Bus (Enable, Clock and Data; 3 V and 5 V Microcontrollers Acceptable)
• Four Programmable Switching Outputs (Open Drain)
• Three DACs for Software Controlled Tuner Alignment
• Low-power Consumption
• High S/N Ratio
• Integrated Band Gap – only One Supply Voltage Necessary
Frequency
Synthesizer for
Radio Tuning
Description
The U4256BM-R is a synthesizer IC for FM receivers and an AM up-convertion
system in BICMOS technology. Together with the AM/FM IC T4258 or U4255BM, it
performs a complete AM/FM car radio front-end, which is recommended also for RDS
(Radio Data System) applications. It is controlled by a 3-wire bus and also contains
switches and Digital to Analog Converters (DACs) for software-controlled alignment of
the AM/FM tuner. The U4256BM-R is the pin-compatible succesor IC of U4256BM-N.
U4256BM-R
Preliminary
Pin Configuration
Figure 1. Pinning SSO20
Rev. 4562C–AUDR–08/04
Pin Description
Pin
Symbol
PDO
Function
1
Phase detector output
Pulsed current output
Digital-to-analog converter 1
Digital-to-analog converter 2
Digital-to-analog converter 3
Supply voltage analog part
Switching output 1
Switching output 2
Switching output 3
Switching output 4
Ground, digital part
Reference oscillator output
Reference oscillator input
Capacitor band gap
Oscillator buffer output
Data input
2
PD
3
DAC1
DAC2
DAC3
VS
4
5
6
7
SWO1
SWO2
SWO3
SWO4
GND
8
9
10
11
12
13
14
15
16
17
18
19
20
OSCOUT
OSCIN
V5
MX2LO
DATA
CLK
Clock
EN
Enable
FMOSCIN
GNDan
FM-oscillator input
Ground, analog part
Figure 2. Block Diagram
SWO1 SWO2 SWO3 SWO4
7
8
9
10
Tuning
13
12
OSCIN
Oscillator
Switching outputs
DAC3
3-bit
OSCOUT
5
DAC3
V
15
Ref
OSC
buffer
MX2LO
DAC2
DAC1
4
3
DAC2
DAC1
17
16
18
CLK
DATA
EN
3W-
bus
interface
R-
divider
DAC
AM/FM
V
Ref
1
2
19
FM-
preamp
N-
divider
Phase
detector
Current
sources
FMOSCIN
PDO
PD
Bandgap
6
20
14
11
GNDan
V5
GND
VS
2
U4256BM-R
4562C–AUDR–08/04
U4256BM-R
Functional
Description
For a tuned FM-broadcast receiver, the following parts are needed:
•
•
•
Voltage-Controlled Oscillator (VCO)
Antenna Amplifier Tuned Circuit
RF Amplifier Tuned Circuit
Typical modern receivers with electronic tuning are tuned to the desired FM frequency
by the frequency synthesizer IC U4256BM-R. The special design allows the user to
build software-controlled tuner alignment systems. Two programmable DACs (Digital-to-
Analog Converter) support the computer-controlled alignment. The output of the PLL is
a tuning voltage which is connected to the VCO of the receiver IC. The output of the
VCO is equal to the desired station frequency plus the IF (10.7 MHz). The RF and the
oscillator signal (VCO) are both input to the mixer that translates the desired FM chan-
nel signal to the fixed IF signal. For FM, the double-conversion system of the receiver
requires exactly 10.7 MHz for the first IF frequency, which determines the center fre-
quency of the software-controlled integrated second IF filter.
If this oscillator tuning feature is not used, the internal capacities have to be switched off
and the oscillator has to be operated with high-quality external capacities to ensure that
the operational frequency is exactly 10.250 MHz.
When dimensioning the oscillator circuit, it is important that the additional capacities
enable the oscillator to operate through its complete tracking range. The oscillating abil-
ity depends very strongly on the used crystal oscillator. Initializing the oscillator should
be established without switching any additional capacities to guarantee that the oscilla-
tor starts to operate properly. Due to the lower quality of the integrated capacities
compared to discrete capacities, the amount of the switched integrated capacities
should always be minimized. (If necessary reduce tracking range or use another crystal
oscillator.)
The U4256BM-R has a very fast response time of maximum 800 µs (at 2 mA,
fStep = 50 kHz, measured on MPX signal). It performs a high signal to noise ratio. Only
one supply voltage is necessary, due to a integrated band gap.
Input/Output
Interface Circuits
PDO (Pin 1)
PD (Pin 2)
PDO is the buffer amplifier output of the PLL. The bipolar output stage is a rail-to-rail
amplifier.
PD is the current charge pump output of the PLL. The current can be controlled by
setting the Bits. The loop filter has to be designed corresponding to the choosen pump
current and the internal reference frequency. A recommendation can be found in the
application circuit.
The charge-pump current can be choosen by setting the Bits 71 and 70 as following:
IPD (µA)
25
B71
0
B70
0
100
0
1
500
1
0
2000
1
1
3
4562C–AUDR–08/04
Figure 3. Internal Components at PDO Connection
VS
VS
VS
PDO
PD
FMOSCIN (Pin 19)
FMOSCIN is the preamplifier input for the FM oscillator signal.
Figure 4. Internal Components at FMOSCIN
V5
FMOSCIN
MX2LO (Pin 15)
MX2LO is the buffered output of the crystal oscillator. This signal can be used as a refer-
ence frequency for U4255BM or T4258.
The oscillator buffer output can be switched by the OSCB Bit as following (Bit 69)
MX2LO AC Voltage
B69
0
ON
OFF
1
Figure 5. Internal Components at MX2LO
V5
V5
OSCIN
MX2LO
4
U4256BM-R
4562C–AUDR–08/04
U4256BM-R
Function of DAC1, 2 in
FM and AM Mode
(Pin 3 and Pin 4)
For automatic tuner alignment, the DAC1 and DAC2 of the U4256BM-R can be con-
trolled by setting gain of VPDO and offset values. The following figure shows the
principle of the operation. In FM Mode the gain is in the range of 0.69 × V(PDO) to 2.16 ×
V(PDO). The offset range is +0.56 V to -0.59 V. For alignment, DAC1 and DAC2 are con-
nected to the varicaps of the preselection filters. For alignment, offset and gain is set for
having the best tuner tracking.
Figure 6. Principle Operation for Alignment
Bit 34
PDO (FM)
DAC1,2
Gain
+/-
Vref (AM)
(3 V)
Offset
The DAC mode can be controlled by setting the Bit 34 as following:
DAC Mode
FM
B34
0
AM
1
If Bit 34 = 1 (AM Mode), the DAC1, DAC2 can be used as standard DAC converters.
The internal voltage of 3 V is connected to the gain- and offset-input of DAC1 and DAC2
(only in AM Mode). The gain is in the range of 0.46 × 3 V to 3.03 × 3 V. The offset range
is +1.46 V to -1.49 V.
Figure 7. Internal Components at DAC1,2 Output
VS
DAC1,2
5
4562C–AUDR–08/04
DAC 1, 2 in FM Mode
(Pin 3 and Pin 4)
The gains of DAC1 and DAC2 have a range of 0.69 × V(PDO) to 2.16 × V(PDO). V(PDO) is
the PLL tuning voltage output. This range is divided into 256 steps. So one step is
approximately (2.16 - 0.46) × V(PDO) / 255 = 0.005764 × V(PDO). The gain of DAC1 can be
controlled by the Bits 36 to 43 (G-20 to G-27) and the gain of DAC2 by the Bits 0 to 7 (G-
20 to G-27) as following:
Gain DAC1
Approximately
Decimal
Gain
B43
B42
B41
B40
B39
B38
B37
B36
Gain DAC2
Approximately
Decimal
Gain
B7
0
B6
0
B5
0
B4
0
B3
0
B2
0
B1
0
B0
0
0.69 × V(PDO)
0.69576 × V(PDO)
0.70153 × V(PDO)
0.70729 × V(PDO)
...
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
2
0
0
0
0
0
0
1
1
3
...
0
...
0
...
1
...
1
...
0
...
1
...
0
...
1
...
0.99549 × V(PDO)
...
53
...
...
1
...
1
...
1
...
1
...
1
...
1
...
0
...
1
2.14847 × V(PDO)
2.15424 × V(PDO)
2.16 × V(PDO)
253
254
255
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
Offset = 31 (intermediate position)
The offset of DAC1 and DAC2 has a range of 0.56 V to -0.59 V. This range is divided
into 64 steps. So one step is approximately 1.15 V/ 63 = 18.25 mV. The offset DAC1
can be controlled by the Bits 44 to 49 (O-20 to O-25) and the offset of DAC2 by the Bits 8
to 13 (O-20 to O-25) as following:
Offset DAC1
Approximately
Decimal
Gain
B49
B48
B47
B46
B45
B44
Offset DAC2
Approximately
Decimal
Gain
B13
0
B12
0
B11
0
B10
0
B9
0
B8
0
0.56 V
0.5417 V
0.5235 V
0.5052 V
...
0
1
0
0
0
0
0
1
0
0
0
0
1
0
2
0
0
0
0
1
1
3
...
0
...
1
...
1
...
1
...
1
...
1
...
31
...
61
62
63
+0.0059 V
...
...
1
...
1
...
1
...
1
...
0
...
1
0.5535 V
-0.5717 V
-0.59 V
1
1
1
1
1
0
1
1
1
1
1
1
Gain = 53 (intermediate position)
6
U4256BM-R
4562C–AUDR–08/04
U4256BM-R
DAC 1, 2 in AM Mode
(Pin 3 and Pin 4)
In AM mode the DAC input voltage V(PDO) is internal connected to 3 V. The gains of
DAC1 and DAC2 have a range of 0.46 × 3 V to 3.03 × 3 V. V(PDO) is the PLL tuning volt-
age output. This range is divided into 256 steps. So one step is approximately
(3.03 - 0.46) × 3 V/255 = 0.01007 × 3 V. The gain of DAC1 can be controlled by the Bits
36 to 43 (G-20 to G-27) and the gain of DAC2 by the Bits 0 to 7 (G-20 to G-27) as
following:
Gain DAC1
Approximately
Decimal
Gain
B43
B42
B41
B40
B39
B38
B37
B36
Gain DAC2
Approximately
Decimal
Gain
B7
0
B6
0
B5
0
B4
0
B3
0
B2
0
B1
0
B0
0
0.4607 × 3 V
0.4710 × 3 V
0.4812 × 3 V
0.4915 × 3 V
...
0
1
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
0
2
0
0
0
0
0
0
1
1
3
...
0
...
0
...
1
...
1
...
0
...
1
...
0
...
1
...
1.0029 × 3 V
...
53
...
...
1
...
1
...
1
...
1
...
1
...
1
...
0
...
1
3.0097 × 3 V
3.0196 × 3 V
3.0296 × 3 V
253
254
255
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
Offset = 31 (intermediate position)
Remark: V(PDO) is 3 V in AM mode.
The offset of DAC1 and DAC2 has a range of +1.46 V to -1.49 V. This range is divided
into 64 steps. So one step is approximately 2.95 V/ 63 = 46.8 mV. The offset DAC1 can
be controlled by the Bits 44 to 49 (O-20 to O-25) and the offset of DAC2 by the Bits 8 to
13 (O-20 to O-25) as following:
Offset DAC1
Approximately
Decimal
Gain
B49
B48
B47
B46
B45
B44
Offset DAC2
Approximately
Decimal
Gain
B13
0
B12
0
B11
0
B10
0
B9
0
B8
0
1.4606 V
1.4138 V
1.3665 V
1.3196 V
...
0
1
0
0
0
0
0
1
0
0
0
0
1
0
2
0
0
0
0
1
1
3
...
0
...
1
...
1
...
1
...
1
...
1
...
31
...
61
62
63
-0.0079 V
...
...
1
...
1
...
1
...
1
...
0
...
1
-1.3975 V
-1.4447 V
-1.4917 V
1
1
1
1
1
0
1
1
1
1
1
1
Gain = 53 (intermediate position)
7
4562C–AUDR–08/04
DAC3 (Pin 5)
The DAC3 output voltage can be controlled by the Bits P-20 to P-22 (Bits 66 to 68) as
following:
DAC3 Offset Approximately
B68
0
B67
0
B66
0
0.55 V
1.25 V
1.90 V
2.60 V
3.30 V
4.10 V
4.80 V
5.45 V
0
0
1
0
1
0
0
1
1
1
0
0
1
0
1
1
1
0
1
1
1
Figure 8. Internal Components at DAC3
VS
DAC3
EN, DATA, CLK
(Pin 16-18)
All functions can be controlled via a 3-wire bus consisting of ENABLE, DATA and
CLOCK. The bus is designed for microcontrollers which operate with 3 V supply voltage.
Details of the data transfer protocol are shown in the table ‘3-wire Bus Description’.
Figure 9. Internal Components at EN, DATA, CLK
V5
EN
DATA
CLK
8
U4256BM-R
4562C–AUDR–08/04
U4256BM-R
SWO1, 2, 3 and 4
(Pin 7-10)
All switching outputs are ‘open drain’ and can be set and reset by software control.
Details are described in the data transfer protocol.
The switching output SWO1 to SWO4 can be controlled as following (Bits 30 to 33):
Switch Output
SWOx = ON (switch to GND)
SWOx = OFF
B30 + X
0
1
X = 0 to 3
Figure 10. Internal Components at SWO1, 2, 3 and 4
SWO1
I
SWO2
SWO3
SWO4
OSCIN, OSCOUT
(Pin 12 and Pin 13)
A crystal resonator (up to 15 MHz) is connected between OSCIN and OSCOUT in order
to generate the reference frequency. By using the U4256BM-R in connection with
U4255BM or T4258, the crystal frequency must be 10.25 MHz. The complete applica-
tion circuit is shown in Figure 15. If a reference is available, it can be applied at OSCIN.
The minimum voltage should be 100 mVrms. In this case, Pin OSCOUT has to be open.
The tuning capacity for the crystal oscillator has a range of 0.5 pF to 71.5 pF. The
values are coded binary. The tuning can be controlled by the Bits 78 to 85 as following:
B85 = 1
[pF]
B85 = 0
[pF]
B84
1
B83
1
B82
1
B81
1
B80
1
B79
1
B78
1
0
8.0
8.5
0.5
1.0
1.5
...
1
1
1
1
1
1
0
9.0
1
1
1
1
1
0
1
19.5
...
1
1
1
1
1
0
0
...
0
...
0
...
0
...
0
...
0
...
0
...
0
63.0
63.5
71.0
71.5
0
0
0
0
0
0
0
9
4562C–AUDR–08/04
Figure 11. Internal Components at OSCIN and OSCOUT
V5
OSCIN
V5
OSCOUT
Figure 12. Internal Connection of Tuning Capacity for Crystal Oscillator
Cx1
Cx2
INV
8pF
0.5 pF
0.5 pF
...
32pF
8pF
32pF
...
B78
B84
B85
10
U4256BM-R
4562C–AUDR–08/04
U4256BM-R
Application Information
Figure 13. FMOSCIN Sensitivity
Vi (mVrms on 50 Ω)
150
100
50
0
0
20
40
60
80
100
120 140
160
Frequency (MHz)
3-wire Bus
Description
The register settings of U4256BM-R are programmed by a 3-wire bus protocol. The bus
protocol consists of separate commands. A defined number of bits is transmitted
sequentially during each command.
One command is used to program all the bits of one register. The different registers
available (see table Data Transfer) are addressed by the length of the command (num-
ber of transmitted bits) and by two address bits, that are unique to each register of a
given length. 16-bit registers are programmed by 16-bit commands and 24-bit registers
are programmed by 24-bit commands.
Each bus command starts with a rising edge on the enable line (EN) and ends with a
falling edge on EN. EN has to be kept HIGH during the bus command.
The sequence of transmitted bits during one command starts with the LSB of the first
byte and ends with the MSB of the last byte of the register addressed. To transmit one
bit (0/1) DATA has to be set to the appropriate value (LOW/HIGH) and a LOW to HIGH
transition has to be performed on the clock line (CLK) while DATA is valid. The DATA is
evaluated at the rising edges of CLK. The number of LOW to HIGH transitions on CLK
during the HIGH period of EN is used to determine the length of the command.
The bus protocol and the register addressing of U4256BM-R are compatible to the
addressing used in U4255BM and T4258. That means U4256BM-R and U4255BM (or
T4258) can be operated on the same 3-wire bus as shown in the application circuit.
11
4562C–AUDR–08/04
Figure 14. 3-wire Bus Timing Diagram
tF
tR
VHIGH
VLOW
Enable
tHEN
tS
tR
tF
VHIGH
VLOW
Data
tHDA
tS
tR
tF
VHIGH
VLOW
Clock
tH
tL
Figure 15. 3-wire Pulse Diagram
16-bit command
EN
DATA
CLK
LSB
BYTE 1
MSB LSB
BYTE 2
MSB
24-bit command
EN
DATA
CLK
LSB
BYTE 1
MSB LSB
BYTE 2
MSB LSB
BYTE 3
MSB
e.g. R-Divider
IPD
Status 0
OSCB
25
27
26
R-Divider
28
20
21
22
23
24
29 210
211 212
0
1
2
0
Addr.
213 214 215
0
P-2 P-2 P-2
DAC3
12
U4256BM-R
4562C–AUDR–08/04
U4256BM-R
Data Transfer
Table 1. Control Registers
A
MSB
ADDR.
BYTE 3
STATUS 0
OSCB
LSB
MSB
BYTE 2
LSB
MSB
BYTE 1
LSB
DAC3
P-21
B67
R-Divider
0
0
IPD
0=on,
1=off
P-22
B68
P-20
B66
215
214
213
212
210
211
29
28
27
26
25
24
23
22
21
20
B71
B70
B69
B65
B64
B63
B62
B61
B60
B59
B58
B57
B56
B55
B54
B53
B52
B51
B50
B
MSB
BYTE 3
LSB
MSB
BYTE 2
LSB
MSB
BYTE 1
LSB
ADDR.
STATUS 1
N-Divider
AM=1 SWO4 SWO3 SWO2 SWO1
FM=0 0=on, 0=on, 0=on, 0=on,
0
1
0
215
214
213
212
210
211
29
28
27
26
25
24
23
22
21
20
DAC
1=off 1=off 1=off 1=off
B35
B34
B33
B32
B31
B30
B29
B28
B27
B26
B25
B24
B23
B22
B21
B20
B19
B18
B17
B16
B15
B14
C
MSB
BYTE 2
DAC1 OFFSET
LSB
MSB
BYTE 1
DAC1 GAIN
LSB
ADDR.
0
0
O-25 O-24
B49 B48
O-23
B47
O-22
B46
O-21
B45
O-20
B44
G-27
B43
G-26
B42
G-27
B41
G-25
B40
G-24
B39
G-23
B38
G-22
B37
G-20
B36
D
MSB
BYTE 2
DAC2 OFFSET
LSB
MSB
BYTE 1
DAC2 GAIN
LSB
ADDR.
0
1
O-25 O-24
O-23
O-22
O-21
B9
O-20
B8
G-27
B7
G-26
B6
G-27
B5
G-25
G-24
G-23
B2
G-22
B1
G-20
B0
B13 B12
B11
B10
B4
B3
E
MSB
BYTE 2
LSB
MSB
BYTE 1
LSB
ADDR.
0
Oscillator tuning function
Not used
1
8pF 32pF 16pF
B85 B84 B83
8pF
B82
4pF
B81
2pF
B80
1pF
B79
0.5pF
B78
X
X
X
X
X
X
B77
B76
B75
B74
B73
B72
Absolute Maximum Ratings
Parameters
Symbol
Value
Unit
Analog supply voltage
Input voltage BUS
Pin 6
VS
VI
IO
8 to 12
V
V
Pins 16, 17 and 18
Pins 7, 8, 9 and 10
-0.3 to +5.3
-1 to +5
Output current switches
(see Figure 10)
mA
Drain voltage switches
Pins 7, 8, 9 and 10
VOD
Tamb
Tstg
Tj
15
-40 to +85
-40 to +125
125
V
Ambient temperature range
Storage temperature range
Junction temperature
°C
°C
°C
V
Electrostatic handling M.M.
VESD
300
13
4562C–AUDR–08/04
Thermal Resistance
Parameters
Symbol
Value
Unit
Junction ambient, when soldering to PCB
RthJA
140
K/W
Operating Range
All voltages are referred to GND (Pin 11)
Parameters
Symbol
VS
Min.
8
Typ.
Max.
12
Unit
Supply voltage range
Pin 6
8.5
V
Ambient temperature
Tamb
fin
-40
70
2
+85
160
65535
15
°C
Input frequency FMOSCIN
Programmable N, R divider
Crystal reference oscillator
Pin 19
MHz
SF
Pins 12 and 13
fXTAL
0.1
MHz
Electrical Characteristics
Test Conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25°C.
No.
1
Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
8.5
10
Max.
12
Unit
V
Type*
Supply Voltage
Analog supply voltage
Supply Current
Analog supply current
OSCIN
1.1
2
6
VS
8
5
A
A
B
2.1
3
6
IS
25
mA
3.1
4
Input voltage
f = 0.1 to 15 MHz
13
OSC
100
mVrms
OSC Buffer (MX2LO)
Output AC voltage
4.1
At Pin15: 47 pF and
1 kΩ
15
15
vMX2LO
VMX2LO
80
120
2.0
200
2.2
mVpp
V
B
A
4.2
5
Output DC voltage
FMOSCIN
1.8
5.1
Input voltage
f = 70 to 120 MHz
f = 120 to 160 MHz
FMOSC
FMOSC
40
150
mVrms
mVrms
19
B
6
Pulsed Current Output PD
6.1
Output current Bit 71,
70 = ‘00’
PD = 2.5 V
2
2
2
±IPD
±IPD
±IPD
20
80
25
100
500
2000
30
µA
µA
µA
A
A
A
6.2
6.3
6.4
6.5
Output current Bit 71,
70 = ‘01’
PD = 2.5 V
PD = 2.5 V
PD = 2.5 V
PD = 2.5 V
120
600
Output current Bit 71,
70 = ‘10’
400
1500
Output current Bit 71,
70 = ‘11’
2
2
±IPD
2400
20
µA
nA
A
A
Leakage current
±IPDL
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
14
U4256BM-R
4562C–AUDR–08/04
U4256BM-R
Electrical Characteristics (Continued)
Test Conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25°C.
No.
7
Parameters
PDO
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
7.1
Saturation voltage
HIGH
3, 4
3, 4
8.0
0
8.5
0.4
V
V
A
A
7.2
Saturation voltage
LOW
8
SWO1, SWO2, SWO3, SWO4 (Open Drain)
8.1
Output leakage current
HIGH
Pin 7,8,9,10 over R
against 8.5 V
7, 8,
9, 10
ISWOH
100
400
nA
A
A
8.2
Output voltage LOW
I = 1 mA
7, 8,
9, 10
VSWOL
100
mV
9
DAC1, DAC2
Output current
Output voltage
9.1
9.2
9.3
3, 4
3, 4
IDAC1, 2
±1
mA
V
C
A
VDAC1, 2
0.3
VS-0.6
Maximum offset range
(FM)
offset = 0, gain = 53
offset = 63, gain = 53
gain = 255, offset = 31
gain = 0, offset = 31
3, 4
3, 4
3, 4
3, 4
0.45
0.56
-0.57
0.69
2.16
0.65
-0.65
0.75
2.23
V
V
A
A
A
A
9.4
9.5
9.6
Minimum offset range
(FM)
-0.45
0.63
2.1
Maximum gain range
(FM)
Minimum gain range
(FM)
10
DAC3
10.1
10.2
10.3
10.4
10.5
10.6
10.7
10.8
10.9
11
Output current
Output voltage
Output voltage
Output voltage
Output voltage
Output voltage
Output voltage
Output voltage
Output voltage
5
5
5
5
5
5
5
5
5
IDAC3
VDAC3
VDAC3
VDAC3
VDAC3
VDAC3
VDAC3
VDAC3
VDAC3
±1
mA
V
C
A
A
A
A
A
A
A
A
Bit 68-66: 000
Bit 68-66: 001
Bit 68-66: 010
Bit 68-66: 011
Bit 68-66: 100
Bit 68-66: 101
Bit 68-66: 110
Bit 68-66: 111
0.4
1.1
1.8
2.4
3.2
3.8
4.5
5.2
0.55
1.25
1.90
2.60
3.30
4.10
4.80
5.45
0.7
1.4
2.1
2.8
3.5
4.3
5.0
5.7
V
V
V
V
V
V
V
3-wire Bus, ENABLE, DATA, CLOCK
11.1
Input voltage HIGH
LOW
VBUSH
VBUSL
2.7
-0.3
5.3
0.8
V
V
16-18
17
A
A
D
11.2
11.3
Clock frequency
1.0
MHz
Period of CLK HIGH
LOW
tH
tL
250
250
ns
ns
17
11.4
11.5
Rise time EN, DATA,
CLK
16-18
16-18
tr
tf
400
100
ns
ns
D
D
Fall time EN, DATA,
CLK
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
15
4562C–AUDR–08/04
Electrical Characteristics (Continued)
Test Conditions (unless otherwise specified): VS = 8.5 V, Tamb = 25°C.
No.
11.6
11.7
11.8
Parameters
Set-up time
Test Conditions
Pin
16-18
18
Symbol
ts
Min.
100
250
0
Typ.
Max.
Unit
ns
Type*
D
D
D
Hold time EN
Hold time DATA
tHEN
tHDA
ns
16
ns
*) Type means: A = 100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
Figure 16. Application Circuit
EN
CLK
DATA
GND
C12
100 nF
C9
*)
R5
*)
5.1 k
*) depends on
crystal
C8
47 pF
10.25 MHz
20
19
18
17
16
15
14
13
12
11
C1
R2
BUS
OSC
600
10 pF
fOSC
LOGIC
FM
VCO
DAC's
4
Switches
8
1
2
3
5
6
7
9
10
V
tune
C16
C5
C 6
330 pF
R4
8.2 k
C15
C4
10 nF
100 nF
C14
10 nF
100 mF
C7
R3
10 nF
10 nF
100
DAC1
DAC2
DAC3
VS
SWO1
SWO2
SWO3
SWO4
8 ... 12 V
16
U4256BM-R
4562C–AUDR–08/04
U4256BM-R
Figure 17. Application Board Schematic
17
4562C–AUDR–08/04
Ordering Information
Extended Type Number
Package
SSO20
SSO20
Remarks
U4256BM-RFS
Tube
U4256BM-RSG3
Taped and reeled
Package Information
5.7
5.3
Package SSO20
Dimensions in mm
6.75
6.50
4.5
4.3
1.30
0.15
0.15
0.05
0.25
0.65
6.6
6.3
5.85
20
11
technical drawings
according to DIN
specifications
1
10
18
U4256BM-R
4562C–AUDR–08/04
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Printed on recycled paper.
4562C–AUDR–08/04
xM
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