U6820BM-FP [ATMEL]
Dual Quad BCDMOS Driver IC; 双四BCDMOS驱动IC
| 型号： | U6820BM-FP |
| 厂家： | 
ATMEL |
| 描述： | Dual Quad BCDMOS Driver IC |
| 文件： | 总11页 (文件大小：221K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• Four Short-circuit-protected High-side Drivers with a Maximum Current Capability of
50 mA Each
• Four Short-circuit-protected Low-side Drivers with a Maximum Current Capability of
50 mA Each
• ON Resistance High Side Ron < 10 Ω Versus Total Temperature Range
• ON Resistance Low Side Ron < 7 Ω Versus Total Temperature Range
• Short-circuit Detection of Each Driver Stage
• Disabling of Driver Stages in the Case of Short-circuit and Overtemperature Detection
• Independent Control of Each Driver Stage via an 8-bit Shift Register
• Status Output Reports Short-circuit Condition
• Status Output Reports when All Loads Are Switched Off
• Timing of Status Output Reset Signalizes Failure Mode
• Temperature Protection in Conjunction with Short-circuit Detection
Dual Quad
BCDMOS
Driver IC
Description
The U6820BM is a driver interface in BCDMOS technology with 8 independent driver
stages having a maximum current capability of 50 mA each. Its partitioning into 4
high-side and 4 low-side driver stages allows an easy connection of either 4 half-
bridges or 2 H-bridges on the pc board. The U6820BM communicates with a micro-
controller via an 8-bit serial interface. Integrated protection against short circuit and
overtemperature give added value. EMI protection and 2-kV ESD protection together
with automotive qualification referring to conducted interference (ISO/TR 7637/1)
make this IC ideal for both automotive and industrial applications.
U6820BM
Figure 1. Block Diagram
HS4
16
HS3
9
HS2
8
HS1
1
V
6
CC
Current
limiter
Current
limiter
Current
limiter
Current
limiter
3
V
V
CC
S
14
STATUS
V
V
Thermal protection
Power-on reset
CC
CC
H
S
4
H
S
3
H
S
2
H
S
1
L
S
4
L
S
3
L
S
2
L
S
1
11
12
13
CS
CLK
DI
Control
logic
V
CC
Input Register
5
GND
S
Current
limiter
Current
limiter
Current
limiter
Current
limiter
15
LS4
10
LS3
4
7
2
GND
CC
LS2
LS1
Rev. 4527A–BCD–03/02
Pin Configuration
Figure 2. Pinning SO16
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
HS4
LS4
HS1
LS1
VS
STATUS
DI
GNDCC
GNDS
VCC
CLK
CS
LS2
LS3
HS2
HS3
Pin Description
Pin
Symbol
Function
1
HS1
Output high side 1
Output low side 1
2
LS1
3
VS
Supply voltage 6 V to 18 V
Digital ground
4
GNDCC
GNDS
VCC
LS2
5
Power ground
6
Supply voltage 5 V (external)
Output low side 2
7
8
HS2
Output high side 2
9
HS3
Output high side 3
10
11
12
13
14
15
16
LS3
Output low side 3
CS
Set supply status (chip select)
Clock line for 8-bit control shift register
Data line for 8-bit control shift register
CLK
DI
STATUS
LS4
Status output (H = fault, diagnostic “H” if all driver stages are switched off)
Output low side 4
Output high side 4
HS4
2
U6820BM
4527A–BCD–03/02
U6820BM
Description of the
Control Interface to
the Microcontroller
The serial-parallel interface basically includes an 8-bit shift register (SR), an 8-bit com-
mand register (CR) and a 4-bit counter.
The data input takes place with commands at Pins DI (data input), CS (chip select) and
CLK (clock). With a falling edge at CLK, the information at DI is transferred into the SR.
The first information written into the SR is the least significant bit (LSB). The Pin STA-
TUS is used for diagnostic purposes and reports any fault condition to the
microcontroller.
The input CS in accordance with the CR controls the serial interface. A high level at CS
disables the SR. With a falling edge at CS, the SR is enabled. The CR control allows
only the first 8 bits to be transferred into the SR, and further clocks at CLK are ineffec-
tive. If a rising edge occurs at CS after 8 clocks precisely, the information from the SR is
transferred into the CR. If the number of clock cycles during the low phase of CS was
less or more than eight transitions, no transfer will take place. A new command switches
the output stages on or off immediately.
Each output stage is controlled by one specific bit of the CR. Low level means “supply
off” or inactive, and high level means “supply on” or active. If all 8 bits are at a low level,
the output stages will be set into standby mode.
If one of the output stages detects a short circuit and additionally overtemperature con-
dition, the corresponding control bit in the CR is set to low. This reset has priority over
an external command to CR, thus, this does not affect the 1st control bit. The priority pro-
tects the IC against overtemperature by activating the temperature shut down
immediately.
The STATUS Output
The STATUS output is at low level during normal operation. If one or more output stages
detect short circuit or if overtemperature is indicated, the STATUS output changes to
high level (OR-connection).
For diagnostic purposes (self test of the status output), the status output can also be
brought into high level during standby mode.
Timing of the Status
Output Reset Signalizes
the Failure Mode
The use of different reset conditions at the STATUS output simplifies the failure analysis
during normal operation, and is also beneficial during testing.
The storage content can be used for STATUS output. It is indicated and latched immedi-
ately with the rising edge of CS at STATUS output if less than 8 clocks were received
during the low phase of CS. The reset is initiated by the falling edge of the 8th clock
(bit 7) of the next data input.
Also, the appearance of more than 8 clocks is latched and indicated at STATUS by the
rising edge of the 9th clock. The reset is initiated by the falling edge of the 2nd clock
(bit 1) of the next data input.
The detection of overtemperature is latched internally. It is reset by the falling edge of
the 4th clock (bit 3) of a data transfer if overtemperature is no longer present.
Power-on Reset
After switching on the supply voltage, all data latches are reset and the outputs are
switched off. The typical power-on reset threshold is VCC = 3.7 V. The outputs are acti-
vated after the first data transfer.
3
4527A–BCD–03/02
Short-circuit Protection
The current of the output stages is limited by an active feedback control. Short circuit at
one output stage sets the diagnostic Pin 14 (STATUS) to high. In case of both condi-
tions, short circuit at one of the outputs and temperature detection, the affected output is
switched off selectively. It will be activated again after the first new data transfer.
Inductance Protection
Temperature Protection
Clamping diodes and FETs are integrated to protect the IC against too high or too low
voltages at the outputs. They prevent the IC from latch up and parasitic currents which
may exceed power dissipation.
The IC is protected by an overtemperature detection. As soon as the junction tempera-
ture Tj = 155°C typically is exceeded, the diagnostic Pin 14 (STATUS) is set “high”.
General overtemperature detection along with short-circuit condition at a specific output
result in temperature shut down at that specific output. After temperature shut down, the
data input register has to be set again with a hysteresis of typically ∆T = 15 K
(Tj = 140°C).
ESD Protection
All output stages are protected against electrostatic discharge up to 5 kV (HBM) with
external components (see Figure 5), all other pins are protected up to 2 kV (HBM).
Table 1. Timing of the STATUS Output
Low-side Switch
High-side Switch
Status
Reset
Command
Shift Register
Condition
Register
LS1 LS2 LS3 LS4 HS1 HS2 HS3 HS4 Set
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 1
0 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1
1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1
1 1 0 0 0 0 1 1 0 0 0 0 0 0 0 0
All out = OK
All on = OK
off
on
off
off
on
off
x
off
on
off
on
on
off
x
off
on
off
on
on
off
x
off
on
off
on
off
off
x
off
on
off
on
on
off
x
off
on
off
on
on
off
x
off
on
off
on
on
off
x
off
on
on
on
on
off
x
H
L
New CS
E.g. one on = OK
Short at LS3
L
H
H
H
H
H
No short
New CS4
P-ON, CS
New CS 8
New CS 2
Temp & short at HS4
VVCC < 3.7 V = P-ON
CS with less 8 CLK
CS with more 8 CLK
1 1 1 0 0 0 1 1 x
0 0 0 1 1 1 0 0 x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
4
U6820BM
4527A–BCD–03/02
U6820BM
Figure 3. Data Transfer Timing Diagram
t
t
t
CLKP
CLKH
CSCLK
t
t
f
r
CLK
90 %
90 %
50%
LSB
MSB
10%
t
t
CLKL
CLKCS
50%
DI
t
t
DICLK DIH/L
t
CS
CS
50%
t
CLKCSH
Table 2. AC Characteristics for Testing
Specification
tr (rise)
tf (fall)
tCLKP
Conditions
Minimum
Maximum
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
10% to 90% VCC on CLK, DI and CS
10
10
10% to 90% VCC on CLK, DI and CS
1/2 VCC
1/2 VCC
1/2 VCC
1/2 VCC
1/2 VCC
1/2 VCC
1/2 VCC
1/2 VCC
1/2 VCC
250
100
100
150
100
80
tCLKH
tCLKL
tCLKCS
tCSCLK
tDICLK
tDIH/L
100
100
250
tCLKCSH
tCS
5
4527A–BCD–03/02
Figure 4. Block Diagram of the Control Interface
Serial-Parallel Interface
DFF
DFF
DFF
EN
D
D
D
1
2
4
8
CS
11
CL
R
Q
CL
R
Q
R
Q
Counter
R
CL NQ
NQ
CL NQ
Q0
Q1
Q2
Q3
h if 8
8CLK
DFF
h if 4
D
Q
h if 2
CLK
R
POR norm=0
CL NQ
EN
CLK
H4
H3
H2
H1
L4
L3
L2
L1
12
CL
Shift register SR
DIN
LSB
Q0
13
Q7
Q6
Q5
Q4
Q3
Q2
Q1
DI
DIN
DIN
DIN
DIN
DIN
DIN
DIN
DIN
Load CR
CL
Command register BR
NR NQ
NR NQ
NR NQ
NR NQ
NR NQ
NR NQ
NR NQ
NR NQ
DFF
D
Q
CL
R
P-ON-Reset
Th-protection
All norm = 0
NQ
14
STATUS
norm = 0
6
U6820BM
4527A–BCD–03/02
U6820BM
Absolute Maximum Ratings
Parameters
Pin
Symbol
VVS
Minimum
-0.3
Maximum
Unit
V
Supply voltage
3
+40
+7
Logic supply voltage
Logic input voltage
Logic output voltage
Input current
6
VVCC
-0.3
V
11, 12 13
CS, CLK, DI
STATUS
IVS
-0.3
VVCC + 0.5
VVCC + 0.3
0.2
V
14
3
-0.3
V
mA
mA
6
IVCC
5
Output current
1-2, 8-11, 15-16
I
1H-4H and I 1L-4L
30
65
mA
(internally limitted)
Junction temperature range
Storage temperature range
Tj
-40
-55
+150
+150
°C
°C
Tstg
Thermal Resistance
Parameters
Symbol
RthJA
Value
110
Unit
K/W
K/W
Junction ambient
Junction case
RthJC
26
Operating Range
Parameters
Pin
Symbol
VVS
Value
6 to 18
Unit
V
Supply voltage
3
6
Logic supply voltage
Logic input voltage low
Logic input voltage high
Logic output voltage (1 mA load)
Clock frequency
VVCC
4.5 to 5.5
V
11, 12, 13
11, 12, 13
14
CS, CLK, DI
CS, CLK, DI
STATUS
fCLK
-0.2 to (0.2 x VVCC
)
V
(0.7 x VVCC) to (VVCC + 0.3)
V
0.5 to (VVCC - 1)
5
V
MHz
°C
Junction temperature range
Tj
-40 to +150
7
4527A–BCD–03/02
Electrical Characteristics
7 V < VVS < 40 V; 4.5 V < VVCC > 5.5 V; -40°C < Tj < 150°C; unless otherwise specified
No. Parameters
Test Conditions
Pin
Symbol
Min.
Typ.
Max.
Unit
Type*
1
Current Consumption
1.1
1.2
1.3
1.4
2
Supply current VS
No external load
No external load
3
6
6
6
IVS
0.2
5
mA
mA
V
A
A
A
D
Supply current VCC
Power-on reset threshold
Power-on reset delay time
Thermal Shutdown
Thermal shutdown set
Thermal shutdown reset
Thermal hysteresis
IVCC
VCC POR
Td POR
3.4
60
3.7
95
4.0
130
After switching on VCC
µs
2.1
2.2
2.3
3
t j PW set
t j PW reset
Dt
140
130
155
135
20
165
155
°C
°C
K
A
A
A
Output Specifications (1L - 4L, 1H - 4H)
3.1
On-resistance low
Iout = 26 mA,
Tj = 125°C
2, 7,
10, 15
RDSONLOW
RDSONHIGH
ILOWSIDE
3
4
4
7
10
5
Ω
Ω
A
A
A
A
3.2
3.3
3.4
3.5
On-resistance high
Iout = 26 mA,
Tj = 125°C
1, 8,
9, 16
6.25
Output leakage current
lowside
VLSIDE 1-4 = 17.5 V
2, 7,
10, 15
µA
µA
Output leakage current
highside
VHSIDE 1-4 = 0.5 V
1, 8,
9, 16
IHIGHSIDE
-5
Output leakage steepness
1-2,
7-10,
15-16
dVOUT/ dt
50
200
400
mV/µs
D
3.6
3.7
Over current limitation
highside
1, 8,
9, 16
IHIGHSIDE
ILOWSIDE
27
27
45
45
95
80
mA
mA
A
A
Over current limitation
lowside
2, 7,
10, 15
4
Serial Interface – Inputs: CS, CLK and DATA
4.1
Input voltage low level
threshold
11-13
11-13
0.2×
VVCC
VILOW
V
A
4.2
Input voltage high level
threshold
0.7×
VVCC
VIHIGH
V
A
A
4.3
4.4
Hysteresis of input voltage
11-13
11-13
∆Vi
300
mV
Pull-down current
(internal pull-up
resistor:
Ii
300
µA
A
30 kΩ to 140 kΩ)
5
Serial Interface – Output: STATUS
5.1
5.2
Output voltage low level
Output voltage high level
I = 1 mA
I = 1 mA
VOLOW
VOHIGH
0.5
V
V
A
A
VVCC-1
VVCC
*) Type means: A =100% tested, B = 100% correlation tested, C = Characterized on samples, D = Design parameter
8
U6820BM
4527A–BCD–03/02
U6820BM
Figure 5. Application Circuit
Typical application with
4 Hall-ICs for rotational speed detection
RR
LR
RF
VCC
LF
+
VBATT
12 V
R *
HS4
R *
HS3
R *
R *
HS1
5 V
33µF
100nF
4.7nF
4.7nF
4.7nF
4.7nF
VCC
HS2
8
16
9
1
6
U6820BM
3
VCC
VS
+
14
STATUS
47µF
100nF
VCC
Thermal protection
Power-on reset
H
S
4
H
S
3
H
S
2
H
S
1
L
S
4
L
S
3
L
S
2
L
S
1
11
12
13
CS
CLK
DI
Control
logic
µC
VCC
Input register
VCC
5
GNDS
4
15
10
7
2
GNDCC
LS4
LS3
LS2
LS1
4.7nF
27k
4.7nF
4.7nF
4.7nF
27k
Sensor
control
27k
27k
R *
= ca. 4 Ohm (I Lim for inv. supply)
Note:
It is strongly recommended to connect the blocking capacitors at VS and VCC as close as possible to the power supply and GND
pins. Recommended value for VS is less than 100 µF electrolytic in parallel with 100 nF ceramic. Value for electrolytic capacitor
depends on external loads, noise and surge immunity efforts. Recommended value for VCC is 33 µF electrolytic in parallel with
100 nF ceramic. The 4-Ω resistors connected to the Pins HS1 - HS4 support the protection in case of a short circuit of these
pins to VBatt
.
9
4527A–BCD–03/02
Ordering Information
Extended Type Number
Package
Remarks
U6820BM-FP
SO16
Package Information
5.2
4.8
Package SO16
Dimensions in mm
10.0
9.85
3.7
1.4
0.2
0.25
0.10
0.4
3.8
1.27
6.15
5.85
8.89
16
9
technical drawings
according to DIN
specifications
13036
1
8
10
U6820BM
4527A–BCD–03/02
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Printed on recycled paper.
4527A–BCD–03/02
xM
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