UG120 [ATMEL]

0.6um ULC Series; 0.6um ULC系列


型号：	UG120
厂家：	ATMEL
描述：	0.6um ULC Series 0.6um ULC系列
文件：	总7页 (文件大小：39K)
中文：	中文翻译
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UG Series

0.6µm ULC Series

Description

The UG series of ULCs is well suited for conversion of

medium- to-large sized CPLDs and FPGAs. Devices are

implemented in high-performance CMOS technology

with 0.6-µm (drawn) channel lengths, and are capable of

supporting flip-flop toggle rates of 350 MHz, operating

clock frequencies up to 150 MHz and input to output

delays as fast as 5 ns.

a very low standby consumption of 0.4 nA/gate

typically, which would yield a standby current of 4 mA

on a 10,000 gate design. Operating consumption is a

strict function of clock frequency, which typically

results in a power reduction of 50% to 90% depending

on the device being compared.

The UG series provides several options for output

buffers, including a variety of drive levels up to 24 mA.

Schmitt trigger inputs are also an option. A number of

techniques are used for improved noise immunity and

reduced EMC emissions, including: several

independent power supply busses and internal

decoupling for isolation; slew rate limited outputs are

also available as required.

The architecture of the UG series allows for efficient

conversion of many PLD architectures and FPGA

device types. A compact RAM cell, along with the large

number of available gates allows the implementation of

RAM in FPGA architectures that support this feature, as

well as JTAG boundary-scan and scan-path testing.

Conversion to the UG series of ULC can provide a

significant reduction in operating power when

compared to the original PLD or FPGA. This is

especially true when compared to many PLD and CPLD

architecture devices, which typically consume 100 mA

or more even when not being clocked. The UG series has

The UG series is designed to allow conversions of high

performance 3.3V devices as well as 5.0V devices.

Support of mixed supply conversions is also possible,

allowing optimal trade-offs between speed and power

consumption.

Features

D High performance ULC family suitable for

medium- to large-sized CPLDs and FPGAs

D Conversions to over 200,000 FPGA gates

D Pin counts to over 300 pins

D High speed performance:

–

250-ps typical cell delay

350-MHz toggle rate

D Full range of packages: DIP, SOIC, LCC/PLCC,

D Any pin-out matched due to limited number of

PQFP/TQFP, PGA/PPGA

dedicated pads

D Advanced 0.6-µm (drawn)/0.45-µm (effective)

feature size

D 3.3V and/or 5.0V operation.

D Low quiescent current: 0.4 nA/gate

D Available in commercial, industrial, automotive,

military and space grades.

D Triple-layer or dual-layer metal CMOS

technology

Rev. B – 25 May. 98

5–1

UG Series

Product Outline

Part Number

Full programmables Pads

Equivalent FPGA Gates

Maximum Drive

UG01

UG04

UG09

UG14

UG20

UG33

UG42

UG52

UG70

UG90

UG120

UG140

3300

7500

N/A

310

15800

24300

34800

46000

58600

63700

85800

108500

145100

156800

790

1210

1740

2880

3660

4550

6130

7750

10360

12250

104

130

146

162

188

212

244

264

Slew Rate Controlled Output Buffer

Architecture

In this mode, the p- and n-output transistor commands

are delayed, so that they are never set “ON”

simultaneously, resulting in a low switching current and

low noise. These buffer are dedicated to very high load

drive.

The basic element of the UG family is called a cell. One

cell can typically implement between two to three FPGA

gates. Cells are located contiguously through out the

core of the device, with routing resources provided in

two or three metal layers above the cells. Some cell

blockage does occur due to routing, and utilization will

be significantly greater with three metal routing than

two. The sizes listed in the Product Outline are

estimated usable amounts using three metal layers. I/O

cells are provided at each pad, and may be configured as

inputs, outputs, I/Os, V or V as required to match

3.3V Compatibility

The UG series of ULCs is fully capable of supporting

high-performance operation at 3.3V or 5.0V. The

performance specifications of any given ULC design

however, must be explicitly specified as 3.3V, 5.0V or

both.

any FPGA or PLD pinout. Special function cells and

pins are located in the corners which typically are

unused.

In order to improve noise immunity within the device,

Power Supply and Noise Protection

separate V

and V busses are provided for the

internal cells and the I/O cells.

In order to improve the noise immunity of the UG series,

several mechanisms have been implemented inside the

UG devices. Two kinds of protection have been added:

one to limit the I/O buffer switching noise and the other

to protect the I/O buffers against the switching noise

coming from the core.

I/O Options

Inputs

Each input can be programmed as TTL, CMOS, or

Schmitt Trigger, with or without a pull up or pull down

resistor.

I/O buffers switching protection

Three features are implemented to limit the noise

generated by the switching current: The power supplies

of the input and output buffer are separated. The rise and

fall times of the output buffers can be controlled. The

number of buffers that are connected on the same power

supply line is limited.

Fast Output Buffer

Fast output buffers are able to source or sink 3 to 12 mA

according to the chosen option. 24mA achievable, using

2 pads.

Rev. B – 25 May. 98

5–2

UG Series

Core switching current protection

Absolute Maximum Ratings

This noise disturbance is caused by a large number of

gates switching simultaneously. To allow this without

impacting the functionality of the circuit, three new

features have been added: Some decoupling capacitors

are integrated directly on the silicon to reduce the power

supply drop. A power supply network has been

implemented in the matrix. This solution lessens the

parasitic elements such as inductance and resistance and

Supply Voltage (V ) . . . . . . . . . . . . . . . . . . . . . . . . –0.5 V to 7.0 V

Input Voltage (V ) . . . . . . . . . . . . . . . . . . . –0.5 V to V + 7.0 V

Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . –65 to 150_C

Recommended Operating Range

. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 V "5% or 3.3 V "5%

constitutes an artificial V and V plane. One mesh

Operating Temperature

of the network supplies approximately 150 cells. A

low-pass filter has been added between the core and the

inputs of the output buffers. This limits the transmission

Commercial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0 to 70_C

Industrial . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –40 to 85_C

Military . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –55 to 125_C

of the noise coming from the ground or the V supply

of the core via the output buffers.

DC Characteristics

Base Part

Parameter

Symbol

Min

Typ

Max

Unit

= Commercial

= 24, 12, 6, 3 depending on buffer

2.4

Output Voltage

= –24, –12, –6, –3 depending on buffer

0.4

0.8

2.0

–5

Input Voltage

= V

–1

= V

Input Leakage Current

= V , with pull-up

–100

–5

–40

µA

= V , with pull-down

100

Output Leakage Current

= V or V

OUT

= V

160

OUT

Output Short Circuit Current

= V

–130

–60

0.4

0.3

OUT

Standby Current

= 5.25 V, V = V

nA/Gate

CCSB

Operating Current

0.4

DDOP

µA/Gate/

MHz

Input Capacitance

Output Capacitance

= 5.0 V, V = 2.0 V

2.5

OUT

= 2.0 V

OUT

Notes:

a. I = 24, 12, 6,3. Selection determined by FPGA or PLD data sheet requirements.

Rev. B – 25 May. 98

5–3

UG Series

characteristics are guaranteed for ULCs, and the actual

specification is determined by the original FPGA or

PLD data sheet plus any specific parameters that are

Internal Timing Characteristics

These timing parameters for selected macro cells are

provided for information only. Only pin-to-pin timing

agreed to separately by Atmel Wireless

Microcontrollers.

Conditions: V_DD= 5 V, Typical Process, Statistical Wire Length. All delays measured at V_IN/V_OUT= 2.5 V.

Macro Type

Parameter

Symbol

Min

Max^a

Max^b

Units

2-Input NAND

4-Input NAND

Inverter

NAND2

NAND4

INV

0.39

0.68

0.41

0.74

0.69

0.56

0.88

0.68

0.99

0.97

Propagation Time

Inverting Tri-State Buffer

TRISTAN

Enable Time

Setup Time

0.60

0.00

Hold Time

Pulse Width

Propagation Time

Enable Time

Reset Time

Resetable Latch

LATCHR

0.97

1.22

0.87

1.25

1.49

1.10

Setup Time

0.40

0.00

0.60

Hold Time

Pulse Width

Clock Delay Time

Reset Time

D Flip-Flop with Reset

FDFFR

0.95

0.81

0.80

0.68

0.80

0.68

2.97

1.96

2.49

1.74

3.27

1.60

2.49

1.74

3.27

1.60

1.22

0.94

0.95

0.74

0.95

0.74

8.18

4.23

6.42

3.47

7.17

3.30

6.42

3.47

7.17

3.30

PLH

PHL

PLH

PHL

PLH

PHL

PLH

PZH

TTL Compatible Input

Buffer

BUFINTTL

BIOT12

TTL Compatible I/O Buffer

Input Mode

Propagation Time

Output Buffer

BOUT6

TTL Compatible I/O Buffer

BIOT12

Enable Time

Propagation Time

Enable Time

PZL

PLH

PHL

PZH

Tri-State Output Buffer

B3STA12

PZL

Notes

a. Fan-outs are three internal loads for NAND2 and NAND4, four loads for all other internal macros and input buffers. Loading of B

20 pF, BIOT12 and B3STA12 are 30 pF.

OUT6

b. Fan-outs are six internal loads for NAND2, seven loads for NAND4, nine loads for all other internal macros and eight for the input buffer.

Loading of B

is 80 pF, BIOT12 and B3STA12 are 120 pF.

OUT6

Rev. B – 25 May. 98

5–4

UG Series

Derating Factors: t_P= K_Px K_tx K_Vx t_NOMINAL

Process

Best

0.82

Nominal

1.00

Worst

1.28

Ambient Temperature _C

–55

–40

125

0.74

0.79

0.92

1.00

1.15

1.20

1.32

Supply Voltage

2.7

3.13

1.58

3.3

3.47

1.41

3.6

1.35

4.5

1.1

4.75

1.05

5.25

0.96

5.5

1.89

1.66

1.49

1.23

0.93

guaranteed for ULCs are determined by the original

FPGA or PLD data sheet plus any specific parameters

that are agreed to separately by Atmel Wireless &

Microcontrollers.

External Timing Characteristics

(Over the Operating Range)

These timing parameters are provided for information

only. Actual pin-to-pin timing characteristics

Max

Parameter

Symbol

Base Part

SSO

Min

Unit

Typ

Max

UG01

5.0

6.0

7.0

8.5

9.5

6.5

7.5

8.5

10.0

11.0

7.5

UG04–UG09

UG14–UG20

UG33–UG90

UG120–UG140

UG01

9.0

10.5

13.0

14.5

10.0

11.5

13.0

15.0

16.5

Propagation Time

UG04–UG09

UG14–UG20

UG33–UG90

UG120–UG140

100

220

300

Clock Delay Time

Hold Time

tCO

0.0

UG01

6.5

7.5

10.0

11.5

13.0

15.0

16.5

UG04–UG09

UG14–UG20

UG33–UG90

UG120–UG140

100

220

300

8.5

Output Enable Time

10.0

11.0

Rev. B – 25 May. 98

5–5

UG Series

approximated as purely capacitive loads,

allowing this term to be treated as zero. TTL

loads source significant current in the low state,

but not the high state, allowing the second

summation to be ignored. If a 50% duty cycle is

assumed for dynamic outputs driving TTL loads,

this can be approximated as:

Power Consumption

Static Power Consumption for UG Series ULCs

There are three main factors to consider:

– Leakage in the core:

– P = V * I * number of used gates

CCSB

– P (mW) = V * (Σ * I /2 + Σ * I

) (TTL

OLn

OLm

– Leakage in inputs and tri-stated outputs:

– P = V * (I * N + I * M)

loads)

LIO

– where n are dynamic outputs and m are static low

outputs.

– Dynamic power dissipation for the internal gates:

– where: N = number of inputs

– M = number of tri-stated outputs

– Care must be taken to include the appropriate

figure for pins with pull-ups or pull-downs. In

practice, the static consumption calculation is

typically done to determine the standby current

of a device; in this case only those pins sourcing

– P (mW) = V * I

* Σ (N * f )/1000

g f g

DDOP

– where: N = number of gates toggling at

frequency f

– f = clock frequency of internal logic in MHz

– Note: If the actual toggle rates are not known, a

rule of thumb is to assume that the average used

gate is toggling at one half of the input clock

frequency.

current should be included, i.e. where V or

OUT

= V

– Dc power dissipation in driving I/O buffers due to

resistive loads:

– Dynamic power dissipation in the outputs:

– In practice, the static consumption calculation is

typically done to determine the standby current

of a device, and under circumstances where all of

the outputs are tri-stated or in input mode. So this

term is zero.

– P (mW) = V

* Σ f * (C

+ C )/1000

OUT n

– where: f = clocking frequency in MHz of output

– C = output load capacitance in pF of output n

– C

output capacitance from DC

OUT

– Global formula for static consumption:

Characteristics

– Global formula for dynamic consumption:

– P = P + P

LIO

– P = P + P + P

Dynamic Power Consumption for UG Series

ULCs

Example:

Static calculation

There are four main factors to consider:

– Static power dissipation is negligible compared to

dynamic and can be ignored.

– A 100-pin ULC with 3000 used gates, 10 inputs,

20 I/Os in input mode, 40 outputs all tri-stated.

No pull-ups or pull-downs. Half of the pins are at

– Dc power dissipation in I/O buffers due to resistive

, half at V . Input clock is not toggling. For

loads:

this example only the current calculation is

desired, so the V

dropped.

– P (mW) = V * Σ (D * I ) + ( V – V )

Ln OLn

term in the equations is

* Σ (D * I )

OHn

– where: Σ is a summation over all of the outputs

– P = 1 * 3000 = 3 mA

and I/Os.

– P

= ((10 + 20) * 5 + 40 * 5)/2 = 105 mA

LIO

– I

and I

are the appropriate values for

OLn

OHn

– P = 3 + 105 = 108 mA

driver n

Dynamic Calculation

– D = percentage of time n is being driven to V

– D = percentage of time n is being driven to

– We take a 16-bit resettable ripple counter which

is approximately 100 gates, operating at a clock

frequency of 33 MHz, which gives an average

clock frequency of 33 MHz/16 for each bit and

each output. There are no static outputs on this

device. Operation is at 5 V, and 6-mA outputs are

used and loaded at 25 pF. The output buffers are

driving CMOS loads.

– It is difficult to obtain an exact value for this

factor, since it is determined primarily by

external system parameters.

However, in

practice this can be simplified to one of two cases

where the device is either driving CMOS loads or

driving TTL loads. CMOS loads can be

Rev. B – 25 May. 98

5–6

UG Series

– P = 0

D Transient energy is absorbed at the end of the line to

prevent reflections which would lead to inaccurate

ATE measurements.

– P = 5 * 0.5 * 100 * 33/16/1000 = 0.5 mW

– P = 5 * 16 * 33/16 * (25 + 2)/1000 = 22 mW

– P = 0 + 0.5 + 22 = 22.5 mW

Figure 5. Typical ULC Test Conditions

Typical ULC Test Conditions

12 mA

For AC specification purposes, an improved output

loading scheme has been defined for Atmel Wireless &

Microcontrollers high-drive (24 mA), high-speed ULC

devices. The schematic below (Figure 5.) describes the

typical conditions for testing these ULC devices, using

the standard loading scheme commonly available on

high-end ATE.

D.U.T.

1.5 V

12 mA

Comp

Compared to a no-load condition, this provides the

following advantages:

D Output load is more representative of “real life”

conditions during transitions.

Rev. B – 25 May. 98

5–7

UG120 [ATMEL]

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