USD700 [ATMEL]
0.35 um ULC Series with Embedded DPRAM; 0.35微米ULC系列嵌入式DPRAM
| 型号： | USD700 |
| 厂家： | 
ATMEL |
| 描述： | 0.35 um ULC Series with Embedded DPRAM |
| 文件： | 总11页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High-performance ULC Family Suitable for Large-sized CPLDs and FPGAs
• From 46K Gates up to 780K Gates Supported
• From 18 Kbit to 390 Kbit DPRAM
• Compatible with Xilinx or Altera
• Pin-counts to Over 976 pins
• Any Pin–out Matched
• Full Range of Packages: DIP, SOIC, LCC/PLCC, PQFP/TQFP, BGA, PGA/PPGA
• Low Quiescent Current: 0.3 nA/gate
• Available in Commercial and Industrial Grades
• 0.35 µm Drawn CMOS, 3 and 4 Metal Layers
• Library Optimised for Synthesis, Floor Plan & Testability
Generation (ATPG)
0.35 µm ULC
Series with
Embedded
DPRAM
• High Speed Performances:
– 150 ps Typical Gate Delay @3.3V
– Typical 600 MHz Toggle Frequency @3.3V
– Typical 360 MHz Toggle Frequency @2.5V
• High System Frequency Skew Control:
– Clock Tree Synthesis Software
• Low Power Consumption:
– 0.25 µW/Gate/ MHz @3.3V
– 0.18 µW/Gate/ MHz @2.5V
UA1E
• Power on Reset (Internal)
• Standard 2, 4, 6, 8,10, 12 and 18mA I/Os
• CMOS/TTL/PCI LVCMOS, LVTTL, GTL, HSTL, LVDS Interfaces
• ESD (2 kV) and Latch-up Protected I/O
• High Noise & EMC Immunity:
– I/O with Slew Rate Control
– Internal Decoupling
– Signal Filtering between Periphery & Core
• Thick oxide matrices allowing 5V Compliance
• Internal Regulator 5V -> 3.3V
• PLL 0.35µm with Integrated Filter
Description
The UA1E series of ULCs is well suited for conversion of large sized CPLDs and
FPGAs. We can support within one ULC from 18 Kbits to 390 Kbits DPRAM and from
46 Kgates to 780 Kgates. Typically, ULC die size is 50% smaller than the equivalent
FPGA die size. DPRAM blocks are compatible with Xilinx or Altera FPGA blocks.
Devices are implemented in high–performance CMOS technology with 0.35µm
(drawn) channel lengths, and are capable of supporting flip–flop toggle rates of 200
MHz at 3.3V and 180 MHz at 2.5V, and input to output delays as fast as 150ps at 3.3V.
The architecture of the UA1E series allows for efficient conversion of many PLD archi-
tecture and FPGA device types with higher IO count. A compact RAM cell, along with
the large number of available gates allows the implementation of RAM in FPGA archi-
tectures that support this feature, as well as JTAG boundary–scan and scan–path
testing.
Conversion to the UA1E series of ULC can provide a significant reduction in operating
power when compared to the original PLD or FPGA. This is especially true when com-
pared to many PLD and CPLD architecture devices, which typically consume 100mA
or more even when not being clocked. The UA1E series has a very low standby con-
sumption of 0.3nA/gate typically commercial temperature, which would yield a
standby current of 42µA on a 144,000 gates design. Operating consumption is a strict
Rev. 4319B–ULC–12/03
1
function of clock frequency, which typically results in a power reduction of 50% to 90%
depending on the device being compared.
The UA1E series provides several options for output buffers, including a variety of drive
levels up to 18mA. Schmitt trigger inputs are also an option. A number of techniques are
used for improved noise immunity and reduced EMC emissions, including: several inde-
pendent power supply busses and internal decoupling for isolation; slew rate limited
outputs are also available if required.
The UA1E series is designed to allow conversion of high performance 3.3V devices as
well as 2.5V devices. Support of mixed supply conversions is also possible, allowing
optimal trade–offs between speed and power consumption.
Array Organization
Table 1. Matrices
Part Number
USD700
USD594
USD492
USD432
USD384
USD312
USD256
USD228
USD210
USD170(1)
USD134(1)
Max Pads
700
KGates
780
590
520
374
300
150
124
98
DPRAM Kbits
PLL
4
390
230
243
144
99
594
3
492
2
432
2
384
0
312
72
0
256
48
2
228
38
2
210
95
18
2
170
67
0
0
134
33
0
0
Note:
1. Arrays with internal regulators 5V -> 3.3V and Power on Reset.
2
4319B–ULC–12/03
Matrix Examples
Figure 1. ATL35_M484E1 Matrix with 108 DPRAMS and 2 PLL’s
PLL
DPRAM
PLL
3
4319B–ULC–12/03
Figure 2. ATL35_MI34E1 Matrix with 1 voltagte Regulator 5V - 3V and Power on Reset
5V - 3V
Regulator
POR
Architecture
The basic element of the UA1E family is called a cell. One cell can typically implement
between one to four FPGA gates. Cells are located contiguously throughout the core of
the device, with routing resources provided in three to four metal layers above the cells.
Some cell blockage does occur due to routing, and utilization will be significantly greater
with three metal routing than two. The sizes listed in the Product Outline are estimated
usable amounts using three metal layers. I/O cells are provided at each pad, and may
be configured as inputs, outputs, I/Os, VDD or VSS as required to match any FPGA or
PLD pinout.
In order to improve noise immunity within the device, separate VDD and VSS busses are
provided for the internal cells and the I/O cells.
I/O buffer interfacing
I/O Flexibility
All I/O buffers may be configured as input, output, bi-directional, oscillator or supply. A
level translator could be located close to each buffer.
4
4319B–ULC–12/03
I/O Options
Inputs
Each input can be programmed as TTL, CMOS, or Schmitt Trigger, with or without a pull
up or pull down resistor.
Fast Output Buffer
Fast output buffers are able to source or sink 2 to 18mA at 3.3V according to the chosen
option. 36mA achievable, using 2 pads.
Slew Rate Controlled Output
Buffer
In this mode, the p– and n–output transistors commands are delayed, so that they are
never set “ON” simultaneously, resulting in a low switching current and low noise. These
buffers are dedicated to very high load drive.
2.5V Compatibility
The UA1E series of ULC’s is fully capable of supporting high–performance operation at
2.5V or 3.3V. The performance specifications of any given ULC design however, must
be explicitly specified as 2.5V, 3.3V or both.
Power Supply and Noise In order to improve the noise immunity of the UA1E core matrix, several mechanisms
have been implemented inside the UA1E arrays. Two types of protection have been
added: one to limit the I/O buffer switching noise and the other to protect the I/O buffers
against the switching noise coming from the matrix.
Protection
The speed and density of the UA1E technology cause large switching current spikes, for
example when:
•
•
16 high current output buffers switch simultaneously, or
10% of the 700 000 gates are switching within a window of 1ns.
Sharp edges and high currents cause some parasitic elements in the packaging to
become significant. In this frequency range, the package inductance and series resis-
tance should be taken into account. It is known that an inductor slows down the setting
time of the current and causes voltage drops on the power supply lines. These drops
can affect the behavior of the circuit itself or disturb the external application (ground
bounce).
I/O Buffers Switching Protection Three features are implemented to limit the noise generated by the switching current:
•
•
The power supplies of the input and output buffers are separated.
The rise and fall times of the output buffers can be controlled by an internal
regulator.
•
A design rule concerning the number of buffers connected on the same power
supply line has been imposed.
Matrix Switching Current
Protection
This noise disturbance is caused by a large number of gates switching simultaneously.
To allow this without impacting the functionality of the circuit, three new features have
been added:
•
Decoupling capacitors are integrated directly on the silicon to reduce the power
supply drop.
•
A power supply network has been implemented in the matrix. This solution reduces
the number of parasitic elements such as inductance and resistance and constitutes
an artificial VDD and Ground plane. One mesh of the network supplies approximately
150 cells.
•
A low pass filter has been added between the matrix and the input to the output
buffer. This limits the transmission of the noise coming from the ground or the VDD
supply of the matrix to the external world via the output buffers.
5
4319B–ULC–12/03
PLL Characterisitics
The following list the caracteristics of the PLL 0.35µm with integrated filter:
•
•
•
•
•
•
•
Input frequency from 5 to 100 MHz
Outout frequency from 20 to 200 MHz
Frequency multiplication by 2 or 4
Phase shifter 0, 90, 180, 270 degrees
Output lock signal: lock_in time: 50us
Supply: 3.3V
Power consumption max: 3.32mA
Application
Use for XILINX and ALTERA conversions, in the following cases:
•
•
•
•
clock deskew
frequency synthesis
clock latency reduction
phase shift
Note:
For detailed information, please contact our technical center.
6
4319B–ULC–12/03
Electrical Characteristics
Absolute Maximum Ratings
*NOTICE:
Stresses at or above those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions above those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions may affect device reliability.
Operating Temperature
Commercial..........................................................0° to 70°C
Industrial...............................................................-40° to 85°C
Max Supply Core Voltage (VDD)..........................3.6V
Max Supply Periphery Voltage (VDD5).................5.5V
Input Voltage (VIN)VDD.............................................+0.5V
5V Tolerant/Compliant VDD5................................+0.5V
Storage Temperature...........................................-65° to 150°C
Operating Ambient Temperature.......................-55° to 125°C
This value is based on the maximum allowable
die temperature and the thermal resistance of
the package.
7
4319B–ULC–12/03
DC Characteristics
2.5V
Specified at VDD = +2.5V + 5%
Symbol
TA
Parameter
Buffer
All
Min
-40
2 . 3
Typ
Max
+85
2 . 7
1 0
Unit
°C
Conditions
Operating Temperature
S u p p l y Vo l t a g e
V D D
IIH
A l l
2 . 5
V
H i g h l e v e l i n p u t c u r r e n t
C M O S
PCI
µ A
V IN = VDD,VDD = VDD (max)
VIN = VSS,VDD = VDD (max)
10
IIL
Low Level input current
CMOS
PCI
-10
-10
µA
High-Impedance State
Output Current
VIN = VDD or VSS,
IOZ
IOS
All
10
µA
VDD = VDD (max), No Pull-up
VOUT = VDD,VDD = VDD (max)
VOUT = VSS,VDD = VDD (max)
O u t p u t s h o r t - c i r c u i t c u r r e n t
P O 11
9
6
m A
PO11
CMOS
VIH
VIL
High-level Input Voltage
0.7VDD
0.475VDD
0.7VDD
V
V
PCI
CMOS Schmitt
CMOS
1.5
Low-Level Input Voltage
0.3VDD
0.325VDD
0.3VDD
PCI
CMOS Schmitt
CMOS Schmitt
1.0
0.5
Vhys
VOH
Hysteresis
V
V
IOH = 1.4mA,VDD = VDD (min)
IOH = -500µA
High-Level output voltage
PO11
PCI
0.7VDD
0.9VDD
IOL = 1.4mA,VDD = VDD (min)
IOL = 1.5mA
VOL
Low-Level output voltage
PO11
PCI
0.4
V
0.1VDD
8
4319B–ULC–12/03
3.3V
Specified at VDD = +3.3V + 5%
Symbol
TA
Parameter
Buffer
All
Min
-40
3 . 0
Typ
Max
+85
3 . 6
1 0
Unit
°C
Conditions
Operating Temperature
S u p p l y Vo l t a g e
VDD
A l l
3 . 3
V
IIH
H i g h l e v e l i n p u t c u r r e n t
C M O S
PCI
µ A
V IN = VDD,VDD = VDD (max)
VIN = VSS,VDD = VDD (max)
10
IIL
Low Level input current
CMOS
PCI
-10
-10
µA
High-Impedance State
Output Current
VIN = VDD or VSS,
IOZ
IOS
All
10
µA
VDD = VDD (max), No Pull-up
VOUT = VDD,VDD = VDD (max)
VOUT = VSS,VDD = VDD (max)
O u t p u t s h o r t - c i r c u i t c u r r e n t
P O 11
1 4
-9
m A
PO11
CMOS, LVTTL
PCI
VIH
VIL
High-level Input Voltage
2.0
0.475VDD
2.0
V
V
CMOS Schmitt
CMOS
1.7
Low-Level Input Voltage
0.8
PCI
0.325VDD
CMOS/TTL-level
Schmitt
1.1
0.6
0.8
Vhys
VOH
Hysteresis
TTL-level Schmitt
V
V
IOH = 2mA,VDD = VDD (min)
IOH = -500µA
High-Level output voltage
PO11
PCI
0.7VDD
0.9VDD
IOL = 2mA,VDD = VDD (min)
IOL = 1.5mA
VOL
Low-Level output voltage
PO11
PCI
0.4
V
0.1VDD
9
4319B–ULC–12/03
5V
Specified at VCC = +5V +/- 5%
Symbol
Parameter
Buffer
All
Min
-55
3.0
4.5
Typ
Max
+125
3.6
Unit
°C
V
Conditions
TA
VDD
VDD5
IIH
Operating Temperature
Supply Voltage
5V Tolerant
5V Compliant
C M O S
3.3
5.0
Supply Voltage
5.5
V
H i g h l e v e l i n p u t c u r r e n t
Low Level input current
1 0
µ A
µA
V IN = VDD,VDD = VDD (max)
VIN = VSS,VDD = VDD (max)
IIL
CMOS
-10
-10
High-Impedance State
Output Current
VIN = VDD or VSS,
IOZ
IOS
All
10
µA
VDD = VDD (max), No Pull-up
VOUT = VDD,VDD = VDD (max)
VOUT = VSS,VDD = VDD (max)
O u t p u t s h o r t - c i r c u i t c u r r e n t
P O 11 V
8
m A
PO11V
PICV5
-7
VIH
VIL
High-level Input Voltage
2.0
2.0
5.0
5.5
V
V
CMOS/TTL-level
Schmitt
1.7
0.5VCC
1.1
Low-Level Input Voltage
PICV5
0.8
0.8
CMOS/TTL-level
Schmitt
Vhys
VOH
Hysteresis
TTL-level Schmitt
PO11V
0.6
V
V
IOH = -1.7mA
IOH = -1.7mA
High-Level output voltage
0.7VDD
0.7VCC
PO11V5
PO11V
VOL
Low-Level output voltage
0.5
0.5
V
IOL = 1.7mA
PO11V5
I/O Buffer
Symbol
Parameter
Typ
Unit
Conditions
3.3V
C IN
C OUT
C I/O
Capacitance, Input Buffer (Die)
Capacitance, Output Buffer (Die)
Capacitance, Bidirectional
2.4
5.6
6.6
pF
pF
pF
3.3V
3.3V
10
4319B–ULC–12/03
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Printed on recycled paper.
4319B–ULC–12/03
/xM
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