WGM01 [ATMEL]
High Performance, Low Power Atmel AVR 8-bit Microcontroller Advanced RISC Architecture; 高性能，低功耗的Atmel公司的AVR 8位微控制器先进的RISC架构
| 型号： | WGM01 |
| 厂家： | 
ATMEL |
| 描述： | High Performance, Low Power Atmel AVR 8-bit Microcontroller Advanced RISC Architecture |
| 文件： | 总294页 (文件大小：5988K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
Features
• High Performance, Low Power Atmel AVR 8-bit Microcontroller
• Advanced RISC Architecture
– 123 Powerful Instructions - Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
• Non-volatile Program and Data Memories
– 16Kbyte of In-system Programmable (ISP) Program Memory Flash
• Endurance: 10,000 Write/Erase Cycles
– 512Bytes In-system Programmable EEPROM
• Endurance: 100,000 Write/Erase Cycles
– 512Bytes Internal SRAM
125kHz LF
Reader/Writer
with Integrated
Atmel AVR
– Programming Lock for Self-programming Flash Program and EEPROM Data
Security
– Low Size LIN/UART Software In-system Programmable
• Peripheral Features
– LF-RFID Reader/Writer Front End
Microcontroller
• Carrier Frequency fOSC = 100kHz to 150kHz
• Typical Data Rate up to 5Kbaud at 125kHz
• Suitable for Manchester anf Biphase Modulation
• Does not Require an External Crystal
• Power Supply from the Car Battery or from 5V Regulated Voltage
• Optimized for Car Immobilizer Applications
• Tuning Capability
Atmel ATA5505
Preliminary
– LIN 2.1 and 1.3 Controller or 8-bit UART
– 8-bit Asynchronous Timer/Counter 0:
• 10-bit Clock Prescaler
• 1 Output Compare or 8-bit PWM Channel
– 16-bit Synchronous Timer/Counter 1:
• 10-bit Clock Prescaler
• External Event Counter
• 2 Output Compares Units or 16-bit PWM Channels each Driving up to 4 Output
Pins
– Master/Slave SPI Serial Interface
– Universal Serial Interface (USI) with Start Condition Detector (Master/Slave SPI,
TWI, ...)
– 10-bit ADC:
• 11 Single-ended Channels
• 8 Differential ADC Channel Pairs with Programmable Gain (8x or 20x)
– On-chip Analog Comparator with Selectable Voltage Reference
– 100µA ±10% Current Source (LIN Node Identification)
– On-chip Temperature Sensor
– Programmable Watchdog Timer with Separate On-chip Oscillator
9219A–RFID–01/11
• Special Microcontroller Features
– Dynamic Clock Switching (External/Internal RC/Watchdog Clock) for Power Control, EMC Reduction
– DebugWIRE On-chip Debug (OCD) System
– Hardware In-System Programmable (ISP) via SPI Port
– External and Internal Interrupt Sources
– Interrupt and Wake-up on Pin Change
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated RC Oscillator 8MHz
– 4-16 MHz and 32 KHz Crystal/Ceramic Resonator Oscillators
• Operating Voltage:
– 7 to 16V
– 4.5 to 5.5V Internal Voltage Regulator available for Digital and Logic
• Operating Temperature: –40°C to +85°C
Applications
• Access Control Units
• Animal Identification
• Component Authetication
• Brand Protection
• Automation
• Industrial
• Waste Management
• Process Control
2
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
1. Description
The Atmel® ATA5505 is an Atmel AVR® microcontroller with LF-RFID reader/writer front end
and LIN interface for low cost network applications.
The Atmel ATA5505 incorporates the energy-transfer circuit for supplying the transponder. It
consists of an on-chip power supply, an oscillator, and a coil driver optimized for automo-
tive-specific distances. It also includes all signal-processing circuits which are necessary to
transform the small input signal into a microcontroller-compatible signal.
The Atmel ATA5505 integrates a low-power CMOS 8-bit microcontroller based on the Atmel
AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle,
the ATA5505 achieves throughputs approaching 1 MIPS per MHz, allowing the system
designer to optimize power consumption versus processing speed.
The Atmel AVR core combines a rich instruction set with 32 general purpose working regis-
ters. All the 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in a single instruction executed in one clock cycle. The
resulting architecture is more code-efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
The Atmel ATA5505 provides the following features: 16K byte of in-system programmable
Flash, 512bytes EEPROM, 512bytes SRAM, 16 general purpose I/O lines, 32 general purpose
working registers, one 8-bit timer/counter with compare modes, one 8-bit high speed
timer/counter, a universal serial interface, a LIN controller, internal and external interrupts, an
11-channel, 10-bit ADC, a programmable watchdog timer with internal oscillator, and three
software selectable power saving modes. The Idle mode stops the CPU while allowing the
SRAM, timer/counter, ADC, analog comparator, and interrupt system to continue functioning.
Power-down mode saves the register contents, disabling all chip functions until the next inter-
rupt or hardware reset. To minimize switching noise during ADC conversions, ADC noise
reduction mode stops the CPU and all I/O modules except ADC,
The device is manufactured using Atmel’s high-density non-volatile memory technology. The
on-chip ISP Flash allows the program memory to be re-programmed in-system via an SPI
serial interface, by a conventional non-volatile memory programmer or by an on-chip boot
code running on the Atmel AVR core. The boot program can use any interface to download the
application program in the Flash memory. By combining an 8-bit RISC CPU with in-system
self-programmable Flash on a monolithic chip, the Atmel ATA5505 is a powerful microcon-
troller providing a highly flexible and cost-effective solution to many embedded control
applications.
The Atmel ATA5505 AVR is supported with a full suite of program and system development
tools including: C compilers, macro assemblers, program debuggers/simulators, in-circuit
emulators, and evaluation kits.
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9219A–RFID–01/11
1.1
System Block Diagram
The system block diagram for a stand alone reader application is shown in Figure 1-1. No
additional microcontroller is required..
Figure 1-1. System Block Diagram - Stand Alone Reader
Atmel ATA5505
T/ATA5551
ATA5557/67
ATA5577
ATA5558
ATA5575
Q5
Osc
Frontend
MCU
Core
SPI
NF
Immobilizer
Stack
Read Channel
Successor
A system block diagram for a reader station application with a LIN transceiver IC is shown in
Figure 1-2. The reader is then communicating with a central unit.
Figure 1-2. System Block Diagram - Reader with LIN Connection
Reader
Atmel ATA5505
T/ATA5551
ATA5557/67
ATA5577
ATA5558
ATA5575
Q5
Osc
Frontend
MCU
Core
LIN
UART
LIN
Central
Unit
TRx
NF
Immobilizer
Stack
Read Channel
Successor
All Atmel® LF-RFID tag ICs can be read by the ATA5505: e5530, TK5530, e5551, T5551,
TK5551, e5552, TK5552, e5554, T5555, Q5, T5557, ATA5567, ATA5558, T5561, TK5561,
ATA5577, ATA5575.
1.2
Block Diagram
In Figure 1-3 on page 5 the basic architecture of the Atmel ATA5505 consisting of the Atmel
AVR and the front end is shown. The Atmel AVR is a low-power CMOS 8-bit microcontroller
with RISC architecture. The Atmel AVR includes several features. The main features are
in-system programmable Flash, EEPROM, SRAM, Ports A and B as general purpose I/O
lines, a timer and a LIN controller. The details of the front end are shown in Figure 1-4 on page
5.
4
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
Figure 1-3. Block Diagram
GND
VCC
Atmel ATA5505
Watchdog
Power / Reset
EEPROM
Flash
SRAM
AVCC
A/D
converter
Timer
AVR CPU
Reader Frontend
LIN / UART
AGND
Input
Control (0 to 3)
COIL1
COIL2
DGND
Input
SPI
Port B
Port A
PB (0 to 7)
PA (0 to 7)
Figure 1-4 shows the front end in more detail. The circuit block depicted consists of the
receiver, an internal oscillator and driver for the coil, and a power supply unit.
Figure 1-4. Reader Front End Block Diagram
DVS
VEXT
VS
VBatt
Frontend
Standby
Power supply
Driver
MS
COIL1
= 1
Control (0 to 3)
CFE
Frequency
adjustment
COIL2
DGND
&
Oscillator
RF
Output
Input
Lowpass filter
Schmitt trigger
&
OE
HIPASS
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9219A–RFID–01/11
1.3
Pin Configuration
Figure 1-5. Pinout Atmel® ATA5505 - QFN38 5 mm by 7 mm
38 37 36 35 34 33 32
PA5
PA6
GND
PA1
1
31
30
29
28
27
26
25
24
23
22
21
20
2
PA7
PA0
3
PB7/RST
PB6
PB0
PB1
PB2
PB3
RF
4
5
PB5
6
Atmel
ATA5505
PB4/XTAL
VDD
7
8
OUTPUT
OE
GAIN
VS
9
10
11
12
INPUT
MS
STBY
VBAT
13 14 15 16 17 18 19
1.4
Pin Description
Table 1-1.
Pin
Pin Description
Symbol
Function
PA5
PCINT5
ADC5
T1
GPIO Port A – Pin 5
PCINT5 (Pin Change Interrupt 5)
ADC5 (ADC Input Channel 5)
T1 (Timer/Counter1 Clock Input)
1
USCK
SCL
SCK
USCK (Three-wire Mode USI Alternate Clock Input)
SCL (Two-wire Mode USI Alternate Clock Input)
SCK (SPI Master Clock)
PA6
PCINT6
ADC6
AIN0
GPIO Port A – Pin 6
PCINT6 (Pin Change Interrupt 6)
ADC6 (ADC Input Channel 6)
AIN0 (Analog Comparator Negative Input)
SS (SPI Slave Select Input)
2
3
SS
PA7
PCINT7
ADC7
AIN1
XREF
AREF
GPIO Port A – Pin 7
PCINT7 (Pin Change Interrupt 7)
ADC7 (ADC Input Channel 7)
AIN1 (Analog Comparator Positive Input)
XREF (Internal Voltage Reference Output)
AREF (External Voltage Reference Input)
PB7
PCINT15
ADC10
OC1BX
RESET
dW
GPIO Port B – Pin 7
PCINT15 (Pin Change Interrupt 15)
ADC10 (ADC Input Channel 10)
OC1BX (Output Compare and PWM Output B-X for Timer/Counter1)
RESET (Reset input pin)
dW (debugWIRE I/O)
4
6
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
Table 1-1.
Pin
Pin Description
Symbol
Function
PB6
PCINT14
ADC9
OC1AX
INT0
GPIO Port B – Pin 6
PCINT14 (Pin Change Interrupt 14)
ADC9 (ADC Input Channel 9)
OC1AX (Output Compare and PWM Output A-X for Timer/Counter 1)
INT0 (External Interrupt0 Input)
5
6
7
PB5
PCINT13
ADC8
OC1BW
XTAL2
CLKO
GPIO Port B – Pin 5
PCINT13 (Pin Change Interrupt 13)
ADC8 (ADC Input Channel 8)
OC1BW (Output Compare and PWM Output B-W for Timer/Counter 1)
XTAL2 (Chip Clock Oscillator Pin 2)
CLKO (System Clock Output)
PB4
PCINT12
OC1AW
XTAL1
CLKI
GPIO Port B – Pin 4
PCINT12 (Pin Change Interrupt 12)
OC1AW (Output Compare and PWM Output A-W for Timer/Counter 1)
XTAL1 (Chip clock Oscillator pin 1)
CLKI (External Clock Input)
8
VDD
OUTPUT
OE
Atmel® AVR® Supply Voltage
9
Reader Data Output
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
Reader Station Data Output Enable
Reader Station Data Input
Reader Station Mode Select
Reader Station: Carrier Frequency Enable
Digital Ground (Driver Ground)
Reader Coil Driver 2
INPUT
MS
CFE
DGND
COIL 2
COIL 1
VEXT
DVS
Reader Coil Driver 1
Reader External Power Supply
Reader Driver Supply Voltage
Ground
GND
VBATT
STANDBY
VS
Battery Voltage for Reader
Front End Standby Input
Internal Power Supply (5V) for Reader
HIPASS DC Decoupling (Gain)
Frequency Adjustment
HIPASS
RF
PB3
GPIO Port B - Pin 3
25
PCINT11
OC1BV
PCINT11 (Pin Change Interrupt 11)
OC1BV (Output Compare and PWM Output B-V for Timer/Counter 1)
PB2
PCINT10
OC1AV
USCK
SCL
GPIO Port B – Pin 2
PCINT10 (Pin Change Interrupt 10)
OC1AV (Output Compare and PWM Output A-V for Timer/Counter 1)
USCK (Three-wire Mode USI Default Clock Input)
SCL (Two-wire Mode USI Default Clock Input)
26
PB1
PCINT9
OC1BU
DO
GPIO Port B – Pin 1
PCINT9 (Pin Change Interrupt 9)
OC1BU (Output Compare and PWM Output B-U for Timer/Counter 1)
DO (Three-wire Mode USI Default Data Output)
27
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9219A–RFID–01/11
Table 1-1.
Pin
Pin Description
Symbol
Function
PB0
PCINT8
OC1AU
DI
GPIO Port B – Pin 0
PCINT8 (Pin Change Interrupt 8)
OC1AU (Output Compare and PWM Output A-U for Timer/Counter 1)
DI (Three-wire Mode USI Default Data Input)
SDA (Two-wire Mode USI Default Data Input / Output)
28
29
30
SDA
PA0
PCINT0
ADC0
RXD
GPIO Port A – Pin 0
PCINT0 (Pin Change Interrupt 0)
ADC0 (ADC Input Channel 0)
RXD (UART Receive Pin)
RXLIN (LIN Receive Pin)
RXLIN
PA1
PCINT1
ADC1
TXD
GPIO Port A – Pin 1
PCINT1 (Pin Change Interrupt 1)
ADC1 (ADC Input Channel 1)
TXD (UART Transmit Pin)
TXLIN (LIN Transmit Pin)
TXLIN
31
32
33
GND
GND
GND
Ground
Ground
Ground
PA2
PCINT2
ADC2
OCA0A
DO
GPIO Port A – Pin 2
PCINT2 (Pin Change Interrupt 2)
ADC2 (ADC Input Channel 2)
OC0A (Output Compare and PWM Output A for Timer/Counter 0)
DO (Three-wire Mode USI Alternate Data Output)
MISO (SPI Master Input/Slave Output)
34
MISO
PA3
PCINT3
ADC3
ISRC
GPIO Port A – Pin 3
PCINT3 (Pin Change Interrupt 3)
ADC3 (ADC Input Channel 3)
ISRC (Current Source Pin)
INT1 (External Interrupt1 Input)
35
INT1
36
37
AVCC
AGND
Analog Supply Voltage
Analog Ground
PA4
PCINT4
ADC4
ICP1
DI
GPIO Port A – Pin 4
PCINT4 (Pin Change Interrupt 4)
ADC4 (ADC Input Channel 4)
ICP1 (Timer/Counter 1 Input Capture Trigger)
DI (Three-wire Mode USI Alternate Data Input)
SDA (Two-wire Mode USI Alternate Data Input/Output)
MOSI (SPI Master Output/Slave Input)
38
SDA
MOSI
8
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
1.4.1
Port A (PA7..PA0)
Port A is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).
The Port A output buffers have symmetrical drive characteristics with both high sink and
source capability. As inputs, Port A pins that are externally pulled low will source current if the
pull-up resistors are activated. The Port A pins are tri-stated when a reset condition becomes
active, even if the clock is not running. Port A also serves the functions of various special fea-
tures of the microcontroller.
1.4.2
Port B (PB7..PB0)
Port B is an 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit).
The Port B output buffers have symmetrical drive characteristics with both high sink and
source capability. As inputs, Port B pins that are pulled low externally will source current if the
pull-up resistors are activated. The Port B pins are tri-stated when a reset condition becomes
active, even if the clock is not running. Port B also serves the functions of various special fea-
tures of the microcontroller.
1.4.3
1.4.4
RESET
Device reset
XTAL1 and XTAL2
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be
configured for use as an On-chip oscillator. Either a quartz crystal or a ceramic resonator may
be used.
1.5
Atmel AVR Description
The microcontroller is a low-power CMOS 8-bit microcontroller based on the Atmel® AVR®
enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the
microcontroller achieves throughputs approaching 1MIPS per MHz, allowing the system
designer to optimize power consumption versus processing speed.
The Atmel AVR core combines a rich instruction set with 32 general purpose working regis-
ters. All 32 registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two
independent registers to be accessed in a single instruction executed in one clock cycle. The
resulting architecture is more code-efficient while achieving throughputs up to ten times faster
than conventional CISC microcontrollers.
The microcontroller provides the following features: 16K byte of in-system programmable
Flash, 512bytes EEPROM, 512bytes SRAM, 16 general purpose I/O lines, 32 general purpose
working registers, one 8-bit timer/counter with compare modes, one 8-bit high speed
timer/counter, a universal serial interface, a LIN controller, internal and external interrupts, an
11-channel, 10-bit ADC, a programmable watchdog timer with internal oscillator, and three
software selectable power saving modes. The Idle mode stops the CPU while allowing the
SRAM, timer/counter, ADC, analog comparator, and interrupt system to continue functioning.
Power-down mode saves the register contents, disabling all chip functions until the next inter-
rupt or hardware reset. To minimize switching noise during ADC conversions, ADC noise
reduction mode stops the CPU and all I/O modules except ADC.
9
9219A–RFID–01/11
The device is manufactured using Atmel®’s high- density non-volatile memory technology. The
on-chip ISP Flash allows the program memory to be re-programmed In-system through via an
SPI serial interface, by a conventional non-volatile memory programmer or by an on-chip boot
code running on the Atmel AVR® core. The boot program can use any interface to download
the application program in the Flash memory. By combining an 8-bit RISC CPU with In-system
self-programmable Flash on a monolithic chip, the Atmel ATA5505 is a powerful microcon-
troller that provides a highly flexible and cost- effective solution to many embedded control
applications.
The embedded microcontroller is supported with a full suite of program and system develop-
ment tools including: C compilers, macro assemblers, program debuggers/simulators,
in-circuit emulators, and evaluation kits.
1.6
1.7
Resources
A comprehensive set of development tools, application notes and datasheets are available for
download at http://www.atmel.com/avr.
About Code Examples
This documentation contains simple code examples that briefly show how to use various parts
of the device. These code examples assume that the part-specific header file is included
before compilation. Be aware that not all C compiler vendors include bit definitions in the
header files and interrupt handling in C is compiler-dependent. Please consult the C compiler
documentation for more details.
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Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
2. AVR CPU Core
2.1
Overview
This section discusses the Atmel® AVR® core architecture in general. The main function of the
CPU core is to ensure correct program execution. The CPU must therefore be able to access
memories, perform calculations, control peripherals, and handle interrupts.
Figure 2-1. Block Diagram of the Atmel AVR Architecture
Data Bus 8-bit
Program
Counter
Status
and Control
Flash
Program
Memory
Interrupt
Unit
32 x 8
General
Purpose
Registrers
Instruction
Register
Watchdog
Timer
Instruction
Decoder
A.D.C.
ALU
Analog
Comparator
Control Lines
I/O Module1
I/O Module 2
I/O Module n
Data
SRAM
EEPROM
I/O Lines
In order to maximize performance and parallelism, the Atmel AVR uses a Harvard architecture
– with separate memories and buses for program and data. Instructions in the Program mem-
ory are executed with a single level pipelining. While one instruction is being executed, the
next instruction is pre-fetched from the Program memory. This concept enables instructions to
be executed in every clock cycle. The Program memory is In-System Reprogrammable Flash
memory. The fast-access Register File contains 32 x 8-bit general purpose working registers
with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU)
operation. In a typical ALU operation, two operands are output from the Register File, the
operation is executed, and the result is stored back in the Register File – in one clock cycle.
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Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data
Space addressing – enabling efficient address calculations. One of the these address pointers
can also be used as an address pointer for look up tables in Flash Program memory. These
added function registers are the 16-bit X-, Y-, and Z-register, described later in this section.
The ALU supports arithmetic and logic operations between registers or between a constant
and a register. Single register operations can also be executed in the ALU. After an arithmetic
operation, the Status Register is updated to reflect information about the result of the
operation.
Program flow is provided by conditional and unconditional jump and call instructions, able to
directly address the whole address space. Most Atmel® AVR® instructions have a single 16-bit
word format. Every Program memory address contains a 16- or 32-bit instruction.
During interrupts and subroutine calls, the return address Program Counter (PC) is stored on
the Stack. The Stack is effectively allocated in the general data SRAM, and consequently the
Stack size is only limited by the total SRAM size and the usage of the SRAM. All user pro-
grams must initialize the SP in the Reset routine (before subroutines or interrupts are
executed). The Stack Pointer (SP) is read/write accessible in the I/O space. The data SRAM
can easily be accessed through the five different addressing modes supported in the Atmel
AVR architecture.
The memory spaces in the Atmel AVR architecture are all linear and regular memory maps.
A flexible interrupt module has its control registers in the I/O space with an additional Global
Interrupt Enable bit in the Status Register. All interrupts have a separate Interrupt Vector in the
Interrupt Vector table. The interrupts have priority in accordance with their Interrupt Vector
position. The lower the Interrupt Vector address, the higher the priority.
The I/O memory space contains 64 addresses for CPU peripheral functions as Control Regis-
ters, SPI, and other I/O functions. The I/O memory can be accessed directly, or as the Data
Space locations following those of the Register File, 0x20 - 0x5F.
2.2
2.3
ALU – Arithmetic Logic Unit
The high-performance Atmel AVR ALU operates in direct connection with all the 32 general
purpose working registers. Within a single clock cycle, arithmetic operations between general
purpose registers or between a register and an immediate are executed. The ALU operations
are divided into three main categories – arithmetic, logical, and bit-functions. Some implemen-
tations of the architecture also provide a powerful multiplier supporting both signed/unsigned
multiplication and fractional format. See the “Instruction Set” section for a detailed description.
Status Register
The Status Register contains information about the result of the most recently executed arith-
metic instruction. This information can be used for altering program flow in order to perform
conditional operations. Note that the Status Register is updated after all ALU operations, as
specified in the Instruction Set Reference. This will in many cases remove the need for using
the dedicated compare instructions, resulting in faster and more compact code.
The Status Register is not automatically stored when entering an interrupt routine and
restored when returning from an interrupt. This must be handled by software.
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Atmel ATA5505 [Preliminary]
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Atmel ATA5505 [Preliminary]
2.3.1
SREG – Atmel AVR Status Register
The Atmel® AVR® Status Register – SREG – is defined as:
Bit
7
I
6
T
5
H
4
S
3
V
2
N
1
Z
0
C
SREG
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bit 7 – I: Global Interrupt Enable
The Global Interrupt Enable bit must be set for the interrupts to be enabled. The individual
interrupt enable control is then performed in separate control registers. If the Global Interrupt
Enable Register is cleared, none of the interrupts are enabled independent of the individual
interrupt enable settings. The I-bit is cleared by hardware after an interrupt has occurred, and
is set by the RETI instruction to enable subsequent interrupts. The I-bit can also be set and
cleared by the application with the SEI and CLI instructions, as described in the instruction set
reference.
• Bit 6 – T: Bit Copy Storage
The Bit Copy instructions BLD (Bit LoaD) and BST (Bit STore) use the T-bit as source or des-
tination for the operated bit. A bit from a register in the Register File can be copied into T by
the BST instruction, and a bit in T can be copied into a bit in a register in the Register File by
the BLD instruction.
• Bit 5 – H: Half Carry Flag
The Half Carry Flag H indicates a Half Carry in some arithmetic operations. Half Carry is use-
ful in BCD arithmetic. See the “Instruction Set Description” for detailed information.
• Bit 4 – S: Sign Bit, S = N
V
The S-bit is always an exclusive or between the Negative Flag N and the Two’s Complement
Overflow Flag V. See the “Instruction Set Description” for detailed information.
• Bit 3 – V: Two’s Complement Overflow Flag
The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the
“Instruction Set Description” for detailed information.
• Bit 2 – N: Negative Flag
The Negative Flag N indicates a negative result in an arithmetic or logic operation. See the
“Instruction Set Description” for detailed information.
• Bit 1 – Z: Zero Flag
The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction
Set Description” for detailed information.
• Bit 0 – C: Carry Flag
The Carry Flag C indicates a carry in an arithmetic or logic operation. See the “Instruction Set
Description” for detailed information.
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2.4
General Purpose Register File
The Register File is optimized for the Atmel® AVR® Enhanced RISC instruction set. In order to
achieve the required performance and flexibility, the following input/output schemes are sup-
ported by the Register File:
• One 8-bit output operand and one 8-bit result input
• Two 8-bit output operands and one 8-bit result input
• Two 8-bit output operands and one 16-bit result input
• One 16-bit output operand and one 16-bit result input
Figure 2-2 shows the structure of the 32 general purpose working registers in the CPU.
Figure 2-2. Atmel AVR CPU General Purpose Working Registers
7
0
Addr.
0x00
0x01
0x02
R0
R1
R2
…
R13
R14
R15
R16
R17
…
0x0D
0x0E
0x0F
0x10
0x11
General
Purpose
Working
Registers
R26
R27
R28
R29
R30
R31
0x1A
0x1B
0x1C
0x1D
0x1E
0x1F
X-register Low Byte
X-register High Byte
Y-register Low Byte
Y-register High Byte
Z-register Low Byte
Z-register High Byte
Most of the instructions operating on the Register File have direct access to all registers, and
most of them are single cycle instructions.
As shown in Figure 2-2, each register is also assigned a Data memory address, mapping them
directly into the first 32 locations of the user Data Space. Although not being physically imple-
mented as SRAM locations, this memory organization provides great flexibility in access of the
registers, as the X-, Y- and Z-pointer registers can be set to index any register in the file.
2.4.1
The X-register, Y-register, and Z-register
The registers R26..R31 have some added functions to their general purpose usage. These
registers are 16-bit address pointers for indirect addressing of the data space. The three indi-
rect address registers X, Y, and Z are defined as described in Figure 2-3 on page 15.
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Figure 2-3. The X-, Y-, and Z-registers
15
XH
XL
YL
ZL
0
0
X-register
Y-register
Z-register
7
0
0
7
R27 (0x1B)
R26 (0x1A)
15
YH
0
0
7
7
R29 (0x1D)
R28 (0x1C)
15
ZH
0
0
0
7
7
R31 (0x1F)
R30 (0x1E)
In the different addressing modes these address registers have functions as fixed displace-
ment, automatic increment, and automatic decrement (see the instruction set reference for
details).
2.5
Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always
points to the top of the Stack. Note that the Stack is implemented as growing from higher
memory locations to lower memory locations. This implies that a Stack PUSH command
decreases the Stack Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM must be defined by the program
before any subroutine calls are executed or interrupts are enabled. The Stack Pointer must be
set to point above 0x60. The Stack Pointer is decremented by one when data is pushed onto
the Stack with the PUSH instruction, and it is decremented by two when the return address is
pushed onto the Stack with subroutine call or interrupt. The Stack Pointer is incremented by
one when data is popped from the Stack with the POP instruction, and it is incremented by two
when data is popped from the Stack with return from subroutine RET or return from interrupt
RETI.
The Atmel® AVR® Stack Pointer is implemented as two 8-bit registers in the I/O space. The
number of bits actually used is implementation dependent. Note that the data space in some
implementations of the Atmel AVR architecture is so small that only SPL is needed. In this
case, the SPH Register will not be present
2.5.1
SPH and SPL – Stack Pointer Register
Bit
15
SP15
SP7
7
14
SP14
SP6
6
13
SP13
SP5
5
12
SP12
SP4
4
11
SP11
SP3
3
10
SP10
SP2
2
9
8
SP9
SP1
1
SP8
SP0
0
SPH
SPL
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
ISRAM end (See Table 3-1 on page 19)
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2.6
Instruction Execution Timing
This section describes the general access timing concepts for instruction execution. The
Atmel® AVR® CPU is driven by the CPU clock clkCPU, directly generated from the selected
clock source for the chip. No internal clock division is used.
Figure 2-4 shows the parallel instruction fetches and instruction executions enabled by the
Harvard architecture and the fast access Register File concept. This is the basic pipelining
concept to obtain up to 1 MIPS per MHz with the corresponding unique results for functions
per cost, functions per clocks, and functions per power-unit.
Figure 2-4. The Parallel Instruction Fetches and Instruction Executions
T1
T2
T3
T4
clkCPU
1st Instruction Fetch
1st Instruction Execute
2nd Instruction Fetch
2nd Instruction Execute
3rd Instruction Fetch
3rd Instruction Execute
4th Instruction Fetch
Figure 2-5 shows the internal timing concept for the Register File. In a single clock cycle an
ALU operation using two register operands is executed, and the result is stored back to the
destination register.
Figure 2-5. Single Cycle ALU Operation
T1
T2
T3
T4
clkCPU
Total Execution Time
Register Operands Fetch
ALU Operation Execute
Result Write Back
2.7
Reset and Interrupt Handling
The Atmel AVR provides several different interrupt sources. These interrupts and the separate
Reset Vector each have a separate Program Vector in the Program memory space. All inter-
rupts are assigned individual enable bits which must be written logic one together with the
Global Interrupt Enable bit in the Status Register in order to enable the interrupt.
The lowest addresses in the Program memory space are by default defined as the Reset and
Interrupt Vectors. The complete list of vectors is shown in Section 7. “Interrupts” on page 63.
The list also determines the priority levels of the different interrupts. The lower the address the
higher is the priority level. RESET has the highest priority, and next is INT0 – the External
Interrupt Request 0.
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2.7.1
Interrupt behavior
When an interrupt occurs, the Global Interrupt Enable I-bit is cleared and all interrupts are dis-
abled. The user software can write logic one to the I-bit to enable nested interrupts. All
enabled interrupts can then interrupt the current interrupt routine. The I-bit is automatically set
when a Return from Interrupt instruction – RETI – is executed.
There are basically two types of interrupts. The first type is triggered by an event that sets the
Interrupt Flag. For these interrupts, the Program Counter is vectored to the actual Interrupt
Vector in order to execute the interrupt handling routine, and hardware clears the correspond-
ing Interrupt Flag. Interrupt Flags can also be cleared by writing a logic one to the flag bit
position(s) to be cleared. If an interrupt condition occurs while the corresponding interrupt
enable bit is cleared, the Interrupt Flag will be set and remembered until the interrupt is
enabled, or the flag is cleared by software. Similarly, if one or more interrupt conditions occur
while the Global Interrupt Enable bit is cleared, the corresponding Interrupt Flag(s) will be set
and remembered until the Global Interrupt Enable bit is set, and will then be executed by order
of priority.
The second type of interrupts will trigger as long as the interrupt condition is present. These
interrupts do not necessarily have Interrupt Flags. If the interrupt condition disappears before
the interrupt is enabled, the interrupt will not be triggered.
When the Atmel® AVR® exits from an interrupt, it will always return to the main program and
execute one more instruction before any pending interrupt is served.
Note that the Status Register is not automatically stored when entering an interrupt routine,
nor restored when returning from an interrupt routine. This must be handled by software.
When using the CLI instruction to disable interrupts, the interrupts will be immediately dis-
abled. No interrupt will be executed after the CLI instruction, even if it occurs simultaneously
with the CLI instruction. The following example shows how this can be used to avoid interrupts
during the timed EEPROM write sequence.
Assembly Code Example
in
r16, SREG
; store SREG value
cli
; disable interrupts during timed sequence
sbi EECR, EEMPE ; start EEPROM write
sbi EECR, EEPE
out SREG, r16
; restore SREG value (I-bit)
C Code Example
char cSREG;
cSREG = SREG;/* store SREG value */
/* disable interrupts during timed sequence */
_CLI();
EECR |= (1<<EEMPE); /* start EEPROM write */
EECR |= (1<<EEPE);
SREG = cSREG; /* restore SREG value (I-bit) */
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When using the SEI instruction to enable interrupts, the instruction following SEI will be exe-
cuted before any pending interrupts, as shown in this example.
Assembly Code Example
sei
; set Global Interrupt Enable
sleep
; enter sleep, waiting for interrupt
; note: will enter sleep before any pending
; interrupt(s)
C Code Example
_SEI();
/* set Global Interrupt Enable */
_SLEEP(); /* enter sleep, waiting for interrupt */
/* note: will enter sleep before any pending interrupt(s) */
2.7.2
Interrupt Response Time
The interrupt execution response for all the enabled Atmel® AVR® interrupts is four clock
cycles minimum. After four clock cycles the Program Vector address for the actual interrupt
handling routine is executed. During this four clock cycle period, the Program Counter is
pushed onto the Stack. The vector is normally a jump to the interrupt routine, and this jump
takes three clock cycles. If an interrupt occurs during execution of a multi-cycle instruction, this
instruction is completed before the interrupt is served. If an interrupt occurs when the MCU is
in sleep mode, the interrupt execution response time is increased by four clock cycles. This
increase comes in addition to the start-up time from the selected sleep mode.
A return from an interrupt handling routine takes four clock cycles. During these four clock
cycles, the Program Counter (two bytes) is popped back from the Stack, the Stack Pointer is
incremented by two, and the I-bit in SREG is set.
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3. Atmel AVR Memories
This section describes the different memories in the Atmel® AVR®. The Atmel AVR architec-
ture has two main memory spaces, the Data memory and the Program memory space. In
addition, the Atmel AVR features an EEPROM Memory for data storage. All three memory
spaces are linear and regular.
Table 3-1.
Memory Mapping.
Memory
Mnemonic
Flash size
-
Atmel AVR
16 K bytes
0x0000
Size
Start Address
Flash
0x3FFF(1)
0x1FFF(2)
End Address
Flash end
Size
-
32 bytes
0x0000
0x001F
64 bytes
0x0020
0x005F
160 bytes
0x0060
0x00FF
512 bytes
0x0100
0x02FF
512 bytes
0x0000
0x01FF
32 Registers
Start Address
End Address
Size
-
-
-
I/O
Start Address
End Address
Size
-
Registers
-
-
Ext I/O
Start Address
End Address
Size
-
Registers
-
ISRAM size
ISRAM start
ISRAM end
E2 size
-
Internal
SRAM
Start Address
End Address
Size
EEPROM
Start Address
End Address
E2 end
Notes: 1. Byte address.
2. Word (16-bit) address.
3.1
In-System Re-programmable Flash Program Memory
The Atmel AVR contains On-chip In-System Reprogrammable Flash memory for program
storage (see “Flash size” in Table 3-1 on page 19). Since all Atmel AVR instructions are 16 or
32 bits wide, the Flash is organized as 16 bits wide. Atmel AVR does not have separate Boot
Loader and Application Program sections, and the SPM instruction can be executed from the
entire Flash. See SELFPRGEN description in Section 21.2.1 “Store Program Memory Control
and Status Register – SPMCSR” on page 230 for more details.
The Flash memory has an endurance of at least 10,000 write/erase cycles in automotive
range. The Atmel AVR Program Counter (PC) address the program memory locations. Sec-
tion 22. “Memory Programming” on page 236 contains a detailed description on Flash data
serial downloading using the SPI pins.
Constant tables can be allocated within the entire Program memory address space (see the
LPM – Load Program memory instruction description).
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Timing diagrams for instruction fetch and execution are presented in Section 2.6 “Instruction
Execution Timing” on page 16.
Figure 3-1. Program Memory Map
Program Memory
0x0000
Flash end
3.2
SRAM Data Memory
Figure 3-2 shows how the Atmel® AVR® SRAM Memory is organized.
The Atmel AVR is a complex microcontroller with more peripheral units than can be supported
within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the
Extended I/O space in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be
used.
The data memory locations address both the Register File, the I/O memory, Extended I/O
memory, and the internal data SRAM. The first 32 locations address the Register File, the next
64 location the standard I/O memory, then 160 locations of Extended I/O memory, and the
next locations address the internal data SRAM (see “ISRAM size” in Table 3-1 on page 19).
The five different addressing modes for the Data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address
given by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers and
the internal data SRAM in the Atmel AVR are all accessible through all these addressing
modes. The Register File is described in “General Purpose Register File” on page 14.
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Figure 3-2. Data Memory Map
Data Memory
0x0000 - 0x001F
0x0020 - 0x005F
0x0060 - 0x00FF
ISRAM start
32 Registers
64 I/O Registers
160 Ext I/O Reg.
Internal SRAM
(ISRAM size)
ISRAM end
3.2.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clkCPU cycles as described in Figure 3-3.
Figure 3-3. On-chip Data SRAM Access Cycles
T1
T2
T3
clkCPU
Address valid
Compute Address
Address
Data
WR
Data
RD
Memory Access Instruction
Next Instruction
3.3
EEPROM Data Memory
The Atmel® AVR® contains EEPROM memory (see “E2 size” in Table 3-1 on page 19). It is
organized as a separate data space, in which single bytes can be read and written. The
EEPROM has an endurance of at least 100,000 write/erase cycles in automotive range. The
access between the EEPROM and the CPU is described in the following, specifying the
EEPROM Address Registers, the EEPROM Data Register and the EEPROM Control
Register.
Section 22. “Memory Programming” on page 236 contains a detailed description on EEPROM
programming in SPI or Parallel Programming mode.
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3.3.1
EEPROM Read/Write Access
The EEPROM Access Registers are accessible in the I/O space.
The write access times for the EEPROM are given in Table 3-2. A self-timing function, how-
ever, lets the user software detect when the next byte can be written. If the user code contains
instructions that write the EEPROM, some precautions must be taken. In heavily filtered power
supplies, VCC is likely to rise or fall slowly on Power-up/down. This causes the device for some
period of time to run at a voltage lower than specified as minimum for the clock frequency
used. See “Preventing EEPROM Corruption” on page 24 for details on how to avoid problems
in these situations.
In order to prevent unintentional EEPROM writes, a specific write procedure must be followed.
Refer to “Atomic Byte Programming” on page 22 and “Split Byte Programming” on page 22 for
details on this.
When the EEPROM is read, the CPU is halted for four clock cycles before the next instruction
is executed. When the EEPROM is written, the CPU is halted for two clock cycles before the
next instruction is executed.
3.3.2
Atomic Byte Programming
Using Atomic Byte Programming is the simplest mode. When writing a byte to the EEPROM,
the user must write the address into the EEARL Register and data into EEDR Register. If the
EEPMn bits are zero, writing EEPE (within four cycles after EEMPE is written) will trigger the
erase/write operation. Both the erase and write cycle are done in one operation and the total
programming time is given in Table 1. The EEPE bit remains set until the erase and write
operations are completed. While the device is busy with programming, it is not possible to do
any other EEPROM operations.
3.3.3
Split Byte Programming
It is possible to split the erase and write cycle in two different operations. This may be useful if
the system requires short access time for some limited period of time (typically if the power
supply voltage falls). In order to take advantage of this method, it is required that the locations
to be written have been erased before the write operation. But since the erase and write oper-
ations are split, it is possible to do the erase operations when the system allows doing
time-critical operations (typically after Power-up).
3.3.4
3.3.5
Erase
Write
To erase a byte, the address must be written to EEAR. If the EEPMn bits are 0b01, writing the
EEPE (within four cycles after EEMPE is written) will trigger the erase operation only (pro-
gramming time is given in Table 1). The EEPE bit remains set until the erase operation
completes. While the device is busy programming, it is not possible to do any other EEPROM
operations.
To write a location, the user must write the address into EEAR and the data into EEDR. If the
EEPMn bits are 0b10, writing the EEPE (within four cycles after EEMPE is written) will trigger
the write operation only (programming time is given in Table 1). The EEPE bit remains set until
the write operation completes. If the location to be written has not been erased before write,
the data that is stored must be considered as lost. While the device is busy with programming,
it is not possible to do any other EEPROM operations.
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The calibrated Oscillator is used to time the EEPROM accesses. Make sure the Oscillator fre-
quency is within the requirements described in “OSCCAL – Oscillator Calibration Register” on
page 41.
The following code examples show one assembly and one C function for erase, write, or
atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by
disabling interrupts globally) so that no interrupts will occur during execution of these
functions.
Assembly Code Example
EEPROM_write:
; Wait for completion of previous write
sbic
rjmp
EECR,EEPE
EEPROM_write
; Set Programming mode
ldi
out
r16, (0<<EEPM1)|(0<<EEPM0)
EECR, r16
; Set up address (r18:r17) in address register
out
out
EEARH, r18
EEARL, r17
; Write data (r16) to data register
out EEDR, r16
; Write logical one to EEMPE
sbi EECR,EEMPE
; Start eeprom write by setting EEPE
sbi
ret
EECR,EEPE
C Code Example
void EEPROM_write(unsigned char ucAddress, unsigned char ucData)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set Programming mode */
EECR = (0<<EEPM1)|(0<<EEPM0);
/* Set up address and data registers */
EEAR = ucAddress;
EEDR = ucData;
/* Write logical one to EEMPE */
EECR |= (1<<EEMPE);
/* Start eeprom write by setting EEPE */
EECR |= (1<<EEPE);
}
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The next code examples show assembly and C functions for reading the EEPROM. The
examples assume that interrupts are controlled so that no interrupts will occur during execu-
tion of these functions.
Assembly Code Example
EEPROM_read:
; Wait for completion of previous write
sbic
rjmp
EECR,EEPE
EEPROM_read
; Set up address (r18:r17) in address register
out
out
EEARH, r18
EEARL, r17
; Start eeprom read by writing EERE
sbi EECR,EERE
; Read data from data register
in
r16,EEDR
ret
C Code Example
unsigned char EEPROM_read(unsigned char ucAddress)
{
/* Wait for completion of previous write */
while(EECR & (1<<EEPE))
;
/* Set up address register */
EEAR = ucAddress;
/* Start eeprom read by writing EERE */
EECR |= (1<<EERE);
/* Return data from data register */
return EEDR;
}
3.3.6
Preventing EEPROM Corruption
During periods of low VCC, the EEPROM data can be corrupted because the supply voltage is
too low for the CPU and the EEPROM to operate properly. These issues are the same as for
board level systems using EEPROM, and the same design solutions should be applied.
An EEPROM data corruption can be caused by two situations when the voltage is too low.
First, a regular write sequence to the EEPROM requires a minimum voltage to operate cor-
rectly. Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage is too
low.
EEPROM data corruption can easily be avoided by following this design recommendation:
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Keep the Atmel® AVR® RESET active (low) during periods of insufficient power supply volt-
age. This can be done by enabling the internal Brown-out Detector (BOD). If the detection
level of the internal BOD does not match the needed detection level, an external low VCC reset
protection circuit can be used. If a reset occurs while a write operation is in progress, the write
operation will be completed provided that the power supply voltage is sufficient.
3.4
I/O Memory
The I/O space definition of the Atmel AVR is shown in Section 26. “Register Summary” on
page 282.
All Atmel AVR I/Os and peripherals are placed in the I/O space. All I/O locations may be
accessed by the LD/LDS/LDD and ST/STS/STD instructions, transferring data between the 32
general purpose working registers and the I/O space. I/O Registers within the address range
0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these registers,
the value of single bits can be checked by using the SBIS and SBIC instructions. Refer to the
instruction set section for more details. When using the I/O specific commands IN and OUT,
the I/O addresses 0x00 - 0x3F must be used. When addressing I/O Registers as data space
using LD and ST instructions, 0x20 must be added to these addresses. The Atmel AVR is a
complex microcontroller with more peripheral units than can be supported within the 64 loca-
tion reserved in Opcode for the IN and OUT instructions. For the Extended I/O space from
0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD instructions can be used.
For compatibility with future devices, reserved bits should be written to zero if accessed.
Reserved I/O memory addresses should never be written.
Some of the Status Flags are cleared by writing a logical one to them. Note that, unlike most
other Atmel AVRs, the CBI and SBI instructions will only operate on the specified bit, and can
therefore be used on registers containing such Status Flags. The CBI and SBI instructions
work with registers 0x00 to 0x1F only.
The I/O and Peripherals Control Registers are explained in later sections.
3.4.1
General Purpose I/O Registers
The Atmel AVR contains three General Purpose I/O Registers. These registers can be used
for storing any information, and they are particularly useful for storing global variables and Sta-
tus Flags.
The General Purpose I/O Registers within the address range 0x00 - 0x1F are directly
bit-accessible using the SBI, CBI, SBIS, and SBIC instructions.
3.5
Register Description
3.5.1
EEARH and EEARL – EEPROM Address Register
Bit
7
6
5
4
3
2
1
0
EEAR8
EEAR0
0
-
-
-
-
-
-
-
EEARH
EEARL
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
Bit
7
R
6
R
5
R
4
R
3
R
2
R
1
R
Read/Write
Read/Write
Initial Value
Initial Value
R/W
R/W
X
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
X
X
X
X
X
X
X
X
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• Bit 7:1 – Reserved Bits
These bits are reserved for future use and will always read as 0 in Atmel® AVR®.
• Bits 8:0 – EEAR8:0: EEPROM Address
The EEPROM Address Registers – EEARH and EEARL – specifies the high EEPROM
address in the EEPROM space (see “E2 size” in Table 3-1 on page 19). The EEPROM data
bytes are addressed linearly between 0 and “E2 size”. The initial value of EEAR is undefined.
A proper value must be written before the EEPROM may be accessed.
Note:
For information only - ATtiny47: EEAR8 exists as register bit but it is not used for addressing.
3.5.2
EEDR – EEPROM Data Register
Bit
7
6
EEDR6
R/W
0
5
EEDR5
R/W
0
4
EEDR4
R/W
0
3
EEDR3
R/W
0
2
EEDR2
R/W
0
1
EEDR1
R/W
0
0
EEDR0
R/W
0
EEDR7
R/W
0
EEDR
Read/Write
Initial Value
• Bits 7:0 – EEDR7:0: EEPROM Data
For the EEPROM write operation the EEDR Register contains the data to be written to the
EEPROM in the address given by the EEAR Register. For the EEPROM read operation, the
EEDR contains the data read out from the EEPROM at the address given by EEAR.
3.5.3
EECR – EEPROM Control Register
Bit
7
6
–
5
EEPM1
R/W
X
4
EEPM0
R/W
X
3
EERIE
R/W
0
2
EEMPE
R/W
0
1
EEPE
R/W
X
0
EERE
R/W
0
–
R
0
EECR
Read/Write
Initial Value
R
0
• Bit 7,6 – Res: Reserved Bits
These bits are reserved for future use and will always read as 0 in the Atmel AVR. After read-
ing, mask out these bits. For compatibility with future Atmel AVR devices, always write these
bits to zero.
• Bits 5, 4 – EEPM1 and EEPM0: EEPROM Programming Mode Bits
The EEPROM Programming mode bits setting defines which programming action that will be
triggered when writing EEPE. It is possible to program data in one atomic operation (erase the
old value and program the new value) or to split the Erase and Write operations in two differ-
ent operations. The Programming times for the different modes are shown in Table 3-2. While
EEPE is set, any write to EEPMn will be ignored. During reset, the EEPMn bits will be reset to
0b00 unless the EEPROM is busy programming.
Table 3-2.
EEPROM Mode Bits
Typical
EEPM1
EEPM0 Programming Time Operation
0
0
1
1
0
1
0
1
3.4ms
1.8ms
1.8ms
–
Erase and Write in one operation (Atomic Operation)
Erase Only
Write Only
Reserved for future use
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• Bit 3 – EERIE: EEPROM Ready Interrupt Enable
Writing EERIE to one enables the EEPROM Ready Interrupt if the I-bit in SREG is set. Writing
EERIE to zero disables the interrupt. The EEPROM Ready Interrupt generates a constant
interrupt when Non-volatile memory is ready for programming.
• Bit 2 – EEMPE: EEPROM Master Program Enable
The EEMPE bit determines whether writing EEPE to one will have effect or not.
When EEMPE is set, setting EEPE within four clock cycles will program the EEPROM at the
selected address. If EEMPE is zero, setting EEPE will have no effect. When EEMPE has been
written to one by software, hardware clears the bit to zero after four clock cycles.
• Bit 1 – EEPE: EEPROM Program Enable
The EEPROM Program Enable Signal EEPE is the programming enable signal to the
EEPROM. When EEPE is written, the EEPROM will be programmed according to the EEPMn
bits setting. The EEMPE bit must be written to one before a logical one is written to EEPE, oth-
erwise no EEPROM write takes place. When the write access time has elapsed, the EEPE bit
is cleared by hardware. When EEPE has been set, the CPU is halted for two cycles before the
next instruction is executed.
• Bit 0 – EERE: EEPROM Read Enable
The EEPROM Read Enable Signal – EERE – is the read strobe to the EEPROM. When the
correct address is set up in the EEAR Register, the EERE bit must be written to one to trigger
the EEPROM read. The EEPROM read access takes one instruction, and the requested data
is available immediately. When the EEPROM is read, the CPU is halted for four cycles before
the next instruction is executed. The user should poll the EEPE bit before starting the read
operation. If a write operation is in progress, it is neither possible to read the EEPROM, nor to
change the EEAR Register.
3.5.4
3.5.5
3.5.6
General Purpose I/O Register 2 – GPIOR2
Bit
7
6
5
4
3
2
1
0
GPIOR27 GPIOR26 GPIOR25 GPIOR24 GPIOR23 GPIOR22 GPIOR21 GPIOR20
GPIOR2
GPIOR1
GPIOR0
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
General Purpose I/O Register 1 – GPIOR1
Bit
7
6
5
4
3
2
1
0
GPIOR17 GPIOR16 GPIOR15 GPIOR14 GPIOR13 GPIOR12 GPIOR11 GPIOR10
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
General Purpose I/O Register 0 – GPIOR0
Bit
7
6
5
4
3
2
1
0
GPIOR07 GPIOR06 GPIOR05 GPIOR04 GPIOR03 GPIOR02 GPIOR01 GPIOR00
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
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9219A–RFID–01/11
4. System Clock and Clock Options
The Atmel® AVR® provides a large number of clock sources. They can be divided into two cat-
egories: internal and external. Some external clock sources can be shared with the
asynchronous timer. After reset, the clock source is determined by the CKSEL Fuses. Once
the device is running, software clock switching is possible to any other clock sources.
Hardware controls are provided for clock switching management but some specific proce-
dures must be observed. Clock switching should be performed with caution as some settings
could result in the device having an incorrect configuration.
4.1
Clock Systems and their Distribution
Figure 4-1 presents the principal clock systems in the Atmel AVR and their distribution. All of
the clocks may not need to be active at any given time. In order to reduce power consumption,
the clocks to modules not being used can be halted by using different sleep modes or by using
features of the dynamic clock switch circuit (See “Power Management and Sleep Modes” on
page 46 and “Dynamic Clock Switch” on page 35). The clock systems are detailed below.
Figure 4-1. Clock Distribution
Asynchronous
Timer/Counter0
Flash and
EEPROM
General I/O
ADC
CPU Core
RAM
clkADC
clkI/O
clkCPU
AVR Clock
Control Unit
clkASY
clkFLASH
Reset Logic
Watchdog Timer
Source Clock
Watchdog Clock
Prescaler
Clock Switch
Multiplexer
Watchdog
Oscillator
Calibrated RC
Oscillator
CKOUT
Fuse
Low-frequency
Crystal Oscillator
Crystal
Oscillator
External Clock
PB4 / XTAL1 / CLKI
PB5 / XTAL2 / CLKO
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Atmel ATA5505 [Preliminary]
4.1.1
4.1.2
CPU Clock – clkCPU
The CPU clock is routed to parts of the system concerned with the Atmel® AVR® core opera-
tion. Examples of such modules are the General Purpose Register File, the Status Register
and the Data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from
performing general operations and calculations.
I/O Clock – clkI/O
The I/O clock is used by the majority of the I/O modules, like synchronous Timer/Counter. The
I/O clock is also used by the External Interrupt module, but note that some external interrupts
are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted.
4.1.3
4.1.4
Flash Clock – clkFLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active
simultaneously with the CPU clock.
Asynchronous Timer Clock – clkASY
The asynchronous timer clock allows the asynchronous Timer/Counter to be clocked directly
from an external clock or an external low frequency crystal. The dedicated clock domain
allows using this Timer/Counter as a real-time counter even when the device is in sleep mode.
4.1.5
ADC Clock – clkADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O
clocks in order to reduce noise generated by digital circuitry. This gives more accurate ADC
conversion results.
4.2
Clock Sources
The device has the following clock source options, selectable by Flash Fuse bits (default) or
by the CLKSELR register (dynamic clock switch circuit) as shown below. The clock from the
selected source is input to the Atmel AVR clock generator, and routed to the appropriate
modules.
Table 4-1.
Device Clocking Options Select(1) vs. PB4 and PB5 Functionality
CKSEL3..0 (2)
Device Clocking Option
CSEL3..0 (3)
0000 b
0010 b
0011 b
01xx b
PB4
CLKI
PB5
CLKO - I/O
CLKO - I/O
CLKO - I/O
XTAL2
External Clock
Calibrated Internal RC Oscillator 8.0 MHz
Watchdog Oscillator 128 kHz
I/O
I/O
External Low-frequency Oscillator
XTAL1
XTAL1
XTAL1
XTAL1
XTAL1
External Crystal/Ceramic Resonator (0.4 - 0.9MHz)
External Crystal/Ceramic Resonator (0.9 - 3.0MHz)
External Crystal/Ceramic Resonator (3.0 - 8.0MHz)
External Crystal/Ceramic Resonator (8.0 - 16.0MHz)
100x b
XTAL2
101x b
XTAL2
110x b
XTAL2
111x b
XTAL2
Notes: 1. For all fuses “1” means unprogrammed while “0” means programmed.
2. Flash Fuse bits.
3. CLKSELR register bits.
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The various choices for each clocking option are given in the following sections.
When the CPU wakes up from Power-down or Power-save, or when a new clock source is
enabled by the dynamic clock switch circuit, the selected clock source is used to time the
start-up, ensuring stable oscillator operation before instruction execution starts.
When the CPU starts from reset, there is an additional delay allowing the power to reach a sta-
ble level before commencing normal operation. The Watchdog Oscillator is used for timing this
real-time part of the start-up sequence. The number of WDT Oscillator cycles used for each
time-out is shown in Table 4-2.
Table 4-2.
Number of Watchdog Oscillator Cycles
Typ. Time-out (VCC = 5.0V)
Typ. Time-out (VCC = 5.0V)
Number of Cycles
512
4.1ms
65ms
4.3ms
69ms
8K (8,192)
4.2.1
Default Clock Source
At reset, the CKSEL and SUT fuse settings are copied into the CLKSELR register. The device
will then use the clock source and the start-up timings defined by the CLKSELR bits
(CSEL3..0 and CSUT1:0).
The device is shipped with CKSEL Fuses = 0010 b, SUT Fuses = 10 b, and CKDIV8 Fuse pro-
grammed. The default clock source setting is therefore the Internal RC Oscillator running at 8
MHz with the longest start-up time and an initial system clock divided by 8. This default setting
ensures that all users can make their desired clock source setting using an In-System or
High-voltage Programmer. This set-up must be taken into account when using ISP tools.
4.2.2
Calibrated Internal RC Oscillator
By default, the Internal RC Oscillator provides an approximate 8.0MHz clock. Though voltage
and temperature dependent, this clock can be accurately calibrated by the user. See Table
23-1 on page 257 and Section 25.7 “Internal Oscillator Speed” on page 279 for more details.
If selected, it can operate without external components. At reset, hardware loads the pre-pro-
grammed calibration value into the OSCCAL Register and thereby automatically configuring
the RC Oscillator. The accuracy of this calibration is shown as Factory calibration in Table
23-1 on page 257.
By adjusting the OSCCAL register in software, see “OSCCAL – Oscillator Calibration Regis-
ter” on page 41, it is possible to get a higher calibration accuracy than by using the factory
calibration. The accuracy of this calibration is shown as User calibration in Table 23-1 on page
257.
The Watchdog Oscillator will still be used for the Watchdog Timer and for the Reset Time-out
even when this Oscillator is used as the device clock. For more information on the pre-pro-
grammed calibration value, see the section “Calibration Byte” on page 239.
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Atmel ATA5505 [Preliminary]
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Atmel ATA5505 [Preliminary]
Table 4-3.
Internal Calibrated RC Oscillator Operating Modes(1)
CKSEL3..0(3)(4)
CSEL3..0(5)
Frequency Range(2) (MHz)
7.6 - 8.4
0010
Notes: 1. If 8 MHz frequency exceeds the specification of the device (depends on VCC), the CKDIV8
fuse can be programmed in order to divide the internal frequency by 8.
2. The frequency ranges are guideline values.
3. The device is shipped with this CKSEL = “0010”.
4. Flash Fuse bits.
5. CLKSELR register bits.
When this Oscillator is selected, start-up times are determined by the SUT Fuses or by CSUT
field as shown in Table 4-4.
Table 4-4.
Start-up Times for the Internal Calibrated RC Oscillator Clock Selection
SUT1..0(1)
Start-up Time from
Power-down/save
Additional Delay from
Reset (VCC = 5.0V)
CSUT1..0(2)
Recommended Usage
BOD enabled
00(3)
6CK
6CK
6CK
14CK
01
14CK + 4.1 ms
14CK + 65 ms
Reserved
Fast rising power
Slowly rising power
10(4)
11
Notes: 1. Flash Fuse bits
2. CLKSELR register bits
3. This setting is only available if RSTDISBL fuse is not set
4. The device is shipped with this option selected.
4.2.3
128 KHz Internal Oscillator
The 128KHz internal Oscillator is a low power Oscillator providing a clock of 128KHz. The fre-
quency is nominal at 3V and 25°C. This clock may be selected as the system clock by
programming CKSEL Fuses or CSEL field as shown in Table 4-1 on page 29.
When this clock source is selected, start-up times are determined by the SUT Fuses or by
CSUT field as shown in Table 4-5.
Table 4-5.
Start-up Times for the 128 kHz Internal Oscillator
SUT1..0(1)
Start-up Time from
Power-down/save
Additional Delay
from Reset (VCC = 5.0V)
CSUT1..0(2)
Recommended Usage
BOD enabled
00(3)
6CK
6CK
6CK
14CK
01
14CK + 4.1ms
14CK + 65ms
Reserved
Fast rising power
Slowly rising power
10
11
Notes: 1. Flash Fuse bits
2. CLKSELR register bits
3. This setting is only available if RSTDISBL fuse is not set
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4.2.4
Crystal Oscillator
XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which can be
configured for use as an On-chip Oscillator, as shown in Figure 4-2. Either a quartz crystal or
a ceramic resonator may be used.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the
capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and
the electromagnetic noise of the environment. Some initial guidelines for choosing capacitors
for use with crystals are given in Table 4-6. For ceramic resonators, the capacitor values given
by the manufacturer should be used.
Figure 4-2. Crystal Oscillator Connections
C2
XTAL2
C1
XTAL1
GND
The Oscillator can operate in three different modes, each optimized for a specific frequency
range. The operating mode is selected by CKSEL3..1 fuses or by CSEL3..1 field as shown in
Table 4-6.
Table 4-6.
Crystal Oscillator Operating Modes
CKSEL3..1(1)
Recommended Range for Capacitors
C1 and C2 for Use with Crystals (pF)
CSEL3..1(2)
100(3)
101
Frequency Range (MHz)
0.4 - 0.9
–
0.9 - 3.0
12 - 22
12 - 22
12 - 22
110
3.0 - 8.0
111
8.0 - 16.0
Notes: 1. Flash Fuse bits.
2. CLKSELR register bits.
3. This option should not be used with crystals, only with ceramic resonators.
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Atmel ATA5505 [Preliminary]
The CKSEL0 Fuse together with the SUT1..0 Fuses or CSEL0 together with CSUT1..0 field
select the start-up times as shown in Table 4-7.
Table 4-7.
Start-up Times for the Crystal Oscillator Clock Selection
Additional Delay
SUT1..0(1)
CSUT1..0(2)
CKSEL0(1)
CSEL0(2)
Start-up Time from
Power-down/save
from Reset
(VCC = 5.0V)
Recommended Usage
Ceramic resonator, fast
rising power
0
0
0
0
1
1
1
1
00
01
258CK(3)
14CK + 4.1ms
14CK + 65ms
14CK
Ceramic resonator, slowly
rising power
258CK(3)
Ceramic resonator, BOD
enabled
10(5)
11
1K (1024)CK(4)
1K (1024)CK(4)
1K (1024)CK(4)
16K (16384)CK
16K (16384)CK
16K (16384)CK
Ceramic resonator, fast
rising power
14CK + 4.1ms
14CK + 65ms
14CK
Ceramic resonator, slowly
rising power
00
Crystal Oscillator, BOD
enabled
01(5)
10
Crystal Oscillator, fast
rising power
14CK + 4.1ms
14CK + 65ms
Crystal Oscillator, slowly
rising power
11
Notes: 1. Flash Fuse bits.
2. CLKSELR register bits.
3. These options should only be used when not operating close to the maximum frequency of
the device, and only if frequency stability at start-up is not important for the application.
These options are not suitable for crystals.
4. These options are intended for use with ceramic resonators and will ensure frequency stabil-
ity at start-up. They can also be used with crystals when not operating close to the maximum
frequency of the device, and if frequency stability at start-up is not important for the
application.
5. This setting is only available if RSTDISBL fuse is not set.
4.2.5
Low-frequency Crystal Oscillator
To use a 32.768kHz watch crystal as the clock source for the device, the low-frequency crystal
oscillator must be selected by setting CKSEL fuses or CSEL field as shown in Table 4-1 on
page 29. The crystal should be connected as shown in Figure 4-3. Refer to the 32.768 kHz
Crystal Oscillator Application Note for details on oscillator operation and how to choose appro-
priate values for C1 and C2.
The 32.768kHz watch crystal oscillator can be used by the asynchronous timer if the (high-fre-
quency) Crystal Oscillator is not running or if the External Clock is not enabed (See
”Enable/Disable Clock Source” on page 36.). The asynchronous timer is then able to start
itself this low-frequency crystal oscillator.
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9219A–RFID–01/11
Figure 4-3. Low-frequency Crystal Oscillator Connections
C1=12-22 pF
XTAL2
32.768 KHz
XTAL1
C2=12-22 pF
GND
12-22 pF capacitors may be necessary if parasitic
impedance (pads, wires & PCB) is very low.
When this oscillator is selected, start-up times are determined by the SUT fuses or by CSUT
field as shown in Table 4-8.
Table 4-8.
Start-up Times for the Low Frequency Crystal Oscillator Clock Selection
SUT1..0(1)
Start-up Time from Additional Delay from
CSUT1..0(2)
Power-down/save
1K (1024)CK(3)
1K (1024)CK(3)
32K (32768)CK
Reset (VCC = 5.0V)
Recommended usage
00
01
10
11
4.1ms
Fast rising power or BOD enabled
Slowly rising power
65ms
65ms
Stable frequency at start-up
Reserved
Notes: 1. Flash Fuse bits.
2. CLKSELR register bits.
3. These options should only be used if frequency stability at start-up is not important for the
application.
4.2.6
External Clock
To drive the device from this external clock source, CLKI should be driven as shown in Figure
4-4. To run the device on an external clock, the CKSEL Fuses or CSEL field must be pro-
grammed as shown in Table 4-1 on page 29.
Figure 4-4. External Clock Drive Configuration
(XTAL2)
(CLKO)
~
External
Clock
Signal
CLKI
(XTAL1)
GND
When this clock source is selected, start-up times are determined by the SUT Fuses or CSUT
field as shown in Table 4-9.
This external clock can be used by the asynchronous timer if the high or low frequency Crystal
Oscillator is not running (See ”Enable/Disable Clock Source” on page 36.). The asynchronous
timer is then able to enable this input.
34
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Atmel ATA5505 [Preliminary]
Table 4-9.
Start-up Times for the External Clock Selection
SUT1..0(1)
CSUT1..0(2)
Start-up Time from
Power-down/save
Additional Delay from Reset
(VCC = 5.0V)
Recommended Usage
BOD enabled
00
01
10
11
6CK
6CK
6CK
14CK (+ 4.1ms(3)
14CK + 4.1ms
14CK + 65ms
Reserved
)
Fast rising power
Slowly rising power
Notes: 1. Flash Fuse bits.
2. CLKSELR register bits.
3. Additional delay (+ 4ms) available if RSTDISBL fuse is set.
Note that the System Clock Prescaler can be used to implement run-time changes of the inter-
nal clock frequency while still ensuring stable operation. Refer to “System Clock Prescaler” on
page 41 for details.
4.2.7
Clock Output Buffer
If not using a crystal oscillator, the device can output the system clock on the CLKO pin. To
enable the output, the CKOUT Fuse or COUT bit of CLKSELR register has to be programmed.
This option is useful when the device clock is needed to drive other circuits on the system.
Note that the clock will not be output during reset and the normal operation of I/O pin will be
overridden when the fuses are programmed. If the System Clock Prescaler is used, it is the
divided system clock that is output.
4.3
Dynamic Clock Switch
4.3.1
Features
The Atmel® AVR® provides a powerful dynamic clock switch circuit that allows users to turn on
and off clocks of the device on the fly. The built-in de-glitching circuitry allows clocks to be
enabled or disabled asynchronously. This enables efficient power management schemes to
be implemented easily and quickly. In a safety application, the dynamic clock switch circuit
allows continuous monitoring of the external clock permitting a fallback scheme in case of
clock failure.
The control of the dynamic clock switch circuit must be supervised by software. This operation
is facilitated by the following features:
• Safe commands, to avoid unintentional commands, a special write procedure must be
followed to change the CLKCSR register bits (See “CLKPR – Clock Prescaler Register” on
page 42.):
• Exclusive action, the actions are controlled by a decoding table (commands) written to the
CLKCSR register. This ensures that only one command operation can be launched at any
time. The main actions of the decoding table are:
– ‘Disable Clock Source’,
– ‘Enable Clock Source’,
– ‘Request Clock Availability’,
– ‘Clock Source Switching’,
35
9219A–RFID–01/11
– ‘Recover System Clock Source’,
– ‘Enable Watchdog in Automatic Reload Mode’.
• Command status return. The ‘Request Clock Availability ’ command returns status via the
CLKRDY bit in the CLKCSR register. The ‘Recover System Clock Source ’ command
returns a code of the current clock source in the CLKSELR register. This information is
used in the supervisory software routines as shown in Section 4.3.7 on page 37.
4.3.2
CLKSELR Register
4.3.2.1
Fuses Substitution
At reset, bits of the Low Fuse Byte are copied into the CLKSELR register. The content of this
register can subsequently be user modified to overwrite the default values from the Low Fuse
Byte. CKSEL3..0, SUT1..0 and CKOUT fuses correspond respectively to CSEL3..0, CSUT1:0
and ~(COUT) bits of the CLKSELR register as shown in Figure 4-5 on page 36.
4.3.2.2
Source Selection
The available codes of clock source are given in Table 4-1 on page 29.
Figure 4-5. Fuses substitution and Clock Source Selection
Fuse:
Register:
Fuse Low Byte
CLKSELR
SEL-0
SEL-1
SEL-2
CKSEL[3..0]
SEL-n
Reset
Selected
Configuration
SUT[1..0]
(
)
*
SCLKRq
CKOUT
EN-0
EN-1
EN-2
Clock
Switch
Current
Configuration
(
)
*
EN-n
SCLKRq : Command of Clock Control & Status Register
The CLKSELR register contains the CSEL, CSUT and COUT values which will be used by the
‘Enable/Disable Clock Source’, ‘Request for Clock Availability’ or ‘Clock Source Switching’
commands.
4.3.2.3
Source Recovering
The ‘Recover System Clock Source’ command updates the CKSEL field of CLKSELR register
(See “System Clock Source Recovering” on page 37.).
4.3.3
Enable/Disable Clock Source
The ‘Enable Clock Source’ command selects and enables a clock source configured by the
settings in the CLKSELR register. CSEL3..0 will select the clock source and CSUT1:0 will
select the start-up time (just as CKSEL and SUT fuse bits do). To be sure that a clock source
is operating, the ‘Request for Clock Availability ’ command must be executed after the ‘Enable
36
Atmel ATA5505 [Preliminary]
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Atmel ATA5505 [Preliminary]
Clock Source’ command. This will indicate via the CLKRDY bit in the CLKCSR register that a
valid clock source is available and operational.
The ‘Disable Clock Source’ command disables the clock source indicated by the settings of
CLKSELR register (only CSEL3..0). If the clock source indicated is currently the one that is
used to drive the system clock, the command is not executed.
Because the selected configuration is latched at clock source level, it is possible to enable
many clock sources at a given time (ex: the internal RC oscillator for system clock + an oscilla-
tor with external crystal). The user (code) is responsible of this management.
4.3.4
4.3.5
COUT Command
The ‘CKOUT ’ command allows to drive the CLKO pin. Refer to Section 4.2.7 “Clock Output
Buffer” on page 35 for using.
Clock Availability
‘Request for Clock Availability’ command enables a hardware oscillation cycle counter driven
by the selected source clock, CSEL3..0. The count limit value is determined by the settings of
CSUT1..0. The clock is declared ready (CLKRDY = 1) when the count limit value is reached.
The CLKRDY flag is reset when the count starts. Once set, this flag remains unchanged until a
new count is commanded. To perform this checking, the CKSEL and CSUT fields should not
be changed while the operation is running.
Note that once the new clock source is selected (‘Enable Clock Source’ command), the count
procedure is automatically started. The user (code) should wait for the setting of the CLKRDY
flag in CLKSCR register before using a newly selected clock.
At any time, the user (code) can ask for the availability of a clock source. The user (code) can
request it by writing the ‘Request for Clock Availability ’ command in the CLKSCR register. A
full polling of the status of clock sources can thus be done.
4.3.6
4.3.7
System Clock Source Recovering
The ‘Recover System Clock Source’ command returns the current clock source used to drive
the system clock as per Table 4-1 on page 29. The CKSEL field of CLKSELR register is then
updated with this returned value. There is no information on the SUT used or status on
CKOUT.
Clock Switching
To drive the system clock, the user can switch from the current clock source to any other of the
following ones (one of them being the current clock source):
1. Calibrated internal RC oscillator 8.0MHz,
2. Internal watchdog oscillator 128kHz,
3. External clock,
4. External low-frequency oscillator,
5. External Crystal/Ceramic Resonator.
The clock switching is performed by a sequence of commands. First, the user (code) must
make sure that the new clock source is operating. Then the ‘Clock Source Switching’ com-
mand can be issued. Once this command has been successfully completed using the
‘Recover System Clock Source’ command, the user (code) may stop the previous clock
source.
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9219A–RFID–01/11
It is strongly recommended to run this sequence only once the interrupts have been disabled.
The user (code) is responsible for the correct implementation of the clock switching sequence.
Here is a “light” C-code that describes such a sequence of commands.
C Code Example
void ClockSwiching (unsigned char clk_number, unsigned char sut) {
#define CLOCK_RECOVER 0x05
#define CLOCK_ENABLE
#define CLOCK_SWITCH
0x02
0x04
#define CLOCK_DISABLE 0x01
unsigned char previous_clk, temp;
// Disable interrupts
temp = SREG; asm ("cli");
// Save the current system clock source
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_RECOVER;
previous_clk = CLKSELR & 0x0F;
// Enable the new clock source
CLKSELR = ((sut << 4 ) & 0x30) | (clk_number & 0x0F);
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_ENABLE;
// Wait for clock validity
while ((CLKCSR & (1 << CLKRDY)) == 0);
// Switch clock source
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_SWITCH;
// Wait for effective switching
while (1){
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_RECOVER;
if ((CLKSELR & 0x0F) == (clk_number & 0x0F)) break;
}
// Shut down unneeded clock source
if (previous_clk != (clk_number & 0x0F)) {
CLKSELR = previous_clk;
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_DISABLE;
}
// Re-enable interrupts
SREG = temp;
}
Warning:
In the Atmel® AVR®, only one among the three external clock sources can be enabled at a
given time. Moreover, the enables of the external clock and of the external low-frequency
oscillator are shared with the asynchronous timer.
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Atmel ATA5505 [Preliminary]
4.3.8
Clock Monitoring
A safe system needs to monitor its clock sources. Two domains need to be monitored:
- Clock sources for peripherals,
- Clocks sources for system clock generation.
In the first domain, the user (code) can easily check the validity of the clock(s) (See “COUT
Command” on page 37.). In the second domain, the lack of a clock results in the code not run-
ning. Thus, the presence of the system clock needs to be monitored by hardware.
Using the on-chip watchdog allows this monitoring. Normally, the watchdog reloading is per-
formed only if the code reaches some specific software labels, reaching these labels proves
that the system clock is running. Otherwise the watchdog reset is enabled. This behavior can
be considered as a clock monitoring.
If the standard watchdog functionality is not desired, the Atmel® AVR® watchdog permits the
system clock to be monitored without having to resort to the complexity of a full software
watchdog handler. The solution proposed in the Atmel AVR is to automate the watchdog
reloading with only one command, at the beginning of the session.
So, to monitor the system clock, the user will have two options:
1. Using the standard watchdog features (software reload),
2. Or using the automatic reloading (hardware reload).
The two options are exclusive.
Note:
Warning:
These two options make sense ONLY if the clock source at RESET is an INTERNAL SOURCE.
The fuse settings determine this operation.
Figure 4-6. Watchdog Timer with Automatic Reloading.
WD
Interrupt
WatchDog Clock
WatchDog
WD
Reset
Reload
Automatic
Reloading
Mode
0
1
Enable
Register:
System CLK
Checker
WDTCSR
Internal Bus
The ‘Enable Watchdog in Automatic Reload Mode’ command has priority over the standard
watchdog enabling. In this mode, only the reset function of the watchdog is enabled (no more
watchdog interrupt). The WDP3..0 bits of the WDTCSR register always determine the watch-
dog timer prescaling.
As the watchdog will not be active before executing the ‘Enable Watchdog in Automatic
Reload Mode’ command, it is recommended to activate this command before switching to an
external clock source (See note on page 39).
Notes: 1. ONLY the reset (watchdog reset included) disables this function. The Watchdog System
Reset Flag (WDRF bit of MCUSR register) can be used to monitor the reset cause.
2. ONLY clock frequencies greater than or equal to (4 * WatchDog Clock Frequency) can be
monitored.
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Here is a “light” C-code of a clock switching function using automatic clock monitoring.
C Code Example
void ClockSwiching (unsigned char clk_number, unsigned char sut) {
#define CLOCK_RECOVER 0x05
#define CLOCK_ENABLE
#define CLOCK_SWITCH
0x02
0x04
#define CLOCK_DISABLE 0x01
#define WD_ARL_ENABLE 0x06
#define WD_2048CYCLES 0x07
unsigned char previous_clk, temp;
// Disable interrupts
temp = SREG; asm ("cli");
// Save the current system clock source
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_RECOVER;
previous_clk = CLKSELR & 0x0F;
// Enable the new clock source
CLKSELR = ((sut << 4 ) & 0x30) | (clk_number & 0x0F);
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_ENABLE;
// Wait for clock validity
while ((CLKCSR & (1 << CLKRDY)) == 0);
// Enable the watchdog in automatic reload mode
WDTCSR = (1 << WDCE) | (1 << WDE);
WDTCSR = (1 << WDE ) | WD_2048CYCLES;
CLKCSR = 1 << CLKCCE;
CLKCSR = WD_ARL_ENABLE;
// Switch clock source
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_SWITCH;
// Wait for effective switching
while (1){
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_RECOVER;
if ((CLKSELR & 0x0F) == (clk_number & 0x0F)) break;
}
// Shut down unneeded clock source
if (previous_clk != (clk_number & 0x0F)) {
CLKSELR = previous_clk;
CLKCSR = 1 << CLKCCE;
CLKCSR = CLOCK_DISABLE;
}
// Re-enable interrupts
SREG = temp;
}
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4.4
System Clock Prescaler
4.4.1
Features
The Atmel® AVR® system clock can be divided by setting the Clock Prescaler Register –
CLKPR. This feature can be used to decrease power consumption when the requirement for
processing power is low. This can be used with all clock source options, and it will affect the
clock frequency of the CPU and all synchronous peripherals. clkI/O, clkADC, clkCPU, and clkFLASH
are divided by a factor as shown in Table 4-10 on page 43.
4.4.2
Switching Time
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither
the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted.
From the time the CLKPS values are written, it takes between T1 + T2 and T1 + 2*T2 before
the new clock frequency is active. In this interval, 2 active clock edges are produced. Here, T1
is the previous clock period, and T2 is the period corresponding to the new prescaler setting.
4.5
Register Description
4.5.1
OSCCAL – Oscillator Calibration Register
Bit
7
6
5
4
3
2
1
0
CAL7
R/W
CAL6
R/W
CAL5
R/W
CAL4
R/W
CAL3
R/W
CAL2
R/W
CAL1
R/W
CAL0
R/W
OSCCAL
Read/Write
Initial Value
Device Specific Calibration Value
• Bits 7:0 – CAL7:0: Oscillator Calibration Value
The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to
remove process variations from the oscillator frequency. The factory-calibrated value is auto-
matically written to this register during chip reset, giving an oscillator frequency of 8.0 MHz at
25°C. The application software can write this register to change the oscillator frequency. The
oscillator can be calibrated to any frequency in the range 7.3 - 8.1MHz within ±2% accuracy.
Calibration outside that range is not guaranteed.
Note that this oscillator is used to time EEPROM and Flash write accesses, and these write
times will be affected accordingly. If the EEPROM or Flash are written, do not calibrate to
more than 8.8MHz. Otherwise, the EEPROM or Flash write may fail.
The CAL7 bit determines the range of operation for the oscillator. Setting this bit to 0 gives the
lowest frequency range, setting this bit to 1 gives the highest frequency range. The two fre-
quency ranges are overlapping, in other words a setting of OSCCAL = 0x7F gives a higher
frequency than OSCCAL = 0x80.
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The CAL6..0 bits are used to tune the frequency within the selected range. A setting of 0x00
gives the lowest frequency in that range, and a setting of 0x7F gives the highest frequency in
the range. Incrementing CAL6..0 by 1 will give a frequency increment of less than 2% in the
frequency range 7.3 - 8.1 MHz.
4.5.2
CLKPR – Clock Prescaler Register
Bit
7
6
–
5
–
4
–
3
2
1
0
CLKPCE
CLKPS3
R/W
CLKPS2
R/W
CLKPS1
R/W
CLKPS0
R/W
CLKPR
Read/Write
Initial Value
R/W
0
R
0
R
0
R
0
See Bit Description
• Bit 7 – CLKPCE: Clock Prescaler Change Enable
The CLKPCE bit must be written to logic one to enable change of the CLKPS bits. The CLK-
PCE bit is only updated when the other bits in CLKPR are simultaneously written to zero.
CLKPCE is cleared by hardware four cycles after it is written or when the CLKPS bits are writ-
ten. Rewriting the CLKPCE bit within this time-out period does neither extend the time-out
period, nor clear the CLKPCE bit.
• Bits 6:4 – Res: Reserved Bits
These bits are reserved bits in the Atmel® AVR® and will always read as zero.
• Bits 3:0 – CLKPS3:0: Clock Prescaler Select Bits 3 - 0
These bits define the division factor between the selected clock source and the internal sys-
tem clock. These bits can be written run-time to vary the clock frequency to suit the application
requirements. As the divider divides the master clock input to the MCU, the speed of all syn-
chronous peripherals is reduced when a division factor is used. The division factors are given
in Table 4-10.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
CLKPR to zero.
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting in order not to disturb the
procedure.
The CKDIV8 Fuse determines the initial value of the CLKPS bits. If CKDIV8 is unprogrammed,
the CLKPS bits will be reset to “0000”. If CKDIV8 is programmed, CLKPS bits are reset to
“0011”, giving a division factor of eight at start up. This feature should be used if the selected
clock source has a higher frequency than the maximum frequency of the device at the present
operating conditions. Note that any value can be written to the CLKPS bits regardless of the
CKDIV8 Fuse setting. The Application software must ensure that a sufficient division factor is
chosen if the selected clock source has a higher frequency than the maximum frequency of
the device at the present operating conditions. The device is shipped with the CKDIV8 Fuse
programmed.
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Table 4-10. Clock Prescaler Select
CLKPS3
CLKPS2
CLKPS1
CLKPS0
Clock Division Factor
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
1
2
4
8
16
32
64
128
256
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
4.5.3
CLKCSR – Clock Control & Status Register
Bit
7
CLKCCE
R/W
6
–
5
–
4
3
CLKC3
R/W
0
2
CLKC2
R/W
0
1
CLKC1
R/W
0
0
CLKC0
R/W
0
CLKRDY
CLKCSR
Read/Write
Initial Value
R
0
R
0
R
0
0
• Bit 7 – CLKCCE: Clock Control Change Enable
The CLKCCE bit must be written to logic one to enable change of the CLKCSR bits. The
CLKCCE bit is only updated when the other bits in CLKCSR are simultaneously written to
zero. CLKCCE is cleared by hardware four cycles after it is written or when the CLKCSR bits
are written. Rewriting the CLKCCE bit within this time-out period does neither extend the
time-out period, nor clear the CLKCCE bit.
• Bits 6:5 – Res: Reserved Bits
These bits are reserved bits in the Atmel® AVR® and will always read as zero.
• Bits 4 – CLKRDY: Clock Ready Flag
This flag is the output of the ‘Clock Availability ’ logic.
This flag is cleared by the ‘Request for Clock Availability’ command or ‘Enable Clock Source’
command being entered.
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It is set when ‘Clock Availability’ logic confirms that the (selected) clock is running and is sta-
ble. The delay from the request and the flag setting is not fixed, it depends on the clock
start-up time, the clock frequency and, of course, if the clock is alive. The user’s code has to
differentiate between ‘no_clock_signal’ and ‘clock_signal_not_yet_available’ condition.
• Bits 3:0 – CLKC3:0: Clock Control Bits 3 - 0
These bits define the command to provide to the ‘Clock Switch’ module. The special write pro-
cedure must be followed to change the CLKC3..0 bits (See ”Bit 7 – CLKCCE: Clock Control
Change Enable” on page 43.).
1. Write the Clock Control Change Enable (CLKCCE) bit to one and all other bits in
CLKCSR to zero.
2. Within 4 cycles, write the desired value to CLKCSR register while clearing CLKCCE
bit.
Interrupts should be disabled when setting CLKCSR register in order not to disturb the
procedure.
Table 4-11. Clock command list.
Clock Command
CLKC3..0
0000 b
0001 b
0010 b
0011 b
0100 b
0101 b
0110 b
0111 b
No command
Disable clock source
Enable clock source
Request for clock availability
Clock source switch
Recover system clock source code
Enable watchdog in automatic reload mode
CKOUT command
No command
1xxxb
4.5.4
CLKSELR - Clock Selection Register
Bit
7
6
5
4
3
2
1
0
-
COUT
R/W
CSUT1
R/W
CSUT0
R/W
CSEL3
R/W
CSEL2
R/W
CSEL1
R/W
CSEL0
R/W
CLKSELR
Read/Write
Initial Value
R
0
~ (CKOUT)
fuse
SUT1..0
fuses
CKSEL3..0
fuses
• Bit 7– Res: Reserved Bit
This bit is reserved bit in the Atmel® AVR® and will always read as zero.
• Bit 6 – COUT: Clock Out
The COUT bit is initialized with ~(CKOUT) Fuse bit.
The COUT bit is only used in case of ‘CKOUT’ command. Refer to Section 4.2.7 “Clock Output
Buffer” on page 35 for using.
In case of ‘Recover System Clock Source’ command, COUT it is not affected (no recovering of
this setting).
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• Bits 5:4 – CSUT1:0: Clock Start-up Time
CSUT bits are initialized with the values of SUT Fuse bits.
In case of ‘Enable/Disable Clock Source’ command, CSUT field provides the code of the clock
start-up time. Refer to subdivisions of Section 4.2 “Clock Sources” on page 29 for code of
clock start-up times.
In case of ‘Recover System Clock Source’ command, CSUT field is not affected (no recover-
ing of SUT code).
• Bits 3:0 – CSEL3:0: Clock Source Select
CSEL bits are initialized with the values of CKSEL Fuse bits.
In case of ‘Enable/Disable Clock Source’, ‘Request for Clock Availability’ or ‘Clock Source
Switch’ command, CSEL field provides the code of the clock source. Refer to Table 4-1 on
page 29 and subdivisions of Section 4.2 “Clock Sources” on page 29 for clock source codes.
In case of ‘Recover System Clock Source’ command, CSEL field contains the code of the
clock source used to drive the Clock Control Unit as described in Figure 4-1 on page 28.
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5. Power Management and Sleep Modes
Sleep modes enable the application to shut down unused modules in the MCU, thereby saving
power. The Atmel® AVR® provides various sleep modes allowing the user to tailor the power
consumption to the application’s requirements.
When enabled, the Brown-out Detector (BOD) actively monitors the power supply voltage dur-
ing the sleep periods. To further save power, it is possible to disable the BOD in some sleep
modes. See “BOD Disable” on page 47 for more details.
5.1
Sleep Modes
Figure 4-1 on page 28 presents the different clock systems in the Atmel AVR, and their distri-
bution. The figure is helpful in selecting an appropriate sleep mode. Table 5-1 shows the
different sleep modes, their wake up sources and BOD disable ability.
Table 5-1.
Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Active Clock Domains Oscillators Wake-up Sources
Sleep Mode
Idle
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
ADC Noise
Reduction
X(1)
Power-down
Power-Save
X(1)
X(1)
X
X
X
X
X
X
X
X
X
Note:
1. For INT1 and INT0, only level interrupt.
To enter any of the four sleep modes, the SE bit in SMCR must be written to logic one and a
SLEEP instruction must be executed. The SM1, and SM0 bits in the SMCR Register select
which sleep mode (Idle, ADC Noise Reduction, Power-down, or Power-save) will be activated
by the SLEEP instruction. See Table 5-2 on page 51 for a summary.
If an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU
is then halted for four cycles in addition to the start-up time, executes the interrupt routine, and
resumes execution from the instruction following SLEEP. The contents of the Register File
and SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep
mode, the MCU wakes up and executes from the Reset Vector.
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5.2
BOD Disable
When the Brown-out Detector (BOD) is enabled by BODLEVEL fuses, Table 22-3 on page
237, the BOD is actively monitoring the power supply voltage during a sleep period. To save
power, it is possible to disable the BOD by software for some of the sleep modes, see Table
5-1. The sleep mode power consumption will then be at the same level as when BOD is glob-
ally disabled by fuses. If BOD is disabled in software, the BOD function is turned off
immediately after entering the sleep mode. Upon wake-up from sleep, BOD is automatically
enabled again. This ensures safe operation in case the VCC level has dropped during the sleep
period.
When the BOD has been disabled, the wake-up time from sleep mode will be approximately
60 µs to ensure that the BOD is working correctly before the MCU continues executing code.
BOD disable is controlled by BODS bit (BOD Sleep) in the control register MCUCR, see
“MCUCR – MCU Control Register” on page 51. Setting it to one turns off the BOD in relevant
sleep modes, while a zero in this bit keeps BOD active. Default setting keeps BOD active, i.e.
BODS is cleared to zero.
Writing to the BODS bit is controlled by a timed sequence and an enable bit, see “MCUCR –
MCU Control Register” on page 51.
5.3
Idle Mode
When the SM1..0 bits are written to 00, the SLEEP instruction makes the MCU enter Idle
mode, stopping the CPU but allowing the SPI, Analog Comparator, ADC, USI start condition,
Asynchronous Timer/Counter, Watchdog, and the interrupt system to continue operating. This
sleep mode basically halts clkCPU and clkFLASH, while allowing the other clocks to run.
Idle mode enables the MCU to wake up from external triggered interrupts as well as internal
ones like the SPI interrupts. If wake-up from the Analog Comparator interrupt is not required,
the Analog Comparator can be powered down by setting the ACD bit in the Analog Compara-
tor Control and Status Register – ACSR. This will reduce power consumption in Idle mode. If
the ADC is enabled, a conversion starts automatically when this mode is entered.
5.4
ADC Noise Reduction Mode
When the SM1..0 bits are written to 01, the SLEEP instruction makes the MCU enter ADC
Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the
USI start condition, the asynchronous Timer/Counter and the Watchdog to continue operating
(if enabled). This sleep mode basically halts clkI/O, clkCPU, and clkFLASH, while allowing the
other clocks to run.
This improves the noise environment for the ADC, enabling higher resolution measurements.
If the ADC is enabled, a conversion starts automatically when this mode is entered. Apart from
the ADC Conversion Complete interrupt, only an External Reset, a Watchdog System Reset, a
Watchdog Interrupt, a Brown-out Reset, a USI start condition interrupt, an asynchronous
Timer/Counter interrupt, an SPM/EEPROM ready interrupt, an external level interrupt on INT0
or INT1 or a pin change interrupt can wake up the MCU from ADC Noise Reduction mode.
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5.5
Power-down Mode
When the SM1..0 bits are written to 10, the SLEEP instruction makes the MCU enter
Power-down mode. In this mode, the external Oscillator is stopped, while the external inter-
rupts, the USI start condition, and the Watchdog continue operating (if enabled). Only an
External Reset, a Watchdog System Reset, a Watchdog Interrupt, a Brown-out Reset, the USI
start condition interrupt, an external level interrupt on INT0 or INT1, or a pin change interrupt
can wake up the MCU. This sleep mode basically halts all generated clocks, allowing opera-
tion of asynchronous modules only.
Note that if a level triggered interrupt is used for wake-up from Power-down mode, the
changed level must be held for some time to wake up the MCU. Refer to Section 8. “External
Interrupts” on page 65 for details.
When waking up from Power-down mode, there is a delay from the wake-up condition occurs
until the wake-up becomes effective. This allows the clock to restart and become stable after
having been stopped. The wake-up period is defined by the same CKSEL Fuses that define
the Reset Time-out period, as described in Section 4.2 “Clock Sources” on page 29.
5.6
Power-save Mode
When the SM1..0 bits are written to 11, the SLEEP instruction makes the MCU enter
Power-save mode. This mode is identical to Power-down, with one exception:
If Timer/Counter0 is clocked asynchronously, i.e., the AS0 bit in ASSR is set, Timer/Counter0
will run during sleep. The device can wake up from either Timer Overflow or Output Compare
event from Timer/Counter0 if the corresponding Timer/Counter0 interrupt enable bits are set in
TIMSK0, and the global interrupt enable bit in SREG is set.
If the Asynchronous Timer is NOT clocked asynchronously, Power-down mode is recom-
mended instead of Power-save mode because the contents of the registers in the
asynchronous timer should be considered undefined after wake-up in Power-save mode if
AS0 is 0.
This sleep mode basically halts all clocks except clkASY, allowing operation only of asynchro-
nous modules, including Timer/Counter0 if clocked asynchronously.
5.7
Power Reduction Register
The Power Reduction Register (PRR), see “PRR – Power Reduction Register” on page 51,
provides a method to stop the clock to individual peripherals to reduce power consumption.
The current state of the peripheral is frozen and the I/O registers can not be read or written.
Resources used by the peripheral when stopping the clock will remain occupied, hence the
peripheral should in most cases be disabled before stopping the clock. Waking up a module,
which is done by clearing the bit in PRR, puts the module in the same state as before
shutdown.
Module shutdown can be used in Idle mode and Active mode to significantly reduce the overall
power consumption. In all other sleep modes, the clock is already stopped.
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5.8
Minimizing Power Consumption
There are several possibilities to consider when trying to minimize the power consumption in
an Atmel® AVR® controlled system. In general, sleep modes should be used as much as pos-
sible, and the sleep mode should be selected so that as few as possible of the device’s
functions are operating. All functions not needed should be disabled. In particular, the follow-
ing modules may need special consideration when trying to achieve the lowest possible power
consumption.
5.8.1
5.8.2
Analog to Digital Converter
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-
abled before entering any sleep mode. When the ADC is turned off and on again, the next
conversion will be an extended conversion. Refer to Section 18. “ADC – Analog to Digital Con-
verter” on page 202 for details on ADC operation.
Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When enter-
ing ADC Noise Reduction mode, the Analog Comparator should be disabled. In other sleep
modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator
is set up to use the Internal Voltage Reference as input, the Analog Comparator should be dis-
abled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled,
independent of sleep mode. Refer to Section 19. “AnaComp - Analog Comparator” on page
222 for details on how to configure the Analog Comparator.
5.8.3
5.8.4
Brown-out Detector
If the Brown-out Detector is not needed by the application, this module should be turned off. If
the Brown-out Detector is enabled by the BODLEVEL Fuses, it will be enabled in all sleep
modes, and hence, always consume power. In the deeper sleep modes, this will contribute
significantly to the total current consumption. Refer to Section 6.1.5 “Brown-out Detection” on
page 55 for details on how to configure the Brown-out Detector.
Internal Voltage Reference
The Internal Voltage Reference will be enabled when needed by the Brown-out Detection, the
Analog Comparator or the ADC. If these modules are disabled as described in the sections
above, the internal voltage reference will be disabled and it will not be consuming power.
When turned on again, the user must allow the reference to start up before the output is used.
If the reference is kept on in sleep mode, the output can be used immediately. Refer to Section
6.2 “Internal Voltage Reference” on page 57 for details on the start-up time.
Output the internal voltage reference is not needed in the deeper sleep modes. This module
should be turned off to reduce significantly to the total current consumption. Refer to “AMISCR
– Analog Miscellaneous Control Register” on page 201 for details on how to disable the inter-
nal voltage reference output.
5.8.5
Internal Current Source
The Internal Current Source is not needed in the deeper sleep modes. This module should be
turned off to reduce significantly to the total current consumption. Refer to “AMISCR – Analog
Miscellaneous Control Register” on page 201 for details on how to disable the Internal Current
Source.
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5.8.6
5.8.7
Watchdog Timer
If the Watchdog Timer is not needed in the application, the module should be turned off. If the
Watchdog Timer is enabled, it will be enabled in all sleep modes and hence always consume
power. In the deeper sleep modes, this will contribute significantly to the total current con-
sumption. Refer to Section 6.3 “Watchdog Timer” on page 57 for details on how to configure
the Watchdog Timer.
Port Pins
When entering a sleep mode, all port pins should be configured to use minimum power. The
most important is then to ensure that no pins drive resistive loads. In sleep modes where both
the I/O clock (clkI/O) and the ADC clock (clkADC) are stopped, the input buffers of the device will
be disabled. This ensures that no power is consumed by the input logic when not needed. In
some cases, the input logic is needed for detecting wake-up conditions, and it will then be
enabled. Refer to the section Section 9.2.6 “Digital Input Enable and Sleep Modes” on page
75 for details on which pins are enabled. If the input buffer is enabled and the input signal is
left floating or have an analog signal level close to VCC/2, the input buffer will use excessive
power.
For analog input pins, the digital input buffer should be disabled at all times. An analog signal
level close to VCC/2 on an input pin can cause significant current even in active mode. Digital
input buffers can be disabled by writing to the Digital Input Disable Registers (DIDR1 and
DIDR0). Refer to Section 18.11.6 “DIDR1 – Digital Input Disable Register 1” on page 221 and
Section 18.11.5 “DIDR0 – Digital Input Disable Register 0” on page 220 for details.
5.8.8
On-chip Debug System
If the On-chip debug system is enabled by the DWEN Fuse and the chip enters sleep mode,
the main clock source is enabled and hence always consumes power. In the deeper sleep
modes, this will contribute significantly to the total current consumption.
5.9
Register Description
5.9.1
SMCR – Sleep Mode Control Register
The Sleep Mode Control Register contains control bits for power management.
Bit
7
–
6
–
5
–
4
–
3
–
2
1
0
SE
R/W
0
SM1
R/W
0
SM0
R/W
0
SMCR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
• Bits 7..3 Res: Reserved Bits
These bits are unused bits in the Atmel® AVR®, and will always read as zero.
• Bits 2..1 – SM1..0: Sleep Mode Select Bits 1, and 0
These bits select between the four available sleep modes as shown in Table 5-2.
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Atmel ATA5505 [Preliminary]
Table 5-2.
Sleep Mode Select
SM1
SM0
Sleep Mode
Idle
0
0
1
1
0
1
0
1
ADC Noise Reduction
Power-down
Power-save
• Bit 0 – SE: Sleep Enable
The SE bit must be written to logic one to make the MCU enter the sleep mode when the
SLEEP instruction is executed. To avoid the MCU entering the sleep mode unless it is the pro-
grammer’s purpose, it is recommended to write the Sleep Enable (SE) bit to one just before
the execution of the SLEEP instruction and to clear it immediately after waking up.
5.9.2
MCUCR – MCU Control Register
Bit
7
6
BODS
R/W
0
5
BODSE
R/W
0
4
3
–
2
–
1
–
0
–
–
R
0
PUD
R/W
0
MCUCR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
• Bit 6 – BODS: BOD Sleep
The BODS bit must be written to logic one in order to turn off BOD during sleep, see Table 5-1
on page 46. Writing to the BODS bit is controlled by a timed sequence and an enable bit,
BODSE in MCUCR. To disable BOD in relevant sleep modes, both BODS and BODSE must
first be set to one. Then, to set the BODS bit, BODS must be set to one and BODSE must be
set to zero within four clock cycles.
The BODS bit is active three clock cycles after it is set. A sleep instruction must be executed
while BODS is active in order to turn off the BOD for the actual sleep mode. The BODS bit is
automatically cleared after three clock cycles.
• Bit 5 – BODSE: BOD Sleep Enable
BODSE enables setting of BODS control bit, as explained in BODS bit description. BOD dis-
able is controlled by a timed sequence.
5.9.3
PRR – Power Reduction Register
Bit
7
6
–
5
PRLIN
R/W
0
4
PRSPI
R/W
0
3
PRTIM1
R/W
0
2
PRTIM0
R/W
0
1
PRUSI
R/W
0
0
PRADC
R/W
0
–
R
0
PRR
Read/Write
Initial Value
R
0
• Bit 7 - Res: Reserved bit
This bit is reserved in Atmel® AVR® and will always read as zero.
• Bit 6 - Res: Reserved bit
This bit is reserved in Atmel AVR and will always read as zero.
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• Bit5 - PRLIN: Power Reduction LIN / UART controller
Writing a logic one to this bit shuts down the LIN by stopping the clock to the module. When
waking up the LIN again, the LIN should be re initialized to ensure proper operation.
• Bit 4 - PRSPI: Power Reduction Serial Peripheral Interface
If using debugWIRE On-chip Debug System, this bit should not be written to one.
Writing a logic one to this bit shuts down the Serial Peripheral Interface by stopping the clock
to the module. When waking up the SPI again, the SPI should be re initialized to ensure
proper operation.
• Bit 3 - PRTIM1: Power Reduction Timer/Counter1
Writing a logic one to this bit shuts down the Timer/Counter1 module. When the
Timer/Counter1 is enabled, operation will continue like before the shutdown.
• Bit 2 - PRTIM0: Power Reduction Timer/Counter0
Writing a logic one to this bit shuts down the Timer/Counter0 module in synchronous mode
(AS0 is 0). When the Timer/Counter0 is enabled, operation will continue like before the
shutdown.
• Bit 1 - PRUSI: Power Reduction USI
Writing a logic one to this bit shuts down the USI by stopping the clock to the module. When
waking up the USI again, the USI should be re-initialized to ensure proper operation.
• Bit 0 - PRADC: Power Reduction ADC
Writing a logic one to this bit shuts down the ADC. The ADC must be disabled before shut
down. The analog comparator cannot use the ADC input MUX when the ADC is shut down.
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Atmel ATA5505 [Preliminary]
6. System Control and Reset
6.1
Reset
6.1.1
Resetting the Atmel AVR
During reset, all I/O Registers are set to their initial values, and the program starts execution
from the Reset Vector. The instruction placed at the Reset Vector must be an RJMP – Relative
Jump – instruction to the reset handling routine. If the program never enables an interrupt
source, the Interrupt Vectors are not used, and regular program code can be placed at these
locations. The circuit diagram in Figure 6-1 shows the reset circuit. Tables in Section 23.5
“RESET Characteristics” on page 258 defines the electrical parameters of the reset circuitry.
The I/O ports of the Atmel® AVR® are immediately reset to their initial state when a reset
source goes active. This does not require any clock source to be running.
After all reset sources have gone inactive, a delay counter is invoked, stretching the internal
reset. This allows the power to reach a stable level before normal operation starts. The
time-out period of the delay counter is defined by the user through the SUT and CKSEL
Fuses. The different selections for the delay period are presented in Section 4.2 “Clock
Sources” on page 29.
6.1.2
Reset Sources
The Atmel AVR has four sources of reset:
• Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset
threshold (VPOT).
• External Reset. The MCU is reset when a low level is present on the RESET pin for longer
than the minimum pulse length.
• Watchdog System Reset. The MCU is reset when the Watchdog Timer period expires and
the Watchdog System Reset mode is enabled.
• Brown-out Reset. The MCU is reset when the supply voltage VCC is below the Brown-out
Reset threshold (VBOT) and the Brown-out Detector is enabled.
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Figure 6-1. Reset Circuit
DATA BUS
MCU Status
Register (MCUSR)
Power-on Reset
Circuit
Brown-out
Reset Circuit
BODLEVEL [2..0]
Pull-up Resistor
RSTDISBL
Spike
Filter
Watchdog
Oscillator
Delay Counters
Clock
Generator
CK
TIMEOUT
CKSEL[3:0]
SUT[1:0]
6.1.3
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection
level is defined in Table 23-4 on page 258. The POR is activated whenever VCC is below the
detection level. The POR circuit can be used to trigger the start-up Reset, as well as to detect
a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after VCC rise. The RESET signal is activated again, without any
delay, when VCC decreases below the detection level.
Figure 6-2. MCU Start-up, RESET Tied to VCC
VCCRR
VPORMAX
VPOT
VCC
VPORMIN
tTOUT
TIME-OUT
INTERNAL
RESET
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Atmel ATA5505 [Preliminary]
Figure 6-3. MCU Start-up, RESET Extended Externally
VCCRR
VCC
VPOR
RESET
VRST
tTOUT
TIME-OUT
INTERNAL
RESET
6.1.4
External Reset
An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the
minimum pulse width (see Table 23-3 on page 258) will generate a reset, even if the clock is
not running. Shorter pulses are not guaranteed to generate a reset. When the applied signal
reaches the Reset Threshold Voltage – VRST – on its positive edge, the delay counter starts
the MCU after the Time-out period – tTOUT – has expired. The External Reset can be disabled
by the RSTDISBL fuse, see Table 22-4 on page 237.
Figure 6-4. External Reset During Operation
CC
6.1.5
Brown-out Detection
Atmel® AVR® has an On-chip Brown-out Detection (BOD) circuit for monitoring the VCC level
during operation by comparing it to a fixed trigger level. The trigger level for the BOD can be
selected by the BODLEVEL Fuses (See ”BODLEVEL Fuse Coding” on page 259.). The trigger
level has a hysteresis to ensure spike free Brown-out Detection. The hysteresis on the detec-
tion level should be interpreted as VBOT = VBOT + VHYST / 2 and VBOT = VBOT - VHYST / 2.
+
–
When the BOD is enabled, and VCC decreases to a value below the trigger level (VBOT– in Fig-
ure 6-5), the Brown-out Reset is immediately activated. When VCC increases above the trigger
level (VBOT in Figure 6-5), the delay counter starts the MCU after the Time-out period tTOUT
+
has expired.
The BOD circuit will only detect a drop in VCC if the voltage stays below the trigger level for lon-
ger than tBOD given in Table 23-6 on page 259.
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Figure 6-5. Brown-out Reset During Operation
VBOT+
VCC
VBOT-
RESET
t
TOUT
TIME-OUT
INTERNAL
RESET
6.1.6
Watchdog System Reset
When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration.
On the falling edge of this pulse, the delay timer starts counting the Time-out period tTOUT
Refer to page 57 for details on operation of the Watchdog Timer.
.
Figure 6-6. Watchdog System Reset During Operation
CC
CK
6.1.7
MCU Status Register – MCUSR
The MCU Status Register provides information on which reset source caused an MCU reset.
Bit
7
–
6
–
5
–
4
–
3
2
1
0
WDRF
R/W
BORF
R/W
EXTRF
R/W
PORF
R/W
MCUSR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
See Bit Description
• Bit 7..4 – Res: Reserved Bits
These bits are unused bits in the Atmel® AVR®, and will always read as zero.
• Bit 3 – WDRF: Watchdog System Reset Flag
This bit is set if a Watchdog System Reset occurs. The bit is reset by a Power-on Reset, or by
writing a logic zero to the flag.
• Bit 2 – BORF: Brown-out Reset Flag
This bit is set if a Brown-out Reset occurs. The bit is reset by a Power-on Reset, or by writing
a logic zero to the flag.
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Atmel ATA5505 [Preliminary]
• Bit 1 – EXTRF: External Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
• Bit 0 – PORF: Power-on Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the
flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then
Reset the MCUSR as early as possible in the program. If the register is cleared before another
reset occurs, the source of the reset can be found by examining the Reset Flags.
6.2
Internal Voltage Reference
The Atmel® AVR® features an internal bandgap reference. This reference is used for
Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC.
6.2.1
Voltage Reference Enable Signals and Start-up Time
The voltage reference has a start-up time that may influence the way it should be used. The
start-up time is given in Table 23-7 on page 259. To save power, the reference is not always
turned on. The reference is on during the following situations:
1. When the BOD is enabled (by programming the BODLEVEL [2:0] Fuses).
2. When the bandgap reference is connected to the Analog Comparator (by setting the
ACIRS bit in ACSR).
3. When the ADC is enabled.
Thus, when the BOD is not enabled, after setting the ACIRS bit or enabling the ADC, the user
must always allow the reference to start up before the output from the Analog Comparator or
ADC is used. To reduce power consumption in Power-down mode or in Power-save, the user
can avoid the three conditions above to ensure that the reference is turned off before entering
in these power reduction modes.
6.3
Watchdog Timer
The Atmel AVR has an Enhanced Watchdog Timer (WDT). The main features are:
• Clocked from separate On-chip Oscillator
• 4 Operating modes
– Interrupt
– System Reset
– Interrupt and System Reset
– Clock Monitoring
• Selectable Time-out period from 16ms to 8s
• Possible Hardware fuse Watchdog always on (WDTON) for fail-safe mode
6.3.1
Watchdog Timer Behavior
The Watchdog Timer (WDT) is a timer counting cycles of a separate on-chip 128 KHz
oscillator.
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Figure 6-7. Watchdog Timer
WATCHDOG
PRESCALER
~128 KHz
OSCILLATOR
WATCHDOG
RESET
WDP0
WDP1
WDP2
WDP3
CLOCK
MONITORING
MCU
RESET
WDE
WDIF
WDIE
INTERRUPT
The WDT gives an interrupt or a system reset when the counter reaches a given time-out
value. In normal operation mode, it is required that the system uses the WDR - Watchdog
Timer Reset - instruction to restart the counter before the time-out value is reached. If the sys-
tem doesn't restart the counter, an interrupt or system reset will be issued.
In Interrupt mode, the WDT gives an interrupt when the timer expires. This interrupt can be
used to wake the device from sleep-modes, and also as a general system timer. One example
is to limit the maximum time allowed for certain operations, giving an interrupt when the opera-
tion has run longer than expected. In System Reset mode, the WDT gives a reset when the
timer expires. This is typically used to prevent system hang-up in case of runaway code. The
third mode, Interrupt and System Reset mode, combines the other two modes by first giving
an interrupt and then switch to System Reset mode. This mode will for instance allow a safe
shutdown by saving critical parameters before a system reset.
The Watchdog always on (WDTON) fuse, if programmed, will force the Watchdog Timer to
System Reset mode. With the fuse programmed the System Reset mode bit (WDE) and Inter-
rupt mode bit (WDIE) are locked to 1 and 0 respectively. To further ensure program security,
alterations to the Watchdog set-up must follow timed sequences. The sequence for clearing
WDE and changing time-out configuration is as follows:
1. In the same operation, write a logic one to the Watchdog change enable bit (WDCE)
and WDE. A logic one must be written to WDE regardless of the previous value of the
WDE bit.
2. Within the next four clock cycles, write the WDE and Watchdog prescaler bits (WDP)
as desired, but with the WDCE bit cleared. This must be done in one operation.
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Atmel ATA5505 [Preliminary]
The following code example shows one assembly and one C function for turning off the
Watchdog Timer. The example assumes that interrupts are controlled (e.g. by disabling inter-
rupts globally) so that no interrupts will occur during the execution of these functions.
Assembly Code Example(1)
WDT_off:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Clear WDRF in MCUSR
in
andi r16, (0xff & (0<<WDRF))
out MCUSR, r16
r16, MCUSR
; Write logical one to WDCE and WDE
; Keep old prescaler setting to prevent unintentional time-out
lds r16, WDTCR
ori
r16, (1<<WDCE) | (1<<WDE)
sts WDTCR, r16
; Turn off WDT
ldi
r16, (0<<WDE)
sts WDTCR, r16
; Turn on global interrupt
sei
ret
C Code Example(1)
void WDT_off(void)
{
__disable_interrupt();
__watchdog_reset();
/* Clear WDRF in MCUSR */
MCUSR &= ~(1<<WDRF);
/* Write logical one to WDCE and WDE */
/* Keep old prescaler setting to prevent unintentional time-out */
WDTCR |= (1<<WDCE) | (1<<WDE);
/* Turn off WDT */
WDTCR = 0x00;
__enable_interrupt();
}
Note:
1. See Section 1.7 “About Code Examples ” on page 10
Note that if the Watchdog is accidentally enabled, for example by a runaway pointer or
brown-out condition, the device will be reset and the Watchdog Timer will stay enabled. If the
code is not set up to handle the Watchdog, this might lead to an eternal loop of time-out
resets. To avoid this situation, the application software should always clear the Watchdog Sys-
tem Reset Flag (WDRF) and the WDE control bit in the initialization routine, even if the
Watchdog is not in use.
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The following code example shows one assembly and one C function for changing the
time-out value of the Watchdog Timer.
Assembly Code Example(1)
WDT_Prescaler_Change:
; Turn off global interrupt
cli
; Reset Watchdog Timer
wdr
; Start timed sequence
lds r16, WDTCR
ori
r16, (1<<WDCE) | (1<<WDE)
sts WDTCR, r16
; -- Got four cycles to set the new values from here -
; Set new prescaler(time-out) value = 64K cycles (~0.5 s)
ldi
r16, (1<<WDE) | (1<<WDP2) | (1<<WDP0)
sts WDTCR, r16
; -- Finished setting new values, used 2 cycles -
; Turn on global interrupt
sei
ret
C Code Example(1)
void WDT_Prescaler_Change(void)
{
__disable_interrupt();
__watchdog_reset();
/* Start timed sequence */
WDTCR |= (1<<WDCE) | (1<<WDE);
/* Set new prescaler(time-out) value = 64K cycles (~0.5 s) */
WDTCR = (1<<WDE) | (1<<WDP2) | (1<<WDP0);
__enable_interrupt();
}
Notes: 1. See Section 1.7 “About Code Examples ” on page 10
2. The Watchdog Timer should be reset before any change of the WDP bits, since a change in
the WDP bits can result in a time-out when switching to a shorter time-out period.
6.3.2
Clock monitoring
The Watchdog Timer can be used to detect a loss of system clock. This configuration is driven
by the dynamic clock switch circuit. Please refer to Section 4.3.8 “Clock Monitoring” on page
39 for more information.
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Atmel ATA5505 [Preliminary]
6.3.3
Watchdog Timer Control Register - WDTCR
Bit
7
WDIF
R/W
0
6
WDIE
R/W
0
5
WDP3
R/W
0
4
WDCE
R/W
0
3
WDE
R/W
X
2
WDP2
R/W
0
1
WDP1
R/W
0
0
WDP0
R/W
0
WDTCR
Read/Write
Initial Value
• Bit 7 - WDIF: Watchdog Interrupt Flag
This bit is set when a time-out occurs in the Watchdog Timer and the Watchdog Timer is con-
figured for interrupt. WDIF is cleared by hardware when executing the corresponding interrupt
handling vector. Alternatively, WDIF is cleared by writing a logic one to the flag. When the I-bit
in SREG and WDIE are set, the Watchdog Time-out Interrupt is executed.
• Bit 6 - WDIE: Watchdog Interrupt Enable
When this bit is written to one and the I-bit in the Status Register is set, the Watchdog Interrupt
is enabled. If WDE is cleared in combination with this setting, the Watchdog Timer is in Inter-
rupt Mode, and the corresponding interrupt is executed if time-out in the Watchdog Timer
occurs.
If WDE is set, the Watchdog Timer is in Interrupt and System Reset Mode. The first time-out in
the Watchdog Timer will set WDIF. Executing the corresponding interrupt vector will clear
WDIE and WDIF automatically by hardware (the Watchdog goes to System Reset Mode). This
is useful for keeping the Watchdog Timer security while using the interrupt. To stay in Interrupt
and System Reset Mode, WDIE must be set after each interrupt. This should however not be
done within the interrupt service routine itself, as this might compromise the safety-function of
the Watchdog System Reset mode. If the interrupt is not executed before the next time-out, a
System Reset will be applied.
If the Watchdog Timer is used as clock monitor (c.f. Section • “Bits 3:0 – CLKC3:0: Clock Con-
trol Bits 3 - 0” on page 44), the System Reset Mode is enabled and the Interrupt Mode is
automatically disabled.
Table 6-1.
Watchdog Timer Configuration
Clock
Monitor
WDTON WDE WDIE Mode
Action on Time-out
None
x
0
y(1)
0
0
y(1)
0
0
y(1)
1
Stopped
On
System Reset Mode
Interrupt Mode
System Reset Mode
Reset
Interrupt
Reset
0
1
0
Off
Interrupt and System Reset
Mode
Interrupt, then go to System
Reset Mode
0
1
1
x
1
x
System Reset Mode
Reset
Note:
1. At least one of these three enables (WDTON, WDE & WDIE) equal to 1.
• Bit 4 - WDCE: Watchdog Change Enable
This bit is used in timed sequences for changing WDE and prescaler bits. To clear the WDE
bit, and/or change the prescaler bits, WDCE must be set.
Once written to one, hardware will clear WDCE after four clock cycles.
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• Bit 3 - WDE: Watchdog System Reset Enable
WDE is overridden by WDRF in MCUSR. This means that WDE is always set when WDRF is
set. To clear WDE, WDRF must be cleared first. This feature ensures multiple resets during
conditions causing failure, and a safe start-up after the failure.
• Bit 5, 2..0 - WDP3..0: Watchdog Timer Prescaler 3, 2, 1 and 0
The WDP3..0 bits determine the Watchdog Timer prescaling when the Watchdog Timer is run-
ning. The different prescaling values and their corresponding time-out periods are shown in
Table 6-2 on page 62.
Table 6-2.
Watchdog Timer Prescale Select
Number of
Typical Time-out
at VCC = 5.0V
WDP3
WDP2
WDP1
WDP0
WDT Oscillator Cycles
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
2K (2048) cycles
16ms
32ms
64ms
0.125s
0.25s
0.5s
4K (4096) cycles
8K (8192) cycles
16K (16384) cycles
32K (32768) cycles
64K (65536) cycles
128K (131072) cycles
256K (262144) cycles
512K (524288) cycles
1024K (1048576) cycles
1.0s
2.0s
4.0s
8.0s
Reserved
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Atmel ATA5505 [Preliminary]
7. Interrupts
This section describes the specifics of the interrupt handling as performed in the Atmel®
AVR®. For a general explanation of the Atmel AVR interrupt handling, refer to “Reset and
Interrupt Handling” on page 16.
7.1
Interrupt Vectors in the Atmel AVR
Table 7-1.
Reset and Interrupt Vectors in the Atmel AVR
Program Address
Atmel AVR
Vector Nb.
Source
Interrupt Definition
External Pin, Power-on Reset, Brown-out Reset and
Watchdog System Reset
1
0x0000
RESET
2
3
0x0002
0x0004
0x0006
0x0008
0x000A
0x000C
0x000E
0x0010
0x0012
0x0014
0x0016
0x0018
0x001A
0x001C
0x001E
0x0020
0x0022
0x0024
0x0026
INT0
External Interrupt Request 0
External Interrupt Request 1
Pin Change Interrupt Request 0
Pin Change Interrupt Request 1
Watchdog Time-out Interrupt
Timer/Counter1 Capture Event
Timer/Counter1 Compare Match A
Timer/Coutner1 Compare Match B
Timer/Counter1 Overflow
Timer/Counter0 Compare Match A
Timer/Counter0 Overflow
LIN/UART Transfer Complete
LIN/UART Error
INT1
4
PCINT0
5
PCINT1
6
WDT
7
TIMER1 CAPT
TIMER1 COMPA
TIMER1 COMPB
TIMER1 OVF
TIMER0 COMPA
TIMER0 OVF
LIN TC
8
9
10
11
12
13
14
15
16
17
18
19
20
LIN ERR
SPI, STC
SPI Serial Transfer Complete
ADC Conversion Complete
EEPROM Ready
ADC
EE READY
ANALOG COMP
USI START
USI OVF
Analog Comparator
USI Start Condition Detection
USI Counter Overflow
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7.2
Program Setup in Atmel AVR
The most typical and general program setup for the Reset and Interrupt Vector Addresses in
Atmel® AVR® is (4-byte step - using “jmp” instruction):
Address(1) Label Code
Comments
0x0000
0x0002
0x0004
0x0006
0x0008
0x000A
0x000C
0x000E
0x0010
0x0012
0x0014
0x0016
0x0018
0x001A
0x001C
0x001E
0x0020
0x0022
0x0024
0x0026
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
jmp
RESET
; Reset Handler
INT0addr
INT1addr
PCINT0addr
PCINT1addr
WDTaddr
; IRQ0 Handler
; IRQ1 Handler
; PCINT0 Handler
; PCINT1 Handler
; Watchdog Timer Handler
; Timer1 Capture Handler
; Timer1 Compare A Handler
; Timer1 Compare B Handler
; Timer1 Overflow Handler
; Timer0 Compare A Handler
; Timer0 Overflow Handler
; LIN Transfer Complete Handler
; LIN Error Handler
ICP1addr
OC1Aaddr
OC1Baddr
OVF1addr
OC0Aaddr
OVF0addr
LINTCaddr
LINERRaddr
SPIaddr
; SPI Transfer Complete Handler
; ADC Conversion Complete Handler
; EEPROM Ready Handler
; Analog Comparator Handler
; USI Start Condition Handler
; USI Overflow Handler
ADCCaddr
ERDYaddr
ACIaddr
USISTARTaddr
USIOVFaddr
0x0028 RESET:
0x0029
ldi
out
ldi
out
sei
r16, high(RAMEND); Main program start
SPH,r16
; Set Stack Pointer to top of RAM
0x002A
r16, low(RAMEND)
SPL,r16
0x002B
0x002C
; Enable interrupts
0x002D
<instr> xxx
... ...
1. 16-bit address
...
...
Note:
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8. External Interrupts
8.1
Overview
The External Interrupts are triggered by the INT1..0 pins or any of the PCINT15..0 pins.
Observe that, if enabled, the interrupts will trigger even if the INT1..0 or PCINT15..0 pins are
configured as outputs. This feature provides a way of generating a software interrupt.
The pin change interrupt PCINT1 will trigger if any enabled PCINT15..8 pin toggles. The pin
change interrupt PCINT0 will trigger if any enabled PCINT7..0 pin toggles. The PCMSK1 and
PCMSK0 Registers control which pins contribute to the pin change interrupts. Pin change
interrupts on PCINT15..0 are detected asynchronously. This implies that these interrupts can
be used for waking the part also from sleep modes other than Idle mode.
The INT1..0 interrupts can be triggered by a falling or rising edge or a low level. This is set up
as indicated in the specification for the External Interrupt Control Register A – EICRA. When
the INT1..0 interrupts are enabled and are configured as level triggered, the interrupts will trig-
ger as long as the pin is held low. The recognition of falling or rising edge interrupts on INT1..0
requires the presence of an I/O clock, described in “Clock Systems and their Distribution” on
page 28. Low level interrupts and the edge interrupt on INT1..0 are detected asynchronously.
This implies that these interrupts can be used for waking the part also from sleep modes other
than Idle mode. The I/O clock is halted in all sleep modes except Idle mode.
Note that if a level triggered interrupt is used for wake-up from Power-down or Power-save,
the required level must be held long enough for the MCU to complete the wake-up to trigger
the level interrupt. If the level disappears before the end of the Start-up Time, the MCU will still
wake up, but no interrupt will be generated. The start-up time is defined by the SUT and
CKSEL Fuses as described in “Clock Systems and their Distribution” on page 28.
8.2
Pin Change Interrupt Timing
An example of timing of a pin change interrupt is shown in Figure 8-1.
Figure 8-1. Timing of pin change interrupts
0
7
pcint_sync
pcint_set/flag
pin_lat
pin_sync
pcint_in[i]
PCINT[i]
pin
PCIFn
(interrupt flag)
D
Q
D
Q
D
Q
D
Q
D
Q
LE
PCINT[i] bit
(of PCMSKn)
clk
clk
clk
PCINT[i] pin
pin_lat
pin_sync
pcint_in[i]
pcint_syn
pcint_set/flag
PCIFn
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8.3
External Interrupts Register Description
8.3.1
External Interrupt Control Register A – EICRA
The External Interrupt Control Register A contains control bits for interrupt sense control.
Bit
7
–
6
–
5
–
4
–
3
ISC11
R/W
0
2
ISC10
R/W
0
1
ISC01
R/W
0
0
ISC00
R/W
0
EICRA
Read/Write
Initial Value
R
0
R
0
R
0
R
0
• Bit 7..4 – Res: Reserved Bits
These bits are unused bits in the Atmel® AVR®, and will always read as zero.
• Bit 3, 2 – ISC11, ISC10: Interrupt Sense Control 1 Bit 1 and Bit 0
The External Interrupt 1 is activated by the external pin INT1 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT1 pin that activate the
interrupt are defined in Table 8-1. The value on the INT1 pin is sampled before detecting
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
• Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 Bit 1 and Bit 0
The External Interrupt 0 is activated by the external pin INT0 if the SREG I-flag and the corre-
sponding interrupt mask are set. The level and edges on the external INT0 pin that activate the
interrupt are defined in Table 8-1. The value on the INT0 pin is sampled before detecting
edges. If edge or toggle interrupt is selected, pulses that last longer than one clock period will
generate an interrupt. Shorter pulses are not guaranteed to generate an interrupt. If low level
interrupt is selected, the low level must be held until the completion of the currently executing
instruction to generate an interrupt.
Table 8-1.
Interrupt Sense Control
ISCn1
ISCn0
Description
0
0
1
1
0
1
0
1
The low level of INTn generates an interrupt request.
Any logical change on INTn generates an interrupt request.
The falling edge of INTn generates an interrupt request.
The rising edge of INTn generates an interrupt request.
8.3.2
External Interrupt Mask Register – EIMSK
Bit
7
–
6
–
5
–
4
–
3
–
2
–
1
0
INT1
R/W
0
INT0
R/W
0
EIMSK
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
• Bit 7, 2 – Res: Reserved Bits
These bits are unused bits in the Atmel AVR, and will always read as zero.
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• Bit 1 – INT1: External Interrupt Request 1 Enable
When the INT1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the
external pin interrupt is enabled. The Interrupt Sense Control1 bits 1/0 (ISC11 and ISC10) in
the External Interrupt Control Register A (EICRA) define whether the external interrupt is acti-
vated on rising and/or falling edge of the INT1 pin or level sensed. Activity on the pin will cause
an interrupt request even if INT1 is configured as an output. The corresponding interrupt of
External Interrupt Request 1 is executed from the INT1 Interrupt Vector.
• Bit 0 – INT0: External Interrupt Request 0 Enable
When the INT0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), the
external pin interrupt is enabled. The Interrupt Sense Control0 bits 1/0 (ISC01 and ISC00) in
the External Interrupt Control Register A (EICRA) define whether the external interrupt is acti-
vated on rising and/or falling edge of the INT0 pin or level sensed. Activity on the pin will cause
an interrupt request even if INT0 is configured as an output. The corresponding interrupt of
External Interrupt Request 0 is executed from the INT0 Interrupt Vector.
8.3.3
External Interrupt Flag Register – EIFR
Bit
7
6
–
5
–
4
–
3
–
2
–
1
INTF1
R/W
0
0
INTF0
R/W
0
–
R
0
EIFR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
• Bit 7, 2 – Res: Reserved Bits
These bits are unused bits in the Atmel® AVR®, and will always read as zero.
• Bit 1 – INTF1: External Interrupt Flag 1
When an edge or logic change on the INT1 pin triggers an interrupt request, INTF1 becomes
set (one). If the I-bit in SREG and the INT1 bit in EIMSK are set (one), the MCU will jump to
the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT1 is configured as a level interrupt.
• Bit 0 – INTF0: External Interrupt Flag 0
When an edge or logic change on the INT0 pin triggers an interrupt request, INTF0 becomes
set (one). If the I-bit in SREG and the INT0 bit in EIMSK are set (one), the MCU will jump to
the corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared
when INT0 is configured as a level interrupt.
8.3.4
Pin Change Interrupt Control Register – PCICR
Bit
7
6
5
–
4
–
3
–
2
–
1
PCIE1
R/W
0
0
PCIE0
R/W
0
–
–
PCICR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
• Bit 7, 2 – Res: Reserved Bits
These bits are unused bits in the Atmel AVR, and will always read as zero.
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• Bit 1 - PCIE1: Pin Change Interrupt Enable 1
When the PCIE1 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 1 is enabled. Any change on any enabled PCINT15..8 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI1
Interrupt Vector. PCINT15..8 pins are enabled individually by the PCMSK1 Register.
• Bit 0 - PCIE0: Pin Change Interrupt Enable 0
When the PCIE0 bit is set (one) and the I-bit in the Status Register (SREG) is set (one), pin
change interrupt 0 is enabled. Any change on any enabled PCINT7..0 pin will cause an inter-
rupt. The corresponding interrupt of Pin Change Interrupt Request is executed from the PCI0
Interrupt Vector. PCINT7..0 pins are enabled individually by the PCMSK0 Register.
8.3.5
Pin Change Interrupt Flag Register – PCIFR
Bit
7
6
5
–
4
–
3
–
2
–
1
PCIF1
R/W
0
0
PCIF0
R/W
0
–
–
PCIFR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
• Bit 7, 2 – Res: Reserved Bits
These bits are unused bits in the Atmel® AVR®, and will always read as zero.
• Bit 1 - PCIF1: Pin Change Interrupt Flag 1
When a logic change on any PCINT15..8 pin triggers an interrupt request, PCIF1 becomes set
(one). If the I-bit in SREG and the PCIE1 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
• Bit 0 - PCIF0: Pin Change Interrupt Flag 0
When a logic change on any PCINT7..0 pin triggers an interrupt request, PCIF0 becomes set
(one). If the I-bit in SREG and the PCIE0 bit in PCICR are set (one), the MCU will jump to the
corresponding Interrupt Vector. The flag is cleared when the interrupt routine is executed.
Alternatively, the flag can be cleared by writing a logical one to it.
8.3.6
Pin Change Mask Register 1 – PCMSK1
Bit
7
6
PCINT14
R/W
5
PCINT13
R/W
4
PCINT12
R/W
3
PCINT11
R/W
2
PCINT10
R/W
1
PCINT9
R/W
0
0
PCINT8
R/W
0
PCINT15
PCMSK1
Read/Write
Initial Value
R/W
0
0
0
0
0
0
• Bit 7..0 – PCINT15..8: Pin Change Enable Mask 15..8
Each PCINT15..8-bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT15..8 is set and the PCIE1 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT15..8 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
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8.3.7
Pin Change Mask Register 0 – PCMSK0
Bit
7
PCINT7
R/W
0
6
PCINT6
R/W
0
5
PCINT5
R/W
0
4
PCINT4
R/W
0
3
PCINT3
R/W
0
2
PCINT2
R/W
0
1
PCINT1
R/W
0
0
PCINT0
R/W
0
PCMSK0
Read/Write
Initial Value
• Bit 7..0 – PCINT7..0: Pin Change Enable Mask 7..0
Each PCINT7..0 bit selects whether pin change interrupt is enabled on the corresponding I/O
pin. If PCINT7..0 is set and the PCIE0 bit in PCICR is set, pin change interrupt is enabled on
the corresponding I/O pin. If PCINT7..0 is cleared, pin change interrupt on the corresponding
I/O pin is disabled.
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9. I/O-Ports
9.1
Introduction
All Atmel® AVR® ports have true Read-Modify-Write functionality when used as general digital
I/O ports. This means that the direction of one port pin can be changed without unintentionally
changing the direction of any other pin with the SBI and CBI instructions. The same applies
when changing drive value (if configured as output) or enabling/disabling of pull-up resistors (if
configured as input). Each output buffer has symmetrical drive characteristics with both high
sink and source capability. The pin driver is strong enough to drive LED displays directly. All
port pins have individually selectable pull-up resistors with a supply-voltage invariant resis-
tance. All I/O pins have protection diodes to both VCC and Ground as indicated in Figure 9-1.
Refer to “Electrical Characteristics” on page 254 for a complete list of parameters.
Figure 9-1. I/O Pin Equivalent Schematic
Rpu
Pxn
Logic
Cpin
See Figure
"General Digital I/O" for
Details
All registers and bit references in this section are written in general form. A lower case “x” rep-
resents the numbering letter for the port, and a lower case “n” represents the bit number.
However, when using the register or bit defines in a program, the precise form must be used.
For example, PORTB3 for bit no. 3 in Port B, here documented generally as PORTxn. The
physical I/O Registers and bit locations are listed in “Register Description for I/O Ports” on
page 89.
Three I/O memory address locations are allocated for each port, one each for the Data Regis-
ter – PORTx, Data Direction Register – DDRx, and the Port Input Pins – PINx. The Port Input
Pins I/O location is read only, while the Data Register and the Data Direction Register are
read/write. However, writing a logic one to a bit in the PINx Register, will result in a toggle in
the corresponding bit in the Data Register. In addition, the Pull-up Disable – PUD bit in
MCUCR or PUDx in PORTCR disables the pull-up function for all pins in all ports when set.
Using the I/O port as General Digital I/O is described in “Ports as General Digital I/O” on page
71. Most port pins are multiplexed with alternate functions for the peripheral features on the
device. How each alternate function interferes with the port pin is described in “Alternate Port
Functions” on page 75. Refer to the individual module sections for a full description of the
alternate functions.
Note that enabling the alternate function of some of the port pins does not affect the use of the
other pins in the port as general digital I/O.
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9.2
Ports as General Digital I/O
The ports are bi-directional I/O ports with optional internal pull-ups. Figure 9-2 shows a func-
tional description of one I/O-port pin, here generically called Pxn.
Figure 9-2. General Digital I/O(Note:)
PUD
Q
D
DDxn
Q CLR
WDx
RDx
RESET
1
0
Q
D
Pxn
PORTxn
Q CLR
WPx
WRx
RESET
SLEEP
RRx
SYNCHRONIZER
RPx
D
Q
D
L
Q
Q
PINxn
Q
clk I/O
WDx: WRITE DDRx
RDx: READ DDRx
WRx: WRITE PORTx
RRx: READ PORTx REGISTER
RPx: READ PORTx PIN
PUD: PULLUP DISABLE
SLEEP: SLEEP CONTROL
clkI/O: I/O CLOCK
WPx: WRITE PINx REGISTER
Note:
WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O
,
SLEEP, and PUD are common to all ports.
9.2.1
Configuring the Pin
Each port pin consists of three register bits: DDxn, PORTxn, and PINxn. As shown in “Regis-
ter Description for I/O Ports” on page 89, the DDxn bits are accessed at the DDRx I/O
address, the PORTxn bits at the PORTx I/O address, and the PINxn bits at the PINx I/O
address.
The DDxn bit in the DDRx Register selects the direction of this pin. If DDxn is written logic one,
Pxn is configured as an output pin. If DDxn is written logic zero, Pxn is configured as an input
pin.
If PORTxn is written logic one when the pin is configured as an input pin, the pull-up resistor is
activated. To switch the pull-up resistor off, PORTxn has to be written logic zero or the pin has
to be configured as an output pin. The port pins are tri-stated when reset condition becomes
active, even if no clocks are running.
If PORTxn is written logic one when the pin is configured as an output pin, the port pin is
driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin,
the port pin is driven low (zero).
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9.2.2
9.2.3
Toggling the Pin
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of
DDRxn. Note that the SBI assembler instruction can be used to toggle one single bit in a port.
Break-Before-Make Switching
In the Break-Before-Make mode when switching the DDRxn bit from input to output an imme-
diate tri-state period lasting one system clock cycle is introduced as indicated in Figure 9-3.
For example, if the system clock is 4MHz and the DDRxn is written to make an output, the
immediate tri-state period of 250ns is introduced, before the value of PORTxn is seen on the
port pin. To avoid glitches it is recommended that the maximum DDRxn toggle frequency is
two system clock cycles. The Break-Before-Make is a port-wise mode and it is activated by the
port-wise BBMx enable bits. For further information about the BBMx bits, see “Port Control
Register – PORTCR” on page 78. When switching the DDRxn bit from output to input there is
no immediate tri-state period introduced.
Figure 9-3. Break Before Make, switching between input and output
YSTEM CLOCK
R 16
R 17
0x02
0x01
nop
NSTRUCTIONS
PORTx
out DDRx, r16
out DDRx, r17
0x55
0x02
DDRx
0x01
0x01
tri-state
Px0
immediate tri-state cycle
tri-state
tri-state
immediate tri-state cycle
Px1
9.2.4
Switching Between Input and Output
When switching between tri-state ({DDxn, PORTxn} = 0, 0) and output high
({DDxn, PORTxn} = 1, 1), an intermediate state with either pull-up enabled
{DDxn, PORTxn} = 0, 1) or output low ({DDxn, PORTxn} = 1, 0) must occur. Normally, the
pull-up enabled state is fully acceptable, as a high-impedant environment will not notice the
difference between a strong high driver and a pull-up. If this is not the case, the PUD bit in the
MCUCR Register or the PUDx bit in PORTCR Register can be set to disable all pull-ups in the
port.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0, 0) or the output high state
({DDxn, PORTxn} = 1, 1) as an intermediate step.
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Table 9-1 summarizes the control signals for the pin value.
Table 9-1.
Port Pin Configurations
PUD
DDxn
PORTxn
(in MCUCR) (1)
I/O
Pull-up Comment
0
0
1
X
Input
No
Tri-state (Hi-Z)
Pxn will source current if ext. pulled
low.
0
0
Input
Yes
0
1
1
1
0
1
1
X
X
Input
Output
Output
No
No
No
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
Note:
1. Or port-wise PUDx bit in PORTCR register.
9.2.5
Reading the Pin Value
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in Figure 9-2, the PINxn Register bit and the preceding latch
constitute a synchronizer. This is needed to avoid metastability if the physical pin changes
value near the edge of the internal clock, but it also introduces a delay. Figure 9-4 shows a
timing diagram of the synchronization when reading an externally applied pin value. The max-
imum and minimum propagation delays are denoted tpd,max and tpd,min respectively.
Figure 9-4. Synchronization when Reading an Externally Applied Pin value
SYSTEM CLK
XXX
XXX
in r17, PINx
INSTRUCTIONS
SYNC LATCH
PINxn
0x00
tpd, max
0xFF
r17
tpd, min
Consider the clock period starting shortly after the first falling edge of the system clock. The
latch is closed when the clock is low, and goes transparent when the clock is high, as indi-
cated by the shaded region of the “SYNC LATCH” signal. The signal value is latched when the
system clock goes low. It is clocked into the PINxn Register at the succeeding positive clock
edge. As indicated by the two arrows tpd,max and tpd,min, a single signal transition on the pin
will be delayed between ½ and 1½ system clock period depending upon the time of assertion.
When reading back a software assigned pin value, a nop instruction must be inserted as indi-
cated in Figure 9-5. The out instruction sets the “SYNC LATCH” signal at the positive edge of
the clock. In this case, the delay tpd through the synchronizer is 1 system clock period.
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Figure 9-5. Synchronization when Reading a Software Assigned Pin Value
SYSTEM CLK
0xFF
r16
out PORTx, r16
nop
in r17, PINx
INSTRUCTIONS
SYNC LATCH
PINxn
0x00
tpd
0xFF
r17
The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and
define the port pins from 4 to 7 as input with pull-ups assigned to port pins 6 and 7. The result-
ing pin values are read back again, but as previously discussed, a nop instruction is included
to be able to read back the value recently assigned to some of the pins.
Assembly Code Example(1)
...
; Define pull-ups and set outputs high
; Define directions for port pins
ldi r16,(1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0)
ldi r17,(1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0)
out PORTB,r16
out DDRB,r17
; Insert nop for synchronization
nop
; Read port pins
in
r16,PINB
...
C Code Example
unsigned char i;
...
/* Define pull-ups and set outputs high */
/* Define directions for port pins */
PORTB = (1<<PB7)|(1<<PB6)|(1<<PB1)|(1<<PB0);
DDRB = (1<<DDB3)|(1<<DDB2)|(1<<DDB1)|(1<<DDB0);
/* Insert nop for synchronization*/
__no_operation();
/* Read port pins */
i = PINB;
...
Note:
1. For the assembly program, two temporary registers are used to minimize the time from
pull-ups are set on pins 0, 1, 6, and 7, until the direction bits are correctly set, defining bit 2
and 3 as low and redefining bits 0 and 1 as strong high drivers.
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9.2.6
Digital Input Enable and Sleep Modes
As shown in Figure 9-2, the digital input signal can be clamped to ground at the input of the
Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in
Power-down or Power-save mode to avoid high power consumption if some input signals are
left floating, or have an analog signal level close to VCC/2.
SLEEP is overridden for port pins enabled as external interrupt pins. If the external interrupt
request is not enabled, SLEEP is active also for these pins. SLEEP is also overridden by vari-
ous other alternate functions as described in “Alternate Port Functions” on page 75.
If a logic high level (“one”) is present on an asynchronous external interrupt pin configured as
“Interrupt on Rising Edge, Falling Edge, or Any Logic Change on Pin” while the external inter-
rupt is not enabled, the corresponding External Interrupt Flag will be set when resuming from
the above mentioned Sleep mode, as the clamping in these sleep mode produces the
requested logic change.
9.2.7
Unconnected Pins
If some pins are unused, it is recommended to ensure that these pins have a defined level.
Even though most of the digital inputs are disabled in the deep sleep modes as described
above, floating inputs should be avoided to reduce current consumption in all other modes
where the digital inputs are enabled (Reset, Active mode and Idle mode).
The simplest method to ensure a defined level of an unused pin, is to enable the internal
pull-up. In this case, the pull-up will be disabled during reset. If low power consumption during
reset is important, it is recommended to use an external pull-up or pull-down. Connecting
unused pins directly to VCC or GND is not recommended, since this may cause excessive cur-
rents if the pin is accidentally configured as an output.
9.3
Alternate Port Functions
Most port pins have alternate functions in addition to being general digital I/Os. Figure 9-6
shows how the port pin control signals from the simplified Figure 9-2 can be overridden by
alternate functions. The overriding signals may not be present in all port pins, but the figure
serves as a generic description applicable to all port pins in the Atmel® AVR® microcontroller
family.
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Figure 9-6. Alternate Port Functions(1)
PUOExn
PUOVxn
1
PUD
0
DDOExn
DDOVxn
1
Q
D
0
DDxn
Q CLR
WDx
RDx
PVOExn
PVOVxn
RESET
1
1
0
Pxn
Q
D
0
PORTxn
PTOExn
WPx
Q CLR
DIEOExn
DIEOVxn
1
RESET
WRx
RRx
RPx
0
SLEEP
SYNCHRONIZER
SET
D
Q
D
L
Q
Q
PINxn
CLR Q
CLR
clk I/O
DIxn
AIOxn
PUOExn: Pxn PULL-UP OVERRIDE ENABLE
PUD: PULLUP DISABLE
PUOVxn: Pxn PULL-UP OVERRIDE VALUE
WDx: WRITE DDRx
RDx: READ DDRx
DDOExn: Pxn DATA DIRECTION OVERRIDE ENABLE
DDOVxn: Pxn DATA DIRECTION OVERRIDE VALUE
PVOExn: Pxn PORT VALUE OVERRIDE ENABLE
PVOVxn: Pxn PORT VALUE OVERRIDE VALUE
RRx: READ PORTx REGISTER
WRx: WRITE PORTx
RPx: READ PORTx PIN
WPx: WRITE PINx
DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE
DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE
SLEEP: SLEEP CONTROL
clk
:
I/O CLOCK
DIxn: DIGITAL INPUT PIN n ON PORTx
AIOxn: ANALOG INPUT/OUTPUT PIN n ON PORTx
I/O
PTOExn: Pxn, PORT TOGGLE OVERRIDE ENABLE
Note:
1. WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. clkI/O
,
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
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Table 9-2 summarizes the function of the overriding signals. The pin and port indexes from
Figure 9-6 are not shown in the succeeding tables. The overriding signals are generated inter-
nally in the modules having the alternate function.
Table 9-2.
Generic Description of Overriding Signals for Alternate Functions
Signal Name
Full Name
Description
If this signal is set, the pull-up enable is controlled by the PUOV
signal. If this signal is cleared, the pull-up is enabled when
{DDxn, PORTxn, (PUD or PDUx)} = 0, 1, 0.
Pull-up Override
Enable
PUOE
PUOV
DDOE
DDOV
If PUOE is set, the pull-up is enabled/disabled when PUOV is
set/cleared, regardless of the setting of the DDxn, PORTxn,
PUD and PUDx Register bits.
Pull-up Override
Value
If this signal is set, the Output Driver Enable is controlled by the
DDOV signal. If this signal is cleared, the Output driver is
enabled by the DDxn Register bit.
Data Direction
Override Enable
If DDOE is set, the Output Driver is enabled/disabled when
DDOV is set/cleared, regardless of the setting of the DDxn
Register bit.
Data Direction
Override Value
If this signal is set and the Output Driver is enabled, the port
Port Value Override value is controlled by the PVOV signal. If PVOE is cleared, and
PVOE
Enable
the Output Driver is enabled, the port Value is controlled by the
PORTxn Register bit.
Port Value Override If PVOE is set, the port value is set to PVOV, regardless of the
PVOV
PTOE
Value
setting of the PORTxn Register bit.
Port Toggle Override
Enable
If PTOE is set, the PORTxn Register bit is inverted.
If this bit is set, the Digital Input Enable is controlled by the
DIEOV signal. If this signal is cleared, the Digital Input Enable is
determined by MCU state (Normal mode, sleep mode).
Digital Input Enable
Override Enable
DIEOE
DIEOV
If DIEOE is set, the Digital Input is enabled/disabled when
DIEOV is set/cleared, regardless of the MCU state (Normal
mode, sleep mode).
Digital Input Enable
Override Value
This is the Digital Input to alternate functions. In the figure, the
signal is connected to the output of the Schmitt Trigger but
before the synchronizer. Unless the Digital Input is used as a
clock source, the module with the alternate function will use its
own synchronizer.
DI
Digital Input
This is the Analog Input/output to/from alternate functions. The
AIO
Analog Input/Output signal is connected directly to the pad, and can be used
bi-directionally.
The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for fur-
ther details.
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9.3.1
MCU Control Register – MCUCR
Bit
7
–
6
BODS
R/W
0
5
BODSE
R/W
0
4
3
–
2
–
1
–
0
–
PUD
R/W
0
MCUCR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
• Bit 4 – PUD: Pull-up Disable
When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and
PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0, 1). See “Con-
figuring the Pin” on page 71 for more details about this feature.
9.3.2
Port Control Register – PORTCR
Bit
7
6
-
5
BBMB
R/W
0
4
BBMA
R/W
0
3
-
2
-
1
PUDB
R/W
0
0
PUDA
R/W
0
-
R/W
0
PORTCR
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
• Bits 5, 4 – BBMx: Break-Before-Make Mode Enable
When these bits are written to one, the port-wise Break-Before-Make mode is activated. The
intermediate tri-state cycle is then inserted when writing DDRxn to make an output. For further
information, see “Break-Before-Make Switching” on page 72.
• Bits 1, 0 – PUDx: Port-Wise Pull-up Disable
When these bits are written to one, the port-wise pull-ups in the defined I/O ports are disabled
even if the DDxn and PORTxn Registers are configured to enable the pull-ups
({DDxn, PORTxn} = 0, 1). The Port-Wise Pull-up Disable bits are ORed with the global Pull-up
Disable bit (PUD) from the MCUCR register. See “Configuring the Pin” on page 71 for more
details about this feature.
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9.3.3
Alternate Functions of Port A
The Port A pins with alternate functions are shown in Table 9-3.
Table 9-3.
Port Pin
Port A Pins Alternate Functions
Alternate Function
PCINT7 (Pin Change Interrupt 7)
ADC7 (ADC Input Channel 7)
PA7
PA6
AIN1 (Analog Comparator Positive Input)
XREF (Internal Voltage Reference Output)
AREF (External Voltage Reference Input)
PCINT6 (Pin Change Interrupt 6)
ADC6 (ADC Input Channel 6)
AIN0 (Analog Comparator Negative Input)
SS (SPI Slave Select Input)
PCINT5 (Pin Change Interrupt 5)
ADC5 (ADC Input Channel 5)
T1 (Timer/Counter1 Clock Input)
PA5
PA4
USCK (Three-wire Mode USI Alternate Clock Input)
SCL (Two-wire Mode USI Alternate Clock Input)
SCK (SPI Master Clock)
PCINT4 (Pin Change Interrupt 4)
ADC4 (ADC Input Channel 4)
ICP1 (Timer/Counter1 Input Capture Trigger)
DI (Three-wire Mode USI Alternate Data Input)
SDA (Two-wire Mode USI Alternate Data Input / Output)
MOSI (SPI Master Output / Slave Input)
PCINT3 (Pin Change Interrupt 3)
ADC3 (ADC Input Channel 3)
ISRC (Current Source Pin)
PA3
PA2
INT1 (External Interrupt1 Input)
PCINT2 (Pin Change Interrupt 2)
ADC2 (ADC Input Channel 2)
OC0A (Output Compare and PWM Output A for Timer/Counter0)
DO (Three-wire Mode USI Alternate Data Output)
MISO (SPI Master Input / Slave Output)
PCINT1 (Pin Change Interrupt 1)
ADC1 (ADC Input Channel 1)
TXD (UART Transmit Pin)
PA1
PA0
TXLIN (LIN Transmit Pin)
PCINT0 (Pin Change Interrupt 0)
ADC0 (ADC Input Channel 0)
RXD (UART Receive Pin)
RXLIN (LIN Receive Pin)
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The alternate pin configuration is as follows:
• PCINT7/ADC7/AIN1/XREF/AREF – Port A, Bit7
PCINT7: Pin Change Interrupt, source 7.
ADC7: Analog to Digital Converter, channel 7.
AIN1: Analog Comparator Positive Input. This pin is directly connected to the positive input
of the Analog Comparator.
XREF: Internal Voltage Reference Output. The internal voltage reference 2.56V or 1.1V is
output when XREFEN is set and if either 2.56V or 1.1V is used as reference for ADC
conversion. When XREF output is enabled, the pin port pull-up and digital output
driver are turned off.
AREF: External Voltage Reference Input for ADC. The pin port pull-up and digital output
driver are disabled when the pin is used as an external voltage reference input for
ADC or as when the pin is only used to connect a bypass capacitor for the voltage ref-
erence of the ADC.
• PCINT6/ADC6/AIN0/SS – Port A, Bit6
PCINT6: Pin Change Interrupt, source 6.
ADC6: Analog to Digital Converter, channel 6.
AIN0: Analog Comparator Negative Input. This pin is directly connected to the negative input
of the Analog Comparator.
SS: SPI Slave Select Input. When the SPI is enabled as a slave, this pin is configured as an
input regardless of the setting of DDA6. As a slave, the SPI is activated when this pin
is driven low. When the SPI is enabled as a master, the data direction of this pin is
controlled by DDA6. When the pin is forced to be an input, the pull-up can still be con-
trolled by the PORTA6 bit.
• PCINT5/ADC5/T1/USCK/SCL/SCK – Port A, Bit5
PCINT5: Pin Change Interrupt, source 5.
ADC5: Analog to Digital Converter, channel 5.
T1: Timer/Counter1 Clock Input.
USCK: Three-wire Mode USI Clock Input.
SCL: Two-wire Mode USI Clock Input.
SCK: SPI Master Clock output, Slave Clock input pin. When the SPI is enabled as a slave,
this pin is configured as an input regardless of the setting of DDA5. When the SPI is
enabled as a master, the data direction of this pin is controlled by DDA5. When the pin
is forced to be an input, the pull-up can still be controlled by the PORTA5 bit.
• PCINT4/ADC4/ICP1/DI/SDA/MOSI – Port A, Bit 4
PCINT4: Pin Change Interrupt, source 4.
ADC4: Analog to Digital Converter, channel 4.
ICP1: Timer/Counter1 Input Capture Trigger. The PA3 pin can act as an Input Capture pin for
Timer/Counter1.
DI: Three-wire Mode USI Data Input. USI Three-wire mode does not override normal port
functions, so pin must be configure as an input for DI function.
SDA: Two-wire Mode Serial Interface (USI) Data Input / Output.
MOSI: SPI Master Output / Slave Input. When the SPI is enabled as a Slave, this pin is con-
figured as an input regardless of the setting of DDA3. When the SPI is enabled as a
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Master, the data direction of this pin is controlled by DDA3. When the pin is forced by
the SPI to be an input, the pull-up can still be controlled by the PORTA3 bit.
• PCINT3/ADC3/ISRC/INT1 – Port A, Bit 3
PCINT3: Pin Change Interrupt, source 3.
ADC3: Analog to Digital Converter, channel 3.
ISCR: Current Source Output pin. While current is sourced by the Current Source module,
the user can use the Analog to Digital Converter channel 4 (ADC4) to measure the pin
voltage.
INT1: External Interrupt, source 1. The PA4 pin can serve as an external interrupt source.
• PCINT2/ADC2/OC0A/DO/MISO – Port A, Bit 2
PCINT2: Pin Change Interrupt, source 2.
ADC2: Analog to Digital Converter, channel 2.
OC0A: Output Compare Match A or output PWM A for Timer/Counter0. The pin has to be
configured as an output (DDA2 set (one)) to serve these functions.
DO: Three-wire Mode USI Data Output. Three-wire mode data output overrides PORTA2
and it is driven to the port when the data direction bit DDA2 is set. PORTA2 still
enables the pull-up, if the direction is input and PORTA2 is set (one).
MISO: Master Data input, Slave Data output pin for SPI channel. When the SPI is enabled
as a Master, this pin is configured as an input regardless of the setting of DDA2. When
the SPI is enabled as a Salve, the data direction of this pin is controlled by DDA2.
When the pin is forced to be an input, the pull-up can still be controlled by PORTA2.
• PCINT1/ADC1/TXD/TXLIN – Port A, Bit 1
PCINT1: Pin Change Interrupt, source 1.
ADC1: Analog to Digital Converter, channel 1.
TXD: UART Transmit pin. When the UART transmitter is enabled, this pin is configured as an
output regardless the value of DDA1. PORTA1 still enables the pull-up, if the direction
is input and PORTA2 is set (one).
TXLIN: LIN Transmit pin. When the LIN is enabled, this pin is configured as an output
regardless the value of DDA1. PORTA1 still enables the pull-up, if the direction is input
and PORTA2 is set (one).
• PCINT0/ADC0/RXD/RXLIN – Port A, Bit 0
PCINT0: Pin Change Interrupt, source 0.
ADC0: Analog to Digital Converter, channel 0.
RXD: UART Receive pin. When the UART receiver is enabled, this pin is configured as an
input regardless of the value of DDA0. When the pin is forced to be an input, a logical
one in PORTA0 will turn on the internal pull-up.
RXLIN: LIN Receive pin. When the LIN is enabled, this pin is configured as an input regard-
less of the value of DDA0. When the pin is forced to be an input, a logical one in
PORTA0 will turn on the internal pull-up.
Table 9-4 and Table 9-5 relate the alternate functions of Port A to the overriding signals shown
in Figure 9-6 on page 76.
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Table 9-4.
Overriding Signals for Alternate Functions in PA7..PA4
PA7/PCINT7/
Signal
Name
ADC7/AIN1
/XREF/AREF
PA6/PCINT6/
ADC6/AIN0/SS
PA5/PCINT5/ADC5/
T1/USCK/SCL/SCK
PA4/PCINT4/ADC4/
ICP1/DI/SDA/MOSI
PUOE
PUOV
0
0
SPE & MSTR
SPE & MSTR
SPE & MSTR
PORTA6 & PUD
PORTA5 & PUD
PORTA4 & PUD
(SPE & MSTR) |
(USI_2_WIRE &
USIPOS)
(SPE & MSTR) |
(USI_2_WIRE & USIPOS)
DDOE
DDOV
PVOE
PVOV
0
0
0
0
SPE & MSTR
{ (SPE & MSTR) ?
(0) :
(USI_SCL_HOLD |
PORTA5)
0
0
0
(USI_SHIFTOUT |
& DDRA6
PORTA4)
& DDRA4) }
(SPE & MSTR) |
(SPE & MSTR) |
(USI_2_WIRE & USIPOS (USI_2_WIRE & USIPOS
& DDRA5)
& DDRA4)
{ (SPE & MSTR) ?
(SCK_OUTPUT) :
{ (SPE & MSTR) ?
(MOSI_OUTPUT) :
~ (USI_2_WIRE &
USIPOS
~ (USI_2_WIRE &
USIPOS
& DDRA5) }
& DDRA4) }
PTOE
0
0
USI_PTOE & USIPOS
0
ADC7D |
ADC6D |
ADC5D |
ADC4D |
DIEOE
(USISIE & USIPOS) |
(PCIE0 & PCMSK05)
(USISIE & USIPOS) |
(PCIE0 & PCMSK04)
(PCIE0 &
PCMSK07)
(PCIE0 &
PCMSK06)
PCIE0 &
PCMSK07
PCIE0 &
PCMSK06
(USISIE & USIPOS) |
(PCIE0 & PCMSK05)
(USISIE & USIPOS) |
(PCIE0 & PCMSK04)
DIEOV
DI
PCINT5 -/- T1
-/- USCK -/- SCL -/- SCK
PCINT4 -/- ICP1
-/- DI -/- SDA -/- MOSI
PCINT7
PCINT6 -/- SS
ADC6 -/- AIN0
ADC7 -/- AIN1 -/-
XREF -/- AREF
AIO
ADC5
ADC4
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Table 9-5.
Overriding Signals for Alternate Functions in PA3..PA0
Signal PA3/PCINT3/ADC3/
PA2/PCINT2/ADC2/
OC0A/DO/MISO
PA1/PCINT1/ADC1/ PA0/PCINT0/ADC0/
Name
ISRC/INT1
TXD/TXLIN
RXD/RXLIN
PUOE
0
SPE & MSTR
LIN_TX_ENABLE
LIN_RX_ENABLE
{ (LIN_TX_ENABLE)
?
PUOV
PORTA3 & PUD
PORTA2 & PUD
PORTA0 & PUD
(0) : (PORTA1 & PUD)
}
DDOE
DDOV
0
0
SPE & MSTR
LIN_TX_ENABLE
LIN_TX_ENABLE
LIN_RX_ENABLE
0
0
(SPE & MSTR) |
(USI_2_WIRE &
USI_3_WIRE & USIPOS) |
OC0A
PVOE
0
LIN_TX_ENABLE
0
{ (SPE & MSTR) ?
(MISO_OUTPUT) :
{ (LIN_TX_ENABLE)
( ( USI_2_WIRE &
USI_3_WIRE & USIPOS ) ?
(USI_SHIFTOUT) : (OC0A) )
}
?
PVOV
0
0
0
(LIN_TX) : (0) }
PTOE
0
0
0
ADC3D |
ADC2D |
ADC1D |
ADC0D |
INT1_ENABLE |
DIEOE
(PCIE0 & PCMSK02)
(PCIE0 & PCMSK01) (PCIE0 & PCMSK00)
(PCIE0 &
PCMSK03)
INT1_ENABLE |
DIEOV
PCIE0 & PCMSK02
PCIE0 & PCMSK01 PCIE0 & PCMSK00
(PCIE0 &
PCMSK03)
DI
PCINT3 -/- INT1
ADC3 -/- ISRC
PCINT2 -/- MISO
PCINT1
ADC1
PCINT0
ADC0
AIO
ADC2
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9.3.4
Alternate Functions of Port B
The Port B pins with alternate functions are shown in Table 9-6.
Table 9-6.
Port Pin
Port B Pins Alternate Functions
Alternate Functions
PCINT15 (Pin Change Interrupt 15)
ADC10 (ADC Input Channel 10)
PB7
PB6
PB5
OC1BX (Output Compare and PWM Output B-X for Timer/Counter1)
RESET (Reset input pin)
dW (debugWIRE I/O)
PCINT14 (Pin Change Interrupt 14)
ADC9 (ADC Input Channel 9)
OC1AX (Output Compare and PWM Output A-X for Timer/Counter1)
INT0 (External Interrupt0 Input)
PCINT13 (Pin Change Interrupt 13)
ADC8 (ADC Input Channel 8)
OC1BW (Output Compare and PWM Output B-W for Timer/Counter1)
XTAL2 (Chip clock Oscillator pin 2)
CLKO (System clock output)
PCINT12 (Pin Change Interrupt 12)
OC1AW (Output Compare and PWM Output A-W for Timer/Counter1)
XTAL1 (Chip clock Oscillator pin 1)
PB4
PB3
PB2
CLKI (External clock input)
PCINT11 (Pin Change Interrupt 11)
OC1BV (Output Compare and PWM Output B-V for Timer/Counter1)
PCINT10 (Pin Change Interrupt 10)
OC1AV (Output Compare and PWM Output A-V for Timer/Counter1)
USCK (Three-wire Mode USI Default Clock Input)
SCL (Two-wire Mode USI Default Clock Input)
PCINT9 (Pin Change Interrupt 9)
PB1
PB0
OC1BU (Output Compare and PWM Output B-U for Timer/Counter1)
DO (Three-wire Mode USI Default Data Output)
PCINT8 (Pin Change Interrupt 8)
OC1AU (Output Compare and PWM Output A-U for Timer/Counter1)
DI (Three-wire Mode USI Default Data Input)
SDA (Two-wire Mode USI Default Data Input / Output)
The alternate pin configuration is as follows:
• PCINT15/ADC10/OC1BX/RESET/dW – Port B, Bit 7
PCINT15: Pin Change Interrupt, source 15.
ADC10: Analog to Digital Converter, channel 10.
OC1BX: Output Compare and PWM Output B-X for Timer/Counter1. The PB7 pin has to be
configured as an output (DDB7 set (one)) to serve this function. The OC1BX pin is
also the output pin for the PWM mode timer function (c.f. OC1BX bit of TCCR1D regis-
ter).
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Atmel ATA5505 [Preliminary]
RESET: Reset input pin. When the RSTDISBL Fuse is programmed, this pin functions as a
normal I/O pin, and the part will have to rely on Power-on Reset and Brown-out Reset
as its reset sources. When the RSTDISBL Fuse is unprogrammed, the reset circuitry
is connected to the pin, and the pin can not be used as an I/O pin.
If PB7 is used as a reset pin, DDB7, PORTB7 and PINB7 will all read 0.
dW: When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unpro-
grammed, the RESET port pin is configured as a wire-AND (open-drain) bi-directional
I/O pin with pull-up enabled and becomes the communication gateway between target
and emulator.
• PCINT14/ADC9/OC1AX/INT0 – Port B, Bit 6
PCINT14: Pin Change Interrupt, source 14.
ADC9: Analog to Digital Converter, channel 9.
OC1AX: Output Compare and PWM Output A-X for Timer/Counter1. The PB6 pin has to be
configured as an output (DDB6 set (one)) to serve this function. The OC1AX pin is
also the output pin for the PWM mode timer function (c.f. OC1AX bit of TCCR1D regis-
ter).
INT0: External Interrupt0 Input. The PB6 pin can serve as an external interrupt source.
• PCINT13/ADC8/OC1BW/XTAL2/CLKO – Port B, Bit 5
PCINT13: Pin Change Interrupt, source 13.
ADC8: Analog to Digital Converter, channel 8.
OC1BW: Output Compare and PWM Output B-W for Timer/Counter1. The PB5 pin has to be
configured as an output (DDB5 set (one)) to serve this function. The OC1BW pin is
also the output pin for the PWM mode timer function (c.f. OC1BW bit of TCCR1D reg-
ister).
XTAL2: Chip clock Oscillator pin 2. Used as clock pin for crystal Oscillator or Low-frequency
crystal Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.
CLKO: Divided system clock output. The divided system clock can be output on the PB5 pin.
The divided system clock will be output if the CKOUT Fuse is programmed, regardless
of the PORTB5 and DDB5 settings. It will also be output during reset.
• PCINT12/OC1AW/XTAL1/CLKI – Port B, Bit 4
PCINT12: Pin Change Interrupt, source 12.
OC1AW: Output Compare and PWM Output A-W for Timer/Counter1. The PB4 pin has to be
configured as an output (DDB4 set (one)) to serve this function. The OC1AW pin is
also the output pin for the PWM mode timer function (c.f. OC1AW bit of TCCR1D reg-
ister).
XTAL1: Chip clock Oscillator pin 1. Used for all chip clock sources except internal calibrated
RC Oscillator. When used as a clock pin, the pin can not be used as an I/O pin.
CLKI: External clock input. When used as a clock pin, the pin can not be used as an I/O pin.
Note:
If PB4 is used as a clock pin (XTAL1 or CLKI), DDB4, PORTB4 and PINB4 will all read 0.
• PCINT11/OC1BV – Port B, Bit 3
PCINT11: Pin Change Interrupt, source 11.
OC1BV: Output Compare and PWM Output B-V for Timer/Counter1. The PB3 pin has to be
configured as an output (DDB3 set (one)) to serve this function. The OC1BV pin is
also the output pin for the PWM mode timer function (c.f. OC1BV bit of TCCR1D regis-
ter).
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• PCINT10/OC1AV/USCK/SCL – Port B, Bit 2
PCINT10: Pin Change Interrupt, source 10.
OC1AV: Output Compare and PWM Output A-V for Timer/Counter1. The PB2 pin has to be
configured as an output (DDB2 set (one)) to serve this function. The OC1AV pin is
also the output pin for the PWM mode timer function (c.f. OC1AV bit of TCCR1D regis-
ter).
USCK: Three-wire Mode USI Clock Input.
SCL: Two-wire Mode USI Clock Input.
• PCINT9/OC1BU/DO – Port B, Bit 1
PCINT9: Pin Change Interrupt, source 9.
OC1BU: Output Compare and PWM Output B-U for Timer/Counter1. The PB1 pin has to be
configured as an output (DDB1 set (one)) to serve this function. The OC1BU pin is
also the output pin for the PWM mode timer function (c.f. OC1BU bit of TCCR1D reg-
ister).
DO: Three-wire Mode USI Data Output. Three-wire mode data output overrides PORTB1
and it is driven to the port when the data direction bit DDB1 is set. PORTB1 still
enables the pull-up, if the direction is input and PORTB1 is set (one).
• PCINT8/OC1AU/DI/SDA – Port B, Bit 0
IPCINT8: Pin Change Interrupt, source 8.
OC1AU: Output Compare and PWM Output A-U for Timer/Counter1. The PB0 pin has to be
configured as an output (DDB0 set (one)) to serve this function. The OC1AU pin is
also the output pin for the PWM mode timer function (c.f. OC1AU bit of TCCR1D regis-
ter).
DI: Three-wire Mode USI Data Input. USI Three-wire mode does not override normal port
functions, so pin must be configure as an input for DI function.
SDA: Two-wire Mode Serial Interface (USI) Data Input / Output.
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Table 9-7 and Table 9-8 relate the alternate functions of Port B to the overriding signals shown
in Figure 9-6 on page 76.
Table 9-7.
Overriding Signals for Alternate Functions in PB7..PB4
Signal PB7/PCINT15/ADC10/ PB6/PCINT14/ADC9/ PB5/PCINT13/ADC8/
PB4/PCINT12/
OC1BW/XTAL2/CLKO OC1AW/XTAL1/CLKI
Name OC1BX/RESET/dW
OC1AX/INT0
PUOE
PUOV
DDOE
DDOV
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
OC1B_ENABLE &
OC1A_ENABLE &
OC1B_ENABLE &
OC1A_ENABLE &
PVOE
OC1BX
OC1AX
OC1BW
OC1AW
PVOV
PTOE
OC1B
0
OC1A
0
OC1B
0
OC1A
0
ADC9D |
ADC10D |
ADC8D |
DIEOE
INT0_ENABLE |
(PCIE1 & PCMSK14)
(PCIE1 & PCMSK13)
(PCIE1 & PCMSK15)
(PCIE1 & PCMSK13)
INT0_ENABLE |
DIEOV PCIE1 & PCMSK15
PCIE1 & PCMSK13
1
(PCIE1 & PCMSK14)
DI
PCINT15
PCINT14 -/- INT1
ADC9 -/- ISRC
PCINT13
PCINT12
AIO
RESET -/- ADC10 -/-
ADC8 -/- XTAL2
XTAL1 -/- CLKI
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Table 9-8.
Overriding Signals for Alternate Functions in PB3..PB0
Signal PB3/PCINT11/
PB2/PCINT10/
OC1AV/USCK/SCL
PB1/PCINT9/
OC1BU/DO
PB0/IPCINT8/
OC1AU/DI/SDA
Name
PUOE
PUOV
OC1BV
0
0
0
0
0
0
0
0
(USI_2_WIRE &
(USI_2_WIRE &
DDOE
0
0
USIPOS)
USIPOS)
(USI_SCL_HOLD |
(USI_SHIFTOUT |
DDOV
0
0
PORTB2)
& DDRB2
PORTB0) & DDRB0)
(USI_2_WIRE &
(USI_2_WIRE &
USI_3_WIRE &
(USI_2_WIRE &
OC1B_ENABLE
USIPOS &
DDRB2) |
(OC1A_ENABLE &
OC1AV)
USIPOS &
DDRB0) |
(OC1A_ENABLE &
OC1AU)
PVOE
PVOV
&
USIPOS) |
(OC1B_ENABLE &
OC1BU)
OC1BV
{ (USI_2_WIRE &
USI_3_WIRE &
{ (USI_2_WIRE &
{ (USI_2_WIRE &
USIPOS &
DDRB2) ?
(0) : (OC1A) }
USIPOS &
DDRB0) ?
(0) : (OC1A) }
OC1B
0
USIPOS) ?
(USI_SHIFTOUT) :
(OC1B) }
PTOE
USI_PTOE & USIPOS
0
0
PCIE1 &
PCMSK11
(USISIE & USIPOS) |
(PCIE1 & PCMSK10)
(USISIE & USIPOS) |
(PCIE1 & PCMSK8)
DIEOE
PCIE1 & PCMSK9
(USISIE & USIPOS) |
(PCIE1 & PCMSK10)
(USISIE & USIPOS) |
(PCIE1 & PCMSK8)
DIEOV
1
1
PCINT10 -/- USCK -/-
DI
PCINT11
0
PCINT9
0
PCINT8 -/- DI -/- SDA
SCL
AIO
0
0
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9.4
Register Description for I/O Ports
9.4.1
Port A Data Register – PORTA
Bit
7
PORTA7
R/W
6
PORTA6
R/W
5
PORTA5
R/W
4
PORTA4
R/W
3
PORTA3
R/W
2
PORTA2
R/W
1
PORTA1
R/W
0
PORTA0
R/W
PORTA
DDRA
PINA
Read/Write
Initial Value
0
0
0
0
0
0
0
0
9.4.2
9.4.3
9.4.4
9.4.5
9.4.6
Port A Data Direction Register – DDRA
Bit
7
DDA7
R/W
0
6
DDA6
R/W
0
5
DDA5
R/W
0
4
DDA4
R/W
0
3
DDA3
R/W
0
2
DDA2
R/W
0
1
DDA1
R/W
0
0
DDA0
R/W
0
Read/Write
Initial Value
Port A Input Pins Register – PINA
Bit
7
6
5
4
3
2
1
0
PINA7
R/(W)
N/A
PINA6
R/(W)
N/A
PINA5
R/(W)
N/A
PINA4
R/(W)
N/A
PINA3
R/(W)
N/A
PINA2
R/(W)
N/A
PINA1
R/(W)
N/A
PINA0
R/(W)
N/A
Read/Write
Initial Value
Port B Data Register – PORTB
Bit
7
6
PORTB6
R/W
5
PORTB5
R/W
4
PORTB4
R/W
3
PORTB3
R/W
2
PORTB2
R/W
1
PORTB1
R/W
0
PORTB0
R/W
PORTB7
PORTB
DDRB
PINB
Read/Write
Initial Value
R/W
0
0
0
0
0
0
0
0
Port B Data Direction Register – DDRB
Bit
7
DDB7
R/W
0
6
DDB6
R/W
0
5
DDB5
R/W
0
4
DDB4
R/W
0
3
DDB3
R/W
0
2
DDB2
R/W
0
1
DDB1
R/W
0
0
DDB0
R/W
0
Read/Write
Initial Value
Port B Input Pins Register – PINB
Bit
7
6
5
4
3
2
1
0
PINB7
R/(W)
N/A
PINB6
R/(W)
N/A
PINB5
R/(W)
N/A
PINB4
R/(W)
N/A
PINB3
R/(W)
N/A
PINB2
R/(W)
N/A
PINB1
R/(W)
N/A
PINB0
R/(W)
N/A
Read/Write
Initial Value
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10. 8-bit Timer/Counter0 and Asynchronous Operation
Timer/Counter0 is a general purpose, single channel, 8-bit Timer/Counter module. The main
features are:
10.1 Features
• Single Channel Counter
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Frequency Generator
• 10-bit Clock Prescaler
• Overflow and Compare Match Interrupt Sources (TOV0 and OCF0A)
• Allows Clocking from External Crystal (i.e. 32kHz Watch Crystal) Independent of the I/O Clock
10.2 Overview
Many register and bit references in this section are written in general form.
• A lower case “n” replaces the Timer/Counter number, in this case 0. However, when using
the register or bit defines in a program, the precise form must be used, i.e., TCNT0 for
accessing Timer/Counter0 counter value and so on.
• A lower case “x” replaces the Output Compare unit channel, in this case A. However, when
using the register or bit defines in a program, the precise form must be used, i.e., OCR0A
for accessing Timer/Counter0 output compare channel A value and so on.
A simplified block diagram of the 8-bit Timer/Counter is shown in Figure 10-1. For the actual
placement of I/O pins, refer to See Section 1.3 “Pin Configuration” on page 6. CPU accessible
I/O Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Regis-
ter and bit locations are listed in the “8-bit Timer/Counter Register Description” on page 103.
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Figure 10-1. 8-bit Timer/Counter0 Block Diagram
TCCRnx
count
clear
TOVn
(Int.Req.)
Control Logic
TOP
direction
clkTn
XTAL2
BOTTOM
Oscillator
Prescaler
XTAL1
Timer/Counter
TCNTn
= 0
= 0xFF
clk I/O
OCnx
(Int.Req.)
Waveform
Generation
OCnx
=
OCRnx
clk I/O
Synchronized Status flags
Synchronization Unit
clk ASY
Status flags
ASSRn
asynchronous mode
select (ASn)
The Timer/Counter (TCNT0) and Output Compare Register (OCR0A) are 8-bit registers. Inter-
rupt request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register
(TIFR0). All interrupts are individually masked with the Timer Interrupt Mask Register
(TIMSK0). TIFR0 and TIMSK0 are not shown in the figure.
The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked
from the XTAL1/2 pins, as detailed later in this section. The asynchronous operation is con-
trolled by the Asynchronous Status Register (ASSR). The Clock Select logic block controls
which clock source the Timer/Counter uses to increment (or decrement) its value. The
Timer/Counter is inactive when no clock source is selected. The output from the Clock Select
logic is referred to as the timer clock (clkT0).
The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter
value at all times. The result of the compare can be used by the Waveform Generator to gen-
erate a PWM or variable frequency output on the Output Compare pin (OC0A). See ”Output
Compare Unit” on page 93. for details. The compare match event will also set the compare
flag (OCF0A) which can be used to generate an Output Compare interrupt request.
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10.2.1
Definitions
The following definitions are used extensively throughout the section:
BOTTOM
MAX
The counter reaches the BOTTOM when it becomes zero (0x00).
The counter reaches its MAXimum when it becomes 0xFF (decimal 255).
TOP
The counter reaches the TOP when it becomes equal to the highest value in
the count sequence. The TOP value can be assigned to be the fixed value
0xFF (MAX) or the value stored in the OCR0A Register. The assignment is
dependent on the mode of operation.
10.3 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal synchronous or an external asynchronous
clock source. The clock source is selected by the clock select logic which is controlled by the
clock select (CS02:0) bits located in the Timer/Counter control register (TCCR0).The clock
source clkT0 is by default equal to the MCU clock, clkI/O. When the AS0 bit in the ASSR Regis-
ter is written to logic one, the clock source is taken from the Timer/Counter Oscillator
connected to XTAL1 and XTAL2 or directly from XTAL1. For details on asynchronous opera-
tion, see “Asynchronous Status Register – ASSR” on page 106. For details on clock sources
and prescaler, see “Timer/Counter0 Prescaler” on page 103.
10.4 Counter Unit
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Fig-
ure 10-2 shows a block diagram of the counter and its surrounding environment.
Figure 10-2. Counter Unit Block Diagram
TOVn
(Int.Req.)
DATA BUS
XTAL2
count
Oscillator
clk Tn
clkTnS
clear
TCNTn
Control Logic
Prescaler
direction
XTAL1
bottom
top
clk
I/O
Signal description (internal signals):
count
direction
clear
Increment or decrement TCNT0 by 1.
Selects between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter0 clock.
clkT0
top
Signalizes that TCNT0 has reached maximum value.
Signalizes that TCNT0 has reached minimum value (zero).
bottom
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Depending on the mode of operation used, the counter is cleared, incremented, or decre-
mented at each timer clock (clkT0). clkT0 can be generated from an external or internal clock
source, selected by the Clock Select bits (CS02:0). When no clock source is selected
(CS02:0 = 0) the timer is stopped. However, the TCNT0 value can be accessed by the CPU,
regardless of whether clkT0 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the WGM01 and WGM00 bits located
in the Timer/Counter Control Register (TCCR0A). There are close connections between how
the counter behaves (counts) and how waveforms are generated on the Output Compare out-
put OC0A. For more details about advanced counting sequences and waveform generation,
see “Modes of Operation” on page 95.
The Timer/Counter Overflow Flag (TOV0) is set according to the mode of operation selected
by the WGM01:0 bits. TOV0 can be used for generating a CPU interrupt.
10.5 Output Compare Unit
The 8-bit comparator continuously compares TCNT0 with the Output Compare Register
(OCR0A). Whenever TCNT0 equals OCR0A, the comparator signals a match. A match will set
the Output Compare Flag (OCF0A) at the next timer clock cycle. If enabled (OCIE0A = 1), the
Output Compare Flag generates an Output Compare interrupt. The OCF0A flag is automati-
cally cleared when the interrupt is executed. Alternatively, the OCF0A flag can be cleared by
software by writing a logical one to its I/O bit location. The Waveform Generator uses the
match signal to generate an output according to operating mode set by the WGM01:0 bits and
Compare Output mode (COM0A1:0) bits. The max and bottom signals are used by the Wave-
form Generator for handling the special cases of the extreme values in some modes of
operation (“Modes of Operation” on page 95).
Figure 10-3 shows a block diagram of the Output Compare unit.
Figure 10-3. Output Compare Unit, Block Diagram
DATA BUS
OCRnx
TCNTn
= (8-bit Comparator )
OCFnx (Int.Req.)
top
bottom
FOCn
Waveform Generator
OCnx
WGMn1:0
COMnX1:0
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The OCR0A Register is double buffered when using any of the Pulse Width Modulation
(PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the
double buffering is disabled. The double buffering synchronizes the update of the OCR0A
Compare Register to either top or bottom of the counting sequence. The synchronization pre-
vents the occurrence of odd-length, non-symmetrical PWM pulses, thereby making the output
glitch-free.
The OCR0A Register access may seem complex, but this is not case. When the double buff-
ering is enabled, the CPU has access to the OCR0A Buffer Register, and if double buffering is
disabled the CPU will access the OCR0A directly.
10.5.1
Force Output Compare
In non-PWM waveform generation modes, the match output of the comparator can be forced
by writing a one to the Force Output Compare (FOC0A) bit. Forcing compare match will not
set the OCF0A flag or reload/clear the timer, but the OC0A pin will be updated as if a real com-
pare match had occurred (the COM0A1:0 bits settings define whether the OC0A pin is set,
cleared or toggled).
10.5.2
10.5.3
Compare Match Blocking by TCNT0 Write
All CPU write operations to the TCNT0 Register will block any compare match that occurs in
the next timer clock cycle, even when the timer is stopped. This feature allows OCR0A to be
initialized to the same value as TCNT0 without triggering an interrupt when the Timer/Counter
clock is enabled.
Using the Output Compare Unit
Since writing TCNT0 in any mode of operation will block all compare matches for one timer
clock cycle, there are risks involved when changing TCNT0 when using the Output Compare
channel, independently of whether the Timer/Counter is running or not. If the value written to
TCNT0 equals the OCR0A value, the compare match will be missed, resulting in incorrect
waveform generation. Similarly, do not write the TCNT0 value equal to BOTTOM when the
counter is downcounting.
The setup of the OC0A should be performed before setting the Data Direction Register for the
port pin to output. The easiest way of setting the OC0A value is to use the Force Output Com-
pare (FOC0A) strobe bit in Normal mode. The OC0A Register keeps its value even when
changing between Waveform Generation modes.
Be aware that the COM0A1:0 bits are not double buffered together with the compare value.
Changing the COM0A1:0 bits will take effect immediately.
10.6 Compare Match Output Unit
The Compare Output mode (COM0A1:0) bits have two functions. The Waveform Generator
uses the COM0A1:0 bits for defining the Output Compare (OC0A) state at the next compare
match. Also, the COM0A1:0 bits control the OC0A pin output source. Figure 10-4 shows a
simplified schematic of the logic affected by the COM0A1:0 bit setting. The I/O Registers, I/O
bits, and I/O pins in the figure are shown in bold. Only the parts of the general I/O port control
registers (DDR and PORT) that are affected by the COM0A1:0 bits are shown. When referring
to the OC0A state, the reference is for the internal OC0A Register, not the OC0A pin.
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Figure 10-4. Compare Match Output Logic
COMnx1
Waveform
Generator
COMnx0
FOCnx
D
Q
1
0
OCnx
Pin
OCnx
D
Q
PORT
D
Q
DDR
clkI/O
10.6.1
Compare Output Function
The general I/O port function is overridden by the Output Compare (OC0A) from the Wave-
form Generator if either of the COM0A1:0 bits are set. However, the OC0A pin direction (input
or output) is still controlled by the Data Direction Register (DDR) for the port pin. The Data
Direction Register bit for the OC0A pin (DDR_OC0A) must be set as output before the OC0A
value is visible on the pin. The port override function is independent of the Waveform Genera-
tion mode.
The design of the Output Compare pin logic allows initialization of the OC0A state before the
output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of
operation. See ”8-bit Timer/Counter Register Description” on page 103.
10.6.2
Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM0A1:0 bits differently in normal, CTC, and PWM
modes. For all modes, setting the COM0A1:0 = 0 tells the Waveform Generator that no action
on the OC0A Register is to be performed on the next compare match. For compare output
actions in the non-PWM modes refer to Table 10-1 on page 104. For fast PWM mode, refer to
Table 10-2 on page 104, and for phase correct PWM refer to Table 10-3 on page 104.
A change of the COM0A1:0 bits state will have effect at the first compare match after the bits
are written. For non-PWM modes, the action can be forced to have immediate effect by using
the FOC0A strobe bits.
10.7 Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGM01:0) and Compare
Output mode (COM0A1:0) bits. The Compare Output mode bits do not affect the counting
sequence, while the Waveform Generation mode bits do. The COM0A1:0 bits control whether
the PWM output generated should be inverted or not (inverted or non-inverted PWM). For
non-PWM modes the COM0A1:0 bits control whether the output should be set, cleared, or tog-
gled at a compare match (See ”Compare Match Output Unit” on page 94.).
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For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 100.
10.7.1
Normal Mode
The simplest mode of operation is the Normal mode (WGM01:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 8-bit value (TOP = 0xFF) and then restarts from the bot-
tom (0x00). In normal operation the Timer/Counter Overflow Flag (TOV0) will be set in the
same timer clock cycle as the TCNT0 becomes zero. The TOV0 flag in this case behaves like
a ninth bit, except that it is only set, not cleared. However, combined with the timer overflow
interrupt that automatically clears the TOV0 flag, the timer resolution can be increased by soft-
ware. There are no special cases to consider in the Normal mode, a new counter value can be
written anytime.
The Output Compare unit can be used to generate interrupts at some given time. Using the
Output Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
10.7.2
Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM01:0 = 2), the OCR0A Register is used to
manipulate the counter resolution. In CTC mode the counter is cleared to zero when the coun-
ter value (TCNT0) matches the OCR0A. The OCR0A defines the top value for the counter,
hence also its resolution. This mode allows greater control of the compare match output fre-
quency. It also simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 10-5. The counter value (TCNT0)
increases until a compare match occurs between TCNT0 and OCR0A, and then counter
(TCNT0) is cleared.
Figure 10-5. CTC Mode, Timing Diagram
OCnx Interrupt Flag Set
TCNTn
OCnx
(Toggle)
(COMnx1:0 = 1)
1
2
3
4
Period
An interrupt can be generated each time the counter value reaches the TOP value by using
the OCF0A flag. If the interrupt is enabled, the interrupt handler routine can be used for updat-
ing the TOP value. However, changing the TOP to a value close to BOTTOM when the
counter is running with none or a low prescaler value must be done with care since the CTC
mode does not have the double buffering feature. If the new value written to OCR0A is lower
than the current value of TCNT0, the counter will miss the compare match. The counter will
then have to count to its maximum value (0xFF) and wrap around starting at 0x00 before the
compare match can occur.
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For generating a waveform output in CTC mode, the OC0A output can be set to toggle its log-
ical level on each compare match by setting the Compare Output mode bits to toggle mode
(COM0A1:0 = 1). The OC0A value will not be visible on the port pin unless the data direction
for the pin is set to output. The waveform generated will have a maximum frequency of
fOC0A = fclk_I/O/2 when OCR0A is set to zero (0x00). The waveform frequency is defined by the
following equation:
f
clk_I/O
f
= ------------------------------------------------------
OCnx
2
N
(1 + OCRnx)
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
As for the Normal mode of operation, the TOV0 flag is set in the same timer clock cycle that
the counter counts from MAX to 0x00.
10.7.3
Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM01:0 = 3) provides a high frequency
PWM waveform generation option. The fast PWM differs from the other PWM option by its sin-
gle-slope operation. The counter counts from BOTTOM to MAX then restarts from BOTTOM.
In non-inverting Compare Output mode, the Output Compare (OC0A) is cleared on the com-
pare match between TCNT0 and OCR0A, and set at BOTTOM. In inverting Compare Output
mode, the output is set on compare match and cleared at BOTTOM. Due to the single-slope
operation, the operating frequency of the fast PWM mode can be twice as high as the phase
correct PWM mode that uses dual-slope operation. This high frequency makes the fast PWM
mode well suited for power regulation, rectification, and DAC applications. High frequency
allows physically small sized external components (coils, capacitors), and therefore reduces
total system cost.
In fast PWM mode, the counter is incremented until the counter value matches the MAX value.
The counter is then cleared at the following timer clock cycle. The timing diagram for the fast
PWM mode is shown in Figure 10-6. The TCNT0 value is in the timing diagram shown as a
histogram for illustrating the single-slope operation. The diagram includes non-inverted and
inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent com-
pare matches between OCR0A and TCNT0.
Figure 10-6. Fast PWM Mode, Timing Diagram
OCRnx Interrupt Flag Set
OCRnx Update and
TOVn Interrupt Flag Set
TCNTn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCnx
OCnx
1
2
3
4
5
6
7
Period
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The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the
interrupt is enabled, the interrupt handler routine can be used for updating the compare value.
In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0A pin.
Setting the COM0A1:0 bits to two will produce a non-inverted PWM and an inverted PWM out-
put can be generated by setting the COM0A1:0 to three (See Table 10-2 on page 104). The
actual OC0A value will only be visible on the port pin if the data direction for the port pin is set
as output. The PWM waveform is generated by setting (or clearing) the OC0A Register at the
compare match between OCR0A and TCNT0, and clearing (or setting) the OC0A Register at
the timer clock cycle the counter is cleared (changes from MAX to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f
clk_I/O
f
= --------------------
OCnxPWM
N
256
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the fast PWM mode. If the OCR0A is set equal to BOTTOM, the output will
be a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0A equal to MAX will
result in a constantly high or low output (depending on the polarity of the output set by the
COM0A1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by
setting OC0A to toggle its logical level on each compare match (COM0A1:0 = 1). The wave-
form generated will have a maximum frequency of foc0A = fclk_I/O/2 when OCR0A is set to zero.
This feature is similar to the OC0A toggle in CTC mode, except the double buffer feature of the
Output Compare unit is enabled in the fast PWM mode.
10.7.4
Phase Correct PWM Mode
The phase correct PWM mode (WGM01:0 = 1) provides a high resolution phase correct PWM
waveform generation option. The phase correct PWM mode is based on a dual-slope opera-
tion. The counter counts repeatedly from BOTTOM to MAX and then from MAX to BOTTOM.
In non-inverting Compare Output mode, the Output Compare (OC0A) is cleared on the com-
pare match between TCNT0 and OCR0A while upcounting, and set on the compare match
while downcounting. In inverting Output Compare mode, the operation is inverted. The
dual-slope operation has lower maximum operation frequency than single slope operation.
However, due to the symmetric feature of the dual-slope PWM modes, these modes are pre-
ferred for motor control applications.
The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct
PWM mode the counter is incremented until the counter value matches MAX. When the coun-
ter reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for
one timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Fig-
ure 10-7. The TCNT0 value is in the timing diagram shown as a histogram for illustrating the
dual-slope operation. The diagram includes non-inverted and inverted PWM outputs. The
small horizontal line marks on the TCNT0 slopes represent compare matches between
OCR0A and TCNT0.
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Figure 10-7. Phase Correct PWM Mode, Timing Diagram
OCnx Interrupt Flag Set
OCRnx Update
TOVn Interrupt Flag Set
TCNTn
(COMnx1:0 = 2)
(COMnx1:0 = 3)
OCnx
OCnx
1
2
3
Period
The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The
interrupt flag can be used to generate an interrupt each time the counter reaches the BOT-
TOM value.
In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the
OC0A pin. Setting the COM0A1:0 bits to two will produce a non-inverted PWM. An inverted
PWM output can be generated by setting the COM0A1:0 to three (See Table 10-3 on page
104). The actual OC0A value will only be visible on the port pin if the data direction for the port
pin is set as output. The PWM waveform is generated by clearing (or setting) the OC0A Regis-
ter at the compare match between OCR0A and TCNT0 when the counter increments, and
setting (or clearing) the OC0A Register at compare match between OCR0A and TCNT0 when
the counter decrements. The PWM frequency for the output when using phase correct PWM
can be calculated by the following equation:
f
clk_I/O
f
= --------------------
OCnxPCPWM
N
510
The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
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10.8 Timer/Counter Timing Diagrams
The following figures show the Timer/Counter in synchronous mode, and the timer clock
(clkT0) is therefore shown as a clock enable signal. In asynchronous mode, clkI/O should be
replaced by the Timer/Counter Oscillator clock. The figures include information on when inter-
rupt flags are set. Figure 10-8 contains timing data for basic Timer/Counter operation. The
figure shows the count sequence close to the MAX value in all modes other than phase correct
PWM mode.
Figure 10-8. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn
(clkI/O/1)
TCNTn
TOVn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
Figure 10-9 shows the same timing data, but with the prescaler enabled.
Figure 10-9. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
TOVn
MAX - 1
MAX
BOTTOM
BOTTOM + 1
Figure 10-10 shows the setting of OCF0A in all modes except CTC mode.
Figure 10-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
OCRnx
OCFnx
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
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Figure 10-11 shows the setting of OCF0A and the clearing of TCNT0 in CTC mode.
Figure 10-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with
Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
(CTC)
TOP - 1
TOP
BOTTOM
BOTTOM + 1
OCRnx
TOP
OCFnx
10.9 Asynchronous Operation of Timer/Counter0
When Timer/Counter0 operates asynchronously, some considerations must be taken.
• Warning: When switching between asynchronous and synchronous clocking of
Timer/Counter0, the timer registers TCNT0, OCR0A, and TCCR0A might be corrupted. A
safe procedure for switching clock source is:
a. Disable the Timer/Counter0 interrupts by clearing OCIE0A and TOIE0.
b. Select clock source by setting AS0 and EXCLK as appropriate.
c. Write new values to TCNT0, OCR0A, and TCCR0A.
d. To switch to asynchronous operation: Wait for TCN0UB, OCR0UB, and TCR0UB.
e. Clear the Timer/Counter0 interrupt flags.
f. Enable interrupts, if needed.
• If an 32.768kHz watch crystal is used, the CPU main clock frequency must be more than
four times the Oscillator or external clock frequency.
• When writing to one of the registers TCNT0, OCR0A, or TCCR0A, the value is transferred
to a temporary register, and latched after two positive edges on TOSC1. The user should
not write a new value before the contents of the temporary register have been transferred
to its destination. Each of the three mentioned registers have their individual temporary
register, which means that e.g. writing to TCNT0 does not disturb an OCR0A write in
progress. To detect that a transfer to the destination register has taken place, the
Asynchronous Status Register – ASSR has been implemented.
• When entering Power-save mode after having written to TCNT0, OCR0A, or TCCR0A, the
user must wait until the written register has been updated if Timer/Counter0 is used to
wake up the device. Otherwise, the MCU will enter sleep mode before the changes are
effective. This is particularly important if the Output Compare0 interrupt is used to wake up
the device, since the Output Compare function is disabled during writing to OCR0A or
TCNT0. If the write cycle is not finished, and the MCU enters sleep mode before the
OCR0UB bit returns to zero, the device will never receive a compare match interrupt, and
the MCU will not wake up.
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• If Timer/Counter0 is used to wake the device up from Power-save mode, precautions must
be taken if the user wants to re-enter one of these modes: The interrupt logic needs one
TOSC1 cycle to be reset. If the time between wake-up and re-entering sleep mode is less
than one TOSC1 cycle, the interrupt will not occur, and the device will fail to wake up. If the
user is in doubt whether the time before re-entering Power-save mode is sufficient, the
following algorithm can be used to ensure that one TOSC1 cycle has elapsed:
a. Write a value to TCCR0A, TCNT0, or OCR0A.
b. Wait until the corresponding Update Busy flag in ASSR returns to zero.
c. Enter Power-save or ADC Noise Reduction mode.
• When the asynchronous operation is selected, the oscillator for Timer/Counter0 is always
running, except in Power-down mode. After a Power-up Reset or wake-up from
Power-down mode, the user should be aware of the fact that this oscillator might take as
long as one second to stabilize. The user is advised to wait for at least one second before
using Timer/Counter0 after power-up or wake-up from Power-down mode. The contents of
all Timer/Counter0 Registers must be considered lost after a wake-up from Power-down
mode due to unstable clock signal upon start-up, no matter whether the oscillator is in use
or a clock signal is applied to the XTAL1 pin.
• Description of wake up from Power-save mode when the timer is clocked asynchronously:
When the interrupt condition is met, the wake up process is started on the following cycle of
the timer clock, that is, the timer is always advanced by at least one before the processor
can read the counter value. After wake-up, the MCU is halted for four cycles, it executes
the interrupt routine, and resumes execution from the instruction following SLEEP.
• Reading of the TCNT0 Register shortly after wake-up from Power-save may give an
incorrect result. Since TCNT0 is clocked on the asynchronous clock, reading TCNT0 must
be done through a register synchronized to the internal I/O clock domain (CPU main clock).
Synchronization takes place for every rising XTAL1 edge. When waking up from
Power-save mode, and the I/O clock (clkI/O) again becomes active, TCNT0 will read as the
previous value (before entering sleep) until the next rising XTAL1 edge. The phase of the
XTAL1 clock after waking up from Power-save mode is essentially unpredictable, as it
depends on the wake-up time. The recommended procedure for reading TCNT0 is thus as
follows:
a. Write any value to either of the registers OCR0A or TCCR0A.
b. Wait for the corresponding Update Busy Flag to be cleared.
c. Read TCNT0.
• During asynchronous operation, the synchronization of the interrupt flags for the
asynchronous timer takes 3 processor cycles plus one timer cycle. The timer is therefore
advanced by at least one before the processor can read the timer value causing the setting
of the interrupt flag. The Output Compare pin is changed on the timer clock and is not
synchronized to the processor clock.
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10.10 Timer/Counter0 Prescaler
Figure 10-12. Prescaler for Timer/Counter0
clkI/O
XTAL2
0
1
clkTnS
Oscillator
10-BIT T/C PRESCALER
0
Clear
XTAL1
1
EXCLK
ASn
0
PSRn
CSn0
CSn1
CSn2
TIMER/COUNTERn CLOCK SOURCE
clkTn
The clock source for Timer/Counter0 is named clkT0S. clkT0S is by default connected to the
main system I/O clock clkIO. By setting the AS0 bit in ASSR, Timer/Counter0 is asynchro-
nously clocked from the XTAL oscillator or XTAL1 pin. This enables use of Timer/Counter0 as
a Real Time Counter (RTC).
A crystal can then be connected between the XTAL1 and XTAL2 pins to serve as an indepen-
dent clock source for Timer/Counter0.
A external clock can also be used using XTAL1 as input. Setting AS0 and EXCLK enables this
configuration.
For Timer/Counter0, the possible prescaled selections are: clkT0S/8, clkT0S/32, clkT0S/64,
clkT0S/128, clkT0S/256, and clkT0S/1024. Additionally, clkT0S as well as 0 (stop) may be
selected. Setting the PSR0 bit in GTCCR resets the prescaler. This allows the user to operate
with a predictable prescaler.
10.11 8-bit Timer/Counter Register Description
• Timer/Counter0 Control Register A – TCCR0A
Bit
7
6
5
–
4
–
3
–
2
–
1
WGM01
R/W
0
0
WGM00
R/W
0
COM0A1 COM0A0
TCCR0A
Read/Write
Initial Value
R/W
0
R/W
0
R
0
R
0
R
0
R
0
• Bit 7:6 – COM0A1:0: Compare Match Output Mode A
These bits control the Output Compare pin (OC0A) behavior. If one or both of the COM0A1:0
bits are set, the OC0A output overrides the normal port functionality of the I/O pin it is con-
nected to. However, note that the Data Direction Register (DDR) bit corresponding to OC0A
pin must be set in order to enable the output driver.
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When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the
WGM01:0 bit setting. Table 10-1 shows the COM0A1:0 bit functionality when the WGM01:0
bits are set to a normal or CTC mode (non-PWM).
Table 10-1. Compare Output Mode, non-PWM Mode
COM0A1
COM0A0
Description
0
0
1
1
0
1
0
1
Normal port operation, OC0A disconnected.
Toggle OC0A on Compare Match.
Clear OC0A on Compare Match.
Set OC0A on Compare Match.
Table 10-2 shows the COM0A1:0 bit functionality when the WGM01:0 bits are set to fast PWM
mode.
Table 10-2. Compare Output Mode, Fast PWM Mode(1)
COM0A1
COM0A0
Description
0
0
0
1
Normal port operation, OC0A disconnected.
Clear OC0A on Compare Match.
1
1
0
1
Set OC0A at BOTTOM (non-inverting mode).
Set OC0A on Compare Match.
Clear OC0A at BOTTOM (inverting mode).
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Fast PWM Mode” on page
97 for more details.
Table 10-3 shows the COM01:0 bit functionality when the WGM01:0 bits are set to phase cor-
rect PWM mode.
Table 10-3. Compare Output Mode, Phase Correct PWM Mode(1)
COM0A1
COM0A0
Description
0
0
0
1
Normal port operation, OC0A disconnected.
Clear OC0A on Compare Match when up-counting.
Set OC0A on Compare Match when down-counting.
1
1
0
1
Set OC0A on Compare Match when up-counting.
Clear OC0A on Compare Match when down-counting.
Note:
1. A special case occurs when OCR0A equals TOP and COM0A1 is set. In this case, the Com-
pare Match is ignored, but the set or clear is done at TOP. See “Phase Correct PWM Mode”
on page 98 for more details.
• Bit 5:2 – Res: Reserved Bits
These bits are reserved in the Atmel® AVR® and will always read as zero.
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• Bit 6, 3 – WGM01:0: Waveform Generation Mode
These bits control the counting sequence of the counter, the source for the maximum (TOP)
counter value, and what type of waveform generation to be used, see Table 10-4. Modes of
operation supported by the Timer/Counter unit are: Normal mode (Counter), Clear Timer on
Compare match (CTC) mode, and two types of Pulse Width Modulation (PWM) modes (See
”Modes of Operation” on page 95.).
Table 10-4. Waveform Generation Mode Bit Description
WGM01
(CTC0)
WGM00
(PWM0)
Timer/Counter
Mode of Operation
Update of
OCR0A at
TOV0 Flag
Set on(1)(2)
Mode
TOP
0
1
2
3
0
0
1
1
0
1
0
1
Normal
0xFF
0xFF
OCR0A
0xFF
Immediate
TOP
MAX
PWM, Phase Correct
CTC
BOTTOM
MAX
Immediate
TOP
Fast PWM
MAX
Notes: 1. MAX = 0xFF,
2. BOTTOM = 0x00.
10.11.1 Timer/Counter0 Control Register B – TCCR0B
Bit
7
FOC0A
W
6
–
5
–
4
–
3
–
2
CS02
R/W
0
1
CS01
R/W
0
0
CS00
R/W
0
TCCR0B
Read/Write
Initial Value
R
0
R
0
R
0
R
0
0
• Bit 7 – FOC0A: Force Output Compare A
The FOC0A bit is only active when the WGM bits specify a non-PWM mode.
However, for ensuring compatibility with future devices, this bit must be set to zero when
TCCR0B is written when operating in PWM mode. When writing a logical one to the FOC0A
bit, an immediate Compare Match is forced on the Waveform Generation unit. The OC0A out-
put is changed according to its COM0A1:0 bits setting. Note that the FOC0A bit is
implemented as a strobe. Therefore it is the value present in the COM0A1:0 bits that deter-
mines the effect of the forced compare.
A FOC0A strobe will not generate any interrupt, nor will it clear the timer in CTC mode using
OCR0A as TOP.
The FOC0A bit is always read as zero.
• Bit 6:3 – Res: Reserved Bits
These bits are reserved in the Atmel® AVR® and will always read as zero.
• Bit 2:0 – CS02:0: Clock Select
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The three Clock Select bits select the clock source to be used by the Timer/Counter, see
Table 10-5.
Table 10-5. Clock Select Bit Description
CS02
CS01
CS00
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No clock source (Timer/Counter stopped).
clkT0S (No prescaling)
clkT0S/8 (From prescaler)
clkT0S/32 (From prescaler)
clkT0S/64 (From prescaler)
clkT0S/128 (From prescaler)
clkT0S/256 (From prescaler)
clkT0S/1024 (From prescaler)
10.11.2 Timer/Counter0 Register – TCNT0
Bit
7
6
TCNT06
R/W
0
5
TCNT05
R/W
0
4
TCNT04
R/W
0
3
TCNT03
R/W
0
2
TCNT02
R/W
0
1
TCNT01
R/W
0
0
TCNT00
R/W
0
TCNT07
R/W
0
TCNT0
Read/Write
Initial Value
The Timer/Counter Register gives direct access, both for read and write operations, to the
Timer/Counter unit 8-bit counter. Writing to the TCNT0 Register blocks (removes) the Com-
pare Match on the following timer clock. Modifying the counter (TCNT0) while the counter is
running, introduces a risk of missing a Compare Match between TCNT0 and the OCR0x
Register.
10.11.3 Output Compare Register A – OCR0A
Bit
7
6
5
4
OCR0A4
R/W
3
OCR0A3
R/W
2
OCR0A2
R/W
1
OCR0A1
R/W
0
OCR0A0
R/W
OCR0A7
R/W
0
OCR0A6 OCR0A5
R/W
0
OCR0A
Read/Write
Initial Value
R/W
0
0
0
0
0
0
The Output Compare Register A contains an 8-bit value that is continuously compared with
the counter value (TCNT0). A match can be used to generate an Output Compare interrupt, or
to generate a waveform output on the OC0A pin.
10.11.4 Asynchronous Status Register – ASSR
Bit
7
6
EXCLK
R/W
0
5
4
3
2
–
1
0
–
R
0
AS0
R/W
0
TCN0UB
OCR0AUB
TCR0AUB TCR0BUB
ASSR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
• Bit 7 – Res: Reserved Bit
This bit is reserved in the Atmel® AVR® and will always read as zero.
• Bit 6 – EXCLK: Enable External Clock Input
When EXCLK is written to one, and asynchronous clock is selected, the external clock input
buffer is enabled and an external clock can be input on XTAL1 pin instead of an external crys-
tal. Writing to EXCLK should be done before asynchronous operation is selected. Note that
the crystal oscillator will only run when this bit is zero.
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• Bit 5 – AS0: Asynchronous Timer/Counter0
When AS0 is written to zero, Timer/Counter0 is clocked from the I/O clock, clkI/O and the
Timer/Counter0 acts as a synchronous peripheral.
When AS0 is written to one, Timer/Counter0 is clocked from the low-frequency crystal oscilla-
tor (See ”Low-frequency Crystal Oscillator” on page 33.) or from external clock on XTAL1 pin
(See ”External Clock” on page 34.) depending on EXCLK setting. When the value of AS0 is
changed, the contents of TCNT0, OCR0A, and TCCR0A might be corrupted.
AS0 also acts as a flag: Timer/Counter0 is clocked from the low-frequency crystal or from
external clock ONLY IF the calibrated internal RC oscillator or the internal watchdog oscillator
is used to drive the system clock. After setting AS0, if the switching is available, AS0 remains
to 1, else it is forced to 0.
• Bit 4 – TCN0UB: Timer/Counter0 Update Busy
When Timer/Counter0 operates asynchronously and TCNT0 is written, this bit becomes set.
When TCNT0 has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCNT0 is ready to be updated with a new
value.
• Bit 3 – OCR0AUB: Output Compare 0 Register A Update Busy
When Timer/Counter0 operates asynchronously and OCR0A is written, this bit becomes set.
When OCR0A has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that OCR0A is ready to be updated with a new
value.
• Bit 2 – Res: Reserved Bit
This bit is reserved in the Atmel® AVR® and will always read as zero.
• Bit 1 – TCR0AUB: Timer/Counter0 Control Register A Update Busy
When Timer/Counter0 operates asynchronously and TCCR0A is written, this bit becomes set.
When TCCR0A has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR0A is ready to be updated with a new
value.
• Bit 0 – TCR0BUB: Timer/Counter0 Control Register B Update Busy
When Timer/Counter0 operates asynchronously and TCCR0B is written, this bit becomes set.
When TCCR0B has been updated from the temporary storage register, this bit is cleared by
hardware. A logical zero in this bit indicates that TCCR0B is ready to be updated with a new
value.
If a write is performed to any of the four Timer/Counter0 Registers while its update busy flag is
set, the updated value might get corrupted and cause an unintentional interrupt to occur.
The mechanisms for reading TCNT0, OCR0A, TCCR0A and TCCR0B are different. When
reading TCNT0, the actual timer value is read. When reading OCR0A, TCCR0A or TCCR0B
the value in the temporary storage register is read.
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10.11.5 Timer/Counter0 Interrupt Mask Register – TIMSK0
Bit
7
–
6
–
5
–
4
–
3
–
2
–
1
OCIE0A
R/W
0
0
TOIE0
R/W
0
TIMSK0
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
• Bit 7:2 – Res: Reserved Bits
These bits are reserved in the Atmel® AVR® and will always read as zero.
• Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable
When the OCIE0A bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter0 Compare Match A interrupt is enabled. The corresponding interrupt is exe-
cuted if a compare match in Timer/Counter0 occurs, i.e., when the OCF0A bit is set in the
Timer/Counter0 Interrupt Flag Register – TIFR0.
• Bit 0 – TOIE0: Timer/Counter0 Overflow Interrupt Enable
When the TOIE0 bit is written to one and the I-bit in the Status Register is set (one), the
Timer/Counter0 Overflow interrupt is enabled. The corresponding interrupt is executed if an
overflow in Timer/Counter0 occurs, i.e., when the TOV0 bit is set in the Timer/Counter0 Inter-
rupt Flag Register – TIFR0.
10.11.6 Timer/Counter0 Interrupt Flag Register – TIFR0
Bit
7
6
5
–
4
–
3
–
2
–
1
OCF0A
R/W
0
0
TOV0
R/W
0
–
–
TIFR0
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
• Bit 7:2 – Res: Reserved Bits
These bits are reserved in the Atmel AVR and will always read as zero.
• Bit 1 – OCF0A: Output Compare Flag 0 A
The OCF0A bit is set (one) when a compare match occurs between the Timer/Counter0 and
the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when exe-
cuting the corresponding interrupt handling vector. Alternatively, OCF0A is cleared by writing a
logic one to the flag. When the I-bit in SREG, OCIE0 (Timer/Counter0 Compare match Inter-
rupt Enable), and OCF0A are set (one), the Timer/Counter0 Compare match Interrupt is
executed.
• Bit 0 – TOV0: Timer/Counter0 Overflow Flag
The TOV0 bit is set (one) when an overflow occurs in Timer/Counter0. TOV0 is cleared by
hardware when executing the corresponding interrupt handling vector. Alternatively, TOV0 is
cleared by writing a logic one to the flag. When the SREG I-bit, TOIE0A (Timer/Counter0
Overflow Interrupt Enable), and TOV0 are set (one), the Timer/Counter0 Overflow interrupt is
executed. In PWM mode, this bit is set when Timer/Counter0 changes counting direction at
0x00.
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10.11.7 General Timer/Counter Control Register – GTCCR
Bit
7
6
–
5
–
4
–
3
–
2
–
1
PSR0
R/W
0
0
PSR1
R/W
0
TSM
R/W
0
GTCCR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
• Bit 1 – PSR0: Prescaler Reset Timer/Counter0
When this bit is one, the Timer/Counter0 prescaler will be reset. This bit is normally cleared
immediately by hardware. If the bit is written when Timer/Counter0 is operating in asynchro-
nous mode, the bit will remain one until the prescaler has been reset. The bit will not be
cleared by hardware if the TSM bit is set. Refer to the description of the “Bit 7 – TSM:
Timer/Counter Synchronization Mode” on page 112 for a description of the Timer/Counter
Synchronization mode.
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11. Timer/Counter1 Prescaler
11.1 Overview
Most bit references in this section are written in general form. A lower case “n” replaces the
Timer/Counter number.
11.1.1
11.1.2
Internal Clock Source
The Timer/Counter can be clocked directly by the system clock (by setting the CSn2:0 = 1).
This provides the fastest operation, with a maximum Timer/Counter clock frequency equal to
system clock frequency (f
). Alternatively, one of four taps from the prescaler can be
CLK_I/O
used as a clock source. The prescaled clock has a frequency of either f
/8, f
/64,
CLK_I/O
CLK_I/O
f
/256, or f
/1024.
CLK_I/O
CLK_I/O
Prescaler Reset
The prescaler is free running, i.e., operates independently of the Clock Select logic of the
Timer/Counter. Since the prescaler is not affected by the Timer/Counter’s clock select, the
state of the prescaler will have implications for situations where a prescaled clock is used. One
example of prescaling artifacts occurs when the timer is enabled and clocked by the prescaler
(6 > CSn2:0 > 1). The number of system clock cycles from when the timer is enabled to the
first count occurs can be from 1 to N+1 system clock cycles, where N equals the prescaler
divisor (8, 64, 256, or 1024).
It is possible to use the prescaler reset for synchronizing the Timer/Counter to program execu-
tion. However, care must be taken if the other Timer/Counter that shares the same prescaler
also uses prescaling. A prescaler reset will affect the prescaler period for all Timer/Counters it
is connected to.
11.1.3
External Clock Source
An external clock source applied to the T1 pin can be used as Timer/Counter clock (clk 1).
T
The T1 pin is sampled once every system clock cycle by the pin synchronization logic. The
synchronized (sampled) signal is then passed through the edge detector. Figure 11-1 shows a
functional equivalent block diagram of the T1 synchronization and edge detector logic. The
registers are clocked at the positive edge of the internal system clock (clkI/O). The latch is
transparent in the high period of the internal system clock.
The edge detector generates one clk pulse for each positive (CSn2:0 = 7) or negative
T1
(CSn2:0 = 6) edge it detects.
Figure 11-1. T1 Pin Sampling
Tn_sync
(To Clock
Tn
D
Q
D
Q
D
Q
Select Logic)
LE
clkI/O
Synchronization
Edge Detector
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The synchronization and edge detector logic introduces a delay of 2.5 to 3.5 system clock
cycles from an edge has been applied to the T1 pin to the counter is updated.
Enabling and disabling of the clock input must be done when T1 has been stable for at least
one system clock cycle, otherwise it is a risk that a false Timer/Counter clock pulse is
generated.
Each half period of the external clock applied must be longer than one system clock cycle to
ensure correct sampling. The external clock must be guaranteed to have less than half the
system clock frequency (f
< f
/2) given a 50/50 % duty cycle. Since the edge detec-
ExtClk
clk_I/O
tor uses sampling, the maximum frequency of an external clock it can detect is half the
sampling frequency (Nyquist sampling theorem). However, due to variation of the system
clock frequency and duty cycle caused by Oscillator source (crystal, resonator, and capaci-
tors) tolerances, it is recommended that maximum frequency of an external clock source is
less than f
/2.5.
clk_I/O
An external clock source can not be prescaled.
Figure 11-2. Prescaler for Timer/Counter1 (1)
CLKI/O
10-BIT T/C PRESCALER
Clear
PSRn
0
Tn
Synchronization
CSn0
CSn1
CSn2
clkTn
TIMER/COUNTERn CLOCK SOURCE
Note:
1. The synchronization logic on the input pin (T1) is shown in Figure 11-1.
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11.2 Timer/Counter1 Prescalers Register Description
11.2.1
General Timer/Counter Control Register – GTCCR
Bit
7
TSM
R
6
–
5
–
4
–
3
–
2
–
1
PSR0
R/W
0
0
PSR1
R/W
0
GTCCR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
0
• Bit 7 – TSM: Timer/Counter Synchronization Mode
Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode,
the value that is written to the PSR0 and PSR1 bits is kept, hence keeping the corresponding
prescaler reset signals asserted. This ensures that the corresponding Timer/Counters are
halted and can be configured to the same value without the risk of one of them advancing dur-
ing configuration. When the TSM bit is written to zero, the PSR0 and PSR1 bits are cleared by
hardware, and the Timer/Counters start counting simultaneously.
• Bit 0 – PSR1: Prescaler Reset Timer/Counter1
When this bit is one, Timer/Counter1 prescaler will be reset. This bit is normally cleared imme-
diately by hardware, except if the TSM bit is set.
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12. 16-bit Timer/Counter1
The 16-bit Timer/Counter unit allows accurate program execution timing (event management),
wave generation, and signal timing measurement. The main features are:
12.1 Features
• True 16-bit Design (i.e., Allows 16-bit PWM)
• Two independent Output Compare Units
• Four Controlled Output Pins per Output Compare Unit
• Double Buffered Output Compare Registers
• One Input Capture Unit
• Input Capture Noise Canceler
• Clear Timer on Compare Match (Auto Reload)
• Glitch-free, Phase Correct Pulse Width Modulator (PWM)
• Variable PWM Period
• Frequency Generator
• External Event Counter
• Four independent interrupt Sources (TOV1, OCF1A, OCF1B, and ICF1)
12.2 Overview
Many register and bit references in this section are written in general form.
• A lower case “n” replaces the Timer/Counter number, in this case 1. However, when using
the register or bit defines in a program, the precise form must be used, i.e., TCNT1 for
accessing Timer/Counter1 counter value and so on.
• A lower case “x” replaces the Output Compare unit channel, in this case A or B. However,
when using the register or bit defines in a program, the precise form must be used, i.e.,
OCR1A for accessing Timer/Counter1 output compare channel A value and so on.
• A lower case “i” replaces the index of the Output Compare output pin, in this case U, V, W
or X. However, when using the register or bit defines in a program, the precise form must
be used.
A simplified block diagram of the 16-bit Timer/Counter is shown in Figure 12-1. For the actual
placement of I/O pins, refer to “Pin Configuration” on page 6. CPU accessible I/O Registers,
including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit
locations are listed in the “16-bit Timer/Counter Register Description” on page 135.
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Figure 12-1. 16-bit Timer/Counter1 Block Diagram(1)
Count
TOVn
(Int.Req.)
Clear
Control Logic
Direction
clkTn
Clock Select
Edge
Detector
Tn
TOP
BOTTOM
( From Prescaler )
Timer/Counter
TCNTn
=
=
0
OCFnA
(Int.Req.)
Waveform
Generation
OCnAU
OCnAV
OCnAW
OCnAX
=
OCRnA
Fixed
TOP
Values
OCFnB
(Int.Req.)
Waveform
Generation
OCnBU
OCnBV
OCnBW
OCnBX
=
OCRnB
( From Analog Comparator Ouput )
ICFn (Int.Req.)
Edge
Detector
Noise
Canceler
ICPn
ICRn
TCCRnA
TCCRnB
TCCRnC
Note:
1. Refer to Figure 1-1 on page 4, Table 9-6 on page 84, and Table 9-3 on page 79 for
Timer/Counter1 pin placement and description.
12.2.1
Registers
The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Reg-
ister (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the
16-bit registers. These procedures are described in the section “Accessing 16-bit Registers”
on page 115. The Timer/Counter Control Registers (TCCR1A/B) are 8-bit registers and have
no CPU access restrictions. Interrupt requests (abbreviated to Int.Req. in the figure) signals
are all visible in the Timer Interrupt Flag Register (TIFR1). All interrupts are individually
masked with the Timer Interrupt Mask Register (TIMSK1). TIFR1 and TIMSK1 are not shown
in the figure.
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The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source
on the Tn pin. The Clock Select logic block controls which clock source and edge the
Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inactive when
no clock source is selected. The output from the Clock Select logic is referred to as the timer
clock (clk ).
n
T
The double buffered Output Compare Registers (OCR1A/B) are compared with the
Timer/Counter value at all time. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins See
”Output Compare Units” on page 122.. The compare match event will also set the Compare
Match Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request.
The Input Capture Register can capture the Timer/Counter value at a given external (edge
triggered) event on either the Input Capture pin (ICP1) or on the Analog Comparator pins (See
”AnaComp - Analog Comparator” on page 222.). The Input Capture unit includes a digital filter-
ing unit (Noise Canceler) for reducing the chance of capturing noise spikes.
The TOP value, or maximum Timer/Counter value, can in some modes of operation be
defined by either the OCR1A Register, the ICR1 Register, or by a set of fixed values. When
using OCR1A as TOP value in a PWM mode, the OCR1A Register can not be used for gener-
ating a PWM output. However, the TOP value will in this case be double buffered allowing the
TOP value to be changed in run time. If a fixed TOP value is required, the ICR1 Register can
be used as an alternative, freeing the OCR1A to be used as PWM output.
12.2.2
Definitions
The following definitions are used extensively throughout the section:
BOTTOM The counter reaches the BOTTOM when it becomes 0x0000.
MAX
TOP
The counter reaches its MAXimum when it becomes 0xFFFF (decimal 65,535).
The counter reaches the TOP when it becomes equal to the highest value in
the count sequence. The TOP value can be assigned to be one of the fixed val-
ues: 0x00FF, 0x01FF, or 0x03FF, or to the value stored in the OCR1A or ICR1
Register. The assignment is dependent of the mode of operation.
12.3 Accessing 16-bit Registers
The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the Atmel®
AVR® CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or
write operations. Each 16-bit timer has a single 8-bit register for temporary storing of the high
byte of the 16-bit access. The same temporary register is shared between all 16-bit registers
within each 16-bit timer. Accessing the low byte triggers the 16-bit read or write operation.
When the low byte of a 16-bit register is written by the CPU, the high byte stored in the tempo-
rary register, and the low byte written are both copied into the 16-bit register in the same clock
cycle. When the low byte of a 16-bit register is read by the CPU, the high byte of the 16-bit reg-
ister is copied into the temporary register in the same clock cycle as the low byte is read.
Not all 16-bit accesses uses the temporary register for the high byte. Reading the OCR1A/B
16-bit registers does not involve using the temporary register.
To do a 16-bit write, the high byte must be written before the low byte. For a 16-bit read, the
low byte must be read before the high byte.
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12.3.1
Code Examples
The following code examples show how to access the 16-bit timer registers assuming that no
interrupts updates the temporary register. The same principle can be used directly for access-
ing the OCR1A/B and ICR1 Registers. Note that when using “C”, the compiler handles the
16-bit access.
Assembly Code Examples(1)
...
; Set TCNT1 to 0x01FF
ldi
ldi
sts
sts
r17,0x01
r16,0xFF
TCNT1H,r17
TCNT1L,r16
; Read TCNT1 into r17:r16
lds
lds
...
r16,TCNT1L
r17,TCNT1H
C Code Examples(1)
unsigned int i;
...
/* Set TCNT1 to 0x01FF */
TCNT1 = 0x1FF;
/* Read TCNT1 into i */
i = TCNT1;
...
Note:
1. The example code assumes that the part specific header file is included.
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
It is important to notice that accessing 16-bit registers are atomic operations. If an interrupt
occurs between the two instructions accessing the 16-bit register, and the interrupt code
updates the temporary register by accessing the same or any other of the 16-bit timer regis-
ters, then the result of the access outside the interrupt will be corrupted. Therefore, when both
the main code and the interrupt code update the temporary register, the main code must dis-
able the interrupts during the 16-bit access.
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The following code examples show how to do an atomic read of the TCNT1 Register contents.
Reading any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Assembly Code Example(1)
TIM16_ReadTCNT1:
; Save global interrupt flag
in
r18,SREG
; Disable interrupts
cli
; Read TCNT1 into r17:r16
lds
lds
r16,TCNT1L
r17,TCNT1H
; Restore global interrupt flag
out
ret
SREG,r18
C Code Example(1)
unsigned int TIM16_ReadTCNT1(void)
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Read TCNT1 into i */
i = TCNT1;
/* Restore global interrupt flag */
SREG = sreg;
return i;
}
Note:
1. The example code assumes that the part specific header file is included.
The assembly code example returns the TCNT1 value in the r17:r16 register pair.
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The following code examples show how to do an atomic write of the TCNT1 Register contents.
Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle.
Assembly Code Example(1)
TIM16_WriteTCNT1:
; Save global interrupt flag
in
r18,SREG
; Disable interrupts
cli
; Set TCNT1 to r17:r16
sts
sts
TCNT1H,r17
TCNT1L,r16
; Restore global interrupt flag
out
ret
SREG,r18
C Code Example(1)
void TIM16_WriteTCNT1(unsigned int i)
{
unsigned char sreg;
unsigned int i;
/* Save global interrupt flag */
sreg = SREG;
/* Disable interrupts */
_CLI();
/* Set TCNT1 to i */
TCNT1 = i;
/* Restore global interrupt flag */
SREG = sreg;
}
Note:
1. The example code assumes that the part specific header file is included.
The assembly code example requires that the r17:r16 register pair contains the value to be
written to TCNT1.
12.3.2
Reusing the Temporary High Byte Register
If writing to more than one 16-bit register where the high byte is the same for all registers writ-
ten, then the high byte only needs to be written once. However, note that the same rule of
atomic operation described previously also applies in this case.
12.4 Timer/Counter Clock Sources
The Timer/Counter can be clocked by an internal or an external clock source. The clock
source is selected by the Clock Select logic which is controlled by the Clock Select (CS12:0)
bits located in the Timer/Counter control Register B (TCCR1B). For details on clock sources
and prescaler, see “Timer/Counter1 Prescaler” on page 110.
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12.5 Counter Unit
The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter
unit. Figure 12-2 shows a block diagram of the counter and its surroundings.
Figure 12-2. Counter Unit Block Diagram
DATA BUS (8-bit)
TOVn
(Int.Req.)
TEMP (8-bit)
Clock Select
Edge
Count
Tn
Detector
TCNTnH (8-bit)
TCNTnL (8-bit)
Clear
clkTn
Control Logic
Direction
TCNTn (16-bit Counter)
( From Prescaler )
TOP
BOTTOM
Signal description (internal signals):
Count
Direction
Clear
Increment or decrement TCNT1 by 1.
Select between increment and decrement.
Clear TCNT1 (set all bits to zero).
clkT1
Timer/Counter clock.
TOP
Signalize that TCNT1 has reached maximum value.
Signalize that TCNT1 has reached minimum value (zero).
BOTTOM
The 16-bit counter is mapped into two 8-bit I/O memory locations: Counter High (TCNT1H)
containing the upper eight bits of the counter, and Counter Low (TCNT1L) containing the lower
eight bits. The TCNT1H Register can only be indirectly accessed by the CPU. When the CPU
does an access to the TCNT1H I/O location, the CPU accesses the high byte temporary regis-
ter (TEMP). The temporary register is updated with the TCNT1H value when the TCNT1L is
read, and TCNT1H is updated with the temporary register value when TCNT1L is written. This
allows the CPU to read or write the entire 16-bit counter value within one clock cycle via the
8-bit data bus. It is important to notice that there are special cases of writing to the TCNT1
Register when the counter is counting that will give unpredictable results. The special cases
are described in the sections where they are of importance.
Depending on the mode of operation used, the counter is cleared, incremented, or decre-
mented at each timer clock (clkT1). The clkT1 can be generated from an external or internal
clock source, selected by the Clock Select bits (CS12:0). When no clock source is selected
(CS12:0 = 0) the timer is stopped. However, the TCNT1 value can be accessed by the CPU,
independent of whether clkT1 is present or not. A CPU write overrides (has priority over) all
counter clear or count operations.
The counting sequence is determined by the setting of the Waveform Generation mode bits
(WGM13:0) located in the Timer/Counter Control Registers A and B (TCCR1A and TCCR1B).
There are close connections between how the counter behaves (counts) and how waveforms
are generated on the Output Compare outputs OC1A/B. For more details about advanced
counting sequences and waveform generation, see “Modes of Operation” on page 125.
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The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected
by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt.
12.6 Input Capture Unit
The Timer/Counter incorporates an Input Capture unit that can capture external events and
give them a time-stamp indicating time of occurrence. The external signal indicating an event,
or multiple events, can be applied via the ICP1 pin or alternatively, via the analog-comparator
unit. The time-stamps can then be used to calculate frequency, duty-cycle, and other features
of the signal applied. Alternatively the time-stamps can be used for creating a log of the
events.
The Input Capture unit is illustrated by the block diagram shown in Figure 12-3. The elements
of the block diagram that are not directly a part of the Input Capture unit are gray shaded.
Figure 12-3. Input Capture Unit Block Diagram
DATA BUS (8-bit)
TEMP (8-bit)
ICRnH (8-bit)
ICRnL (8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
ICRn (16-bit Register)
TCNTn (16-bit Counter)
WRITE
ACIC
ICNCn
ICESn
ICPn
Noise
Canceler
Edge
Detector
ICF1n (Int.Req.)
ACO
Analog
Comparator
When a change of the logic level (an event) occurs on the Input Capture pin (ICP1), alterna-
tively on the Analog Comparator output (ACO), and this change confirms to the setting of the
edge detector, a capture will be triggered. When a capture is triggered, the 16-bit value of the
counter (TCNT1) is written to the Input Capture Register (ICR1). The Input Capture Flag
(ICF1) is set at the same system clock as the TCNT1 value is copied into ICR1 Register. If
enabled (ICIE1 = 1), the Input Capture Flag generates an Input Capture interrupt. The ICF1
flag is automatically cleared when the interrupt is executed. Alternatively the ICF1 flag can be
cleared by software by writing a logical one to its I/O bit location.
Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low
byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is cop-
ied into the high byte temporary register (TEMP). When the CPU reads the ICR1H I/O location
it will access the TEMP Register.
The ICR1 Register can only be written when using a Waveform Generation mode that utilizes
the ICR1 Register for defining the counter’s TOP value. In these cases the Waveform Genera-
tion mode (WGM13:0) bits must be set before the TOP value can be written to the ICR1
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Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O loca-
tion before the low byte is written to ICR1L.
For more information on how to access the 16-bit registers refer to “Accessing 16-bit Regis-
ters” on page 115.
12.6.1
Input Capture Trigger Source
The main trigger source for the Input Capture unit is the Input Capture pin (ICP1). Only
Timer/Counter1 can alternatively use the Analog Comparator output as trigger source for the
Input Capture unit. The Analog Comparator is selected as trigger source by setting the Analog
Comparator Input Capture (ACIC) bit in the Analog Comparator Control and Status Register
(ACSR). Be aware that changing trigger source can trigger a capture. The Input Capture Flag
must therefore be cleared after the change.
Both the Input Capture pin (ICP1) and the Analog Comparator output (ACO) inputs are sam-
pled using the same technique as for the T1 pin (Figure 11-1 on page 110). The edge detector
is also identical. However, when the noise canceler is enabled, additional logic is inserted
before the edge detector, which increases the delay by four system clock cycles. Note that the
input of the noise canceler and edge detector is always enabled unless the Timer/Counter is
set in a Waveform Generation mode that uses ICR1 to define TOP.
An Input Capture can be triggered by software by controlling the port of the ICP1 pin.
12.6.2
Noise Canceler
The noise canceler improves noise immunity by using a simple digital filtering scheme. The
noise canceler input is monitored over four samples, and all four must be equal for changing
the output that in turn is used by the edge detector.
The noise canceler is enabled by setting the Input Capture Noise Canceler (ICNC1) bit in
Timer/Counter Control Register B (TCCR1B). When enabled the noise canceler introduces
additional four system clock cycles of delay from a change applied to the input, to the update
of the ICR1 Register. The noise canceler uses the system clock and is therefore not affected
by the prescaler.
12.6.3
Using the Input Capture Unit
The main challenge when using the Input Capture unit is to assign enough processor capacity
for handling the incoming events. The time between two events is critical. If the processor has
not read the captured value in the ICR1 Register before the next event occurs, the ICR1 will
be overwritten with a new value. In this case the result of the capture will be incorrect.
When using the Input Capture interrupt, the ICR1 Register should be read as early in the inter-
rupt handler routine as possible. Even though the Input Capture interrupt has relatively high
priority, the maximum interrupt response time is dependent on the maximum number of clock
cycles it takes to handle any of the other interrupt requests.
Using the Input Capture unit in any mode of operation when the TOP value (resolution) is
actively changed during operation, is not recommended.
Measurement of an external signal’s duty cycle requires that the trigger edge is changed after
each capture. Changing the edge sensing must be done as early as possible after the ICR1
Register has been read. After a change of the edge, the Input Capture Flag (ICF1) must be
cleared by software (writing a logical one to the I/O bit location). For measuring frequency
only, the clearing of the ICF1 flag is not required (if an interrupt handler is used).
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12.7 Output Compare Units
The 16-bit comparator continuously compares TCNT1 with the Output Compare Register
(OCR1A/B). If TCNT equals OCR1A/B the comparator signals a match. A match will set the
Output Compare Flag (OCF1A/B) at the next timer clock cycle. If enabled (OCIE1A/B = 1), the
Output Compare Flag generates an Output Compare interrupt. The OCF1A/B flag is automati-
cally cleared when the interrupt is executed. Alternatively the OCF1A/B flag can be cleared by
software by writing a logical one to its I/O bit locations. The Waveform Generator uses the
match signal to generate an output according to operating mode set by the Waveform Gener-
ation mode (WGM13:0) bits and Compare Output mode (COM1A/B1:0) bits. The TOP and
BOTTOM signals are used by the Waveform Generator for handling the special cases of the
extreme values in some modes of operation (See “Modes of Operation” on page 125.)
A special feature of Output Compare unit A allows it to define the Timer/Counter TOP value
(i.e., counter resolution). In addition to the counter resolution, the TOP value defines the
period time for waveforms generated by the Waveform Generator.
Figure 12-4 shows a block diagram of the Output Compare unit. The elements of the block dia-
gram that are not directly a part of the Output Compare unit are gray shaded.
Figure 12-4. Output Compare Unit, Block Diagram
DATA BUS (8-bit)
TEMP (8-bit)
OCRnxH Buf.(8-bit)
OCRnxL Buf.(8-bit)
TCNTnH (8-bit)
TCNTnL (8-bit)
OCRnx Buffer (16-bit Register)
TCNTn (16-bit Counter)
OCRnxH (8-bit)
OCRnxL (8-bit)
OCRnx (16-bit Register)
=
(16-bit Comparator )
OCFnx
OCnxU
(Int.Req.)
TOP
Waveform Generator
OCnxV
OCnxW
OCnxX
BOTTOM
WGMn3:0
COMnx1:0
The OCR1A/B Register is double buffered when using any of the twelve Pulse Width Modula-
tion (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation,
the double buffering is disabled. The double buffering synchronizes the update of the
OCR1A/B Compare Register to either TOP or BOTTOM of the counting sequence. The syn-
chronization prevents the occurrence of odd-length, non-symmetrical PWM pulses, thereby
making the output glitch-free.
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The OCR1A/B Register access may seem complex, but this is not case. When the double
buffering is enabled, the CPU has access to the OCR1A/B Buffer Register, and if double buff-
ering is disabled the CPU will access the OCR1A/B directly. The content of the OCR1A/B
(Buffer or Compare) Register is only changed by a write operation (the Timer/Counter does
not update this register automatically as the TCNT1 and ICR1 Register). Therefore OCR1A/B
is not read via the high byte temporary register (TEMP). However, it is a good practice to read
the low byte first as when accessing other 16-bit registers. Writing the OCR1A/B Registers
must be done via the TEMP Register since the compare of all 16bits is done continuously. The
high byte (OCR1A/BH) has to be written first. When the high byte I/O location is written by the
CPU, the TEMP Register will be updated by the value written. Then when the low byte
(OCR1A/BL) is written to the lower eight bits, the high byte will be copied into the upper 8-bits
of either the OCR1A/B buffer or OCR1A/B Compare Register in the same system clock cycle.
For more information of how to access the 16-bit registers refer to “Accessing 16-bit Registers”
on page 115.
12.7.1
Force Output Compare
In non-PWM Waveform Generation modes, the match output of the comparator can be forced
by writing a one to the Force Output Compare (FOC1A/B) bit. Forcing compare match will not
set the OCF1A/B flag or reload/clear the timer, but the OC1A/Bi pins will be updated as if a
real compare match had occurred (the COM1A/B1:0 bits settings define whether the OC1A/Bi
pins are set, cleared or toggled - if the respective OCnxi bit is set).
12.7.2
12.7.3
Compare Match Blocking by TCNT1 Write
All CPU writes to the TCNT1 Register will block any compare match that occurs in the next
timer clock cycle, even when the timer is stopped. This feature allows OCR1A/B to be initial-
ized to the same value as TCNT1 without triggering an interrupt when the Timer/Counter clock
is enabled.
Using the Output Compare Unit
Since writing TCNT1 in any mode of operation will block all compare matches for one timer
clock cycle, there are risks involved when changing TCNT1 when using any of the Output
Compare channels, independent of whether the Timer/Counter is running or not. If the value
written to TCNT1 equals the OCR1A/B value, the compare match will be missed, resulting in
incorrect waveform generation. Do not write the TCNT1 equal to TOP in PWM modes with
variable TOP values. The compare match for the TOP will be ignored and the counter will con-
tinue to 0xFFFF. Similarly, do not write the TCNT1 value equal to BOTTOM when the counter
is downcounting.
The setup of the OC1A/B should be performed before setting the Data Direction Register for
the port pin to output. The easiest way of setting the OC1A/B value is to use the Force Output
Compare (FOC1A/B) strobe bits in Normal mode. The OC1A/B Register keeps its value even
when changing between Waveform Generation modes.
Be aware that the COM1A/B1:0 bits are not double buffered together with the compare value.
Changing the COM1A/B1:0 bits will take effect immediately.
12.8 Compare Match Output Unit
The Compare Output mode (COM1A/B1:0) bits have two functions. The Waveform Generator
uses the COM1A/B1:0 bits for defining the Output Compare (OC1A/B) state at the next com-
pare match. Secondly the COM1A/B1:0 and OCnxi bits control the OC1A/Bi pin output source.
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Figure 12-6 shows a simplified schematic of the logic affected by the COM1A/B1:0 and OCnxi
bit setting. The I/O Registers, I/O bits, and I/O pins in the figure are shown in bold. Only the
parts of the general I/O port control registers (DDR and PORT) that are affected by the
COM1A/B1:0 and OCnxi bits are shown. When referring to the OC1A/B state, the reference is
for the internal OC1A/B Register, not the OC1A/Bi pin. If a system reset occur, the OC1A/B
Register is reset to “0”.
Figure 12-5. Compare Match Output
( )
OC1AU
*
PINB0
1
0
20 PB0 / OC1AU
18 PB2 / OC1AV
14 PB4 / OC1AW
12 PB6 / OC1AX
PORTB0
( )
DDB0
PINB2
OC1AV
*
1
0
PORTB2
( )
DDB2
PINB4
OC1AW
*
1
0
PORTB4
( )
OCR1A
16-bit Register
DDB4
PINB6
COM1A0
COM1A1
OC1AX
*
OCF1A
1
0
Waveform
Generation
=
PORTB6
FOC1A
DDB6
WGM10
WGM11
WGM12
WGM13
Count
Clear
Top
TCNT1
16-bit Counter
Bottom
Direction
( )
OC1BU
*
FOC1B
PINB1
1
0
Waveform
Generation
=
19 PB1 / OC1BU
17 PB3 / OC1BV
13 PB5 / OC1BW
11 PB7 / OC1BX
PORTB1
( )
OCF1B
DDB1
PINB3
COM1B0
COM1B1
OCR1B
16-bit Register
OC1BV
*
1
0
PORTB3
( )
DDB3
PINB5
OC1BW
*
1
0
PORTB5
( )
DDB5
PINB7
OC1BX
*
1
0
( )
*
OC1xi: TCCR1D register bit
PORTB7
DDB7
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Atmel ATA5505 [Preliminary]
Figure 12-6. Compare Match Output Logic
OCnxi
COMnx1
Waveform
Generator
COMnx0
FOCnx
D
Q
1
0
OCnxi
Pin
OCnx
D
Q
PORT
D
Q
clkI/O
DDR
12.8.1
Compare Output Function
The general I/O port function is overridden by the Output Compare (OC1A/B) from the Wave-
form Generator if either of the COM1A/B1:0 bits are set and if OCnxi respective bit is set in
TCCR1D register. However, the OC1A/Bi pin direction (input or output) is still controlled by the
Data Direction Register (DDR) for the port pin. The Data Direction Register bit for the OC1A/Bi
pin (DDR_OC1A/Bi) must be set as output before the OC1A/B value is visible on the pin. The
port override function is generally independent of the Waveform Generation mode, but there
are some exceptions. Refer to Table 12-1, Table 12-2 and Table 12-3 for details.
The design of the Output Compare pin logic allows initialization of the OC1A/B state before the
output is enabled. Note that some COM1A/B1:0 bit settings are reserved for certain modes of
operation. See “16-bit Timer/Counter Register Description” on page 135.
The COM1A/B1:0 bits have no effect on the Input Capture unit.
12.8.2
Compare Output Mode and Waveform Generation
The Waveform Generator uses the COM1A/B1:0 bits differently in normal, CTC, and PWM
modes. For all modes, setting the COM1A/B1:0 = 0 tells the Waveform Generator that no
action on the OC1A/B Register is to be performed on the next compare match. For compare
output actions in the non-PWM modes refer to Table 12-1 on page 135. For fast PWM mode
refer to Table 12-2 on page 136, and for phase correct and phase and frequency correct PWM
refer to Table 12-3 on page 136.
A change of the COM1A/B1:0 bits state will have effect at the first compare match after the
bits are written. For non-PWM modes, the action can be forced to have immediate effect by
using the FOC1A/B strobe bits.
12.9 Modes of Operation
The mode of operation, i.e., the behavior of the Timer/Counter and the Output Compare pins,
is defined by the combination of the Waveform Generation mode (WGM13:0) and Compare
Output mode (COM1A/B1:0) bits. The Compare Output mode bits do not affect the counting
sequence, while the Waveform Generation mode bits do. The COM1A/B1:0 bits control
whether the PWM output generated should be inverted or not (inverted or non-inverted PWM).
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For non-PWM modes the COM1A/B1:0 bits control whether the output should be set, cleared
or toggle at a compare match (See ”Compare Match Output Unit” on page 123.). The OCnxi
bits over control the setting of the COM1A/B1:0 bits as shown in Figure 12-6 on page 125.
For detailed timing information refer to “Timer/Counter Timing Diagrams” on page 133.
12.9.1
Normal Mode
The simplest mode of operation is the Normal mode (WGM13:0 = 0). In this mode the counting
direction is always up (incrementing), and no counter clear is performed. The counter simply
overruns when it passes its maximum 16-bit value (MAX = 0xFFFF) and then restarts from the
BOTTOM (0x0000). In normal operation the Timer/Counter Overflow Flag (TOV1) will be set in
the same timer clock cycle as the TCNT1 becomes zero. The TOV1 flag in this case behaves
like a 17th bit, except that it is only set, not cleared. However, combined with the timer over-
flow interrupt that automatically clears the TOV1 flag, the timer resolution can be increased by
software. There are no special cases to consider in the Normal mode, a new counter value
can be written anytime.
The Input Capture unit is easy to use in Normal mode. However, observe that the maximum
interval between the external events must not exceed the resolution of the counter. If the inter-
val between events are too long, the timer overflow interrupt or the prescaler must be used to
extend the resolution for the capture unit.
The Output Compare units can be used to generate interrupts at some given time. Using the
Output Compare to generate waveforms in Normal mode is not recommended, since this will
occupy too much of the CPU time.
12.9.2
Clear Timer on Compare Match (CTC) Mode
In Clear Timer on Compare or CTC mode (WGM13:0 = 4 or 12), the OCR1A or ICR1 Register
are used to manipulate the counter resolution. In CTC mode the counter is cleared to zero
when the counter value (TCNT1) matches either the OCR1A (WGM13:0 = 4) or the ICR1
(WGM13:0 = 12). The OCR1A or ICR1 define the top value for the counter, hence also its res-
olution. This mode allows greater control of the compare match output frequency. It also
simplifies the operation of counting external events.
The timing diagram for the CTC mode is shown in Figure 12-7. The counter value (TCNT1)
increases until a compare match occurs with either OCR1A or ICR1, and then counter
(TCNT1) is cleared.
Figure 12-7. CTC Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
OCnAi
(Toggle)
(COMnA1:0 = 1)
1
2
3
4
Period
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An interrupt can be generated at each time the counter value reaches the TOP value by either
using the OCF1A or ICF1 flag according to the register used to define the TOP value. If the
interrupt is enabled, the interrupt handler routine can be used for updating the TOP value.
However, changing the TOP to a value close to BOTTOM when the counter is running with
none or a low prescaler value must be done with care since the CTC mode does not have the
double buffering feature. If the new value written to OCR1A or ICR1 is lower than the current
value of TCNT1, the counter will miss the compare match. The counter will then have to count
to its maximum value (0xFFFF) and wrap around starting at 0x0000 before the compare match
can occur. In many cases this feature is not desirable. An alternative will then be to use the
fast PWM mode using OCR1A for defining TOP (WGM13:0 = 15) since the OCR1A then will
be double buffered.
For generating a waveform output in CTC mode, the OC1A output can be set to toggle its log-
ical level on each compare match by setting the Compare Output mode bits to toggle mode
(COM1A1:0 = 1). The OC1A value will not be visible on the port pin unless the data direction
for the pin is set to output (DDR_OC1A = 1) and OC1Ai is set. The waveform generated will
have a maximum frequency of fOC1A = fclk_I/O/2 when OCR1A is set to zero (0x0000). The
waveform frequency is defined by the following equation:
f
clk_I/O
f
= --------------------------------------------------------
OCnA
2
N
(1 + OCRnA)
The N variable represents the prescaler factor (1, 8, 64, 256, or 1024).
As for the Normal mode of operation, the TOV1 flag is set in the same timer clock cycle that
the counter counts from MAX to 0x0000.
12.9.3
Fast PWM Mode
The fast Pulse Width Modulation or fast PWM mode (WGM13:0 = 5, 6, 7, 14, or 15) provides a
high frequency PWM waveform generation option. The fast PWM differs from the other PWM
options by its single-slope operation. The counter counts from BOTTOM to TOP then restarts
from BOTTOM. In non-inverting Compare Output mode, the Output Compare (OC1A/B) is set
on the compare match between TCNT1 and OCR1A/B, and cleared at TOP. In inverting Com-
pare Output mode output is cleared on compare match and set at TOP. Due to the
single-slope operation, the operating frequency of the fast PWM mode can be twice as high as
the phase correct and phase and frequency correct PWM modes that use dual-slope opera-
tion. This high frequency makes the fast PWM mode well suited for power regulation,
rectification, and DAC applications. High frequency allows physically small sized external
components (coils, capacitors), hence reduces total system cost.
The PWM resolution for fast PWM can be fixed to 8-, 9-, or 10-bit, or defined by either ICR1 or
OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003), and the
maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in bits can be
calculated by using the following equation:
log(TOP + 1)
R
= ----------------------------------
FPWM
log(2)
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In fast PWM mode the counter is incremented until the counter value matches either one of
the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 5, 6, or 7), the value in ICR1
(WGM13:0 = 14), or the value in OCR1A (WGM13:0 = 15). The counter is then cleared at the
following timer clock cycle. The timing diagram for the fast PWM mode is shown in Figure
12-8. The figure shows fast PWM mode when OCR1A or ICR1 is used to define TOP. The
TCNT1 value is in the timing diagram shown as a histogram for illustrating the single-slope
operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal
line marks on the TCNT1 slopes represent compare matches between OCR1A/B and TCNT1.
The OC1A/B interrupt flag will be set when a compare match occurs.
Figure 12-8. Fast PWM Mode, Timing Diagram
OCRnx/TOP Update and
TOVn Interrupt Flag Set and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TCNTn
(COMnx1:0 = 2)
OCnxi
(COMnx1:0 = 3)
OCnxi
1
2
3
4
5
6
7
8
Period
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches TOP. In addi-
tion the OC1A or ICF1 flag is set at the same timer clock cycle as TOV1 is set when either
OCR1A or ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the
interrupt handler routine can be used for updating the TOP and compare values.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the
OCR1A/B. Note that when using fixed TOP values the unused bits are masked to zero when
any of the OCR1A/B Registers are written.
The procedure for updating ICR1 differs from updating OCR1A when used for defining the
TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a
low value when the counter is running with none or a low prescaler value, there is a risk that
the new ICR1 value written is lower than the current value of TCNT1. The result will then be
that the counter will miss the compare match at the TOP value. The counter will then have to
count to the MAX value (0xFFFF) and wrap around starting at 0x0000 before the compare
match can occur. The OCR1A Register however, is double buffered. This feature allows the
OCR1A I/O location to be written anytime. When the OCR1A I/O location is written the value
written will be put into the OCR1A Buffer Register. The OCR1A Compare Register will then be
updated with the value in the Buffer Register at the next timer clock cycle the TCNT1 matches
TOP. The update is done at the same timer clock cycle as the TCNT1 is cleared and the TOV1
flag is set.
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Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. How-
ever, if the base PWM frequency is actively changed (by changing the TOP value), using the
OCR1A as TOP is clearly a better choice due to its double buffer feature.
In fast PWM mode, the compare units allow generation of PWM waveforms on the OC1A/B
pins. Setting the COM1x1:0 bits to two will produce a non-inverted PWM and an inverted
PWM output can be generated by setting the COM1A/B1:0 to three (see Table 12-2 on page
136). The actual OC1A/B value will only be visible on the port pin if the data direction for the
port pin is set as output (DDR_OC1A/B) and OC1A/Bi is set. The PWM waveform is generated
by setting (or clearing) the OC1A/B Register at the compare match between OCR1A/B and
TCNT1, and clearing (or setting) the OC1A/B Register at the timer clock cycle the counter is
cleared (changes from TOP to BOTTOM).
The PWM frequency for the output can be calculated by the following equation:
f
clk_I/O
f
= -------------------------------------
OCnxPWM
N
(1 + TOP)
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1A/B Register represents special cases when generating a
PWM waveform output in the fast PWM mode. If the OCR1A/B is set equal to BOTTOM
(0x0000) the output will be a narrow spike for each TOP+1 timer clock cycle. Setting the
OCR1A/B equal to TOP will result in a constant high or low output (depending on the polarity
of the output set by the COM1A/B1:0 bits.)
A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by
setting OC1A to toggle its logical level on each compare match (COM1A1:0 = 1). The wave-
form generated will have a maximum frequency of f 1A = f
/2 when OCR1A is set to
OC
clk_I/O
zero (0x0000). This feature is similar to the OC1A toggle in CTC mode, except the double buf-
fer feature of the Output Compare unit is enabled in the fast PWM mode.
12.9.4
Phase Correct PWM Mode
The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13:0 = 1, 2, 3,
10, or 11) provides a high resolution phase correct PWM waveform generation option. The
phase correct PWM mode is, like the phase and frequency correct PWM mode, based on a
dual-slope operation. The counter counts repeatedly from BOTTOM (0x0000) to TOP and
then from TOP to BOTTOM. In non-inverting Compare Output mode, the Output Compare
(OC1A/B) is cleared on the compare match between TCNT1 and OCR1A/B while upcounting,
and set on the compare match while downcounting. In inverting Output Compare mode, the
operation is inverted. The dual-slope operation has lower maximum operation frequency than
single slope operation. However, due to the symmetric feature of the dual-slope PWM modes,
these modes are preferred for motor control applications.
The PWM resolution for the phase correct PWM mode can be fixed to 8-, 9-, or 10-bit, or
defined by either ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A
set to 0x0003), and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM
resolution in bits can be calculated by using the following equation:
log(TOP + 1)
R
= ----------------------------------
PCPWM
log(2)
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In phase correct PWM mode the counter is incremented until the counter value matches either
one of the fixed values 0x00FF, 0x01FF, or 0x03FF (WGM13:0 = 1, 2, or 3), the value in ICR1
(WGM13:0 = 10), or the value in OCR1A (WGM13:0 = 11). The counter has then reached the
TOP and changes the count direction. The TCNT1 value will be equal to TOP for one timer
clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 12-9.
The figure shows phase correct PWM mode when OCR1A or ICR1 is used to define TOP. The
TCNT1 value is in the timing diagram shown as a histogram for illustrating the dual-slope
operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal
line marks on the TCNT1 slopes represent compare matches between OCR1A/B and TCNT1.
The OC1A/B interrupt flag will be set when a compare match occurs.
Figure 12-9. Phase Correct PWM Mode, Timing Diagram
OCRnx/TOP Update and
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
(COMnx1:0 = 2)
OCnxi
(COMnx1:0 = 3)
OCnxi
1
2
3
4
Period
The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM.
When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 flag is set
accordingly at the same timer clock cycle as the OCR1A/B Registers are updated with the
double buffer value (at TOP). The interrupt flags can be used to generate an interrupt each
time the counter reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the
OCR1A/B. Note that when using fixed TOP values, the unused bits are masked to zero when
any of the OCR1A/B Registers are written. As the third period shown in Figure 12-9 illustrates,
changing the TOP actively while the Timer/Counter is running in the phase correct mode can
result in an unsymmetrical output. The reason for this can be found in the time of update of the
OCR1A/B Register. Since the OCR1A/B update occurs at TOP, the PWM period starts and
ends at TOP. This implies that the length of the falling slope is determined by the previous
TOP value, while the length of the rising slope is determined by the new TOP value. When
these two values differ the two slopes of the period will differ in length. The difference in length
gives the unsymmetrical result on the output.
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It is recommended to use the phase and frequency correct mode instead of the phase correct
mode when changing the TOP value while the Timer/Counter is running. When using a static
TOP value there are practically no differences between the two modes of operation.
In phase correct PWM mode, the compare units allow generation of PWM waveforms on the
OC1A/B pins. Setting the COM1A/B1:0 bits to two will produce a non-inverted PWM and an
inverted PWM output can be generated by setting the COM1A/B1:0 to three (See Table on
page 136). The actual OC1A/B value will only be visible on the port pin if the data direction for
the port pin is set as output (DDR_OC1A/B) and OC1A/Bi is set. The PWM waveform is gener-
ated by setting (or clearing) the OC1A/B Register at the compare match between OCR1A/B
and TCNT1 when the counter increments, and clearing (or setting) the OC1A/B Register at
compare match between OCR1A/B and TCNT1 when the counter decrements. The PWM fre-
quency for the output when using phase correct PWM can be calculated by the following
equation:
f
clk_I/O
f
= ---------------------------------
OCnxPCPWM
2
N
TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1A/B Register represent special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR1A/B is set equal to BOT-
TOM the output will be continuously low and if set equal to TOP the output will be continuously
high for non-inverted PWM mode. For inverted PWM the output will have the opposite logic
values.
12.9.5
Phase and Frequency Correct PWM Mode
The phase and frequency correct Pulse Width Modulation, or phase and frequency correct
PWM mode (WGM13:0 = 8 or 9) provides a high resolution phase and frequency correct PWM
waveform generation option. The phase and frequency correct PWM mode is, like the phase
correct PWM mode, based on a dual-slope operation. The counter counts repeatedly from
BOTTOM (0x0000) to TOP and then from TOP to BOTTOM. In non-inverting Compare Output
mode, the Output Compare (OC1A/B) is cleared on the compare match between TCNT1 and
OCR1A/B while upcounting, and set on the compare match while downcounting. In inverting
Compare Output mode, the operation is inverted. The dual-slope operation gives a lower max-
imum operation frequency compared to the single-slope operation. However, due to the
symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control
applications.
The main difference between the phase correct, and the phase and frequency correct PWM
mode is the time the OCR1A/B Register is updated by the OCR1A/B Buffer Register, (see Fig-
ure 12-9 and Figure 12-10).
The PWM resolution for the phase and frequency correct PWM mode can be defined by either
ICR1 or OCR1A. The minimum resolution allowed is 2-bit (ICR1 or OCR1A set to 0x0003),
and the maximum resolution is 16-bit (ICR1 or OCR1A set to MAX). The PWM resolution in
bits can be calculated using the following equation:
log(TOP + 1)
R
= ----------------------------------
PFCPWM
log(2)
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In phase and frequency correct PWM mode the counter is incremented until the counter value
matches either the value in ICR1 (WGM13:0 = 8), or the value in OCR1A (WGM13:0 = 9). The
counter has then reached the TOP and changes the count direction. The TCNT1 value will be
equal to TOP for one timer clock cycle. The timing diagram for the phase correct and fre-
quency correct PWM mode is shown on Figure 12-10. The figure shows phase and frequency
correct PWM mode when OCR1A or ICR1 is used to define TOP. The TCNT1 value is in the
timing diagram shown as a histogram for illustrating the dual-slope operation. The diagram
includes non-inverted and inverted PWM outputs. The small horizontal line marks on the
TCNT1 slopes represent compare matches between OCR1A/B and TCNT1. The OC1A/B
interrupt flag will be set when a compare match occurs.
Figure 12-10. Phase and Frequency Correct PWM Mode, Timing Diagram
OCnA Interrupt Flag Set
or ICFn Interrupt Flag Set
(Interrupt on TOP)
OCRnx/TOP Update and
TOVn Interrupt Flag Set
(Interrupt on Bottom)
TCNTn
(COMnx1:0 = 2)
OCnxi
(COMnx1:0 = 3)
OCnxi
1
2
3
4
Period
The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1A/B
Registers are updated with the double buffer value (at BOTTOM). When either OCR1A or
ICR1 is used for defining the TOP value, the OC1A or ICF1 flag set when TCNT1 has reached
TOP. The interrupt flags can then be used to generate an interrupt each time the counter
reaches the TOP or BOTTOM value.
When changing the TOP value the program must ensure that the new TOP value is higher or
equal to the value of all of the Compare Registers. If the TOP value is lower than any of the
Compare Registers, a compare match will never occur between the TCNT1 and the
OCR1A/B.
As Figure 12-10 shows the output generated is, in contrast to the phase correct mode, sym-
metrical in all periods. Since the OCR1A/B Registers are updated at BOTTOM, the length of
the rising and the falling slopes will always be equal. This gives symmetrical output pulses and
is therefore frequency correct.
Using the ICR1 Register for defining TOP works well when using fixed TOP values. By using
ICR1, the OCR1A Register is free to be used for generating a PWM output on OC1A. How-
ever, if the base PWM frequency is actively changed by changing the TOP value, using the
OCR1A as TOP is clearly a better choice due to its double buffer feature.
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In phase and frequency correct PWM mode, the compare units allow generation of PWM
waveforms on the OC1A/B pins. Setting the COM1A/B1:0 bits to two will produce a
non-inverted PWM and an inverted PWM output can be generated by setting the COM1A/B1:0
to three (See Table on page 136). The actual OC1A/B value will only be visible on the port pin
if the data direction for the port pin is set as output (DDR_OC1A/B) and OC1A/Bi is set. The
PWM waveform is generated by setting (or clearing) the OC1A/B Register at the compare
match between OCR1A/B and TCNT1 when the counter increments, and clearing (or setting)
the OC1A/B Register at compare match between OCR1A/B and TCNT1 when the counter
decrements. The PWM frequency for the output when using phase and frequency correct
PWM can be calculated by the following equation:
f
clk_I/O
f
= ---------------------------------
OCnxPFCPWM
2
N
TOP
The N variable represents the prescaler divider (1, 8, 64, 256, or 1024).
The extreme values for the OCR1A/B Register represents special cases when generating a
PWM waveform output in the phase correct PWM mode. If the OCR1A/B is set equal to BOT-
TOM the output will be continuously low and if set equal to TOP the output will be set to high
for non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
12.10 Timer/Counter Timing Diagrams
The Timer/Counter is a synchronous design and the timer clock (clkT1) is therefore shown as a
clock enable signal in the following figures. The figures include information on when interrupt
flags are set, and when the OCR1A/B Register is updated with the OCR1A/B buffer value
(only for modes utilizing double buffering). Figure 12-11 shows a timing diagram for the setting
of OCF1A/B.
Figure 12-11. Timer/Counter Timing Diagram, Setting of OCF1A/B, no Prescaling
clkI/O
clkTn
(clkI/O/1)
TCNTn
OCRnx
OCFnx
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
Figure 12-12 shows the same timing data, but with the prescaler enabled.
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Figure 12-12. Timer/Counter Timing Diagram, Setting of OCF1A/B, with Prescaler (fclk_I/O/8)
clkI/O
clkTn
(clkI/O/8)
TCNTn
OCRnx
OCFnx
OCRnx - 1
OCRnx
OCRnx + 1
OCRnx + 2
OCRnx Value
Figure 12-13 shows the count sequence close to TOP in various modes. When using phase
and frequency correct PWM mode the OCR1A/B Register is updated at BOTTOM. The timing
diagrams will be the same, but TOP should be replaced by BOTTOM, TOP-1 by BOTTOM+1
and so on. The same renaming applies for modes that set the TOV1 flag at BOTTOM.
Figure 12-13. Timer/Counter Timing Diagram, no Prescaling
clkI/O
clkTn
(clkI/O/1)
TCNTn
TOP - 1
TOP - 1
TOP
TOP
BOTTOM
TOP - 1
BOTTOM + 1
TOP - 2
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOVn (FPWM)
and ICFn (if used
as TOP)
OCRnx
(Update at TOP)
New OCRnx Value
Old OCRnx Value
Figure 12-14 shows the same timing data, but with the prescaler enabled.
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Figure 12-14. Timer/Counter Timing Diagram, with Prescaler (fclk_I/O/8)
clk
I/O
clk
Tn
(clk /8)
I/O
TCNTn
TOP - 1
TOP - 1
TOP
TOP
BOTTOM
TOP - 1
BOTTOM + 1
TOP - 2
(CTC and FPWM)
TCNTn
(PC and PFC PWM)
TOVn(FPWM)
and ICFn(if used
as TOP)
OCRnx
(Update at TOP)
Old OCRnx Value
New OCRnx Value
12.11 16-bit Timer/Counter Register Description
12.11.1 Timer/Counter1 Control Register A – TCCR1A
Bit
7
COM1A1
R/W
6
COM1A0
R/W
5
COM1B1
R/W
4
3
–
2
–
1
0
COM1B0
WGM11
R/W
0
WGM10
R/W
0
TCCR1A
Read/Write
Initial Value
R/W
0
R
0
R
0
0
0
0
• Bit 7:6 – COM1A1:0: Compare Output Mode for Channel A
• Bit 5:4 – COM1B1:0: Compare Output Mode for Channel B
The COM1A1:0 and COM1B1:0 control the Output Compare pins (OC1Ai and OC1Bi respec-
tively) behavior. If one or both of the COM1A1:0 bits are written to one, the OC1Ai output
overrides the normal port functionality of the I/O pin it is connected to. If one or both of the
COM1B1:0 bit are written to one, the OC1Bi output overrides the normal port functionality of
the I/O pin it is connected to. However, note that the Data Direction Register (DDR) bit and
OC1xi bit (TCCR1D) corresponding to the OC1Ai or OC1Bi pin must be set in order to enable
the output driver.
When the OC1Ai or OC1Bi is connected to the pin, the function of the COM1A/B1:0 bits is
dependent of the WGM13:0 bits setting. Table 12-1 shows the COM1A/B1:0 bit functionality
when the WGM13:0 bits are set to a Normal or a CTC mode (non-PWM).
Table 12-1. Compare Output Mode, non-PWM
OC1Ai
OC1Bi
COM1A1
COM1B1
COM1A0
COM1B0
Description
0
1
x
0
0
x
0
1
Normal port operation, OC1A/OC1B disconnected.
Toggle OC1A/OC1B on Compare Match.
Clear OC1A/OC1B on Compare Match (Set output to low
level).
1
1
0
1
Set OC1A/OC1B on Compare Match (Set output to high level).
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Table 12-2 shows the COM1A/B1:0 bit functionality when the WGM13:0 bits are set to the fast
PWM mode.
Table 12-2. Compare Output Mode, Fast PWM (1)
OC1Ai
OC1Bi
COM1A1
COM1B1
COM1A0
COM1B0
Description
0
1
x
x
Normal port operation, OC1A/OC1B disconnected.
0
0
WGM13=0: Normal port operation, OC1A/OC1B
disconnected.
1
0
1
WGM13=1: Toggle OC1A on Compare Match, OC1B
reserved.
Clear OC1A/OC1B on Compare Match
Set OC1A/OC1B at TOP
1
1
1
1
0
1
Set OC1A/OC1B on Compare Match
Clear OC1A/OC1B at TOP
Note:
1. A special case occurs when OCR1A/OCR1B equals TOP and COM1A1/COM1B1 is set. In
this case the compare match is ignored, but the set or clear is done at TOP. See “Fast PWM
Mode” on page 127. for more details.
Table 12-3 shows the COM1A/B1:0 bit functionality when the WGM13:0 bits are set to the
phase correct or the phase and frequency correct, PWM mode.
Table 12-3. Compare Output Mode, Phase Correct and Phase and Frequency Correct
PWM(1)
OC1Ai
OC1Bi
COM1A1
COM1B1
COM1A0
COM1B0
Description
0
1
x
x
Normal port operation, OC1A/OC1B disconnected.
0
0
WGM13=0: Normal port operation, OC1A/OC1B
disconnected.
1
0
1
WGM13=1: Toggle OC1A on Compare Match, OC1B
reserved.
Clear OC1A/OC1B on Compare Match when up-counting.
Set OC1A/OC1B on Compare Match when downcounting.
1
1
1
1
0
1
Set OC1A/OC1B on Compare Match when up-counting.
Clear OC1A/OC1B on Compare Match when downcounting.
Note:
1. A special case occurs when OC1A/OC1B equals TOP and COM1A1/COM1B1 is set. See
“Phase Correct PWM Mode” on page 129. for more details.
• Bit 3:2 – Reserved Bits
These bits are reserved for future use.
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• Bit 1:0 – WGM11:0: Waveform Generation Mode
Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the count-
ing sequence of the counter, the source for maximum (TOP) counter value, and what type of
waveform generation to be used, see Table 12-4. Modes of operation supported by the
Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode,
and three types of Pulse Width Modulation (PWM) modes. (See “Modes of Operation” on page
125.).
Table 12-4. Waveform Generation Mode Bit Description (1)
WGM12
(CTC1)
WGM11
(PWM11) (PWM10)
WGM10
Timer/Counter
Mode of Operation
Update of
OCR1A/B at
TOV1 Flag
Set on
Mode
WGM13
TOP
0
1
2
0
0
0
0
0
0
0
0
1
0
1
0
Normal
0xFFFF
0x00FF
0x01FF
Immediate
TOP
MAX
PWM, Phase Correct, 8-bit
PWM, Phase Correct, 9-bit
BOTTOM
BOTTOM
TOP
PWM, Phase Correct,
10-bit
3
0
0
1
1
0x03FF
TOP
BOTTOM
4
5
6
7
0
0
0
0
1
1
1
1
0
0
1
1
0
1
0
1
CTC
OCR1A
0x00FF
0x01FF
0x03FF
Immediate
TOP
MAX
TOP
TOP
TOP
Fast PWM, 8-bit
Fast PWM, 9-bit
Fast PWM, 10-bit
TOP
TOP
PWM, Phase and
Frequency Correct
8
9
1
1
0
0
0
0
0
1
ICR1
BOTTOM
BOTTOM
BOTTOM
BOTTOM
PWM, Phase and
Frequency Correct
OCR1A
10
11
12
13
14
15
1
1
1
1
1
1
0
0
1
1
1
1
1
1
0
0
1
1
0
1
0
1
0
1
PWM, Phase Correct
PWM, Phase Correct
CTC
ICR1
OCR1A
ICR1
–
TOP
TOP
BOTTOM
BOTTOM
MAX
Immediate
–
(Reserved)
–
Fast PWM
ICR1
OCR1A
TOP
TOP
Fast PWM
TOP
TOP
Note:
1. The CTC1 and PWM11:0 bit definition names are obsolete. Use the WGM12:0 definitions. However, the functionality and
location of these bits are compatible with previous versions of the timer.
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12.11.2 Timer/Counter1 Control Register B – TCCR1B
Bit
7
ICNC1
R/W
0
6
ICES1
R/W
0
5
–
4
WGM13
R/W
0
3
WGM12
R/W
0
2
CS12
R/W
0
1
CS11
R/W
0
0
CS10
R/W
0
TCCR1B
Read/Write
Initial Value
R
0
• Bit 7 – ICNC1: Input Capture Noise Canceler
Setting this bit (to one) activates the Input Capture Noise Canceler. When the noise canceler
is activated, the input from the Input Capture pin (ICP1) is filtered. The filter function requires
four successive equal valued samples of the ICP1 pin for changing its output. The Input Cap-
ture is therefore delayed by four Oscillator cycles when the noise canceler is enabled.
• Bit 6 – ICES1: Input Capture Edge Select
This bit selects which edge on the Input Capture pin (ICP1) that is used to trigger a capture
event. When the ICES1 bit is written to zero, a falling (negative) edge is used as trigger, and
when the ICES1 bit is written to one, a rising (positive) edge will trigger the capture.
When a capture is triggered according to the ICES1 setting, the counter value is copied into
the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and
this can be used to cause an Input Capture Interrupt, if this interrupt is enabled.
When the ICR1 is used as TOP value (see description of the WGM13:0 bits located in the
TCCR1A and the TCCR1B Register), the ICP1 is disconnected and consequently the Input
Capture function is disabled.
• Bit 5 – Reserved Bit
This bit is reserved for future use. For ensuring compatibility with future devices, this bit must
be written to zero when TCCR1B is written.
• Bit 4:3 – WGM13:2: Waveform Generation Mode
See TCCR1A Register description.
• Bit 2:0 – CS12:0: Clock Select
The three Clock Select bits select the clock source to be used by the Timer/Counter, see Fig-
ure 12-11 and Figure 12-12.
Table 12-5. Clock Select Bit Description
CS12
CS11
CS10
Description
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
No clock source (Timer/Counter stopped).
clk /1 (No prescaling)
I/O
clk /8 (From prescaler)
I/O
clk /64 (From prescaler)
I/O
clk /256 (From prescaler)
I/O
clk /1024 (From prescaler)
I/O
External clock source on T1 pin. Clock on falling edge.
External clock source on T1 pin. Clock on rising edge.
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If external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the
counter even if the pin is configured as an output. This feature allows software control of the
counting.
12.11.3 Timer/Counter1 Control Register C – TCCR1C
Bit
7
6
5
–
4
–
3
–
2
–
1
–
0
–
FOC1A
FOC1B
TCCR1C
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R
0
R
0
R
0
R
0
R
0
• Bit 7 – FOC1A: Force Output Compare for Channel A
• Bit 6 – FOC1B: Force Output Compare for Channel B
The FOC1A/FOC1B bits are only active when the WGM13:0 bits specifies a non-PWM mode.
However, for ensuring compatibility with future devices, these bits must be set to zero when
TCCR1A is written when operating in a PWM mode. When writing a logical one to the
FOC1A/FOC1B bit, an immediate compare match is forced on the Waveform Generation unit.
The OC1nx output is changed according to its COM1A/B1:0 and OC1nx bits setting. Note that
the FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the
COM1A/B1:0 bits that determine the effect of the forced compare.
A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear Timer
on Compare match (CTC) mode using OCR1A as TOP.
The FOC1A/FOC1B bits are always read as zero.
12.11.4 Timer/Counter1 Control Register D – TCCR1D
Bit
7
6
5
OC1BV
R/W
0
4
OC1BU
R/W
0
3
OC1AX
R/W
0
2
OC1AW
R/W
0
1
OC1AV
R/W
0
0
OC1AU
R/W
0
OC1BX
OC1BW
TCCR1D
Read/Write
Initial Value
R/W
0
R/W
0
• Bit 7:4 – OC1Bi: Output Compare Pin Enable for Channel B
The OC1Bi bits enable the Output Compare pins of Channel B as shown in Figure 12-6 on
page 125.
• Bit 3:0 – OC1Ai: Output Compare Pin Enable for Channel A
The OC1Ai bits enable the Output Compare pins of Channel A as shown in Figure 12-6 on
page 125.
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12.11.5 Timer/Counter1 – TCNT1H and TCNT1L
Bit
7
6
5
4
3
2
1
0
TCNT1[15:8]
TCNT1[7:0]
TCNT1H
TCNT1L
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
The two Timer/Counter I/O locations (TCNT1H and TCNT1L, combined TCNT1) give direct
access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To
ensure that both the high and low bytes are read and written simultaneously when the CPU
accesses these registers, the access is performed using an 8-bit temporary high byte register
(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing
16-bit Registers” on page 115.
Modifying the counter (TCNT1) while the counter is running introduces a risk of missing a
compare match between TCNT1 and one of the OCR1A/B Registers.
Writing to the TCNT1 Register blocks (removes) the compare match on the following timer
clock for all compare units.
12.11.6 Output Compare Register A – OCR1AH and OCR1AL
Bit
7
6
5
4
3
2
1
0
OCR1A[15:8]
OCR1A[7:0]
OCR1AH
OCR1AL
Read/Write
Initial Value
R/W
R/W
R/W
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
0
0
0
12.11.7 Output Compare Register B – OCR1BH and OCR1BL
Bit
7
6
5
4
3
2
1
0
OCR1B[15:8]
OCR1B[7:0]
OCR1BH
OCR1BL
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
The Output Compare Registers contain a 16-bit value that is continuously compared with the
counter value (TCNT1). A match can be used to generate an Output Compare interrupt, or to
generate a waveform output on the OC1A/B pin.
The Output Compare Registers are 16-bit in size. To ensure that both the high and low bytes
are written simultaneously when the CPU writes to these registers, the access is performed
using an 8-bit temporary high byte register (TEMP). This temporary register is shared by all
the other 16-bit registers. See “Accessing 16-bit Registers” on page 115.
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Atmel ATA5505 [Preliminary]
12.11.8 Input Capture Register – ICR1H and ICR1L
Bit
7
6
5
4
3
2
1
0
ICR1[15:8]
ICR1[7:0]
ICR1H
ICR1L
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
The Input Capture is updated with the counter (TCNT1) value each time an event occurs on
the ICP1 pin (or optionally on the Analog Comparator output for Timer/Counter1). The Input
Capture can be used for defining the counter TOP value.
The Input Capture Register is 16-bit in size. To ensure that both the high and low bytes are
read simultaneously when the CPU accesses these registers, the access is performed using
an 8-bit temporary high byte register (TEMP). This temporary register is shared by all the other
16-bit registers. See “Accessing 16-bit Registers” on page 115.
12.11.9 Timer/Counter1 Interrupt Mask Register – TIMSK1
Bit
7
6
5
4
–
3
–
2
OCIE1B
R/W
0
1
OCIE1A
R/W
0
0
TOIE1
R/W
0
–
–
ICIE1
R/W
0
TIMSK1
Read/Write
Initial Value
R
0
R
0
R
0
R
0
• Bit 7..6 – Reserved Bits
These bits are reserved for future use.
• Bit 5 – ICIE1: Input Capture Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt
Vector (See ”Interrupt Vectors in the Atmel AVR” on page 63.) is executed when the ICF1 flag,
located in TIFR1, is set.
• Bit 4..3 – Reserved Bits
These bits are reserved for future use.
• Bit 2 – OCIE1B: Output Compare B Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare B Match interrupt is enabled. The correspond-
ing Interrupt Vector (See ”Interrupt Vectors in the Atmel AVR” on page 63.) is executed when
the OCF1B flag, located in TIFR1, is set.
• Bit 1 – OCIE1A: Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Output Compare A Match interrupt is enabled. The correspond-
ing Interrupt Vector (See ”Interrupt Vectors in the Atmel AVR” on page 63.) is executed when
the OCF1A flag, located in TIFR1, is set.
• Bit 0 – TOIE1: Timer/Counter Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Counter1 Overflow interrupt is enabled. The corresponding Interrupt Vec-
tor (See ”Interrupt Vectors in the Atmel AVR” on page 63.) is executed when the TOV1 flag,
located in TIFR1, is set.
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12.11.10 Timer/Counter1 Interrupt Flag Register – TIFR1
Bit
7
–
6
–
5
4
–
3
–
2
OCF1B
R/W
0
1
OCF1A
R/W
0
0
TOV1
R/W
0
ICF1
R/W
0
TIFR1
Read/Write
Initial Value
R
0
R
0
R
0
R
0
• Bit 7..6 – Reserved Bits
These bits are reserved for future use.
• Bit 5 – ICF1: Input Capture Flag
This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register
(ICR1) is set by the WGM13:0 to be used as the TOP value, the ICF1 flag is set when the
counter reaches the TOP value.
ICF1 is automatically cleared when the Input Capture Interrupt Vector is executed. Alterna-
tively, ICF1 can be cleared by writing a logic one to its bit location.
• Bit 4..3 – Reserved Bits
These bits are reserved for future use.
• Bit 2 – OCF1B: Output Compare B Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register B (OCR1B).
Note that a Forced Output Compare (FOC1B) strobe will not set the OCF1B flag.
OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe-
cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location.
• Bit 1 – OCF1A: Output Compare A Match Flag
This flag is set in the timer clock cycle after the counter (TCNT1) value matches the Output
Compare Register A (OCR1A).
Note that a Forced Output Compare (FOC1A) strobe will not set the OCF1A flag.
OCF1A is automatically cleared when the Output Compare Match A Interrupt Vector is exe-
cuted. Alternatively, OCF1A can be cleared by writing a logic one to its bit location.
• Bit 0 – TOV1: Timer/Counter Overflow Flag
The setting of this flag is dependent of the WGM13:0 bits setting. In Normal and CTC modes,
the TOV1 flag is set when the timer overflows. Refer to Table 12-4 on page 137 for the TOV1
flag behavior when using another WGM13:0 bit setting.
TOV1 is automatically cleared when the Timer/Counter1 Overflow Interrupt Vector is exe-
cuted. Alternatively, TOV1 can be cleared by writing a logic one to its bit location.
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Atmel ATA5505 [Preliminary]
13. SPI - Serial Peripheral Interface
The Serial Peripheral Interface (SPI) allows high-speed synchronous data transfer between
the Atmel® AVR® and peripheral devices or between several Atmel AVR devices. The Atmel
AVR SPI includes the following features:
13.1 Features
• Full-duplex, Three-wire Synchronous Data Transfer
• Master or Slave Operation
• LSB First or MSB First Data Transfer
• Seven Programmable Bit Rates
• End of Transmission Interrupt Flag
• Write Collision Flag Protection
• Wake-up from Idle Mode
• Double Speed (CK/2) Master SPI Mode
Figure 13-1. SPI Block Diagram(1)
clkIO
DIVIDER
/2/4/8/16/32/64/128
Note:
1. Refer to Figure 1-5 on page 6, and Table 9-3 on page 79 for SPI pin placement.
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The interconnection between Master and Slave CPUs with SPI is shown in Figure 13-2. The
system consists of two shift Registers, and a Master clock generator. The SPI Master initiates
the communication cycle when pulling low the Slave Select SS pin of the desired Slave. Mas-
ter and Slave prepare the data to be sent in their respective shift Registers, and the Master
generates the required clock pulses on the SCK line to interchange data. Data is always
shifted from Master to Slave on the Master Out – Slave In, MOSI, line, and from Slave to Mas-
ter on the Master In – Slave Out, MISO, line. After each data packet, the Master will
synchronize the Slave by pulling high the Slave Select, SS, line.
When configured as a Master, the SPI interface has no automatic control of the SS line. This
must be handled by user software before communication can start. When this is done, writing
a byte to the SPI Data Register starts the SPI clock generator, and the hardware shifts the
eight bits into the Slave. After shifting one byte, the SPI clock generator stops, setting the end
of transmission flag (SPIF). If the SPI Interrupt Enable bit (SPIE) in the SPCR Register is set,
an interrupt is requested. The Master may continue to shift the next byte by writing it into
SPDR, or signal the end of packet by pulling high the Slave Select, SS line. The last incoming
byte will be kept in the Buffer Register for later use.
When configured as a Slave, the SPI interface will remain sleeping with MISO tri-stated as
long as the SS pin is driven high. In this state, software may update the contents of the SPI
Data Register, SPDR, but the data will not be shifted out by incoming clock pulses on the SCK
pin until the SS pin is driven low. As one byte has been completely shifted, the end of trans-
mission flag, SPIF is set. If the SPI Interrupt Enable bit, SPIE, in the SPCR Register is set, an
interrupt is requested. The Slave may continue to place new data to be sent into SPDR before
reading the incoming data. The last incoming byte will be kept in the Buffer Register for later
use.
Figure 13-2. SPI Master-slave Interconnection
SHIFT
ENABLE
The system is single buffered in the transmit direction and double buffered in the receive direc-
tion. This means that bytes to be transmitted cannot be written to the SPI Data Register before
the entire shift cycle is completed. When receiving data, however, a received character must
be read from the SPI Data Register before the next character has been completely shifted in.
Otherwise, the first byte is lost.
In SPI Slave mode, the control logic will sample the incoming signal of the SCK pin. To ensure
correct sampling of the clock signal, the frequency of the SPI clock should never exceed
f
/4.
clkio
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overrid-
den according to Table 13-1. For more details on automatic port overrides, refer to “Alternate
Port Functions” on page 75.
Table 13-1. SPI Pin Overrides(1)
Pin
MOSI
MISO
SCK
SS
Direction, Master SPI
User Defined
Input
Direction, Slave SPI
Input
User Defined
Input
User Defined
User Defined
Input
Note:
1. See “Alternate Functions of Port B” on page 84 for a detailed description of how to define the
direction of the user defined SPI pins.
The following code examples show how to initialize the SPI as a Master and how to perform a
simple transmission.
DDR_SPI in the examples must be replaced by the actual Data Direction Register controlling
the SPI pins. DD_MOSI, DD_MISO and DD_SCK must be replaced by the actual data direc-
tion bits for these pins. E.g. if MOSI is placed on pin PB2, replace DD_MOSI with DDB2 and
DDR_SPI with DDRB.
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Assembly Code Example(1)
SPI_MasterInit:
; Set MOSI and SCK output, all others input
ldi
out
r17,(1<<DD_MOSI)|(1<<DD_SCK)
DDR_SPI,r17
; Enable SPI, Master, set clock rate fck/16
ldi
out
ret
r17,(1<<SPE)|(1<<MSTR)|(1<<SPR0)
SPCR,r17
SPI_MasterTransmit:
; Start transmission of data (r16)
out
SPDR,r16
Wait_Transmit:
; Wait for transmission complete
in
r17,SPSR
sbrs
rjmp
ret
r17,SPIF
Wait_Transmit
C Code Example(1)
void SPI_MasterInit(void)
{
/* Set MOSI and SCK output, all others input */
DDR_SPI = (1<<DD_MOSI)|(1<<DD_SCK);
/* Enable SPI, Master, set clock rate fck/16 */
SPCR = (1<<SPE)|(1<<MSTR)|(1<<SPR0);
}
void SPI_MasterTransmit(char cData)
{
/* Start transmission */
SPDR = cData;
/* Wait for transmission complete */
while(!(SPSR & (1<<SPIF)));
}
Note:
1. The example code assumes that the part specific header file is included.
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The following code examples show how to initialize the SPI as a Slave and how to perform a
simple reception.
Assembly Code Example(1)
SPI_SlaveInit:
; Set MISO output, all others input
ldi
out
r17,(1<<DD_MISO)
DDR_SPI,r17
; Enable SPI
ldi
out
ret
r17,(1<<SPE)
SPCR,r17
SPI_SlaveReceive:
; Wait for reception complete
sbis
rjmp
SPSR,SPIF
SPI_SlaveReceive
; Read received data and return
in
r16,SPDR
ret
C Code Example(1)
void SPI_SlaveInit(void)
{
/* Set MISO output, all others input */
DDR_SPI = (1<<DD_MISO);
/* Enable SPI */
SPCR = (1<<SPE);
}
char SPI_SlaveReceive(void)
{
/* Wait for reception complete */
while(!(SPSR & (1<<SPIF)));
/* Return data register */
return SPDR;
}
Note:
1. The example code assumes that the part specific header file is included.
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13.2 SS Pin Functionality
13.2.1
Slave Mode
When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is
held low, the SPI is activated, and MISO becomes an output if configured so by the user. All
other pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which
means that it will not receive incoming data. Note that the SPI logic will be reset once the SS
pin is driven high.
The SS pin is useful for packet/byte synchronization to keep the slave bit counter synchronous
with the master clock generator. When the SS pin is driven high, the SPI slave will immediately
reset the send and receive logic, and drop any partially received data in the Shift Register.
13.2.2
Master Mode
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the
direction of the SS pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI
system. Typically, the pin will be driving the SS pin of the SPI Slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the SS
pin is driven low by peripheral circuitry when the SPI is configured as a Master with the SS pin
defined as an input, the SPI system interprets this as another master selecting the SPI as a
slave and starting to send data to it. To avoid bus contention, the SPI system takes the follow-
ing actions:
1. The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result
of the SPI becoming a Slave, the MOSI and SCK pins become inputs.
2. The SPIF flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in
SREG is set, the interrupt routine will be executed.
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a pos-
sibility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If
the MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI
Master mode.
13.2.3
SPI Control Register – SPCR
Bit
7
SPIE
R/W
0
6
5
DORD
R/W
0
4
MSTR
R/W
0
3
CPOL
R/W
0
2
CPHA
R/W
0
1
SPR1
R/W
0
0
SPR0
R/W
0
SPE
R/W
0
SPCR
Read/Write
Initial Value
• Bit 7 – SPIE: SPI Interrupt Enable
This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is set and if
the Global Interrupt Enable bit in SREG is set.
• Bit 6 – SPE: SPI Enable
When the SPE bit is written to one, the SPI is enabled. This bit must be set to enable any SPI
operations.
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• Bit 5 – DORD: Data Order
When the DORD bit is written to one, the LSB of the data word is transmitted first.
When the DORD bit is written to zero, the MSB of the data word is transmitted first.
• Bit 4 – MSTR: Master/Slave Select
This bit selects Master SPI mode when written to one, and Slave SPI mode when written logic
zero. If SS is configured as an input and is driven low while MSTR is set, MSTR will be
cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to re-enable
SPI Master mode.
• Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero, SCK is
low when idle. Refer to Figure 13-3 and Figure 13-4 for an example. The CPOL functionality is
summarized below:
Table 13-2. CPOL Functionality
CPOL
Leading Edge
Rising
Trailing Edge
Falling
0
1
Falling
Rising
• Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first)
or trailing (last) edge of SCK. Refer to Figure 13-3 and Figure 13-4 for an example. The CPOL
functionality is summarized below:
Table 13-3. CPHA Functionality
CPHA
Leading Edge
Sample
Trailing Edge
Setup
0
1
Setup
Sample
• Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0
have no effect on the Slave. The relationship between SCK and the clkIO frequency fclkio is
shown in the following table:
Table 13-4. Relationship Between SCK and the Oscillator Frequency
SPI2X
SPR1
SPR0
SCK Frequency
fclkio/4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
fclkio/16
fclkio/64
fclkio/128
fclkio/2
fclkio/8
fclkio/32
fclkio/64
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13.2.4
SPI Status Register – SPSR
Bit
7
SPIF
R
6
5
–
4
–
3
–
2
–
1
–
0
SPI2X
R/W
0
WCOL
SPSR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
0
• Bit 7 – SPIF: SPI Interrupt Flag
When a serial transfer is complete, the SPIF flag is set. An interrupt is generated if SPIE in
SPCR is set and global interrupts are enabled. If SS is an input and is driven low when the SPI
is in Master mode, this will also set the SPIF flag. SPIF is cleared by hardware when executing
the corresponding interrupt handling vector. Alternatively, the SPIF bit is cleared by first read-
ing the SPI Status Register with SPIF set, then accessing the SPI Data Register (SPDR).
• Bit 6 – WCOL: Write COLlision Flag
The WCOL bit is set if the SPI Data Register (SPDR) is written during a data transfer. The
WCOL bit (and the SPIF bit) are cleared by first reading the SPI Status Register with WCOL
set, and then accessing the SPI Data Register.
• Bit 5..1 – Res: Reserved Bits
These bits are reserved bits in the Atmel® AVR® and will always read as zero.
• Bit 0 – SPI2X: Double SPI Speed Bit
When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the
SPI is in Master mode (see Table 13-4). This means that the minimum SCK period will be two
CPU clock periods. When the SPI is configured as Slave, the SPI is only guaranteed to work at
fclkio/4 or lower.
The SPI interface on the Atmel AVR is also used for program memory and EEPROM down-
loading or uploading. See “Serial Downloading” on page 249 for serial programming and
verification.
13.2.5
SPI Data Register – SPDR
Bit
7
SPD7
R/W
X
6
SPD6
R/W
X
5
SPD5
R/W
X
4
SPD4
R/W
X
3
SPD3
R/W
X
2
SPD2
R/W
X
1
SPD1
R/W
X
0
SPD0
R/W
X
SPDR
Read/Write
Initial Value
Undefined
• Bits 7:0 - SPD7:0: SPI Data
The SPI Data Register is a read/write register used for data transfer between the Register File
and the SPI Shift Register. Writing to the register initiates data transmission. Reading the reg-
ister causes the Shift Register Receive buffer to be read.
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13.3 Data Modes
There are four combinations of SCK phase and polarity with respect to serial data, which are
determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in Fig-
ure 13-3 and Figure 13-4. Data bits are shifted out and latched in on opposite edges of the
SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by sum-
marizing Table 13-2 and Table 13-3, as done below:
Table 13-5. CPOL Functionality
Leading Edge
Sample (Rising)
Setup (Rising)
Sample (Falling)
Setup (Falling)
Trailing Edge
Setup (Falling)
Sample (Falling)
Setup (Rising)
Sample (Rising)
SPI Mode
CPOL=0, CPHA=0
CPOL=0, CPHA=1
CPOL=1, CPHA=0
CPOL=1, CPHA=1
0
1
2
3
Figure 13-3. SPI Transfer Format with CPHA = 0
SCK (CPOL = 0)
mode 0
SCK (CPOL = 1)
mode 2
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0) MSB
LSB first (DORD = 1) LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
Figure 13-4. SPI Transfer Format with CPHA = 1
SCK (CPOL = 0)
mode 1
SCK (CPOL = 1)
mode 3
SAMPLE I
MOSI/MISO
CHANGE 0
MOSI PIN
CHANGE 0
MISO PIN
SS
MSB first (DORD = 0)
LSB first (DORD = 1)
MSB
LSB
Bit 6
Bit 1
Bit 5
Bit 2
Bit 4
Bit 3
Bit 3
Bit 4
Bit 2
Bit 5
Bit 1
Bit 6
LSB
MSB
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14. USI – Universal Serial Interface
14.1 Features
• Two-wire Synchronous Data Transfer (Master or Slave)
• Three-wire Synchronous Data Transfer (Master or Slave)
• Data Received Interrupt
• Wakeup from Idle Mode
• In Two-wire Mode: Wake-up from All Sleep Modes, Including Power-down Mode
• Two-wire Start Condition Detector with Interrupt Capability
14.2 Overview
The Universal Serial Interface, or USI, provides the basic hardware resources needed for
serial communication. Combined with a minimum of control software, the USI allows signifi-
cantly higher transfer rates and uses less code space than solutions based on software only.
Interrupts are included to minimize the processor load.
A simplified block diagram of the USI is shown on Figure 14-1 For the actual placement of I/O
pins, refer to Section 1.3 “Pin Configuration” on page 6. CPU accessible I/O Registers, includ-
ing I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations
are listed in the “Register Descriptions” on page 159.
Figure 14-1. Universal Serial Interface, Block Diagram
(Output only)
DO
D
LE
Q
(Input/Open Drain)
DI/SDA
3
2
USIDR
USIDB
1
0
TIM0 COMP
3
2
0
1
(Input/Open Drain)
USCK/SCL
4-bit Counter
1
0
CLOCK
HOLD
[1]
Two-wire Clock
Control Unit
USISR
2
USICR
The 8-bit USI Data Register is directly accessible via the data bus and contains the incoming
and outgoing data. The register has no buffering so the data must be read as quickly as possi-
ble to ensure that no data is lost. The USI Data Register is a serial shift register and the most
significant bit that is the output of the serial shift register is connected to one of two output pins
depending of the wire mode configuration.
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A transparent latch is inserted between the USI Data Register Output and output pin, which
delays the change of data output to the opposite clock edge of the data input sampling. The
serial input is always sampled from the Data Input (DI) pin independent of the configuration.
The 4-bit counter can be both read and written via the data bus, and can generate an overflow
interrupt. Both the USI Data Register and the counter are clocked simultaneously by the same
clock source. This allows the counter to count the number of bits received or transmitted and
generate an interrupt when the transfer is complete. Note that when an external clock source
is selected the counter counts both clock edges. In this case the counter counts the number of
edges, and not the number of bits. The clock can be selected from three different sources: The
USCK pin, Timer/Counter0 Compare Match or from software.
The Two-wire clock control unit can generate an interrupt when a start condition is detected on
the Two-wire bus. It can also generate wait states by holding the clock pin low after a start
condition is detected, or after the counter overflows.
14.3 Functional Descriptions
14.3.1
Three-wire Mode
The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1,
but does not have the slave select (SS) pin functionality. However, this feature can be imple-
mented in software if necessary. Pin names used by this mode are: DI, DO, and USCK.
Figure 14-2. Three-wire Mode Operation, Simplified Diagram
DO
DI
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
USCK
SLAVE
DO
DI
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
USCK
PORTxn
MASTER
Figure 14-2 shows two USI units operating in Three-wire mode, one as Master and one as
Slave. The two USI Data Register are interconnected in such way that after eight USCK
clocks, the data in each register are interchanged. The same clock also increments the USI’s
4-bit counter. The Counter Overflow (interrupt) Flag, or USIOIF, can therefore be used to
determine when a transfer is completed.
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The clock is generated by the Master device software by toggling the USCK pin via the PORT
Register or by writing a one to the USITC bit in USICR.
Figure 14-3. Three-wire Mode, Timing Diagram
( Reference )
1
2
3
4
5
6
7
8
CYCLE
USCK
USCK
DO
MSB
MSB
6
5
4
3
2
1
LSB
LSB
6
5
4
3
2
1
DI
A
B
C
D
E
The Three-wire mode timing is shown in Figure 14-3 At the top of the figure is a USCK cycle
reference. One bit is shifted into the USI Data Register (USIDR) for each of these cycles. The
USCK timing is shown for both external clock modes. In External Clock mode 0 (USICS0 = 0),
DI is sampled at positive edges, and DO is changed (Data Register is shifted by one) at nega-
tive edges. External Clock mode 1 (USICS0 = 1) uses the opposite edges versus mode 0, i.e.,
samples data at negative and changes the output at positive edges. The USI clock modes cor-
responds to the SPI data mode 0 and 1.
Referring to the timing diagram (Figure 14-3), a bus transfer involves the following steps:
1. The Slave device and Master device sets up its data output and, depending on the
protocol used, enables its output driver (mark A and B). The output is set up by writ-
ing the data to be transmitted to the USI Data Register. Enabling of the output is done
by setting the corresponding bit in the port Data Direction Register. Note that point A
and B does not have any specific order, but both must be at least one half USCK
cycle before point C where the data is sampled. This must be done to ensure that the
data setup requirement is satisfied. The 4-bit counter is reset to zero.
2. The Master generates a clock pulse by software toggling the USCK line twice (C and
D). The bit value on the slave and master’s data input (DI) pin is sampled by the USI
on the first edge (C), and the data output is changed on the opposite edge (D). The
4-bit counter will count both edges.
3. Step 2. is repeated eight times for a complete register (byte) transfer.
4. After eight clock pulses (i.e., 16 clock edges) the counter will overflow and indicate
that the transfer is completed. The data bytes transferred must now be processed
before a new transfer can be initiated. The overflow interrupt will wake up the proces-
sor if it is set to Idle mode. Depending of the protocol used the slave device can now
set its output to high impedance.
14.3.2
SPI Master Operation Example
The following code demonstrates how to use the USI module as a SPI Master:
SPITransfer:
sts
ldi
sts
ldi
USIDR,r16
r16,(1<<USIOIF)
USISR,r16
r16,(1<<USIWM0)|(1<<USICS1)|(1<<USICLK)|(1<<USITC)
SPITransfer_loop:
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sts
USICR,r16
lds
r16, USISR
sbrs
rjmp
lds
r16, USIOIF
SPITransfer_loop
r16,USIDR
ret
The code is size optimized using only eight instructions (+ ret). The code example assumes
that the DO and USCK pins are enabled as output in the DDRA or DDRB Register. The value
stored in register r16 prior to the function is called is transferred to the Slave device, and when
the transfer is completed the data received from the Slave is stored back into the r16 Register.
The second and third instructions clears the USI Counter Overflow Flag and the USI counter
value. The fourth and fifth instruction set Three-wire mode, positive edge Shift Register clock,
count at USITC strobe, and toggle USCK. The loop is repeated 16 times.
The following code demonstrates how to use the USI module as a SPI Master with maximum
speed (fsck = fck/4):
SPITransfer_Fast:
sts
ldi
ldi
USIDR,r16
r16,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)
r17,(1<<USIWM0)|(0<<USICS0)|(1<<USITC)|(1<<USICLK)
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
sts
USICR,r16 ; MSB
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16
USICR,r17
USICR,r16 ; LSB
USICR,r17
lds
ret
r16,USIDR
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14.3.3
SPI Slave Operation Example
The following code demonstrates how to use the USI module as a SPI Slave:
init:
ldi
sts
r16,(1<<USIWM0)|(1<<USICS1)
USICR,r16
...
SlaveSPITransfer:
sts
ldi
sts
USIDR,r16
r16,(1<<USIOIF)
USISR,r16
SlaveSPITransfer_loop:
lds
r16, USISR
sbrs
rjmp
lds
r16, USIOIF
SlaveSPITransfer_loop
r16,USIDR
ret
The code is size optimized using only eight instructions (+ ret). The code example assumes
that the DO is configured as output and USCK pin is configured as input in the DDR Register.
The value stored in register r16 prior to the function is called is transferred to the master
device, and when the transfer is completed the data received from the Master is stored back
into the r16 Register.
Note that the first two instructions is for initialization only and needs only to be executed
once.These instructions sets Three-wire mode and positive edge USI Data Register clock.
The loop is repeated until the USI Counter Overflow Flag is set.
14.3.4
Two-wire Mode
The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate
limiting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA.
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Figure 14-4. Two-wire Mode Operation, Simplified Diagram
VCC
SDA
SCL
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
HOLD
SCL
Two-wire Clock
Control Unit
SLAVE
SDA
SCL
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
PORTxn
MASTER
Figure 14-4 shows two USI units operating in Two-wire mode, one as Master and one as
Slave. It is only the physical layer that is shown since the system operation is highly depen-
dent of the communication scheme used. The main differences between the Master and Slave
operation at this level, is the serial clock generation which is always done by the Master, and
only the Slave uses the clock control unit. Clock generation must be implemented in software,
but the shift operation is done automatically by both devices. Note that only clocking on nega-
tive edge for shifting data is of practical use in this mode. The slave can insert wait states at
start or end of transfer by forcing the SCL clock low. This means that the Master must always
check if the SCL line was actually released after it has generated a positive edge.
Since the clock also increments the counter, a counter overflow can be used to indicate that
the transfer is completed. The clock is generated by the master by toggling the USCK pin via
the PORT Register.
The data direction is not given by the physical layer. A protocol, like the one used by the
TWI-bus, must be implemented to control the data flow.
Figure 14-5. Two-wire Mode, Typical Timing Diagram
SDA
1 - 7
8
9
1 - 8
9
1 - 8
9
SCL
S
P
ADDRESS
R/W
ACK
DATA
ACK
DATA
ACK
A
B
C
D
E
F
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Referring to the timing diagram (Figure 14-5), a bus transfer involves the following steps:
1. The a start condition is generated by the Master by forcing the SDA low line while the
SCL line is high (A). SDA can be forced low either by writing a zero to bit 7 of the Shift
Register, or by setting the corresponding bit in the PORT Register to zero. Note that
the USI Data Register bit must be set to one for the output to be enabled. The slave
device’s start detector logic (Figure 14-6.) detects the start condition and sets the
USISIF Flag. The flag can generate an interrupt if necessary.
2. In addition, the start detector will hold the SCL line low after the Master has forced an
negative edge on this line (B). This allows the Slave to wake up from sleep or com-
plete its other tasks before setting up the USI Data Register to receive the address.
This is done by clearing the start condition flag and reset the counter.
3. The Master set the first bit to be transferred and releases the SCL line (C). The Slave
samples the data and shift it into the USI Data Register at the positive edge of the
SCL clock.
4. After eight bits are transferred containing slave address and data direction (read or
write), the Slave counter overflows and the SCL line is forced low (D). If the slave is
not the one the Master has addressed, it releases the SCL line and waits for a new
start condition.
5. If the Slave is addressed it holds the SDA line low during the acknowledgment cycle
before holding the SCL line low again (i.e., the Counter Register must be set to 14
before releasing SCL at (D)). Depending of the R/W bit the Master or Slave enables
its output. If the bit is set, a master read operation is in progress (i.e., the slave drives
the SDA line) The slave can hold the SCL line low after the acknowledge (E).
6. Multiple bytes can now be transmitted, all in same direction, until a stop condition is
given by the Master (F). Or a new start condition is given.
If the Slave is not able to receive more data it does not acknowledge the data byte it has last
received. When the Master does a read operation it must terminate the operation by force the
acknowledge bit low after the last byte transmitted.
Figure 14-6. Start Condition Detector, Logic Diagram
USISIF
CLOCK
HOLD
D Q
D Q
SDA
CLR
CLR
SCL
Write( USISIF)
14.3.5
Start Condition Detector
The start condition detector is shown in Figure 14-6. The SDA line is delayed (in the range of
50 to 300ns) to ensure valid sampling of the SCL line. The start condition detector is only
enabled in Two-wire mode.
The start condition detector is working asynchronously and can therefore wake up the proces-
sor from the Power-down sleep mode. However, the protocol used might have restrictions on
the SCL hold time. Therefore, when using this feature in this case the Oscillator start-up time
set by the CKSEL Fuses (see “Clock Systems and their Distribution” on page 28) must also be
taken into the consideration. Refer to the USISIF bit description on page 160 for further
details.
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14.4 Alternative USI Usage
When the USI unit is not used for serial communication, it can be set up to do alternative tasks
due to its flexible design.
14.4.1
14.4.2
14.4.3
14.4.4
Half-duplex Asynchronous Data Transfer
By utilizing the USI Data Register in Three-wire mode, it is possible to implement a more com-
pact and higher performance UART than by software only.
4-bit Counter
The 4-bit counter can be used as a stand-alone counter with overflow interrupt. Note that if the
counter is clocked externally, both clock edges will generate an increment.
12-bit Timer/Counter
Combining the USI 4-bit counter and Timer/Counter0 allows them to be used as a 12-bit
counter.
Edge Triggered External Interrupt
By setting the counter to maximum value (F) it can function as an additional external interrupt.
The Overflow Flag and Interrupt Enable bit are then used for the external interrupt. This fea-
ture is selected by the USICS1 bit.
14.4.5
Software Interrupt
The counter overflow interrupt can be used as a software interrupt triggered by a clock strobe.
14.5 Register Descriptions
14.5.1
USIDR – USI Data Register
Bit
7
USID7
R/W
0
6
USID6
R/W
0
5
USID5
R/W
0
4
USID4
R/W
0
3
USID3
R/W
0
2
USID2
R/W
0
1
USID1
R/W
0
0
USID0
R/W
0
USIDR
Read/Write
Initial Value
• Bits 7:0 – USID7..0: USI Data
When accessing the USI Data Register (USIDR) the Serial Register can be accessed directly.
If a serial clock occurs at the same cycle the register is written, the register will contain the
value written and no shift is performed. A (left) shift operation is performed depending of the
USICS1..0 bits setting. The shift operation can be controlled by an external clock edge, by a
Timer/Counter0 Compare Match, or directly by software using the USICLK strobe bit. Note
that even when no wire mode is selected (USIWM1..0 = 0) both the external data input
(DI/SDA) and the external clock input (USCK/SCL) can still be used by the USI Data Register.
The output pin in use, DO or SDA depending on the wire mode, is connected via the output
latch to the most significant bit (bit 7) of the Data Register. The output latch is open (transpar-
ent) during the first half of a serial clock cycle when an external clock source is selected
(USICS1 = 1), and constantly open when an internal clock source is used (USICS1 = 0). The
output will be changed immediately when a new MSB written as long as the latch is open. The
latch ensures that data input is sampled and data output is changed on opposite clock edges.
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Note that the corresponding Data Direction Register to the pin must be set to one for enabling
data output from the USI Data Register.
14.5.2
USIBR – USI Buffer Register
Bit
7
USIB7
R
6
USIB6
R
5
USIB5
R
4
USIB4
R
3
USIB3
R
2
USIB2
R
1
USIB1
R
0
USIB0
R
USIBR
Read/Write
Initial Value
0
0
0
0
0
0
0
0
• Bits 7:0 – USID7..0: USI Buffer
The content of the Serial Register is loaded to the USI Buffer Register when the transfer is
completed, and instead of accessing the USI Data Register (the Serial Register) the USI Data
Buffer can be accessed when the CPU reads the received data. This gives the CPU time to
handle other program tasks too as the controlling of the USI is not so timing critical. The USI
flags as set same as when reading the USIDR register.
14.5.3
USISR – USI Status Register
The Status Register contains Interrupt Flags, line Status Flags and the counter value.
Bit
7
USISIF
R/W
0
6
USIOIF
R/W
0
5
USIPF
R/W
0
4
3
USICNT3
R/W
2
USICNT2
R/W
1
USICNT1
R/W
0
USICNT0
R/W
USIDC
USISR
Read/Write
Initial Value
R
0
0
0
0
0
• Bit 7 – USISIF: Start Condition Interrupt Flag
When Two-wire mode is selected, the USISIF Flag is set (to one) when a start condition is
detected. When output disable mode or Three-wire mode is selected and (USICSx = 11b &
USICLK = 0) or (USICS = 10b & USICLK = 0), any edge on the SCK pin sets the flag.
An interrupt will be generated when the flag is set while the USISIE bit in USICR and the
Global Interrupt Enable Flag are set. The flag will only be cleared by writing a logical one to the
USISIF bit. Clearing this bit will release the start detection hold of USCL in Two-wire mode.
A start condition interrupt will wakeup the processor from all sleep modes.
• Bit 6 – USIOIF: Counter Overflow Interrupt Flag
This flag is set (one) when the 4-bit counter overflows (i.e., at the transition from 15 to 0). An
interrupt will be generated when the flag is set while the USIOIE bit in USICR and the Global
Interrupt Enable Flag are set. The flag will only be cleared if a one is written to the USIOIF bit.
Clearing this bit will release the counter overflow hold of SCL in Two-wire mode.
A counter overflow interrupt will wakeup the processor from Idle sleep mode.
• Bit 5 – USIPF: Stop Condition Flag
When Two-wire mode is selected, the USIPF Flag is set (one) when a stop condition is
detected. The flag is cleared by writing a one to this bit. Note that this is not an Interrupt Flag.
This signal is useful when implementing Two-wire bus master arbitration.
• Bit 4 – USIDC: Data Output Collision
This bit is logical one when bit 7 in the USI Data Register differs from the physical pin value.
The flag is only valid when Two-wire mode is used. This signal is useful when implementing
Two-wire bus master arbitration.
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• Bits 3:0 – USICNT3..0: Counter Value
These bits reflect the current 4-bit counter value. The 4-bit counter value can directly be read
or written by the CPU.
The 4-bit counter increments by one for each clock generated either by the external clock
edge detector, by a Timer/Counter0 Compare Match, or by software using USICLK or USITC
strobe bits. The clock source depends of the setting of the USICS1..0 bits. For external clock
operation a special feature is added that allows the clock to be generated by writing to the
USITC strobe bit. This feature is enabled by write a one to the USICLK bit while setting an
external clock source (USICS1 = 1).
Note that even when no wire mode is selected (USIWM1..0 = 0) the external clock input
(USCK/SCL) are can still be used by the counter.
14.5.4
USICR – USI Control Register
Bit
7
USISIE
R/W
0
6
USIOIE
R/W
0
5
USIWM1
R/W
4
USIWM0
R/W
3
USICS1
R/W
0
2
USICS0
R/W
0
1
0
USITC
W
USICLK
USICR
Read/Write
Initial Value
W
0
0
0
0
The Control Register includes interrupt enable control, wire mode setting, Clock Select setting,
and clock strobe.
• Bit 7 – USISIE: Start Condition Interrupt Enable
Setting this bit to one enables the Start Condition detector interrupt. If there is a pending inter-
rupt when the USISIE and the Global Interrupt Enable Flag is set to one, this will immediately
be executed. Refer to the USISIF bit description on page 160 for further details.
• Bit 6 – USIOIE: Counter Overflow Interrupt Enable
Setting this bit to one enables the Counter Overflow interrupt. If there is a pending interrupt
when the USIOIE and the Global Interrupt Enable Flag is set to one, this will immediately be
executed. Refer to the USIOIF bit description on page 160 for further details.
• Bit 5:4 – USIWM1:0: Wire Mode
These bits set the type of wire mode to be used. Basically only the function of the outputs are
affected by these bits. Data and clock inputs are not affected by the mode selected and will
always have the same function. The counter and USI Data Register can therefore be clocked
externally, and data input sampled, even when outputs are disabled. The relations between
USIWM1:0 and the USI operation is summarized in Table 14-1.
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Table 14-1. Relations between USIWM1..0 and the USI Operation
USIWM1 USIWM0 Description
0
0
Outputs, clock hold, and start detector disabled. Port pins operates as normal.
Three-wire mode. Uses DO, DI, and USCK pins.
The Data Output (DO) pin overrides the corresponding bit in the PORT Register
in this mode. However, the corresponding DDR bit still controls the data
direction. When the port pin is set as input the pins pull-up is controlled by the
PORT bit.
0
1
The Data Input (DI) and Serial Clock (USCK) pins do not affect the normal port
operation. When operating as master, clock pulses are software generated by
toggling the PORT Register, while the data direction is set to output. The USITC
bit in the USICR Register can be used for this purpose.
Two-wire mode. Uses SDA (DI) and SCL (USCK) pins(1)
.
The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-directional and
uses open-collector output drives. The output drivers are enabled by setting the
corresponding bit for SDA and SCL in the DDR Register.
When the output driver is enabled for the SDA pin, the output driver will force the
line SDA low if the output of the USI Data Register or the corresponding bit in the
PORT Register is zero. Otherwise the SDA line will not be driven (i.e., it is
released). When the SCL pin output driver is enabled the SCL line will be forced
low if the corresponding bit in the PORT Register is zero, or by the start detector.
Otherwise the SCL line will not be driven.
1
0
The SCL line is held low when a start detector detects a start condition and the
output is enabled. Clearing the Start Condition Flag (USISIF) releases the line.
The SDA and SCL pin inputs is not affected by enabling this mode. Pull-ups on
the SDA and SCL port pin are disabled in Two-wire mode.
Two-wire mode. Uses SDA and SCL pins.
Same operation as for the Two-wire mode described above, except that the SCL
line is also held low when a counter overflow occurs, and is held low until the
Counter Overflow Flag (USIOIF) is cleared.
1
1
Note:
1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respec-
tively to avoid confusion between the modes of operation.
• Bit 3:2 – USICS1:0: Clock Source Select
These bits set the clock source for the USI Data Register and counter. The data output latch
ensures that the output is changed at the opposite edge of the sampling of the data input
(DI/SDA) when using external clock source (USCK/SCL). When software strobe or
Timer/Counter0 Compare Match clock option is selected, the output latch is transparent and
therefore the output is changed immediately. Clearing the USICS1:0 bits enables software
strobe option. When using this option, writing a one to the USICLK bit clocks both the USI
Data Register and the counter. For external clock source (USICS1 = 1), the USICLK bit is no
longer used as a strobe, but selects between external clocking and software clocking by the
USITC strobe bit.
Table 14-2 on page 163 shows the relationship between the USICS1..0 and USICLK setting
and clock source used for the USI Data Register and the 4-bit counter.
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Table 14-2. Relations between the USICS1..0 and USICLK Setting
USI Data Register Clock
Source
USICS1
USICS0
USICLK
4-bit Counter Clock Source
0
0
0
No Clock
No Clock
Software clock strobe
(USICLK)
Software clock strobe
(USICLK)
0
0
0
1
1
Timer/Counter0 Compare
Match
Timer/Counter0 Compare
Match
X
1
1
1
1
0
1
0
1
0
0
1
1
External, positive edge
External, negative edge
External, positive edge
External, negative edge
External, both edges
External, both edges
Software clock strobe (USITC)
Software clock strobe (USITC)
• Bit 1 – USICLK: Clock Strobe
Writing a one to this bit location strobes the USI Data Register to shift one step and the coun-
ter to increment by one, provided that the USICS1..0 bits are set to zero and by doing so the
software clock strobe option is selected. The output will change immediately when the clock
strobe is executed, i.e., in the same instruction cycle. The value shifted into the USI Data Reg-
ister is sampled the previous instruction cycle. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1), the USICLK function is changed
from a clock strobe to a Clock Select Register. Setting the USICLK bit in this case will select
the USITC strobe bit as clock source for the 4-bit counter (see Table 14-2).
• Bit 0 – USITC: Toggle Clock Port Pin
Writing a one to this bit location toggles the USCK/SCL value either from 0 to 1, or from 1 to 0.
The toggling is independent of the setting in the Data Direction Register, but if the PORT value
is to be shown on the pin the DDB2 must be set as output (to one). This feature allows easy
clock generation when implementing master devices. The bit will be read as zero.
When an external clock source is selected (USICS1 = 1) and the USICLK bit is set to one,
writing to the USITC strobe bit will directly clock the 4-bit counter. This allows an early detec-
tion of when the transfer is done when operating as a master device.
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14.5.5
USIPP – USI Pin Position
Bit
7
-
6
-
5
-
4
-
3
-
2
-
1
-
0
USIPOS
R/W
0
USIPP
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
R
0
• Bits 7:1 – Res: Reserved Bits
These bits are reserved bits in the Atmel® AVR® and always reads as zero.
• Bit 0 – USIPOS: USI Pin Position
Setting or clearing this bit changes the USI pin position.
Table 14-3. USI Pin Position
USIPOS
USI Pin Position
DI, SDA
PB0 - (PCINT8/OC1AU)
PortB
0
1
DO
PB1 - (PCINT9/OC1BU)
(Default)
USCK, SCL
DI, SDA
PB2 - (PCINT10/OC1AV)
PA4 - (PCINT4/ADC4/ICP1/MOSI)
PA2 - (PCINT2/ADC2/OC0A/MISO)
PA5 - (PCINT5/ADC5/T1/SCK)
Port A
(Alternate)
DO
USCK, SCL
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15. LIN / UART - Local Interconnect Network Controller or UART
The LIN (Local Interconnect Network) is a serial communications protocol which efficiently
supports the control of mechatronics nodes in distributed automotive applications. The main
properties of the LIN bus are:
• Single master with multiple slaves concept
• Low cost silicon implementation based on common UART/SCI interface
• Self synchronization with on-chip oscillator in slave node
• Deterministic signal transmission with signal propagation time computable in advance
• Low cost single-wire implementation
• Speed up to 20 Kbit/s.
LIN provides a cost efficient bus communication where the bandwidth and versatility of CAN
are not required. The specification of the line driver/receiver needs to match the ISO9141
NRZ-standard.
If LIN is not required, the controller alternatively can be programmed as Universal Asynchro-
nous serial Receiver and Transmitter (UART).
15.1 LIN Features
• Hardware Implementation of LIN 2.1 (LIN 1.3 Compatibility)
• Small, CPU Efficient and Independent Master/Slave Routines Based on “LIN Work Flow
Concept” of LIN 2.1 Specification
• Automatic LIN Header Handling and Filtering of Irrelevant LIN Frames
• Automatic LIN Response Handling
• Extended LIN Error Detection and Signaling
• Hardware Frame Time-out Detection
• “Break-in-data” Support Capability
• Automatic Re-synchronization to Ensure Proper Frame Integrity
• Fully Flexible Extended Frames Support Capabilities
15.2 UART Features
• Full Duplex Operation (Independent Serial Receive and Transmit Processes)
• Asynchronous Operation
• High Resolution Baud Rate Generator
• Hardware Support of 8 Data Bits, Odd/Even/No Parity Bit, 1 Stop Bit Frames
• Data Over-Run and Framing Error Detection
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15.3 LIN Protocol
15.3.1
Master and Slave
A LIN cluster consists of one master task and several slave tasks. A master node contains the
master task as well as a slave task. All other nodes contain a slave task only.
Figure 15-1. LIN cluster with one master node and “n” slave nodes
master node
slave node
1
slave node
n
master task
slave task
slave task
slave task
LIN bus
The master task decides when and which frame shall be transferred on the bus. The slave
tasks provide the data transported by each frame. Both the master task and the slave task are
parts of the Frame handler
15.3.2
Frames
A frame consists of a header (provided by the master task) and a response (provided by a
slave task).
The header consists of a BREAK and SYNC pattern followed by a PROTECTED IDENTIFIER.
The identifier uniquely defines the purpose of the frame. The slave task appointed for provid-
ing the response associated with the identifier transmits it. The response consists of a DATA
field and a CHECKSUM field.
Figure 15-2. Master and slave tasks behavior in LIN frame
HEADER
HEADER
Master Task
Slave Task 1
Slave Task 2
RESPONSE
RESPONSE
The slave tasks waiting for the data associated with the identifier receives the response and
uses the data transported after verifying the checksum.
Figure 15-3. Structure of a LIN frame
FRAME SLOT
HEADER
RESPONSE
PROTECTED
IDENTIFIER
BREAK
SYNC
DATA-0
DATA-n
CHECKSUM
Field
Field
Field
Field
Field
Field
Break Delimiter
Response Space
Inter-Byte Space
Inter-Frame Space
Each byte field is transmitted as a serial byte, LSB first.
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15.3.3
Data Transport
Two types of data may be transported in a frame; signals or diagnostic messages.
• Signals
Signals are scalar values or byte arrays that are packed into the data field of a frame. A
signal is always present at the same position in the data field for all frames with the same
identifier.
• Diagnostic messages
Diagnostic messages are transported in frames with two reserved identifiers. The
interpretation of the data field depends on the data field itself as well as the state of the
communicating nodes.
15.3.4
15.3.5
Schedule Table
The master task (in the master node) transmits frame headers based on a schedule table. The
schedule table specifies the identifiers for each header and the interval between the start of a
frame and the start of the following frame. The master application may use different schedule
tables and select among them.
Compatibility with LIN 1.3
LIN 2.1 is a super-set of LIN 1.3.
A LIN 2.1 master node can handle clusters consisting of both LIN 1.3 slaves and/or LIN 2.1
slaves. The master will then avoid requesting the new LIN 2.1 features from a LIN 1.3 slave:
• Enhanced checksum,
• Re-configuration and diagnostics,
• Automatic baud rate detection,
• "Response error" status monitoring.
LIN 2.1 slave nodes can not operate with a LIN 1.3 master node (e.g. the LIN1.3 master does
not support the enhanced checksum).
The LIN 2.1 physical layer is backwards compatible with the LIN1.3 physical layer. But not the
other way around. The LIN 2.1 physical layer sets greater requirements, i.e. a master node
using the LIN 2.1 physical layer can operate in a LIN 1.3 cluster.
15.4 LIN / UART Controller
The LIN/UART controller is divided in three main functions:
• Tx LIN Header function,
• Rx LIN Header function,
• LIN Response function.
These functions mainly use two services:
• Rx service,
• Tx service.
Because these two services are basically UART services, the controller is also able to switch
into an UART function.
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15.4.1
LIN Overview
The LIN/UART controller is designed to match as closely as possible to the LIN software appli-
cation structure. The LIN software application is developed as independent tasks, several
slave tasks and one master task (c.f. Section 15.3.4 on page 167). The Atmel® AVR® con-
forms to this perspective. The only link between the master task and the slave task will be at
the cross-over point where the interrupt routine is called once a new identifier is available.
Thus, in a master node, housing both master and slave task, the Tx LIN Header function will
alert the slave task of an identifier presence. In the same way, in a slave node, the Rx LIN
Header function will alert the slave task of an identifier presence.
When the slave task is warned of an identifier presence, it has first to analyze it to know what
to do with the response. Hardware flags identify the presence of one of the specific identifiers
from 60 (0x3C) up to 63 (0x3F).
For LIN communication, only four interrupts need to be managed:
• LIDOK: New LIN identifier available,
• LRXOK: LIN response received,
• LTXOK: LIN response transmitted,
• LERR: LIN Error(s).
The wake-up management can be automated using the UART wake-up capability and a node
sending a minimum of 5 low bits (0xF0) for LIN 2.1 and 8 low bits (0x80) for LIN 1.3. Pin
change interrupt on LIN wake-up signal can be also used to exit the device of one of its sleep
modes.
Extended frame identifiers 62 (0x3E) and 63 (0x3F) are reserved to allow the embedding of
user-defined message formats and future LIN formats. The byte transfer mode offered by the
UART will ensure the upwards compatibility of LIN slaves with accommodation of the LIN
protocol.
15.4.2
UART Overview
The LIN/UART controller can also function as a conventional UART. By default, the UART
operates as a full duplex controller. It has local loop back circuitry for test purposes. The UART
has the ability to buffer one character for transmit and two for receive. The receive buffer is
made of one 8-bit serial register followed by one 8-bit independent buffer register. Automatic
flag management is implemented when the application puts or gets characters, thus reducing
the software overhead. Because transmit and receive services are independent, the user can
save one device pin when one of the two services is not used. The UART has an enhanced
baud rate generator providing a maximum error of 2% whatever the clock frequency and the
targeted baud rate.
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15.4.3
LIN/UART Controller Structure
Figure 15-4. LIN/UART Controller Block Diagram
Prescaler
Sample /bit
Finite State Machine
CLK
IO
BAUD_RATE
FSM
Get Byte
RX
Put Byte
TX
RxD
TxD
Frame Time-out
Synchronization
Monitoring
Data FIFO
BUFFER
15.4.4
LIN/UART Command Overview
Figure 15-5. LIN/UART Command Dependencies
Tx
Response
Tx Header
IDOK
TXOK
Rx
Response
Rx Header
or
RXOK
LIN Abort
Automatic
Return
LIN
Recommended
Way
DISABLE
UART
Possible
Way
Byte
Transfer
Rx
Byte
Full
Duplex
Tx
Byte
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Table 15-1. LIN/UART Command List
LENA LCMD[2] LCMD[1] LCMD[0]
Command
Disable peripheral
Rx Header - LIN Abort
Tx Header
Comment
0
x
x
x
0
1
0
1
0
0
1
1
LIN Withdrawal
0
LCMD[2..0]=000 after Tx
LCMD[2..0]=000 after Rx
LCMD[2..0]=000 after Tx
0
Rx Response
Tx Response
Byte transfer
Rx Byte
1
1
0
1
0
1
no CRC, no Time out
LTXDL=LRXDL=0
(LINDLR: read only register)
1
Tx Byte
Full duplex
15.4.5
15.4.6
Enable / Disable
LIN Commands
Setting the LENA bit in LINCR register enables the LIN/UART controller. To disable the
LIN/UART controller, LENA bit must be written to 0. No wait states are implemented, so, the
disable command is taken into account immediately.
Clearing the LCMD[2] bit in LINCR register enables LIN commands.
As shown in Table 15-1 on page 170, four functions controlled by the LCMD[1..0] bits of
LINCR register are available (c.f. Figure 15-5 on page 169).
15.4.6.1
Rx Header / LIN Abort Function
This function (or state) is mainly the withdrawal mode of the controller.
When the controller has to execute a master task, this state is the start point before enabling a
Tx Header command.
When the controller has only to execute slave tasks, LIN header detection/acquisition is
enabled as background function. At the end of such an acquisition (Rx Header function), auto-
matically the appropriate flags are set, and in LIN 1.3, the LINDLR register is set with the
uncoded length value.
This state is also the start point before enabling the Tx or the Rx Response command.
A running function (i.e. Tx Header, Tx or Rx Response ) can be aborted by clearing
LCMD[1..0] bits in LINCR register (See ”Break-in-data” on page 180.). In this case, an abort
flag - LABORT - in LINERR register will be set to inform the other software tasks. No wait
states are implemented, so, the abort command is taken into account immediately.
Rx Header function is responsible for:
• The BREAK field detection,
• The hardware re-synchronization analyzing the SYNCH field,
• The reception of the PROTECTED IDENTIFIER field, the parity control and the update of
the LINDLR register in case of LIN 1.3,
• The starting of the Frame_Time_Out,
• The checking of the LIN communication integrity.
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15.4.6.2
Tx Header Function
In accordance with the LIN protocol, only the master task must enable this function. The
header is sent in the appropriate timed slots at the programmed baud rate (c.f. LINBRR & LIN-
BTR registers).
The controller is responsible for:
• The transmission of the BREAK field - 13 dominant bits,
• The transmission of the SYNCH field - character 0x55,
• The transmission of the PROTECTED IDENTIFIER field. It is the full content of the LINIDR
register (automatic check bits included).
At the end of this transmission, the controller automatically returns to Rx Header / LIN Abort
state (i.e. LCMD[1..0] = 00) after setting the appropriate flags. This function leaves the control-
ler in the same setting as after the Rx Header function. This means that, in LIN 1.3, the
LINDLR register is set with the uncoded length value at the end of the Tx Header function.
During this function, the controller is also responsible for:
• The starting of the Frame_Time_Out,
• The checking of the LIN communication integrity.
15.4.6.3
Rx & TX Response Functions
These functions are initiated by the slave task of a LIN node. They must be used after sending
an header (master task) or after receiving an header (considered as belonging to the slave
task). When the TX Response order is sent, the transmission begins. A Rx Response order
can be sent up to the reception of the last serial bit of the first byte (before the stop-bit).
In LIN 1.3, the header slot configures the LINDLR register. In LIN 2.1, the user must configure
the LINDLR register, either LRXDL[3..0] for Rx Response either LTXDL[3..0] for Tx Response.
When the command starts, the controller checks the LIN13 bit of the LINCR register to apply
the right rule for computing the checksum. Checksum calculation over the DATA bytes and the
PROTECTED IDENTIFIER byte is called enhanced checksum and it is used for communica-
tion with LIN 2.1 slaves. Checksum calculation over the DATA bytes only is called classic
checksum and it is used for communication with LIN 1.3 slaves. Note that identifiers 60 (0x3C)
to 63 (0x3F) shall always use classic checksum.
At the end of this reception or transmission, the controller automatically returns to Rx Header /
LIN Abort state (i.e. LCMD[1..0] = 00) after setting the appropriate flags.
If an LIN error occurs, the reception or the transmission is stopped, the appropriate flags are
set and the LIN bus is left to recessive state.
During these functions, the controller is responsible for:
• The initialization of the checksum operator,
• The transmission or the reception of ‘n’ data with the update of the checksum calculation,
• The transmission or the checking of the CHECKSUM field,
• The checking of the Frame_Time_Out,
• The checking of the LIN communication integrity.
While the controller is sending or receiving a response, BREAK and SYNCH fields can be
detected and the identifier of this new header will be recorded. Of course, specific errors on
the previous response will be maintained with this identifier reception.
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15.4.6.4
Handling Data of LIN response
A FIFO data buffer is used for data of the LIN response. After setting all parameters in the LIN-
SEL register, repeated accesses to the LINDAT register perform data read or data write (c.f.
“Data Management” on page 182).
Note that LRXDL[3..0] and LTXDL[3..0] are not linked to the data access.
15.4.7
UART Commands
Setting the LCMD[2] bit in LINENR register enables UART commands.
Tx Byte and Rx Byte services are independent as shown in Table 15-1 on page 170.
• Byte Transfer: the UART is selected but both Rx and Tx services are disabled,
• Rx Byte: only the Rx service is enable but Tx service is disabled,
• Tx Byte: only the Tx service is enable but Rx service is disabled,
• Full Duplex: the UART is selected and both Rx and Tx services are enabled.
This combination of services is controlled by the LCMD[1..0] bits of LINENR register (c.f. Fig-
ure 15-5 on page 169).
15.4.7.1
15.4.7.2
Data Handling
Rx Service
The FIFO used for LIN communication is disabled during UART accesses. LRXDL[3..0] and
LTXDL[3..0] values of LINDLR register are then irrelevant. LINDAT register is then used as
data register and LINSEL register is not relevant.
Once this service is enabled, the user is warned of an in-coming character by the LRXOK flag
of LINSIR register. Reading LINDAT register automatically clears the flag and makes free the
second stage of the buffer. If the user considers that the in-coming character is irrelevant with-
out reading it, he directly can clear the flag (see specific flag management described in
Section 15.6.2 on page 185).
The intrinsic structure of the Rx service offers a 2-byte buffer. The fist one is used for serial to
parallel conversion, the second one receives the result of the conversion. This second buffer
byte is reached reading LINDAT register. If the 2-byte buffer is full, a new in-coming character
will overwrite the second one already recorded. An OVRERR error in LINERR register will
then accompany this character when read.
A FERR error in LINERR register will be set in case of framing error.
15.4.7.3
Tx Service
If this service is enabled, the user sends a character by writing in LINDAT register. Automati-
cally the LTXOK flag of LINSIR register is cleared. It will rise at the end of the serial
transmission. If no new character has to be sent, LTXOK flag can be cleared separately (see
specific flag management described in Section 15.6.2 on page 185).
There is no transmit buffering.
No error is detected by this service.
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15.5 LIN / UART Description
15.5.1
Reset
The Atmel® AVR® core reset logic signal also resets the LIN/UART controller. Another form of
reset exists, a software reset controlled by LSWRES bit in LINCR register. This self-reset bit
performs a partial reset as shown in Table 15-2.
Table 15-2. Reset of LIN/UART Registers
Register
Name
LINCR
Reset Value
0000 0000 b
0000 0000 b
0000 0000 b
0000 0000 b
0010 0000 b
0000 0000 b
0000 0000 b
0000 0000 b
1000 0000 b
0000 0000 b
0000 0000 b
LSWRES Value
0000 0000 b
0000 0000 b
xxxx 0000 b
0000 0000 b
0010 0000 b
uuuu uuuu b
xxxx uuuu b
0000 0000 b
1000 0000 b
xxxx 0000 b
0000 0000 b
Comment
LIN Control Reg.
LIN Status & Interrupt Reg.
LIN Enable Interrupt Reg.
LIN Error Reg.
LINSIR
LINENIR
LINERR
LINBTR
LINBRRL
LINBRRH
LINDLR
LINIDR
x=unknown
LIN Bit Timing Reg.
LIN Baud Rate Reg. Low
LIN Baud Rate Reg. High
LIN Data Length Reg.
LIN Identifier Reg.
u=unchanged
LIN Data Buffer Selection
LIN Data
LINSEL
LINDAT
15.5.2
15.5.3
Clock
The I/O clock signal (clki/o) also clocks the LIN/UART controller. It is its unique clock.
LIN Protocol Selection
LIN13 bit in LINCR register is used to select the LIN protocol:
• LIN13 = 0 (default): LIN 2.1 protocol,
• LIN13 = 1: LIN 1.3 protocol.
The controller checks the LIN13 bit in computing the checksum (enhanced checksum in
LIN2.1 / classic checksum in LIN 1.3).
This bit is irrelevant for UART commands.
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15.5.4
Configuration
Depending on the mode (LIN or UART), LCONF[1..0] bits of the LINCR register set the con-
troller in the following configuration (Table 15-3):
Table 15-3. Configuration Table versus Mode
Mode
LCONF[1..0]
00 b
Configuration
LIN standard configuration (default)
No CRC field detection or transmission
Frame_Time_Out disable
01 b
LIN
10 b
11 b
Listening mode
00 b
8-bit data, no parity & 1 stop-bit
8-bit data, even parity & 1 stop-bit
8-bit data, odd parity & 1 stop-bit
Listening mode, 8-bit data, no parity & 1 stop-bit
01 b
UART
10 b
11 b
The LIN configuration is independent of the programmed LIN protocol.
The listening mode connects the internal Tx LIN and the internal Rx LIN together. In this
mode, the TXLIN output pin is disabled and the RXLIN input pin is always enabled. The same
scheme is available in UART mode.
Figure 15-6. Listening Mode
internal
Tx LIN
TXLIN
RXLIN
LISTEN
internal
1
0
Rx LIN
15.5.5
Busy Signal
LBUSY bit flag in LINSIR register is the image of the BUSY signal. It is set and cleared by
hardware. It signals that the controller is busy with LIN or UART communication.
15.5.5.1
Busy Signal in LIN Mode
Figure 15-7. Busy Signal in LIN Mode
FRAME SLOT
HEADER
RESPONSE
PROTECTED
IDENTIFIER
BREAK
SYNC
DATA-0
DATA-n
CHECKSUM
LIN bus
Field
Field
Field
Field
Field
Field
1) LBUSY
2) LBUSY
3) LBUSY
Node providing the master task
Node providing a slave task
Node providing neither the master task, neither a slave task
LIDOK LCMD=Tx or Rx Response
LCMD=Tx Header
LTXOK or LRXOK
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When the busy signal is set, some registers are locked, user writing is not allowed:
• “LIN Control Register” - LINCR - except LCMD[2..0], LENA & LSWRES,
• “LIN Baud Rate Registers” - LINBRRL & LINBRRH,
• “LIN Data Length Register” - LINDLR,
• “LIN Identifier Register” - LINIDR,
• “LIN Data Register” - LINDAT.
If the busy signal is set, the only available commands are:
• LCMD[1..0] = 00 b, the abort command is taken into account at the end of the byte,
• LENA = 0 and/or LCMD[2] = 0, the kill command is taken into account immediately,
• LSWRES = 1, the reset command is taken into account immediately.
Note that, if another command is entered during busy signal, the new command is not vali-
dated and the LOVRERR bit flag of the LINERR register is set. The on-going transfer is not
interrupted.
15.5.5.2
Busy Signal in UART Mode
During the byte transmission, the busy signal is set. This locks some registers from being
written:
• “LIN Control Register” - LINCR - except LCMD[2..0], LENA & LSWRES,
• “LIN Data Register” - LINDAT.
The busy signal is not generated during a byte reception.
15.5.6
Bit Timing
Baud rate Generator
15.5.6.1
The baud rate is defined to be the transfer rate in bits per second (bps):
• BAUD: Baud rate (in bps),
• fclk : System I/O clock frequency,
i/o
• LDIV[11..0]: Contents of LINBRRH & LINBRRL registers - (0-4095), the pre-scaler
receives clk as input clock.
i/o
• LBT[5..0]: Least significant bits of - LINBTR register- (0-63) is the number of samplings in a
LIN or UART bit (default value 32).
Equation for calculating baud rate:
BAUD = fclk
/ LBT[5..0] x (LDIV[11..0] + 1)
i/o
Equation for setting LINDIV value:
LDIV[11..0] = ( fclk
/ LBT[5..0] x BAUD ) - 1
i/o
Note that in reception a majority vote on three samplings is made.
15.5.6.2
Re-synchronization in LIN Mode
When waiting for Rx Header, LBT[5..0] = 32 in LINBTR register. The re-synchronization
begins when the BREAK is detected. If the BREAK size is not in the range (10.5 bits min., 28
bits max. — 13 bits nominal), the BREAK is refused. The re-synchronization is done by adjust-
ing LBT[5..0] value to the SYNCH field of the received header (0x55). Then the PROTECTED
IDENTIFIER is sampled using the new value of LBT[5..0].
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The re-synchronization implemented in the controller tolerates a clock deviation of ± 20% and
adjusts the baud rate in a ± 2% range.
The new LBT[5..0] value will be used up to the end of the response. Then, the LBT[5..0] will be
reset to 32 for the next header.
The LINBTR register can be used to (software) re-calibrate the clock oscillator.
The re-synchronization is not performed if the LIN node is enabled as a master.
15.5.6.3
Handling LBT[5..0]
LDISR bit of LINBTR register is used to:
• Disable the re-synchronization (for instance in the case of LIN MASTER node),
• To enable the setting of LBT[5..0] (to manually adjust the baud rate especially in the case of
UART mode). A minimum of 8 is required for LBT[5..0] due to the sampling operation.
Note that the LENA bit of LINCR register is important for this handling (see Figure 15-8 on
page 176).
Figure 15-8. Handling LBT[5..0]
Write in LINBTR register
=1
LENA ?
=0
(LINCR bit 4)
=1
LDISR
to write
=0
LBT[5..0] = LBT[5..0] to write
(LBT[5..0]min=8)
LBT[5..0] forced to 0x20
LDISR forced to 0
LDISR forced to 1
Disable re-synch. in LIN mode
Enable re-synch. in LIN mode
15.5.7
Data Length
Section 15.4.6 “LIN Commands” on page 170 describes how to set or how are automatically
set the LRXDL[3..0] or LTXDL[3..0] fields of LINDLR register before receiving or transmitting a
response.
In the case of Tx Response the LRXDL[3..0] will be used by the hardware to count the number
of bytes already successfully sent.
In the case of Rx Response the LTXDL[3..0] will be used by the hardware to count the number
of bytes already successfully received.
If an error occurs, this information is useful to the programmer to recover the LIN messages.
15.5.7.1
Data Length in LIN 2.1
• If LTXDL[3..0]=0 only the CHECKSUM will be sent,
• If LRXDL[3..0]=0 the first byte received will be interpreted as the CHECKSUM,
• If LTXDL[3..0] or LRXDL[3..0] >8, values will be forced to 8 after the command setting and
before sending or receiving of the first byte.
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15.5.7.2
15.5.7.3
Data Length in LIN 1.3
• LRXDL and LTXDL fields are both hardware updated before setting LIDOK by decoding the
data length code contained in the received PROTECTED IDENTIFIER (LRXDL = LTXDL).
• Via the above mechanism, a length of 0 or >8 is not possible.
Data Length in Rx Response
Figure 15-9. LIN2.1 - Rx Response - No error
LIDOK
LRXOK
st
nd
rd
th
4 Byte
1
Byte
2
Byte
3
Byte
DATA-0
DATA-1
DATA-2
DATA-3
CHECKSUM
LIN bus
LRXDL (*)
LTXDL (*)
LBUSY
4
?
0
1
2
3
4
LCMD=Rx Response
LCMD2..0=000
b
LINDLR=0x?4
(*) : LRXDL & LTXDL updated by user
• The user initializes LRXDL field before setting the Rx Response command,
• After setting the Rx Response command, LTXDL is reset by hardware,
• LRXDL field will remain unchanged during Rx (during busy signal),
• LTXDL field will count the number of received bytes (during busy signal),
• If an error occurs, Rx stops, the corresponding error flag is set and LTXDL will give the
number of received bytes without error,
• If no error occurs, LRXOK is set after the reception of the CHECKSUM, LRXDL will be
unchanged (and LTXDL = LRXDL).
15.5.7.4
Data Length in Tx Response
Figure 15-10. LIN1.3 - Tx Response - No error
LIDOK
LTXOK
st
nd
rd
th
4 Byte
1
Byte
2
Byte
3
Byte
DATA-0
0
DATA-1
1
DATA-2
2
DATA-3
3
CHECKSUM
4
LIN bus
LRXDL (*)
LTXDL (*)
LBUSY
4
4
LCMD2..0=000
b
LCMD=Tx Response
(*) : LRXDL & LTXDL updated by Rx Response or Tx Response task
• The user initializes LTXDL field before setting the Tx Response command,
• After setting the Tx Response command, LRXDL is reset by hardware,
• LTXDL will remain unchanged during Tx (during busy signal),
• LRXDL will count the number of transmitted bytes (during busy signal),
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• If an error occurs, Tx stops, the corresponding error flag is set and LRXDL will give the
number of transmitted bytes without error,
• If no error occurs, LTXOK is set after the transmission of the CHECKSUM, LTXDL will be
unchanged (and LRXDL = LTXDL).
15.5.7.5
Data Length after Error
Figure 15-11. Tx Response - Error
LERR
st
nd
rd
3 Byte
1
Byte
2
Byte
DATA-0
0
DATA-1
1
DATA-2
ERROR
LIN bus
LRXDL
LTXDL
LBUSY
4
4
2
LCMD2..0=000
b
LCMD=Tx Response
Note:
Information on response (ex: error on byte) is only available at the end of the serializa-
tion/de-serialization of the byte.
15.5.7.6
Data Length in UART Mode
• The UART mode forces LRXDL and LTXDL to 0 and disables the writing in LINDLR
register,
• Note that after reset, LRXDL and LTXDL are also forced to 0.
15.5.8
xxOK Flags
There are three xxOK flags in LINSIR register:
• LIDOK: LIN IDentifier OK
It is set at the end of the header, either by the Tx Header function or by the Rx Header. In
LIN 1.3, before generating LIDOK, the controller updates the LRXDL & LTXDL fields in
LINDLR register.
It is not driven in UART mode.
• LRXOK: LIN RX response complete
It is set at the end of the response by the Rx Response function in LIN mode and once a
character is received in UART mode.
• LTXOK: LIN TX response complete
It is set at the end of the response by the Tx Response function in LIN mode and once a
character has been sent in UART mode.
These flags can generate interrupts if the corresponding enable interrupt bit is set in the LINE-
NIR register (see Section 15.5.13 “Interrupts” on page 181).
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15.5.9
xxERR Flags
LERR bit of the LINSIR register is an logical ‘OR’ of all the bits of LINERR register (see Sec-
tion 15.5.13 “Interrupts” on page 181). There are eight flags:
• LBERR = LIN Bit ERRor.
A unit that is sending a bit on the bus also monitors the bus. A LIN bit error will be flagged
when the bit value that is monitored is different from the bit value that is sent. After
detection of a LIN bit error the transmission is aborted.
• LCERR = LIN Checksum ERRor.
A LIN checksum error will be flagged if the inverted modulo-256 sum of all received data
bytes (and the protected identifier in LIN 2.1) added to the checksum does not result in
0xFF.
• LPERR = LIN Parity ERRor (identifier).
A LIN parity error in the IDENTIFIER field will be flagged if the value of the parity bits does
not match with the identifier value. (See LP[1:0] bits in Section 15.6.8 “LIN Identifier
Register - LINIDR” on page 189). A LIN slave application does not distinguish between
corrupted parity bits and a corrupted identifier. The hardware does not undertake any
correction. However, the LIN slave application has to solve this as:
- known identifier (parity bits corrupted),
- or corrupted identifier to be ignored,
- or new identifier.
• LSERR = LIN Synchronization ERRor.
A LIN synchronization error will be flagged if a slave detects the edges of the SYNCH field
outside the given tolerance.
• LFERR = LIN Framing ERRor.
A framing error will be flagged if dominant STOP bit is sampled.
Same function in UART mode.
• LTOERR = LIN Time Out ERRor.
A time-out error will be flagged if the MESSAGE frame is not fully completed within the
maximum length T Frame_Maximum by any slave task upon transmission of the SYNCH and
IDENTIFIER fields (see Section 15.5.10 “Frame Time Out” on page 180).
• LOVERR = LIN OVerrun ERRor.
Overrun error will be flagged if a new command (other than LIN Abort) is entered while
‘Busy signal’ is present.
In UART mode, an overrun error will be flagged if a received byte overwrites the byte stored
in the serial input buffer.
• LABORT
LIN abort transfer reflects a previous LIN Abort command (LCMD[2..0] = 000) while ‘Busy
signal’ is present.
After each LIN error, the LIN controller stops its previous activity and returns to its withdrawal
mode (LCMD[2..0] = 000 b) as illustrated in Figure 15-11 on page 178.
Writing 1 in LERR of LINSIR register resets LERR bit and all the bits of the LINERR register.
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15.5.10 Frame Time Out
According to the LIN protocol, a frame time-out error is flagged if: T Frame > T Frame_Maximum
.
This feature is implemented in the LIN/UART controller.
Figure 15-12. LIN timing and frame time-out
T Frame
T Header
T Response
PROTECTED
IDENTIFIER
BREAK
SYNC
DATA-0
DATA-n
CHECKSUM
Field
Field
Field
Field
Field
Field
Nominal
T Header_Nominal
T Response_Nominal
T Frame_Nominal
=
=
34 x T Bit
10 ( Number_of_Data + 1 ) x T Bit
= T Header_Nominal + T Response_Nominal
Maximun before Time-out
T Header_Maximum
T Response_Maximum
T Frame_Maximum
=
=
1.4 x T Header_Nominal
1.4 x T Response_Nominal
= T Header_Maximum + T Response_Maximum
15.5.11 Break-in-data
According to the LIN protocol, the LIN/UART controller can detect the BREAK/SYNC field
sequence even if the break is partially superimposed with a byte of the response. When a
BREAK/SYNC field sequence happens, the transfer in progress is aborted and the processing
of the new frame starts.
• On slave node(s), an error is generated (i.e. LBERR in case of Tx Response or LFERR in
case of Rx Response). Information on data error is also available, refer to the Section
15.5.7.5.
• On master node, the user (code) is responsible for this aborting of frame. To do this, the
master task has first to abort the on-going communication (clearing LCMD bits - LIN Abort
command) and then to apply the Tx Header command. In this case, the abort error flag -
LABORT - is set.
On the slave node, the BREAK detection is processed with the synchronization setting avail-
able when the LIN/UART controller processed the (aborted) response. But the
re-synchronization restarts as usual. Due to a possible difference of timing reference between
the BREAK field and the rest of the frame, the time-out values can be slightly inaccurate.
15.5.12 Checksum
The last field of a frame is the checksum.
In LIN 2.1, the checksum contains the inverted eight bit sum with carry over all data bytes and
the protected identifier. This calculation is called enhanced checksum.
n
n
CHECKSUM = 255 – unsigned char
DATA
+ PROTECTED ID. + unsigned char
DATA
+ PROTECTED ID. » 8
n
∑
∑
n
0
0
In LIN 1.3, the checksum contains the inverted eight bit sum with carry over all data bytes.
This calculation is called classic checksum.
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n
n
CHECKSUM = 255 – unsigned char DATAn + unsigned char
DATAn » 8
∑
∑
0
0
Frame identifiers 60 (0x3C) to 61 (0x3D) shall always use classic checksum.
15.5.13 Interrupts
As shown in Figure 15-13 on page 181, the four communication flags of the LINSIR register
are combined to drive two interrupts. Each of these flags have their respective enable interrupt
bit in LINENIR register.
(see Section 15.5.8 “xxOK Flags” on page 178 and Section 15.5.9 “xxERR Flags” on page
179).
Figure 15-13. LIN Interrupt Mapping
LINERR.7
LABORT
LINERR.6
LTOERR
LINERR.5
LOVERR
LINERR.4
LINERR.3
LINERR.2
LINERR.1
LINERR.0
LINSIR.3
LFERR
LSERR
LPERR
LCERR
LBERR
LIN ERR
LERR
LINENIR.3
LINENIR.2
LINENIR.1
LINENIR.0
LENERR
LENIDOK
LENTXOK
LENRXOK
LINSIR.2
LINSIR.1
LINSIR.0
LIDOK
LTXOK
LRXOK
LIN TC
15.5.14 Message Filtering
Message filtering based upon the whole identifier is not implemented. Only a status for frame
headers having 0x3C, 0x3D, 0x3E and 0x3F as identifier is available in the LINSIR register.
Table 15-4. Frame Status
LIDST[2..0]
0xx b
Frame Status
No specific identifier
60 (0x3C) identifier
61 (0x3D) identifier
62 (0x3E) identifier
63 (0x3F) identifier
100 b
101 b
110 b
111 b
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The LIN protocol says that a message with an identifier from 60 (0x3C) up to 63 (0x3F) uses a
classic checksum (sum over the data bytes only). Software will be responsible for switching
correctly the LIN13 bit to provide/check this expected checksum (the insertion of the ID field in
the computation of the CRC is set - or not - just after entering the Rx or Tx Response
command).
15.5.15 Data Management
15.5.15.1
LIN FIFO Data Buffer
To preserve register allocation, the LIN data buffer is seen as a FIFO (with address pointer
accessible). This FIFO is accessed via the LINDX[2..0] field of LINSEL register through the
LINDAT register.
LINDX[2..0], the data index, is the address pointer to the required data byte. The data byte can
be read or written. The data index is automatically incremented after each LINDAT access if
the LAINC (active low) bit is cleared. A roll-over is implemented, after data index=7 it is data
index=0. Otherwise, if LAINC bit is set, the data index needs to be written (updated) before
each LINDAT access.
The first byte of a LIN frame is stored at the data index=0, the second one at the data index=1,
and so on. Nevertheless, LINSEL must be initialized by the user before use.
15.5.15.2
UART Data Register
The LINDAT register is the data register (no buffering - no FIFO). In write access, LINDAT will
be for data out and in read access, LINDAT will be for data in.
In UART mode the LINSEL register is unused.
15.5.16 OCD Support
When a debugger break occurs, the state machine of the LIN/UART controller is stopped
(included frame time-out) and further communication may be corrupted.
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15.6 LIN / UART Register Description
Table 15-5. LIN/UART Register Bits Summary
Name
Bit 7
LSWRES
R/W
LIDST2
R
Bit 6
Bit 5
LCONF1
R/W
Bit 4
LCONF0
R/W
LBUSY
R
Bit 3
Bit 2
LCMD2
R/W
Bit 1
LCMD1
R/W
Bit 0
LCMD0
R/W
LIN13
LENA
LINCR
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W
LERR
R/Wone
0
0
0
0
0
0
LIDST1
LIDST0
R
LIDOK
R/Wone
LTXOK
R/Wone
LRXOK
R/Wone
LINSIR
LINENIR
LINERR
LINBTR
LINBRRL
LINBRRH
LINDLR
LINIDR
R
—
—
—
—
LENERR
R/W
LENIDOK
LENTXOK
LENRXOK
R
R
LTOERR
R
R
R
0
R/W
LPERR
R
0
R/W
LCERR
R
0
R/W
LBERR
R
LABORT
R
LOVERR
R
LFERR
R
LSERR
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
LDISR
R/W
LDIV7
R/W
—
LBT5
R/(W)
LDIV5
R/W
LBT4
R/(W)
LDIV4
R/W
—
LBT3
R/(W)
LDIV3
R/W
LBT2
R/(W)
LDIV2
R/W
LBT1
R/(W)
LDIV1
R/W
LBT0
R/(W)
LDIV0
R/W
R
LDIV6
R/W
—
—
LDIV11
R/W
LDIV10
R/W
LDIV9
R/W
LDIV8
R/W
R
R
R
R
LTXDL3
R/W
LP1
LTXDL2
R/W
LP0
R
LTXDL1
R/W
LTXDL0
R/W
LRXDL3
R/W
LRXDL2
R/W
LRXDL1
R/W
LRXDL0
R/W
LID5/LDL1
R/W
LID4/LDL0
R/W
LID3
LID2
LID1
LID0
R
0
0
R/W
R/W
R/W
R/W
—
—
—
—
LAINC
R/W
LINDX2
R/W
LINDX1
R/W
LINDX0
R/W
LINSEL
LINDAT
R
R
0
0
R
LDATA5
R/W
0
0
R
LDATA4
R/W
LDATA7
R/W
LDATA6
R/W
LDATA3
R/W
LDATA2
R/W
LDATA1
R/W
LDATA0
R/W
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15.6.1
LIN Control Register - LINCR
Bit
7
LSWRES
R/W
6
LIN13
R/W
0
5
LCONF1
R/W
4
LCONF0
R/W
3
LENA
R/W
0
2
LCMD2
R/W
0
1
LCMD1
R/W
0
0
LCMD0
R/W
0
LINCR
Read/Write
Initial Value
0
0
0
• Bit 7 - LSWRES: Software Reset
– 0 = No action,
– 1 = Software reset (this bit is self-reset at the end of the reset procedure).
• Bit 6 - LIN13: LIN 1.3 mode
– 0 = LIN 2.1 (default),
– 1 = LIN 1.3.
• Bit 5:4 - LCONF[1:0]: Configuration
a. LIN mode (default = 00):
– 00 = LIN Standard configuration (listen mode “off”, CRC “on” & Frame_Time_Out
“on”,
– 01 = No CRC, No Frame_Time_Out (listen mode “off”),
– 10 = No Frame_Time_Out (listen mode “off” & CRC “on”),
– 11 = Listening mode (CRC “on” & Frame_Time_Out “on”).
b. UART mode (default = 00):
– 00 = 8-bit, no parity (listen mode “off”),
– 01 = 8-bit, even parity (listen mode “off”),
– 10 = 8-bit, odd parity (listen mode “off”),
– 11 = Listening mode, 8-bit, no parity.
• Bit 3 - LENA: Enable
– 0 = Disable (both LIN and UART modes),
– 1 = Enable (both LIN and UART modes).
• Bit 2:0 - LCMD[2..0]: Command and mode
The command is only available if LENA is set.
– 000 = LIN Rx Header - LIN abort,
– 001 = LIN Tx Header,
– 010 = LIN Rx Response,
– 011 = LIN Tx Response,
– 100 = UART Rx & Tx Byte disable,
– 11x = UART Rx Byte enable,
– 1x1 = UART Tx Byte enable.
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15.6.2
LIN Status and Interrupt Register - LINSIR
Bit
7
6
5
4
3
LERR
R/Wone
0
2
1
0
LIDST2
LIDST1
LIDST0
LBUSY
LIDOK
R/Wone
0
LTXOK
R/Wone
0
LRXOK
R/Wone
0
LINSIR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
• Bits 7:5 - LIDST[2:0]: Identifier Status
– 0xx = no specific identifier,
– 100 = Identifier 60 (0x3C),
– 101 = Identifier 61 (0x3D),
– 110 = Identifier 62 (0x3E),
– 111 = Identifier 63 (0x3F).
• Bit 4 - LBUSY: Busy Signal
– 0 = Not busy,
– 1 = Busy (receiving or transmitting).
• Bit 3 - LERR: Error Interrupt
It is a logical OR of LINERR register bits. This bit generates an interrupt if its respective
enable bit - LENERR - is set in LINENIR.
– 0 = No error,
– 1 = An error has occurred.
The user clears this bit by writing 1 in order to reset this interrupt. Resetting LERR also
resets all LINERR bits.
In UART mode, this bit is also cleared by reading LINDAT.
• Bit 2 - LIDOK: Identifier Interrupt
This bit generates an interrupt if its respective enable bit - LENIDOK - is set in LINENIR.
– 0 = No identifier,
– 1 = Slave task: Identifier present, master task: Tx Header complete.
The user clears this bit by writing 1, in order to reset this interrupt.
• Bit 1 - LTXOK: Transmit Performed Interrupt
This bit generates an interrupt if its respective enable bit - LENTXOK - is set in
LINENIR.
– 0 = No Tx,
– 1 = Tx Response complete.
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by writing LINDAT.
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• Bit 0 - LRXOK: Receive Performed Interrupt
This bit generates an interrupt if its respective enable bit - LENRXOK - is set in
LINENIR.
– 0 = No Rx
– 1 = Rx Response complete.
The user clears this bit by writing 1, in order to reset this interrupt.
In UART mode, this bit is also cleared by reading LINDAT.
15.6.3
LIN Enable Interrupt Register - LINENIR
Bit
7
-
R
0
6
-
R
0
5
-
R
0
4
-
R
0
3
LENERR
R/W
2
LENIDOK
R/W
1
LENTXOK
R/W
0
LENRXOK LINENIR
Read/Write
Initial Value
R/W
0
0
0
0
• Bits 7:4 - Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be
written to zero when LINENIR is written.
• Bit 3 - LENERR: Enable Error Interrupt
– 0 = Error interrupt masked,
– 1 = Error interrupt enabled.
• Bit 2 - LENIDOK: Enable Identifier Interrupt
– 0 = Identifier interrupt masked,
– 1 = Identifier interrupt enabled.
• Bit 1 - LENTXOK: Enable Transmit Performed Interrupt
– 0 = Transmit performed interrupt masked,
– 1 = Transmit performed interrupt enabled.
• Bit 0 - LENRXOK: Enable Receive Performed Interrupt
– 0 = Receive performed interrupt masked,
– 1 = Receive performed interrupt enabled.
15.6.4
LIN Error Register - LINERR
Bit
7
6
5
4
3
2
1
0
LABORT
LTOERR
LOVERR
LFERR
LSERR
LPERR
LCERR
LBERR LINERR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R
0
R
0
R
0
• Bit 7 - LABORT: Abort Flag
– 0 = No warning,
– 1 = LIN abort command occurred.
This bit is cleared when LERR bit in LINSIR is cleared.
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• Bit 6 - LTOERR: Frame_Time_Out Error Flag
– 0 = No error,
– 1 = Frame_Time_Out error.
This bit is cleared when LERR bit in LINSIR is cleared.
• Bit 5 - LOVERR: Overrun Error Flag
– 0 = No error,
– 1 = Overrun error.
This bit is cleared when LERR bit in LINSIR is cleared.
• Bit 4 - LFERR: Framing Error Flag
– 0 = No error,
– 1 = Framing error.
This bit is cleared when LERR bit in LINSIR is cleared.
• Bit 3 - LSERR: Synchronization Error Flag
– 0 = No error,
– 1 = Synchronization error.
This bit is cleared when LERR bit in LINSIR is cleared.
• Bit 2 - LPERR: Parity Error Flag
– 0 = No error,
– 1 = Parity error.
This bit is cleared when LERR bit in LINSIR is cleared.
• Bit 1 - LCERR: Checksum Error Flag
– 0 = No error,
– 1 = Checksum error.
This bit is cleared when LERR bit in LINSIR is cleared.
• Bit 0 - LBERR: Bit Error Flag
– 0 = no error,
– 1 = Bit error.
This bit is cleared when LERR bit in LINSIR is cleared.
15.6.5
LIN Bit Timing Register - LINBTR
Bit
7
6
-
5
4
3
2
1
0
LDISR
R/W
0
LBT5
R/(W)
1
LBT4
R/(W)
0
LBT3
R/(W)
0
LBT2
R/(W)
0
LBT1
R/(W)
0
LBT0
R/(W)
0
LINBTR
Read/Write
Initial Value
R
0
• Bit 7 - LDISR: Disable Bit Timing Re synchronization
– 0 = Bit timing re-synchronization enabled (default),
– 1 = Bit timing re-synchronization disabled.
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• Bits 5:0 - LBT[5:0]: LIN Bit Timing
Gives the number of samples of a bit.
sample-time = (1 / fclki/o ) x (LDIV[11..0] + 1)
Default value: LBT[6:0]=32 — Min. value: LBT[6:0]=8 — Max. value: LBT[6:0]=63
15.6.6
LIN Baud Rate Register - LINBRR
Bit
7
LDIV7
-
6
LDIV6
-
5
LDIV5
-
4
LDIV4
-
3
LDIV3
LDIV11
11
2
LDIV2
LDIV10
10
1
LDIV1
LDIV9
9
0
LDIV0
LDIV8
8
LINBRRL
LINBRRH
Bit
15
14
13
12
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bits 15:12 - Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be
written to zero when LINBRR is written.
• Bits 11:0 - LDIV[11:0]: Scaling of clki/o Frequency
The LDIV value is used to scale the entering clki/o frequency to achieve appropriate LIN or
UART baud rate.
15.6.7
LIN Data Length Register - LINDLR
Bit
7
6
LTXDL2
R/W
0
5
LTXDL1
R/W
0
4
LTXDL0
R/W
0
3
LRXDL3
R/W
2
LRXDL2
R/W
1
LRXDL1
R/W
0
LRXDL0
R/W
LTXDL3
R/W
0
LINDLR
Read/Write
Initial Value
0
0
0
0
• Bits 7:4 - LTXDL[3:0]: LIN Transmit Data Length
In LIN mode, this field gives the number of bytes to be transmitted (clamped to 8 Max).
In UART mode this field is unused.
• Bits 3:0 - LRXDL[3:0]: LIN Receive Data Length
In LIN mode, this field gives the number of bytes to be received (clamped to 8 Max).
In UART mode this field is unused.
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15.6.8
LIN Identifier Register - LINIDR
Bit
7
6
5
4
3
2
1
0
LID5 /
LDL1
LID4 /
LDL0
LP1
LP0
LID3
LID2
LID1
LID0
LINIDR
Read/Write
Initial Value
R
0
R
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bits 7:6 - LP[1:0]: Parity
In LIN mode:
LP0 = LID4 ^ LID2 ^ LID1 ^ LID0
LP1 = ! ( LID1 ^ LID3 ^ LID4 ^ LID5 )
In UART mode this field is unused.
• Bits 5:4 - LDL[1:0]: LIN 1.3 Data Length
In LIN 1.3 mode:
– 00 = 2-byte response,
– 01 = 2-byte response,
– 10 = 4-byte response,
– 11 = 8-byte response.
In UART mode this field is unused.
• Bits 3:0 - LID[3:0]: LIN 1.3 Identifier
In LIN 1.3 mode: 4-bit identifier.
In UART mode this field is unused.
• Bits 5:0 - LID[5:0]: LIN 2.1 Identifier
In LIN 2.1 mode: 6-bit identifier (no length transported).
In UART mode this field is unused.
15.6.9
LIN Data Buffer Selection Register - LINSEL
Bit
7
6
5
-
4
-
3
LAINC
R/W
0
2
LINDX2
R/W
0
1
LINDX1
R/W
0
0
LINDX0
R/W
0
-
-
LINSEL
Read/Write
Initial Value
-
-
-
-
-
-
-
-
• Bits 7:4 - Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be
written to zero when LINSEL is written.
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• Bit 3 - LAINC: Auto Increment of Data Buffer Index
In LIN mode:
– 0 = Auto incrementation of FIFO data buffer index (default),
– 1 = No auto incrementation.
In UART mode this field is unused.
• Bits 2:0 - LINDX 2:0: FIFO LIN Data Buffer Index
In LIN mode: location (index) of the LIN response data byte into the FIFO data buffer.
The FIFO data buffer is accessed through LINDAT.
In UART mode this field is unused.
15.6.10 LIN Data Register - LINDAT
Bit
7
LDATA7
R/W
0
6
LDATA6
R/W
0
5
LDATA5
R/W
0
4
LDATA4
R/W
0
3
LDATA3
R/W
0
2
LDATA2
R/W
0
1
LDATA1
R/W
0
0
LDATA0
R/W
0
LINDAT
Read/Write
Initial Value
• Bits 7:0 - LDATA[7:0]: LIN Data In / Data out
In LIN mode: FIFO data buffer port.
In UART mode: data register (no data buffer - no FIFO).
– In Write access, data out.
– In Read access, data in.
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Atmel ATA5505 [Preliminary]
16. Reader/Writer Front End
16.1 Power Supply (PS)
Figure 16-1. Equivalent Circuit of Power Supply and Antenna Driver
DVS
VEXT
VS
VBatt
Frontend
Standby
Power supply
Driver
MS
COIL1
= 1
Control (0 to 3)
CFE
Frequency
adjustment
COIL2
DGND
&
Oscillator
RF
Output
Input
Lowpass filter
Schmitt trigger
&
OE
HIPASS
The reader front end can be operated with one external supply voltage or with two exter-
nally-stabilized supply volt-ages for extended driver output voltage or be operated from 12V
vehicle battery voltage. The 12V supply capability is achieved via the on-chip power supply
(see Figure 16-1). The power supply provides two different output voltages, VS and VEXT
.
VS is the internal power supply voltage for everything except the driver circuit. Pin VS is used
to connect a block capacitor. VS can be switched off via the STANDBY pin. In standby mode,
the reader front end’s power consumption is very low. VEXT is the supply voltage of the
antenna’s pre-driver. This voltage can also be used to operate external circuits. In conjunction
with an external NPN transistor, it also establishes the supply voltage of the antenna coil
driver, DVS.
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16.2 Operation Modes for Powering the Reader/Writer Front End
The following section explains the three different operation modes used to power the
Reader/Writer front end.
16.2.1
5V Operation
In this mode all internal circuits are operated from one 5V power rail (see Figure 16-2). In this
case, VS, VEXT and DVS serve as inputs. VBatt is not used but should also be connected to the
5V supply rail.
Figure 16-2. 5V Supply
+5V (stabilized)
+
DVS VEXT
VS VBatt Standby
16.2.2
Increased Power Operation
In this mode the driver voltage, DVS, and the pre-driver supply, VEXT, are operated at a higher
voltage than the rest of the circuitry to obtain a higher driver-output swing and thus a higher
magnetic field (see Figure 16-3). The internal supply voltage VS is derived from VBatt input volt-
age and needs capacitor circuitry, at VS pin for blocking. This operation mode is intended for
use in applications requiring extended communication distance.
Figure 16-3. 8V Supply
7V to 8V (stabilized)
+
+
DV
V
V
V
Batt
Standby
S
EXT
S
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Atmel ATA5505 [Preliminary]
16.2.3
Car Battery-voltage Operation
In this operation mode VS and VEXT are generated by the internal power supply, no external
voltage regulator is required. The IC can be switched off via the STANDBY pin. VEXT provides
the reference voltage for the external NPN transistor. In case of external use of VEXT a nega-
tive impact to the reader performance by the load has to be considered.
Pin VEXT and VBatt are overvoltage protected via internal Zener diodes (see Figure 16-1 on
page 191). The maximum current into the pins is determined by the IC’s maximum power dis-
sipation and maximum junction temperature.
Figure 16-4. Car Battery Operation
7V to 16V
+
+
+
DVS VEXT
VS
VBatt Standby
Table 16-1. Characteristics of the Various Operation Modes
Driver Output
Voltage Swing
Standby Mode
Available
Operation Mode
External Components Required
Supply-voltage Range
1 voltage regulator
1 capacitor
5V operation
5V ±10%
≈ 4V
No
1 voltage regulator
2 capacitors
Increased power operation
7V to 8V
6V to 7V
Yes
1 transistor
2 capacitors
Optional, for load dump protection:
1 resistor
Car battery-voltage
operation
6V to 16V
≈ 4V
Yes
1 capacitor
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16.3 Oscillator (Osc)
The frequency of the on-chip oscillator is controlled by a current fed into the RF input. An inte-
grated compensation circuit ensures a wide temperature range and a
supply-voltage-independent frequency which is selected by a fixed resistor between RF (pin
15) and VS (pin 14). For 125kHz, a resistor value of 110kΩ is defined. For other frequencies,
use the following formula:
14375
Rt[kΩ] = ----------------- – 5
f0[kHz]
This input can be used to adjust the frequency close to the resonance of the antenna.
Figure 16-5. Equivalent Circuit of the RF Pin
VS
Rf
2kΩ
RF
16.4 Low-pass Filter (LPF)
The fully integrated low-pass filter (4th-order Butterworth) removes the remaining carrier sig-
nal and high-frequency disturbances after demodulation. The upper cut-off frequency of the
LPF depends on the selected oscillator frequency. The typical value is fOsc/18. This means
data rates of up to fOsc/25 are possible if biphase or Manchester signal encoding is used.
A high-pass characteristic results from the capacitive coupling at the input pin 4 as shown in
Figure 16-6. The input voltage swing is limited to 2Vpp. For frequency response calculation, the
impedances of the signal source and LPF input (typically 210kΩ) have to be considered.
Figure 16-6. Equivalent Circuit of Pin Input
V
Bias + 0.4V
RS
Input
10kΩ
CIN
210kΩ
V
Bias - 0.4V
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Atmel ATA5505 [Preliminary]
16.5 Amplifier (AMP)
The differential amplifier has a fixed gain, typically 30. The HIPASS pin is used for DC decou-
pling. The lower cut-off frequency of the decoupling circuit can be calculated as follows:
1
fcut = --------------------------------------------
2 × π × CHP × Ri
The value of the internal resistor Ri can be assumed to be 2.5kΩ.
Figure 16-7. Equivalent Circuit of the HIPASS Pin
R
+
-
Schmitt
trigger
R
LPF
VRef
R
R
Ri
HIPASS
CHP
16.6 Antenna Resonant Loop Control
An improved read performance can be achieved by tracking the oscillator frequency to the res-
onant condition of the antenna LC tank.
Therefore the oscillator input is controlled by a loop circuitry according to Figure 16-8. It pro-
vides a bi-directional compensation current (Icomp) into RF pin in order to track the driver
frequency close to the resonant frequency of the antenna LC.
Figure 16-8. Circuitry for Antenna Resonant Frequency Tracking
IComp
R3 68kΩ
VS
D1
D2
C1
R4
43kΩ
4.7nF
R1 75kΩ
RF
R2 100kΩ
D3
D4
CAnt
Coil 1
Coil 2
LAnt
RAnt
Tap Point
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Application hint:
The value of the coupling capacity CIN is oriented on data rate to be transmit as well on the
recovery time needed after write command or power on. In automotive immobilizer applica-
tions it is needed for crypto processing to switch over from write to read mode with short
recovery time. Therefore, appropriate values are given by Table 16-2. In case of access con-
trol applications, whereas the recovery time has not so high, a bigger CIN value is
recommended to get an increased read performance.
Table 16-2. Recommended Capacitor Values
Data Rate f = 125 kHz
f / 32 = 3.9Kbits/s
Input Capacitor 8CIN)
Decoupling Capacitor (CHP)
680pF
1.2nF
100nF
220nF
f / 64 = 1.95Kbits/s
16.7 Schmitt Trigger
The signal is processed by a Schmitt trigger to suppress possible noise and to make the signal
microcontroller-compatible. The hysteresis level is 100mV applied symmetrically to the DC
operation point. The open-collector output is enabled by a low level at OE (pin 10).
Figure 16-9. Equivalent Circuit of Pin OE
7µA
OE
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Atmel ATA5505 [Preliminary]
16.8 Driver (DRV)
The driver supplies the antenna coil with the appropriate energy. The circuit consists of two
independent output stages. These output stages can be operated in two different modes. In
common mode, the outputs of the stages are in phase; in this mode the outputs can be inter-
connected to achieve high-current output capability. The output voltages are in anti-phase
when using the differential mode; the antenna coil is thus driven with a higher voltage. For a
specific magnetic field, the antenna coil impedance is higher for the differential mode.
Because higher coil impedance results in better system sensitivity, the differential mode
should be given preference.
The CFE input is intended for writing data to a read/write or a crypto transponder. This is done
by interrupting the RF field with short gaps. The various functions are controlled by the MS and
CFE inputs (see Table 16-3 on page 198). The equivalent circuit of the driver is shown in Fig-
ure 16-1 on page 191.
Figure 16-10. Equivalent Circuit of Pin MS
30µA
MS
Figure 16-11. Equivalent Circuit of Pin CFE
30 µA
CFE
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Table 16-3. Function Table
CFE
Low
Low
MS
Low
High
COIL1
High
COIL2
High
Low
High
High
High
Low
High
Reader/Writer
Front End
OE
Low
High
Output
Enabled
Disabled
STANDBY
Low
Standby mode
Active
High
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17. ISRC - Current Source
17.1 Features
• 100µA Constant current source
• ±10% Absolute Accuracy
The Atmel® AVR® features a 100µA ±10% Current Source. Up on request, the current is flow-
ing through an external resistor. The voltage can be measured on the dedicated pin shared
with the ADC. Using a resistor in series with a ≤ 0.5% tolerance is recommended. To protect
the device against big values, the ADC must be configured with AVCC as internal reference to
perform the first measurement. Afterwards, another internal reference can be chosen accord-
ing to the previous measured value to refine the result.
When ISRCEN bit is set, the ISRC pin sources 100µA. Otherwise this pin keeps its initial
function.
Figure 17-1. Current Source Block Diagram
AVCC
100 uA
ISRCEN
ADCn/ ISRC
ADC Input
External
Resistor
17.2 Typical Applications
17.2.1
LIN Current Source
During the configuration of a LIN node in a cluster, it may be necessary to attribute dynami-
cally an unique physical address to every cluster node. The way to do it is not described in the
LIN protocol.
The Current Source offers an excellent solution to associate a physical address to the applica-
tion supported by the LIN node. A full dynamic node configuration can be used to set-up the
LIN nodes in a cluster.
The Atmel AVR proposes to have an external resistor used in conjunction with the Current
Source. The device measures the voltage to the boundaries of the resistance via the Analog to
Digital converter. The resulting voltage defines the physical address that the communication
handler will use when the node will participate in LIN communication.
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In automotive applications, distributed voltages are very disturbed. The internal Current
Source solution of Atmel® AVR® immunizes the address detection the against any kind of volt-
age variations.
Table 17-1. Example of Resistor Values(±5%) for a 8-address System (AVCC = 5V(1))
Minimum
Typical
Maximum
Physical
Address
Resistor Value Typical Measured Reading with Reading with Reading with
Rload (Ohm)
1 000
Voltage (V)
0.1
a 2.56V ref
a 2.56V ref
40
a 2.56V ref
0
1
2
3
4
5
6
7
2 200
0.22
0.33
0.47
0.68
1
88
3 300
132
4 700
188
6 800
272
10 000
15 000
22 000
400
1.5
600
2.2
880
Table 17-2. Example of Resistor Values(±1%) for a 16-address System (AVCC = 5V(1))
Minimum Typical Maximum
Resistor Value Typical Measured Reading with Reading with Reading with
Physical
Address
Rload (Ohm)
Voltage (V)
a 2.56V ref
a 2.56V ref
a 2.56V ref
0
1
1 000
0.1
38
40
45
1 200
0.12
0.15
0.18
0.22
0.27
0.33
0.47
0.68
0.82
1.0
46
48
54
2
1500
57
60
68
3
1800
69
72
81
4
2200
84
88
99
5
2700
104
127
181
262
316
386
463
579
694
849
1023
108
132
188
272
328
400
480
600
720
880
1023
122
149
212
306
369
450
540
675
810
989
1023
6
3300
7
4700
8
6 800
9
8 200
10
11
12
13
14
15
10 000
12 000
15 000
18 000
22 000
27 000
1.2
1.5
1.8
2.2
2.7
Note:
1. 5V range: Max Rload 30KΩ
3V range: Max Rload 15KΩ
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17.2.2
Current Source for Low Cost Transducer
An external transducer based on a variable resistor can be connected to the Current Source.
This can be, for instance:
• A thermistor, or temperature-sensitive resistor, used as a temperature sensor,
• A CdS photoconductive cell, or luminosity-sensitive resistor, used as a luminosity sensor,
• ...
Using the Current Source with this type of transducer eliminates the need for additional parts
otherwise required in resistor network or Wheatstone bridge.
17.2.3
17.2.4
Voltage Reference for External Devices
An external resistor used in conjunction with the Current Source can be used as voltage refer-
ence for external devices. Using a resistor in series with a lower tolerance than the Current
Source accuracy (≤ 2%) is recommended. Table 17-2 gives an example of voltage references
using standard values of resistors.
Threshold Reference for Internal Analog Comparator
An external resistor used in conjunction with the Current Source can be used as threshold ref-
erence for internal Analog Comparator (See ”AnaComp - Analog Comparator” on page 222.).
This can be connected to AIN0 (negative Analog Compare input pin) as well as AIN1 (positive
Analog Compare input pin). Using a resistor in series with a lower tolerance than the Current
Source accuracy (≤ 2%) is recommended. Table 17-2 gives an example of threshold refer-
ences using standard values of resistors.
17.3 Control Register
17.3.1
AMISCR – Analog Miscellaneous Control Register
Bit
7
-
6
-
5
-
4
-
3
-
2
AREFEN
R/W
1
XREFEN
R/W
0
ISRCEN AMISCR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
R/W
0
0
0
• Bit 0 – ISRCEN: Current Source Enable
Writing this bit to one enables the Current Source as shown in Figure 17-1. It is recommended
to use DIDR register bit function when ISRCEN is set. It also recommended to turn off the Cur-
rent Source as soon as possible (e.g. once the ADC measurement is done).
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18. ADC – Analog to Digital Converter
18.1 Features
• 10-bit Resolution
• 1.0 LSB Integral Non-linearity
• ±2 LSB Absolute Accuracy
• 13 - 260 µs Conversion Time (Low - High Resolution)
• Up to 15 kSPS at Maximum Resolution
• 11 Multiplexed Single Ended Input Channels
• 8 Differential input pairs with selectable gain
• Temperature sensor input channel
• Voltage from Internal Current Source Driving (ISRC)
• Optional Left Adjustment for ADC Result Readout
• 0 - AVCC ADC Input Voltage Range
• Selectable 1.1V / 2.56V ADC Voltage Reference
• Free Running or Single Conversion Mode
• ADC Start Conversion by Auto Triggering on Interrupt Sources
• Interrupt on ADC Conversion Complete
• Sleep Mode Noise Canceler
• Unipolar / Bipolar Input Mode
• Input Polarity Reversal Mode
18.2 Overview
The Atmel® AVR® features a 10-bit successive approximation ADC. The ADC is connected to
a 11-channel Analog Multiplexer which allows 16 differential voltage input combinations and
11 single-ended voltage inputs constructed from the pins PA7..PA0 or PB7..PB4. The differen-
tial input is equipped with a programmable gain stage, providing amplification steps of 8x or
20x on the differential input voltage before the A/D conversion. The single-ended voltage
inputs refer to 0V (AGND).
The ADC contains a Sample and Hold circuit which ensures that the input voltage to the ADC
is held at a constant level during conversion. A block diagram of the ADC is shown in Figure
18-1.
Internal reference voltages of nominally 1.1V or 2.56V are provided On-chip. Alternatively,
AVCC can be used as reference voltage for single ended channels. There are also options to
output the internal 1.1V or 2.56V reference voltages or to input an external voltage reference
and turn-off the internal voltage reference. These options are selected using the REFS[1:0]
bits of the ADMUX control register and using AREFEN and XREFEN bits of the AMISCR con-
trol register.
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Figure 18-1. Analog to Digital Converter Block Schematic
8-Bit Data Bus
ADC Conversion
Complete IRQ
Analog Misc.
(AMISCR)
ADC Control & Status
Register A & B (ADCSRA/ADCSRB)
ADC Multiplexer
Select (ADMUX)
ADC Data Register
(ADCH / ADCL)
Interrupt
Flags
Trigger
Select
Internal
2.56 / 1.1V
Reference
Prescaler
Start
Mux.
Decoder
Conversion Logic
Sample & Hold
Comparator
AVCC
10-bit DAC
AGND
AVCC
/
4
Bandgap
Reference
Temperature
Sensor
ADC10
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
Pos.
Input
Mux.
AREF
XREF
ADC Multiplexer
Output
ISRC / ADC3
ADC2
Mux.
ADC1
x8 / x20 Gain
Amplifier
ADC0
Neg.
Input
Mux.
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18.3 Operation
The ADC converts an analog input voltage to a 10-bit digital value through successive approx-
imation. The minimum value represents AGND and the maximum value represents the voltage
on AVCC, the voltage refrence on AREF pin or an internal 1.1V / 2.56V voltage reference.
The voltage reference for the ADC may be selected by writing to the REFS[1..0] bits in
ADMUX and AREFEN bit in AMISCR. The AVCC supply, the AREF pin or an internal 1.1V /
2.56V voltage reference may be selected as the ADC voltage reference.
The analog input channel and differential gain are selected by writing to the MUX[4..0] bits in
ADMUX register. Any of the 11 ADC input pins ADC[10..0] can be selected as single ended
inputs to the ADC. The positive and negative inputs to the differential gain amplifier are
described in Table 18-5.
If differential channels are selected, the differential gain stage amplifies the voltage difference
between the selected input pair by the selected gain factor 8x or 20x, according to the setting
of the MUX[4..0] bits in ADMUX register. This amplified value then becomes the analog input
to the ADC. If single ended channels are used, the gain amplifier is bypassed altogether.
The on-chip temperature sensor is selected by writing the code defined in Table 18-5 to the
MUX[4..0] bits in ADMUX register when its dedicated ADC channel is used as an ADC input.
A specific ADC channel (defined in Table 18-5) is used to measure the voltage to the boundar-
ies of an external resistance flowing by a current driving by the Internal Current Source
(ISRC).
The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA register. Voltage refer-
ence and input channel selections will not go into effect until ADEN is set. The ADC does not
consume power when ADEN is cleared, so it is recommended to switch off the ADC before
entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX register.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the data
registers belongs to the same conversion. Once ADCL is read, ADC access to data registers
is blocked. This means that if ADCL has been read, and a conversion completes before ADCH
is read, neither register is updated and the result from the conversion is lost. When ADCH is
read, ADC access to the ADCH and ADCL Registers is re-enabled.
The ADC has its own interrupt which can be triggered when a conversion completes. When
ADC access to the data registers is prohibited between reading of ADCH and ADCL, the inter-
rupt will trigger even if the result is lost.
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18.4 Starting a Conversion
A single conversion is started by writing a logical one to the ADC Start Conversion bit, ADSC.
This bit stays high as long as the conversion is in progress and will be cleared by hardware
when the conversion is completed. If a different data channel is selected while a conversion is
in progress, the ADC will finish the current conversion before performing the channel change.
Alternatively, a conversion can be triggered automatically by various sources. Auto Triggering
is enabled by setting the ADC Auto Trigger Enable bit, ADATE in ADCSRA register. The trig-
ger source is selected by setting the ADC Trigger Select bits, ADTS in ADCSRB register (see
description of the ADTS bits for a list of the trigger sources). When a positive edge occurs on
the selected trigger signal, the ADC prescaler is reset and a conversion is started. This pro-
vides a method of starting conversions at fixed intervals. If the trigger signal still is set when
the conversion completes, a new conversion will not be started. If another positive edge
occurs on the trigger signal during conversion, the edge will be ignored. Note that an Interrupt
Flag will be set even if the specific interrupt is disabled or the Global Interrupt Enable bit in
SREG register is cleared. A conversion can thus be triggered without causing an interrupt.
However, the Interrupt Flag must be cleared in order to trigger a new conversion at the next
interrupt event.
Figure 18-2. ADC Auto Trigger Logic
CLK IO
ADTS[2:0]
Start
ADC Prescaler
ADIF
ADATE
CLKADC
SOURCE 1
. . .
Conversion
Logic
. . .
. . .
Edge
Detector
. . .
SOURCE n
ADSC
Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as
soon as the ongoing conversion has finished. The ADC then operates in Free Running mode,
constantly sampling and updating the ADC Data Register. The first conversion must be started
by writing a logical one to the ADSC bit in ADCSRA register. In this mode the ADC will perform
successive conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or
not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA
register to one. ADSC can also be used to determine if a conversion is in progress. The ADSC
bit will be read as one during a conversion, independently of how the conversion was started.
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18.5 Prescaling and Conversion Timing
Figure 18-3. ADC Prescaler
ADEN
Start
Reset
7-bit ADC Prescaler
CLK IO
ADPS0
ADPS1
ADPS2
By default, the successive approximation circuitry requires an input clock frequency between
50kHz and 200kHz to get maximum resolution. If a lower resolution than 10bits is needed, the
input clock frequency to the ADC can be higher than 200kHz to get a higher sample rate.
The ADC module contains a prescaler, which generates an acceptable ADC clock frequency
from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA
register. The prescaler starts counting from the moment the ADC is switched on by setting the
ADEN bit in ADCSRA register. The prescaler keeps running for as long as the ADEN bit is set,
and is continuously reset when ADEN is low.
When initiating a single ended conversion by setting the ADSC bit in ADCSRA register, the
conversion starts at the following rising edge of the ADC clock cycle.
A normal conversion takes 13 ADC clock cycles. The first conversion after the ADC is
switched on (ADEN in ADCSRA register is set) takes 25 ADC clock cycles in order to initialize
the analog circuitry.
The actual sample-and-hold takes place 1.5 ADC clock cycles after the start of a normal con-
version and 14.5 ADC clock cycles after the start of an first conversion. When a conversion is
complete, the result is written to the ADC Data Registers, and ADIF is set. In Single Conver-
sion mode, ADSC is cleared simultaneously. The software may then set ADSC again, and a
new conversion will be initiated on the first rising ADC clock edge.
When Auto Triggering is used, the prescaler is reset when the trigger event occurs. This
assures a fixed delay from the trigger event to the start of conversion. In this mode, the sam-
ple-and-hold takes place 2 ADC clock cycles after the rising edge on the trigger source signal.
Three additional CPU clock cycles are used for synchronization logic.
In Free Running mode, a new conversion will be started immediately after the conversion
completes, while ADSC remains high. For a summary of conversion times, see Table 18-1.
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Figure 18-4. ADC Timing Diagram, First Conversion (Single Conversion Mode)
Next
First Conversion
Conversion
ycle Number
1
2
12
13
14
15
16
17
18
19
20
21
22
23
24
25
1
2
3
DC Clock
DEN
DSC
DIF
Sign and MSB of Result
DCH
DCL
LSB of Result
MUX
MUX and REFS
Update
Conversion
Complete
and REFS
Update
Sample & Hold
Figure 18-5. ADC Timing Diagram, Single Conversion
One Conversion
Next Conversion
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
3
ycle Number
DC Clock
DSC
DIF
DCH
Sign and MSB of Result
LSB of Result
DCL
Sample & Hold
Conversion
Complete
MUX and REFS
Update
MUX and REFS
Update
Figure 18-6. ADC Timing Diagram, Auto Triggered Conversion
One Conversion
Next Conversion
1
2
3
4
5
6
7
8
9
10
11
12
13
1
2
ycle Number
DC Clock
igger
ource
DATE
DIF
DCH
DCL
Sign and MSB of Result
LSB of Result
Sample &
Hold
Prescaler
Reset
Conversion
Complete
Prescaler
Reset
MUX and REFS
Update
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Figure 18-7. ADC Timing Diagram, Free Running Conversion
One Conversion
Next Conversion
11
12
13
1
2
3
4
ycle Number
DC Clock
DSC
DIF
DCH
DCL
Sign and MSB of Result
LSB of Result
Sample & Hold
Conversion
Complete
MUX and REFS
Update
Table 18-1. ADC Conversion Time
Sample & Hold
Condition
(Cycles from Start of Conversion)
Conversion Time (Cycles)
25cycles
First conversion
13.5cycles
1.5cycles
2cycles
Normal conversions
Auto Triggered conversions
13cycles
13.5cycles
18.6 Changing Channel or Reference Selection
The MUX[4:0] and REFS[1:0] bits in the ADMUX register are single buffered through a tempo-
rary register to which the CPU has random access. This ensures that the channels and
reference selection only takes place at a safe point during the conversion. The channel and
reference selection is continuously updated until a conversion is started. Once the conversion
starts, the channel and reference selection is locked to ensure a sufficient sampling time for
the ADC. Continuous updating resumes in the last ADC clock cycle before the conversion
completes (ADIF in ADCSRA register is set). Note that the conversion starts on the following
rising ADC clock edge after ADSC is written. The user is thus advised not to write new channel
or reference selection values to ADMUX until one ADC clock cycle after ADSC is written.
If Auto Triggering is used, the exact time of the triggering event can be indeterministic. Special
care must be taken when updating the ADMUX register, in order to control which conversion
will be affected by the new settings.
If both ADATE and ADEN is written to one, an interrupt event can occur at any time. If the
ADMUX Register is changed in this period, the user cannot tell if the next conversion is based
on the old or the new settings. ADMUX can be safely updated in the following ways:
a. When ADATE or ADEN is cleared.
b. During conversion, minimum one ADC clock cycle after the trigger event.
c. After a conversion, before the Interrupt Flag used as trigger source is cleared.
When updating ADMUX in one of these conditions, the new settings will affect the next ADC
conversion.
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18.6.1
ADC Input Channels
When changing channel selections, the user should observe the following guidelines to ensure
that the correct channel is selected:
In Single Conversion mode, always select the channel before starting the conversion. The
channel selection may be changed one ADC clock cycle after writing one to ADSC. However,
the simplest method is to wait for the conversion to complete before changing the channel
selection.
In Free Running mode, always select the channel before starting the first conversion. The
channel selection may be changed one ADC clock cycle after writing one to ADSC. However,
the simplest method is to wait for the first conversion to complete, and then change the chan-
nel selection. Since the next conversion has already started automatically, the next result will
reflect the previous channel selection. Subsequent conversions will reflect the new channel
selection.
18.6.2
ADC Voltage Reference
The voltage reference for the ADC (VREF) indicates the conversion range for the ADC. Single
ended channels that exceed VREF will result in codes close to 0x3FF. VREF can be selected as
either AVCC, internal 1.1V / 2.56V voltage reference or external AREF pin. The first ADC con-
version result after switching voltage reference source may be inaccurate, and the user is
advised to discard this result.
18.7 ADC Noise Canceler
The ADC features a noise canceler that enables conversion during sleep mode to reduce
noise induced from the CPU core and other I/O peripherals. The noise canceler can be used
with ADC Noise Reduction and Idle mode. To make use of this feature, the following proce-
dure should be used:
a. Make sure that the ADC is enabled and is not busy converting. Single Conversion
mode must be selected and the ADC conversion complete interrupt must be
enabled.
b. Enter ADC Noise Reduction mode (or Idle mode). The ADC will start a conver-
sion once the CPU has been halted.
c. If no other interrupts occur before the ADC conversion completes, the ADC inter-
rupt will wake up the CPU and execute the ADC Conversion Complete interrupt
routine. If another interrupt wakes up the CPU before the ADC conversion is com-
plete, that interrupt will be executed, and an ADC Conversion Complete interrupt
request will be generated when the ADC conversion completes. The CPU will
remain in active mode until a new sleep command is executed.
Note that the ADC will not be automatically turned off when entering other sleep modes than
Idle mode and ADC Noise Reduction mode. The user is advised to write zero to ADEN before
entering such sleep modes to avoid excessive power consumption.
18.7.1
Analog Input Circuitry
The analog input circuitry for single ended channels is illustrated in Figure 18-8. An analog
source applied to ADCn is subjected to the pin capacitance and input leakage of that pin,
regardless of whether that channel is selected as input for the ADC. When the channel is
selected, the source must drive the S/H capacitor through the series resistance (combined
resistance in the input path).
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The ADC is optimized for analog signals with an output impedance of approximately 10 kΩ or
less. If such a source is used, the sampling time will be negligible. If a source with higher
impedance is used, the sampling time will depend on how long time the source needs to
charge the S/H capacitor, with can vary widely. The user is recommended to only use low
impedant sources with slowly varying signals, since this minimizes the required charge trans-
fer to the S/H capacitor.
Signal components higher than the Nyquist frequency (fADC/2) should not be present to avoid
distortion from unpredictable signal convolution. The user is advised to remove high frequency
components with a low-pass filter before applying the signals as inputs to the ADC.
Figure 18-8. Analog Input Circuitry
IIH
ADCn
1..100 kO
CS/H= 14 pF
IIL
VCC/2
18.7.2
Analog Noise Canceling Techniques
Digital circuitry inside and outside the device generates EMI which might affect the accuracy of
analog measurements. If conversion accuracy is critical, the noise level can be reduced by
applying the following techniques:
a. Keep analog signal paths as short as possible. Make sure analog tracks run over
the analog ground plane, and keep them well away from high-speed switching
digital tracks.
b. Use the ADC noise canceler function to reduce induced noise from the CPU.
c. If any port pins are used as digital outputs, it is essential that these do not switch
while a conversion is in progress.
18.7.3
ADC Accuracy Definitions
An n-bit single-ended ADC converts a voltage linearly between GND and VREF in 2n steps
(LSBs). The lowest code is read as 0, and the highest code is read as 2n-1.
Several parameters describe the deviation from the ideal behavior:
• Offset: The deviation of the first transition (0x000 to 0x001) compared to the ideal transition
(at 0.5LSB). Ideal value: 0LSB.
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Figure 18-9. Offset Error
Output Code
Ideal ADC
Actual ADC
Offset
Error
VREF
Input Voltage
• Gain Error: After adjusting for offset, the Gain Error is found as the deviation of the last
transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5LSB below maximum).
Ideal value: 0LSB
Figure 18-10. Gain Error
Gain
Error
Output Code
Ideal ADC
Actual ADC
VREF
Input Voltage
• Integral Non-linearity (INL): After adjusting for offset and gain error, the INL is the maximum
deviation of an actual transition compared to an ideal transition for any code. Ideal value:
0LSB.
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Figure 18-11. Integral Non-linearity (INL)
Output Code
Ideal ADC
Actual ADC
VREF Input Voltage
• Differential Non-linearity (DNL): The maximum deviation of the actual code width (the
interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value:
0LSB.
Figure 18-12. Differential Non-linearity (DNL)
Output Code
0x3FF
1 LSB
DNL
0x000
0
VREF Input Voltage
• Quantization Error: Due to the quantization of the input voltage into a finite number of
codes, a range of input voltages (1LSB wide) will code to the same value. Always ±0.5LSB.
• Absolute Accuracy: The maximum deviation of an actual (unadjusted) transition compared
to an ideal transition for any code. This is the compound effect of offset, gain error,
differential error, non-linearity, and quantization error. Ideal value: ±0.5LSB.
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18.8 ADC Conversion Result
After the conversion is complete (ADIF is high), the conversion result can be found in the ADC
Result Registers (ADCL, ADCH). The form of the conversion result depends on the type of the
conversion as there are three types of conversions: single ended conversion, unipolar differ-
ential conversion and bipolar differential conversion.
18.8.1
Single Ended Conversion
For single ended conversion, the result is:
V
1024
IN
ADC = -----------------------------
V
REF
where VIN is the voltage on the selected input pin and VREF the selected voltage reference (see
Table 18-4 on page 216 and Table 18-5 on page 217). 0x000 represents analog ground, and
0x3FF represents the selected voltage reference minus one LSB. The result is presented in
one-sided form, from 0x3FF to 0x000.
18.8.2
Unipolar Differential Conversion
If differential channels and an unipolar input mode are used, the result is:
(V
– V
)
NEG
1024
POS
----------------------------------------------------------
ADC =
GAIN
V
REF
where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin,
and VREF the selected voltage reference (see Table 18-4 on page 216 and Table 18-5 on page
217). The voltage on the positive pin must always be larger than the voltage on the negative
pin or otherwise the voltage difference is saturated to zero. The result is presented in
one-sided form, from 0x000 (0d) to 0x3FF (+1023d). The GAIN is either 8x or 20x.
18.8.3
Bipolar Differential Conversion
As default the ADC converter operates in the unipolar input mode, but the bipolar input mode
can be selected by writing the BIN bit in the ADCSRB register to one. In the bipolar input mode
two-sided voltage differences are allowed and thus the voltage on the negative input pin can
also be larger than the voltage on the positive input pin. If differential channels and a bipolar
input mode are used, the result is:
(V
– V
)
NEG
512
POS
-------------------------------------------------------
ADC =
GAIN
V
REF
where VPOS is the voltage on the positive input pin, VNEG the voltage on the negative input pin,
and VREF the selected voltage reference. The result is presented in two’s complement form,
from 0x200 (-512d) through 0x000 (+0d) to 0x1FF (+511d). The GAIN is either 8x or 20x.
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However, if the signal is not bipolar by nature (9bits + sign as the 10th bit), this scheme loses
one bit of the converter dynamic range. Then, if the user wants to perform the conversion with
the maximum dynamic range, the user can perform a quick polarity check of the result and use
the unipolar differential conversion with selectable differential input pair. When the polarity
check is performed, it is sufficient to read the MSB of the result (ADC9 in ADCH register). If the
bit is one, the result is negative, and if this bit is zero, the result is positive.
18.9 Temperature Measurement
The temperature measurement is based on an on-chip temperature sensor that is coupled to a
single ended ADC input. MUX[4..0] bits in ADMUX register enables the temperature sensor.
The internal 1.1V voltage reference must also be selected for the ADC voltage reference
source in the temperature sensor measurement. When the temperature sensor is enabled, the
ADC converter can be used in single conversion mode to measure the voltage over the tem-
perature sensor.
The measured voltage has a linear relationship to the temperature as described in Table 18-2.
The voltage sensitivity is approximately 1LSB/°C and the accuracy of the temperature mea-
surement is ±10°C using manufacturing calibration values (TS_GAIN, TS_OFFSET). The
values described in Table 18-2 are typical values. However, due to the process variation the
temperature sensor output varies from one chip to another.
Table 18-2. Temperature vs. Sensor Output Voltage (Typical Case): Example ADC Values
Temperature/°C
–40°C
+25°C
+85°C
0x00F6
0x0144
0c01B8
18.9.1
Manufacturing Calibration
Calibration values determined during test are available in the signature row.
The temperature in degrees Celsius can be calculated using the formula:
([(ADCH « 8) ADCL] – (273 + 25 – TS_OFFSET)) × 128
T = ------------------------------------------------------------------------------------------------------------------------------------------------------ + 25
TS_GAIN
Where:
a. ADCH & ADCL are the ADC data registers,
b. is the temperature sensor gain
c. TSOFFSET is the temperature sensor offset correction term
TS_GAIN is the unsigned fixed point 8-bit temperature sensor gain factor in
1/128th units stored in the signature row
TS_OFFSET is the signed twos complement temperature sensor offset reading
stored in the signature row. See Table 21-1 on page 232 for signature row
parameter address.
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The following code example allows to read Signature Row data:
.equ TS_GAIN = 0x0007
.equ TS_OFFSET = 0x0005
LDI R30,LOW(TS_GAIN)
LDI R31,HIGH (TS_GAIN)
RCALL Read_signature_row
MOV R17,R16 ; Save R16 result
LDI R30,LOW(TS_OFFSET)
LDI R31,HIGH (TS_OFFSET)
RCALL Read_signature_row
; R16 holds TS_OFFSET and R17 holds TS_GAIN
Read_signature_row:
IN R16,SPMCSR ; Wait for SPMEN ready
SBRC R16,SPMEN ; Exit loop here when SPMCSR is free
RJMP Read_signature_row
LDI R16,((1<<SIGRD)|(1<<SPMEN)) ; We need to set SIGRD and SPMEN
together
OUT SPMCSR,R16 ; and execute the LPM within 3 cycles
LPM R16,Z
RET
18.10 Internal Voltage Reference Output
The internal voltage reference is output on XREF pin as described in Table 18-3 if the ADC is
turned on (See “Voltage Reference Enable Signals and Start-up Time” on page 57.). Addition
of an external filter capacitor (5 - 10nF) on XREF pin may be necessary. XREF current load
must be from 1 µA to 100 µA with VCC from 2.7V to 5.5V for XREF = 1.1V and with VCC from
4.5V to 5.5V for XREF = 2.56V.
XREF pin can be coupled to an analog input of the ADC (See Section 1.3 “Pin Configuration”
on page 6).
Table 18-3. Internal Voltage Reference Output
XREFEN (1)
REFS1 (2) REFS0 (2) Voltage Reference Output (Iload ≤ 100µA)
Hi-Z, the pin can be used as AREF input or other alternate
functions.
0
x
x
1 (1)
1 (1)
0
1
1
1
XREF = 1.1V (3)
XREF = 2.56V (3)(4)
Notes: 1. See ”Bit 1 – XREFEN: Internal Voltage Reference Output Enable” on page 221.
2. See ”Bit 7:6 – REFS1:REFS0: Voltage Reference Selection Bits” on page 216.
3. In these configurations, the pin pull-up must be turned off and the pin digital output must be
set in Hi-Z.
4. VCC in range 4.5 - 5.5V.
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18.11 Register Description
18.11.1 ADMUX – ADC Multiplexer Selection Register
Bit
7
REFS1
R/W
0
6
REFS0
R/W
0
5
ADLAR
R/W
0
4
MUX4
R/W
0
3
MUX3
R/W
0
2
MUX2
R/W
0
1
MUX1
R/W
0
0
MUX0
R/W
0
ADMUX
Read/Write
Initial Value
• Bit 7:6 – REFS1:REFS0: Voltage Reference Selection Bits
These bits and AREFEN bit from the Analog Miscellaneous Control Register (AMISCR) select
the voltage reference for the ADC, as shown in Table 18-4. If these bits are changed during a
conversion, the change will not go in effect until this conversion is complete (ADIF in ADCSRA
register is set). Whenever these bits are changed, the next conversion will take 25 ADC clock
cycles. If active channels are used, using AVCC or an external AREF higher than (AVCC - 1V)
is not recommended, as this will affect ADC accuracy. The internal voltage reference options
may not be used if an external voltage is being applied to the AREF pin.
Table 18-4. Voltage Reference Selections for ADC
REFS1
REFS0
AREFEN Voltage Reference (VREF) Selection
X
X
0
1
0
0
1
1
0
1
0
0
AVCC used as Voltage Reference, diconnected from AREF pin.
External Voltage Reference at AREF pin (AREF ≥ 2.0V)
Internal 1.1V Voltage Reference .
Internal 2.56V Voltage Reference .
• Bit 5 – ADLAR: ADC Left Adjust Result
The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Regis-
ter. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted.
Changing the ADLAR bit will affect the ADC Data Register immediately, regardless of any
ongoing conversions. For a complete description of this bit, see “ADCL and ADCH – The ADC
Data Register” on page 219.
• Bits 4:0 – MUX4:0: Analog Channel and Gain Selection Bits
These bits select which combination of analog inputs are connected to the ADC. In case of dif-
ferential input, gain selection is also made with these bits. Refer to Table 18-5 for details. If
these bits are changed during a conversion, the change will not go into effect until this
conversion is complete (ADIF in ADCSRA register is set).
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Atmel ATA5505 [Preliminary]
Table 18-5. Input Channel Selections
Positive
Negative
MUX[4..0]
0 0000
0 0001
0 0010
0 0011
0 0100
0 0101
0 0110
0 0111
0 1000
0 1001
0 1010
0 1011
0 1100
0 1101
0 1110
0 1111
1 0000
1 0001
1 0010
1 0011
1 0100
1 0101
1 0110
1 0111
1 1000
1 1001
1 1010
1 1011
1 1100
1 1101
1 1110
1 1111
Single Ended Input
ADC0 (PA0)
Differential Input Differential Input
Gain
ADC1 (PA1)
ADC2 (PA2)
ADC3 / ISRC (PA3)
ADC4 (PA4)
ADC5 (PA5)
ADC6 (PA6)
ADC7 / AREF (PA7)
ADC8 (PB5)
NA
NA
NA
ADC9 (PB6)
ADC10 (PB7)
Temperature Sensor
Bandgap Reference (1.1V)
AVCC/4
GND (0V)
(reserved)
8x
20x
8x
ADC0 (PA0)
ADC1 (PA1)
ADC2 (PA2)
ADC4 (PA4)
ADC5 (PA5)
ADC6 (PA6)
ADC8 (PB5)
ADC9 (PB6)
ADC1 (PA1)
ADC2 (PA2)
ADC3 (PA3)
ADC5 (PA5)
ADC6 (PA6)
ADC7 (PA7)
ADC9 (PB6)
ADC10 (PB7)
20x
8x
20x
8x
20x
8x
N/A
20x
8x
20x
8x
20x
8x
20x
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18.11.2 ADCSRA – ADC Control and Status Register A
Bit
7
ADEN
R/W
0
6
ADSC
R/W
0
5
ADATE
R/W
0
4
ADIF
R/W
0
3
ADIE
R/W
0
2
ADPS2
R/W
0
1
ADPS1
R/W
0
0
ADPS0
R/W
0
ADCSRA
Read/Write
Initial Value
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running
mode, write this bit to one to start the first conversion. The first conversion after ADSC has
been written after the ADC has been enabled, or if ADSC is written at the same time as the
ADC is enabled, will take 25 ADC clock cycles instead of the normal 13. This first conversion
performs initialization of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is com-
plete, it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a
conversion on a positive edge of the selected trigger signal. The trigger source is selected by
setting the ADC Trigger Select bits, ADTS in ADCSRB.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the data registers are updated. The
ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
ADIF is cleared by hardware when executing the corresponding interrupt handling vector.
Alternatively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a
Read-Modify-Write on ADCSRA, a pending interrupt can be disabled. This also applies if the
SBI and CBI instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete
Interrupt is activated.
• Bits 2:0 – ADPS2:0: ADC Prescaler Select Bits
These bits determine the division factor between the system clock frequency and the input
clock to the ADC.
Table 18-6. ADC Prescaler Selections
ADPS2
ADPS1
ADPS0
Division Factor
0
0
0
0
0
0
1
1
0
1
0
1
2
2
4
8
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Atmel ATA5505 [Preliminary]
Table 18-6. ADC Prescaler Selections (Continued)
ADPS2
ADPS1
ADPS0
Division Factor
1
1
1
1
0
0
1
1
0
1
0
1
16
32
64
128
18.11.3 ADCL and ADCH – The ADC Data Register
18.11.3.1 ADLAR = 0
Bit
15
14
13
12
11
10
9
8
–
–
–
–
–
–
ADC9
ADC8
ADCH
ADCL
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
7
R
R
0
6
R
R
0
5
R
R
0
4
R
R
0
3
R
R
0
2
R
R
0
1
R
R
0
0
R
R
0
Read/Write
Initial Value
0
0
0
0
0
0
0
0
18.11.3.2
ADLAR = 1
Bit
15
14
13
12
11
10
9
8
ADC9
ADC8
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADCH
ADCL
ADC1
ADC0
–
5
–
4
–
3
–
2
–
1
–
0
7
R
R
0
6
R
R
0
Read/Write
Initial Value
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
R
R
0
0
0
0
0
0
0
0
0
When an ADC conversion is complete, the result is found in these two registers.
When ADCL is read, the ADC Data Register is not updated until ADCH is read. Consequently,
if the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH.
The ADLAR bit in ADMUX, and the MUXn bits in ADMUX affect the way the result is read from
the registers. If ADLAR is set, the result is left adjusted. If ADLAR is cleared (default), the
result is right adjusted.
• ADC9:0: ADC Conversion Result
These bits represent the result from the conversion, as detailed in “ADC Conversion Result”
on page 213.
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18.11.4 ADCSRB – ADC Control and Status Register B
Bit
7
BIN
R/W
0
6
ACME
R/W
0
5
ACIR1
R/W
0
4
ACIR0
R/W
0
3
–
2
ADTS2
R/W
0
1
ADTS1
R/W
0
0
ADTS0
R/W
0
ADCSRB
Read/Write
Initial Value
R
0
• Bit 7– BIN: Bipolar Input Mode
The gain stage is working in the unipolar mode as default, but the bipolar mode can be
selected by writing the BIN bit in the ADCSRB register. In the unipolar mode only one-sided
conversions are supported and the voltage on the positive input must always be larger than
the voltage on the negative input. Otherwise the result is saturated to the voltage reference. In
the bipolar mode two-sided conversions are supported and the result is represented in the
two’s complement form. In the unipolar mode the resolution is 10 bits and the bipolar mode the
resolution is 9bits + 1 sign bit.
• Bit 3 – Res: Reserved Bit
This bit is reserved for future use. For compatibility with future devices it must be written to
zero when ADCSRB register is written.
• Bits 2:0 – ADTS2:0: ADC Auto Trigger Source
If ADATE in ADCSRA register is written to one, the value of these bits selects which source
will trigger an ADC conversion. If ADATE is cleared, the ADTS2:0 settings will have no effect.
A conversion will be triggered by the rising edge of the selected Interrupt Flag. Note that
switching from a trigger source that is cleared to a trigger source that is set, will generate a
positive edge on the trigger signal. If ADEN in ADCSRA register is set, this will start a conver-
sion. Switching to Free Running mode (ADTS[2:0]=0) will not cause a trigger event, even if the
ADC Interrupt Flag is set.
Table 18-7. ADC Auto Trigger Source Selections
ADTS2
ADTS1
ADTS0
Trigger Source
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
Free Running mode
Analog Comparator
External Interrupt Request 0
Timer/Counter1 Compare Match A
Timer/Counter1 Overflow
Timer/Counter1 Compare Match B
Timer/Counter1 Capture Event
Watchdog Interrupt Request
18.11.5 DIDR0 – Digital Input Disable Register 0
Bit
7
6
5
4
3
2
1
0
ADC7D /
AIN1D
ADC6D /
AIN0D
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
DIDR0
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
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Atmel ATA5505 [Preliminary]
• Bits 7:0 – ADC7D:ADC0D: ADC7:0 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN register bit will always read as zero when this bit is set. When
an analog signal is applied to the ADC7:0 pin and the digital input from this pin is not needed,
this bit should be written logic one to reduce power consumption in the digital input buffer.
18.11.6 DIDR1 – Digital Input Disable Register 1
Bit
7
6
ADC10D
R/W
5
ADC9D
R/W
0
4
ADC8D
R/W
0
3
-
2
-
1
-
0
-
-
DIDR1
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
0
• Bit 7 – Res: Reserved Bit
This bit is reserved for future use. For compatibility with future devices it must be written to
zero when DIDR1 register is written.
• Bits 6..4 – ADC10D..ADC8D: ADC10..8 Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding ADC pin is dis-
abled. The corresponding PIN register bit will always read as zero when this bit is set. When
an analog signal is applied to the ADC10:8 pin and the digital input from this pin is not needed,
this bit should be written logic one to reduce power consumption in the digital input buffer.
• Bits 3:0 - Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be writ-
ten to zero when DIDR1 is written.
18.11.7 AMISCR – Analog Miscellaneous Control Register
Bit
7
6
5
4
-
3
-
2
AREFEN
R/W
1
XREFEN
R/W
0
ISRCEN
R/W
0
-
-
-
AMISCR
Read/Write
Initial Value
R
0
R
0
R
0
R
0
R
0
0
0
• Bits 7:3 – Reserved Bits
These bits are reserved for future use. For compatibility with future devices, they must be writ-
ten to zero when AMISCR is written.
• Bit 2 – AREFEN: External Voltage Reference Input Enable
When this bit is written logic one, the voltage reference for the ADC is input from AREF pin as
described in Table 18.10 on page 215. If active channels are used, using AVCC or an external
AREF higher than (AVCC - 1V) is not recommended, as this will affect ADC accuracy. The
internal voltage reference options may not be used if an external voltage is being applied to
the AREF pin. It is recommended to use DIDR register bit function (digital input disable) when
AREFEN is set.
• Bit 1 – XREFEN: Internal Voltage Reference Output Enable
When this bit is written logic one, the internal voltage reference 1.1V or 2.56V is output on
XREF pin as described in Table 18.10 on page 215. It is recommended to use DIDR register
bit function (digital input disable) when XREFEN is set.
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19. AnaComp - Analog Comparator
The Analog Comparator compares the input values on the positive pin (AIN1) and negative pin
(AIN0). When the voltage on the positive pin is higher than the voltage on the negative pin, the
Analog Comparator output, ACO, is set. The comparator can trigger a separate interrupt,
exclusive to the Analog Comparator. The user can select Interrupt triggering on comparator
output rise, fall or toggle. A block diagram of the comparator and its surrounding logic is shown
in Figure 19-1.
Figure 19-1. Analog Comparator Block Diagram(1)(2)
ADC Multiplexer
Output (1)
AVcc
ACME
ADEN
ACO
ACI
ACD
16-bit Timer/Counter
Input Capture
AIN1
(PA7)
Interrupt
Sensivity
Control
Analog Comparator
Interrupt
AIN0
(PA6)
ACIE
(from ADC)
ACIS1 ACIS0
ACIRS
Internal
2.56 V
Reference
2.56 V
1.28 V
0.64 V
0.32 V
REFS0
REFS1
ACIR0
ACIR1
Notes: 1. See Table 19-2 on page 225 and Table 19-3 on page 225
2. Refer to Figure 1-5 on page 6 and Table 9-3 on page 79 for Analog Comparator pin
placement.
19.1 Register Description
19.1.1
ADC Control and Status Register B – ADCSRB
Bit
7
BIN
R
6
ACME
R/W
0
5
ACIR1
R/W
0
4
ACIR0
R/W
0
3
—
R
0
2
ADTS2
R/W
0
1
ADTS1
R/W
0
0
ADTS0 ADCSRB
Read/Write
Initial Value
R/W
0
0
• Bit 6 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the
ADC multiplexer selects the positive input to the Analog Comparator. When this bit is written
logic zero, AIN1 is applied to the positive input of the Analog Comparator.
When the Analog to Digital Converter (ADC) is configured as single ended input channel, it is
possible to select any of the ADC[10..0] pins to replace the positive input to the Analog Com-
parator. The ADC multiplexer (MUX[4..0]) is used to select this input, and consequently, the
ADC must be switched off to utilize this feature.
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Atmel ATA5505 [Preliminary]
• Bits 5, 4 – ACIR1, ACIR0: Analog Comparator Internal Voltage Reference Select
When ACIRS bit is set in ADCSRA register, these bits select a voltage reference for the nega-
tive input to the Analog Comparator, see Table 19-3 on page 225.
19.1.2
ACSR – Analog Comparator Control and Status Register
Bit
7
6
5
4
ACI
R/W
0
3
ACIE
R/W
0
2
ACIC
R/W
0
1
ACIS1
R/W
0
0
ACIS0
R/W
0
ACD
ACIRS
ACO
ACSR
Read/Write
Initial Value
R/W
0
R/W
0
R
N/A
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the Analog Comparator is switched off. This bit
can be set at any time to turn off the Analog Comparator. This will reduce power consumption
in Active and Idle mode. When changing the ACD bit, the Analog Comparator Interrupt must
be disabled by clearing the ACIE bit of ACSR register. Otherwise an interrupt can occur when
the bit is changed.
• Bit 6 – ACIRS: Analog Comparator Internal Reference Select
When this bit is set an Internal Reference Voltage replaces the negative input to the Analog
Comparator (c.f. Table 19-3 on page 225).
If ACIRS is cleared, AIN0 is applied to the negative input to the Analog Comparator.
• Bit 5 – ACO: Analog Comparator Output
The output of the Analog Comparator is synchronized and then directly connected to ACO.
The synchronization introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit is
set and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding
interrupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the Status Register is set, the Analog
Comparator interrupt is activated. When written logic zero, the interrupt is disabled.
• Bit 2 – ACIC: Analog Comparator Input Capture Enable
When written logic one, this bit enables the input capture function in Timer/Counter1 to be trig-
gered by the Analog Comparator. The comparator output is in this case directly connected to
the input capture front end logic, making the comparator utilize the noise canceler and edge
select features of the Timer/Counter1 Input Capture interrupt. When written logic zero, no con-
nection between the Analog Comparator and the input capture function exists. To make the
comparator trigger the Timer/Counter1 Input Capture interrupt, the ICIE1 bit in the Timer Inter-
rupt Mask Register (TIMSK1) must be set.
• Bits 1, 0 – ACIS1, ACIS0: Analog Comparator Interrupt Mode Select
These bits determine which comparator events that trigger the Analog Comparator interrupt.
The different settings are shown in Table 19-1.
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Table 19-1. ACIS1 / ACIS0 Settings
ACIS1
ACIS0
Interrupt Mode
0
0
1
1
0
1
0
1
Comparator Interrupt on Output Toggle.
Reserved
Comparator Interrupt on Falling Output Edge.
Comparator Interrupt on Rising Output Edge.
Note:
When changing the ACIS1/ACIS0 bits, the Analog Comparator Interrupt must be disabled by
clearing its Interrupt Enable bit in the ACSR Register. Otherwise an interrupt can occur when
the bits are changed.
19.1.3
DIDR0 – Digital Input Disable Register 0
Bit
7
6
5
4
3
2
1
0
ADC7D /
AIN1D
ADC6D /
AIN0D
ADC5D
ADC4D
ADC3D
ADC2D
ADC1D
ADC0D
DIDR0
Read/Write
Initial Value
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
• Bits 7,6 – AIN1D, AIN0D: AIN1D and AIN0D Digital Input Disable
When this bit is written logic one, the digital input buffer on the corresponding Analog Com-
pare pin is disabled. The corresponding PIN register bit will always read as zero when this bit
is set. When an analog signal is applied to the AIN0/1 pin and the digital input from this pin is
not needed, this bit should be written logic one to reduce power consumption in the digital
input buffer.
19.2 Analog Comparator Inputs
19.2.1
Analog Compare Positive Input
It is possible to select any of the inputs of the ADC Positive Input Multiplexer to replace the
positive input to the Analog Comparator. The ADC multiplexer is used to select this input, and
consequently, the ADC must be switched off to utilize this feature. If the Analog Comparator
Multiplexer Enable bit (ACME in ADCSRB register) is set and the ADC is switched off (ADEN
in ADCSRA register is zero), MUX[4..0] in ADMUX register select the input pin to replace the
positive input to the Analog Comparator, as shown in Table 19-2. If ACME is cleared or ADEN
is set, AIN1 pin is applied to the positive input to the Analog Comparator.
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Atmel ATA5505 [Preliminary]
Table 19-2. Analog Comparator Positive Input
ACME
ADEN
MUX[4..0]
x xxxx b
x xxxx b
0 0000 b
0 0001 b
0 0010 b
0 0011 b
0 0100 b
0 0101 b
0 0110 b
0 0111 b
0 1000 b
0 1001 b
0 1010 b
Other
Analog Comparator Positive Input - Comment
0
x
x
1
0
0
0
0
0
0
0
0
0
0
0
0
AIN1
ADC Switched On
AIN1
1
1
1
1
1
1
1
1
1
1
1
1
ADC0
ADC1
ADC2
ADC3 / ISRC
ADC4
ADC5
ADC6
ADC7
ADC8
ADC9
ADC10
ADC Switched Off.
This doesn’t make sense - Don’t use.
19.2.2
Analog Compare Negative Input
It is possible to select an internal voltage reference to replace the negative input to the Analog
Comparator. The output of a 2-bit DAC using the Internal Voltage Reference of the DAC is
available when ACIRS bit of ACSR register is set. The voltage reference division factor is
done by ACIR[1..0] of ADCSRB register.
If ACIRS is cleared, AIN0 pin is applied to the negative input to the Analog Comparator.
Table 19-3. Analog Comparator Negative Input
ACIRS ACIR[1..0] REFS[1..0] Analog Comparator Negative Input - Comment
0
x
x
AIN0
0 0 b
0 1 b
1 0 b
1
x
Reserved
1
1
1
1
0 0 b
0 1 b
1 0 b
1 1 b
1 1 b
1 1 b
1 1 b
1 1 b
2.56V - using Internal 2.56V Voltage Reference
1.28V (1/2 of 2.56V) - using Internal 2.56V Voltage Reference
0.64V (1/4 of 2.56V - using Internal 2.56V Voltage Reference
0.32V (1/8 of 2.56V) - using Internal 2.56V Voltage Reference
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20. DebugWIRE On-chip Debug System
20.1 Features
• Complete Program Flow Control
• Emulates All On-chip Functions, Both Digital and Analog, except RESET Pin
• Real-time Operation
• Symbolic Debugging Support (Both at C and Assembler Source Level, or for Other HLLs)
• Unlimited Number of Program Break Points (Using Software Break Points)
• Non-intrusive Operation
• Electrical Characteristics Identical to Real Device
• Automatic Configuration System
• High-Speed Operation
• Programming of Non-volatile Memories
20.2 Overview
The debugWIRE On-chip debug system uses a One-wire, bi-directional interface to control the
program flow, execute AVR® instructions in the CPU and to program the different non-volatile
memories.
20.3 Physical Interface
When the debugWIRE Enable (DWEN) Fuse is programmed and Lock bits are unpro-
grammed, the debugWIRE system within the target device is activated. The RESET port pin is
configured as a wire-AND (open-drain) bi-directional I/O pin with pull-up enabled and becomes
the communication gateway between target and emulator.
Figure 20-1. The debugWIRE Setup
+1.8 - +5.5V
Vcc
dW
dW (RESET)
GND
Figure 20-1 shows the schematic of a target MCU, with debugWIRE enabled, and the emula-
tor connector. The system clock is not affected by debugWIRE and will always be the clock
source selected by the CKSEL Fuses.
When designing a system where debugWIRE will be used, the following observations must be
made for correct operation:
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Atmel ATA5505 [Preliminary]
• Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up
resistor is not required for debugWIRE functionality.
• Connecting the RESET pin directly to VCC will not work.
• Capacitors connected to the RESET pin must be disconnected when using debugWire.
• All external reset sources must be disconnected.
20.4 Software Break Points
DebugWIRE supports Program memory break points by the Atmel® AVR® BREAK instruction.
Setting a break point in Atmel AVR Studio® will insert a BREAK instruction in the Program
memory. The instruction replaced by the BREAK instruction will be stored. When program
execution is continued, the stored instruction will be executed before continuing from the Pro-
gram memory. A break can be inserted manually by putting the BREAK instruction in the
program.
The Flash must be re-programmed each time a break point is changed. This is automatically
handled by Atmel AVR Studio through the debugWIRE interface. The use of break points will
therefore reduce the Flash Data retention. Devices used for debugging purposes should not
be shipped to end customers.
20.5 Limitations of DebugWIRE
The debugWIRE communication pin (dW) is physically located on the same pin as External
Reset (RESET). An External Reset source is therefore not supported when the debugWIRE is
enabled.
The debugWIRE system accurately emulates all I/O functions when running at full speed, i.e.,
when the program in the CPU is running. When the CPU is stopped, care must be taken while
accessing some of the I/O Registers via the debugger (Atmel AVR Studio).
A programmed DWEN Fuse enables some parts of the clock system to be running in all sleep
modes. This will increase the power consumption while in sleep. Thus, the DWEN Fuse
should be disabled when debugWire is not used.
20.6 DebugWIRE Related Register in I/O Memory
The following section describes the registers used with the debugWire.
20.6.1
DebugWIRE Data Register – DWDR
Bit
7
6
5
4
3
2
1
0
DWDR[7:0]
DWDR
Read/Write
Initial Value
R/W
R/W
0
R/W
0
R/W
R/W
R/W
0
R/W
0
R/W
0
0
0
0
The DWDR Register provides a communication channel from the running program in the MCU
to the debugger. This register is only accessible by the debugWIRE and can therefore not be
used as a general purpose register in the normal operations.
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21. Flash Programming
The device provides a Self-Programming mechanism for downloading and uploading program
code by the MCU itself. The Self-Programming can use any available data interface (i.e. LIN,
USART, ...) and associated protocol to read code and write (program) that code into the Pro-
gram memory.
The Program memory is updated in a page by page fashion. Before programming a page with
the data stored in the temporary page buffer, the page must be erased. The temporary page
buffer is filled one word at a time using SPM and the buffer can be filled either before the Page
Erase command or between a Page Erase and a Page Write operation:
• Alternative 1, fill the buffer before a Page Erase
– Fill temporary page buffer
– Perform a Page Erase
– Perform a Page Write
• Alternative 2, fill the buffer after Page Erase
– Perform a Page Erase
– Fill temporary page buffer
– Perform a Page Write
If only a part of the page needs to be changed, the rest of the page must be stored (for exam-
ple in the temporary page buffer) before the erase, and then be re-written. When using
alternative 1, the Boot Loader provides an effective Read-Modify-Write feature which allows
the user software to first read the page, do the necessary changes, and then write back the
modified data. If alternative 2 is used, it is not possible to read the old data while loading since
the page is already erased. The temporary page buffer can be accessed in a random
sequence. It is essential that the page address used in both the Page Erase and Page Write
operation is addressing the same page.
21.1 Self-Programming the Flash
21.1.1
Performing Page Erase by SPM
To execute Page Erase, set up the address in the Z-pointer, write “00000011 b” to SPMCSR
and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is
ignored. The page address must be written to PCPAGE in the Z-register. Other bits in the
Z-pointer will be ignored during this operation.
• The CPU is halted during the Page Erase operation.
21.1.2
Filling the Temporary Buffer (Page Loading)
To write an instruction word, set up the address in the Z-pointer and data in R1:R0, write
“00000001 b” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR.
The content of PCWORD in the Z-register is used to address the data in the temporary buffer.
The temporary buffer will auto-erase after a Page Write operation or by writing the CTPB bit in
SPMCSR. It is also erased after a system reset. Note that it is not possible to write more than
one time to each address without erasing the temporary buffer.
If the EEPROM is written in the middle of an SPM Page Load operation, all data loaded will be
lost.
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21.1.3
Performing a Page Write
To execute Page Write, set up the address in the Z-pointer, write “00000101 b” to SPMCSR
and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is
ignored. The page address must be written to PCPAGE. Other bits in the Z-pointer must be
written to zero during this operation.
• The CPU is halted during the Page Write operation.
21.2 Addressing the Flash During Self-Programming
The Z-pointer is used to address the SPM commands. The Z pointer consists of the Z-regis-
ters ZL and ZH in the register file. The number of bits actually used is implementation
dependent.
Bit
15
Z15
Z7
7
14
Z14
Z6
6
13
Z13
Z5
5
12
Z12
Z4
4
11
Z11
Z3
3
10
Z10
Z2
2
9
Z9
Z1
1
8
Z8
Z0
0
ZH (R31)
ZL (R30)
Bit
Since the Flash is organized in pages (see Table 22-7 on page 239), the Program Counter can
be treated as having two different sections. One section, consisting of the least significant bits,
is addressing the words within a page, while the most significant bits are addressing the
pages. This is shown in Figure 21-1.
Note that the Page Erase and Page Write operations are addressed independently. Therefore
it is of major importance that the software addresses the same page in both the Page Erase
and Page Write operation.
The LPM instruction uses the Z-pointer to store the address. Since this instruction addresses
the Flash byte-by-byte, also the LSB (bit Z0) of the Z-pointer is used.
Figure 21-1. Addressing the Flash During SPM (1)
BIT 15
ZPCMSB
PCMSB
ZPAGEMSB
1
0
0
Z - POINTER
PAGEMSB
PROGRAM COUNTER
PCPAGE
PCWORD
PAGE ADDRESS
WITHIN THE FLASH
WORD ADDRESS
WITHIN A PAGE
PROGRAM MEMORY
PAGE
PAGE
INSTRUCTION WORD
PCWORD[PAGEMSB:0]:
00
01
02
PAGEEND
Note:
1. The different variables used in Table 21-2 are listed in Table 22-7 on page 239.
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21.2.1
Store Program Memory Control and Status Register – SPMCSR
The Store Program Memory Control and Status Register contains the control bits needed to
control the Boot Loader operations.
Bit
7
–
6
5
4
CTPB
R/W
0
3
RFLB
R/W
0
2
PGWRT
R/W
0
1
PGERS
R/W
0
0
SPMEN
R/W
0
RWWSB
SIGRD
SPMCSR
Read/Write
Initial Value
R
0
R
0
R
0
• Bit 7 – Res: Reserved Bit
This bit is a reserved bit in the Atmel® AVR® and will always read as zero.
• Bit 6 – RWWSB: Read-While-Write Section Busy
This bit is for compatibility with devices supporting Read-While-Write. It will always read as
zero in Atmel AVR.
• Bit 5 – SIGRD: Signature Row Read
If this bit is written to one at the same time as SPMEN, the next LPM instruction within three
clock cycles will read a byte from the signature row into the destination register. See ”Reading
the Signature Row from Software” on page 232. for details. An SPM instruction within four
cycles after SIGRD and SPMEN are set will have no effect.
• Bit 4 – CTPB: Clear Temporary Page Buffer
If the CTPB bit is written while filling the temporary page buffer, the temporary page buffer will
be cleared and the data will be lost.
• Bit 3 – RFLB: Read Fuse and Lock Bits
An LPM instruction within three cycles after RFLB and SPMEN are set in the SPMCSR Regis-
ter, will read either the Lock bits or the Fuse bits (depending on Z0 in the Z-pointer) into the
destination register. See ”Reading the Fuse and Lock Bits from Software” on page 231. for
details.
• Bit 2 – PGWRT: Page Write
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four
clock cycles executes Page Write, with the data stored in the temporary buffer. The page
address is taken from the high part of the Z-pointer. The data in R1 and R0 are ignored. The
PGWRT bit will auto-clear upon completion of a Page Write, or if no SPM instruction is exe-
cuted within four clock cycles. The CPU is halted during the entire Page Write operation.
• Bit 1 – PGERS: Page Erase
If this bit is written to one at the same time as SPMEN, the next SPM instruction within four
clock cycles executes Page Erase. The page address is taken from the high part of the
Zpointer. The data in R1 and R0 are ignored. The PGERS bit will auto-clear upon completion
of a Page Erase, or if no SPM instruction is executed within four clock cycles. The CPU is
halted during the entire Page Write operation.
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• Bit 0 – SPMEN: Self Programming Enable
This bit enables the SPM instruction for the next four clock cycles. If written to one together
with either SIGRD, CTPB, RFLB, PGWRT, or PGERS, the following SPM instruction will have
a special meaning, see description above. If only SPMEN is written, the following SPM instruc-
tion will store the value in R1:R0 in the temporary page buffer addressed by the Z-pointer. The
LSB of the Z-pointer is ignored. The SPMEN bit will auto-clear upon completion of an SPM
instruction, or if no SPM instruction is executed within four clock cycles. During Page Erase
and Page Write, the SPMEN bit remains high until the operation is completed.
Writing any other combination than “10 0001 b”, “01 0001 b”, “00 1001 b”, “00 0101 b”,
“00 0011 b” or “00 0001 b” in the lower six bits will have no effect.
Note:
Only one SPM instruction should be active at any time.
21.2.2
21.2.3
EEPROM Write Prevents Writing to SPMCSR
Note that an EEPROM write operation will block all software programming to Flash. Reading
the Fuses and Lock bits from software will also be prevented during the EEPROM write opera-
tion. It is recommended that the user checks the status bit (EEPE) in the EECR Register and
verifies that the bit is cleared before writing to the SPMCSR Register.
Reading the Fuse and Lock Bits from Software
It is possible to read both the Fuse and Lock bits from software. To read the Lock bits, load the
Z-pointer with 0x0001 and set the RFLB and SPMEN bits in SPMCSR. When an LPM instruc-
tion is executed within three CPU cycles after the RFLB and SPMEN bits are set in SPMCSR,
the value of the Lock bits will be loaded in the destination register. The RFLB and SPMEN bits
will auto-clear upon completion of reading the Lock bits or if no LPM instruction is executed
within three CPU cycles or no SPM instruction is executed within four CPU cycles. When
RFLB and SPMEN are cleared, LPM will work as described in the Instruction set Manual.
Bit
7
6
5
4
3
2
1
0
Rd (Z=0x0001)
–
–
–
–
–
–
LB2
LB1
The algorithm for reading the Fuse Low byte is similar to the one described above for reading
the Lock bits. To read the Fuse Low byte, load the Z-pointer with 0x0000 and set the RFLB
and SPMEN bits in SPMCSR. When an LPM instruction is executed within three cycles after
the RFLB and SPMEN bits are set in the SPMCSR, the value of the Fuse Low byte (FLB) will
be loaded in the destination register as shown below. See Table 22-5 on page 238 for a
detailed description and mapping of the Fuse Low byte.
Bit
7
6
5
4
3
2
1
0
Rd (Z=0x0000)
FLB7
FLB6
FLB5
FLB4
FLB3
FLB2
FLB1
FLB0
Similarly, when reading the Fuse High byte (FHB), load 0x0003 in the Z-pointer. When an
LPM instruction is executed within three cycles after the RFLB and SPMEN bits are set in the
SPMCSR, the value of the Fuse High byte will be loaded in the destination register as shown
below. See Table 22-4 on page 237 for detailed description and mapping of the Fuse High
byte.
Bit
7
6
5
4
3
2
1
0
Rd (Z=0x0003)
FHB7
FHB6
FHB5
FHB4
FHB3
FHB2
FHB1
FHB0
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Similarly, when reading the Extended Fuse byte (EFB), load 0x0002 in the Z-pointer. When an
LPM instruction is executed within three cycles after the RFLB and SPMEN bits are set in the
SPMCSR, the value of the Extended Fuse byte will be loaded in the destination register as
shown below. See Table 22-3 on page 237 for detailed description and mapping of the
Extended Fuse byte.
Bit
7
6
5
4
3
2
1
0
Rd (Z=0x0002)
–
–
–
–
–
–
–
EFB0
Fuse and Lock bits that are programmed, will be read as zero. Fuse and Lock bits that are
unprogrammed, will be read as one.
21.2.4
Reading the Signature Row from Software
To read the Signature Row from software, load the Z-pointer with the signature byte address
given in Table 21-1 on page 232 and set the SIGRD and SPMEN bits in SPMCSR. When an
LPM instruction is executed within three CPU cycles after the SIGRD and SPMEN bits are set
in SPMCSR, the signature byte value will be loaded in the destination register. The SIGRD
and SPMEN bits will auto-clear upon completion of reading the Signature Row Lock bits or if
no LPM instruction is executed within three CPU cycles. When SIGRD and SPMEN are
cleared, LPM will work as described in the Instruction set Manual.
Table 21-1. Signature Row Addressing
Signature Byte
Device Signature Byte 0
Z-Pointer Address
0x0000
Device Signature Byte 1
0x0002
Device Signature Byte 2
0x0004
8MHz RC Oscillator Calibration Byte
TSOFFSET - Temp Sensor Offset
TSGAIN - Temp Sensor Gain
0x0001
0x0005
0x0007
Note:
All other addresses are reserved for future use.
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21.2.5
Preventing Flash Corruption
During periods of low VCC, the Flash program can be corrupted because the supply voltage is
too low for the CPU and the Flash to operate properly. These issues are the same as for board
level systems using the Flash, and the same design solutions should be applied.
A Flash program corruption can be caused by two situations when the voltage is too low.
• First, a regular write sequence to the Flash requires a minimum voltage to operate
correctly.
• Secondly, the CPU itself can execute instructions incorrectly, if the supply voltage for
executing instructions is too low.
Flash corruption can easily be avoided by following these design recommendations (one is
sufficient):
1. Keep the Atmel® AVR® RESET active (low) during periods of insufficient power sup-
ply voltage. This can be done by enabling the internal Brown-out Detector (BOD) if
the operating voltage matches the detection level. If not, an external low VCC reset
protection circuit can be used. If a reset occurs while a write operation is in progress,
the write operation will be completed provided that the power supply voltage is
sufficient.
2. Keep the Atmel AVR core in Power-down sleep mode during periods of low VCC. This
will prevent the CPU from attempting to decode and execute instructions, effectively
protecting the SPMCSR Register and thus the Flash from unintentional writes.
21.2.6
Programming Time for Flash when Using SPM
The calibrated RC Oscillator is used to time Flash accesses. Table 21-2 shows the typical pro-
gramming time for Flash accesses from the CPU.
Table 21-2. SPM Programming Time
Symbol
Min Programming Time
Max Programming Time
Flash write (Page Erase, Page Write,
and write Lock bits by SPM)
3.7ms
4.5ms
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21.2.7
Simple Assembly Code Example for a Boot Loader
Note that the RWWSB bit will always be read as zero in the Atmel® AVR®. Nevertheless, it is
recommended to check this bit as shown in the code example, to ensure compatibility with
devices supporting Read-While-Write.
;- The routine writes one page of data from RAM to Flash
;
;
the first data location in RAM is pointed to by the Y-pointer
the first data location in Flash is pointed to by the Z-pointer
;- Error handling is not included
;- Registers used: r0, r1, temp1 (r16), temp2 (r17), looplo (r24),
;
loophi (r25), spmcsrval (r20)
; -Storing and restoring of registers is not included in the routine
register usage can be optimized at the expense of code size
;
.equ PAGESIZEB = PAGESIZE*2
.org SMALLBOOTSTART
; AGESIZEB is page size in BYTES, not words
Write_page:
; Page Erase
ldi
spmcsrval, (1<<PGERS) | (1<<SELFPGEN)
rcall Do_spm
; Clear temporary page buffer
spmcsrval, (1<<CPTB) | (1<<SELFPGEN)
ldi
rcall Do_spm
; Transfer data from RAM to Flash temporary page buffer
ldi
ldi
looplo, low(PAGESIZEB)
loophi, high(PAGESIZEB)
; init loop variable
; not required for PAGESIZEB<=256
Wrloop:
ld
ld
r0, Y+
r1, Y+
spmcsrval, (1<<SELFPGEN)
ldi
rcall Do_spm
adiw
sbiw
brne
ZH:ZL, 2
loophi:looplo, 2
Wrloop
; use subi for PAGESIZEB<=256
; Execute Page Write
subi
sbci
ldi
ZL, low(PAGESIZEB) ; restore pointer
ZH, high(PAGESIZEB) ; not required for PAGESIZEB<=256
spmcsrval, (1<<PGWRT) | (1<<SELFPGEN)
rcall Do_spm
; Clear temporary page buffer
spmcsrval, (1<<CPTB) | (1<<SELFPGEN)
ldi
rcall Do_spm
; Read back and check, optional
ldi
looplo, low(PAGESIZEB) ; init loop variable
loophi, high(PAGESIZEB) ; not required for PAGESIZEB<=256
ldi
subi
sbci
YL, low(PAGESIZEB)
YH, high(PAGESIZEB)
; restore pointer
Rdloop:
lpm
r0, Z+
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ld
r1, Y+
r0, r1
cpse
rjmp
sbiw
brne
Error
loophi:looplo, 1
Rdloop
; use subi for PAGESIZEB<=256
; To ensure compatibility with devices supporting Read-While-Write
; Return to RWW section
; Verify that RWW section is safe to read
Return:
in
sbrs
temp1, SPMCSR
temp1, RWWSB
; If RWWSB is set, the RWW section is not ready
yet
ret
; Clear temporary page buffer
ldi
call
rjmp
spmcsrval, (1<<CPTB) | (1<<SELFPGEN)
Do_spm
Return
Do_spm:
; Check for previous SPM complete
Wait_spm:
in
sbrc
rjmp
temp1, SPMCSR
temp1, SELFPGEN
Wait_spm
; Input: spmcsrval determines SPM action
; Disable interrupts if enabled, store status
in
temp2, SREG
cli
; Check that no EEPROM write access is present
Wait_ee:
sbic EECR, EEPE
rjmp Wait_ee
; SPM timed sequence
out
spm
SPMCSR, spmcsrval
; Restore SREG (to enable interrupts if originally enabled)
out
ret
SREG, temp2
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22. Memory Programming
22.1 Program and Data Memory Lock Bits
The Atmel® AVR® provides two Lock bits which can be left unprogrammed (“1”) or can be pro-
grammed (“0”) to obtain the additional features listed in Table 22-2. The Lock bits can only be
erased to “1” with the Chip Erase command. The Atmel AVR has no separate Boot Loader
section.
Table 22-1. Lock Bit Byte(Note:)
Lock Bit Byte
Bit No
Description
Default Value
7
6
5
4
3
2
1
0
–
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
–
–
–
–
–
LB2
LB1
Lock bit
Lock bit
Note:
“1” means unprogrammed, “0” means programmed.
Table 22-2. Lock Bit Protection Modes(1)(2)
Memory Lock Bits
Protection Type
LB Mode
LB2
LB1
1
1
1
No memory lock features enabled.
Further programming of the Flash and EEPROM is disabled in
Parallel and Serial Programming mode. The Fuse bits are locked
in both Serial and Parallel Programming mode.(1)
2
1
0
0
0
Further programming and verification of the Flash and EEPROM
is disabled in Parallel and Serial Programming mode. The Fuse
bits are locked in both Serial and Parallel Programming mode.(1)
3
Notes: 1. Program the Fuse bits before programming the LB1 and LB2.
2. “1” means unprogrammed, “0” means programmed
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22.2 Fuse Bits
The Atmel® AVR® has three Fuse bytes. Table 22-3, Table 22-4 & Table 22-5 describe briefly
the functionality of all the fuses and how they are mapped into the Fuse bytes.
The SPM instruction is enabled for the whole Flash if the SELFPRGEN fuse is programmed
(“0”), otherwise it is disabled.
Note that the fuses are read as logical zero, “0”, if they are programmed.
Table 22-3. Extended Fuse Byte
Fuse Extended Byte
Bit No Description
Default Value
–
7
6
5
4
3
2
1
0
–
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
1 (unprogrammed)
–
–
–
–
–
–
–
–
–
–
–
–
SELFPRGEN
Self Programming Enable
Table 22-4. Fuse High Byte
Fuse High Byte
RSTDISBL(1)
DWEN
Bit No Description
Default Value
7
6
External Reset Disable
1 (unprogrammed)
1 (unprogrammed)
DebugWIRE Enable
Enable Serial Program
and Data Downloading
0 (programmed,
SPIEN(2)
WDTON(3)
EESAVE
5
4
3
SPI programming enabled)
Watchdog Timer always on
1 (unprogrammed)
EEPROM memory is preserved 1 (unprogrammed,
through the Chip Erase
EEPROM not preserved)
BODLEVEL2(4)
BODLEVEL1(4)
BODLEVEL0(4)
2
1
0
Brown-out Detector trigger level 1 (unprogrammed)
Brown-out Detector trigger level 1 (unprogrammed)
Brown-out Detector trigger level 1 (unprogrammed)
Notes: 1. See ”Alternate Functions of Port B” on page 84. for description of RSTDISBL Fuse.
2. The SPIEN Fuse is not accessible in serial programming mode.
3. See ”Watchdog Timer Control Register - WDTCR” on page 61. for details.
4. See Table 23-5 on page 259 for BODLEVEL Fuse coding.
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Table 22-5. Fuse Low Byte
Fuse Low Byte
CKDIV8(4)
CKOUT(3)
SUT1
Bit No
Description
Default Value
7
6
5
4
3
2
1
0
Divide clock by 8
Clock output
0 (programmed)
1 (unprogrammed)
1 (unprogrammed)(1)
0 (programmed)(1)
0 (programmed)(2)
0 (programmed)(2)
1 (unprogrammed)(2)
0 (programmed)(2)
Select start-up time
Select start-up time
Select Clock source
Select Clock source
Select Clock source
Select Clock source
SUT0
CKSEL3
CKSEL2
CKSEL1
CKSEL0
Notes: 1. The default value of SUT1..0 results in maximum start-up time for the default clock source.
See Table 4-4 on page 31 for details.
2. The default setting of CKSEL3..0 results in internal RC Oscillator at 8MHz. See Table 4-3 on
page 31 for details.
3. The CKOUT Fuse allows the system clock to be output on PORTB5. See ”Clock Output Buf-
fer” on page 35. for details.
4. See ”System Clock Prescaler” on page 41.for details.
22.2.1
Latching of Fuses
The fuse values are latched when the device enters programming mode and changes of the
fuse values will have no effect until the part leaves Programming mode. This does not apply to
the EESAVE Fuse which will take effect once it is programmed. The fuses are also latched on
Power-up in Normal mode.
22.3 Signature Bytes
All Atmel® microcontrollers have a three-byte signature code which identifies the device. This
code can be read in both serial and parallel mode, also when the device is locked. The three
bytes reside in a separate address space.
Table 22-6. Signature Bytes
Device
Address
Value
0x1E
0x94
Signature Byte Description
Indicates manufactured by Atmel
Indicates 16 KB Flash memory
0
1
Atmel AVR®
Indicates Atmel AVR device when address 1 contains
0x94
2
0x87
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22.4 Calibration Byte
22.5 Page Size
The Atmel® AVR® has a byte calibration value for the internal RC Oscillator. This byte resides
in the high byte of address 0x000 in the signature address space. During reset, this byte is
automatically written into the OSCCAL Register to ensure correct frequency of the calibrated
RC Oscillator.
Table 22-7. Number of Words in a Page and No. of Pages in the Flash
Device
Flash Size Page Size PCWORD No. of Pages PCPAGE PCMSB
8K words 64words PC[5:0] 128 PC[12:6] 12
Atmel AVR
Table 22-8. Number of Words in a Page and No. of Pages in the EEPROM
Device
EEPROM Size Page Size PCWORD No. of Pages PCPAGE EEAMSB
512bytes 4bytes EEA[1:0] 128 EEA[8:2]
Atmel AVR
8
22.6 Parallel Programming Parameters, Pin Mapping, and Commands
This section describes how to parallel program and verify Flash Program memory, EEPROM
Data memory, Memory Lock bits, and Fuse bits in the Atmel AVR. Pulses are assumed to be
at least 250 ns unless otherwise noted.
22.6.1
Signal Names
In this section, some pins of the Atmel AVR are referenced by signal names describing their
functionality during parallel programming, see Figure 22-1 and Figure 22-9. Pins not described
in the following table are referenced by pin names.
The XA1/XA0 pins determine the action executed when the XTAL1 pin is given a positive
pulse. The bit coding is shown in Figure 22-11.
When pulsing WR or OE, the command loaded determines the action executed. The different
commands are shown in Figure 22-12.
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Figure 22-1. Parallel programming
WR
XA0
PB0
+4.5 - +5.5V
+4.5 - +5.5V
PB1
Vcc
XA1 / BS2
PAGEL / BS1
PB2
PB3
AVcc
XTAL1 / PB4
PB5
OE
RDY / BSY
PB6
PA7 - PA0
DATA
+12 V
RESET / PB7
GND
Note:
VCC - 0.3V < AVCC < VCC + 0.3V, however, AVCC should always be within 4.5 - 5.5V
Table 22-9. Pin Name Mapping
Signal Name in
Programming Mode
Pin Name
PB0
I/O Function
WR
I
I
Write Pulse (Active low).
XTAL1 Action Bit 0
XA0
PB1
- XTAL1 Action Bit 1
- Byte Select 2
XA1 / BS2
PB2
PB3
I
I
(“0” selects low byte, “1” selects 2’nd high byte)
- Program Memory and EEPROM data Page Load
- Byte Select 1
PAGEL / BS1
(“0” selects low byte, “1” selects high byte)
PB4
PB5
I
I
XTAL1 (Clock input)
OE
Output Enable (Active low).
0: Device is busy programming,
1: Device is ready for new command.
RDY / BSY
PB6
O
I
- Reset (Active low)
- Parallel programming mode (+12V).
+12V
DATA
PB7
PA7-PA0
I/O Bi-directional Data bus (Output when OE is low).
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Table 22-10. Pin Values Used to Enter Programming Mode
Pin
PAGEL / BS1
XA1 / BS2
XA0
Symbol
Value
Prog_enable[3]
Prog_enable[2]
Prog_enable[1]
Prog_enable[0]
0
0
0
0
WR
Table 22-11. XA1 and XA0 Coding
XA1
XA0
Action when XTAL1 is Pulsed
Load Flash or EEPROM Address (High or low address byte determined by
BS1).
0
0
0
1
1
1
0
1
Load Data (High or Low data byte for Flash determined by BS1).
Load Command
No Action, Idle
Table 22-12. Command Byte Bit Coding
Command Byte
1000 0000 b
0100 0000 b
0010 0000 b
0001 0000 b
0001 0001 b
0000 1000 b
0000 0100 b
0000 0010 b
0000 0011 b
Command Executed
Chip Erase
Write Fuse bits
Write Lock bits
Write Flash
Write EEPROM
Read Signature bytes and Calibration byte
Read Fuse and Lock bits
Read Flash
Read EEPROM
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22.7 Parallel Programming
22.7.1
Enter Programming Mode
The following algorithm puts the device in parallel programming mode:
1. Apply 4.5 - 5.5V between VCC and GND.
2. Set RESET to “0” and toggle XTAL1 at least six times.
3. Set the Prog_enable pins listed in Table 22-10 on page 241 to “0000 b” and wait at
least 100ns.
4. Apply 11.5 - 12.5V to RESET. Any activity on Prog_enable pins within 100 ns after
+12V has been applied to RESET, will cause the device to fail entering programming
mode.
5. Wait at least 50µs before sending a new command.
22.7.2
Considerations for Efficient Programming
The loaded command and address are retained in the device during programming. For effi-
cient programming, the following should be considered.
• The command needs only be loaded once when writing or reading multiple memory
locations.
• Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the
EESAVE Fuse is programmed) and Flash after a Chip Erase.
• Address high byte needs only be loaded before programming or reading a new 256 word
window in Flash or 256 byte EEPROM. This consideration also applies to Signature bytes
reading.
22.7.3
Chip Erase
The Chip Erase will erase the Flash and EEPROM(Note:) memories plus Lock bits. The Lock
bits are not reset until the program memory has been completely erased. The Fuse bits are
not changed. A Chip Erase must be performed before the Flash and/or EEPROM are
reprogrammed.
Note:
The EEPRPOM memory is preserved during Chip Erase if the EESAVE Fuse is programmed.
Load Command “Chip Erase”
1. Set XA1, XA0 to “1,0 ”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “1000 0000 b”. This is the command for Chip Erase.
4. Give XTAL1 a positive pulse. This loads the command.
5. Give WR a negative pulse. This starts the Chip Erase. RDY/BSY goes low.
6. Wait until RDY/BSY goes high before loading a new command.
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22.7.4
Programming the Flash
The Flash is organized in pages, see Table 22-7 on page 239. When programming the Flash,
the program data is latched into a page buffer. This allows one page of program data to be
programmed simultaneously. The following procedure describes how to program the entire
Flash memory:
A. Load Command “Write Flash”
1. Set XA1, XA0 to “1,0”. This enables command loading.
2. Set BS1 to “0”.
3. Set DATA to “0001 0000 b”. This is the command for Write Flash.
4. Give XTAL1 a positive pulse. This loads the command.
B. Load Address Low byte
1. Set XA1, XA0 to “00”. This enables address loading.
2. Set BS1 to “0”. This selects low address.
3. Set DATA = Address low byte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the address low byte.
C. Load Data Low Byte
1. Set XA1, XA0 to “0,1”. This enables data loading.
2. Set DATA = Data low byte (0x00 - 0xFF).
3. Give XTAL1 a positive pulse. This loads the data byte.
D. Load Data High Byte
1. Set BS1 to “1”. This selects high data byte.
2. Set XA1, XA0 to “0,1”. This enables data loading.
3. Set DATA = Data high byte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the data byte.
E. Latch Data
1. Set BS1 to “1”. This selects high data byte.
2. Give PAGEL a positive pulse. This latches the data bytes. (See Figure 22-3 for signal
waveforms)
F. Repeat B through E until the entire buffer is filled or until all data within the page is loaded.
While the lower bits in the address are mapped to words within the page, the higher bits
address the pages within the FLASH. This is illustrated in Figure 22-2 on page 244. Note that
if less than eight bits are required to address words in the page (pagesize < 256), the most sig-
nificant bit(s) in the address low byte are used to address the page when performing a Page
Write.
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G. Load Address High byte
1. Set XA1, XA0 to “0,0”. This enables address loading.
2. Set BS1 to “1”. This selects high address.
3. Set DATA = Address high byte (0x00 - 0xFF).
4. Give XTAL1 a positive pulse. This loads the address high byte.
H. Program Page
1. Give WR a negative pulse. This starts programming of the entire page of data.
RDY/BSY goes low.
2. Wait until RDY/BSY goes high (See Figure 22-3 for signal waveforms).
I. Repeat B through H until the entire Flash is programmed or until all data has been
programmed.
J. End Page Programming
1. 1. Set XA1, XA0 to “1,0”. This enables command loading.
2. Set DATA to “0000 0000 b”. This is the command for No Operation.
3. Give XTAL1 a positive pulse. This loads the command, and the internal write signals
are reset.
Figure 22-2. Addressing the Flash Which is Organized in Pages
PCMSB
PAGEMSB
PROGRAM COUNTER
PCPAGE
PCWORD
PAGE ADDRESS
WITHIN THE FLASH
WORD ADDRESS
WITHIN A PAGE
PROGRAM MEMORY
PAGE
INSTRUCTION WORD
PCWORD[PAGEMSB:0]:
00
PAGE
01
02
PAGEEND
Note:
1. PCPAGE and PCWORD are listed in
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Figure 22-3. Programming the Flash Waveforms (1)
F
A
B
C
D
E
B
C
D
E
G
H
0x10
ADDR. LOW
DATA LOW
DATA HIGH
ADDR. LOW DATA LOW
DATA HIGH
ADDR. HIGH
XX
XX
XX
DATA
XA1 / BS2
XA0
PAGEL / BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
Note:
1. “XX” is don’t care. The letters refer to the programming description above.
22.7.5
Programming the EEPROM
The EEPROM is organized in pages, see Table 22-8 on page 239. When programming the
EEPROM, the program data is latched into a page buffer. This allows one page of data to be
programmed simultaneously. The programming algorithm for the EEPROM data memory is as
follows (refer to “Programming the Flash” on page 243 for details on Command, Address and
Data loading):
A: Load Command “0001 0001 b”.
G: Load Address High Byte (0x00 - 0xFF).
B: Load Address Low Byte (0x00 - 0xFF).
C: Load Data (0x00 - 0xFF).
E: Latch data (give PAGEL a positive pulse).
K: Repeat A through E until the entire buffer is filled.
L: Program EEPROM page
1. Set BS1 to “0”.
2. Give WR a negative pulse. This starts programming of the EEPROM page. RDY/BSY
goes low.
3. Wait until to RDY/BSY goes high before programming the next page (See Figure 22-4
for signal waveforms).
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Figure 22-4. Programming the EEPROM Waveforms
K
A
G
B
C
E
B
C
E
L
0x11
ADDR. HIGH
ADDR. LOW
DATA
ADDR. LOW
DATA
XX
XX
DATA
XA1 / BS2
XA0
PAGEL / BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
22.7.6
Reading the Flash
The algorithm for reading the Flash memory is as follows (refer to “Programming the Flash” on
page 243 for details on Command and Address loading):
1. A: Load Command “0000 0010 b”.
2. G: Load Address High Byte (0x00 - 0xFF).
3. B: Load Address Low Byte (0x00 - 0xFF).
4. Set OE to “0”, and BS1 to “0”. The Flash word low byte can now be read at DATA.
5. Set BS1 to “1”. The Flash word high byte can now be read at DATA.
6. Set OE to “1”.
22.7.7
Reading the EEPROM
The algorithm for reading the EEPROM memory is as follows (refer to “Programming the
Flash” on page 243 for details on Command and Address loading):
1. A: Load Command “0000 0011 b”.
2. G: Load Address High Byte (0x00 - 0xFF).
3. B: Load Address Low Byte (0x00 - 0xFF).
4. Set OE to “0”, and BS1 to “0”. The EEPROM Data byte can now be read at DATA.
5. Set OE to “1”.
22.7.8
Programming the Fuse Low Bits
The algorithm for programming the Fuse Low bits is as follows (refer to “Programming the
Flash” on page 243 for details on Command and Data loading):
1. A: Load Command “0100 0000 b”.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Give WR a negative pulse and wait for RDY/BSY to go high.
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22.7.9
Programming the Fuse High Bits
The algorithm for programming the Fuse High bits is as follows (refer to “Programming the
Flash” on page 243 for details on Command and Data loading):
1. A: Load Command “0100 0000 b”.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Set BS1 to “1” and BS2 to “0”. This selects high data byte.
4. Give WR a negative pulse and wait for RDY/BSY to go high.
5. Set BS1 to “0”. This selects low data byte.
22.7.10 Programming the Extended Fuse Bits
The algorithm for programming the Extended Fuse bits is as follows (refer to “Programming
the Flash” on page 243 for details on Command and Data loading):
1. A: Load Command “0100 0000 b”.
2. C: Load Data Low Byte. Bit n = “0” programs and bit n = “1” erases the Fuse bit.
3. Set BS1 to “0” and BS2 to “1”. This selects extended data byte.
4. Give WR a negative pulse and wait for RDY/BSY to go high.
5. Set BS2 to “0”. This selects low data byte.
Figure 22-5. Programming the FUSES Waveforms
Write Fuse Low byte
Write Fuse high byte
Write Extended Fuse byte
C
A
C
A
C
A
0x40
DATA
XX
0x40
DATA
XX
0x40
DATA
XX
DATA
XA1 / BS2
XA0
PAGEL / BS1
XTAL1
WR
RDY/BSY
RESET +12V
OE
22.7.11 Programming the Lock Bits
The algorithm for programming the Lock bits is as follows (refer to “Programming the Flash” on
page 243 for details on Command and Data loading):
1. A: Load Command “0010 0000 b”.
2. C: Load Data Low Byte. Bit n = “0” programs the Lock bit. If LB mode 3 is pro-
grammed (LB1 and LB2 is programmed), it is not possible to re-program the Lock bits
by any External Programming mode.
3. Give WR a negative pulse and wait for RDY/BSY to go high.
4. The Lock bits can only be cleared by executing Chip Erase.
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22.7.12 Reading the Fuse and Lock Bits
The algorithm for reading the Fuse and Lock bits is as follows (refer to “Programming the
Flash” on page 243 for details on Command loading):
1. A: Load Command “0000 0100 b”.
2. Set OE to “0”, BS2 to “0” and BS1 to “0”. The status of the Fuse Low bits can now be
read at DATA (“0” means programmed).
3. Set OE to “0”, BS2 to “1” and BS1 to “1”. The status of the Fuse High bits can now be
read at DATA (“0” means programmed).
4. Set OE to “0”, BS2 to “1”, and BS1 to “0”. The status of the Extended Fuse bits can
now be read at DATA (“0” means programmed).
5. Set OE to “0”, BS2 to “0” and BS1 to “1”. The status of the Lock bits can now be read
at DATA (“0” means programmed).
6. Set OE to “1”.
Figure 22-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read
0
1
0
1
Fuse Low Byte
Extended Fuse Byte
Lock Bits
0
1
DATA
BS2
BS1
Fuse High Byte
BS2
22.7.13 Reading the Signature Bytes
The algorithm for reading the Signature bytes is as follows (refer to “Programming the Flash”
on page 243 for details on Command and Address loading):
1. A: Load Command “0000 1000 b”.
2. B: Load Address Low Byte (0x00 - 0x02).
3. Set OE to “0”, and BS to “0”. The selected Signature byte can now be read at DATA.
4. Set OE to “1”.
22.7.14 Reading the 8 MHz RC Oscillator Calibration Byte
The algorithm for reading the 8 MHz RC Oscillator Calibration byte is as follows (refer to “Pro-
gramming the Flash” on page 243 for details on Command and Address loading):
1. A: Load Command “0000 1000 b”.
2. B: Load Address Low Byte, 0x00.
3. Set OE to “0”, and BS1 to “1”. The 8 MHz RC Oscillator Calibration byte can now be
read at DATA.
4. Set OE to “1”.
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22.7.15 Reading the Temperature Sensor Parameter Bytes
The algorithm for reading the Temperature Sensor parameter bytes is as follows (refer to “Pro-
gramming the Flash” on page 243 for details on Command and Address loading):
1. A: Load Command “0000 1000 b”.
2. B: Load Address Low Byte, 0x0003 or 0x0005.
3. Set OE to “0”, and BS1 to “1”. The Temperature Sensor parameter byte can now be
read at DATA.
4. Set OE to “1”.
22.8 Serial Downloading
Both the Flash and EEPROM memory arrays can be programmed using the serial SPI bus
while RESET is pulled to GND. The serial interface consists of pins SCK, MOSI (input) and
MISO (output). After RESET is set low, the Programming Enable instruction needs to be exe-
cuted first before program/erase operations can be executed.
Note:
In Table 22-13, the pin mapping for SPI programming is listed. Not all parts use the SPI pins
dedicated for the internal SPI interface.
Figure 22-7. Serial Programming and Verify (Note:)
+2.7 - +5.5V
Vcc
MOSI
MISO
SCK
PA4
PA2
PA5
RESET / PB7
GND
Note:
If the device is clocked by the internal Oscillator, it is no need to connect a clock source to the
XTAL1 pin
Table 22-13. Pin Mapping Serial Programming
Symbol
MOSI
MISO
SCK
Pin Name
PA4
I/O Function
I
O
I
Serial Data In
PA2
Serial Data Out
Serial Clock
PA5
When programming the EEPROM, an auto-erase cycle is built into the self-timed program-
ming operation (in the Serial mode ONLY) and there is no need to first execute the Chip Erase
instruction. The Chip Erase operation turns the content of every memory location in both the
Program and EEPROM arrays into 0xFF.
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Depending on CKSEL Fuses, a valid clock must be present. The minimum low and high peri-
ods for the serial clock (SCK) input are defined as follows:
Low: > 2 CPU clock cycles for f < 12MHz, 3 CPU clock cycles for f >= 12MHz
ck
ck
High:> 2 CPU clock cycles for f < 12MHz, 3 CPU clock cycles for f >= 12MHz
ck
ck
22.8.1
Serial Programming Algorithm
When writing serial data to the Atmel® AVR®, data is clocked on the rising edge of SCK.
When reading data from the Atmel AVR, data is clocked on the falling edge of SCK. See Fig-
ure 22-7 and Figure 22-8 for timing details.
To program and verify the Atmel AVR in the Serial Programming mode, the following
sequence is recommended (see four byte instruction formats in Table 22-15 on page 251):
1. Power-up sequence:
Apply power between VCC and GND while RESET and SCK are set to “0”. In some
systems, the programmer can not guarantee that SCK is held low during power-up. In
this case, RESET must be given a positive pulse of at least two CPU clock cycles
duration after SCK has been set to “0”.
2. Wait for at least 20 ms and enable serial programming by sending the Programming
Enable serial instruction to pin MOSI.
3. The serial programming instructions will not work if the communication is out of syn-
chronization. When in sync. the second byte (0x53), will echo back when issuing the
third byte of the Programming Enable instruction. Whether the echo is correct or not,
all four bytes of the instruction must be transmitted. If the 0x53 did not echo back,
give RESET a positive pulse and issue a new Programming Enable command.
4. The Flash is programmed one page at a time. The memory page is loaded one byte
at a time by supplying the 5 LSB of the address and data together with the Load Pro-
gram memory Page instruction. To ensure correct loading of the page, the data low
byte must be loaded before data high byte is applied for a given address. The Pro-
gram memory Page is stored by loading the Write Program memory Page instruction
with the 6 MSB of the address. If polling (RDY/BSY) is not used, the user must wait at
least t WD_FLASH before issuing the next page. (See Table 22-14) Accessing the serial
programming interface before the Flash write operation completes can result in incor-
rect programming.
5. A: The EEPROM array is programmed one byte at a time by supplying the address
and data together with the appropriate Write instruction. An EEPROM memory loca-
tion is first automatically erased before new data is written. If polling (RDY/BSY) is not
used, the user must wait at least t WD_EEPROM before issuing the next byte. (See Table
22-14) In a chip erased device, no 0xFFs in the data file(s) need to be programmed.
B: The EEPROM array is programmed one page at a time. The Memory page is
loaded one byte at a time by supplying the 2 LSB of the address and data together
with the Load EEPROM Memory Page instruction. The EEPROM Memory Page is
stored by loading the Write EEPROM Memory Page Instruction with the 6 MSB of the
address. When using EEPROM page access only byte locations loaded with the
Load EEPROM Memory Page instruction is altered. The remaining locations remain
unchanged. If polling (RDY/BSY) is not used, the used must wait at least t WD_EEPROM
before issuing the next page (See Table 22-8). In a chip erased device, no 0xFF in
the data file(s) need to be programmed.
6. Any memory location can be verified by using the Read instruction which returns the
content at the selected address at serial output MISO.
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7. At the end of the programming session, RESET can be set high to commence normal
operation.
8. Power-off sequence (if needed):
Set RESET to “1”.
Turn VCC power off.
Table 22-14. Minimum Wait Delay Before Writing the Next Flash or EEPROM Location
Symbol Minimum Wait Delay
t WD_FLASH 4.5ms
t WD_EEPROM 4.0ms
t WD_ERASE 4.0ms
t WD_FUSE 4.5ms
22.8.2
Serial Programming Instruction set
Table 22-15 on page 251 and Figure 22-8 on page 253 describes the Instruction set
Table 22-15. Serial Programming Instruction Set
Instruction Format
Instruction/Operation
Byte 1
0xAC
0xAC
0xF0
Byte 2
Byte 3
0x00
0x00
0x00
Byte4
0x00
Programming Enable
0x53
0x80
0x00
Chip Erase (Program Memory/EEPROM)
Poll RDY/BSY
0x00
data byte out
Load Instructions
Load Extended Address byte(1)
Load Program Memory Page, High byte
Load Program Memory Page, Low byte
Load EEPROM Memory Page (page access)
Read Instructions
0x4D
0x48
0x40
0xC1
0x00
add. MSB
add. MSB
0x00
Extended add.
add. LSB
0x00
high data byte in
low data byte in
data byte in
add. LSB
0000 000aa b
Read Program Memory, High byte
Read Program Memory, Low byte
Read EEPROM Memory
Read Lock bits
0x28
0x20
0xA0
0x58
0x30
0x50
0x58
0x50
0x38
add. MSB
add. MSB
0x00
add. LSB
add. LSB
00aa aaaa
0x00
high data byte out
low data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
data byte out
0x00
Read Signature Byte
0x00
0000 000aa
0x00
Read Fuse bits
0x00
Read Fuse High bits
0x08
0x00
Read Extended Fuse Bits
0x08
0x00
Read Calibration Byte
0x00
0x00
Write Instructions(6)
Write Program Memory Page
0x4C
add. MSB
add. LSB
0x00
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Table 22-15. Serial Programming Instruction Set (Continued)
Instruction Format
Instruction/Operation
Write EEPROM Memory
Write EEPROM Memory Page (page access)
Write Lock bits
Byte 1
0xC0
0xC2
0xAC
0xAC
0xAC
0xAC
Byte 2
Byte 3
00aa aaaa b
00aa aa00 b
0x00
Byte4
0x00
0x00
0xE0
0xA0
0xA8
0xA4
data byte in
0x00
data byte in
data byte in
data byte in
data byte in
Write Fuse bits
0x00
Write Fuse High bits
0x00
Write Extended Fuse Bits
0x00
Notes: 1. Not all instructions are applicable for all parts.
2. a = address
3. Bits are programmed ‘0’, unprogrammed ‘1’.
4. To ensure future compatibility, unused Fuses and Lock bits should be unprogrammed (‘1’).
5. Refer to the corresponding section for Fuse and Lock bits, Calibration and Signature bytes
and Page size.
6. Instructions accessing program memory use a word address. This address may be random
within the page range.
7. See http://www.atmel.com/avr for Application Notes regarding programming and
programmers.
If the LSB in RDY/BSY data byte out is ‘1’, a programming operation is still pending. Wait until
this bit returns ‘0’ before the next instruction is carried out.
Within the same page, the low data byte must be loaded prior to the high data byte.
After data is loaded to the page buffer, program the EEPROM page, see Figure 22-8 on page
253.
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Figure 22-8. Serial programming Instruction Example
Serial Programming Instruction
Load Program Memory Page (High/Low Byte) /
Load EEPROM Memory Page (Page Access)
Write Program Memory Page /
Write EEPROM Memory Page
Byte 1
Byte 2
Byte 3
Byte 4
Byte 1
Byte 2
Byte 3
Byte 4
Addr. MSB
Addr. LSB
Addr. MSB
Addr. MSB
Bit 15
B
0
Bit 15
B
0
Page Buffer
Page Offset
Page 0
Page 1
Page 2
Page Number
Page N-1
Program Memory /
EEPROM Memory
22.9 Serial Programming Characteristics
Figure 22-9. Serial Programming Waveforms
SERIAL DATA INPUT
(MOSI)
MSB
LSB
LSB
SERIAL DATA OUTPUT
(MISO)
MSB
SERIAL CLOCK INPUT
(SCK)
SAMPLE
For characteristics of the SPI module, See ”SPI Timing Characteristics” on page 267.
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23. Electrical Characteristics
23.1 Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All values are valid for the Atmel® AVR® microcontroller. The parameters for the reader/writer front end are listed in Section 23.7 “Front
End Reader/Writer” on page 260.
Parameter
Value
Operating Temperature
–40°C to +85°C
–55°C to +125°C
–0.5V to Vcc+0.5V
–0.5V to +13.0V
–0.5V to 6.0V
Storage Temperature
Voltage on any Pin except RESET with respect to Ground
Voltage on RESET with respect to Ground
Voltage on Vcc with respect to Ground
DC Current per I/O Pin
40.0mA
DC Current Vcc and GND Pins
200.0mA
Injection Current at VCC = 0V to 5V(2)
±5.0mA(1)
Notes: 1. Maximum current per port = ±30mA
2. Functional corruption may occur
254
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
23.2 DC Characteristics
TA = –40°C to +85°C, VCC = 2.7V to 5.5V (unless otherwise noted)
Symbol Parameter
Condition
Min.
Typ.(1)
Max.
Unit
Except XTAL1 and RESET
pins
VIL
–0.5
0.2 Vcc(2)
V
XTAL1 pin - External Clock
Selected
VIL1
–0.5
0.1 Vcc(2)
V
Input Low Voltage
VIL2
VIL3
RESET pin
–0.5
–0.5
0.2 Vcc(2)
0.2 Vcc(2)
V
V
RESET pin as I/O
Except XTAL1 and RESET
pins
VIH
0.7 Vcc(3)
0.8 Vcc(3)
Vcc + 0.5
Vcc + 0.5
V
V
XTAL1 pin - External Clock
Selected
VIH1
Input High Voltage
VIH2
VIH3
RESET pin
0.9 Vcc(3)
0.7 Vcc(3)
Vcc + 0.5
Vcc + 0.5
V
V
RESET pin as I/O
Output Low Voltage(4)
(Ports A, B,)
Output High Voltage(5)
(Ports A, B)
IOL = 10mA, Vcc = 5V
IOL = 5mA, Vcc = 3V
0.6
0.5
VOL
VOH
IIL
V
V
I
OH = –10mA, Vcc = 5V
4.3
2.5
IOH = –5mA, Vcc = 3V
Input Leakage
Current I/O Pin
Vcc = 5.5V, pin low
(absolute value)
< 0.05
< 0.05
1
1
µA
µA
Input Leakage
Current I/O Pin
Vcc = 5.5V, pin high
(absolute value)
IIH
RRST
Rpu
Reset Pull-up Resistor
I/O Pin Pull-up Resistor
30
20
60
50
kΩ
kΩ
Notes: 1. “Typ.”, typical values at 25°C. Maximum values are characterized values and not test limits in production.
2. “Max.” means the highest value where the pin is guaranteed to be read as low.
3. “Min.” means the lowest value where the pin is guaranteed to be read as high.
4. Although each I/O port can sink more than the test conditions (10mA at VCC= 5V, 5mA at VCC = 3V) under steady state con-
ditions (non-transient), the following must be observed:
The sum of all IOL, for all ports, should not exceed 120mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
5. Although each I/O port can source more than the test conditions (10mA at VCC = 5V, 5mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
The sum of all IOH, for all ports, should not exceed 120mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
6. Values using methods described in “Minimizing Power Consumption” on page 49. Power Reduction is enabled
(PRR = 0xFF) and there is no I/O drive.
7. BOD disabled.
255
9219A–RFID–01/11
23.2 DC Characteristics (Continued)
TA = –40°C to +85°C, VCC = 2.7V to 5.5V (unless otherwise noted)
Symbol Parameter
Power Supply Current(6)
Condition
Min.
Typ.(1)
10
Max.
13
Unit
mA
mA
mA
mA
mA
mA
mA
mA
µA
16MHz, Vcc = 5V
8MHz, Vcc = 5V
5.5
2.8
1.8
3.5
1.8
1
7.0
3.5
2.5
5.0
2.5
1.5
0.8
100
70
Active Mode
(external clock)
8MHz, Vcc = 3V
4MHz, Vcc = 3V
16MHz, Vcc = 5V
8MHz, Vcc = 5V
Power Supply Current(6)
Idle Mode
ICC
8MHz, Vcc = 3V
(external clock)
4MHz, Vcc = 3V
0.5
7
WDT enabled, Vcc = 5V
WDT disabled, Vcc = 5V
WDT enabled, Vcc = 3V
WDT disabled, Vcc = 3V
Power Supply Current(7)
Power-down Mode
0.18
5
µA
70
µA
0.15
45
µA
Analog Comparator
Input Offset Voltage
Vcc = 5V
Vin = Vcc/2
VACIO
IACLK
–10
–50
+10
+40
+50
mV
nA
Analog Comparator
Input Leakage Current
Vcc = 5V
Vin = Vcc/2
Analog Comparator
Propagation Delay Common
Mode Vcc/2
Vcc = 2.7V
Vcc = 5.0V
170
180
ns
ns
tACID
Notes: 1. “Typ.”, typical values at 25°C. Maximum values are characterized values and not test limits in production.
2. “Max.” means the highest value where the pin is guaranteed to be read as low.
3. “Min.” means the lowest value where the pin is guaranteed to be read as high.
4. Although each I/O port can sink more than the test conditions (10mA at VCC= 5V, 5mA at VCC = 3V) under steady state con-
ditions (non-transient), the following must be observed:
The sum of all IOL, for all ports, should not exceed 120mA.
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater
than the listed test condition.
5. Although each I/O port can source more than the test conditions (10mA at VCC = 5V, 5mA at VCC = 3V) under steady state
conditions (non-transient), the following must be observed:
The sum of all IOH, for all ports, should not exceed 120mA.
If IOH exceeds the test condition, VOH may exceed the related specification. Pins are not guaranteed to source current
greater than the listed test condition.
6. Values using methods described in “Minimizing Power Consumption” on page 49. Power Reduction is enabled
(PRR = 0xFF) and there is no I/O drive.
7. BOD disabled.
256
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
23.3 Speed Grades
Figure 23-1. Maximum Frequency vs. VCC, Atmel® AVR®
Frequency
16 MHz
8 MHz
Safe Operating Area
Voltage
2.7V
4.5V
5.5V
23.4 Clock Characteristics
23.4.1
Calibrated Internal RC Oscillator Accuracy
Table 23-1. Calibration and Accuracy of Internal RC Oscillator
Frequency
VCC
Temperature
Accuracy
Factory
Calibration
8.0MHz
3V
25°C
±2%
2.7V
5.5V
–40°C/+125°C
–40°C/+125°C
±10%
±10%
Maximum
Deviation
8.0MHz
23.4.2
External Clock Drive Waveforms
Figure 23-2. External Clock Drive Waveforms
VIH1
VIL1
257
9219A–RFID–01/11
23.4.3
External Clock Drive
Table 23-2. External Clock Drive
VCC = 2.7 - 5.5V
VCC = 4.5 - 5.5V
Symbol
1/tCLCL
tCLCL
Parameter
Oscillator Frequency
Clock Period
High Time
Min.
Max.
Min.
0
Max.
Units
MHz
ns
0
8
16
125
50
62.5
25
tCHCX
tCLCX
tCLCH
tCHCL
ns
Low Time
50
25
ns
Rise Time
1.6
1.6
0.5
0.5
ms
Fall Time
ms
Change in period from one clock
cycle to the next
ΔtCLCL
2
2
%
23.5 RESET Characteristics
Table 23-3. External Reset Characteristics
Symbol
Parameter
Condition
Min
Typ
Max
Units
RESET Pin Threshold
Voltage
VRST
VCC = 5V
VCC = 5V
0.1 VCC
0.9 VCC
V
Minimum pulse width on
RESET Pin
tRST
VBG
tBG
2.5
1.2
70
µs
V
VCC = 2.7V,
TA = 25°C
Bandgap reference voltage
1.0
1.1
40
15
Bandgap reference start-up
time
VCC = 2.7V,
TA = 25°C
µs
µA
Bandgap reference current
consumption
VCC = 2.7V,
TA = 25°C
IBG
Table 23-4. Power On Reset Characteristics
Symbol
Parameter
Min
Typ
1.4
1.3
Max
Units
Power-on Reset Threshold Voltage (rising)
Power-on Reset Threshold Voltage (falling)(1)
V
V
V
POT
1.0
1.6
0.4
VCC Max. start voltage to ensure internal
Power-on Reset signal
V
PORMAX
V
VCC Min. start voltage to ensure internal
Power-on Reset signal
V
PORMIN
–0.1
0.01
V
V/ms
V
V
CCRR
VCC Rise Rate to ensure Power-on Reset
RESET Pin Threshold Voltage
0.9
VCC
V
RST
0.1 VCC
Note:
1. Before rising, the supply has to be between VPORMIN and VPORMAX to ensure a Reset.
258
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
Table 23-5. BODLEVEL Fuse Coding
(1)
BODLEVEL 2:0 Fuses
1 1 1 b
Min. VBOT
Typ. VBOT
Max. VBOT
Units
BOD Disabled
1 1 0 b
1.7
2.5
4.1
1.8
2.7
4.3
2.0
2.9
4.5
1 0 1 b
1 0 0 b
0 1 1 b
V
0 1 0 b
Reserved
0 0 1 b
0 0 0 b
Notes: 1. VBOT may be below nominal minimum operating voltage for some devices. For devices
where this is the case, the device is tested down to VCC = VBOT during the production test.
This guarantees that a Brown-Out Reset will occur before VCC drops to a voltage where cor-
rect operation of the microcontroller is no longer guaranteed. The test is performed using
BODLEVEL = 101 for Low Operating Voltage and BODLEVEL = 100 for High operating
Voltage.
Table 23-6. Brown-out Characteristics
Symbol
VHYST
tBOD
Parameter
Min.
Typ.
80
2
Max.
Units
mV
Brown-out Detector Hysteresis
Min Pulse Width on Brown-out Reset
µs
23.6 Internal Voltage Characteristics
Table 23-7. Internal Voltage Reference Characteristics
Symbol Parameter Condition
Min.
Typ.
Max.
Units
VCC = 4.5
TA = 25°C
VBG
tBG
IBG
Bandgap reference voltage
1.0
1.1
40
10
1.2
70
V
VCC = 4.5
Bandgap reference start-up time
µs
TA = 25°C
VCC = 4.5
TA = 25°C
Bandgap reference current consumption
µA
259
9219A–RFID–01/11
23.7 Front End Reader/Writer
23.7.1
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
All voltages are referred to GND (Pins 1 and 7)
Symbol
Parameter
Pin
Min.
Max.
Unit
VBatt
Operating voltage
20
VS
16
V
VS, VEXT, DVS, Coil 1,
Coil 2
Operating voltage
15, 16, 17, 18, 22
–0.3
8
V
V
VIN
VOUT
Range of input and output 10, 11, 12, 13, 23, 24
voltages
–0.3
–0.3
VS + 0.3
VBatt
9 and 21
IEXT
IOUT
ICoil
Ptot
Tj
Output current
17
10
mA
mA
mA
mW
°C
Output current
9
10
Driver output current
Power dissipation SO16
Junction temperature
Storage temperature
Ambient temperature
15, 16
200
380
150
125
105
Tstg
Tamb
–55
–40
°C
°C
23.7.2
Operating Range
All voltages are referred to GND (Pins 1 and 7)
Symbol
VBatt
Parameter
Pin
20
Value
7 to 16
Unit
V
Operating voltage
Operating voltage
Operating voltage
Carrier frequency
VS
22
4.5 to 6.3
4.5 to 8
V
VEXT, DVS
17, 18
V
100 to 150
kHz
260
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
23.7.3
Electrical Characteristics
All voltages are referred to GND (Pins 1 and 7)
Symbol
Parameters
Test Conditions
out = 5mA
Pin
Min.
Typ.
Max.
Unit
Data output
- Collector emitter
- Saturation voltage
VCEsat
I
9
400
mV
Data output enable
Vil
Vih
- Low-level input voltage
- High-level input voltage
10
11
0.5
V
V
2.4
Data input
Vil
Vih
Rin
SIN
- Clamping level low
- Clamping level high
- Input resistance
- Input sensitivity
2
3.8
220
V
V
kΩ
f = 3 kHz (square wave)
Gain capacitor = 100nF
10
2.4
3.0
mVpp
Driver polarity mode
- Low-level input voltage
- High-level input voltage
Vil
Vih
12
13
V
V
0.2
Carrier frequency enable
- Low-level input voltage
- High-level input voltage
Vil
Vih
V
V
0.8
9
17, 18,
20 and
22
5V application without load
connected to the coil driver
IS
Operating current
Standby current
4.5
30
mA
µA
ISt
12V application
20
70
6.3
VS
VS
dVs/dT
IS
- Supply voltage
- Supply voltage drift
- Output current
4.6
1.8
5.4
4.2
3.5
V
mV/K
mA
22
Driver output voltage
- One-rail operation
- Battery-voltage operation
IL = ±100 mA
VS, VEXT, VBatt, DVS = 5V
VBatt = 12V
VDRV
VDRV
15, 16
17
2.9
3.1
3.6
4.0
4.3
4.7
VPP
VPP
VEXT
- Output voltage
dVEXT/dT - Supply voltage drift
VEXT
4.6
5.4
4.2
6.3
V
mV/K
mA
IEXT
IEXT
- Output current
- Standby output current
IC active
Standby mode
3.5
0.4
mA
Standby input
Vil
Vih
- Low-level input voltage
- High-level input voltage
21
0.8
V
V
3.1
Oscillator
- Carrier frequency
RF resistor = 110kΩ
f0
121
125
129
kHz
kHz
REM 1(1)
Low-pass filter
- Cut-off frequency
fcut
Carrier frequency = 125kHz
7
Amplifier gain
CHP = 100nF
30
261
9219A–RFID–01/11
23.8 Current Source Characteristics
Table 23-8. Current Source Characteristics
Symbol Parameter
Condition
Min.
Typ.
Max. Units
VCC = 2.7V / 5.5V
T = -40°C / +125°C
IISRC
tISRC
Current
94
106
µA
µs
VCC = 4.5
Current Source start-up time
60
TA = 25°C
23.9 ADC Characteristics
Table 23-9. ADC Characteristics, Single Ended Channels (-40°C/+125°C)
Symbol Parameter
Condition
Min
Typ
Max
Units
Resolution
Single Ended Conversion
10
Bits
V
CC = 4V, VRef = 4V,
TUE
INL
Absolute accuracy
2.0
0.6
0.3
-2.5
1.5
3.5
2.0
0.8
2.0
LSB
LSB
LSB
LSB
LSB
ADC clock = 200kHz
VCC = 4V, VRef = 4V,
Integral Non Linearity
Differential Non Linearity
Gain error
ADC clock = 200kHz
VCC = 4V, VRef = 4V,
ADC clock = 200kHz
DNL
VCC = 4V, VRef = 4V,
ADC clock = 200kHz
-6.0
VCC = 4V, VRef = 4V,
ADC clock = 200kHz
Offset error
-3.5
3.5
VREF
Ref voltage
2.56
AVCC
V
kHz
V
Input bandwidth
38.5
2.56
32
VINT
RREF
RAIN
Internal voltage
2.4
2.7
Reference input resistance
Analog input resistance
kΩ
MΩ
100
262
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
Table 23-10. ADC Characteristics, Differential Channels (-40°C/+125°C)
Symbol Parameter
Condition
Min
Typ
Max
Units
Resolution
Differential conversion
8
Gain = 8x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
1.0
1.5
2.0
2.0
0.2
0.4
0.5
1.6
0.3
0.3
0.4
0.6
1.0
1.5
-2.5
-0.5
3.0
3.5
4.5
6.0
1.0
1.5
2.0
5.0
0.8
0.8
0.8
1.6
3.0
4.0
0.0
4.0
Gain = 20x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
TUE
Absolute accuracy
LSB
Gain = 8x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
Gain = 20x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
Gain = 8x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
Gain = 20x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
INL
Integral Non Linearity
Differential Non Linearity
Gain error
LSB
LSB
LSB
Gain = 8x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
Gain = 20x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
Gain = 8x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
Gain = 20x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
DNL
Gain = 8x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
Gain = 20x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
Gain = 8x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
-3.0
-4.0
-5.0
-4.0
Gain = 20x, BIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
Gain = 8x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
Gain = 20x, UNIPOLAR
VREF = 4V, VCC = 5V
ADC clock = 200kHz
263
9219A–RFID–01/11
Table 23-10. ADC Characteristics, Differential Channels (-40°C/+125°C) (Continued)
Symbol Parameter
Condition
Min
Typ
Max
Units
Gain = 8x or 20x, BIPOLAR
VREF = 4V, VCC = 5V
-2.0
0.5
2.0
ADC clock = 200kHz
Offset error
LSB
Gain = 8x or 20x, UNIPOLAR
VREF = 4V, VCC = 5V
-2.0
0.5
2.0
ADC clock = 200kHz
VREF
VDIFF
AVCC
VIN
Reference voltage
2.56
–VREF/Gain
VCC - 0.3
0
AVCC – 0.5
+VREF/Gain
VCC + 0.3
AVcc
V
V
Input differential voltage
Analog supply voltage
Input voltage
V
Differential conversion
Differential conversion
V
ADC conversion output
Input bandwidth
–511
+511
LSB
kHz
V
4
VINT
RREF
RAIN
Internal voltage reference
Reference input resistance
Analog input resistance
2.4
2.56
32
2.7
kΩ
MΩ
100
23.10 Parallel Programming Characteristics
Figure 23-3. Parallel Programming Timing, Including some General Timing Requirements
tXLWL
XTAL1
tXHXL
tDVXH
tXLDX
Data & Contol
(DATA, XA0,
XA1/BS2,
tBVPH
tPLBX
t BVWL
tWLBX
PAGEL/BS1)
tWLWH
tRLRH
WR
tPLWL
RDY/BSY
tWLRH
264
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
Figure 23-4. Parallel Programming Timing, Loading Sequence with Timing Requirements(1)
LOAD ADDRESS
(LOW BYTE)
LOAD DATA
(LOW BYTE)
LOAD DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
t XLXH
XTAL1
AGEL/BS1
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
DATA (High Byte)
ADDR1 (Low Byte)
XA0
XA1/BS2
Note:
1. The timing requirements shown in Figure 23-3 (i.e., tDVXH, tXHXL, and tXLDX) also apply to
loading operation.
Figure 23-5. Parallel Programming Timing, Reading Sequence (within the Same Page) with
Timing Requirements(Note:)
LOAD ADDRESS
(LOW BYTE)
READ DATA
(LOW BYTE)
READ DATA
(HIGH BYTE)
LOAD ADDRESS
(LOW BYTE)
tXLOL
XTAL1
tBVDV
AGEL/BS1
tOLDV
OE
tOHDZ
ADDR1 (Low Byte)
DATA (High Byte)
DATA
ADDR0 (Low Byte)
DATA (Low Byte)
XA0
XA1/BS2
Note:
The timing requirements shown in Figure 23-3 (i.e., tDVXH, tXHXL, and tXLDX) also apply to read-
ing operation.
265
9219A–RFID–01/11
Table 23-11. Parallel Programming Characteristics, VCC = 5V ± 10%
Symbol
VPP
Parameter
Min
Typ
Max
12.5
250
Units
V
Programming Enable Voltage
Programming Enable Current
Data and Control Valid before XTAL1 High
XTAL1 Low to XTAL1 High
XTAL1 Pulse Width High
Data and Control Hold after XTAL1 Low
XTAL1 Low to WR Low
11.5
IPP
µA
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
µs
ms
ms
ns
ns
ns
ns
tDVXH
tXLXH
tXHXL
tXLDX
tXLWL
tBVPH
tPLBX
tWLBX
tPLWL
tBVWL
tWLWH
tWLRL
tWLRH
tWLRH_CE
tXLOL
tBVDV
tOLDV
tOHDZ
67
200
150
67
0
BS1 Valid before PAGEL High
BS1 Hold after PAGEL Low
BS2/1 Hold after WR Low
PAGEL Low to WR Low
67
67
67
67
67
150
0
BS1 Valid to WR Low
WR Pulse Width Low
WR Low to RDY/BSY Low
WR Low to RDY/BSY High(1)
WR Low to RDY/BSY High for Chip Erase(2)
XTAL1 Low to OE Low
1
4.5
9
3.7
7.5
0
BS1 Valid to DATA valid
0
250
250
250
OE Low to DATA Valid
OE High to DATA Tri-stated
Notes: 1. tWLRH is valid for the Write Flash, Write EEPROM, Write Fuse bits and Write Lock bits
commands.
2. tWLRH_CE is valid for the Chip Erase command.
266
Atmel ATA5505 [Preliminary]
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Atmel ATA5505 [Preliminary]
23.11 SPI Timing Characteristics
See Figure 23-6 and Figure 23-7 for details.
Table 23-12. SPI Timing Parameters
Description
SCK period
SCK high/low
Rise/Fall time
Setup
Mode
Min.
Typ.
Max.
1
2
Master
Master
Master
Master
Master
Master
Master
Master
Slave
See Table 13-4
50% duty cycle
3
3.6
10
4
5
Hold
10
ns
6
Out to SCK
SCK to out
SCK to out high
SS low to out
SCK period
SCK high/low (1)
Rise/Fall time
Setup
0.5 • tsck
10
7
8
10
9
15
10
11
12
13
14
15
16
17
18
Slave
4 • tck
2 • tck
Slave
Slave
1.6
µs
ns
Slave
10
tck
Hold
Slave
SCK to out
SCK to SS high
SS high to tri-state
SS low to SCK
Slave
15
10
Slave
20
Slave
Slave
2 • tck
Note:
In SPI Programming mode the minimum SCK high/low period is:
- 2 tCLCL for fCK < 12MHz
- 3 tCLCL for fCK >12MHz
Figure 23-6. SPI Interface Timing Requirements (Master Mode)
SS
6
1
SCK
(CPOL = 0)
2
2
SCK
(CPOL = 1)
4
5
3
MISO
(Data Input)
MSB
...
LSB
7
8
MOSI
(Data Output)
MSB
...
LSB
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9219A–RFID–01/11
Figure 23-7. SPI Interface Timing Requirements (Slave Mode)
18
SS
10
16
9
SCK
(CPOL = 0)
11
11
SCK
(CPOL = 1)
13
14
12
MOSI
(Data Input)
MSB
...
LSB
15
17
MISO
(Data Output)
MSB
...
LSB
X
268
Atmel ATA5505 [Preliminary]
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Atmel ATA5505 [Preliminary]
24. Decoupling Capacitors
The operating frequency (i.e. system clock) of the processor determines in 95% of cases the
value needed for microcontroller decoupling capacitors.
The hypotheses used as first evaluation for decoupling capacitors are:
• The operating frequency (fop) supplies itself the maximum peak levels of noise. The main
peaks are located at fop and 2 • fop.
• An SMC capacitor connected to 2 micro-vias on a PCB has the following characteristics:
– 1.5 nH from the connection of the capacitor to the PCB,
– 1.5 nH from the capacitor intrinsic inductance.
Figure 24-1. Capacitor description
1.5 nH
0.75 nH
0.75 nH
Capacitor
PCB
According to the operating frequency of the product, the decoupling capacitances are chosen
considering the frequencies to filter, fop and 2 • fop.
The relation between frequencies to cut and decoupling characteristics are defined by:
1
1
and
fop = ----------------------
2 • fop = ----------------------
2Π LC1
2Π LC2
where:
– L: the inductance equivalent to the global inductance on the VCC/Gnd lines.
– C1 & C2: decoupling capacitors (C1 = 4 • C2).
Then, in normalized value range, the decoupling capacitors become:
Table 24-1. Decoupling Capacitors vs. Frequency
fop , operating frequency
C1
C2
16MHz
12MHz
10MHz
8MHz
33nF
56nF
82nF
120nF
220nF
560nF
10nF
15nF
22nF
33nF
56nF
120nF
6MHz
4MHz
These decoupling capacitors must to be implemented as close as possible to each pair of
power supply pins:
– 16-17 for logic sub-system,
– 5-6 for analogical sub-system.
Nevertheless, a bulk capacitor of 10-47µF is also needed on the power distribution network of
the PCB, near the power source.
For further information, please refer to Application Notes Atmel® AVR040 “EMC Design Con-
siderations“ and Atmel AVR042 “Hardware Design Considerations“ on the Atmel web site.
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25. Typical Atmel AVR Characteristics
The data contained in this section is largely based on simulations and characterization of sim-
ilar devices in the same process and design methods. It also does include the base station
block. Thus, the data should be treated as indications of how the part will behave.
The following charts show typical behavior. These figures are not tested during manufacturing.
All current consumption measurements are performed with all I/O pins configured as inputs
and with internal pull-ups enabled. A sine wave generator with rail-to-rail output is used as
clock source.
The power consumption in Power-down mode is independent of clock selection.
The current consumption is a function of several factors such as: operating voltage, operating
frequency, loading of I/O pins, switching rate of I/O pins, code executed and ambient tempera-
ture. The dominating factors are operating voltage and frequency.
The current drawn from capacitive loaded pins may be estimated (for one pin) as CL*VCC*f
where CL = load capacitance, VCC = operating voltage and f = average switching frequency of
I/O pin.
The parts are characterized at frequencies higher than test limits. Parts are not guaranteed to
function properly at frequencies higher than the ordering code indicates.
The difference between current consumption in Power-down mode with Watchdog Timer
enabled and Power-down mode with Watchdog Timer disabled represents the differential cur-
rent drawn by the Watchdog Timer.
25.1 Active Supply Current
Figure 25-1. Active Supply Current versus Low Frequency (0.1 - 1.0MHz)
ACTIVE SUPPLY CURRENT vs. LOW FREQUENCY
PRR=0x FF / A TD ON
1.4
1.2
1
6
5.5
5
4.5
4
0.8
0.6
0.4
0.2
0
3.6
3.3
3
2.7
2.4
2.1
2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (MHz)
1.8
1.6
270
Atmel ATA5505 [Preliminary]
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Atmel ATA5505 [Preliminary]
Figure 25-2. Active Supply Current vs. Frequency (≥ 1MHz)
Figure 25-3. Active Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR 8MHz (No ATD influence)
9
8
7
6
5
4
3
2
1
0
150
125
85
25
-40
1.5
2
2.5
3
3.5
4
4.5
5
5.5
VCC (V)
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Figure 25-4. Active Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
ACTIVE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR 128 KHz / ATD ON
0.2
0.18
0.16
0.14
0.12
0.1
150
125
85
0.08
0.06
0.04
0.02
0
25
-40
1.5
2
2.5
3
3.5
4
4.5
5
5.5
V
CC (V)
25.2 Idle Supply Current
Figure 25-5. Idle Supply Current vs. Frequency (≥ 1MHz)
IDLE SUPPLY CURRENT vs. FREQUENCY
NO POWER REDUCTION ENABLED
10
9
8
7
6
5
4
3
2
1
0
6
5.5
5
4.5
4
3.6
3.3
3
2.7
2.4
0
2
4
6
8
10
12
14
16
18
20
Frequency (MHz)
272
Atmel ATA5505 [Preliminary]
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Atmel ATA5505 [Preliminary]
Figure 25-6. Idle Supply Current vs. VCC (Internal RC Oscillator, 8MHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR 8MHz
3
2.5
2
150
125
85
1.5
1
25
-40
0.5
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
V
CC (V)
Figure 25-7. Idle Supply Current vs. VCC (Internal RC Oscillator, 128kHz)
IDLE SUPPLY CURRENT vs. VCC
INTERNAL RC OSCILLATOR 125 KHz
0.08
0.07
0.06
0.05
0.04
0.03
0.02
0.01
0
150
125
85
25
-40
1.5
2
2.5
3
3.5
4
4.5
5
5.5
V
CC (V)
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25.3 Supply Current of I/O modules
The table below can be used to calculate the additional current consumption for the different
I/O modules Idle mode. The enabling or disabling of the I/O modules are controlled by the
Power Reduction Register. See Section 5.9.3 “PRR – Power Reduction Register” on page 51
for details.
Table 25-1. Additional Current Consumption for the different I/O modules (absolute values)
VCC = 5.0V
VCC = 5.0V
VCC = 3.0V
VCC = 3.0V
Module
LIN/UART
SPI
Freq. = 16MHz
Freq. = 8MHz
Freq. = 8MHz
Freq. = 4MHz
Units
mA
mA
mA
mA
mA
mA
0.77
0.37
0.14
0.13
0.20
0.05
0.22
0.20
0.08
0.08
0.10
0.04
0.10
0.10
0.04
0.04
0.05
0.02
0.05
0.31
TIMER-1
TIMER-0
USI
0.28
0.41
0.14
ADC
0.48
25.4 Power-down Supply Current
Figure 25-8. Power-down Supply Current vs. VCC (Watchdog Timer Disabled)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER DISABLED
30
25
20
15
10
5
150
125
85
25
-40
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
V
CC (V)
274
Atmel ATA5505 [Preliminary]
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Atmel ATA5505 [Preliminary]
Figure 25-9. Power-down Supply Current vs. VCC (Watchdog Timer Enabled)
POWER-DOWN SUPPLY CURRENT vs. VCC
WATCHDOG TIMER ENABLED
40
35
30
25
20
15
10
5
150
125
85
25
-40
0
1.5
2
2.5
3
3.5
4
4.5
5
5.5
V
CC (V)
25.5 Pin Pull-up
Figure 25-10. I/O Pin pull-up Resistor Current vs. Input Voltage (VCC = 2.7V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 2.7 V
90
80
70
60
50
40
30
20
10
0
150
125
85
25
-40
0
0.5
1
1.5
2
2.5
3
-10
V
OP (V)
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Figure 25-11. I/O Pin pull-up Resistor Current vs. Input Voltage (VCC = 5V)
I/O PIN PULL-UP RESISTOR CURRENT vs. INPUT VOLTAGE
Vcc = 5.0 V
160
140
120
100
80
150
125
85
60
25
40
-40
20
0
0
1
2
3
4
5
6
-20
VOP (V)
Figure 25-12. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 2.7V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 2.7 V
70
60
50
40
30
20
10
0
150
125
85
25
-40
0
0.5
1
1.5
2
2.5
3
-10
VRESET (V)
276
Atmel ATA5505 [Preliminary]
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Atmel ATA5505 [Preliminary]
Figure 25-13. Reset Pull-up Resistor Current vs. Reset Pin Voltage (VCC = 5V)
RESET PULL-UP RESISTOR CURRENT vs. RESET PIN VOLTAGE
Vcc = 5.0 V
120
100
80
150
125
85
60
40
25
-40
20
0
0
1
2
3
4
5
6
-20
VRESET (V)
25.6 Pin Driver Strength
Figure 25-14. I/O Pin Output Voltage vs. Sink Current (VCC = 3V)
I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
Vcc = 3.0 V
2
1.8
1.6
1.4
1.2
1
150
125
85
25
0.8
0.6
0.4
0.2
0
-40
0
2
4
6
8
10
12
14
16
18
IOL (mA)
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Figure 25-15. I/O Pin Output Voltage vs. Sink Current (VCC = 5V)
I/O PIN OUTPUT VOLTAGE vs. SINK CURRENT
Vcc = 5.0V
1.2
1
150
125
85
0.8
0.6
0.4
0.2
0
25
-40
0
5
10
15
20
25
IOL (mA)
Figure 25-16. I/O Pin Output Voltage vs. Source Current (VCC = 3V)
I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
Vcc = 3.0 V
3
2.5
2
150
125
85
1.5
1
25
-40
0.5
0
0
2
4
6
8
10
12
14
16
18
20
IOH (mA)
278
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
Figure 25-17. I/O Pin Output Voltage vs. Source Current (VCC = 5V)
I/O PIN OUTPUT VOLTAGE vs. SOURCE CURRENT
Vcc = 5.0 V
5.1
4.9
4.7
4.5
4.3
4.1
3.9
3.7
150
125
85
25
-40
0
2
4
6
8
10
12
14
16
18
20
IOH (mA)
25.7 Internal Oscillator Speed
Figure 25-18. Calibrated 8.0MHz RC Oscillator Frequency vs. VCC
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9219A–RFID–01/11
Figure 25-19. Calibrated 8.0MHz RC Oscillator Frequency vs. OSCCAL Value
25.8 Current Consumption in Reset
Figure 25-20. Reset Supply Current vs. VCC, Frequencies 0.1 - 1.0MHz
(Excluding CurrentThrough the Reset Pull-up)
RESET SUPPLY CURRENT vs. VCC
EXCLUDING CURRENT THROUGH THE RESET PULLUP
0.3
0.25
0.2
6
5.5
5
4.5
4
0.15
0.1
3.6
3.3
3
0.05
0
2.7
2.4
2.1
2
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
Frequency (MHz)
1.8
1.6
280
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
Figure 25-21. Reset Supply Current vs. VCC, Frequencies ≥ 1MHz
(Excluding Current Through the Reset Pull-up)
RESET SUPPLY CURRENT vs. VCC
EXCLUDING CURRENT THROUGH THE RESET PULLUP
4.5
4
6
3.5
3
5.5
5
4.5
4
2.5
2
3.6
3.3
3
1.5
1
2.7
2.4
2.1
2
0.5
0
0
2
4
6
8
10
12
14
16
18
20
Frequency (MHz)
1.8
1.6
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26. Register Summary
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xFF)
(0xFE)
(0xFD)
(0xFC)
(0xFB)
(0xFA)
(0xF9)
(0xF8)
(0xF7)
(0xF6)
(0xF5)
(0xF4)
(0xF3)
(0xF2)
(0xF1)
(0xF0)
(0xEF)
(0xEE)
(0xED)
(0xEC)
(0xEB)
(0xEA)
(0xE9)
(0xE8)
(0xE7)
(0xE6)
(0xE5)
(0xE4)
(0xE3)
(0xE2)
(0xE1)
(0xE0)
(0xDF)
(0xDE)
(0xDD)
(0xDC)
(0xDB)
(0xDA)
(0xD9)
(0xD8)
(0xD7)
(0xD6)
(0xD5)
(0xD4)
(0xD3)
(0xD2)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
LINDAT
LDATA7
LDATA6
LDATA5
LDATA4
LDATA3
LDATA2
LDATA1
LDATA0
page 189
Notes: 1. Address bits exceeding EEAMSB (Table 22-8 on page 239) are don’t care.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
3. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
4. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other Atmel® AVR®s, the CBI
and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status
flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
5. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel AVR is a com-
plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN
and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used
282
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
26. Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xD1)
(0xD0)
(0xCF)
(0xCE)
(0xCD)
(0xCC)
(0xCB)
(0xCA)
(0xC9)
(0xC8)
(0xC7)
(0xC6)
(0xC5)
(0xC4)
(0xC3)
(0xC2)
(0xC1)
(0xC0)
(0xBF)
(0xBE)
(0xBD)
(0xBC)
(0xBB)
(0xBA)
(0xB9)
(0xB8)
(0xB7)
(0xB6)
(0xB5)
(0xB4)
(0xB3)
(0xB2)
(0xB1)
(0xB0)
(0xAF)
(0xAE)
(0xAD)
(0xAC)
(0xAB)
(0xAA)
(0xA9)
(0xA8)
(0xA7)
(0xA6)
(0xA5)
(0xA4)
(0xA3)
(0xA2)
LINSEL
LINIDR
–
–
LP0
–
LID5 / LDL1
LTXDL1
–
–
LID4 / LDL0
LTXDL0
–
/LAINC
LID3
LINDX2
LID2
LINDX1
LID1
LINDX0
LID0
page 189
page 189
page 188
page 188
page 188
page 187
page 186
page 186
page 185
page 184
LP1
LINDLR
LTXDL3
–
LTXDL2
–
LRXDL3
LDIV11
LDIV3
LRXDL2
LDIV10
LDIV2
LRXDL1
LDIV9
LRXDL0
LDIV8
LINBRRH
LINBRRL
LINBTR
LDIV7
LDISR
LABORT
–
LDIV6
–
LDIV5
LBT5
LDIV4
LBT4
LDIV1
LDIV0
LBT3
LBT2
LBT1
LBT0
LINERR
LTOERR
–
LOVERR
–
LFERR
–
LSERR
LENERR
LERR
LPERR
LENIDOK
LIDOK
LCMD2
LCERR
LENTXOK
LTXOK
LCMD1
LBERR
LENRXOK
LRXOK
LCMD0
LINENIR
LINSIR
LIDST2
LSWRES
LIDST1
LIN13
LIDST0
LCONF1
LBUSY
LCONF0
LINCR
LENA
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
USIPP
USIPOS
USIB0
page 164
page 160
page 159
page 160
page 161
USIBR
USIB7
USID7
USISIF
USISIE
USIB6
USID6
USIOIF
USIOIE
USIB5
USID5
USIB4
USID4
USIB3
USID3
USIB2
USID2
USIB1
USID1
USIDR
USID0
USISR
USIPF
USIDC
USIWM0
USICNT3
USICS1
USICNT2
USICS0
USICNT1
USICLK
USICNT0
USITC
USICR
USIWM1
Reserved
ASSR
EXCLK
TCN0UB
–
AS0
OCR0AUB
–
TCR0AUB
TCR0BUB
page 106
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Notes: 1. Address bits exceeding EEAMSB (Table 22-8 on page 239) are don’t care.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
3. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
4. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other Atmel® AVR®s, the CBI
and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status
flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
5. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel AVR is a com-
plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN
and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used
283
9219A–RFID–01/11
26. Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0xA1)
(0xA0)
(0x9F)
(0x9E)
(0x9D)
(0x9C)
(0x9B)
(0x9A)
(0x99)
(0x98)
(0x97)
(0x96)
(0x95)
(0x94)
(0x93)
(0x92)
(0x91)
(0x90)
(0x8F)
(0x8E)
(0x8D)
(0x8C)
(0x8B)
(0x8A)
(0x89)
(0x88)
(0x87)
(0x86)
(0x85)
(0x84)
(0x83)
(0x82)
(0x81)
(0x80)
(0x7F)
(0x7E)
(0x7D)
(0x7C)
(0x7B)
(0x7A)
(0x79)
(0x78)
(0x77)
(0x76)
(0x75)
(0x74)
(0x73)
(0x72)
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
OCR1BH
OCR1BL
OCR1AH
OCR1AL
ICR1H
OCR1B15
OCR1B7
OCR1A15
OCR1A7
ICR115
ICR17
OCR1B14
OCR1B6
OCR1A14
OCR1A6
ICR114
OCR1B13
OCR1B5
OCR1A13
OCR1A5
ICR113
ICR15
OCR1B12
OCR1B4
OCR1A12
OCR1A4
ICR112
ICR14
OCR1B11
OCR1B3
OCR1A11
OCR1A3
ICR111
ICR13
TCNT111
TCNT13
OC1AX
–
OCR1B10
OCR1B2
OCR1A10
OCR1A2
ICR110
ICR12
TCNT110
TCNT12
OC1AW
–
OCR1B9
OCR1B1
OCR1A9
OCR1A1
ICR19
ICR11
TCNT19
TCNT11
OC1AV
–
OCR1B8
OCR1B0
OCR1A8
OCR1A0
ICR18
ICR10
TCNT18
TCNT10
OC1AU
–
page 140
page 140
page 140
page 140
page 141
ICR1L
ICR16
page 141
TCNT1H
TCNT1L
TCCR1D
TCCR1C
TCCR1B
TCCR1A
DIDR1
TCNT115
TCNT17
OC1BX
FOC1A
ICNC1
TCNT114
TCNT16
OC1BW
FOC1B
TCNT113
TCNT15
OC1BV
–
TCNT112
TCNT14
OC1BU
–
page 140
page 140
page 139
page 139
ICES1
–
WGM13
COM1B0
ADC8D
ADC4D
WGM12
–
CS12
CS11
CS10
page 138
COM1A1
–
COM1A0
ADC10D
COM1B1
ADC9D
ADC5D
–
WGM11
–
WGM10
–
page 135
–
–
page 221
DIDR0
ADC7D/AIN1D ADC6D/AIN0D
ADC3D
ADC2D
ADC1D
ADC0D
page 220, page 224
Reserved
ADMUX
REFS1
BIN
REFS0
ACME
ADLAR
ACIR1
ADATE
- / ADC7
ADC5 / -
–
MUX4
ACIR0
ADIF
MUX3
–
MUX2
ADTS2
MUX1
ADTS1
MUX0
ADTS0
page 216
page 220, page 222
page 218
ADCSRB
ADCSRA
ADCH
ADEN
- / ADC9
ADSC
ADIE
- / ADC5
ADC3 / -
–
ADPS2
ADPS1
ADPS0
- / ADC8
- / ADC6
ADC4 / -
–
- / ADC4
ADC2 / -
AREFEN
ADC9 / ADC3
ADC1 / -
XREFEN
ADC8 / ADC2
ADC0 /
page 219
ADCL
ADC7 / ADC1 ADC6 / ADC0
page 219
AMISCR
Reserved
Reserved
Reserved
Reserved
Reserved
–
–
ISRCEN
page 201, page 201
Notes: 1. Address bits exceeding EEAMSB (Table 22-8 on page 239) are don’t care.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
3. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
4. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other Atmel® AVR®s, the CBI
and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status
flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
5. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel AVR is a com-
plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN
and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used
284
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
26. Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
(0x71)
(0x70)
Reserved
Reserved
TIMSK1
TIMSK0
Reserved
PCMSK1
PCMSK0
Reserved
EICRA
(0x6F)
–
–
–
–
ICIE1
–
–
–
–
–
OCIE1B
–
OCIE1A
OCIE0A
TOIE1
TOIE0
page 141
page 108
(0x6E)
(0x6D)
(0x6C)
PCINT15
PCINT7
PCINT14
PCINT6
PCINT13
PCINT5
PCINT12
PCINT4
PCINT11
PCINT3
PCINT10
PCINT2
PCINT9
PCINT1
PCINT8
PCINT0
page 68
page 69
(0x6B)
(0x6A)
(0x69)
–
–
–
–
–
–
–
–
ISC11
–
ISC10
–
ISC01
PCIE1
ISC00
PCIE0
page 66
page 67
(0x68)
PCICR
(0x67)
Reserved
OSCCAL
Reserved
PRR
(0x66)
CAL7
CAL6
CAL5
CAL4
CAL3
CAL2
CAL1
CAL0
page 41
(0x65)
(0x64)
–
–
–
COUT
–
PRLIN
CSUT1
–
PRSPI
CSUT0
CLKRDY
–
PRTIM1
CSEL3
CLKC3
CLKPS3
WDE
PRTIM0
CSEL2
CLKC2
CLKPS2
WDP2
N
PRUSI
CSEL1
CLKC1
CLKPS1
WDP1
Z
PRADC
CSEL0
CLKC0
CLKPS0
WDP0
C
page 51
page 44
page 42
page 42
page 61
page 13
page 15
page 15
(0x63)
CLKSELR
CLKCSR
CLKPR
(0x62)
CLKCCE
CLKPCE
WDIF
I
(0x61)
–
–
(0x60)
WDTCR
SREG
WDIE
T
WDP3
H
WDCE
S
0x3F (0x5F)
0x3E (0x5E)
0x3D (0x5D)
0x3C (0x5C)
0x3B (0x5B)
0x3A (0x5A)
0x39 (0x59)
0x38 (0x58)
0x37 (0x57)
0x36 (0x56)
0x35 (0x55)
0x34 (0x54)
0x33 (0x53)
0x32 (0x52)
0x31 (0x51)
0x30 (0x50)
0x2F (0x4F)
0x2E (0x4E)
0x2D (0x4D)
0x2C (0x4C)
0x2B (0x4B)
0x2A (0x4A)
0x29 (0x49)
0x28 (0x48)
0x27 (0x47)
0x26 (0x46)
0x25 (0x45)
0x24 (0x44)
0x23 (0x43)
0x22 (0x42)
V
SPH
SP15
SP7
SP14
SP6
SP13
SP5
SP12
SP4
SP11
SP3
SP10
SP9
SP8
SPL
SP2
SP1
SP0
Reserved
Reserved
Reserved
Reserved
Reserved
SPMCSR
Reserved
MCUCR
MCUSR
SMCR
–
–
–
–
–
RWWSB
SIGRD
CTPB
RFLB
PGWRT
–
PGERS
–
SPMEN
page 230
–
–
–
PUD
–
–
–
–
BODS
BODSE
–
WDRF
–
–
–
page 50, page 78
page 56
–
–
–
–
BORF
SM1
EXTRF
SM0
PORF
SE
–
page 50
Reserved
DWDR
DWDR7
ACD
DWDR6
ACIRS
DWDR5
ACO
DWDR4
ACI
DWDR3
ACIE
DWDR2
ACIC
DWDR1
ACIS1
DWDR0
ACIS0
page 227
page 223
ACSR
Reserved
SPDR
SPD7
SPIF
SPD6
WCOL
SPD5
–
SPD4
–
SPD3
–
SPD2
–
SPD1
–
SPD0
SPI2X
page 150
page 150
page 148
page 27
page 27
SPSR
SPCR
SPIE
SPE
DORD
GPIOR25
GPIOR15
MSTR
GPIOR24
GPIOR14
CPOL
CPHA
SPR1
SPR0
GPIOR2
GPIOR1
Reserved
OCR0A
TCNT0
GPIOR27
GPIOR17
GPIOR26
GPIOR16
GPIOR23
GPIOR13
GPIOR22
GPIOR12
GPIOR21
GPIOR11
GPIOR20
GPIOR10
OCR0A7
TCNT07
FOC0A
OCR0A6
TCNT06
–
OCR0A5
OCR0A4
OCR0A3
OCR0A2
TCNT02
CS02
–
OCR0A1
TCNT01
CS01
OCR0A0
TCNT00
CS00
page 106
page 106
page 105
page 103
TCNT05
TCNT04
TCNT03
TCCR0B
TCCR0A
Reserved
GTCCR
EEARH(1)
–
–
–
–
–
–
COM0A1
COM0A0
WGM01
WGM00
TSM
–
–
–
–
–
–
–
–
–
–
–
PSR0
–
PSR1
page 109, page 112
page 25
EEAR8
Notes: 1. Address bits exceeding EEAMSB (Table 22-8 on page 239) are don’t care.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
3. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
4. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other Atmel® AVR®s, the CBI
and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status
flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
5. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel AVR is a com-
plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN
and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used
285
9219A–RFID–01/11
26. Register Summary (Continued)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Page
0x21 (0x41)
0x20 (0x40)
0x1F (0x3F)
0x1E (0x3E)
0x1D (0x3D)
0x1C (0x3C)
0x1B (0x3B)
0x1A (0x3A)
0x19 (0x39)
EEARL
EEDR
EEAR7
EEAR6
EEAR5
EEAR4
EEAR3
EEAR2
EEAR1
EEDR1
EEPE
EEAR0
EEDR0
EERE
page 25
page 26
page 26
page 27
page 66
page 67
page 68
EEDR7
EEDR6
EEDR5
EEDR4
EEDR3
EEDR2
EECR
–
–
EEPM1
EEPM0
EERIE
EEMPE
GPIOR0
EIMSK
GPIOR07
GPIOR06
GPIOR05
GPIOR04
GPIOR03
GPIOR02
GPIOR01
INT1
GPIOR00
INT0
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
–
EIFR
INTF1
INTF0
PCIFR
PCIF1
PCIF0
Reserved
Reserved
Reserved
Reserved
TIFR1
0x18 (0x38)
0x17 (0x37)
0x16 (0x36)
0x15 (0x35)
0x14 (0x34)
0x13 (0x33)
0x12 (0x32)
0x11 (0x31)
0x10 (0x30)
0x0F (0x2F)
0x0E (0x2E)
0x0D (0x2D)
0x0C (0x2C)
0x0B (0x2B)
0x0A (0x2A)
0x09 (0x29)
0x08 (0x28)
0x07 (0x27)
0x06 (0x26)
0x05 (0x25)
0x04 (0x24)
0x03 (0x23)
0x02 (0x22)
0x01 (0x21)
0x00 (0x20)
–
–
–
–
ICF1
–
–
–
–
–
OCF1B
–
OCF1A
OCF0A
TOV1
TOV0
page 142
page 108
TIFR0
Reserved
Reserved
PORTCR
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
PORTB
DDRB
–
–
BBMB
BBMA
–
–
PUDB
PUDA
page 78
PORTB7
DDB7
PORTB6
DDB6
PORTB5
DDB5
PORTB4
DDB4
PORTB3
DDB3
PORTB2
DDB2
PORTB1
DDB1
PORTB0
DDB0
page 89
page 89
page 89
page 89
page 89
page 89
PINB
PINB7
PINB6
PINB5
PINB4
PINB3
PINB2
PINB1
PINB0
PORTA
DDRA
PORTA7
DDA7
PORTA6
DDA6
PORTA5
DDA5
PORTA4
DDA4
PORTA3
DDA3
PORTA2
DDA2
PORTA1
DDA1
PORTA0
DDA0
PINA
PINA7
PINA6
PINA5
PINA4
PINA3
PINA2
PINA1
PINA0
Notes: 1. Address bits exceeding EEAMSB (Table 22-8 on page 239) are don’t care.
2. For compatibility with future devices, reserved bits should be written to zero if accessed. Reserved I/O memory addresses
should never be written.
3. I/O Registers within the address range 0x00 - 0x1F are directly bit-accessible using the SBI and CBI instructions. In these
registers, the value of single bits can be checked by using the SBIS and SBIC instructions.
4. Some of the status flags are cleared by writing a logical one to them. Note that, unlike most other Atmel® AVR®s, the CBI
and SBI instructions will only operate on the specified bit, and can therefore be used on registers containing such status
flags. The CBI and SBI instructions work with registers 0x00 to 0x1F only.
5. When using the I/O specific commands IN and OUT, the I/O addresses 0x00 - 0x3F must be used. When addressing I/O
Registers as data space using LD and ST instructions, 0x20 must be added to these addresses. The Atmel AVR is a com-
plex microcontroller with more peripheral units than can be supported within the 64 location reserved in Opcode for the IN
and OUT instructions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and LD/LDS/LDD
instructions can be used
286
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
27. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
ARITHMETIC AND LOGIC INSTRUCTIONS
Add two Registers
ADD
ADC
ADIW
SUB
SUBI
SBC
SBCI
SBIW
AND
ANDI
OR
Rd, Rr
Rd, Rr
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rdl,K
Rd, Rr
Rd, K
Rd, Rr
Rd, K
Rd, Rr
Rd
Rd ←Rd + Rr
Rd ←Rd + Rr + C
Rdh:Rdl ←Rdh:Rdl + K
Rd ←Rd - Rr
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,H
Z,C,N,V,S
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,C,N,V
Z,C,N,V,H
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
Z,N,V
None
1
1
2
1
1
1
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Add with Carry two Registers
Add Immediate to Word
Subtract two Registers
Subtract Constant from Register
Subtract with Carry two Registers
Subtract with Carry Constant from Reg.
Subtract Immediate from Word
Logical AND Registers
Logical AND Register and Constant
Logical OR Registers
Rd ←Rd - K
Rd ←Rd - Rr - C
Rd ←Rd - K - C
Rdh:Rdl ←Rdh:Rdl - K
Rd ←Rd • Rr
Rd ←Rd • K
Rd ←Rd v Rr
Rd ←Rd v K
Rd ←Rd Rr
Rd ←0xFF −Rd
Rd ←0x00 −Rd
Rd ←Rd v K
ORI
Logical OR Register and Constant
Exclusive OR Registers
One’s Complement
EOR
COM
NEG
SBR
CBR
INC
DEC
TST
CLR
SER
Rd
Two’s Complement
Set Bit(s) in Register
Clear Bit(s) in Register
Increment
Decrement
Test for Zero or Minus
Clear Register
Rd,K
Rd,K
Rd
Rd
Rd
Rd ←Rd • (0xFF - K)
Rd ←Rd + 1
Rd ←Rd −1
Rd ←Rd • Rd
Rd ←Rd Rd
Rd ←0xFF
Rd
Rd
Set Register
BRANCH INSTRUCTIONS
Relative Jump
Indirect Jump to (Z)
Direct Jump
Relative Subroutine Call
Indirect Call to (Z)
RJMP
IJMP
JMP
RCALL
ICALL
CALL
RET
k
PC ←PC + k + 1
PC ←Z
PC ←k
PC ←PC + k + 1
PC ←Z
PC ←k
PC ←STACK
PC ←STACK
None
None
None
None
None
None
None
I
2
2
3
3
3
4
4
4
k
k
k
Direct Subroutine Call
Subroutine Return
RETI
Interrupt Return
CPSE
CP
CPC
Rd,Rr
Rd,Rr
Rd,Rr
Rd,K
Rr, b
Rr, b
P, b
P, b
s, k
s, k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
k
Compare, Skip if Equal
Compare
Compare with Carry
if (Rd = Rr) PC ←PC + 2 or 3
Rd −Rr
None
Z, N,V,C,H
Z, N,V,C,H
Z, N,V,C,H
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1/2/3
1
1
Rd −Rr −C
Rd −K
CPI
Compare Register with Immediate
Skip if Bit in Register Cleared
Skip if Bit in Register is Set
Skip if Bit in I/O Register Cleared
Skip if Bit in I/O Register is Set
Branch if Status Flag Set
Branch if Status Flag Cleared
Branch if Equal
1
SBRC
SBRS
SBIC
SBIS
if (Rr(b)=0) PC ←PC + 2 or 3
if (Rr(b)=1) PC ←PC + 2 or 3
if (P(b)=0) PC ←PC + 2 or 3
if (P(b)=1) PC ←PC + 2 or 3
if (SREG(s) = 1) then PC←PC+k + 1
if (SREG(s) = 0) then PC←PC+k + 1
if (Z = 1) then PC ←PC + k + 1
if (Z = 0) then PC ←PC + k + 1
if (C = 1) then PC ←PC + k + 1
if (C = 0) then PC ←PC + k + 1
if (C = 0) then PC ←PC + k + 1
if (C = 1) then PC ←PC + k + 1
if (N = 1) then PC ←PC + k + 1
if (N = 0) then PC ←PC + k + 1
if (N V= 0) then PC ←PC + k + 1
if (N V= 1) then PC ←PC + k + 1
if (H = 1) then PC ←PC + k + 1
if (H = 0) then PC ←PC + k + 1
if (T = 1) then PC ←PC + k + 1
if (T = 0) then PC ←PC + k + 1
if (V = 1) then PC ←PC + k + 1
if (V = 0) then PC ←PC + k + 1
if ( I = 1) then PC ←PC + k + 1
if ( I = 0) then PC ←PC + k + 1
1/2/3
1/2/3
1/2/3
1/2/3
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
1/2
BRBS
BRBC
BREQ
BRNE
BRCS
BRCC
BRSH
BRLO
BRMI
BRPL
BRGE
BRLT
BRHS
BRHC
BRTS
BRTC
BRVS
BRVC
BRIE
BRID
Branch if Not Equal
Branch if Carry Set
Branch if Carry Cleared
Branch if Same or Higher
Branch if Lower
Branch if Minus
Branch if Plus
Branch if Greater or Equal, Signed
Branch if Less Than Zero, Signed
Branch if Half Carry Flag Set
Branch if Half Carry Flag Cleared
Branch if T Flag Set
Branch if T Flag Cleared
Branch if Overflow Flag is Set
Branch if Overflow Flag is Cleared
Branch if Interrupt Enabled
Branch if Interrupt Disabled
BIT AND BIT-TEST INSTRUCTIONS
Set Bit in I/O Register
k
SBI
CBI
LSL
P,b
P,b
Rd
I/O(P,b) ←1
I/O(P,b) ←0
Rd(n+1) ←Rd(n), Rd(0) ←0
None
None
Z,C,N,V
2
2
1
Clear Bit in I/O Register
Logical Shift Left
287
9219A–RFID–01/11
27. Instruction Set Summary
Mnemonics
Operands
Description
Operation
Flags
#Clocks
LSR
ROL
ROR
ASR
SWAP
BSET
BCLR
BST
BLD
SEC
CLC
SEN
CLN
SEZ
CLZ
SEI
Rd
Rd
Rd
Rd
Rd
s
Logical Shift Right
Rotate Left Through Carry
Rotate Right Through Carry
Arithmetic Shift Right
Swap Nibbles
Flag Set
Flag Clear
Bit Store from Register to T
Bit load from T to Register
Set Carry
Rd(n) ←Rd(n+1), Rd(7) ←0
Rd(0)←C,Rd(n+1)←Rd(n),C←Rd(7)
Rd(7)←C,Rd(n)←Rd(n+1),C←Rd(0)
Rd(n) ←Rd(n+1), n=0..6
Rd(3..0)←Rd(7..4),Rd(7..4)←Rd(3..0)
Z,C,N,V
Z,C,N,V
Z,C,N,V
Z,C,N,V
None
SREG(s)
SREG(s)
T
None
C
C
N
N
Z
Z
I
I
S
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
SREG(s) ←1
SREG(s) ←0
T ←Rr(b)
Rd(b) ←T
C ←1
s
Rr, b
Rd, b
Clear Carry
Set Negative Flag
Clear Negative Flag
Set Zero Flag
Clear Zero Flag
C ←0
N ←1
N ←0
Z ←1
Z ←0
I ←1
I ←0
S ←1
S ←0
V ←1
V ←0
T ←1
T ←0
H ←1
H ←0
Global Interrupt Enable
Global Interrupt Disable
Set Signed Test Flag
Clear Signed Test Flag
Set Twos Complement Overflow.
Clear Twos Complement Overflow
Set T in SREG
CLI
SES
CLS
SEV
CLV
SET
CLT
S
V
V
T
T
H
H
Clear T in SREG
SEH
CLH
Set Half Carry Flag in SREG
Clear Half Carry Flag in SREG
DATA TRANSFER INSTRUCTIONS
Move Between Registers
Copy Register Word
Load Immediate
MOV
MOVW
LDI
LD
LD
LD
LD
LD
LD
LDD
LD
LD
LD
LDD
LDS
ST
ST
ST
ST
ST
ST
STD
ST
ST
ST
STD
STS
LPM
LPM
LPM
SPM
IN
OUT
PUSH
POP
Rd, Rr
Rd, Rr
Rd, K
Rd ←Rr
Rd+1:Rd ←Rr+1:Rr
Rd ←K
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
None
1
1
1
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
3
3
3
-
Rd, X
Load Indirect
Rd ←(X)
Rd, X+
Rd, - X
Rd, Y
Rd, Y+
Rd, - Y
Rd,Y+q
Rd, Z
Rd, Z+
Rd, -Z
Rd, Z+q
Rd, k
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Indirect
Load Indirect and Post-Inc.
Load Indirect and Pre-Dec.
Load Indirect with Displacement
Load Direct from SRAM
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Indirect
Store Indirect and Post-Inc.
Store Indirect and Pre-Dec.
Store Indirect with Displacement
Store Direct to SRAM
Load Program Memory
Load Program Memory
Load Program Memory and Post-Inc
Store Program Memory
In Port
Rd ←(X), X ←X + 1
X ←X - 1, Rd ←(X)
Rd ←(Y)
Rd ←(Y), Y ←Y + 1
Y ←Y - 1, Rd ←(Y)
Rd ←(Y + q)
Rd ←(Z)
Rd ←(Z), Z ←Z+1
Z ←Z - 1, Rd ←(Z)
Rd ←(Z + q)
Rd ←(k)
X, Rr
(X) ←Rr
X+, Rr
- X, Rr
Y, Rr
Y+, Rr
- Y, Rr
Y+q,Rr
Z, Rr
Z+, Rr
-Z, Rr
Z+q,Rr
k, Rr
(X) ←Rr, X ←X + 1
X ←X - 1, (X) ←Rr
(Y) ←Rr
(Y) ←Rr, Y ←Y + 1
Y ←Y - 1, (Y) ←Rr
(Y + q) ←Rr
(Z) ←Rr
(Z) ←Rr, Z ←Z + 1
Z ←Z - 1, (Z) ←Rr
(Z + q) ←Rr
(k) ←Rr
R0 ←(Z)
Rd ←(Z)
Rd, Z
Rd, Z+
Rd ←(Z), Z ←Z+1
(Z) ←R1:R0
Rd ←P
P ←Rr
STACK ←Rr
Rd ←STACK
Rd, P
P, Rr
Rr
1
1
2
2
Out Port
Push Register on Stack
Pop Register from Stack
MCU CONTROL INSTRUCTIONS
No Operation
Rd
NOP
SLEEP
WDR
None
None
None
None
1
1
1
(see specific descr. for Sleep
(see specific descr. for WDR/timer)
For On-chip Debug Only
Sleep
Watchdog Reset
BREAK
Break
N/A
288
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
28. Application Examples
Please refer to the following pages for examples of typical applications based on the Atmel®
ATA5505 device.
Figure 28-1. Atmel ATA5505 Reader with SPI
SS
SCK
MISO
MOSI
D3
VS
2
1
3
3
R5
68kΩ
VS
J5
Feedback Circuit
1
3
5
2
4
6
BAV23C
MISO
SCK
RST
V+
MOSI
GND
D5
R4
100kΩ
2
1
R8
ISP
GND
43kΩ
R9
75kΩ
BAV23A
C12
4700pF
100V
VS
GND
GND
OUTPUT
GND
R3
4.7kΩ
C5
1
31
PA5
GND
2
3
30
29
28
27
26
25
24
23
22
21
20
1000pF
100V, COG
PA6
PA1
PA0
TUNE
RST
PA7
Tank Circuit
4
PB7/RST
PB6
PB0
PB1
PB2
PB3
RF
C9
5
U1
Atmel
ATA5505
1000pF
100V, COG
6
PB5
VS
7
PB4/XTAL
VDD
8
C8
9
1000pF
100V, COG
OUTPUT
OE
GAIN
VS
10
11
12
C11
0.22µF
GND
VS
INPUT
MS
STBY
VBAT
C14
0.1µF
C13
0.1µF
GND
L1
735µH
R10
CFE
24Ω
GND
GND
Coil2
Coil1
D6
R11
1kΩ
1
2
C16
INPUT
680pF
100V
BAV21WS
C6
C17
R12
390kΩ
330pF
2200pF
100V
Input Circuit
GND
GND
Q1
TUNE
TN2404K
GND
125kHz
289
9219A–RFID–01/11
Figure 28-2. Atmel® ATA5505 Reader with UART
D3
VS
2
1
3
3
VS
J5
R5
68kΩ
1
3
5
2
4
6
MISO
SCK
RST
V+
MOSI
GND
Feedback Circuit
BAV23C
D5
R4
100kΩ
2
1
R8
ISP
GND
43kΩ
R9
75kΩ
BAV23A
C12
4700pF
100V
VS
GND
OUTPUT
GND
GND
R3
4.7kΩ
C5
1
31
PA5
GND
TUNE
2
3
30
29
28
27
26
25
24
23
22
21
20
1000pF
100V, COG
PA6
PA1
PA0
TXD
RXD
PA7
Tank Circuit
RST
4
PB7/RST
PB6
PB0
PB1
PB2
PB3
RF
C9
5
U1
Atmel
ATA5505
1000pF
100V, COG
6
PB5
VS
7
PB4/XTAL
VDD
8
C8
9
1000pF
100V, COG
OUTPUT
OE
GAIN
VS
10
11
12
C11
0.22µF
GND
VS
INPUT
MS
STBY
VBAT
C14
0.1µF
C13
0.1µF
GND
L1
735 µH
R10
CFE
24Ω
GND
GND
Coil2
Coil1
D6
R11
1kΩ
1
2
C16
INPUT
680pF
100V
BAV21WS
C6
C17
R12
390kΩ
330pF
2200pF
100V
Input Circuit
GND
GND
Q1
TUNE
TN2404K
125kHz
GND
290
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
Figure 28-3. Atmel® ATA5505 Reader with USI
SCK
D3
VS
MISO
MOSI
2
1
3
3
R5
68kΩ
VS
J5
Feedback Circuit
1
3
5
2
4
6
BAV23C
MISO
SCK
RST
V+
MOSI
GND
D5
R4
2
1
100kΩ
R8
ISP
GND
43kΩ
R9
75kΩ
BAV23A
C12
4700pF
100V
VS
GND
OUTPUT
GND
GND
R3
4.7kΩ
C5
1
31
30
29
28
27
26
25
24
23
22
21
20
PA5
GND
PA1
2
3
1000pF
100V, COG
PA6
TUNE
RST
PA7
PA0
Tank Circuit
4
PB7/RST
PB6
PB0
PB1
PB2
PB3
RF
C9
5
U1
Atmel
ATA5505
1000pF
100V, COG
6
PB5
VS
7
PB4/XTAL
VDD
8
C8
9
1000pF
100V, COG
OUTPUT
OE
GAIN
VS
10
11
12
C11
VS
INPUT
MS
STBY
VBAT
0.22µF
GND
C14
0.1µF
C13
0.1µF
GND
L1
735 µH
R10
CFE
24Ω
GND
GND
Coil2
Coil1
D6
R11
1kΩ
1
2
C16
INPUT
680pF
100V
BAV21WS
C6
C17
R12
390kΩ
330pF
2200pF
100V
Input Circuit
GND
GND
Q1
TUNE
TN2404K
GND
125kHz
291
9219A–RFID–01/11
Figure 28-4. Atmel® ATA5505 Reader with LIN Transceiver
D3
V5
2
1
3
V5
J5
R5
68kΩ
1
3
5
2
4
6
MISO
SCK
RST
V+
MOSI
GND
Feedback Circuit
BAV23C
D5
R4
2
1
100kΩ
R8
ISP
3
GND
43kΩ
R9
75kΩ
BAV23A
C12
4700pF
100V
V5
GND
OUTPUT
GND
GND
R3
4.7kΩ
C5
1
31
PA5
GND
TXD
RXD
TUNE
2
3
30
29
28
27
26
25
24
23
22
21
20
1000pF
100V, COG
PA6
PA1
PA0
PA7
Tank Circuit
RST
4
PB7/RST
PB6
PB0
PB1
PB2
PB3
RF
C9
5
U1
Atmel
ATA5505
1000pF
100V, COG
6
PB5
V5
7
PB4/XTAL
VDD
8
C8
9
1000pF
100V, COG
OUTPUT
OE
GAIN
VS
10
11
12
C11
V5
INPUT
MS
STBY
VBAT
0.22µF
GND
C14
0.1µF
C13
0.1µF
GND
L1
735µH
R10
CFE
24Ω
GND
GND
Coil2
Coil1
D6
R11
1kΩ
1
2
C16
INPUT
680pF
100V
BAV21WS
C6
C17
R12
390kΩ
VBatt
330pF
2200pF
100V
C31
Input Circuit
5
0.1µF
GND
GND
Q1
WAKE
VS
7
TUNE
Master Node
Pull up
V5
EN
INH
D32
R31
2
8
TN2404K
U1
Atmel
Not needed for
Slave Node.
GND
R32
ATA6662
4.7kΩ
*1)
4
1
LIN
BUS
*1) Optional instead of Atmel ATA6662:
TXD
RXD
LIN
6
C32
Atmel ATA6624: add. voltage regulator and Watchdog
Atmel ATA6625: add. voltage regulator
GND
5
220pF
292
Atmel ATA5505 [Preliminary]
9219A–RFID–01/11
Atmel ATA5505 [Preliminary]
29. Ordering Information
Extended Type Number
Package
Remarks
ATA5505-P3QW
QFN38 5 mm × 7 mm
Green package, 16k flash
30. Package Information
Top View
D
40
1
PIN 1 ID
technical drawings
according to DIN
specifications
Dimensions in mm
Side View
Bottom View
D2
13
19
20
12
COMMON DIMENSIONS
(Unit of Measure = mm)
Symbol MIN
NOM
0.9
MAX NOTE
A
A1
A3
D
0.8
0.0
1
0.02
0.2
0.05
0.25
5.1
0.15
4.9
1
5
31
D2
E
3.45
6.9
3.6
3.75
7.1
32
38
7
e
Z
E2
L
5.45
0.3
5.6
5.75
0.5
0.4
b
0.16
0.23
0.5 BSC
0.3
Z 10:1
e
b
08/22/08
DRAWING NO.
TITLE
REV.
Package Drawing Contact:
packagedrawings@atmel.com
Package: VQFN_5x7_38L
Exposed pad 3.6x5.6
6.543-5156.01-4
1
293
9219A–RFID–01/11
Atmel Corporation
2325 Orchard Parkway
San Jose, CA 95131
USA
Tel: (+1)(408) 441-0311
Fax: (+1)(408) 487-2600
Atmel Asia Limited
Unit 01-5 & 16, 19/F
BEA Tower, Millennium City 5
418 Kwun Tong Road
Kwun Tong, Kowloon
HONG KONG
Atmel Munich GmbH
Business Campus
Parkring 4
D-85748 Garching b. Munich
GERMANY
Atmel Japan
9F, Tonetsu Shinkawa Bldg.
1-24-8 Shinkawa
Chuo-ku, Tokyo 104-0033
JAPAN
Tel: (+81) (3) 3523-3551
Fax: (+81) (3) 3523-7581
Tel: (+49) 89-31970-0
Fax: (+49) 89-3194621
Tel: (+852) 2245-6100
Fax: (+852) 2722-1369
© 2011 Atmel Corporation. All rights reserved. / Rev.: 9219A–RFID–01/11
Atmel®, Atmel logo and combinations thereof, AVR®, AVR Studio® and others are registered trademarks or trademarks of Atmel Corporation or
its subsidiaries. Other terms and product names may be trademarks of others.
Disclaimer: The information in this document is provided in connection with Atmel products. No license, express or implied, by estoppel or otherwise, to any intellec-
tual property right is granted by this document or in connection with the sale of Atmel products. EXCEPT AS SET FORTH IN THE ATMEL TERMS AND CONDITIONS
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