AS4C4M4 [AUSTIN]
4M x 4 CMOS DRAM WITH FAST PAGE MODE, 5 VOLT; 4M ×4 CMOS的DRAM快速页面模式， 5伏
| 型号： | AS4C4M4 |
| 厂家： | 
AUSTIN SEMICONDUCTOR |
| 描述： | 4M x 4 CMOS DRAM WITH FAST PAGE MODE, 5 VOLT |
| 文件： | 总19页 (文件大小：2644K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
4M x 4 CMOS DRAM
WITH FAST PAGE MODE, 5 VOLT
PIN ASSIGNMENT
(Top View)
24 Pin TSOP (DG)
AVAILABLEAS MILITARY
SPECIFICATIONS
• MIL-STD-883
1
2
3
4
5
6
24
23
22
21
20
19
Vss
Vcc
DQ0
DQ1
W\
RAS\
NC
DQ3
DQ2
CAS\
OE\
A9
FEATURES
• Fast Page Mode Operation
• CAS\-before-RAS\ Refresh Capability
• RAS\-only and Hidden Refresh Capability
• Self-refresh Capability
• Fast Parallel Test Mode Capability
• TTL Compatible Inputs and Outputs
• Early Write or Output Enable Controlled Write
• JEDEC Standard Pinout
7
8
9
10
11
12
18
17
16
15
14
13
A8
A7
A6
A5
A4
Vss
A10
A0
A1
A2
A3
Vcc
• Single +5V (±10%) Power Supply
OPTIONS
MARKINGS
•
Timing
60ns access
70ns access
-6
-7
PIN ASSIGNMENT
PIN
FUNCTION
A0 - A10
Address Inputs
Data In/Out
•
Package
Plastic TSOP, 24-pin
DG
DQ0 -DQ3
VSS
Ground
• Operating Temperature Ranges
Military (-55oC to +125oC)
Industrial (-40oC to +85oC)
XT
IT
RAS\
CAS\
W\
Row Address Strobe
Column Address Strobe
Read/Write Input
Data Output Enable
Power (+5V)
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. AS4C4M4DG is a
4,194,304 x 4 bit Fast Page Mode CMOS DRAM offering
high speed random access of memory cells within the same
row. This device features a +5V (±10%) power supply,
refresh cycle (2K), and fast access times (60 and 70ns). Other
features include CAS\-before-RAS\, RAS\-only refresh, and
Hidden refresh capabilities. This 4M x 4 Fast Page Mode DRAM
is fabricated using an advanced CMOS process to realize high
bandwidth, low power consumption and high reliability. It may
be used as main memory for high level computers,
microcomputers and personal computers.
OE\
VCC
NC
No Connect
PERFORMANCE RANGE
SPEED
t
t
t
t
UNITS
RAC
CAC
RC
PC
40
45
-6
-7
60
70
15
18
110
130
ns
ns
For more products and information
please visit our web site at
www.austinsemiconductor.com
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
1
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
VCC
RAS\
Control
Clocks
VSS
CAS\
W\
VBB Generator
Data In
Buffer
Row Decoder
Refresh Timer
Refresh Control
Refresh Counter
DQ0
to
DQ3
Memory Array
4,194,304 x 4
Cells
Row Address Buffer
Col. Address Buffer
(A0 - A10)
(A0 - A10)
Data Out
Buffer
Column Decoder
OE\
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied.
Exposure to absolute maximum rating conditions for extended
periods may affect reliability. Junction temperature depends
upon package type, cycle time, loading, ambient temperature
and airflow, and humidity (plastics).
ABSOLUTE MAXIMUM RATINGS*
Voltage on any pin relative to VCC (VIN, VOUT) .....-1.0V to +7.0V
Voltage on VCC supply relative to VSS (VCC).........-1.0V to +7.0V
Storage Temperature (Tstg)................................-55°C to +150°C
Power Dissipation (PD).............................................................1W
Short Circuit Output Current (IOS Address).........................50mA
ELECTRICAL CHARACTERISTICSAND RECOMMENDED OPERATING CONDITIONS
(-55oC < TA < +125oC & -40oC < TA < +85oC ; Vcc = 5V +10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
Supply Voltage
4.5
5.0
5.5
V
VCC
VCC + 0.51
0.8
Input High Voltage
Input Low Voltage
NOTES:
2.4
---
---
V
V
VIH
VIL
-0.52
1. VCC + 2.0V/20ns, Pulse width is measured at VCC
2. -2.0V/20ns, Pulse width is measured at VSS
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
2
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TA < +125oC & -40oC < TA < +85oC ; Vcc = 5V +10%)
PARAMETER
SYMBOL
MIN
MAX
UNITS
Input Leakage Current (any input 0<VIN<VIN+0.5V,
all other input pins not under test = 0 Volt)
Output Leakage Current
-5
5
uA
II(L)
-5
5
uA
IO(L)
(Data out is disabled, 0V<VOUT<VCC
Output High Voltage (IOH = -5mA)
Output Low Voltage (IOL = 4.2mA)
)
2.4
---
---
V
V
VOH
VOL
0.4
MAX
SYMBOL
PARAMETERS
-60
-70
UNITS
Operating Current (RAS\ and CAS\, Address cycling @ tRC = MIN),
Power = Don't Care
110
100
mA
ICC1
*
Standby Current (RAS\ = CAS\ = W\ = VIH)
Power = Normal L
3
3
mA
mA
ICC2
RAS\-only Refresh Current (CAS\ = VIH, RAS\, Address cycling @
tRC = MIN), Power = Don't Care
110
100
ICC3
*
Fast Page Mode Current (RAS\ = VIL, CAS\, Address cycling @
tPC = MIN), Power = Don't Care
90
80
mA
ICC4
*
Standby Current (RAS\ = CAS\ = W\ = Vcc - 0.2V)
Power = Normal L
CAS\-BEFORE-RAS\ Refresh Current (RAS\ and CAS\ cycling @
ICC5
ICC6
2
2
mA
mA
110
100
*
tRC = MIN), Power = Don't Care
Battery back-up current, Average power supply current, Battery back-
up mode, Input high voltage (VIH) = VCC - 0.2V, Input low voltage
ICC7
1
1
1
1
mA
(VIL) = 0.2V, CAS\ = 0.2V, DQ = Don't care, tRC = 62.5us (2K/L-ver),
tRAS = tRAS min ~ 300ns
Self Refresh Current, RAS\ = CAS\ = 0.2V, W\ = OE\ = A0 ~ A11 =
VCC - 0.2V or 0.2V, DQ0 ~ DQ3 = VCC - 0.2V, 0.2V or Open
ICCS
NOTES:
*ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an
average current. In ICC1, ICC3, and ICC6 address can be changed maximum once while RAS\ = VIL. In ICC4, address can be changed maximum once within one
fast page mode cycle time, tPC
.
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
3
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
CAPACITANCE (TA < +25oC ; Vcc = 5V +10%)
PARAMETER
SYMBOL
MAX
UNITS
Input capacitance (A0 - A11)
C
C
C
6
pF
IN1
IN2
DQ
Input capacitance (RAS\, CAS\, W\, OE\)
Output capacitance (DQ0 - DQ3)
8
8
pF
pF
ELECTRICAL CHARACTERISTICSAND RECOMMENDED AC OPERATING CONDITIONS1,2
(-55oC<TA<+125oC & -40oC<TA<+85oC; Vcc = 5V +10%; VIH/VIL = 2.4/0.8V; VOH/VOL = 2.4/0.4V)
-60
-70
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNITS
NOTES
Random read or write cycle time
110
130
ns
tRC
Read-modify-write cycle time
Access time from RAS\
155
185
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRWC
tRAC
tCAC
tAA
60
15
30
70
20
35
3, 4, 10
Access time from CAS\
3, 4, 5
Access time from column address
CAS\ to output in Low-Z
3, 10
0
0
0
0
3
6
2
tCLZ
tOFF
tT
Output buffer turn-off delay
Transition time (raise and fall)
RAS\ precharge time
15
50
15
50
3
3
40
60
15
60
15
20
15
5
50
70
17
65
18
25
17
5
tRP
RAS\ pulse width
10K
10K
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
RAS\ hold time
CAS\ hold time
CAS\ pulse width
10K
45
10K
50
RAS\ to CAS\ delay time
4
RAS\ to column address delay time
CAS\ to RAS\ precharge time
Row address set-up time
30
35
10
0
0
Row address hold time
10
0
10
0
Column address set-up time
Column address hold time
Column address to RAS\ lead time
Read command set-up time
Read command hold time referenced to CAS\
Read command hold time referenced to RAS\
Write command hold time
Write command pulse width
Write command to RAS\ lead time
Write command to CAS\ lead time
10
30
0
12
35
0
0
0
8
8
0
0
10
10
15
15
12
12
17
17
tRWL
tCWL
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
4
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICSAND RECOMMENDED AC OPERATING CONDITIONS1,2
(CONTINUED)
-60
-70
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNITS
NOTES
Data set-up time
Data hold time
Refresh period
0
0
ns
9
tDS
10
12
ns
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
9
tDH
tREF
32
32
Write command set-up time
0
0
7
7
7
7
tWCS
tCWD
tRWD
tAWD
tCPWD
tCSR
tCHR
tRPC
tCPA
tPC
CAS\ to W\ delay time
40
85
55
60
5
45
90
60
65
5
RAS\ to W\ delay time
Column address to W\ delay time
CAS\ precharge to W\ delay time
CAS\ set-up time (CAS\-before-RAS\ refresh)
CAS\ hold time (CAS\-before-RAS\ refresh)
RAS\ to CAS\ precharge time
10
5
15
5
Access time from CAS\ precharge
Fast Page cycle time
35
40
3
40
85
10
60
35
45
95
10
70
40
Fast Page read-modify-write cycle time
CAS\ precharge time (Fast Page Cycle)
RAS\ pulse width (Fast Page Cycle)
RAS\ hold time from CAS\ precharge
OE\ access time
tPRWC
tCP
100K
15
100K
17
tRASP
tRHCP
tOEA
tOED
tOEZ
tOEH
tWTS
tWTH
tWRP
tWRH
tRASS
tRPS
tCHS
OE\ to data delay
15
0
17
0
Output buffer turn off delay time from OE\
OE\ command hold time
15
17
6
15
17
Write command set-up time (Test mode in)
Write command hold time (Test mode in)
W\ to RAS\ precharge time (C\-B-R\ refresh)
W\ to RAS\ hold time (C\-B-R\ refresh)
RAS\ pulse width (C\-B-R\ self refresh)
RAS\ precharge time (C\-B-R\ self refresh)
CAS\ hold time (C\-B-R\ self refresh)
10
10
11
11
10
10
10
10
10
10
100
110
-50
110
120
-50
13, 14, 15
13, 14, 15
13, 14, 15
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
5
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
TEST MODE CYCLE11
-60
-70
SYMBOL
PARAMETER
MIN
MAX
MIN
MAX
UNITS
NOTES
Random read or write cycle time
Read-modify-write cycle time
Access time from RAS\
Access time from CAS\
Access time from column address
RAS\ pulse width
115
135
ns
tRC
160
180
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tRWC
tRAC
tCAC
tAA
65
20
70
22
3, 4, 10, 12
3, 4, 5, 12
3, 10 ,12
35
38
65
20
20
65
35
45
90
60
65
45
90
65
10K
10K
75
25
10K
10K
tRAS
tCAS
tRSH
tCSH
tRAL
CAS\ pulse width
RAS\ hold time
22
CAS\ hold time
70
Column address to RAS\ lead time
CAS\ to W\ delay time
40
48
7
7
7
tCWD
tRWD
tAWD
tCPWD
tPC
RAS\ to W\ delay time
100
70
Column address to W\ delay time
CAS\ precharge to W\ delay time
Fast Page cycle time
70
50
Fast Page read-modify-write time
RAS\ pulse width (Fast Page Cycle)
Access time from CAS\ precharge
OE\ access time
100
75
tPRWC
tRASP
tCPA
tOEA
tOED
tOEH
100K
40
100K
45
3
20
22
OE\ to data delay
20
20
22
22
OE\ command hold time
NOTES:
1. An initial pause of 200us is required after power-up followed by an 8 RAS\-only refresh or CAS\-before-RAS\ refresh cycles
before proper device operation is achieved.
2. VIH(MIN) and VIL(MAX) are reference levels for measuring timing of input signals. Transition times are measured between
VIH(MIN) and VIL(MAX) and are assumed to be 5ns for all inputs.
3. Measured with a load equivalent to 2 TTL loads and 100pF.
4. Operation within the tRCD(MAX) limit insures that tRAC(MAX) and be met. tRCD(MAX) is specified as a reference point only.
If tRCD is greater than the specified tRCD(MAX) limit, then access time is controlled exclusively by tCAC
5. Assumes that tRCD > tRCD(MAX).
.
6. tOFF(MIN) and tOEZ(MAX) define the time at which the output achieves the open circuit condition and are not referenced VOH
or VOL.
7. tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electrical character-
istics only. If tWCS > tWCS(MIN), the cycle is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD > tCWD(MIN), tRWD > tRWD(MIN) and tAWD > tAWD(MIN), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
(Continued on page 7)
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
6
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
NOTES (continued):
8. Either tRCH or tRRH must be satisfied for a read cycle.
9. These parameters are referenced to CAS\ falling edge in early write cycles and to W\ falling edge in read-modify-write
cycles.
10. Operation within the tRAD(MAX) limit insures that tRAC(MAX) can be met. tRAD(MAX) is specified as a reference point only.
If tRAD is greater than the specified tRAS(MAX) limit, then access time is controlled by tAA.
11. These specifications are applied in the test mode.
12. In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.
13. If tRASS > 100 us, then RAS\ precharge time must use tRPS instead of tRP.
14. For RAS\-only refresh and burst CAS\-before-RAS\ refresh mode, 2048 cycles of burst refresh must be executed within
32ms before and after self refresh, in order to meet refresh specification.
15. For distributed CAS\-before-RAS\ with 15.6us interval CAS\-before-RAS\ refresh should be executed with in 15.6us
immediately before and after self refresh in order to meet refresh specification.
READ CYCLE
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
7
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
WRITE CYCLE (EARLY WRITE) DOUT = OPEN
AS4C4M4
Rev. 1.1 06/05
8
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
WRITE CYCLE (OE\ CONTROLLED WRITE) DOUT = OPEN
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
9
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
READ-MODIFY-WRITE CYCLE
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
10
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
FAST PAGE READ CYCLE
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
11
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
FAST PAGE WRITE CYCLE (EARLY WRITE) DOUT = OPEN
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
12
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
FAST PAGE READ-MODIFY-WRITE CYCLE
AS4C4M4
Rev. 1.1 06/05
13
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
RAS\-ONLY REFRESH CYCLE (W\, OE\, DIN = DON’T CARE; DOUT = OPEN)
CAS\-BEFORE-RAS\ REFRESH CYCLE (OE\, A = DON’T CARE)
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
14
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
HIDDEN REFRESH CYCLE (READ)
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
15
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
HIDDEN REFRESH CYCLE (WRITE) DOUT = OPEN
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
16
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
CAS\-BEFORE-RAS\ SELF REFRESH CYCLE (OE\, A = DON’T CARE)
TEST MODE IN CYCLE (OE\, A = DON’T CARE)
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
17
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
Package Designator DG
*All measurements are in inches (millimeters).
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
18
16 Meg FPM DRAM
AS4C4M4
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE:
AS4C4M4DG-7/IT
Device Number Package Type
Speed
Process
AS4C4M4
AS4C4M4
DG
DG
-6
-7
/*
/*
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT= Military Temperature Range
-40oC to +85oC
-55oC to +125oC
AS4C4M4
AustinSemiconductor,Inc.reservestherighttochangeproductsorspecificationswithoutnotice.
Rev. 1.1 06/05
19
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