AS5SS256K18DQ-10/IT [AUSTIN]
256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through; 256K ×18 SSRAM同步突发SRAM的流通
| 型号： | AS5SS256K18DQ-10/IT |
| 厂家： | 
AUSTIN SEMICONDUCTOR |
| 描述： | 256K x 18 SSRAM Synchronous Burst SRAM, Flow-Through |
| 文件： | 总13页 (文件大小：217K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
256K x 18 SSRAM
PIN ASSIGNMENT
Synchronous Burst SRAM,
(Top View)
Flow-Through
FEATURES
100-pinTQFP
• Fast access times: 8, 10, and 15ns
• Fast clock speed: 113, 100, and 66 MHz
• Fast clock and OE\ access times
• Single +3.3V +0.3V/-0.165V power supply (VDD
• SNOOZE MODE for reduced-power standby
• Common data inputs and data outputs
• Individual BYTE WRTIE control and GLOBAL WRITE
• Three chip enables for simple depth expansion and address
pipelining
• Clock-controlled and registered addresses, data I/Os and
control signals
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81
NC
NC
NC
DDQ
VSS
NC
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
SA
NC
NC
VDD
VSS
NC
DQPa
DQa
DQa
VSS
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
)
V
Q
NC
DQb
DQb
VSS
VDD
Q
DQb
DQb
VSS
VDD
Q
DQa
DQa
VSS
NC
VDD
ZZ
VDD
NC
VSS
DQb
DQb 19
DDQ
VSS 21
DQb 22
DQb
• Interally self-timed WRITE cycle
• Burst control pin (interleaved or linear burst)
• Automatic power-down
DQa
DQa
V
20
VDD
VSS
DQa
DQa
NC
NC
VSS
VDD
NC
NC
NC
Q
• Low capacitive bus loading
• Operating Temperature Ranges:
23
- Military -55oC to +125oC
DQPb 24
NC 25
- Industrial -40oC to +85oC
VSS
VDD
26
27
Q
Q
NC 28
NC
NC 30
OPTIONS
• Timing
MARKING
29
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
7.5ns/8ns/113 MHz
8.5ns/10ns/100 MHz
10ns/15ns/66 MHz
• Packages
-8*
-9
-10
**pins 42,43 reserved for future address expansion for 8Mb, 16Mb densities.
100-pin TQFP
DQ No. 1001
CE2), burst control inputs (ADSC\, ADSP\, ADV\), byte write enables
(BWx\) and global write (GW\).
• Operating Temperature Ranges:
- Military -55oC to +125oC
- Industrial -45oC to +85oC
*available as IT only.
IT
XT
Asynchronous inputs include the output enable (OE\), clock (CLK)
and snooze enable (ZZ). There is also a burst mode input (MODE) that
selects between interleaved and linear burst modes. The data-out (Q),
enabled by OE\, is also asynchronous. WRITE cycles can be from one
to two bytes wide, as controlled by the write control inputs.
Burst operation can be initiated with either address status processor
(ADSP\) or address status controller (ADSC\) inputs. Subsequent burst
addresses can be internally generated as controlled by the burst ad-
vance input (ADV\).
For more products and information
please visit our web site at
www.austinsemiconductor.com
Address and write control are registered on-chip to simplify WRITE
cycles. This allows self-timed WRITE cycles. Individual byte enables
allow individual bytes to be written. During WRITE cycles on this x18
device BWa\ controls DQa pins and DQPa; BWb\ controls DQb pins
and DQPb. GW\ LOW causes all bytes to be written. Parity bits are
available on this device.
ASI’s 4Mb Synchronous Burst SRAMs operate from a +3.3V VDD
power supply, and all inputs and outputs are TTL-compatible. The de-
vice is ideally suited for 486, Pentium®, and PowerPC systems and
those systems that benefit from a wide synchronous data bus.
GENERAL DESCRIPTION
The Austin Semiconductor, Inc. Synchronous Burst SRAM family
employs high-speed, low power CMOS designs that are fabricated us-
ing an advanced CMOS process.
ASI’s 4Mb Synchronous Burst SRAMs integrate a 256K x 18, SRAM
core with advanced synchronous peripheral circuitry and a 2-bit burst
counter. All synchronous inputs pass through registers controlled by a
positive-edge-triggered single clock input (CLK). The synchronous
inputs include all addresses, all data inputs, active LOW chip enable
(CE\), two additional chip enables for easy depth expansion (CE2\,
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS256K18
Rev. 2.0 12/00
1
SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
PIN DESCRIPTIONS
PIN NUMBERS
SYM
TYPE
DESCRIPTION
37, 36, 32-35, 44-50, SA0, SA1,
Input
Synchronous Address Inputs: These inputs are registered and must meet the setup and
hold times around the rising edge of CLK.
80-82, 99, 100
93, 94
SA
BWa\
BWb\
Input
Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be
written and must meet the setup and hold times around the rising edge of CLK. A byte
write enables is LOW for a WRITE cycle and HIGH for a READ cycle. BWa\ controls DQa
pins and DQPa; BWb\ controls DQb pins and DQPb.
87
88
BWE\
GW\
Input
Input
Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet
the setup and hold times around the rising edge of CLK.
Global Write: This active LOW input allows a full 18-bit WRITE to occur independent of the
BWE\ and BWx\ lines and must meet the setup and hold times around the rising edge of
CLK.
89
98
CLK
CE\
Input
Input
Clock: This signal registers the addresses, data, chip enables, byte write enables and burst
control inputs on its rising edge. All synchronous inputs must meet setup and hold times
around the clock’s rising edge.
Synchronous Chip Enable: This active LOW input is used to enable the device and
Conditions the internal use of ADSP\. CE\ is sampled only when a new external address is
loaded.
92
97
CE2\
CE2
Input
Input
Synchronous Chip Enable: This active LOW input is used to enable the device and is
sampled only when a new external address is loaded.
Synchronous Chip Enable: This active HIGH input is used to enable the device and is
sampled only when a new external address is loaded.
86
83
OE\
Input
Input
Output Enable: This active LOW, asynchronous input enables the data I/O output drivers.
ADV\
Synchronous Address Advance: This active LOW input is used to advance the internal
burst counter, controlling burst access after the external address is loaded. A HIGH on this
pin effectively causes wait states to be generated (no address advance). To ensure use of
correct address during WRITE cycle, ADV\ must be HIGH at the rising edge of the first
clock after an ADSP\ cycle is initiated.
84
85
ADSP\
ADSC\
Input
Input
Synchronous Address Status Processor: This active LOW input interrupts any ongoing
burst, causing a new external address to be registered. A READ is performed using the
new address, independent of the byte write enables and ADSC\, but dependent upon CE\,
CE2, and CE2\. ADSP\ is ignored if CE\ is HIGH. Power-down state is entered if CE2 if
LOW or CE2\ is HIGH.
Synchronous Address Status Controller: This active LOW input interrupts any ongoing
burst, causing a new external address to be registered. A READ or WRITE is performed
using the new address if CE\ is LOW. ADSC\ is also used to place the chip into power-
down state when CE\ is HIGH.
31
64
MODE
ZZ
Input
Input
Mode: This input selects the burst sequence. A LOW on this pin selects LINEAR BURST. A
NC or HIGH on this pin selects INTERLEAVED BURST. Do not alter input state while
device is operating.
Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-
power standby mode in which all data in the memory array is retained. When ZZ is active,
all other inputs are ignored.
(a) 58, 59, 62, 63, 68,
69, 72, 73
DQa
DQb
Input/ SRAM Data I/Os: Byte "a" is DQa pins; Byte "b" is DQb pins. Input data must meet setup
Output and hold times around the rising edge of CLK.
(b) 8, 9, 12,13, 18, 19,
22, 23
74, 24
NC/DQPa
NC/DQPb
NC/ I/O No Connect/Parity Data I/Os: Byte "a" is DQPa pins; Byte "b" is DQPb pins.
15, 41,65, 91
VDD
Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range.
4, 11, 20, 27, 54, 61,
70, 77
VDDQ
Supply Isolated Output Buffer Supply: See DC Electrical Characterics and Operating Conditions for
range.
5, 10, 14, 17, 21, 26,
VSS
Supply Ground: GND
40, 55, 60, 67 71, 76,
90
38, 39
DNU
NC
---
Do Not Use: These signals may either be unconnected or wired to GND to improve
package heat dissipation.
1-3, 6, 7, 16,25, 28-30,
51-53, 56,57, 66, 75,
78, 79, 95, 96
-----
No Connect: These signals are not internally connected and may be connected to ground to
improve package heat dissipation.
42, 43
NF
No Function: These pins are internally connected to the die and will have the capacitance of
input pins. It is allowable to leave these pins unconnected or driven by signals.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS256K18
Rev. 2.0 12/00
2
SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
INTERLEAVED BURST ADDRESS TABLE (MODE=NC OR HIGH)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X…X00
X…X01
X…X10
X…X11
X…X01
X…X00
X…X11
X…X10
X…X10
X…X11
X…X00
X…X01
X…X11
X…X10
X…X01
X…X00
LINEAR BURST ADDRESS TABLE (MODE=LOW)
FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) THIRD ADDRESS (INTERNAL) FOURTH ADDRESS (INTERNAL)
X…X00
X…X01
X…X10
X…X11
X…X01
X…X10
X…X11
X…X00
X…X10
X…X11
X…X00
X…X01
X…X11
X…X00
X…X01
X…X10
PARTIAL TRUTH TABLE FOR WRITE COMMANDS
FUNCTION
READ
READ
WRITE Byte "a"
WRITE Byte "b"
WRITE All Bytes
WRITE All Bytes
GW\
H
H
H
H
BWE\
BWa\
BWb\
H
L
L
L
L
X
X
H
L
H
L
X
H
H
L
L
X
H
L
X
NOTE: Using BWE\ and BWa\ through BWb\, any one or more bytes may be
written.
FUNCTIONAL BLOCK DIAGRAM
18
18
16
18
ADDRESS
REGISTER
SA0, SA1, SA
2
SA0-SA1
MODE
ADV\
CLK
SA1'
SA0'
Q1
BINARY
COUNTER AND
LOGIC
Q0
CLR
ADSC\
ADSP\
9
9
BYTE "b"
WRITE DRIVER
9
9
BYTE "b"
WRITE REGISTER
BWb\
256K x 9 x 2
MEMORY
ARRAY
DQs
DQPa
DQPb
SENSE
AMPS
18
18
OUTPUT
BUFFERS
18
BYTE "a"
WRITE DRIVER
BYTE "a"
WRITE REGISTER
BWa\
BWE\
GW\
CE\
CE2
CE2\
OE\
18
INPUT
REGISTERS
ENABLE
REGISTER
2
NOTE: The Functional Block Diagram illustrates simplified device operation. See Truth Table, pin descriptions and timing
diagrams for detailed information.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS256K18
Rev. 2.0 12/00
3
SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
TRUTH TABLE
ADDRESS
USED
NONE
NONE
NONE
NONE
NONE
NONE
EXTERNAL
EXTERNAL
EXTERNAL
EXTERNAL
EXTERNAL
NEXT
OPERATION
CE\ CE2\ CE2 ZZ ADSP\ ADSC\ ADV\ WRITE\ OE\ CLK
DQ
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
DESELECT Cycle, Power-Down
SNOOZE MODE, Power-Down
READ Cycle, Begin Burst
READ Cycle, Begin Burst
WRITE Cycle, Begin Burst
READ Cycle, Begin Burst
H
L
X
X
H
X
H
X
L
X
L
L
L
L
L
L
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
X
L
L
X
X
L
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
X
X
L
X
X
X
X
X
X
L
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L-H High-Z
L
L
L
X
L
L
L
L
L
X
X
H
H
X
H
X
X
H
H
X
H
X
L
L
H
H
X
L
X
X
H
H
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
L
X
X
X
L
L
L
H
H
H
H
H
H
H
H
H
H
H
H
X
L-H
L-H High-Z
L-H
L-H
High-Z
Q
L
L
L
L
L
H
X
L
H
L
H
L
H
X
X
L
H
L
H
X
X
H
H
H
H
H
X
X
H
X
H
H
X
X
H
X
D
Q
H
H
H
H
H
H
L
READ Cycle, Begin Burst
L-H High-Z
L-H
L-H High-Z
L-H
L-H High-Z
L-H
L-H
L-H
L-H High-Z
L-H
L-H High-Z
L-H
L-H
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
READ Cycle, Continue Burst
WRITE Cycle, Continue Burst
WRITE Cycle, Continue Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
READ Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
WRITE Cycle, Suspend Burst
X
X
X
X
X
X
X
X
X
X
X
X
Q
NEXT
NEXT
NEXT
NEXT
L
L
L
L
Q
D
D
Q
NEXT
L
L
CURRENT
CURRENT
CURRENT
CURRENT
CURRENT
CURRENT
H
H
H
H
H
H
H
H
H
H
L
Q
D
D
L
NOTES: 1. X means “Don’t Care.” \ means active LOW. H means logic HIGH. L means logic LOW.
2. For WRITE\, L means any one or more byte write enable signals (BWa\, BWb\) and BWE\ are LOW or GW\ is LOW. WRITE\ = H for a ll BWx\,
BWE\, GW\ HIGH.
3. BWa\ enables WRITEs to DQas and DQPa. BWb\ enables WRITEs to DQbs and DQPb.
4. All inputs except OE\ and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK.
5. Wait states are inserted by suspending burst.
6. For a WRITE operation following a READ operation, OE\ must be HIGH before the input data setup time and held HIGH throughout the input
data hold time.
7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up.
8. ADSP\ LOW always initiates an internal READ at the L-H edge of CLK. A WRITE is performed by setting one or more byte write enable signals
and BWE\ LOW or GW\ LOW for the subsequent L-H edge of CLK. Refer to WRITE timing diagram for clarification.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS256K18
Rev. 2.0 12/00
4
SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
*Stresses greater than those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification is
not implied. Exposure to absolute maximum rating conditions for ex-
tended periods may affect reliability.
ABSOLUTE MAXIMUM RATINGS*
Voltage on VDD Supply Relative to VSS............-0.5V to +4.6V
Voltage on VDDQ Supply Relative to VSS.........-0.5V to +4.6V
Storage Temperature (plastic) .....................-55°C to +125°C
Max Junction Temperature**.......................................+150°C
Short Circuit Output Current..........…...........................100mA
**Maximum junction temperature depends upon package type, cycle
time, loading, ambient temperature and airflow.
DC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(-55oC < TA < +125oC and -40oC<TA<+85oC;VDD = +3.3V +0.3V/-0.165V unless otherwise noted)
DESCRIPTION
Input High (Logic 1) Voltage
Input Low (Logic 0) Voltage
CONDITIONS
SYMBOL
MIN
2.0
MAX
DD +0.3
UNITS
NOTES
1, 2
VIH
V
V
V
VIL
ILI
-0.3
0.8
2
1, 2
Input Leakage Current
-2
µΑ
(0V<VIN<VDD
)
3
Output(s) disabled;
0V<VIN<VDD
ILO
Output Leakage Current
-2
2
µΑ
IOH = -4.0mA
VOH
VOL
VDD
2.4
--
--
V
V
V
V
1, 4
1, 4
1
Output High Voltage
Output Low Voltage
Supply Voltage
IOL = 8.0 mA
0.5
3.6
3.6
3.135
3.135
VDDQ
1, 5
Isolated Output Buffer Supply
CAPACITANCE
DESCRIPTION
CONDITIONS
SYM
MAX
UNITS
NOTES
Control Input Capacitance
Input/Output Capacitance (DQ)
Address Capacitance
4
pF
6
CI
5
pF
pF
pF
6
6
6
TA = 25°C; f = 1MHz;
VDD = 3.3V
CO
CA
3.5
3.5
Clock Capacitance
CCK
THERMAL RESISTANCE
DESCRIPTION
CONDITIONS
SYM
TYP
UNITS
NOTES
Thermal Resistance
(Junction to Ambient)
46
°C/W
6
θJA
Test conditions follow standard test
methods and procedures for measuring
thermal impedance, per EIA/JESD51
Thermal Resistance
(Junction to Top of Case)
θJC
2.8
°C/W
6
NOTES:
1. All voltages referenced to VSS (GND)
2. Overshoot: VIH < +4.6V for t < tKC/2 for I < 20mA
Undershoot: VIL > -0.7V for t < tKC/2 for I < 20mA
Power-up: VIH < +3.6V and VDD<3.135V for t < 200ms
3. MODE pin has an internal pull-up, and input leakage = ±10µA.
4. The load used for VOH, VOL testing is shown in Figure 2 for 3.3V I/O. AC load current is higher then the stated DC values.
5. VDDQ should never exceed VDD. VDD and VDDQ can be connected together, for 3.3V I/O operation only.
6. This parameter is sampled.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS256K18
Rev. 2.0 12/00
5
SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
IDD ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS
(-55oC < TA < +125oC and -40oC<TA<+85oC;VDD = +3.3V +0.3V/-0.165V unless otherwise noted)
MAX
PARAMETER
CONDITIONS
Device selected; all inputs < VIL or > VIH;
SYM
-8
-9
-10 UNITS NOTES
Power Supply Current:
Operating
375
325
250
mA
2, 3, 4
IDD
Cycle time > tKC (MIN); VDD = MAX; Outputs Open
Device selected; VDD = MAX; ADSC\, ADSP\,
ADV\, GW\, BWx\ > VIH; All inputs < VSS +0.2 or
Power Supply Current:
Idle
IDD1
100
85
65
mA
2, 3, 4
> VDDQ -0.2; Cycle time > tKC (MIN);
Outputs Open
Device deselected; VDD = MAX;
CMOS Standby
TTL Standby
ISB2
10
25
10
25
10
25
mA
mA
3, 4
3, 4
All inputs < Vss +0.2 or > VDDQ -0.2;
All inputs static; CLK frequency =0
Device deselected; VDD = MAX;
All inputs < VIL or > VIH;
ISB3
All inputs static; CLK frequency = 0
Device deselected; VDD = MAX;
ASDP\, ADV\, GW\, BWx\ > VIH;
All inputs < VSS +0.2 or > VDDQ -0.2;
Clock Running
ISB4
100
85
65
mA
3, 4
Cycle time > tKC (MIN)
NOTES:
1. VDDQ = +3.3V +0.3V/-0.165V for 3.3V I/O configuration.
2. IDD is specified with no output current and increases with faster cycle times. IDDQ increases with faster cycle
times and greater output loading.
3. “Device deselected” means device is in power-down mode as defined in the truth table. “Device selected” means
device is active (not in power-down mode).
4. Typical values are measured at 3.3V, 25°C and 15ns cycle time.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS256K18
Rev. 2.0 12/00
6
SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) -55oC < TA < +125oC and -40oC<TA<+85oC;VDD = +3.3V +0.3V/-0.165V unless otherwise noted)
-8
-9
-10
DESCRIPTION
SYMBOL
UNITS NOTES
MIN MAX MIN MAX
MIN
MAX
CLOCK
Clock cycle time
8.8
10
15
ns
tKC
tKF
tKH
tKL
Clock frequency
Clock HIGH time
113
7.5
100
8.5
66
MHz
2.5
2.5
3.0
3.0
4.0
4.0
ns
ns
2
2
Clock LOW time
OUTPUT TIMES
Clock to output valid
10
ns
ns
ns
ns
ns
ns
ns
tKQ
Clock to output invalid
1.5
1.5
3.0
3.0
3.0
3.0
3
tKQX
Clock to output in Low-Z
Clock to output in High-Z
OE\ to output valid
3, 4, 5
3, 4, 5
6
tKQLZ
tKQHZ
tOEQ
tOELZ
tOEHZ
4.2
4.2
5.0
5.0
5.0
5.0
OE\ to output in Low-Z
0
0
0
3, 4, 5
3, 4, 5
OE\ to output in High-Z
SETUP TIMES
Address
4.2
5.0
5.0
ns
ns
ns
ns
ns
ns
1.5
1.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
1.8
1.8
2.0
2.0
2.0
2.0
2.0
2.0
7, 8
7, 8
7, 8
7, 8
7, 8
7, 8
tAS
tADSS
tAAS
tWS
Address status (ADSC\, ADSP\)
Address advance (ADV\)
Byte write enables (BWa\-BWb\, GW\, BWE\)
Data-in
tDS
Chip enable (CE\)
HOLD TIMES
Address
tCES
ns
ns
ns
ns
ns
ns
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
7, 8
7, 8
7, 8
7, 8
7, 8
7, 8
tAH
tADSH
tAAH
tWH
Address status (ADSC\, ADSP\)
Address advance (ADV\)
Byte write enables (BWa\-BWb\, GW\, BWE\)
Data-in
tDH
Chip enable (CE\)
tCEH
NOTES:
1. Test conditions as specified with the output loading shown in Figure 1 for 3.3V I/O (VDDQ = +3.3V +0.3V/-0.165V) unless otherwise
noted.
2. Measured as HIGH above VIH and LOW below VIL.
3. This parameter is measured with the output loading shown in Figure 2 for 3.3V I/O.
4. This parameter is sampled.
5. Transition is measured ±500mV from steady state voltage.
6. OE\ is a “Don’t Care” when a byte write enable is sampled LOW.
7. A READ cycle is defined by byte write enables all HIGH or ADSP\ LOW for the required setup and hold times. A WRITE cycle is
defined by at least one byte write enable LOW and ADSP\ HIGH for the required setup and hold times.
8. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when either ADSP\ or
ADSC\ is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges
of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when either ADSP\ or ADSC\ is LOW to
remain enabled.
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AS5SS256K18
Rev. 2.0 12/00
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SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
AC TEST CONDITIONS
OUTPUT LOADS
VIH = (VDD/2.2) + 1.5V
Input pulse levels
VIL = (VDD/2.2) - 1.5V
1ns
DQ
Input rise and fall times
Z0=50Ω
Input timing reference levels
V
DD/2.2
50Ω
Output reference levels
Output load
VDDQ/2.2
See Figures 1 and 2
Vt = 1.5V
LOAD DERATING CURVES
ASI’s 256K x 18 Synchronous Burst SRAM timing is dependent upon
Fig. 1 OUTPUT LOAD EQUIVALENT
the capacitive loading on the outputs.
3.3v
SNOOZE MODE
317Ω
SNOOZE MODE is a low-current, “power-down” mode in which the
device is deselected and current is reduced to ISB2Z. The duration of
SNOOZE MODE is dictated by the length of time ZZ is in a HIGH
state. After the device enters SNOOZE MODE, all inputs except ZZ
become gated inputs and are ignored.
DQ
5 pF
351Ω
ZZ is an asynchronous, active HIGH input that causes the device to
enter SNOOZE MODE. When ZZ becomes a logic HIGH, ISB2Z is
guaranteed after the setup time tZZ is met. Any READ or WRITE
operation pending when the device enters SNOOZE MODE is not
quaranteed to complete successfully. Therefore, SNOOZE MODE
must not be initiated until valid pending operations are completed.
Fig. 2 OUTPUT LOAD EQUIVALENT
SNOOZE MODE ELECTRICAL CHARACTERISTICS
DESCRIPTION
CONDITIONS
SYM
MIN
MAX
UNITS
NOTES
Current during SNOOZE MODE
10
mA
ZZ > VIH
ISB2Z
ZZ active to input ignored
ns
ns
ns
ns
1
1
1
1
tZZ
tRZZ
tZZI
tKC
ZZ inactive to input sampled
ZZ active to snooze current
ZZ inactive to exit snooze current
NOTE: 1. This parameter is sampled.
tKC
tKC
0
tRZZI
SNOOZE MODEWAVEFORM
CLK
ZZ
tRZZ
tZZ
tZZI
ISB2
ISUPPLY
tRZZI
ALL INPUTS*
* Except ZZ
Don’t Care
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AS5SS256K18
Rev. 2.0 12/00
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SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
READ TIMING
tKC
tKL
CLK
ADSP\
tKH
tADSS
tADSH tADSS
ADSC\
Deselect Cycle
(Note 4)
tAS
tADSH
ADDRESS
A1
A2
tAH
BWE\, GW\,
BWa\-BWb\
tCES
tCEH
tWS
tWH
CE\
(Note 2)
tAAS
tAAH
ADV\
OE\
Q
ADV\ suspends burst.
tOEQ
tOELZ tKQ
tKQX
Q(A2)
tKQHZ
tOEHZ
tKQLZ
High-Z
Q(A2+1)
Q(A2+2)
Q(A2+2)
Q(A2+3)
Q(A2)
Q(A2+1)
Q(A1)
(NOTE1)
Burst wraps around
to its initial state.
tKQ
SINGLE READ
BURST READ
READTIMING PARAMETERS
-8
-9
-10
-8
-9
-10
SYM MIN MAX MIN MAX MIN MAX UNITS
SYM MIN MAX MIN MAX MIN MAX UNITS
8.8
10
15
ns
66 MHz
ns
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1.8
1.8
1.8
1.8
1.8
0.5
0.5
0.5
0.5
0.5
2.0
2.0
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tKC
tAS
113
7.5
100
8.5
tKF
tADSS
tAAS
tWS
2.5
2.5
3.0
3.0
4.0
4.0
tKH
ns
tKL
10
ns
ns
ns
ns
ns
ns
ns
tKQ
tCES
tAH
1.5
1.5
3.0
3.0
3.0
3.0
tKQX
tKQLZ
tKQHZ
tOEQ
tOELZ
tOEHZ
tADSH
tAAH
tWH
4.2
4.2
5.0
5.0
5.0
5.0
0
0
0
tCEH
4.2
5.0
5.0
NOTE: 1. Q(A2) referes to output from address A2. Q(A2+1) refers to output from the next internal burst address following A2.
2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.
3. Timing is shown assuming that the device was not enabled before entering into this sequence.
4. Outputs are disabled tKQHZ after deselect.
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AS5SS256K18
Rev. 2.0 12/00
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SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
tKC
tKL
WRITETIMING
CLK
ADSP\
tKH
tADSS
ADSC\ extends burst.
tADSS
tADSH
ADSC\
tAS
tADSH
ADDRESS
A1
A2
A3
tWS tWH
tAH
BYTE WRITE signals are ignored
when ADSP\ is LOW.
BEW\,
BWa\ - BWb\
tWS tWH
(Note 5)
GW\
tCES tCEH
CE\
(NOTE 2)
t
AAS tAAH
ADV\
OE\
ADV\ suspends burst.
(Note 4)
(Note 3)
tDS tDH
D(A2+1)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
D(A1)
D
Q
D(A2)
High-Z
tOEHZ
(Note 1)
Extended
BURST WRITE
BURST READ
SINGLE WRITE
BURST WRITE
Don’t Care
WRITE TIMING PARAMETERS
-8
-9
-10
-8
-9
-10
SYM MIN MAX MIN MAX MIN MAX UNITS
SYM MIN MAX MIN MAX MIN MAX UNITS
tKC
8.8
10
15
ns
66 MHz
ns
tDS
1.5
1.5
0.5
1.8
1.8
0.5
0.5
0.5
0.5
0.5
0.5
2.0
2.0
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
tKF
113
4.2
100
5.0
tCES
tAH
tKH
2.5
2.5
3.0
3.0
4.0
4.0
tKL
ns
tADSH 0.5
tOEHZ
tAS
5.0
ns
ns
ns
ns
ns
tAAH
tWH
tDH
0.5
0.5
0.5
0.5
1.5
1.5
1.5
1.5
1.8
1.8
1.8
1.8
2.0
2.0
2.0
2.0
tADSS
tAAS
tWS
tCEH
NOTE: 1. D(A2) refers to output from address A2. D(A2+1) refres to output from the next internal burst address following A2.
2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.
3. OE\ must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data contention for the time period
prior to the byte write enable inputs being sampled.
4. ADV\ must be HIGH to permit a WRITE to the loaded address.
5. Full-width WRITE can be initiated by GW\ LOW; or GW\ HIGH and BWE\, BWa\ and BWb\ LOW.
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AS5SS256K18
Rev. 2.0 12/00
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SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
READ/WRITE TIMING6
tKC
tKL
CLK
ADSP\
tADSS
tKH
tADSH
ADSC\
tAS
ADDRESS
A2
A4
A5
A6
A3
A1
tAH
tWS
BWE\, GW\
BWa\ - BWb\
tCES
tWH
CE\
(Note 2)
tCEH
ADV\
OE\
tDS tDH
tOELZ
tKQ
D(A3)
D(A5)
D(A6)
D
Q
High-Z
tOEHZ
(NOTE1)
Q(A4+1)
Q(A4)
Q(A4+2)
Q(A4+3)
Q(A1)
Q(A2)
Back-to-Back
WRITEs
SINGLE WRITE
BURST READ
Back-to-Back READS
(NOTE 5)
Undefined
Don’t Care
READ/WRITE PARAMETERS
-8
-9
-10
-8
-9
-10
SYM MIN MAX MIN MAX MIN MAX UNITS
SYM MIN MAX MIN MAX MIN MAX UNITS
8.8
10
15
ns
66 MHz
ns
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
1.8
1.8
1.8
0.5
0.5
0.5
0.5
0.5
2.0
2.0
2.0
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
ns
ns
ns
ns
tKC
tWS
tDS
tCES
tAH
113
100
tKF
2.5
2.5
3.0
3.0
4.0
4.0
tKH
ns
tKL
7.5
3.5
8.5
4.2
10
ns
ns
ns
ns
ns
tKQ
tADSH
tWH
tDH
0
0
0
tOELZ
tOEHZ
tAS
5.0
1.5
1.5
1.8
1.8
2.0
2.0
tCEH
tADSS
NOTE: 1. Q(A4) refers to output from address A4. Q(A4+1) refers to output from the next internal burst address following A4.
2. CE2\ and CE2 have timing identical to CE\. On this diagram, when CE\ is LOW, CE2\ is LOW and CE2 is HIGH. When CE\ is HIGH, CE2\ is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP\, ADSC\, or ADV\ cycle is performed.
4. GW\ is HIGH.
5. Back-to-back READs may be controlled by either ADSP\ or ADSC\.
6. Timing is shown assuming that the device was not enabled before entering into this sequence.
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AS5SS256K18
Rev. 2.0 12/00
11
SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS
ASI Case #1001 (Package Designator DQ)
16.00 +0.20/-0.05
14.00 + 0.10
Pin #1 ID
DETAIL A
0.25
Gage Plane
0.10 +0.10/-0.05
1.00 TYP
0.62
See Detail A
1.40 + 0.05
0.10
0.15 +0.03/-0.02
1.50 + 0.10
0.32 +0.06/-0.10
0.65
0.60 + 0.15
NOTE: 1. All dimensions in Millimeters (MAX/MIN) or typical where noted.
2. Package width and length do not include mold protrusion; allowable mold protursion is 0.25mm per side.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS5SS256K18
Rev. 2.0 12/00
12
SSRAM
AS5SS256K18
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE: AS5SS256K18DQ-8/IT
Package
Device Number
Speed ns Process
Type
DQ
DQ
AS5SS256K18
AS5SS256K18
AS5SS256K18
-8
-9
IT only
/*
/*
DQ
-10
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Extended Temperature Range
-40oC to +85oC
-55oC to +125oC
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AS5SS256K18
Rev. 2.0 12/00
13
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