MT5C1005EC-55L/883C [AUSTIN]
256K x 4 SRAM SRAM MEMORY ARRAY; 256K ×4的SRAM SRAM存储器阵列
| 型号： | MT5C1005EC-55L/883C |
| 厂家： | 
AUSTIN SEMICONDUCTOR |
| 描述： | 256K x 4 SRAM SRAM MEMORY ARRAY |
| 文件： | 总13页 (文件大小：174K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
SRAM
MT5C1005
Austin Semiconductor, Inc.
256K x 4 SRAM
PIN ASSIGNMENT
(Top View)
SRAM MEMORY ARRAY
32-Pin LCC (EC)
32-Pin SOJ (DCJ)
AVAILABLE AS MILITARY
SPECIFICATIONS
•MIL-STD-883
28-Pin DIP (C)
(400 MIL)
A7
A8
A9
1
2
3
4
5
6
7
8
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Vcc
A6
A5
A2
A4
A3
A1
NC
NC
A7
A8
A9
1
2
3
4
5
6
7
8
9
28
27
26
25
24
23
22
21
20
19
18
17
16
15
Vcc
A6
A5
A4
A3
A2
A1
A0
NC
DQ4
DQ3
DQ2
DQ1
WE\
A12
A10
A11
A13
NC
A14
A15
A16
A17
NC
A10
A11
A12
A13
A14
A15
A16 10
A17 11
CE\ 12
OE\ 13
Vss 14
FEATURES
• High Speed: 20, 25, 35, and 45
• Battery Backup: 2V data retention
• Low power standby
9
10
11
12
13
14
15
16
A0
NC
DQ4
DQ3
DQ2
DQ1
WE\
• High-performance, low-power CMOS double-metal
process
• Single +5V (+10%) Power Supply
• Easy memory expansion with CE\ and OE\ options.
• All inputs and outputs are TTL compatible
CE\
OE\
Vss
32-Pin Flat Pack (F)
32-Pin LCC (ECW)
1
A7
A8
Vcc
A6
3 2
2
3 1
3
4 3 2 1 31 32 30
A9
A5
3 0
4
A12
A10
A11
A13
NC
A2
2 9
OPTIONS
• Timing
MARKING
5
A4
2 8
2 9
2 8
2 7
2 6
2 5
2 4
2 3
2 2
2 1
A2
A4
A3
A1
A0
NC
NC
NC
DQ4
A10
A11
A12
A13
A14
A15 1 0
A16 1 1
A17 1 2
CE\ 1 3
5
6
7
8
9
6
A3
2 7
7
A1
2 6
20ns access
25ns access
35ns access
45ns access
55ns access
70ns access
-20
8
NC
NC
A0
2 5
9
A14
A15
A16
A17
NC
2 4
-25
-35
-45
-55*
-70*
1 0
1 1
1 2
1 3
1 4
1 5
1 6
2 3
2 2
2 1
2 0
1 9
1 8
1 7
NC
DQ4
DQ3
DQ2
DQ1
WE\
CE\
OE\
Vss
14 15 16 17 18 19 20
• Package(s)
Ceramic DIP (400 mil)
C
No. 109
Ceramic Quad LCC (contact factory)ECW
No. 206
No. 207
No. 303
No. 501
GENERAL DESCRIPTION
Ceramic LCC
Ceramic Flatpack
Ceramic SOJ
EC
F
DCJ
The Austin Semiconductor SRAM family employs
high-speed, low power CMOS designs fabricated using double-
layer metal, double-layer polysilicon technology.
For flexibility in high-speed memory applications, ASI
offers chip enable (CE\) and output enable (OE\) capability.
These enhancements can place the outputs in High-Z for addi-
tional flexibility in system design. Writing to these devices is
accomplished when write enable (WE\) and CE\ inputs are both
LOW. Reading is accomplished when WE\ remains HIGH while
CE\ and OE\ go LOW. The devices offer a reduced power
standby mode when disabled. This allows system designs to
achieve low standby power requirements.
• Operating Temperature Ranges
Industrial (-40oC to +85oC)
IT
XT
Military (-55oC to +125oC)
• 2V data retention/low power
L
*Electrical characteristics identical to those provided for the
45ns access devices.
All devices operation from a single +5V power supply
and all inputs and outputs are fully TTL compatible.
For more products and information
please visit our web site at
www.austinsemiconductor.com
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1005
Rev. 3.1 1/01
1
SRAM
MT5C1005
Austin Semiconductor, Inc.
FUNCTIONAL BLOCK DIAGRAM
VCC
GND
A
A
A
A
A
A
A
A
A
A
DQ4
262,144 x 4-BIT
MEMORY ARRAY
DQ1
CE\
COLUMN DECODER
OE\
WE\
A
A
A
A
A
A
A
A
POWER
DOWN
TRUTHTABLE
MODE
STANDBY
READ
READ
WRITE
OE\ CE\ WE\
DQ
POWER
X
L
H
L
L
L
X
H
H
L
HIGH-Z STANDBY
Q
HIGH-Z
D
ACTIVE
ACTIVE
ACTIVE
H
X
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1005
Rev. 3.1 1/01
2
SRAM
MT5C1005
Austin Semiconductor, Inc.
*Stresses greater than those listed under "Absolute Maximum
Ratings" may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
these or any other conditions above those indicated in the
operation section of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods
may affect reliability.
ABSOLUTEMAXIMUMRATINGS*
Supply Voltage Range (Vcc)................................-.5V to +7.0V
Storage Temperature......................................-65°C to +150°C
Voltage on any Pin Relative to Vss................-.5V to Vcc+.5V
Max Junction Temperature............................................+175°C
Lead Temperature (soldering 10 seconds)..................+260oC
Power Dissipation ...............................................................1 W
ELECTRICAL CHARACTERISTICS AND RECOMMENDED DC OPERATING CONDITIONS
(-55oC < TC < 125oC; VCC = 5V +10%)
DESCRIPTION
CONDITIONS
SYM MIN
MAX
UNITS
NOTES
Input High (Logic 1) Voltage
2.2
-0.5
-10
V
1
VIH
VIL
ILI
VCC+0.5
Input Low (Logic 0) Voltage
Input Leakage Current
0.8
10
V
1
µA
0V<VIN<VCC
Output(s) disabled
0V<VOUT<VCC
Output Leakage Current
ILO
-10
2.4
10
µA
Output High Voltage
Output Low Voltage
V
V
1
1
I
OH = -4.0mA
OL = 8.0mA
VOH
VOL
0.4
I
MAX
PARAMETER
CONDITIONS
SYM
-20
-25
-35
-45 UNITS NOTES
WE\, CE\ < VIL; VCC = MAX
Output Open
Power Supply
Current: Operating
180
180
180
25
180
25
mA
mA
mA
3
I
cc
CE\ > VIH; All Other Inputs
< VIL or > VIH, VCC = MAX
Power Supply
Current: Standby
25
16
25
16
ISBT2
CE\ > VCC -0.2V; VCC = MAX
VIL < VSS +0.2V
ISBC
16
16
VIH > VCC -0.2V; f = 0 Hz*
* “L” version only.
CAPACITANCE
PARAMETER
CONDITIONS
VIN = 0V,
SYM
MAX
UNITS
NOTES
Input Capacitance
12
14
pF
4
CI
TA = 25°C, f = 1MHz
VCC = 5V
Output Capacitance (DQ1-DQ4)
pF
4
CO
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1005
Rev. 3.1 1/01
3
SRAM
MT5C1005
Austin Semiconductor, Inc.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 5) (-55oC < TC < 125oC;VCC = 5V +10%)
-20
-25
-35
-45
DESCRIPTION
READ CYCLE
MIN MAX MIN MAX MIN MAX MIN MAX UNITS NOTES
SYMBOL
tRC
tAA
tACE
tOH
READ cycle time
20
25
35
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Address access time
20
20
25
25
35
35
45
45
Chip Enable access time
Output hold from address change
3
3
3
3
3
3
3
3
tLZCE
tHZCE
tPU
4, 6, 7
Chip Enable to output in Low-Z
Chip disable to output in High-Z
Chip Enable to power-up time
Chip disable to power-down time
Output Enable access time
Output Enable to output in Low-Z
Output disable to output in High-Z
WRITE CYCLE
10
12
20
25
4, 6, 7
0
0
0
0
0
0
0
0
4
4
tPD
20
8
25
10
35
20
45
25
tAOE
tLZOE
tHZOE
4, 6, 7
4, 6, 7
8
10
20
25
tWC
tCW
tAW
WRITE cycle time
20
15
15
0
25
20
20
0
35
30
30
0
45
35
35
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Chip Enable to end of write
Address valid to end of write
Address setup time
tAS
tAH
Address hold from end of write
WRITE pulse width
0
0
0
0
tWP
15
12
0
20
15
0
30
20
0
35
25
0
tDS
Data setup time
tDH
Data hold time
tLZWE
tHZWE
Write disable to output in Low-Z
Write Enable to output in High-Z
3
3
3
3
4, 6, 7
4, 6, 7
0
8
0
10
0
15
0
20
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1005
Rev. 3.1 1/01
4
SRAM
MT5C1005
Austin Semiconductor, Inc.
ACTEST CONDITIONS
Input pulse levels ................................... Vss to 3.0V
Input rise and fall times ....................................... 5ns
Input timing reference levels ............................. 1.5V
Output reference levels ..................................... 1.5V
Output load .............................. See Figures 1 and 2
167Ω
167Ω
Q
Q
VTH =1.73V
VTH =1.73V
5pF
30pF
Fig. 1 Output Load
Equivalent
Fig. 2 Output Load
Equivalent
7. At any given temperature and voltage condition,
NOTES
t
tHZCE is less than tLZCE, and HZWE is less than
1. All voltages referenced to VSS (GND).
2. -3V for pulse width < 20ns
tLZWE and tHZOE is less than tLZOE.
8. WE\ is HIGH for READ cycle.
3. ICC is dependent on output loading and cycle rates.
The specified value applies with the outputs
9. Device is continuously selected. Chip enables and
output enables are held in their active state.
10. Address valid prior to, or coincident with, latest
occurring chip enable.
unloaded, and f =
1
Hz.
tRC (MIN)
4. This parameter is guaranteed but not tested.
5. Test conditions as specified with the output loading
as shown in Fig. 1 unless otherwise noted.
t
11. RC = Read Cycle Time.
12. Chip enable (CE\) and write enable (WE\) can initiate and
terminate a WRITE cycle.
6. Minimum of 5pF for tEHQZ, tOHQZ, tELQX, tOLQX
and tWHQX
,
.
DATA RETENTION ELECTRICAL CHARACTERISTICS (L Version Only)
DESCRIPTION
CONDITIONS
SYM
MIN
MAX UNITS NOTES
2
V
VCC for Retention Data
VDR
CE\ > (VCC-0.2V)
and
Data Retention Current
VCC = 2V
ICCDR
5
mA
VIN > (VCC-0.2V)
or < 0.2V
Chip Deselect to Data
Retention Time
tCDR
tR
0
--
ns
ns
4
Operation Recovery Time
4, 11
tRC
LOWVcc DATA RETENTIONWAVEFORM
DATA RETENTION MODE
VCC
CE\
4.5V
4.5V
VDR > 2V
t
tCDR
R
VIH
VIL
VDR
DON’T CARE
UNDEFINED
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1005
Rev. 3.1 1/01
5
SRAM
MT5C1005
Austin Semiconductor, Inc.
READ CYCLE NO. 1 8, 9
t
RC
VALID
ADDRESS
DQ
t
AA
tOH
PREVIOUS DATA VALID
DATA VALID
READ CYCLE NO. 2 7, 8, 10
tR
C
CE\
tA
OE
tHZOE
tLZOE
OE\
DQ
Icc
tLZCE
tHZCE
t
E
ACE
DATA VALID
t
PU
tP
D
DON’T CARE
UNDEFINED
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1005
Rev. 3.1 1/01
6
SRAM
MT5C1005
Austin Semiconductor, Inc.
WRITE CYCLE NO. 1 12
(Chip Enabled Controlled)
tWC
ADDRESS
tA
W
tAH
tAS
tCW
CE\
t
WP
WE\
tDH
t
DS
DATA VAILD
D
Q
HIGH Z
7, 12
WRITE CYCLE NO. 2
(Write Enabled Controlled)
tW
C
ADDRESS
tAW
tAW
tAH
tCW
CE\
tAS
t
WP
WE\
tDS
tDH
tDH
D
Q
DATA VALID
HIGH-Z
DON’T CARE
UNDEFINED
NOTE: Output enable (OE\) is inactive (HIGH).
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1005
Rev. 3.1 1/01
7
SRAM
MT5C1005
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #109 (Package Designator C)
D
A
Q
L
Pin 1
b
e
b1
E
c
E1
ASI PACKAGE SPECIFICATIONS
SYMBOL
MIN
MAX
0.110
0.020
0.060
0.012
1.414
0.405
0.410
0.110
0.175
0.060
A
b
b1
c
D
E
E1
e
0.090
0.016
0.040
0.008
1.386
0.385
0.390
0.090
0.125
0.040
L
Q
*All measurements are in inches.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1005
Rev. 3.1 1/01
8
SRAM
MT5C1005
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #206 (Package Designator ECW)
E1
A
L1
e
D1
D
b2
L
b1
b
E
ASI PACKAGE SPECIFICATIONS
SYMBOL
MIN
MAX
0.093
0.028
0.014
0.066
0.758
0.405
0.458
0.305
0.055
0.055
0.093
A
b
b1
b2
D
D1
E
E1
e
0.077
0.022
0.004
0.054
0.742
0.395
0.442
0.295
0.045
0.045
0.077
L
L1
*All measurements are in inches.
MT5C1005
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
Rev. 3.1 1/01
9
SRAM
MT5C1005
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #207 (Package Designator EC)
A
L1
D
L
b1
e
b
E
b2
ASI PACKAGE SPECIFICATIONS
SYMBOL
MIN
MAX
0.100
0.028
0.014
0.066
0.835
0.408
0.055
0.080
0.110
A
b
b1
b2
D
E
e
L
L1
0.080
0.022
0.004
0.054
0.815
0.392
0.045
0.070
0.090
*All measurements are in inches.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1005
Rev. 3.1 1/01
10
SRAM
MT5C1005
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #303 (Package Designator F)
E
L
Pin 1
Index
e
32
1
D
b
D1
17
16
Bottom View
Top View
A
c
Q
E2
ASI PACKAGE SPECIFICATIONS
SYMBOL
MIN
---
MAX
0.125
0.019
0.006
0.828
0.755
0.415
0.336
0.055
0.310
0.033
A
b
c
D
D1
E
E2
e
0.015
0.004
0.812
0.745
0.405
0.324
0.045
0.290
0.027
L
Q
*All measurements are in inches.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1005
Rev. 3.1 1/01
11
SRAM
MT5C1005
Austin Semiconductor, Inc.
MECHANICAL DEFINITIONS*
ASI Case #501 (Package Designator DCJ)
A
D
e
D1
R
E2
E1
b
E
A2
ASI PACKAGE SPECIFICATIONS
SYMBOL
MIN
MAX
0.153
0.036
0.019
0.828
0.755
0.415
0.055
0.445
0.380
0.040
A
A2
b
D
D1
E
0.135
0.026
0.015
0.812
0.740
0.405
0.045
0.435
0.360
0.030
e
E1
E2
R
*All measurements are in inches.
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1005
Rev. 3.1 1/01
12
SRAM
MT5C1005
Austin Semiconductor, Inc.
ORDERING INFORMATION
EXAMPLE: MT5C1005EC-45/XT
EXAMPLE: MT5C1005C-20L/IT
Device
Number
Package Speed
Device
Number
Package Speed
Options** Process
Options** Process
Type
ns
Type
EC
ECW
EC
ns
MT5C1005
MT5C1005
MT5C1005
MT5C1005
MT5C1005
MT5C1005
C
-20
L
L
L
L
L
L
/*
/*
/*
/*
/*
/*
MT5C1005
MT5C1005
MT5C1005
MT5C1005
MT5C1005
MT5C1005
-20
L
L
L
L
L
L
/*
/*
/*
/*
/*
/*
C
C
C
C
C
-25
-35
-40
-55
-70
-25
-35
-40
-55
-70
ECW
EC
ECW
EC
ECW
EC
ECW
EC
ECW
EXAMPLE: MT5C1005DCJ-70/XT
EXAMPLE: MT5C1005F-25L/883C
Device
Number
Package Speed
Device
Number
Package Speed
Options** Process
Options** Process
Type
ns
-20
-25
-35
-40
-55
-70
Type
DCJ
DCJ
DCJ
DCJ
DCJ
DCJ
ns
-20
-25
-35
-40
-55
-70
MT5C1005
MT5C1005
MT5C1005
MT5C1005
MT5C1005
MT5C1005
F
F
F
F
F
F
L
L
L
L
L
L
/*
/*
/*
/*
/*
/*
MT5C1005
MT5C1005
MT5C1005
MT5C1005
MT5C1005
MT5C1005
L
L
L
L
L
L
/*
/*
/*
/*
/*
/*
*AVAILABLE PROCESSES
IT = Industrial Temperature Range
XT = Extended Temperature Range
883C = Full Military Processing
-40oC to +85oC
-55oC to +125oC
-55oC to +125oC
** OPTIONS
L = 2V Data Retention/Low Power
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
MT5C1005
Rev. 3.1 1/01
13
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