5962-8876903FC [AVAGO]
4 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 5Mbps, HERMETIC SEALED, FP-16;
| 型号： | 5962-8876903FC |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | 4 CHANNEL LOGIC OUTPUT OPTOCOUPLER, 5Mbps, HERMETIC SEALED, FP-16 输出元件 光电 |
| 文件： | 总14页 (文件大小：258K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCPL-520x, HCPL-523x, HCPL-623x, HCPL-625x,
5962-88768 and 5962-88769
Hermetically Sealed Low IF, Wide VCC, Logic Gate Optocouplers
Data Sheet
Description
Features
•ꢀ DualꢀMarkedꢀwithꢀDeviceꢀPartꢀNumberꢀandꢀDSCCꢀ
StandardꢀMicrocircuitꢀDrawing
•ꢀ Manu�acturedꢀandꢀꢁeꢂtedꢀonꢀaꢀMꢃꢄꢅPꢆꢇꢅꢈꢉꢊꢈꢀCertiꢅ
ꢁheꢂeꢀunitꢂꢀareꢀꢂingleꢌꢀdualꢀandꢀquadꢀchannelꢌꢀhermetiꢅ
callꢏꢀꢂealedꢀoꢘtocouꢘlerꢂ.ꢀꢁheꢀꢘroductꢂꢀareꢀcaꢘableꢀo�ꢀ
oꢘerationꢀandꢀꢂtorageꢀoverꢀtheꢀ�ullꢀmilitarꢏꢀtemꢘeratureꢀ
rangeꢀandꢀcanꢀbeꢀꢘurchaꢂedꢀaꢂꢀeitherꢀꢂtandardꢀꢘroductꢀ
fiedꢀꢄine
orꢀ withꢀ �ullꢀ MꢃꢄꢅPꢆꢇꢅꢈꢉꢊꢈꢀ Claꢂꢂꢀ ꢄevelꢀ ꢍꢀ orꢀ ꢎꢀ teꢂtingꢀ •ꢀ ꢋMꢄꢅꢈꢉꢊꢈꢌꢀClaꢂꢂꢀꢍꢀandꢀꢎ
orꢀ�romꢀtheꢀaꢘꢘroꢘriateꢀDSCCꢀDrawing.ꢀꢞllꢀdeviceꢂꢀareꢀ
manu�acturedꢀandꢀteꢂtedꢀonꢀaꢀMꢃꢄꢅPꢆꢇꢅꢈꢉꢊꢈꢀcertifiedꢀ
lineꢀandꢀareꢀincludedꢀinꢀtheꢀDSCCꢀꢋualifiedꢀManu�acturꢅ
erꢂꢀꢄiꢂtꢀꢋMꢄꢅꢈꢉꢊꢈꢀ�orꢀꢍꢏbridꢀMicrocircuitꢂ.
•ꢀ ꢇourꢀꢍermeticallꢏꢀSealedꢀPackageꢀConfigurationꢂ
•ꢀ Per�ormanceꢀꢐuaranteedꢀoverꢀꢅꢊꢊꢑCꢀtoꢀꢒꢓꢔꢊꢑC
•ꢀ ꢕideꢀꢖ ꢀꢆangeꢀ(.ꢊꢀtoꢀꢔ0ꢀꢖ)
CC
•ꢀ ꢈꢊ0ꢀnꢂꢀMaꢗimumꢀProꢘagationꢀDelaꢏ
•ꢀ CMꢆꢙꢀꢚꢀꢓ0ꢌ000ꢀꢖꢛꢜꢂꢀꢁꢏꢘical
•ꢀ ꢓꢊ00ꢀꢖdcꢀꢕithꢂtandꢀꢁeꢂtꢀꢖoltage
•ꢀ ꢁhreeꢀStateꢀꢝutꢘutꢀꢞvailable
•ꢀ ꢍighꢀꢆadiationꢀꢃmmunitꢏ
Eachꢀchannelꢀcontainꢂꢀanꢀꢞlꢐaꢞꢂꢀlightꢀemittingꢀdiodeꢀ
whichꢀ iꢂꢀ oꢘticallꢏꢀ couꢘledꢀ toꢀ anꢀ integratedꢀ highꢀ gainꢀ
ꢘhotonꢀdetector.ꢀꢁheꢀdetectorꢀhaꢂꢀaꢀthreꢂholdꢀwithꢀhꢏꢂꢅ
tereꢂiꢂꢀwhichꢀꢘrovideꢂꢀdifferentialꢀmodeꢀnoiꢂeꢀimmunitꢏꢀ
andꢀ eliminateꢂꢀ theꢀ ꢘotentialꢀ �orꢀ outꢘutꢀ ꢂignalꢀ chatter.ꢀ
ꢁheꢀdetectorꢀinꢀtheꢀꢂingleꢀchannelꢀunitꢂꢀhaꢂꢀaꢀtriꢅꢂtateꢀ •ꢀ ꢍCPꢄꢅꢔꢔ00ꢛꢈꢓꢀꢇunctionꢀComꢘatibilitꢏ
outꢘutꢀꢂtageꢀwhichꢀallowꢂꢀ�orꢀdirectꢀconnectionꢀtoꢀdataꢀ
buꢂeꢂ.ꢀꢁheꢀoutꢘutꢀiꢂꢀnoninverting.ꢀꢁheꢀdetectorꢀꢃCꢀhaꢂꢀ
anꢀinternalꢀꢂhieldꢀthatꢀꢘrovideꢂꢀaꢀguaranteedꢀcommonꢀ
modeꢀtranꢂientꢀimmunitꢏꢀo�ꢀuꢘꢀtoꢀꢓ0ꢌ000ꢀꢖꢛꢜꢂ.ꢀꢃmꢘrovedꢀ
ꢘowerꢀꢂuꢘꢘlꢏꢀrejectionꢀeliminateꢂꢀtheꢀneedꢀ�orꢀꢂꢘecialꢀ
ꢘowerꢀꢂuꢘꢘlꢏꢀbꢏꢘaꢂꢂꢀꢘrecautionꢂ.
•ꢀ ꢆeliabilitꢏꢀDataꢀꢞvailable
•ꢀ ComꢘatibleꢀwithꢀꢄSꢁꢁꢄꢌꢀꢁꢁꢄꢌꢀandꢀCMꢝSꢀꢄogic
Applications
•ꢀ MilitarꢏꢀandꢀSꢘace
•ꢀ ꢍighꢀꢆeliabilitꢏꢀSꢏꢂtemꢂ
•ꢀ ꢁranꢂꢘortationꢀandꢀꢄi�eꢀCriticalꢀSꢏꢂtemꢂ
•ꢀ ꢍighꢀSꢘeedꢀꢄineꢀꢆeceiver
•ꢀ ꢃꢂolatedꢀBuꢂꢀDriverꢀ(SingleꢀChannel)
•ꢀ Pulꢂeꢀꢁranꢂ�ormerꢀꢆeꢘlacement
•ꢀ ꢐroundꢀꢄooꢘꢀElimination
•ꢀ ꢍarꢂhꢀꢃnduꢂtrialꢀEnvironmentꢂ
•ꢀ ComꢘuterꢅPeriꢘheralꢀꢃnter�aceꢂ
Noteꢙꢀꢞꢀ0.ꢓꢀmꢇꢀbꢏꢘaꢂꢂꢀcaꢘacitorꢀmuꢂtꢀbeꢀconnectedꢀbetweenꢀꢖ ꢀandꢀꢐNDꢀꢘinꢂ.
CC
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Functional Diagram
MultiꢘleꢀChannelꢀDeviceꢂꢀꢞvailable
Truth Tables
(Poꢂitiveꢀꢄogic)
V
CC
Multichannel Devices
Input
V
V
O
E
Output
On (H)
Off (L)
H
L
GND
Packageꢀꢂtꢏleꢂꢀ�orꢀtheꢂeꢀꢘartꢂꢀareꢀꢉꢀꢘinꢀDꢃPꢀthroughꢀholeꢀ
(caꢂeꢀoutlineꢀP)ꢌꢀꢓ6ꢀꢘinꢀDꢃPꢀflatꢀꢘackꢀ(caꢂeꢀoutlineꢀꢇ)ꢌꢀandꢀ
leadleꢂꢂꢀceramicꢀchiꢘꢀcarrierꢀ(caꢂeꢀoutlineꢀꢔ).ꢀDeviceꢂꢀmaꢏꢀ
beꢀꢘurchaꢂedꢀwithꢀaꢀvarietꢏꢀo�ꢀleadꢀbendꢀandꢀꢘlatingꢀ
oꢘtionꢂꢌꢀꢂeeꢀSelectionꢀꢐuideꢀꢁableꢀ�orꢀdetailꢂ.ꢀStandardꢀ
MicrocircuitꢀDrawingꢀ(SMD)ꢀꢘartꢂꢀareꢀavailableꢀ�orꢀeachꢀ
ꢘackageꢀandꢀleadꢀꢂtꢏle.
Single Channel Devices
Input
On (H)
Off (L)
On (H)
Off (L)
Enable
Output
H
H
L
Z
Z
H
L
Becauꢂeꢀtheꢀꢂameꢀelectricalꢀdieꢀ(emitterꢂꢀandꢀdetectorꢂ)ꢀ
areꢀuꢂedꢀ�orꢀeachꢀchannelꢀo�ꢀeachꢀdeviceꢀliꢂtedꢀinꢀthiꢂꢀ
dataꢀ ꢂheetꢌꢀ abꢂoluteꢀ maꢗimumꢀ ratingꢂꢌꢀ recommendedꢀ
oꢘeratingꢀconditionꢂꢌꢀelectricalꢀꢂꢘecificationꢂꢌꢀandꢀꢘer�orꢅ
manceꢀcharacteriꢂticꢂꢀꢂhownꢀinꢀtheꢀfigureꢂꢀareꢀidenticalꢀ
�orꢀallꢀꢘartꢂ.ꢀꢝccaꢂionalꢀeꢗceꢘtionꢂꢀeꢗiꢂtꢀdueꢀtoꢀꢘackageꢀ
variationꢂꢀandꢀlimitationꢂꢀandꢀareꢀaꢂꢀnoted.ꢀꢞdditionallꢏꢌꢀ
theꢀꢂameꢀꢘackageꢀaꢂꢂemblꢏꢀꢘroceꢂꢂeꢂꢀandꢀmaterialꢂꢀareꢀ
uꢂedꢀinꢀallꢀdeviceꢂ.ꢀꢁheꢂeꢀꢂimilaritieꢂꢀgiveꢀjuꢂtificationꢀ�orꢀ
theꢀuꢂeꢀo�ꢀdataꢀobtainedꢀ�romꢀoneꢀꢘartꢀtoꢀreꢘreꢂentꢀotherꢀ
ꢘart’ꢂꢀꢘer�ormanceꢀ�orꢀdieꢀrelatedꢀreliabilitꢏꢀandꢀcertainꢀ
limitedꢀradiationꢀteꢂtꢀreꢂultꢂ.
L
Functional Diagrams
8 Pin DIP
Through Hole
1 Channel
8 Pin DIP
Through Hole
2 Channels
16 Pin Flat Pack
20 Pad LCCC
Surface Mount
2 Channels
Unformed Leads
4 Channels
15
V
8
7
6
5
V
8
7
6
5
1
2
3
4
1
2
3
4
CC
CC
16
15
14
13
1
2
3
4
V
CC2
V
O1
V
V
O
CC
19
13
12
V
O2
O1
V
20
O1
V
GND
2
O2
V
V
V
O2
O3
O4
V
E
V
CC1
2
3
10
V
7
12
11
5
6
7
8
GND
GND
GND
1
GND 10
9
8
NoteꢙꢀMultichannelꢀDꢃPꢀandꢀflatꢀꢘackꢀdeviceꢂꢀhaveꢀcommonꢀꢖ ꢀandꢀground.ꢀSingleꢀchannelꢀDꢃPꢀhaꢂꢀanꢀenableꢀꢘinꢀ6.ꢀꢄCCCꢀ(leadleꢂꢂꢀceramicꢀchiꢘꢀ
CC
carrier)ꢀꢘackageꢀhaꢂꢀiꢂolatedꢀchannelꢂꢀwithꢀꢂeꢘarateꢀꢖ ꢀandꢀgroundꢀconnectionꢂ.
CC
ꢀ
Selection Guide–Package Styles and Lead Configuration Options
Package
8 Pin DIP
Through Hole
1
8 Pin DIP
Through Hole
2
16 Pin Flat Pack
Unformed Leads
4
20 Pad LCCC
Surface Mount
2
Lead Style
Channels
Common Channel Wiring
None
V
CC
GND
V
CC
GND
None
Avago Technologies’ Part Numbers and Options
Commercial
HCPL-5200
HCPL-5201
HCPL-520K
Gold Plate
Option 200
Option 100
Option 300
HCPL-5230
HCPL-5231
HCPL-523K
Gold Plate
Option 200
Option 100
Option 300
HCPL-6250
HCPL-6251
HCPL-625K
Gold Plate
HCPL-6230
HCPL-6231
HCPL-623K
Solder Pads *
MIL-PRF-38534 Class H
MIL-PRF-38534 Class K
Standard Lead Finish
Solder Dipped*
Butt Joint/Gold Plate
Gull Wing/Soldered*
Class H SMD Part Number
Prescript for all below
Either Gold or Soldered
Gold Plate
5962-
5962-
5962-
5962-
8876801PX
8876801PC
8876801PA
8876801YC
8876801YA
8876801XA
8876901PX
8876901PC
8876901PA
8876901YC
8876901YA
8876901XA
8876903FX
8876903FC
88769022X
Solder Dipped*
88769022A
Butt Joint/Gold Plate
Butt Joint/Soldered*
Gull Wing/Soldered*
Class K SMD Part Number
Prescript for all below
5962-
5962-
5962-
5962-
Either Gold or Soldered
Gold Plate
8876802KPX
8876802KPC
8876802KPA
8876802KYC
8876802KYA
8876802KXA
8876904KPX
8876904KPC
8876904KPA
8876904KYC
8876904KYA
8876904KXA
8876906KFX
8876906KFC
8876905K2X
Solder Dipped*
8876905K2A
Butt Joint/Gold Plate
Butt Joint/Soldered*
Gull Wing/Soldered*
*ꢀSolderꢀcontainꢂꢀlead
ꢁ
Outline Drawings
8 Pin DIP Through Hole, 1 and 2 Channel
9.40 (0.370)
9.91 (0.390)
8.13 (0.320)
MAX.
0.76 (0.030)
1.27 (0.050)
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
3.81 (0.150)
0.20 (0.008)
0.33 (0.013)
MIN.
7.36 (0.290)
7.87 (0.310)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
16 Pin Flat Pack, 4 Channels
2.29 (0.090)
MAX.
7.24 (0.285)
6.99 (0.275)
1.27 (0.050)
REF.
11.13 (0.438)
10.72 (0.422)
0.46 (0.018)
0.36 (0.014)
8.13 (0.320)
MAX.
2.85 (0.112)
MAX.
0.88 (0.0345)
MIN.
9.02 (0.355)
8.76 (0.345)
0.31 (0.012)
0.23 (0.009)
5.23
(0.206)
MAX.
0.89 (0.035)
0.69 (0.027)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
ꢂ
20 Terminal LCCC Surface Mount, 2 Channels
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
1.02 (0.040) (3 PLCS)
2.03 (0.080)
1.14 (0.045)
1.40 (0.055)
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
TERMINAL 1 IDENTIFIER
2.16 (0.085)
METALIZED
CASTILLATIONS (20 PLCS)
1.78 (0.070)
2.03 (0.080)
0.64
(0.025)
(20 PLCS)
0.51 (0.020)
1.52 (0.060)
2.03 (0.080)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
SOLDER THICKNESS 0.127 (0.005) MAX.
Leaded Device Marking
AVAGO Designator
A QYYWWZ
XXXXXX
XXXXXXX
XXX XXX
50434
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
AVAGO P/N
DSCC SMD*
DSCC SMD*
PIN ONE/
COUNTRY OF MFR.
AVAGO FSCN*
ESD IDENT
*QUALIFIED PARTS ONLY
Leadless Device Marking
AVAGO Designator
AVAGO P/N
A QYYWWZ
XXXXXX
XXXX
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD*
PIN ONE/
ESD IDENT
COUNTRY OF MFR.
XXXXXX
XXX 50434
DSCC SMD*
AVAGO FSCN*
*QUALIFIED PARTS ONLY
ꢃ
Hermetic Optocoupler Options
Option
Description
100
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly.
This option is available on commercial and hi-rel product in 8 pin DIP (see drawings below for details).
4.32 (0.170)
MAX.
0.51 (0.020)
1.14 (0.045)
MIN.
0.20 (0.008)
0.33 (0.013)
1.40 (0.055)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
200
300
Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in 8 pin DIP.
DSCC Drawing part numbers contain provisions for lead finish. All leadless chip carrier devices are delivered with solder
dipped terminals as a standard feature.
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is available on commercial
and hi-rel product in 8 pin DIP (see drawings below for details). This option has solder dipped leads.
4.57 (0.180)
MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MIN.
5˚ MAX.
1.40 (0.055)
1.65 (0.065)
9.65 (0.380)
9.91 (0.390)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
NOTE: DIMENSIONS IN MILLIMETERS (INCHES).
Note: Solderꢀcontainꢂꢀlead
ꢄ
Absolute Maximum Ratings
Parameter
Symbol
Min.
Max.
Units
Storageꢀꢁemꢘeratureꢀꢆange
ꢝꢘeratingꢀꢞmbientꢀꢁemꢘerature
Junctionꢀꢁemꢘerature
ꢁS
ꢅ6ꢊꢑ
ꢒꢓꢊ0ꢑ
C
ꢁꢞ
ꢁJ
ꢅꢊꢊꢑ
ꢒꢓꢔꢊꢑ
ꢒꢓ7ꢊꢑ
ꢒꢓ70ꢑ
C
C
C
Caꢂeꢀꢁemꢘerature
ꢁC
ꢄeadꢀSolderꢀꢁemꢘerature
(ꢓ.6ꢀmmꢀbelowꢀꢂeatingꢀꢘlane)
ꢔ60ꢑꢀ�orꢀꢓ0ꢀꢂ
C
ꢞverageꢀꢇorwardꢀCurrentꢌꢀeachꢀchannel
PeakꢀꢃnꢘutꢀCurrentꢌꢀeachꢀchannel
ꢆeverꢂeꢀꢃnꢘutꢀꢖoltageꢌꢀeachꢀchannel
ꢞverageꢀꢝutꢘutꢀCurrentꢌꢀeachꢀchannel
Suꢘꢘlꢏꢀꢖoltage
ꢃꢇꢀꢞꢖꢐ
ꢃꢇPꢎ
ꢖꢆ
ꢉ
ꢔ0ꢀꢀ[ꢓ]
ꢈ
mꢞ
mꢞ
ꢖ
ꢃꢝ
ꢓꢊ
mꢞ
ꢖ
ꢖCC
ꢖꢝ
0.0
ꢔ0
ꢝutꢘutꢀꢖoltageꢌꢀeachꢀchannel
PackageꢀPowerꢀDiꢂꢂiꢘationꢌꢀeachꢀchannel
Single Channel Product Only
ꢅ0.ꢈ
ꢔ0
ꢖ
PD
ꢔ00
mꢕ
ꢁriꢅStateꢀEnableꢀꢖoltage
ꢖE
ꢅ0.ꢈ
ꢔ0
ꢖ
8 Pin Ceramic DIP Single Channel Schematic
Noteꢀenableꢀꢘinꢀ6.ꢀꢞnꢀeꢗternalꢀ0.0ꢓꢀꢜꢇꢀtoꢀ0.ꢓꢀꢜꢇꢀbꢏꢘaꢂꢂꢀcaꢘacitorꢀiꢂꢀrecommendedꢀbetweenꢀꢖ ꢀandꢀgroundꢀ�orꢀeachꢀꢘackageꢀtꢏꢘe.
CC
ESD Classification
(MIL-STD-883, Method 3015)
ꢍCPꢄꢅꢊꢔ00ꢛ0ꢓꢛ0ꢎꢀandꢀꢍCPꢄꢅ6ꢔꢈ0ꢛꢈꢓꢛꢈꢎ
ꢍCPꢄꢅꢊꢔꢈ0ꢛꢈꢓꢛꢈꢎꢀandꢀꢍCPꢄꢅ6ꢔꢊ0ꢛꢊꢓꢛꢊꢎ
(D)ꢌꢀClaꢂꢂꢀꢓ
(Dot)ꢌꢀClaꢂꢂꢀꢈ
Recommended Operating Conditions
Parameter
Symbol
ꢖCC
ꢃꢇꢍ
Min.
.ꢊ
ꢔ
Max.
ꢔ0
ꢉ
Units
ꢖ
PowerꢀSuꢘꢘlꢏꢀꢖoltage
ꢃnꢘutꢀCurrentꢌꢀꢍighꢀꢄevelꢌꢀeachꢀchannel
ꢃnꢘutꢀꢖoltageꢌꢀꢄowꢀꢄevelꢌꢀeachꢀchannel
ꢇanꢀꢝutꢀ(ꢁꢁꢄꢀꢄoad)ꢌꢀeachꢀchannel
Single Channel Product Only
mꢞ
ꢖ
ꢖꢇꢄ
0
0.ꢉ
N
ꢍighꢀꢄevelꢀEnableꢀꢖoltage
ꢖEꢍ
ꢖEꢄ
ꢔ.0
0
ꢔ0
ꢖ
ꢖ
ꢄowꢀꢄevelꢀEnableꢀꢖoltage
0.ꢉ
ꢅ
Electrical Characteristics
ꢁ ꢀ=ꢀꢅꢊꢊꢑCꢀtoꢀꢒꢓꢔꢊꢑCꢌꢀ.ꢊꢀꢖꢀ≤ꢀꢖ ꢀ≤ꢀꢔ0ꢀꢖꢌꢀꢔꢀmꢞꢀ≤ꢀꢃ
ꢞ
ꢀ≤ꢀꢉꢀmꢞꢌꢀ0ꢀꢖꢀ≤ꢀꢖ ꢀ≤ꢀ0.ꢉꢀꢖꢌꢀunleꢂꢂꢀotherwiꢂeꢀꢂꢘecified.
ꢇ(ꢝN) ꢇ(ꢝꢇꢇ)
CC
Limits
Group A,
Symbol Sub-groups[11]
Parameter
Test Conditions
Min.
Typ.*
Max. Units Fig. Notes
ꢄogicꢀꢄowꢀꢝutꢘutꢀꢖoltage
ꢖꢝꢄ
ꢓꢌꢀꢔꢌꢀꢈ
ꢃꢝꢄꢀ=ꢀ6.ꢀmꢞꢀ
(ꢀꢁꢁꢄꢀꢄoadꢂ)
0.ꢊ
ꢖ
ꢓꢌꢀꢈ
ꢔ
ꢄogicꢀꢍighꢀꢝutꢘutꢀꢖoltage
ꢖꢝꢍ
ꢓꢌꢀꢔꢌꢀꢈ
ꢃꢝꢍꢀ=ꢀꢅꢔ.6ꢀmꢞꢌ
(**ꢖꢝꢍꢀ=ꢀꢖCCꢀꢅꢀꢔ.ꢓꢀꢖ)
ꢔ.
**
ꢖ
ꢔꢌꢀꢈ
ꢔ
Nꢞ
ꢃꢝꢍꢀ=ꢀꢅ0.ꢈꢔꢀmꢞ
ꢈ.ꢓ
ꢝutꢘutꢀꢄeakage
Currentꢀ(ꢖꢝUꢁꢀꢚꢀꢖCC
ꢃꢝꢍꢍ
ꢓꢌꢀꢔꢌꢀꢈ
ꢖꢝꢀ=ꢀꢊ.ꢊꢀꢖ
ꢖꢝꢀ=ꢀꢔ0ꢀꢖ
ꢃꢇꢀ=ꢀꢉꢀmꢞ
ꢖCCꢀ=ꢀ
.ꢊꢀꢖ
ꢓ00
ꢊ00
mꢞ
ꢔ
)
ꢄogicꢀ
ꢄowꢀ
Suꢘꢘlꢏ
Current
Singleꢀ
Channel
ꢃCCꢄ
ꢓꢌꢀꢔꢌꢀꢈ
ꢖCCꢀ=ꢀꢊ.ꢊꢀꢖ
ꢖCCꢀ=ꢀꢔ0ꢀꢖ
ꢖꢇꢀ=ꢀ0ꢀꢖ
ꢖEꢀ=ꢀ
Don’tꢀ
Care
.ꢊ
ꢊ.ꢈ
6
mꢞ
7.ꢊ
Dualꢀꢀ
Channel
ꢖCCꢀ=ꢀꢊ.ꢊꢀꢖ
ꢖCCꢀ=ꢀꢔ0ꢀꢖ
ꢖCCꢀ=ꢀꢊ.ꢊꢀꢖ
ꢖꢇꢓꢀ=ꢀꢖꢇꢔ
=ꢀ0ꢀꢖ
ꢀ
ꢀ
9.0
ꢓ0.6
ꢓ
ꢓꢔ
ꢓꢊ
ꢔ
ꢋuad
Channel
ꢖꢇꢓꢀ=ꢀꢖꢇꢔ
=ꢀꢖꢇꢈꢀ=ꢀ
ꢖꢇꢀ=0ꢀꢖ
ꢖCCꢀ=ꢀꢔ0ꢀꢖ
ꢖCCꢀ=ꢀꢊ.ꢊꢀꢖ
ꢖCCꢀ=ꢀꢔ0ꢀꢖ
ꢓ7
ꢔ.9
ꢈ.ꢈ
ꢈ0
.ꢊ
6
ꢄogicꢀ
Singleꢀ
Channel
ꢃCCꢍ
ꢓꢌꢀꢔꢌꢀꢈ
ꢃꢇꢀ=ꢀꢉmꢞ
ꢖEꢀ=ꢀ
Don’tꢀ
Care
mꢞ
ꢍighꢀ
Suꢘꢘlꢏꢀ
Current
Dualꢀ
Channel
ꢖCCꢀ=ꢀꢊ.ꢊꢀꢖ
ꢖCCꢀ=ꢀꢔ0ꢀꢖ
ꢖCCꢀ=ꢀꢊ.ꢊꢀꢖ
ꢖCCꢀ=ꢀꢔ0ꢀꢖ
ꢃꢇꢓꢀ=ꢀꢃꢇꢔꢀ=ꢀ
ꢉmꢞ
ꢊ.ꢉ
6.6
9
9
ꢓꢔ
ꢓꢉ
ꢔ
ꢋuad
Channel
ꢃꢇꢓꢀ=ꢀꢃꢇꢔꢀ=ꢀ
ꢃꢇꢈꢀ=ꢀꢃꢇꢀ=ꢀ
ꢉmꢞ
ꢓꢓ
ꢄogicꢀꢄowꢀShortꢀCircuitꢀ
ꢝutꢘutꢀCurrent
ꢃꢝSꢄ
ꢓꢌꢀꢔꢌꢀꢈ
ꢓꢌꢀꢔꢌꢀꢈ
ꢖꢝꢀ=ꢀꢖCCꢀ=ꢀ
ꢊ.ꢊꢀꢖ
ꢖꢇꢀ=ꢀ0ꢀꢖ
ꢔ0
ꢈꢊ
mꢞ
mꢞ
ꢔꢌꢀꢈ
ꢔꢌꢀꢈ
ꢖꢝꢀ=ꢀꢖCCꢀ=ꢀꢔ0ꢀꢖ
ꢖCCꢀ=ꢀꢊ.ꢊꢖ
ꢄogicꢀꢍighꢀShortꢀCircuitꢀ
ꢝutꢘutꢀCurrent
ꢃꢝSꢍ
ꢃꢇꢀ=ꢀꢉꢀmꢞ
ꢖꢝꢀ=ꢀꢐND
ꢅꢓ0
ꢖCCꢀ=ꢀꢔ0ꢀꢖ
ꢅꢔꢊ
ꢓ.ꢉ
ꢃnꢘutꢀꢇorwardꢀꢖoltage
ꢖꢇ
ꢓꢌꢀꢔꢌꢀꢈ
ꢓꢌꢀꢔꢌꢀꢈ
ꢃꢇꢀ=ꢀꢉꢀmꢞ
ꢓ.0
ꢈ
ꢓ.ꢈ
ꢖ
ꢖ
ꢔ
ꢔ
ꢃnꢘutꢀꢆeverꢂeꢀ
Bꢖꢆ
ꢃꢆꢀ=ꢀꢓ0ꢀmꢞ
Breakdownꢀꢖoltage
ꢃnꢘutꢅꢝutꢘutꢀꢃnꢂulationꢀ
ꢄeakageꢀCurrent
ꢃꢃꢅꢝ
ꢓ
ꢖꢃꢅꢝꢀ=ꢀꢓꢊ00ꢀꢖdcꢌꢀtꢀ=ꢀꢊꢂꢌꢀ
ꢆꢍꢀ≤ꢀ6ꢊ%ꢌꢀꢁꢞꢀ=ꢀꢔꢊꢑC
ꢓ.0
mꢞ
ꢌꢀꢊ
ꢄogicꢀꢍighꢀCommonꢀModeꢀ |CMꢍ|
ꢁranꢂientꢀꢃmmunitꢏ
9ꢌꢀꢓ0ꢌꢀꢓꢓ
9ꢌꢀꢓ0ꢌꢀꢓꢓ
9ꢌꢀꢓ0ꢌꢀꢓꢓ
9ꢌꢀꢓ0ꢌꢀꢓꢓ
ꢃꢇꢀ=ꢀꢔꢀmꢞꢌꢀꢖCMꢀ=ꢀꢊ0ꢀꢖPꢅP ꢓ000 ꢓ0ꢌ000
ꢖꢛmꢂ
ꢖꢛmꢂ
nꢂ
9
ꢔꢌꢀ6ꢌꢀꢓꢔ
ꢔꢌꢀ6ꢌꢀꢓꢔ
ꢔꢌꢀ7
ꢄogicꢀꢄowꢀCommonꢀModeꢀ
ꢁranꢂientꢀꢃmmunitꢏ
|CMꢄ|
ꢃꢇꢀ=ꢀ0ꢀmꢞꢌꢀꢖCMꢀ=ꢀꢊ0ꢀꢖPꢅP ꢓ000 ꢓ0ꢌ000
9
ProꢘagationꢀDelaꢏꢀꢀ
ꢁimeꢀtoꢀꢄogicꢀꢄow
tPꢍꢄ
ꢓ7ꢈ
ꢓꢓꢉ
ꢈꢊ0
ꢈꢊ0
ꢊꢌꢀ6
ꢊꢌꢀ6
ProꢘagationꢀDelaꢏꢀꢀ
ꢁimeꢀtoꢀꢄogicꢀꢍigh
tPꢄꢍ
nꢂ
ꢔꢌꢀ7
ꢆ
Electrical Characteristics - Single Channel Product Only
ꢁ ꢀ=ꢀꢅꢊꢊꢑCꢀtoꢀꢒꢓꢔꢊꢑCꢌꢀ.ꢊꢀꢖꢀ≤ꢀꢖ ꢀ≤ꢀꢔ0ꢀꢖꢌꢀꢔꢀmꢞꢀ≤ꢀꢃ ꢀ≤ꢀꢉꢀmꢞꢌꢀ0ꢀꢖꢀ≤ꢀꢖ
ꢇꢀ(ꢝN)
ꢀ≤ꢀ0.ꢉꢀꢖꢌꢀꢔ.0ꢀꢖꢀ≤ꢀꢖ ꢀ≤ꢀꢔ0ꢀꢖꢌꢀ0ꢀꢖꢀ≤ꢀꢖ ꢀ≤ꢀ0.ꢉꢀꢖꢌꢀ
ꢞ
CC
ꢇ(ꢝꢇꢇ)
Eꢍ
Eꢄ
unleꢂꢂꢀotherwiꢂeꢀꢂꢘecified.
Limits
Typ.*
ꢀ
Group A,
Sub-groups[11]
Parameter
Symbol
Test Conditions
Min.
Max.
Units Fig. Notes
ꢍighꢀꢃmꢘedanceꢀ
Stateꢀꢝutꢘutꢀꢀ
Current
ꢃꢝZꢄ
ꢓꢌꢔꢌꢈ
ꢖꢝꢀ=ꢀ0.ꢀꢖ
ꢖENꢀ=ꢀꢔꢀꢖꢌꢀ
ꢖꢇꢀ=ꢀ0ꢀꢖ
ꢀ
ꢅꢔ0
mꢞ
ꢀ
ꢀ
ꢃꢝZꢍ
ꢓꢌꢔꢌꢈ
ꢖꢝꢀ=ꢀꢔ.ꢀꢖ
ꢖENꢀ=ꢀꢔꢀꢖꢌꢀ
ꢃꢇꢀ=ꢀꢉꢀmꢞ
ꢔ0
mꢞ
ꢖꢝꢀ=ꢀꢊ.ꢊꢀꢖ
ꢖꢝꢀ=ꢀꢔ0ꢀꢖ
ꢓ00
ꢊ00
ꢄogicꢀꢍighꢀꢀ
Enableꢀꢀꢖoltage
ꢖEꢍ
ꢖEꢄ
ꢃEꢍ
ꢓꢌꢀꢔꢌꢀꢈ
ꢓꢌꢀꢔꢌꢀꢈ
ꢓꢌꢀꢔꢌꢀꢈ
ꢔ.0
ꢖ
ꢖ
ꢄogicꢀꢄowꢀꢀ
Enableꢀꢀꢖoltage
0.ꢉ
ꢀ
ꢀ
ꢀ
ꢀ
ꢄogicꢀꢍighꢀꢀ
EnableꢀꢀCurrent
ꢖENꢀ=ꢀꢔ.7ꢀꢖ
ꢔ0
ꢓ00
ꢔꢊ0
ꢅ0.ꢈꢔ
mꢞ
ꢀ
ꢖENꢀ=ꢀꢊ.ꢊꢀꢖ
ꢖENꢀ=ꢀꢔ0ꢀꢖ
ꢖENꢀ=ꢀ0.ꢀꢖ
0.00
ꢄogicꢀꢄowꢀꢀ
ꢃEꢄ
ꢓꢌꢀꢔꢌꢀꢈ
mꢞ
EnableꢀꢀCurrent
*ꢞllꢀtꢏꢘicalꢀvalueꢂꢀareꢀatꢀꢖ ꢀ=ꢀꢊꢀꢖꢌꢀꢁ ꢀ=ꢀꢔꢊꢑCꢌꢀꢃ ꢀ=ꢀꢊꢀmꢞꢀunleꢂꢂꢀotherwiꢂeꢀꢂꢘecified.
ꢇ(ꢝN)
CC
ꢞ
ꢇ
Typical Characteristics
ꢞllꢀtꢏꢘicalꢀvalueꢂꢀareꢀatꢀꢁ ꢀ=ꢀꢔꢊꢑCꢌꢀꢖ ꢀ=ꢀꢊꢀꢖꢌꢀꢃ ꢀ=ꢀꢊꢀmꢞꢀunleꢂꢂꢀotherwiꢂeꢀꢂꢘecified.
ꢞ
CC
ꢇ(ꢝN)
Parameter
Symbol
Test Conditions
ꢖCCꢀ=ꢀꢊꢀꢖ
Typ.
0.07
ꢅꢓ.ꢔꢊ
Units
mꢞ
Fig.
Notes
ꢃnꢘutꢀCurrentꢀꢍꢏꢂtereꢂiꢂ
ꢃꢍYS
ꢈ
ꢔ
ꢔ
ꢃnꢘutꢀDiodeꢀꢁemꢘeratureꢀ
Coefficient
Dꢖꢇ
Dꢁꢞ
ꢃꢇꢀ=ꢀꢉꢀmꢞ
mꢖꢛꢑC
W
ꢘꢇ
ꢘꢇ
nꢂ
nꢂ
ꢆeꢂiꢂtanceꢀ(ꢃnꢘutꢅꢝutꢘut)
ꢆꢃꢅꢝ
Cꢃꢅꢝ
CꢃN
tr
ꢖꢃꢅꢝꢀ=ꢀꢊ00ꢀꢖdc
�ꢀ=ꢀꢓꢀMꢍz
ꢓ0ꢓꢈ
ꢔ.0
ꢔ0
ꢔꢌꢀꢉ
ꢔꢌꢀꢉ
ꢔꢌꢀꢓ0
ꢔ
Caꢘacitanceꢀ(ꢃnꢘutꢅꢝutꢘut)
ꢃnꢘutꢀCaꢘacitance
ꢖꢇꢀ=ꢀ0ꢀꢖꢌꢀ�ꢀ=ꢀꢓꢀMꢍz
ꢝutꢘutꢀꢆiꢂeꢀꢁimeꢀ(ꢓ0ꢅ90%)
ꢝutꢘutꢀꢇallꢀꢁimeꢀ(90ꢅꢓ0%)
ꢊ
ꢊꢌꢀ7
ꢊꢌꢀ7
t�
ꢓ0
ꢔ
Single Channel Product Only
ꢝutꢘutꢀEnableꢀꢁimeꢀtoꢀꢄogicꢀꢍigh
ꢝutꢘutꢀEnableꢀꢁimeꢀtoꢀꢄogicꢀꢄow
ꢝutꢘutꢀDiꢂableꢀꢁimeꢀ�romꢀꢄogicꢀꢍigh
ꢝutꢘutꢀDiꢂableꢀꢁimeꢀ�romꢀꢄogicꢀꢄow
Multi-Channel Product Only
tPZꢍ
tPZꢄ
tPꢍZ
tPꢄZ
ꢈ0
ꢈ0
ꢊ
ꢊꢊ
nꢂ
nꢂ
nꢂ
nꢂ
ꢉ
ꢉ
ꢉ
ꢉ
ꢃnꢘutꢅꢃnꢘutꢀꢃnꢂulationꢀꢄeakageꢀꢀ
Current
ꢃꢃꢅꢃ
ꢆꢍꢀ≤ꢀ6ꢊ%ꢌꢀ
ꢖꢃꢅꢃꢀ=ꢀꢊ00ꢀꢖꢌꢀtꢀ=ꢀꢊꢀꢂ
0.ꢊ
nꢞ
9
ꢓ0ꢓꢈ
ꢓ.ꢊ
9
9
W
ꢆeꢂiꢂtanceꢀ(ꢃnꢘutꢅꢃnꢘut)
Caꢘacitanceꢀ(ꢃnꢘutꢅꢃnꢘut)
ꢆꢃꢅꢃ
Cꢃꢅꢃ
ꢖꢃꢅꢃꢀ=ꢀꢊ00ꢀꢖ
�ꢀ=ꢀꢓꢀMꢍz
ꢘꢇ
Noteꢂꢙ
ꢓ.ꢀ PeakꢀꢇorwardꢀꢃnꢘutꢀCurrentꢀꢘulꢂeꢀwidthꢀ<ꢀꢊ0ꢀꢜꢂꢀatꢀꢓꢀꢎꢍzꢀmaꢗimumꢀreꢘetitionꢀrate.
ꢔ.ꢀ Eachꢀchannelꢀo�ꢀaꢀmultichannelꢀdevice.
ꢈ.ꢀ Durationꢀo�ꢀoutꢘutꢀꢂhortꢀcircuitꢀtimeꢀnotꢀtoꢀeꢗceedꢀꢓ0ꢀmꢂ.
.ꢀ ꢞllꢀdeviceꢂꢀareꢀconꢂideredꢀtwoꢅterminalꢀdeviceꢂꢙꢀmeaꢂuredꢀbetweenꢀallꢀinꢘutꢀleadꢂꢀorꢀterminalꢂꢀꢂhortedꢀtogetherꢀandꢀallꢀoutꢘutꢀleadꢂꢀorꢀterꢅ
minalꢂꢀꢂhortedꢀtogether.
ꢊ.ꢀ ꢁhiꢂꢀiꢂꢀaꢀmomentarꢏꢀwithꢂtandꢀteꢂtꢌꢀnotꢀanꢀoꢘeratingꢀcondition.
6.ꢀ CM ꢀiꢂꢀtheꢀmaꢗimumꢀrateꢀo�ꢀriꢂeꢀo�ꢀtheꢀcommonꢀmodeꢀvoltageꢀthatꢀcanꢀbeꢀꢂuꢂtainedꢀwithꢀtheꢀoutꢘutꢀvoltageꢀinꢀtheꢀlogicꢀlowꢀꢂtateꢀ(ꢖ ꢀ<ꢀ0.ꢉꢀ
ꢄ
ꢝ
ꢖ).ꢀCM ꢀiꢂꢀtheꢀmaꢗimumꢀrateꢀo�ꢀ�allꢀo�ꢀtheꢀcommonꢀmodeꢀvoltageꢀthatꢀcanꢀbeꢀꢂuꢂtainedꢀwithꢀtheꢀoutꢘutꢀvoltageꢀinꢀtheꢀlogicꢀhighꢀꢂtateꢀ(ꢖ ꢀꢚꢀ
ꢍ
ꢝ
ꢔ.0ꢀꢖ).
7.ꢀ t ꢀꢘroꢘagationꢀdelaꢏꢀiꢂꢀmeaꢂuredꢀ�romꢀtheꢀꢊ0%ꢀꢘointꢀonꢀtheꢀleadingꢀedgeꢀo�ꢀtheꢀinꢘutꢀꢘulꢂeꢀtoꢀtheꢀꢓ.ꢈꢀꢖꢀꢘointꢀonꢀtheꢀleadingꢀedgeꢀo�ꢀtheꢀ
Pꢍꢄ
outꢘutꢀꢘulꢂe.ꢀꢁheꢀt ꢀꢘroꢘagationꢀdelaꢏꢀiꢂꢀmeaꢂuredꢀ�romꢀtheꢀꢊ0%ꢀꢘointꢀonꢀtheꢀtrailingꢀedgeꢀo�ꢀtheꢀinꢘutꢀꢘulꢂeꢀtoꢀtheꢀꢓ.ꢈꢀꢖꢀꢘointꢀonꢀtheꢀ
Pꢄꢍ
trailingꢀedgeꢀo�ꢀtheꢀoutꢘutꢀꢘulꢂe.
ꢉ.ꢀ Meaꢂuredꢀbetweenꢀeachꢀinꢘutꢀꢘairꢀꢂhortedꢀtogetherꢀandꢀallꢀoutꢘutꢀconnectionꢂꢀ�orꢀthatꢀchannelꢀꢂhortedꢀtogether.
9.ꢀ Meaꢂuredꢀbetweenꢀadjacentꢀinꢘutꢀꢘairꢂꢀꢂhortedꢀtogetherꢀ�orꢀeachꢀmultichannelꢀdevice.
ꢓ0.ꢀZeroꢅbiaꢂꢀcaꢘacitanceꢀmeaꢂuredꢀbetweenꢀtheꢀꢄEDꢀanodeꢀandꢀcathode.
ꢓꢓ.ꢀStandardꢀꢘartꢂꢀreceiveꢀꢓ00%ꢀteꢂtingꢀatꢀꢔꢊꢑCꢀ(Subgrouꢘꢂꢀꢓꢀandꢀ9).ꢀSMDꢌꢀClaꢂꢂꢀꢍꢀandꢀClaꢂꢂꢀꢎꢀꢘartꢂꢀreceiveꢀꢓ00%ꢀteꢂtingꢀatꢀꢔꢊꢌꢀꢓꢔꢊꢌꢀandꢀ–ꢊꢊꢑCꢀ
(Subgrouꢘꢂꢀꢓꢀandꢀ9ꢌꢀꢔꢀandꢀꢓ0ꢌꢀꢈꢀandꢀꢓꢓꢌꢀreꢂꢘectivelꢏ).
ꢓꢔ.ꢀParameterꢂꢀareꢀteꢂtedꢀaꢂꢀꢘartꢀo�ꢀdeviceꢀinitialꢀcharacterizationꢀandꢀa�terꢀdeꢂignꢀandꢀꢘroceꢂꢂꢀchangeꢂ.ꢀParameterꢂꢀguaranteedꢀtoꢀlimitꢂꢀꢂꢘeciꢅ
fiedꢀ�orꢀallꢀlotꢂꢀnotꢀꢂꢘecificallꢏꢀteꢂted.
10
Figure 1. Typical Logic Low Output Voltage vs. Temperature.
Figure 2. Typical Logic High Output Current vs. Temperature.
Figure 3. Output Voltage vs. Forward Input Current.
Figure 4. Typical Diode Input Forward Characteristic.
V
CC
OUTPUT V
PULSE GEN.
= t 5 ns
t = 100 kHz
10 % DUTY
CYCLE
O
t
=
r
f
MONITORING
NODE
5 V
D.U.T.
V
CC
619
Ω
D
1
I
F
V
O
INPUT
MONITORING
NODE
D
D
D
2
3
4
C
15 pF
=
L
V
E
GND
5 K
R
f
THE PROBE AND JIG CAPACITANCES
ARE INCLUDED IN C
.
L
Figure 5. Test Circuit for tPLH, tPHL, tr, and tf.
11
Figure 6. Typical Propagation Delay vs. Temperature.
Figure 7. Typical Rise, Fall Time vs. Temperature.
C
= 15 pF INCLUDING PROBE
L
AND JIG CAPACITANCE.
PULSE
GENERATOR
+5 V
V
CC
Z
= 50 Ω
f
O
t
= t = 5 ns
r
V
O
S1
619 Ω
D.U.T.
V
CC
D
1
V
O
I
F
D
D
D
2
3
4
C
L
V
E
GND
5 K Ω
INPUT VO
MONITORING
NODE
S2
Figure 8. Test Circuit for tPHZ, tPZH, tPLZ, and tPZL
.
A
VCC
D.U.T.
B
OUTPUT VO
MONITORING
NODE
VCC
RIN
VO
0.1 µF
BYPASS
VE
VFF
GND
VCM
+
-
PULSE GEN.
Figure 9. Test Circuit for Common Mode Transient Immunity and Typical Waveforms.
1ꢀ
VCC1
(+5 V)
VCC2
(4.5 TO 20 V)
VCC1
(+5 V)
665 Ω
D.U.T.
750 Ω
D.U.T.
VCC
VO
RL
DATA
OUTPUT
VCC
DATA
CMOS
DATA
INPUT
TTL OR
LSTTL
INPUT
TTL OR
LSTTL
VE
GND
TOTEM
POLE
GND
TOTEM
OUTPUT
GATE
VCC2
R L
POLE
OUTPUT
GATE
5 V
1.1 K
1
2
10 V
15 V
20 V
2.37 K
3.83 K
5.11 K
Figure 11. Recommended LED Drive Circuit.
Figure 10. LSTTL to CMOS Interface Circuit.
VCC1
(+5 V)
619 Ω
D.U.T.
VCC
4.02 KΩ
DATA
INPUT
TTL OR
LSTTL
GND
OPEN
COLLECTOR
GATE
Figure 12. Series LED Drive with Open Collector Gate
(4.02 kΩ Resistor Shunts IOH from the LED).
V
CC2
(+5 V)
DATA
OUTPUT
V
CC1
(+5 V)
UP TO 16 LSTTL
LOADS
665 Ω
665 Ω
D.U.T.
OR 4 TTL LOADS
V
CC
0.1
µF
DATA
INPUT
TTL OR
LSTTL
DATA
OUTPUT
DATA
INPUT
TTL OR
LSTTL
TOTEM
POLE
GND
OUTPUT
GATE
1
TOTEM
POLE
OUTPUT
GATE
UP TO 16 LSTTL
LOADS
OR 4 TTL LOADS
1
2
Figure 13. Recommended LSTTL to LSTTL Circuit.
V
+ 20 V
CC
MIL-PRF-38534 Class H, Class K, and DSCC SMD Test Pro-
gram
D.U.T.*
V
CC
ꢞvagoꢀꢁechnologieꢂ’ꢀ ꢀ ꢍiꢅꢆelꢀ ꢝꢘtocouꢘlerꢂꢀ areꢀ inꢀ comꢅ
ꢘlianceꢀ withꢀ MꢃꢄꢅPꢆꢇꢅꢈꢉꢊꢈꢀ Claꢂꢂeꢂꢀ ꢍꢀ andꢀ ꢎ.ꢀ Claꢂꢂꢀ ꢍꢀ
andꢀClaꢂꢂꢀꢎꢀdeviceꢂꢀareꢀalꢂoꢀinꢀcomꢘlianceꢀwithꢀDSCCꢀ
drawingꢂꢀꢊ96ꢔꢅꢉꢉ76ꢉꢀandꢀꢊ96ꢔꢅꢉꢉ769.
I
F
I
O
0.01 µF
+-
1200 Ω
V
E
V
IN
1.90 V
100 Ω
GND
ꢁeꢂtingꢀconꢂiꢂtꢂꢀo�ꢀꢓ00%ꢀꢂcreeningꢀandꢀqualitꢏꢀcon�orꢅ
manceꢀinꢂꢘectionꢀtoꢀMꢃꢄꢅPꢆꢇꢅꢈꢉꢊꢈ.
CONDITIONS: I = 8 mA
F
I
= -14 mA
O
T
= +125 ˚C
A
*ALL CHANNELS TESTED SIMULTANEOUSLY.
Figure 14. Single Channel Operating Circuit for Burn-in and Steady State
Life Tests.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com
Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Limited in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Limited. All rights reserved.
5989-2666EN - April 4, 2007
相关型号：
©2020 ICPDF网 联系我们和版权申明