5962-8957104K2X [AVAGO]
Logic IC Output Optocoupler, 2-Element, 1500V Isolation, 40MBps, CERAMIC, LCCC-20;
| 型号： | 5962-8957104K2X |
| 厂家： | 
AVAGO TECHNOLOGIES LIMITED |
| 描述： | Logic IC Output Optocoupler, 2-Element, 1500V Isolation, 40MBps, CERAMIC, LCCC-20 输出元件 光电 |
| 文件： | 总12页 (文件大小：584K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
HCPL-540X*, 5962-89570, HCPL-543X,
HCPL-643X, 5962-89571
Hermetically Sealed, Very High Speed,
Logic Gate Optocouplers
Data Sheet
*See matrix for available extensions.
Description
Features
These units are single and dual channel, hermetically Dual marked with device part number and DSCC
sealed optocouplers. The products are capable of
operation and storage over the full military temperature
range and can be purchased as either standard product or
with full MIL-PRF-38534 Class Level H or K testing or from
the appropriate DSCC Drawing. All devices are manufac-
tured and tested on a MIL-PRF-38534 certified line and
are included in the DSCC Qualified Manufacturers List,
QML-38534 for Hybrid Microcircuits.
standard microcircuit drawing
Manufactured and tested on a MIL-PRF-38534 certified
line
QML-38534, Class H and K
Three hermetically sealed package configurations
Performance guaranteed over full military temperature
range: -55° C to +125° C
High Speed: 40 M bit/s
High common mode rejection 500 V/s guaranteed
1500 Vdc withstand test voltage
Active (totem pole) outputs
Three stage output available
High radiation immunity
Truth Tables (Positive Logic)
Multichannel Devices
Input
Output
On (H)
Off (L)
L
H
HCPL-2400/30 function compatibility
Reliability data
Single Channel DIP
Compatible with TTL, STTL, LSTTL, and HCMOS logic
Input
Enable
Output
families
On (H)
Off (L)
On (H)
Off (L)
L
L
Applications
L
H
Z
Z
Military and space
High reliability systems
Transportation, medical, and life critical systems
Isolation of high speed logic systems
Computer-peripheral interfaces
Switching power supplies
H
H
Functional Diagram
Multiple channel devices available
Isolated bus driver (networking applications) –
VCC
VE
(5400/1/K only)
Pulse transformer replacement
Ground loop elimination
Harsh industrial environments
High speed disk drive I/O
VO
GND
Digital isolation for A/D, D/A conversion
The connection of a 0.1 F bypass capacitor between V and GND is
CC
recommended.
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Each channel contains an AlGaAs light emitting diode (case outlines P), and leadless ceramic chip carrier (case
which is optically coupled to an integrated high gain outline 2). Devices may be purchased with a variety of
photon detector. This combination results in very high lead bend and plating options. See Selection Guide Table
data rate capability. The detector has a threshold with for details. Standard Microcircuit Drawing (SMD) parts are
hysteresis, which typically provides 0.25 mA of differen- available for each package and lead style.
tial mode noise immunity and minimizes the potential for
Because the same electrical die (emitters and detectors)
output signal chatter. The detector in the single channel
are used for each channel of each device listed in this
units has a three state output stage which eliminates the
data sheet, absolute maximum ratings, recommended
need for a pull-up resistor and allows for direct drive of a
operating conditions, electrical specifications, and per-
data bus.
formance characteristics shown in the figures are similar
All units are compatible withTTL, STTL, LSTTL, and HCMOS for all parts. Occasional exceptions exist due to package
logic families. The 35 ns pulse width distortion speci- variations and limitations and are as noted. Additionally,
fication guarantees a 10 MBd signaling rate at +125° C the same package assembly processes and materials are
with 35% pulse width distortion. Figures 13 through 16
used in all devices. These similarities give justification for
show recommended circuits for reducing pulse width the use of data obtained from one part to represent other
distortion and optimizing the signal rate of the product. part’s performance for die related reliability and certain
Package styles for these parts are 8 pin DIP through hole limited radiation test results.
Selection Guide–Package Styles and Lead Configuration Options
Package
8 Pin DIP
Through Hole
1
8 Pin DIP
Through Hole
2
20 Pad LCCC
Surface Mount
2
Lead Style
Channels
Common Channel Wiring
Avago Part # & Options
Commercial
None
VCC, GND
None
HCPL-5400
HCPL-5401
HCPL-540K
Gold Plate
Option 200
Option 100
Option 300
HCPL-5430
HCPL-5431
HCPL-543K
Gold Plate
Option 200
Option 100
Option 300
HCPL-6430
HCPL-6431
HCPL-643K
Solder Pads*
MIL-PRF-38534, Class H
MIL-PRF-38534, Class K
Standard Lead Finish
Solder Dipped*
Butt Cut/Gold Plate
Gull Wing/Soldered*
Class H SMD Part #
Prescript for all below
Either Gold or Solder
Gold Plate
5962-
5962-
5962-
8957001PX
8957001PC
8957001PA
8957001YC
8957001YA
8957001XA
8957101PX
8957101PC
8957101PA
8957101YC
8957101YA
8957101XA
89571022X
Solder Dipped*
89571022A
Butt Cut/Gold Plate
Butt Cut/Soldered*
Gull Wing/Soldered*
Class K SMD Part #
Prescript for all below
Either Gold of Solder
Gold Plate
5962-
5962-
5962-
8957002KPX
8957002KPC
8957002KPA
8957002KYC
8957002KYA
8957002KXA
8957103KPX
8957103KPC
8957103KPA
8957103KYC
8957103KYA
8957103KXA
8957104K2X
Solder Dipped*
8957104K2A
Butt Cut/Gold Plate
Butt Cut/Soldered*
Gull Wing/Soldered*
*Solder contains lead.
2
Functional Diagrams
8 Pin DIP
8 Pin DIP
20 Pad LCCC
Through Hole
1 Channel
Through Hole
2 Channels
Surface Mount
2 Channels
15
VCC2
VCC
VE
8
7
6
5
VCC
VO1
8
7
6
5
1
2
3
4
1
2
3
4
19
20
13
12
VO2
GND2
VCC1
VO2
2
3
10
VO1
VO
GND1
GND
GND
7
8
Note:
All DIP devices have common V and ground. LCCC (leadless ceramic chip carrier) package has isolated channels with separate V and ground
CC
CC
connections.
Outline Drawings
20 Terminal LCCC Surface Mount, 2 Channels
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
5.21 (0.205)
1.78 (0.070)
1.02 (0.040) (3 PLCS)
2.03 (0.080)
1.14 (0.045)
1.40 (0.055)
8.70 (0.342)
9.10 (0.358)
4.95 (0.195)
TERMINAL 1 IDENTIFIER
2.16 (0.085)
5.21 (0.205)
METALLIZED
1.78 (0.070)
2.03 (0.080)
CASTILLATIONS (20 PLCS)
0.64
0.51 (0.020)
(0.025)
(20 PLCS)
1.52 (0.060)
2.03 (0.080)
Note: Dimensions in millimeters (inches).
Solder thickness 0.127 (0.005) max.
8 Pin DIP Through Hole, 1 and 2 Channel
9.40 (0.370)
9.91 (0.390)
8.13 (0.320)
MAX.
0.76 (0.030)
1.27 (0.050)
7.16 (0.282)
7.57 (0.298)
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
3.81 (0.150)
MIN.
0.20 (0.008)
0.33 (0.013)
7.36 (0.290)
7.87 (0.310)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
Note: Dimensions in millimeters (inches).
3
Leaded Device Marking
Leadless Device Marking
Avago LOGO
Avago P/N
DSCC SMD*
DSCC SMD*
PIN ONE/
Avago QYYWWZ
XXXXXX
COMPLIANCE INDICATOR,*
Avago LOGO
Avago P/N
Avago QYYWWZ
COMPLIANCE INDICATOR,*
DATE CODE, SUFFIX (IF NEEDED)
DSCC SMD*
DATE CODE, SUFFIX (IF NEEDED)
XXXXXX
* XXXX
XXXXXXX
PIN ONE/
XXX USA
* 50434
XXXXXX
USA 50434
COUNTRY OF MFR.
Avago FSCN*
DSCC SMD*
ESD IDENT
COUNTRY OF MFR.
Avago FSCN*
ESD IDENT
* QUALIFIED PARTS ONLY
* QUALIFIED PARTS ONLY
Hermetic Optocoupler Options
Option
Description
100
Surface mountable hermetic optocoupler with leads trimmed for butt joint assembly. This option is available on
commercial and hi-rel product in 8 pin DIP (see drawings below for details).
4.32 (0.170)
MAX.
0.51 (0.020)
MIN.
1.14 (0.045)
1.40 (0.055)
0.20 (0.008)
0.33 (0.013)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
7.36 (0.290)
7.87 (0.310)
Note: Dimensions in millimeters (inches).
200
300
Lead finish is solder dipped rather than gold plated. This option is available on commercial and hi-rel product in
8 pin DIP. DSCC Drawing part numbers contain provisions for leadfinish. All leadless chip carrier devices are
delivered with solder dipped terminals as a standard feature.
Surface mountable hermetic optocoupler with leads cut and bent for gull wing assembly. This option is
available on commercial and hi-rel product in 8 pin DIP (see drawings below for details). This option has
solder dipped leads.
4.57 (0.180)
MAX.
4.57 (0.180)
MAX.
0.20 (0.008)
0.33 (0.013)
0.51 (0.020)
MIN.
5° MAX.
1.40 (0.055)
1.65 (0.065)
9.65 (0.380)
9.91 (0.390)
2.29 (0.090)
2.79 (0.110)
0.51 (0.020)
MAX.
Note: Dimensions in millimeters (inches).
*Solder contains lead.
4
Absolute Maximum Ratings
No derating required up to +125° C.
Parameter
Symbol
TS
Min.
-65
-55
Max.
Units
°C
Note
Storage Temperature
+150
Operating Temperature
TA
+125
°C
Case Temperature
TC
+170
°C
Junction Temperature
TJ
+175
°C
Lead Solder Temperature
260 for 10 sec
°C
Average Forward Current (each channel)
Peak Input Current (each channel)
Reverse Input Voltage (each channel)
Supply Voltage
IF(AVG)
IF(PEAK)
VR
10
20
3
mA
mA
V
1
VCC
0.0
7.0
25
10
130
200
V
Average Output Current (each channel)
Output Voltage (each channel)
Output Power Dissipation (each channel)
Package Power Dissipation (each channel)
IO(AVG)
VO
-25
-0.5
mA
V
PO
mW
mW
PD
Single Channel Product Only
Three State Enable Voltage
VE
-0.5
10
V
8 Pin Ceramic DIP Single Channel Schematic
ICC
8
ANODE
2
VCC
IF
+
7
6
VF
VE
VO
3
–
IE
CATHODE
5
GND
Note: Enable pin 7. An external 0.01 F to 0.1 μF bypass capacitor
must be connected between V and ground for each package type.
CC
ESD Classification
(MIL-STD-883, Method 3015)
HCPL-5400/01/0K
(
), Class 2
HCPL-5430/31/3K and HCPL-6430/31/3K
(Dot), Class 3
Recommended Operating Conditions
Parameter
Symbol
IF(ON)
VCC
Min.
6
Max.
Units
Input Current (High)
Supply Voltage, Output
Input Voltage (Low)
Fan Out (Each Channel)
10
5.25
0.7
5
mA
4.75
–
V
VF(OFF)
N
V
–
TTL Loads
Single Channel Product Only
High Level Enable Voltage
Low Level Enable Voltage
VEH
VEL
2.0
0
VCC
0.8
V
V
5
Electrical Characteristics
T = -55° C to +125° C, 4.75 V ≤ V ≤ 5.25 V, 6 mA ≤ I
≤ 10 mA, 0 V ≤ V
≤ 0.7 V, unless otherwise specified.
A
CC
F(ON)
F(OFF)
10
Group A
Limits
Parameter
Sym.
Test Conditions
Subgroups Min.
Typ.*
Max.
Units
Fig.
Notes
Low Level Output Voltage
VOL
IOL = 8.0 mA
(5 TTL Loads)
1, 2, 3
0.3
0.5
V
1
9
High Level Output Voltage
Output Leakage Current
VOH
IOH = -4.0 mA
1, 2, 3
1, 2, 3
2.4
V
2
9
9
IOHH
VO = 5.25 V,
VF = 0.7 V
100
A
Logic High
Supply Current
Single Channel ICCH
Dual Channel
VCC = 5.25 V,
VE = 0 V
1, 2, 3
1, 2, 3
17
26
mA
mA
34
52
13
Logic Low
Supply Current
Single Channel ICCL
Dual Channel
19
26
38
52
13
9
Input Forward Voltage
VF
IF = 10 mA
1, 2, 3
1, 2, 3
1.0
3.0
1.35
4.8
1.85
V
V
4
Input Reverse Breakdown
Voltage
VR
IR = 10 A
9
Input-Output Insulation
Leakage Current
II-O
VI-O = 1500 Vdc,
RH ≤ 65%,
t = 5 s
1
1.0
A
2, 3
Propagation Delay Time
Logic Low Output
tPHL
tPLH
PWD
9, 10, 11
9, 10, 11
33
30
60
60
35
ns
ns
5, 6, 7 4, 9
5, 6, 7 4, 9
5, 6, 7 4, 9
Propagation Delay Time
Logic High Output
Pulse Width Distortion
9, 10, 11
9, 10, 11
3
ns
Logic High Common
Mode Transient Immunity
|CMH| VCM = 50 VP-P
,
500
500
3000
V/s
11
5, 9, 11
IF = 0 mA
Logic Low Common
Mode Transient Immunity
|CML| VCM = 50 VP-P
,
9, 10, 11
3000
V/s
11
5, 9, 11
IF = 6 mA
Single Channel Product Only
Group A10
Limits
Max.
Parameter
Sym.
VEH
VEL
IEH
Test Conditions
Subgroups Min.
Typ.*
Units
V
Fig.
Notes
Logic High Enable Voltage
Logic Low Enable Voltage
Logic High Enable Current
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
1, 2, 3
2.0
0.8
20
V
VE = 2.4 V
VE = 5.25 V
VE = 0.4 V
A
100
-0.4
28
Logic Low Enable Current
IEL
-0.28
22
mA
mA
High Impedance State
Supply Current
ICCZ
VCC = 5.25 V,
VE = 5.25 V
High Impedance State
Output Current
IOZL
IOZH
VO = 0.4 V, VE = 2 V
VO = 2.4 V, VE = 2 V
VO = 5.25 V, VE = 2 V
1, 2, 3
-20
20
A
100
*All typical values are at V = 5 V, T = 25° C, I = 8 mA except where noted.
CC
A
F
6
Typical Characteristics
All typical values are at T = 25°C, V = 5 V, I = 8 mA, unless otherwise specified.
A
CC
F
Parameter
Symbol
IHYS
Typ.
Units
mA
Test Conditions
VCC = 5 V
Fig.
3
Notes
Input Current Hysteresis
0.25
-1.11
Input Diode Temperature Coefficient
VF
TA
mV/°C
IF = 10 mA
4
Resistance (Input-Output)
Capacitance (Input-Output)
RI-O
CI-O
IOSL
IOSH
1012
0.6
V
I-O = 500 V
2
pF
f = 1 MHz, VI-O = 0 V
2
Logic Low Short Circuit Output Current
Logic High Short Circuit Output Current
65
mA
mA
VO = VCC = 5.25 V, IF = 10 mA
6, 9
6, 9
-50
VCC = 5.25 V, IF = 0 mA,
VO = GND
Output Rise Time (10-90%)
Output Fall Time (90-10%)
Propagation Delay Skew
tr
15
10
30
0.5
ns
5
tf
ns
5
tPSK
PSNI
ns
10
12
7
Power Supply Noise Immunity
VP-P
48 Hz ≤ fac ≤ 50 MHz
Single Channel Product Only
Parameter
Symbol
Typ.
Units
Test Conditions
Fig.
Notes
Input Capacitance
CIN
15
pF
f = 1 MHz, VF = 0 V,
Pins 2 and 3
Output Enable Time to Logic High
Output Enable Time to Logic Low
Output Disable Time from Logic High
Output Disable Time from Logic Low
tPZH
tPZL
tPHZ
tPLZ
15
30
20
15
ns
ns
ns
ns
8, 9
8, 9
8, 9
8, 9
Dual and Quad Channel Product Only
Input Capacitance
Input-Input Leakage Current
Input-Input Resistance
Input-Input Capacitance
Notes:
CIN
II-I
15
pF
nA
f = 1 MHz, VO = 0 V
0.5
1012
1.3
RH ≤ 65%, VI-I = 500 Vdc
8
8
8
RI-I
CI-I
VI-I = 500 V
pF
f = 1 MHz, VF = 0 V
1. Not to exceed 5% duty factor, not to exceed 50 sec pulse width.
2. All devices are considered two-terminal devices: measured between
all input leads or terminals shorted together and all output leads or
terminals shorted together.
8. Measured between adjacent input pairs shorted together for each
multichannel device.
9. Each channel.
10. Standard parts receive 100% testing at 25° C (Subgroups 1 and 9).
SMD, Class H and Class K parts receive 100% testing at 25° C, 125° C,
and -55° C (Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
11. Parameters are tested as part of device initial characterization and
after design and process changes. Parameters are guaranteed to
limits specified for all lots not specifically tested.
12. Propagation delay skew is defined as the difference between the
minimum and maximum propagation delays for any given group of
optocouplers with the same part number that are all switching at the
same time under the same operating conditions.
3. This is a momentary withstand test, not an operating condition.
4.
t
propagation delay is measured from the 50% point on the rising
PHL
edge of the input current pulse to the 1.5 V point on the falling edge
of the output pulse. The t propagation delay is measured from the
PLH
50% point on the falling edge of the input current pulse to the 1.5 V
point on the rising edge of the output pulse. Pulse Width Distortion,
PWD = |t
- t |.
PHL PLH
5. CM is the maximum slew rate of the common mode voltage that can
L
be sustained with the output voltage in the logic low state (V
O(MAX)
< 0.8 V). CM is the maximum slew rate of the common mode voltage
that can be sustained with the output voltage in the logic high state
13. The HCPL-6430, HCPL-6431, and HCPL-643K dual channel parts
function as two independent single channel units. Use the single
channel parameter limits.
H
(V
O(MIN)
> 2.0 V).
6. Duration of output short circuit time not to exceed 10 ms.
7. Power Supply Noise Immunity is the peak to peak amplitude of the
ac ripple voltage on the V line that the device will withstand and
CC
still remain in the desired logic state. For desired logic high state,
V
> 2.0 V, and for desired logic low state, V
< 0.8 V.
OH(MIN)
OL(MAX)
7
Figure 1. Typical logic low output voltage vs. logic low output current
Figure 2. Typical logic high output voltage vs. logic high output current
Figure 3. Typical output voltage vs. input forward current
Figure 4. Typical diode input forward current characteristic
8
PULSE GEN.
tr = tf = 5 ns
f = 500 kHz
25 % DUTY
CYCLE
VO
V
5.0 V
CC
OUTPUT
MONITORING
NODE
D.U.T.
IF
1.3 KΩ
VCC
0.1 µF
INPUT
MONITORING
NODE
30 pF
C2
100 Ω
GND
2.5 KΩ
C1
15 pF
THE PROBE AND JIG CAPACITANCES
ARE REPRESENTED BY C1 AND C2.
ALL DIODES ARE 1N4150 OR EQUIVALENT.
Figure 5. Test circuit for tPLH, tPHL, tr, and tf
Figure 6. Typical propagation delay vs. ambient temperature
Figure 7. Typical propagation delay vs. input forward current
PULSE
GENERATOR
ZO = 50 Ω
VCC
5.0 V
S1
tr = tf = 5 ns
D.U.T.
VCC
1
2
3
4
8
7
6
5
0.1 µF
VO
IF
1.3 KΩ
D1
C1
30 pF
D2
D3
D4
GND
INPUT VE
MONITORING
NODE
2.5 KΩ
S2
Figure 8. Test circuit for tPHZ, tPZH, tPLZ, and tPZL. (single channel product only)
9
Figure 9. Typical enable propagation delay vs. ambient temperature.
(single channel product only)
Figure 10. Propagation delay skew, tPSK, waveform
IF
V
CC = 5.0 V
D.U.T.
B
VCC
0.1 µF*
A
OUTPUT VO
MONITORING
NODE
+
VFF
–
GND
–
+ CL
15 pF
VCM
V
CC = 5.25 V
+
D.U.T.*
PULSE GEN.
IF
ICC
VCC
IO
0.01 μF
+
–
VIN
100 W TYP.
100 W
2.1 V
GND
V
DC = 3.0 V
CONDITIONS: IF = 10 mA
O = 25 mA
I
T
A = +125 °C
* FOR SINGLE CHANNEL UNITS,
GROUND ENABLE PIN.
Figure 11. Test diagram for common mode transient immunity and typical
waveforms
Figure 12. Operating circuit for burn-in and steady state life tests
10
MIL-PRF-38534 Class H, Class K, and DSCC SMD Test Program
Avago Technologies’ Hi-Rel Optocouplers are in compli- the amount of time required for a system’s output to
ance with MIL-PRF-38534 Classes H and K. Class H and change from a Logic 1 to a Logic 0, when given a stimulus
Class K devices are also in compliance with DSCC drawings at the input (see Figure 5).
5962-89570, and 5962-89571.
When t
and t
differ in value, pulse width distortion
PLH
PHL
Testing consists of 100% screening and quality confor- results. Pulse width distortion is defined as |t -t | and
PHL PLH
mance inspection to MIL-PRF-38534.
determines the maximum data rate capability of a dis-
tortion-limited system. Maximum pulse width distortion
on the order of 25-35% is typically used when specifying
the maximum data rate capabilities of systems. The exact
figure depends on the particular application (RS-232,
PCM, T-1, etc.).
Data Rate and Pulse-Width Distortion Definitions
Propagation delay is a figure of merit which describes the
finite amount of time required for a system to translate in-
formation from input to output when shifting logic levels.
Propagation delay from low to high (t ) specifies the
amount of time required for a system’s output to change
from a Logic 0 to a Logic 1, when given a stimulus at the
PLH
These high performance optocouplers offer the advan-
tages of specified propagation delay (t , t ), and pulse
PLH PHL
width distortion (|t -t |) over temperature and power
PLH PHL
input. Propagation delay from high to low (t ) specifies
PHL
supply voltage ranges.
Applications
VCC1 = +5 V
30 pF
HCPL-5400
VCC
226 Ω
274 Ω
V
CC2 = 5 V
DATA
IN
A
0.1 μF
DATA
OUT
Y
TTL
LSTTL
STTL
HCMOS
GND 1
GND
TOTEM
POLE
GND 2
Y = A
1
OUTPUT GATE
2
(e.g. 54AS1000)
Figure 13. Recommended HCPL-5400 interface circuit
VCC1 = +5 V
HCPL-5400
VCC2 = 5 V
464 Ω
VCC
DATA
IN
A
0.1 μF
STTL
DATA
OUT
Y
TTL
LSTTL
STTL
GND 1
GND
OPEN
GND 2
Y = A
1
COLLECTOR
OUTPUT
GATE
2
(e.g. 54S05)
Figure 14. Alternative HCPL-5400 interface circuit
11
30 pF
226 Ω
VCC1 = 5 V
HCPL-5430
VCC
V
CC2 = +5 V
DATA
IN A
TTL
0.1 μF
274 Ω
LSTTL
STTL
DATA
OUT Y
DATA
OUT Y
HCMOS
TOTEM POLE
TTL
LSTTL
STTL
OUTPUT GATE
(e.g. 54AS1000)
HCMOS
274 Ω
DATA
GND
IN A
Y = A
GND 2
GND 1
226 Ω
30 pF
2
1
Figure 15. Recommended HCPL-5430 and HCPL-6430 interface circuit
464 Ω
VCC1 = +5 V
HCPL-5430
VCC
DATA
IN A
V
CC2 = +5 V
TTL
0.1 μF
LSTTL
HCMOS
STTL
DATA
OUT Y
DATA
OUT Y
STTL OPEN COLLECTOR
OUTPUT GATE
(e.g. 54AS05)
DATA
464 Ω
TTL
LSTTL
HCMOS
STTL
GND
IN A
Y = A
GND 2
GND 1
2
1
Figure 16. Alternative HCPL-5430 and HCPL-6430 interface circuit
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries.
Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. Obsoletes 5968-9403E
AV02-3578EN - June 11, 2012
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